diff --git a/Documentation/ABI/testing/configfs-usb-gadget-uvc b/Documentation/ABI/testing/configfs-usb-gadget-uvc index 5d4180aaf18e..809765bd9573 100644 --- a/Documentation/ABI/testing/configfs-usb-gadget-uvc +++ b/Documentation/ABI/testing/configfs-usb-gadget-uvc @@ -265,71 +265,6 @@ Description: Specific uncompressed frame descriptors bmCapabilities - still image support, fixed frame-rate support -What: /config/usb-gadget/gadget/functions/uvc.name/streaming/framebased -Date: Oct 2025 -KernelVersion: 5.4 -Description: Framebased format descriptors - -What: /config/usb-gadget/gadget/functions/uvc.name/streaming/framebased/name -Date: Oct 2025 -KernelVersion: 5.4 -Description: Specific framebased format descriptors - - ================== ======================================= - bFormatIndex unique id for this format descriptor; - only defined after parent header is - linked into the streaming class; - read-only - bmaControls this format's data for bmaControls in - the streaming header - bmInterlaceFlags specifies interlace information, - read-only - bAspectRatioY the X dimension of the picture aspect - ratio, read-only - bAspectRatioX the Y dimension of the picture aspect - ratio, read-only - bDefaultFrameIndex optimum frame index for this stream - bBitsPerPixel number of bits per pixel used to - specify color in the decoded video - frame - guidFormat globally unique id used to identify - stream-encoding format - ================== ======================================= - -What: /config/usb-gadget/gadget/functions/uvc.name/streaming/framebased/name/name -Date: Sept 2024 -KernelVersion: 5.15 -Description: Specific framebased frame descriptors - - ========================= ===================================== - bFrameIndex unique id for this framedescriptor; - only defined after parent format is - linked into the streaming header; - read-only - dwFrameInterval indicates how frame interval can be - programmed; a number of values - separated by newline can be specified - dwDefaultFrameInterval the frame interval the device would - like to use as default - dwBytesPerLine Specifies the number of bytes per line - - of video for packed fixed frame size - formats, allowing the receiver to - perform stride alignment of the video. - If the bVariableSize value (above) is - TRUE (1), or if the format does not - permit such alignment, this value shall - be set to zero (0). - dwMaxBitRate the maximum bit rate at the shortest - frame interval in bps - dwMinBitRate the minimum bit rate at the longest - frame interval in bps - wHeight height of decoded bitmap frame in px - wWidth width of decoded bitmam frame in px - bmCapabilities still image support, fixed frame-rate - support - ========================= ===================================== - What: /config/usb-gadget/gadget/functions/uvc.name/streaming/header Date: Dec 2014 KernelVersion: 4.0 diff --git a/Documentation/ABI/testing/sysfs-fs-fuse b/Documentation/ABI/testing/sysfs-fs-fuse deleted file mode 100644 index b9956842b36f..000000000000 --- a/Documentation/ABI/testing/sysfs-fs-fuse +++ /dev/null @@ -1,19 +0,0 @@ -What: /sys/fs/fuse/features/fuse_bpf -Date: December 2022 -Contact: Paul Lawrence -Description: - Read-only file that contains the word 'supported' if fuse-bpf is - supported, does not exist otherwise - -What: /sys/fs/fuse/bpf_prog_type_fuse -Date: December 2022 -Contact: Paul Lawrence -Description: - bpf_prog_type_fuse defines the program type of bpf programs that - may be passed to fuse-bpf. For upstream bpf program types, this - is a constant defined in a contiguous array of constants. - bpf_prog_type_fuse is appended to the end of the list, so it may - change and therefore its value must be read from this file. - - Contents is ASCII decimal representation of bpf_prog_type_fuse - diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index c33eb805ec85..25443c227e27 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3187,21 +3187,6 @@ in certain environments such as networked servers or real-time systems. - no_hash_pointers - Force pointers printed to the console or buffers to be - unhashed. By default, when a pointer is printed via %p - format string, that pointer is "hashed", i.e. obscured - by hashing the pointer value. This is a security feature - that hides actual kernel addresses from unprivileged - users, but it also makes debugging the kernel more - difficult since unequal pointers can no longer be - compared. However, if this command-line option is - specified, then all normal pointers will have their true - value printed. Pointers printed via %pK may still be - hashed. This option should only be specified when - debugging the kernel. Please do not use on production - kernels. - nohibernate [HIBERNATION] Disable hibernation and resume. nohz= [KNL] Boottime enable/disable dynamic ticks diff --git a/Documentation/dev-tools/index.rst b/Documentation/dev-tools/index.rst index cdabec1e168c..b0522a4dd107 100644 --- a/Documentation/dev-tools/index.rst +++ b/Documentation/dev-tools/index.rst @@ -21,7 +21,6 @@ whole; patches welcome! kasan ubsan kmemleak - kfence gdb-kernel-debugging kgdb kselftest diff --git a/Documentation/dev-tools/kfence.rst b/Documentation/dev-tools/kfence.rst deleted file mode 100644 index fdf04e741ea5..000000000000 --- a/Documentation/dev-tools/kfence.rst +++ /dev/null @@ -1,298 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 -.. Copyright (C) 2020, Google LLC. - -Kernel Electric-Fence (KFENCE) -============================== - -Kernel Electric-Fence (KFENCE) is a low-overhead sampling-based memory safety -error detector. KFENCE detects heap out-of-bounds access, use-after-free, and -invalid-free errors. - -KFENCE is designed to be enabled in production kernels, and has near zero -performance overhead. Compared to KASAN, KFENCE trades performance for -precision. The main motivation behind KFENCE's design, is that with enough -total uptime KFENCE will detect bugs in code paths not typically exercised by -non-production test workloads. One way to quickly achieve a large enough total -uptime is when the tool is deployed across a large fleet of machines. - -Usage ------ - -To enable KFENCE, configure the kernel with:: - - CONFIG_KFENCE=y - -To build a kernel with KFENCE support, but disabled by default (to enable, set -``kfence.sample_interval`` to non-zero value), configure the kernel with:: - - CONFIG_KFENCE=y - CONFIG_KFENCE_SAMPLE_INTERVAL=0 - -KFENCE provides several other configuration options to customize behaviour (see -the respective help text in ``lib/Kconfig.kfence`` for more info). - -Tuning performance -~~~~~~~~~~~~~~~~~~ - -The most important parameter is KFENCE's sample interval, which can be set via -the kernel boot parameter ``kfence.sample_interval`` in milliseconds. The -sample interval determines the frequency with which heap allocations will be -guarded by KFENCE. The default is configurable via the Kconfig option -``CONFIG_KFENCE_SAMPLE_INTERVAL``. Setting ``kfence.sample_interval=0`` -disables KFENCE. - -The KFENCE memory pool is of fixed size, and if the pool is exhausted, no -further KFENCE allocations occur. With ``CONFIG_KFENCE_NUM_OBJECTS`` (default -255), the number of available guarded objects can be controlled. Each object -requires 2 pages, one for the object itself and the other one used as a guard -page; object pages are interleaved with guard pages, and every object page is -therefore surrounded by two guard pages. - -The total memory dedicated to the KFENCE memory pool can be computed as:: - - ( #objects + 1 ) * 2 * PAGE_SIZE - -Using the default config, and assuming a page size of 4 KiB, results in -dedicating 2 MiB to the KFENCE memory pool. - -Note: On architectures that support huge pages, KFENCE will ensure that the -pool is using pages of size ``PAGE_SIZE``. This will result in additional page -tables being allocated. - -Error reports -~~~~~~~~~~~~~ - -A typical out-of-bounds access looks like this:: - - ================================================================== - BUG: KFENCE: out-of-bounds read in test_out_of_bounds_read+0xa3/0x22b - - Out-of-bounds read at 0xffffffffb672efff (1B left of kfence-#17): - test_out_of_bounds_read+0xa3/0x22b - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - kfence-#17 [0xffffffffb672f000-0xffffffffb672f01f, size=32, cache=kmalloc-32] allocated by task 507: - test_alloc+0xf3/0x25b - test_out_of_bounds_read+0x98/0x22b - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - CPU: 4 PID: 107 Comm: kunit_try_catch Not tainted 5.8.0-rc6+ #7 - Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.13.0-1 04/01/2014 - ================================================================== - -The header of the report provides a short summary of the function involved in -the access. It is followed by more detailed information about the access and -its origin. Note that, real kernel addresses are only shown when using the -kernel command line option ``no_hash_pointers``. - -Use-after-free accesses are reported as:: - - ================================================================== - BUG: KFENCE: use-after-free read in test_use_after_free_read+0xb3/0x143 - - Use-after-free read at 0xffffffffb673dfe0 (in kfence-#24): - test_use_after_free_read+0xb3/0x143 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - kfence-#24 [0xffffffffb673dfe0-0xffffffffb673dfff, size=32, cache=kmalloc-32] allocated by task 507: - test_alloc+0xf3/0x25b - test_use_after_free_read+0x76/0x143 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - freed by task 507: - test_use_after_free_read+0xa8/0x143 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - CPU: 4 PID: 109 Comm: kunit_try_catch Tainted: G W 5.8.0-rc6+ #7 - Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.13.0-1 04/01/2014 - ================================================================== - -KFENCE also reports on invalid frees, such as double-frees:: - - ================================================================== - BUG: KFENCE: invalid free in test_double_free+0xdc/0x171 - - Invalid free of 0xffffffffb6741000: - test_double_free+0xdc/0x171 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - kfence-#26 [0xffffffffb6741000-0xffffffffb674101f, size=32, cache=kmalloc-32] allocated by task 507: - test_alloc+0xf3/0x25b - test_double_free+0x76/0x171 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - freed by task 507: - test_double_free+0xa8/0x171 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - CPU: 4 PID: 111 Comm: kunit_try_catch Tainted: G W 5.8.0-rc6+ #7 - Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.13.0-1 04/01/2014 - ================================================================== - -KFENCE also uses pattern-based redzones on the other side of an object's guard -page, to detect out-of-bounds writes on the unprotected side of the object. -These are reported on frees:: - - ================================================================== - BUG: KFENCE: memory corruption in test_kmalloc_aligned_oob_write+0xef/0x184 - - Corrupted memory at 0xffffffffb6797ff9 [ 0xac . . . . . . ] (in kfence-#69): - test_kmalloc_aligned_oob_write+0xef/0x184 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - kfence-#69 [0xffffffffb6797fb0-0xffffffffb6797ff8, size=73, cache=kmalloc-96] allocated by task 507: - test_alloc+0xf3/0x25b - test_kmalloc_aligned_oob_write+0x57/0x184 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - CPU: 4 PID: 120 Comm: kunit_try_catch Tainted: G W 5.8.0-rc6+ #7 - Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.13.0-1 04/01/2014 - ================================================================== - -For such errors, the address where the corruption occurred as well as the -invalidly written bytes (offset from the address) are shown; in this -representation, '.' denote untouched bytes. In the example above ``0xac`` is -the value written to the invalid address at offset 0, and the remaining '.' -denote that no following bytes have been touched. Note that, real values are -only shown if the kernel was booted with ``no_hash_pointers``; to avoid -information disclosure otherwise, '!' is used instead to denote invalidly -written bytes. - -And finally, KFENCE may also report on invalid accesses to any protected page -where it was not possible to determine an associated object, e.g. if adjacent -object pages had not yet been allocated:: - - ================================================================== - BUG: KFENCE: invalid read in test_invalid_access+0x26/0xe0 - - Invalid read at 0xffffffffb670b00a: - test_invalid_access+0x26/0xe0 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - CPU: 4 PID: 124 Comm: kunit_try_catch Tainted: G W 5.8.0-rc6+ #7 - Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.13.0-1 04/01/2014 - ================================================================== - -DebugFS interface -~~~~~~~~~~~~~~~~~ - -Some debugging information is exposed via debugfs: - -* The file ``/sys/kernel/debug/kfence/stats`` provides runtime statistics. - -* The file ``/sys/kernel/debug/kfence/objects`` provides a list of objects - allocated via KFENCE, including those already freed but protected. - -Implementation Details ----------------------- - -Guarded allocations are set up based on the sample interval. After expiration -of the sample interval, the next allocation through the main allocator (SLAB or -SLUB) returns a guarded allocation from the KFENCE object pool (allocation -sizes up to PAGE_SIZE are supported). At this point, the timer is reset, and -the next allocation is set up after the expiration of the interval. To "gate" a -KFENCE allocation through the main allocator's fast-path without overhead, -KFENCE relies on static branches via the static keys infrastructure. The static -branch is toggled to redirect the allocation to KFENCE. - -KFENCE objects each reside on a dedicated page, at either the left or right -page boundaries selected at random. The pages to the left and right of the -object page are "guard pages", whose attributes are changed to a protected -state, and cause page faults on any attempted access. Such page faults are then -intercepted by KFENCE, which handles the fault gracefully by reporting an -out-of-bounds access, and marking the page as accessible so that the faulting -code can (wrongly) continue executing (set ``panic_on_warn`` to panic instead). - -To detect out-of-bounds writes to memory within the object's page itself, -KFENCE also uses pattern-based redzones. For each object page, a redzone is set -up for all non-object memory. For typical alignments, the redzone is only -required on the unguarded side of an object. Because KFENCE must honor the -cache's requested alignment, special alignments may result in unprotected gaps -on either side of an object, all of which are redzoned. - -The following figure illustrates the page layout:: - - ---+-----------+-----------+-----------+-----------+-----------+--- - | xxxxxxxxx | O : | xxxxxxxxx | : O | xxxxxxxxx | - | xxxxxxxxx | B : | xxxxxxxxx | : B | xxxxxxxxx | - | x GUARD x | J : RED- | x GUARD x | RED- : J | x GUARD x | - | xxxxxxxxx | E : ZONE | xxxxxxxxx | ZONE : E | xxxxxxxxx | - | xxxxxxxxx | C : | xxxxxxxxx | : C | xxxxxxxxx | - | xxxxxxxxx | T : | xxxxxxxxx | : T | xxxxxxxxx | - ---+-----------+-----------+-----------+-----------+-----------+--- - -Upon deallocation of a KFENCE object, the object's page is again protected and -the object is marked as freed. Any further access to the object causes a fault -and KFENCE reports a use-after-free access. Freed objects are inserted at the -tail of KFENCE's freelist, so that the least recently freed objects are reused -first, and the chances of detecting use-after-frees of recently freed objects -is increased. - -Interface ---------- - -The following describes the functions which are used by allocators as well as -page handling code to set up and deal with KFENCE allocations. - -.. kernel-doc:: include/linux/kfence.h - :functions: is_kfence_address - kfence_shutdown_cache - kfence_alloc kfence_free __kfence_free - kfence_ksize kfence_object_start - kfence_handle_page_fault - -Related Tools -------------- - -In userspace, a similar approach is taken by `GWP-ASan -`_. GWP-ASan also relies on guard pages and -a sampling strategy to detect memory unsafety bugs at scale. KFENCE's design is -directly influenced by GWP-ASan, and can be seen as its kernel sibling. Another -similar but non-sampling approach, that also inspired the name "KFENCE", can be -found in the userspace `Electric Fence Malloc Debugger -`_. - -In the kernel, several tools exist to debug memory access errors, and in -particular KASAN can detect all bug classes that KFENCE can detect. While KASAN -is more precise, relying on compiler instrumentation, this comes at a -performance cost. - -It is worth highlighting that KASAN and KFENCE are complementary, with -different target environments. For instance, KASAN is the better debugging-aid, -where test cases or reproducers exists: due to the lower chance to detect the -error, it would require more effort using KFENCE to debug. Deployments at scale -that cannot afford to enable KASAN, however, would benefit from using KFENCE to -discover bugs due to code paths not exercised by test cases or fuzzers. diff --git a/Documentation/filesystems/fuse.txt b/Documentation/filesystems/fuse.txt index d32457766947..13af4a49e7db 100644 --- a/Documentation/filesystems/fuse.txt +++ b/Documentation/filesystems/fuse.txt @@ -46,8 +46,10 @@ non-privileged mounts. This opens up new possibilities for the use of filesystems. A good example is sshfs: a secure network filesystem using the sftp protocol. -The userspace library and utilities are available from the -`FUSE homepage: `_ +The userspace library and utilities are available from the FUSE +homepage: + + http://fuse.sourceforge.net/ Filesystem type ~~~~~~~~~~~~~~~ diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt index 8acb7244b2e6..6882bfd2c097 100644 --- a/Documentation/filesystems/proc.txt +++ b/Documentation/filesystems/proc.txt @@ -1823,20 +1823,18 @@ if precise results are needed. 3.8 /proc//fdinfo/ - Information about opened file --------------------------------------------------------------- This file provides information associated with an opened file. The regular -files have at least four fields -- 'pos', 'flags', 'mnt_id' and 'ino'. -The 'pos' represents the current offset of the opened file in decimal -form [see lseek(2) for details], 'flags' denotes the octal O_xxx mask the -file has been created with [see open(2) for details] and 'mnt_id' represents -mount ID of the file system containing the opened file [see 3.5 -/proc//mountinfo for details]. 'ino' represents the inode number of -the file. +files have at least three fields -- 'pos', 'flags' and mnt_id. The 'pos' +represents the current offset of the opened file in decimal form [see lseek(2) +for details], 'flags' denotes the octal O_xxx mask the file has been +created with [see open(2) for details] and 'mnt_id' represents mount ID of +the file system containing the opened file [see 3.5 /proc//mountinfo +for details]. A typical output is pos: 0 flags: 0100002 mnt_id: 19 - ino: 63107 All locks associated with a file descriptor are shown in its fdinfo too. @@ -1850,7 +1848,6 @@ pair provide additional information particular to the objects they represent. pos: 0 flags: 04002 mnt_id: 9 - ino: 63107 eventfd-count: 5a where 'eventfd-count' is hex value of a counter. @@ -1860,7 +1857,6 @@ pair provide additional information particular to the objects they represent. pos: 0 flags: 04002 mnt_id: 9 - ino: 63107 sigmask: 0000000000000200 where 'sigmask' is hex value of the signal mask associated @@ -1871,7 +1867,6 @@ pair provide additional information particular to the objects they represent. pos: 0 flags: 02 mnt_id: 9 - ino: 63107 tfd: 5 events: 1d data: ffffffffffffffff pos:0 ino:61af sdev:7 where 'tfd' is a target file descriptor number in decimal form, @@ -1888,8 +1883,6 @@ pair provide additional information particular to the objects they represent. pos: 0 flags: 02000000 - mnt_id: 9 - ino: 63107 inotify wd:3 ino:9e7e sdev:800013 mask:800afce ignored_mask:0 fhandle-bytes:8 fhandle-type:1 f_handle:7e9e0000640d1b6d where 'wd' is a watch descriptor in decimal form, ie a target file @@ -1912,7 +1905,6 @@ pair provide additional information particular to the objects they represent. pos: 0 flags: 02 mnt_id: 9 - ino: 63107 fanotify flags:10 event-flags:0 fanotify mnt_id:12 mflags:40 mask:38 ignored_mask:40000003 fanotify ino:4f969 sdev:800013 mflags:0 mask:3b ignored_mask:40000000 fhandle-bytes:8 fhandle-type:1 f_handle:69f90400c275b5b4 @@ -1935,7 +1927,6 @@ pair provide additional information particular to the objects they represent. pos: 0 flags: 02 mnt_id: 9 - ino: 63107 clockid: 0 ticks: 0 settime flags: 01 @@ -1950,22 +1941,6 @@ pair provide additional information particular to the objects they represent. with TIMER_ABSTIME option which will be shown in 'settime flags', but 'it_value' still exhibits timer's remaining time. -DMA Buffer files -~~~~~~~~~~~~~~~~ - -:: - - pos: 0 - flags: 04002 - mnt_id: 9 - ino: 63107 - size: 32768 - count: 2 - exp_name: system-heap - -where 'size' is the size of the DMA buffer in bytes. 'count' is the file count of -the DMA buffer file. 'exp_name' is the name of the DMA buffer exporter. - 3.9 /proc//map_files - Information about memory mapped files --------------------------------------------------------------------- This directory contains symbolic links which represent memory mapped files diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt index 11ad3403bdda..12cf648120f4 100644 --- a/Documentation/networking/ip-sysctl.txt +++ b/Documentation/networking/ip-sysctl.txt @@ -1660,14 +1660,6 @@ accept_ra_min_hop_limit - INTEGER Default: 1 -accept_ra_min_lft - INTEGER - Minimum acceptable lifetime value in Router Advertisement. - - RA sections with a lifetime less than this value shall be - ignored. Zero lifetimes stay unaffected. - - Default: 0 - accept_ra_pinfo - BOOLEAN Learn Prefix Information in Router Advertisement. diff --git a/MAINTAINERS b/MAINTAINERS index 3cf5cc8042c4..a5c7c0cb7ff2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6742,8 +6742,7 @@ F: drivers/platform/x86/fujitsu-tablet.c FUSE: FILESYSTEM IN USERSPACE M: Miklos Szeredi L: linux-fsdevel@vger.kernel.org -S: Maintained -W: https://github.com/libfuse/ +W: http://fuse.sourceforge.net/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/fuse.git S: Maintained F: fs/fuse/ @@ -9141,7 +9140,6 @@ F: include/linux/skmsg.h F: net/core/skmsg.c F: net/core/sock_map.c F: net/ipv4/tcp_bpf.c -F: net/ipv4/udp_bpf.c LANTIQ / INTEL Ethernet drivers M: Hauke Mehrtens @@ -12851,7 +12849,6 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/brauner/linux.git F: samples/pidfd/ F: tools/testing/selftests/pidfd/ -F: tools/testing/selftests/clone3/ K: (?i)pidfd K: (?i)clone3 K: \b(clone_args|kernel_clone_args)\b diff --git a/Makefile b/Makefile index 8fad00d03e52..4593e9d0cdde 100644 --- a/Makefile +++ b/Makefile @@ -596,11 +596,9 @@ CLANG_FLAGS += --target=$(notdir $(CROSS_COMPILE:%-=%)) endif # CROSS_COMPILE ifeq ($(LLVM_IAS),0) -CLANG_FLAGS += -fno-integrated-as +CLANG_FLAGS += -no-integrated-as GCC_TOOLCHAIN_DIR := $(dir $(shell which $(CROSS_COMPILE)elfedit)) CLANG_FLAGS += --prefix=$(GCC_TOOLCHAIN_DIR)$(notdir $(CROSS_COMPILE)) -else -CLANG_FLAGS += -fintegrated-as endif CLANG_FLAGS += -Werror=unknown-warning-option KBUILD_CPPFLAGS += $(CLANG_FLAGS) @@ -873,8 +871,7 @@ DEBUG_CFLAGS += -gsplit-dwarf else DEBUG_CFLAGS += -g endif - -ifdef CONFIG_AS_IS_LLVM +ifeq ($(LLVM_IAS),1) KBUILD_AFLAGS += -g else KBUILD_AFLAGS += -Wa,-gdwarf-2 @@ -947,6 +944,7 @@ endif ifdef CONFIG_LTO_CLANG ifdef CONFIG_THINLTO CC_FLAGS_LTO_CLANG := -flto=thin $(call cc-option, -fsplit-lto-unit) +KBUILD_LDFLAGS += --thinlto-cache-dir=.thinlto-cache else CC_FLAGS_LTO_CLANG := -flto endif @@ -963,8 +961,7 @@ endif ifdef CONFIG_LTO CC_FLAGS_LTO := $(CC_FLAGS_LTO_CLANG) -KBUILD_CFLAGS += -fno-lto $(CC_FLAGS_LTO) -KBUILD_AFLAGS += -fno-lto +KBUILD_CFLAGS += $(CC_FLAGS_LTO) export CC_FLAGS_LTO endif @@ -1017,6 +1014,15 @@ KBUILD_CFLAGS += $(call cc-disable-warning, maybe-uninitialized) # disable invalid "can't wrap" optimizations for signed / pointers KBUILD_CFLAGS += $(call cc-option,-fno-strict-overflow) +# clang sets -fmerge-all-constants by default as optimization, but this +# is non-conforming behavior for C and in fact breaks the kernel, so we +# need to disable it here generally. +KBUILD_CFLAGS += $(call cc-option,-fno-merge-all-constants) + +# for gcc -fno-merge-all-constants disables everything, but it is fine +# to have actual conforming behavior enabled. +KBUILD_CFLAGS += $(call cc-option,-fmerge-constants) + # Make sure -fstack-check isn't enabled (like gentoo apparently did) KBUILD_CFLAGS += $(call cc-option,-fno-stack-check,) @@ -1058,8 +1064,7 @@ LDFLAGS_vmlinux += $(call ld-option, -X,) endif ifeq ($(CONFIG_RELR),y) -# ld.lld before 15 did not support -z pack-relative-relocs. -LDFLAGS_vmlinux += $(call ld-option,--pack-dyn-relocs=relr,-z pack-relative-relocs) +LDFLAGS_vmlinux += --pack-dyn-relocs=relr --use-android-relr-tags endif # userspace programs are linked via the compiler, use the correct linker diff --git a/android/GKI_VERSION b/android/GKI_VERSION index eaa5b79f5d73..6e522a6fd53c 100644 --- a/android/GKI_VERSION +++ b/android/GKI_VERSION @@ -1 +1 @@ -LTS_5.4.302_91d385eb2a41 +LTS_5.4.289_4c8fb3275889 diff --git a/arch/alpha/include/uapi/asm/socket.h b/arch/alpha/include/uapi/asm/socket.h index d033d3f92d6d..de6c4df61082 100644 --- a/arch/alpha/include/uapi/asm/socket.h +++ b/arch/alpha/include/uapi/asm/socket.h @@ -124,8 +124,6 @@ #define SO_DETACH_REUSEPORT_BPF 68 -#define SO_NETNS_COOKIE 71 - #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 diff --git a/arch/arm/configs/vendor/sdxlemur.config b/arch/arm/configs/vendor/sdxlemur.config index 0d6a262c17ea..2d12580404e8 100644 --- a/arch/arm/configs/vendor/sdxlemur.config +++ b/arch/arm/configs/vendor/sdxlemur.config @@ -51,10 +51,6 @@ CONFIG_CNSS_ASYNC=y CONFIG_CNSS_QCA6490=y CONFIG_CNSS_UTILS=y # CONFIG_CNSS_GENL is not set -CONFIG_CNSS=m -CONFIG_CNSS_CRYPTO=y -CONFIG_CNSS_PCI=y -CONFIG_CNSS_LOGGER=m CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild index 580ed13b70a7..68ca86f85eb7 100644 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -15,6 +15,7 @@ generic-y += mmiowb.h generic-y += msi.h generic-y += parport.h generic-y += preempt.h +generic-y += seccomp.h generic-y += serial.h generic-y += trace_clock.h diff --git a/arch/arm/include/asm/seccomp.h b/arch/arm/include/asm/seccomp.h deleted file mode 100644 index e9ad0f37d2ba..000000000000 --- a/arch/arm/include/asm/seccomp.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _ASM_SECCOMP_H -#define _ASM_SECCOMP_H - -#include - -#define SECCOMP_ARCH_NATIVE AUDIT_ARCH_ARM -#define SECCOMP_ARCH_NATIVE_NR NR_syscalls -#define SECCOMP_ARCH_NATIVE_NAME "arm" - -#endif /* _ASM_SECCOMP_H */ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 79f9288483f8..206e355cfa09 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -129,7 +129,6 @@ config ARM64 select HAVE_ARCH_JUMP_LABEL_RELATIVE select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN - select HAVE_ARCH_KFENCE select HAVE_ARCH_KGDB select HAVE_ARCH_MMAP_RND_BITS select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT diff --git a/arch/arm64/boot/dts/vendor/qcom/blair-corfur-common-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/blair-corfur-common-overlay.dtsi index cfb1e952d730..6fb4921566ab 100644 --- a/arch/arm64/boot/dts/vendor/qcom/blair-corfur-common-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/blair-corfur-common-overlay.dtsi @@ -187,7 +187,7 @@ label = "google_key"; gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; linux,input-type = <1>; - linux,code = ; + linux,code = ; gpio-key,wakeup; debounce-interval = <15>; linux,can-disable; diff --git a/arch/arm64/boot/dts/vendor/qcom/blair-cypfr-common-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/blair-cypfr-common-overlay.dtsi index ab2183f6ca94..3e89b8cf3d34 100644 --- a/arch/arm64/boot/dts/vendor/qcom/blair-cypfr-common-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/blair-cypfr-common-overlay.dtsi @@ -628,7 +628,7 @@ label = "google_key"; gpios = <&tlmm 60 GPIO_ACTIVE_LOW>; linux,input-type = <1>; - linux,code = ; + linux,code = ; gpio-key,wakeup; debounce-interval = <15>; linux,can-disable; diff --git a/arch/arm64/boot/dts/vendor/qcom/holi-cypfg-common-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/holi-cypfg-common-overlay.dtsi index 23137456e0ce..87a94a1759d8 100644 --- a/arch/arm64/boot/dts/vendor/qcom/holi-cypfg-common-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/holi-cypfg-common-overlay.dtsi @@ -152,7 +152,7 @@ label = "google_key"; gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; linux,input-type = <1>; - linux,code = ; + linux,code = ; gpio-key,wakeup; debounce-interval = <15>; linux,can-disable; diff --git a/arch/arm64/boot/dts/vendor/qcom/holi-cypfq-common-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/holi-cypfq-common-overlay.dtsi index bf340b75a419..86055b0cbda9 100644 --- a/arch/arm64/boot/dts/vendor/qcom/holi-cypfq-common-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/holi-cypfq-common-overlay.dtsi @@ -340,7 +340,7 @@ label = "google_key"; gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; linux,input-type = <1>; - linux,code = ; + linux,code = ; gpio-key,wakeup; debounce-interval = <15>; linux,can-disable; diff --git a/arch/arm64/boot/dts/vendor/qcom/holi-ibiza-common-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/holi-ibiza-common-overlay.dtsi index 30d1a5ca4100..e8d6e24d0018 100644 --- a/arch/arm64/boot/dts/vendor/qcom/holi-ibiza-common-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/holi-ibiza-common-overlay.dtsi @@ -135,7 +135,7 @@ label = "google_key"; gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; linux,input-type = <1>; - linux,code = ; + linux,code = ; gpio-key,wakeup; debounce-interval = <15>; linux,can-disable; diff --git a/arch/arm64/configs/gki_defconfig b/arch/arm64/configs/gki_defconfig index 64beb2922cf9..59ddabbd31fc 100644 --- a/arch/arm64/configs/gki_defconfig +++ b/arch/arm64/configs/gki_defconfig @@ -209,27 +209,14 @@ CONFIG_L2TP=y CONFIG_BRIDGE=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_HTB=y -CONFIG_NET_SCH_PRIO=y -CONFIG_NET_SCH_MULTIQ=y -CONFIG_NET_SCH_TBF=y -CONFIG_NET_SCH_NETEM=y CONFIG_NET_SCH_INGRESS=y CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y CONFIG_NET_CLS_BPF=y CONFIG_NET_CLS_MATCHALL=y CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y -CONFIG_NET_ACT_GACT=y -CONFIG_NET_ACT_MIRRED=y -CONFIG_NET_ACT_SKBEDIT=y CONFIG_NET_ACT_BPF=y CONFIG_BPF_JIT=y CONFIG_BT=y @@ -513,7 +500,6 @@ CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y CONFIG_QUOTA=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y -CONFIG_FUSE_BPF=y CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y @@ -603,9 +589,6 @@ CONFIG_DEBUG_INFO_DWARF4=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_KFENCE=y -CONFIG_KFENCE_SAMPLE_INTERVAL=500 -CONFIG_KFENCE_NUM_OBJECTS=63 CONFIG_SOFTLOCKUP_DETECTOR=y # CONFIG_DETECT_HUNG_TASK is not set CONFIG_PANIC_ON_OOPS=y diff --git a/arch/arm64/configs/vendor/ext_config/moto-holi-ibiza.config b/arch/arm64/configs/vendor/ext_config/moto-holi-ibiza.config index 4804e99b9e0c..dc13da133a82 100644 --- a/arch/arm64/configs/vendor/ext_config/moto-holi-ibiza.config +++ b/arch/arm64/configs/vendor/ext_config/moto-holi-ibiza.config @@ -17,49 +17,9 @@ CONFIG_IBIZA_DTB=y # Camera CONFIG_CAM_SENSOR_PROBE_RETRY=y -CONFIG_CAMERA_CCI_INTF=m -# CONFIG_CAMERA_CCI_MASTER_CHANGE is not set -CONFIG_REGULATOR_WL2864C=m # Charger -CONFIG_MMI_SMBCHARGER_IIO=m CONFIG_QG_LEGACY=y -CONFIG_QPNP_ADAPTIVE_CHARGE=m - -# Fingerprint -CONFIG_INPUT_CHIPONE_FPS_MMI=m -CONFIG_INPUT_MISC_FPC1020=m -CONFIG_INPUT_MISC_FPC1020_SAVE_TO_CLASS_DEVICE=y - -# MMI -CONFIG_MMI_ANNOTATE=m -CONFIG_MMI_INFO=m -CONFIG_MMI_RELAY=m -CONFIG_MMI_SYS_TEMP=m -CONFIG_MOTO_UTAGS=m -CONFIG_SENSORS_CLASS=m - -# NFC -CONFIG_NFC_QTI_I2C=m - -# SAR -CONFIG_SARSENSOR_SX937X=m - -# Touchscreen -CONFIG_TOUCHSCREEN_NT36xxx_HOSTDL_SPI_MMI=m -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_ENABLE_DOUBLE_TAP=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_NOTIFY_TOUCH_STATE=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_LAST_TIME=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_STOWED_MODE_EN=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_CHIP_VER_1=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_WAKEUP_GESTURE_CTRL=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_STYLUS_PALM=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_STYLUS_PALM_RANGE=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_DDA_STYLUS=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_PEN_NOTIFIER=y -CONFIG_TOUCHSCREEN_CHIPONE_TDDI=m -CONFIG_TOUCHSCREEN_CHIPONE_TDDI_ESD=y -CONFIG_BOARD_USES_DOUBLE_TAP_CTRL=y # UFS # CONFIG_UFSFEATURE is not set diff --git a/arch/arm64/configs/vendor/holi-qgki_defconfig b/arch/arm64/configs/vendor/holi-qgki_defconfig index f9282a24cc5d..cecdf8f0cb64 100644 --- a/arch/arm64/configs/vendor/holi-qgki_defconfig +++ b/arch/arm64/configs/vendor/holi-qgki_defconfig @@ -239,27 +239,15 @@ CONFIG_BRIDGE=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_HTB=y CONFIG_NET_SCH_PRIO=y -CONFIG_NET_SCH_MULTIQ=y -CONFIG_NET_SCH_TBF=y -CONFIG_NET_SCH_NETEM=y CONFIG_NET_SCH_INGRESS=y CONFIG_NET_CLS_FW=y CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y CONFIG_NET_CLS_BPF=y CONFIG_NET_CLS_MATCHALL=y CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y -CONFIG_NET_ACT_GACT=y -CONFIG_NET_ACT_MIRRED=y -CONFIG_NET_ACT_SKBEDIT=y CONFIG_NET_ACT_BPF=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y @@ -782,7 +770,6 @@ CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y CONFIG_QUOTA=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y -CONFIG_FUSE_BPF=y CONFIG_OVERLAY_FS=y CONFIG_INCREMENTAL_FS=y CONFIG_MSDOS_FS=y @@ -878,9 +865,6 @@ CONFIG_HEADERS_INSTALL=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_KFENCE=y -CONFIG_KFENCE_SAMPLE_INTERVAL=500 -CONFIG_KFENCE_NUM_OBJECTS=63 CONFIG_SOFTLOCKUP_DETECTOR=y # CONFIG_DETECT_HUNG_TASK is not set CONFIG_PANIC_ON_OOPS=y diff --git a/arch/arm64/include/asm/kfence.h b/arch/arm64/include/asm/kfence.h deleted file mode 100644 index d061176d57ea..000000000000 --- a/arch/arm64/include/asm/kfence.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arm64 KFENCE support. - * - * Copyright (C) 2020, Google LLC. - */ - -#ifndef __ASM_KFENCE_H -#define __ASM_KFENCE_H - -#include - -static inline bool arch_kfence_init_pool(void) { return true; } - -static inline bool kfence_protect_page(unsigned long addr, bool protect) -{ - set_memory_valid(addr, 1, !protect); - - return true; -} - -#endif /* __ASM_KFENCE_H */ diff --git a/arch/arm64/include/asm/seccomp.h b/arch/arm64/include/asm/seccomp.h index 30256233788b..c36387170936 100644 --- a/arch/arm64/include/asm/seccomp.h +++ b/arch/arm64/include/asm/seccomp.h @@ -19,13 +19,4 @@ #include -#define SECCOMP_ARCH_NATIVE AUDIT_ARCH_AARCH64 -#define SECCOMP_ARCH_NATIVE_NR NR_syscalls -#define SECCOMP_ARCH_NATIVE_NAME "aarch64" -#ifdef CONFIG_COMPAT -# define SECCOMP_ARCH_COMPAT AUDIT_ARCH_ARM -# define SECCOMP_ARCH_COMPAT_NR __NR_compat_syscalls -# define SECCOMP_ARCH_COMPAT_NAME "arm" -#endif - #endif /* _ASM_SECCOMP_H */ diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index ae412b438122..8fcd1dbe1fb7 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -328,9 +327,6 @@ static void __do_kernel_fault(unsigned long addr, unsigned int esr, } else if (addr < PAGE_SIZE) { msg = "NULL pointer dereference"; } else { - if (kfence_handle_page_fault(addr, esr & ESR_ELx_WNR, regs)) - return; - msg = "paging request"; } diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index b6983b5502bc..9eaaa69fea9a 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -471,8 +471,7 @@ static void __init map_mem(pgd_t *pgdp) struct memblock_region *reg; int flags = 0; - if (rodata_full || debug_pagealloc_enabled() || - IS_ENABLED(CONFIG_KFENCE)) + if (rodata_full || debug_pagealloc_enabled()) flags = NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; /* @@ -1471,12 +1470,7 @@ int arch_add_memory(int nid, u64 start, u64 size, return -1; } - /* - * KFENCE requires linear map to be mapped at page granularity, so that - * it is possible to protect/unprotect single pages in the KFENCE pool. - */ - if (rodata_full || debug_pagealloc_enabled() || - IS_ENABLED(CONFIG_KFENCE)) + if (rodata_full || debug_pagealloc_enabled()) flags = NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; __create_pgd_mapping(swapper_pg_dir, start, __phys_to_virt(start), diff --git a/arch/csky/include/asm/seccomp.h b/arch/csky/include/asm/seccomp.h deleted file mode 100644 index d33e758126fb..000000000000 --- a/arch/csky/include/asm/seccomp.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _ASM_SECCOMP_H -#define _ASM_SECCOMP_H - -#include - -#define SECCOMP_ARCH_NATIVE AUDIT_ARCH_CSKY -#define SECCOMP_ARCH_NATIVE_NR NR_syscalls -#define SECCOMP_ARCH_NATIVE_NAME "csky" - -#endif /* _ASM_SECCOMP_H */ diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h index aa809589a181..e383d7e27b93 100644 --- a/arch/mips/include/asm/seccomp.h +++ b/arch/mips/include/asm/seccomp.h @@ -9,12 +9,12 @@ static inline const int *get_compat_mode1_syscalls(void) static const int syscalls_O32[] = { __NR_O32_Linux + 3, __NR_O32_Linux + 4, __NR_O32_Linux + 1, __NR_O32_Linux + 193, - -1, /* negative terminated */ + 0, /* null terminated */ }; static const int syscalls_N32[] = { __NR_N32_Linux + 0, __NR_N32_Linux + 1, __NR_N32_Linux + 58, __NR_N32_Linux + 211, - -1, /* negative terminated */ + 0, /* null terminated */ }; if (IS_ENABLED(CONFIG_MIPS32_O32) && test_thread_flag(TIF_32BIT_REGS)) diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h index ff3ab771e769..d0a9ed2ca2d6 100644 --- a/arch/mips/include/uapi/asm/socket.h +++ b/arch/mips/include/uapi/asm/socket.h @@ -135,8 +135,6 @@ #define SO_DETACH_REUSEPORT_BPF 68 -#define SO_NETNS_COOKIE 71 - #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 diff --git a/arch/parisc/include/asm/Kbuild b/arch/parisc/include/asm/Kbuild index ae63364de2cf..9ceedf6393c4 100644 --- a/arch/parisc/include/asm/Kbuild +++ b/arch/parisc/include/asm/Kbuild @@ -19,6 +19,7 @@ generic-y += mm-arch-hooks.h generic-y += mmiowb.h generic-y += percpu.h generic-y += preempt.h +generic-y += seccomp.h generic-y += trace_clock.h generic-y += user.h generic-y += vga.h diff --git a/arch/parisc/include/asm/seccomp.h b/arch/parisc/include/asm/seccomp.h deleted file mode 100644 index b058b2220322..000000000000 --- a/arch/parisc/include/asm/seccomp.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _ASM_SECCOMP_H -#define _ASM_SECCOMP_H - -#include - -#ifdef CONFIG_64BIT -# define SECCOMP_ARCH_NATIVE AUDIT_ARCH_PARISC64 -# define SECCOMP_ARCH_NATIVE_NR NR_syscalls -# define SECCOMP_ARCH_NATIVE_NAME "parisc64" -# ifdef CONFIG_COMPAT -# define SECCOMP_ARCH_COMPAT AUDIT_ARCH_PARISC -# define SECCOMP_ARCH_COMPAT_NR NR_syscalls -# define SECCOMP_ARCH_COMPAT_NAME "parisc" -# endif -#else /* !CONFIG_64BIT */ -# define SECCOMP_ARCH_NATIVE AUDIT_ARCH_PARISC -# define SECCOMP_ARCH_NATIVE_NR NR_syscalls -# define SECCOMP_ARCH_NATIVE_NAME "parisc" -#endif - -#endif /* _ASM_SECCOMP_H */ diff --git a/arch/parisc/include/uapi/asm/socket.h b/arch/parisc/include/uapi/asm/socket.h index 1a8ec3838c9b..10173c32195e 100644 --- a/arch/parisc/include/uapi/asm/socket.h +++ b/arch/parisc/include/uapi/asm/socket.h @@ -116,8 +116,6 @@ #define SO_DETACH_REUSEPORT_BPF 0x4042 -#define SO_NETNS_COOKIE 0x4045 - #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 diff --git a/arch/powerpc/include/asm/seccomp.h b/arch/powerpc/include/asm/seccomp.h index ac2033f134f0..51209f6071c5 100644 --- a/arch/powerpc/include/asm/seccomp.h +++ b/arch/powerpc/include/asm/seccomp.h @@ -8,27 +8,4 @@ #include -#ifdef __LITTLE_ENDIAN__ -#define __SECCOMP_ARCH_LE __AUDIT_ARCH_LE -#define __SECCOMP_ARCH_LE_NAME "le" -#else -#define __SECCOMP_ARCH_LE 0 -#define __SECCOMP_ARCH_LE_NAME -#endif - -#ifdef CONFIG_PPC64 -# define SECCOMP_ARCH_NATIVE (AUDIT_ARCH_PPC64 | __SECCOMP_ARCH_LE) -# define SECCOMP_ARCH_NATIVE_NR NR_syscalls -# define SECCOMP_ARCH_NATIVE_NAME "ppc64" __SECCOMP_ARCH_LE_NAME -# ifdef CONFIG_COMPAT -# define SECCOMP_ARCH_COMPAT (AUDIT_ARCH_PPC | __SECCOMP_ARCH_LE) -# define SECCOMP_ARCH_COMPAT_NR NR_syscalls -# define SECCOMP_ARCH_COMPAT_NAME "ppc" __SECCOMP_ARCH_LE_NAME -# endif -#else /* !CONFIG_PPC64 */ -# define SECCOMP_ARCH_NATIVE (AUDIT_ARCH_PPC | __SECCOMP_ARCH_LE) -# define SECCOMP_ARCH_NATIVE_NR NR_syscalls -# define SECCOMP_ARCH_NATIVE_NAME "ppc" __SECCOMP_ARCH_LE_NAME -#endif - #endif /* _ASM_POWERPC_SECCOMP_H */ diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 054ab2f280db..1641d8201412 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -38,7 +38,7 @@ ifeq ($(CONFIG_LD_IS_LLD),y) ifeq ($(shell test $(CONFIG_LLD_VERSION) -lt 150000; echo $$?),0) KBUILD_CFLAGS += -mno-relax KBUILD_AFLAGS += -mno-relax -ifndef CONFIG_AS_IS_LLVM +ifneq ($(LLVM_IAS),1) KBUILD_CFLAGS += -Wa,-mno-relax KBUILD_AFLAGS += -Wa,-mno-relax endif diff --git a/arch/s390/include/asm/seccomp.h b/arch/s390/include/asm/seccomp.h index 71d46f0ba97b..795bbe0d7ca6 100644 --- a/arch/s390/include/asm/seccomp.h +++ b/arch/s390/include/asm/seccomp.h @@ -16,13 +16,4 @@ #include -#define SECCOMP_ARCH_NATIVE AUDIT_ARCH_S390X -#define SECCOMP_ARCH_NATIVE_NR NR_syscalls -#define SECCOMP_ARCH_NATIVE_NAME "s390x" -#ifdef CONFIG_COMPAT -# define SECCOMP_ARCH_COMPAT AUDIT_ARCH_S390 -# define SECCOMP_ARCH_COMPAT_NR NR_syscalls -# define SECCOMP_ARCH_COMPAT_NAME "s390" -#endif - #endif /* _ASM_S390_SECCOMP_H */ diff --git a/arch/sh/include/asm/seccomp.h b/arch/sh/include/asm/seccomp.h index d4578395fd66..54111e4d32b8 100644 --- a/arch/sh/include/asm/seccomp.h +++ b/arch/sh/include/asm/seccomp.h @@ -8,14 +8,4 @@ #define __NR_seccomp_exit __NR_exit #define __NR_seccomp_sigreturn __NR_rt_sigreturn -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#define __SECCOMP_ARCH_LE __AUDIT_ARCH_LE -#else -#define __SECCOMP_ARCH_LE 0 -#endif - -#define SECCOMP_ARCH_NATIVE (AUDIT_ARCH_SH | __SECCOMP_ARCH_LE) -#define SECCOMP_ARCH_NATIVE_NR NR_syscalls -#define SECCOMP_ARCH_NATIVE_NAME "sh" - #endif /* __ASM_SECCOMP_H */ diff --git a/arch/sparc/include/uapi/asm/socket.h b/arch/sparc/include/uapi/asm/socket.h index 08f9bbbf5bf2..8029b681fc7c 100644 --- a/arch/sparc/include/uapi/asm/socket.h +++ b/arch/sparc/include/uapi/asm/socket.h @@ -117,8 +117,6 @@ #define SO_DETACH_REUSEPORT_BPF 0x0047 -#define SO_NETNS_COOKIE 0x0050 - #if !defined(__KERNEL__) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 8a42463ffee5..6e1e5f49664e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -139,7 +139,6 @@ config X86 select HAVE_ARCH_JUMP_LABEL select HAVE_ARCH_JUMP_LABEL_RELATIVE select HAVE_ARCH_KASAN if X86_64 - select HAVE_ARCH_KFENCE select HAVE_ARCH_KGDB select HAVE_ARCH_MMAP_RND_BITS if MMU select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT diff --git a/arch/x86/configs/gki_defconfig b/arch/x86/configs/gki_defconfig index ebab1f1901d8..5e751e6cb304 100644 --- a/arch/x86/configs/gki_defconfig +++ b/arch/x86/configs/gki_defconfig @@ -188,27 +188,14 @@ CONFIG_L2TP=y CONFIG_BRIDGE=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_HTB=y -CONFIG_NET_SCH_PRIO=y -CONFIG_NET_SCH_MULTIQ=y -CONFIG_NET_SCH_TBF=y -CONFIG_NET_SCH_NETEM=y CONFIG_NET_SCH_INGRESS=y CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y CONFIG_NET_CLS_BPF=y CONFIG_NET_CLS_MATCHALL=y CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y -CONFIG_NET_ACT_GACT=y -CONFIG_NET_ACT_MIRRED=y -CONFIG_NET_ACT_SKBEDIT=y CONFIG_NET_ACT_BPF=y CONFIG_BPF_JIT=y CONFIG_BT=y @@ -442,7 +429,6 @@ CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y CONFIG_QUOTA=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y -CONFIG_FUSE_BPF=y CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y @@ -534,9 +520,6 @@ CONFIG_DEBUG_INFO_DWARF4=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_KFENCE=y -CONFIG_KFENCE_SAMPLE_INTERVAL=500 -CONFIG_KFENCE_NUM_OBJECTS=63 CONFIG_SOFTLOCKUP_DETECTOR=y # CONFIG_DETECT_HUNG_TASK is not set CONFIG_PANIC_ON_OOPS=y diff --git a/arch/x86/include/asm/kfence.h b/arch/x86/include/asm/kfence.h deleted file mode 100644 index 2d66d70600bd..000000000000 --- a/arch/x86/include/asm/kfence.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * x86 KFENCE support. - * - * Copyright (C) 2020, Google LLC. - */ - -#ifndef _ASM_X86_KFENCE_H -#define _ASM_X86_KFENCE_H - -#include -#include - -#include -#include -#include -#include - -/* Force 4K pages for __kfence_pool. */ -static inline bool arch_kfence_init_pool(void) -{ - unsigned long addr; - - for (addr = (unsigned long)__kfence_pool; is_kfence_address((void *)addr); - addr += PAGE_SIZE) { - unsigned int level; - - if (!lookup_address(addr, &level)) - return false; - - if (level != PG_LEVEL_4K) - set_memory_4k(addr, 1); - } - - return true; -} - -/* Protect the given page and flush TLB. */ -static inline bool kfence_protect_page(unsigned long addr, bool protect) -{ - unsigned int level; - pte_t *pte = lookup_address(addr, &level); - - if (WARN_ON(!pte || level != PG_LEVEL_4K)) - return false; - - /* - * We need to avoid IPIs, as we may get KFENCE allocations or faults - * with interrupts disabled. Therefore, the below is best-effort, and - * does not flush TLBs on all CPUs. We can tolerate some inaccuracy; - * lazy fault handling takes care of faults after the page is PRESENT. - */ - - if (protect) - set_pte(pte, __pte(pte_val(*pte) & ~_PAGE_PRESENT)); - else - set_pte(pte, __pte(pte_val(*pte) | _PAGE_PRESENT)); - - /* Flush this CPU's TLB. */ - __flush_tlb_one_kernel(addr); - return true; -} - -#endif /* _ASM_X86_KFENCE_H */ diff --git a/arch/x86/include/asm/seccomp.h b/arch/x86/include/asm/seccomp.h index fef16e398161..2bd1338de236 100644 --- a/arch/x86/include/asm/seccomp.h +++ b/arch/x86/include/asm/seccomp.h @@ -16,26 +16,6 @@ #define __NR_seccomp_sigreturn_32 __NR_ia32_sigreturn #endif -#ifdef CONFIG_X86_64 -# define SECCOMP_ARCH_NATIVE AUDIT_ARCH_X86_64 -# define SECCOMP_ARCH_NATIVE_NR NR_syscalls -# define SECCOMP_ARCH_NATIVE_NAME "x86_64" -# ifdef CONFIG_COMPAT -# define SECCOMP_ARCH_COMPAT AUDIT_ARCH_I386 -# define SECCOMP_ARCH_COMPAT_NR IA32_NR_syscalls -# define SECCOMP_ARCH_COMPAT_NAME "ia32" -# endif -/* - * x32 will have __X32_SYSCALL_BIT set in syscall number. We don't support - * caching them and they are treated as out of range syscalls, which will - * always pass through the BPF filter. - */ -#else /* !CONFIG_X86_64 */ -# define SECCOMP_ARCH_NATIVE AUDIT_ARCH_I386 -# define SECCOMP_ARCH_NATIVE_NR NR_syscalls -# define SECCOMP_ARCH_NATIVE_NAME "ia32" -#endif - #include #endif /* _ASM_X86_SECCOMP_H */ diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index e6dc014ece01..2fa5e0e5f8e5 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -9,7 +9,6 @@ #include /* oops_begin/end, ... */ #include /* search_exception_tables */ #include /* max_low_pfn */ -#include /* kfence_handle_page_fault */ #include /* NOKPROBE_SYMBOL, ... */ #include /* kmmio_handler, ... */ #include /* perf_sw_event */ @@ -802,11 +801,6 @@ no_context(struct pt_regs *regs, unsigned long error_code, if (IS_ENABLED(CONFIG_EFI)) efi_recover_from_page_fault(address); - /* Only not-present faults should be handled by KFENCE. */ - if (!(error_code & X86_PF_PROT) && - kfence_handle_page_fault(address, error_code & X86_PF_WRITE, regs)) - return; - oops: /* * Oops. The kernel tried to access some bad page. We'll have to diff --git a/arch/xtensa/include/asm/seccomp.h b/arch/xtensa/include/asm/seccomp.h deleted file mode 100644 index f1cb6b0a9e1f..000000000000 --- a/arch/xtensa/include/asm/seccomp.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _ASM_SECCOMP_H -#define _ASM_SECCOMP_H - -#include - -#define SECCOMP_ARCH_NATIVE AUDIT_ARCH_XTENSA -#define SECCOMP_ARCH_NATIVE_NR NR_syscalls -#define SECCOMP_ARCH_NATIVE_NAME "xtensa" - -#endif /* _ASM_SECCOMP_H */ diff --git a/block/blk-core.c b/block/blk-core.c index c565130ddf75..74f7a2a4f295 100644 --- a/block/blk-core.c +++ b/block/blk-core.c @@ -504,6 +504,8 @@ struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id) if (!q->stats) goto fail_stats; + q->backing_dev_info->ra_pages = VM_READAHEAD_PAGES; + q->backing_dev_info->io_pages = VM_READAHEAD_PAGES; q->backing_dev_info->capabilities = BDI_CAP_CGROUP_WRITEBACK; q->backing_dev_info->name = "block"; q->node = node_id; diff --git a/drivers/android/binder.c b/drivers/android/binder.c index cfe7a2aa026c..5419d6e0e560 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -6923,7 +6923,7 @@ const struct file_operations binder_fops = { .owner = THIS_MODULE, .poll = binder_poll, .unlocked_ioctl = binder_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = binder_ioctl, .mmap = binder_mmap, .open = binder_open, .flush = binder_flush, diff --git a/drivers/cdrom/cdrom.c b/drivers/cdrom/cdrom.c index 628d6598efe8..c846cd711bb0 100644 --- a/drivers/cdrom/cdrom.c +++ b/drivers/cdrom/cdrom.c @@ -3495,7 +3495,7 @@ static int cdrom_print_info(const char *header, int val, char *info, } static int cdrom_sysctl_info(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int pos; char *info = cdrom_sysctl_settings.info; diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index 979debfc811c..7ecf16753f17 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /* Uncomment this block to log an error on every VERIFY failure */ @@ -62,7 +62,6 @@ #define TZ_PIL_AUTH_QDSP6_PROC 1 #define FASTRPC_DMAHANDLE_NOMAP (16) -#define FASTRPC_MAP_DMA_HANDLE 0x20000 #define FASTRPC_ENOSUCH 39 #define DEBUGFS_SIZE 3072 @@ -444,7 +443,6 @@ struct smq_invoke_ctx { uint32_t sc_interrupted; struct fastrpc_file *fl_interrupted; uint32_t handle_interrupted; - struct timespec64 invoke_start_time; /* submission timestamp for async perf */ }; struct fastrpc_ctx_lst { @@ -1130,7 +1128,7 @@ static void fastrpc_mmap_add(struct fastrpc_mmap *map) } static int fastrpc_mmap_find(struct fastrpc_file *fl, int fd, - uintptr_t va, size_t len, int mflags, bool refs, + uintptr_t va, size_t len, int mflags, int refs, struct fastrpc_mmap **ppmap) { struct fastrpc_mmap *match = NULL, *map = NULL; @@ -1308,7 +1306,7 @@ static void fastrpc_mmap_free(struct fastrpc_mmap *map, uint32_t flags) dma_free_attrs(me->dev, map->size, (void *)map->va, (dma_addr_t)map->phys, (unsigned long)map->attr); } - } else if (map->flags & FASTRPC_DMAHANDLE_NOMAP) { + } else if (map->flags == FASTRPC_DMAHANDLE_NOMAP) { trace_fastrpc_dma_unmap(cid, map->phys, map->size); if (!IS_ERR_OR_NULL(map->table)) dma_buf_unmap_attachment(map->attach, map->table, @@ -1393,7 +1391,6 @@ static int fastrpc_mmap_create(struct fastrpc_file *fl, int fd, unsigned long flags; int err = 0, vmid, sgl_index = 0; struct scatterlist *sgl = NULL; - bool take_ref = true; if (!fl) { err = -EBADF; @@ -1407,9 +1404,7 @@ static int fastrpc_mmap_create(struct fastrpc_file *fl, int fd, } chan = &apps->channel[cid]; - if (mflags & FASTRPC_MAP_DMA_HANDLE) - take_ref = false; - if (!fastrpc_mmap_find(fl, fd, va, len, mflags, take_ref, ppmap)) + if (!fastrpc_mmap_find(fl, fd, va, len, mflags, 1, ppmap)) return 0; map = kzalloc(sizeof(*map), GFP_KERNEL); VERIFY(err, !IS_ERR_OR_NULL(map)); @@ -1447,7 +1442,7 @@ static int fastrpc_mmap_create(struct fastrpc_file *fl, int fd, if (err) goto bail; } - } else if (mflags & FASTRPC_DMAHANDLE_NOMAP) { + } else if (mflags == FASTRPC_DMAHANDLE_NOMAP) { if (map->attr & FASTRPC_ATTR_KEEP_MAP) { ADSPRPC_ERR("Invalid attribute 0x%x for fd %d\n", map->attr, fd); @@ -2507,10 +2502,10 @@ static int get_args(uint32_t kernel, struct smq_invoke_ctx *ctx) handles = REMOTE_SCALARS_INHANDLES(sc) + REMOTE_SCALARS_OUTHANDLES(sc); mutex_lock(&ctx->fl->map_mutex); for (i = bufs; i < bufs + handles; i++) { - int dmaflags = FASTRPC_MAP_DMA_HANDLE; + int dmaflags = 0; if (ctx->attrs && (ctx->attrs[i] & FASTRPC_ATTR_NOMAP)) - dmaflags |= FASTRPC_DMAHANDLE_NOMAP; + dmaflags = FASTRPC_DMAHANDLE_NOMAP; if (ctx->fds && (ctx->fds[i] != -1)) err = fastrpc_mmap_create(ctx->fl, ctx->fds[i], FASTRPC_ATTR_NOVA, 0, 0, dmaflags, @@ -2671,7 +2666,7 @@ static int get_args(uint32_t kernel, struct smq_invoke_ctx *ctx) if (ctx->maps[i]) { /* check if map still exist */ if (!fastrpc_mmap_find(ctx->fl, ctx->fds[i], 0, 0, - 0, false, &mmap)) { + 0, 0, &mmap)) { if (mmap) { pages[i].addr = mmap->phys; pages[i].size = mmap->size; @@ -2886,7 +2881,7 @@ static int put_args(uint32_t kernel, struct smq_invoke_ctx *ctx, if (!fdlist[i]) break; if (!fastrpc_mmap_find(ctx->fl, (int)fdlist[i], 0, 0, - 0, false, &mmap)) { + 0, 0, &mmap)) { if (mmap && mmap->dma_handle_refs) { mmap->dma_handle_refs = 0; fastrpc_mmap_free(mmap, 0); @@ -3369,15 +3364,6 @@ static int fastrpc_internal_invoke(struct fastrpc_file *fl, uint32_t mode, inv_args(ctx); PERF_END); - /* - * Store submission timestamp in ctx before sending to DSP. - * For async invokes, perf->invoke will be updated in the collector - * thread (fastrpc_wait_on_async_queue) where ctx is still valid, - * measuring full end-to-end latency consistent with the sync path. - */ - if (fl->profile && isasyncinvoke) - ctx->invoke_start_time = invoket; - PERF(fl->profile, GET_COUNTER(perf_counter, PERF_LINK), VERIFY(err, 0 == (err = fastrpc_invoke_send(ctx, kernel, invoke->handle))); @@ -3439,6 +3425,9 @@ static int fastrpc_internal_invoke(struct fastrpc_file *fl, uint32_t mode, err = -ECONNRESET; invoke_end: + if (fl->profile && !interrupted && isasyncinvoke) + fastrpc_update_invoke_count(invoke->handle, perf_counter, + &invoket); return err; } @@ -3508,15 +3497,6 @@ bail: async_res->result = ierr; if (ctx) { if (fl->profile && ctx->perf && ctx->handle > FASTRPC_STATIC_HANDLE_MAX) { - /* - * Update invoke/count perf counters here where ctx->perf is - * guaranteed valid. This measures full end-to-end async latency - * (submit → DSP → collect), consistent with the sync path. - * invoke_start_time was stored in ctx before fastrpc_invoke_send - * in fastrpc_internal_invoke. - */ - fastrpc_update_invoke_count(ctx->handle, perf_counter, - &ctx->invoke_start_time); trace_fastrpc_perf_counters(ctx->handle, ctx->sc, ctx->perf->count, ctx->perf->flush, ctx->perf->map, ctx->perf->copy, ctx->perf->link, ctx->perf->getargs, @@ -4981,7 +4961,7 @@ static int fastrpc_internal_munmap_fd(struct fastrpc_file *fl, } mutex_lock(&fl->internal_map_mutex); mutex_lock(&fl->map_mutex); - err = fastrpc_mmap_find(fl, ud->fd, ud->va, ud->len, 0, false, &map); + err = fastrpc_mmap_find(fl, ud->fd, ud->va, ud->len, 0, 0, &map); if (err) { ADSPRPC_ERR( "mapping not found to unmap fd 0x%x, va 0x%llx, len 0x%x, err %d\n", diff --git a/drivers/char/random.c b/drivers/char/random.c index e7fc274a9608..e624bbc09fb1 100644 --- a/drivers/char/random.c +++ b/drivers/char/random.c @@ -799,11 +799,16 @@ early_param("random.trust_cpu", parse_trust_cpu); early_param("random.trust_bootloader", parse_trust_bootloader); /* - * This is called extremely early, before time keeping functionality is - * available, but arch randomness is. Interrupts are not yet enabled. + * The first collection of entropy occurs at system boot while interrupts + * are still turned off. Here we push in latent entropy, RDSEED, a timestamp, + * utsname(), and the command line. Depending on the above configuration knob, + * RDSEED may be considered sufficient for initialization. Note that much + * earlier setup may already have pushed entropy into the input pool by the + * time we get here. */ -void __init random_init_early(const char *command_line) +int __init random_init(const char *command_line) { + ktime_t now = ktime_get_real(); unsigned int i, arch_bits; unsigned long entropy; @@ -816,41 +821,22 @@ void __init random_init_early(const char *command_line) i < BLAKE2S_BLOCK_SIZE; i += sizeof(entropy)) { if (!arch_get_random_seed_long_early(&entropy) && !arch_get_random_long_early(&entropy)) { + entropy = random_get_entropy(); arch_bits -= sizeof(entropy) * 8; - continue; } _mix_pool_bytes(&entropy, sizeof(entropy)); } - + _mix_pool_bytes(&now, sizeof(now)); + _mix_pool_bytes(utsname(), sizeof(*(utsname()))); _mix_pool_bytes(command_line, strlen(command_line)); + add_latent_entropy(); - /* Reseed if already seeded by earlier phases. */ if (crng_ready()) crng_reseed(); else if (trust_cpu) _credit_init_bits(arch_bits); -} -/* - * This is called a little bit after the prior function, and now there is - * access to timestamps counters. Interrupts are not yet enabled. - */ -void __init random_init(void) -{ - unsigned long entropy = random_get_entropy(); - ktime_t now = ktime_get_real(); - - _mix_pool_bytes(utsname(), sizeof(*(utsname()))); - _mix_pool_bytes(&now, sizeof(now)); - _mix_pool_bytes(&entropy, sizeof(entropy)); - add_latent_entropy(); - - /* Reseed if already seeded by earlier phases. */ - if (crng_ready()) - crng_reseed(); - - WARN(!entropy, "Missing cycle counter and fallback timer; RNG " - "entropy collection will consequently suffer."); + return 0; } /* @@ -1491,7 +1477,7 @@ static int proc_do_uuid(struct ctl_table *table, int write, void *buf, } /* The same as proc_dointvec, but writes don't change anything. */ -static int proc_do_rointvec(struct ctl_table *table, int write, void *buf, +static int proc_do_rointvec(struct ctl_table *table, int write, void __user *buf, size_t *lenp, loff_t *ppos) { return write ? 0 : proc_dointvec(table, 0, buf, lenp, ppos); diff --git a/drivers/crypto/msm/qcedev_smmu.c b/drivers/crypto/msm/qcedev_smmu.c index 7039bce67c5c..8d4844becc85 100644 --- a/drivers/crypto/msm/qcedev_smmu.c +++ b/drivers/crypto/msm/qcedev_smmu.c @@ -329,6 +329,10 @@ int qcedev_check_and_map_buffer(void *handle, mapped_size = binfo->ion_buf.mapped_buf_size; atomic_inc(&binfo->ref_count); + /* Add buffer mapping information to regd buffer list */ + mutex_lock(&qce_hndl->registeredbufs.lock); + list_add_tail(&binfo->list, &qce_hndl->registeredbufs.list); + mutex_unlock(&qce_hndl->registeredbufs.lock); } /* Make sure the offset is within the mapped range */ @@ -340,13 +344,6 @@ int qcedev_check_and_map_buffer(void *handle, goto unmap; } - if (!found) { - /* Add buffer mapping information to regd buffer list */ - mutex_lock(&qce_hndl->registeredbufs.lock); - list_add_tail(&binfo->list, &qce_hndl->registeredbufs.list); - mutex_unlock(&qce_hndl->registeredbufs.lock); - } - /* return the mapped virtual address adjusted by offset */ *vaddr += offset; @@ -355,6 +352,9 @@ int qcedev_check_and_map_buffer(void *handle, unmap: if (!found) { qcedev_unmap_buffer(handle, mem_client, binfo); + mutex_lock(&qce_hndl->registeredbufs.lock); + list_del(&binfo->list); + mutex_unlock(&qce_hndl->registeredbufs.lock); } error: diff --git a/drivers/crypto/qat/qat_common/adf_ctl_drv.c b/drivers/crypto/qat/qat_common/adf_ctl_drv.c index ef0e482ee04f..abc7a7f64d64 100644 --- a/drivers/crypto/qat/qat_common/adf_ctl_drv.c +++ b/drivers/crypto/qat/qat_common/adf_ctl_drv.c @@ -68,7 +68,7 @@ static long adf_ctl_ioctl(struct file *fp, unsigned int cmd, unsigned long arg); static const struct file_operations adf_ctl_ops = { .owner = THIS_MODULE, .unlocked_ioctl = adf_ctl_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = adf_ctl_ioctl, }; struct adf_ctl_drv_info { diff --git a/drivers/dax/super.c b/drivers/dax/super.c index c54bb58de20c..5005b92b197d 100644 --- a/drivers/dax/super.c +++ b/drivers/dax/super.c @@ -348,26 +348,6 @@ size_t dax_copy_to_iter(struct dax_device *dax_dev, pgoff_t pgoff, void *addr, } EXPORT_SYMBOL_GPL(dax_copy_to_iter); -int dax_zero_page_range(struct dax_device *dax_dev, pgoff_t pgoff, - size_t nr_pages) -{ - if (!dax_alive(dax_dev)) - return -ENXIO; - - if (!dax_dev->ops->zero_page_range) - return -EOPNOTSUPP; - /* - * There are no callers that want to zero more than one page as of now. - * Once users are there, this check can be removed after the - * device mapper code has been updated to split ranges across targets. - */ - if (nr_pages != 1) - return -EIO; - - return dax_dev->ops->zero_page_range(dax_dev, pgoff, nr_pages); -} -EXPORT_SYMBOL_GPL(dax_zero_page_range); - #ifdef CONFIG_ARCH_HAS_PMEM_API void arch_wb_cache_pmem(void *addr, size_t size); void dax_flush(struct dax_device *dax_dev, void *addr, size_t size) diff --git a/drivers/devfreq/arm-memlat-mon.c b/drivers/devfreq/arm-memlat-mon.c index 1ab4a88e4fa0..4fc8f76918e4 100644 --- a/drivers/devfreq/arm-memlat-mon.c +++ b/drivers/devfreq/arm-memlat-mon.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014-2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. */ #define pr_fmt(fmt) "arm-memlat-mon: " fmt @@ -126,7 +126,6 @@ struct memlat_mon { * @mons: All of the memlat_mon structs representing * the different voters who share this cpu_grp. * @mons_lock: A lock used to protect the @mons. - * @init_mons_lock: A lock used to protect the @mons in probe routine. */ struct memlat_cpu_grp { cpumask_t cpus; @@ -144,7 +143,6 @@ struct memlat_cpu_grp { unsigned int num_active_mons; struct memlat_mon *mons; struct mutex mons_lock; - struct mutex init_mons_lock; spinlock_t mon_active_lock; }; @@ -519,15 +517,11 @@ static int memlat_event_hotplug_going_down(unsigned int cpu) return ret; } -/* - * Note: We must be holding cpus_read_lock() before calling this function - * since we are using cpuslocked version of function inside it - */ static int memlat_event_cpu_hp_init(void) { int ret = 0; - ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN, + ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "MEMLAT_EVENT", memlat_event_hotplug_coming_up, memlat_event_hotplug_going_down); @@ -857,7 +851,6 @@ static int memlat_cpu_grp_probe(struct platform_device *pdev) return -ENOMEM; mutex_init(&cpu_grp->mons_lock); - mutex_init(&cpu_grp->init_mons_lock); spin_lock_init(&cpu_grp->mon_active_lock); cpu_grp->update_ms = DEFAULT_UPDATE_MS; @@ -893,7 +886,7 @@ static int memlat_mon_probe(struct platform_device *pdev, bool is_compute) return -ENODEV; } - mutex_lock(&cpu_grp->init_mons_lock); + mutex_lock(&cpu_grp->mons_lock); mon = &cpu_grp->mons[cpu_grp->num_inited_mons]; spin_lock_irqsave(&cpu_grp->mon_active_lock, flags); mon->is_active = false; @@ -1010,7 +1003,7 @@ static int memlat_mon_probe(struct platform_device *pdev, bool is_compute) cpu_grp->num_inited_mons++; unlock_out: - mutex_unlock(&cpu_grp->init_mons_lock); + mutex_unlock(&cpu_grp->mons_lock); return ret; } diff --git a/drivers/devfreq/bimc-bwmon.c b/drivers/devfreq/bimc-bwmon.c index f7be1c0353d2..668477348ae9 100644 --- a/drivers/devfreq/bimc-bwmon.c +++ b/drivers/devfreq/bimc-bwmon.c @@ -882,7 +882,7 @@ int __suspend_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type) struct bwmon *m = to_bwmon(hw); mon_irq_disable(m, type); - disable_irq(m->irq); + free_irq(m->irq, m); mon_disable(m, type); mon_irq_clear(m, type); @@ -908,6 +908,7 @@ static __always_inline int __resume_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type) { struct bwmon *m = to_bwmon(hw); + int ret; irq_handler_t handler; switch (type) { @@ -923,7 +924,15 @@ int __resume_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type) } mon_clear(m, false, type); - enable_irq(m->irq); + ret = request_threaded_irq(m->irq, handler, bwmon_intr_thread, + IRQF_ONESHOT | IRQF_SHARED, + dev_name(m->dev), m); + if (ret < 0) { + dev_err(m->dev, "Unable to register interrupt handler! (%d)\n", + ret); + return ret; + } + mon_irq_enable(m, type); mon_enable(m, type); diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index 81709add4b0e..88afaed2cb61 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -70,28 +70,28 @@ static struct devfreq *find_device_devfreq(struct device *dev) return ERR_PTR(-ENODEV); } -static long find_available_min_freq(struct devfreq *devfreq) +static unsigned long find_available_min_freq(struct devfreq *devfreq) { struct dev_pm_opp *opp; - long min_freq = 0; + unsigned long min_freq = 0; opp = dev_pm_opp_find_freq_ceil(devfreq->dev.parent, &min_freq); if (IS_ERR(opp)) - min_freq = PTR_ERR(opp); + min_freq = 0; else dev_pm_opp_put(opp); return min_freq; } -static long find_available_max_freq(struct devfreq *devfreq) +static unsigned long find_available_max_freq(struct devfreq *devfreq) { struct dev_pm_opp *opp; - long max_freq = LONG_MAX; + unsigned long max_freq = ULONG_MAX; opp = dev_pm_opp_find_freq_floor(devfreq->dev.parent, &max_freq); if (IS_ERR(opp)) - max_freq = PTR_ERR(opp); + max_freq = 0; else dev_pm_opp_put(opp); @@ -318,7 +318,7 @@ static int devfreq_set_target(struct devfreq *devfreq, unsigned long new_freq, devfreq->previous_freq = new_freq; - if (devfreq->suspend_freq >= devfreq->scaling_min_freq) + if (devfreq->suspend_freq) devfreq->resume_freq = new_freq; return err; @@ -552,23 +552,18 @@ static int devfreq_notifier_call(struct notifier_block *nb, unsigned long type, { struct devfreq *devfreq = container_of(nb, struct devfreq, nb); int err = -EINVAL; - long freq; mutex_lock(&devfreq->lock); - freq = find_available_min_freq(devfreq); - if (freq < 0) { - devfreq->scaling_min_freq = 0; + devfreq->scaling_min_freq = find_available_min_freq(devfreq); + if (!devfreq->scaling_min_freq) goto out; - } - devfreq->scaling_min_freq = freq; - freq = find_available_max_freq(devfreq); - if (freq < 0) { + devfreq->scaling_max_freq = find_available_max_freq(devfreq); + if (!devfreq->scaling_max_freq) { devfreq->scaling_max_freq = ULONG_MAX; goto out; } - devfreq->scaling_max_freq = freq; err = update_devfreq(devfreq); @@ -621,7 +616,6 @@ struct devfreq *devfreq_add_device(struct device *dev, struct devfreq *devfreq; struct devfreq_governor *governor; int err = 0; - long freq; if (!dev || !profile || !governor_name) { dev_err(dev, "%s: Invalid parameters.\n", __func__); @@ -666,21 +660,21 @@ struct devfreq *devfreq_add_device(struct device *dev, mutex_lock(&devfreq->lock); } - freq = find_available_min_freq(devfreq); - if (freq < 0) { + devfreq->scaling_min_freq = find_available_min_freq(devfreq); + if (!devfreq->scaling_min_freq) { mutex_unlock(&devfreq->lock); err = -EINVAL; goto err_dev; } - devfreq->min_freq = devfreq->scaling_min_freq = freq; + devfreq->min_freq = devfreq->scaling_min_freq; - freq = find_available_max_freq(devfreq); - if (freq < 0) { + devfreq->scaling_max_freq = find_available_max_freq(devfreq); + if (!devfreq->scaling_max_freq) { mutex_unlock(&devfreq->lock); err = -EINVAL; goto err_dev; } - devfreq->max_freq = devfreq->scaling_max_freq = freq; + devfreq->max_freq = devfreq->scaling_max_freq; devfreq->suspend_freq = dev_pm_opp_get_suspend_opp_freq(dev); atomic_set(&devfreq->suspend_count, 0); @@ -912,7 +906,7 @@ int devfreq_suspend_device(struct devfreq *devfreq) return ret; } - if (devfreq->suspend_freq >= devfreq->scaling_min_freq) { + if (devfreq->suspend_freq) { mutex_lock(&devfreq->lock); ret = devfreq_set_target(devfreq, devfreq->suspend_freq, 0); mutex_unlock(&devfreq->lock); diff --git a/drivers/devfreq/governor_bw_hwmon.c b/drivers/devfreq/governor_bw_hwmon.c index 261b40843ff3..2acdb0a3fe5a 100644 --- a/drivers/devfreq/governor_bw_hwmon.c +++ b/drivers/devfreq/governor_bw_hwmon.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. */ #define pr_fmt(fmt) "bw-hwmon: " fmt @@ -80,8 +80,6 @@ static DEFINE_MUTEX(list_lock); static int use_cnt; static DEFINE_MUTEX(state_lock); -static DEFINE_MUTEX(event_handle_lock); - #define show_attr(name) \ static ssize_t name##_show(struct device *dev, \ struct device_attribute *attr, char *buf) \ @@ -867,7 +865,7 @@ static int devfreq_bw_hwmon_ev_handler(struct devfreq *df, struct hwmon_node *node; struct bw_hwmon *hw; - mutex_lock(&event_handle_lock); + mutex_lock(&state_lock); switch (event) { case DEVFREQ_GOV_START: @@ -941,7 +939,7 @@ static int devfreq_bw_hwmon_ev_handler(struct devfreq *df, } out: - mutex_unlock(&event_handle_lock); + mutex_unlock(&state_lock); return ret; } diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index 6541c28ede73..9b774277b75e 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -468,7 +468,9 @@ static const struct file_operations dma_buf_fops = { .llseek = dma_buf_llseek, .poll = dma_buf_poll, .unlocked_ioctl = dma_buf_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = dma_buf_ioctl, +#endif .show_fdinfo = dma_buf_show_fdinfo, }; diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c index 7f5ed1aa7a9f..7e7356970d5f 100644 --- a/drivers/dma-buf/sw_sync.c +++ b/drivers/dma-buf/sw_sync.c @@ -408,5 +408,5 @@ const struct file_operations sw_sync_debugfs_fops = { .open = sw_sync_debugfs_open, .release = sw_sync_debugfs_release, .unlocked_ioctl = sw_sync_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = sw_sync_ioctl, }; diff --git a/drivers/dma-buf/sync_file.c b/drivers/dma-buf/sync_file.c index f0c822952c20..992c15c016dd 100644 --- a/drivers/dma-buf/sync_file.c +++ b/drivers/dma-buf/sync_file.c @@ -481,5 +481,5 @@ static const struct file_operations sync_file_fops = { .release = sync_file_release, .poll = sync_file_poll, .unlocked_ioctl = sync_file_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = sync_file_ioctl, }; diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index eb9aea7851ff..44e2e7de129e 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2525,12 +2524,6 @@ struct dma_async_tx_descriptor *gpi_prep_slave_sg(struct dma_chan *chan, for_each_sg(sgl, sg, sg_len, i) { tre = sg_virt(sg); - if (!tre) { - kfree(gpi_desc); - GPII_ERR(gpii, gpii_chan->chid, "TRE address is null\n"); - return NULL; - } - if (sg_len == 1) { tre_type = MSM_GPI_TRE_TYPE(((struct msm_gpi_tre *)tre)); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index fb5fca3d2149..548cd062b9cd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -49,7 +49,7 @@ static const char kfd_dev_name[] = "kfd"; static const struct file_operations kfd_fops = { .owner = THIS_MODULE, .unlocked_ioctl = kfd_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = kfd_ioctl, .open = kfd_open, .mmap = kfd_mmap, }; diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index a37aa033ed98..3a898033c178 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -1743,12 +1743,6 @@ static int adreno_pm_suspend(struct device *dev) status = ops->pm_suspend(adreno_dev); mutex_unlock(&device->mutex); - if (status) - return status; - - kthread_flush_worker(device->events_worker); - flush_workqueue(kgsl_driver.mem_workqueue); - return status; } diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index 93bebbdb24fc..048e33de599c 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -2524,7 +2523,6 @@ int a6xx_perfcounter_update(struct adreno_device *adreno_dev, struct cpu_gpu_lock *lock = ptr; u32 *data = ptr + sizeof(*lock); int i, offset = 0; - u32 pending_pairs = 2; /* No of pairs to add: and */ if (cpu_gpu_lock(lock)) { cpu_gpu_unlock(lock); @@ -2548,13 +2546,6 @@ int a6xx_perfcounter_update(struct adreno_device *adreno_dev, offset += 2; } - /* Ensure there is enough space in the reglist buffer for new pairs */ - if ((offset + (pending_pairs * 2)) >= - (adreno_dev->pwrup_reglist->size / sizeof(u32))) { - cpu_gpu_unlock(lock); - return -ENOSPC; - } - /* * For all targets A6XX_RBBM_PERFCTR_CNTL needs to be the last entry, * so overwrite the existing A6XX_RBBM_PERFCNTL_CTRL and add it back to diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index 07b1e1d24f45..8a4ea1752b24 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -593,7 +593,7 @@ static int find_vma_block(struct a6xx_gmu_device *gmu, u32 addr, u32 size) { int i; - for (i = 0; i < gmu->num_vmas; i++) { + for (i = 0; i < GMU_MEM_TYPE_MAX; i++) { struct gmu_vma_entry *vma = &gmu->vma[i]; if ((addr >= vma->start) && @@ -2685,13 +2685,10 @@ int a6xx_gmu_probe(struct kgsl_device *device, if (ret) goto error; - if (adreno_is_a650_family(adreno_dev)) { + if (adreno_is_a650_family(adreno_dev)) gmu->vma = a6xx_gmu_vma; - gmu->num_vmas = ARRAY_SIZE(a6xx_gmu_vma); - } else { + else gmu->vma = a6xx_gmu_vma_legacy; - gmu->num_vmas = ARRAY_SIZE(a6xx_gmu_vma_legacy); - } /* Map and reserve GMU CSRs registers */ ret = a6xx_gmu_reg_probe(adreno_dev); diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.h b/drivers/gpu/msm/adreno_a6xx_gmu.h index b671771c46b4..d39597683ec9 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.h +++ b/drivers/gpu/msm/adreno_a6xx_gmu.h @@ -187,8 +187,6 @@ struct a6xx_gmu_device { /** @global_entries: To keep track of number of gmu buffers */ u32 global_entries; struct gmu_vma_entry *vma; - /** @num_vmas: Number of entries in the @vma array */ - u32 num_vmas; unsigned int log_wptr_retention; /** @cm3_fault: whether gmu received a cm3 fault interrupt */ atomic_t cm3_fault; diff --git a/drivers/gpu/msm/adreno_a6xx_rpmh.c b/drivers/gpu/msm/adreno_a6xx_rpmh.c index c7a4b3297e45..0594304d64ee 100644 --- a/drivers/gpu/msm/adreno_a6xx_rpmh.c +++ b/drivers/gpu/msm/adreno_a6xx_rpmh.c @@ -120,7 +120,6 @@ static void tcs_cmd_data(struct bcm *bcms, int count, u32 ab, u32 ib, u32 *data) { int i; - u64 total_width; for (i = 0; i < count; i++) { bool valid = true; @@ -146,11 +145,8 @@ static void tcs_cmd_data(struct bcm *bcms, int count, u32 ab, u32 ib, /* Multiple the bandwidth by the width of the connection */ avg = ((u64) ab) * bcms[i].width; - total_width = bcms[i].buswidth * bcms[i].channels; - /* And then divide by the total width across channels */ - if (total_width) - do_div(avg, (u32) total_width); + do_div(avg, bcms[i].buswidth * bcms[i].channels); peak = ((u64) ib) * bcms[i].width; do_div(peak, bcms[i].buswidth); diff --git a/drivers/gpu/msm/governor_gpubw_mon.c b/drivers/gpu/msm/governor_gpubw_mon.c index af437abf107e..fabcd56b3776 100644 --- a/drivers/gpu/msm/governor_gpubw_mon.c +++ b/drivers/gpu/msm/governor_gpubw_mon.c @@ -101,7 +101,7 @@ static int devfreq_gpubw_get_target(struct devfreq *df, int act_level; int norm_max_cycles; int norm_cycles; - int wait_active_percent = 0; + int wait_active_percent; int gpu_percent; /* * Normalized AB should at max usage be the gpu_bimc frequency in MHz. @@ -132,9 +132,8 @@ static int devfreq_gpubw_get_target(struct devfreq *df, (unsigned int) priv->bus.total_time; norm_cycles = (unsigned int)(priv->bus.ram_time + priv->bus.ram_wait) / (unsigned int) priv->bus.total_time; - if (priv->bus.ram_time) - wait_active_percent = (100 * (unsigned int)priv->bus.ram_wait) / - (unsigned int) priv->bus.ram_time; + wait_active_percent = (100 * (unsigned int)priv->bus.ram_wait) / + (unsigned int) priv->bus.ram_time; gpu_percent = (100 * (unsigned int)priv->bus.gpu_time) / (unsigned int) priv->bus.total_time; diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index 99c3207530c5..60368d1ffcba 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -349,14 +349,12 @@ static void kgsl_destroy_ion(struct kgsl_memdesc *memdesc) if (meta != NULL) { remove_dmabuf_list(meta); - dma_buf_unmap_attachment(meta->attach, memdesc->sgt, DMA_BIDIRECTIONAL); dma_buf_detach(meta->dmabuf, meta->attach); dma_buf_put(meta->dmabuf); kfree(meta); } memdesc->sgt = NULL; - entry->priv_data = NULL; } static const struct kgsl_memdesc_ops kgsl_dmabuf_ops = { @@ -687,11 +685,11 @@ int kgsl_context_init(struct kgsl_device_private *dev_priv, if (id == -ENOSPC) { /* * Before declaring that there are no contexts left try - * flushing the event worker just in case there are + * flushing the event workqueue just in case there are * detached contexts waiting to finish */ - kthread_flush_worker(device->events_worker); + flush_workqueue(device->events_wq); id = _kgsl_get_context_id(device); } @@ -2997,7 +2995,7 @@ static int kgsl_setup_dma_buf(struct kgsl_device *device, { int ret = 0; struct scatterlist *s; - struct sg_table *sg_table = NULL; + struct sg_table *sg_table; struct dma_buf_attachment *attach = NULL; struct kgsl_dma_buf_meta *meta; @@ -3039,6 +3037,8 @@ static int kgsl_setup_dma_buf(struct kgsl_device *device, goto out; } + dma_buf_unmap_attachment(attach, sg_table, DMA_BIDIRECTIONAL); + meta->table = sg_table; entry->priv_data = meta; entry->memdesc.sgt = sg_table; @@ -3093,9 +3093,6 @@ skip_access_check: out: if (ret) { - if (!IS_ERR_OR_NULL(sg_table)) - dma_buf_unmap_attachment(attach, sg_table, DMA_BIDIRECTIONAL); - if (!IS_ERR_OR_NULL(attach)) dma_buf_detach(dmabuf, attach); @@ -4057,9 +4054,9 @@ static unsigned long _gpu_set_svm_region(struct kgsl_process_private *private, return addr; } -unsigned long kgsl_get_align(struct kgsl_memdesc *memdesc) +static unsigned long get_align(struct kgsl_mem_entry *entry) { - u32 bit = kgsl_memdesc_get_align(memdesc); + int bit = kgsl_memdesc_get_align(&entry->memdesc); if (bit >= ilog2(SZ_2M)) return SZ_2M; @@ -4068,7 +4065,7 @@ unsigned long kgsl_get_align(struct kgsl_memdesc *memdesc) else if (bit >= ilog2(SZ_64K)) return SZ_64K; - return PAGE_SIZE; + return SZ_4K; } static unsigned long set_svm_area(struct file *file, @@ -4101,7 +4098,7 @@ static unsigned long get_svm_unmapped_area(struct file *file, { struct kgsl_device_private *dev_priv = file->private_data; struct kgsl_process_private *private = dev_priv->process_priv; - unsigned long align = kgsl_get_align(&entry->memdesc); + unsigned long align = get_align(entry); unsigned long ret, iova; u64 start = 0, end = 0; struct vm_area_struct *vma; @@ -4528,16 +4525,15 @@ int kgsl_device_platform_probe(struct kgsl_device *device) device->pwrctrl.interrupt_num = status; disable_irq(device->pwrctrl.interrupt_num); - device->events_worker = kthread_create_worker(0, "kgsl-events"); + device->events_wq = alloc_workqueue("kgsl-events", + WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS | WQ_HIGHPRI, 0); - if (IS_ERR(device->events_worker)) { - status = PTR_ERR(device->events_worker); - dev_err(device->dev, "Failed to create events worker ret=%d\n", status); + if (!device->events_wq) { + dev_err(device->dev, "Failed to allocate events workqueue\n"); + status = -ENOMEM; goto error_pwrctrl_close; } - sched_set_fifo(device->events_worker->task); - /* This can return -EPROBE_DEFER */ status = kgsl_mmu_probe(device); if (status != 0) @@ -4562,8 +4558,10 @@ int kgsl_device_platform_probe(struct kgsl_device *device) return 0; error_pwrctrl_close: - if (!IS_ERR(device->events_worker)) - kthread_destroy_worker(device->events_worker); + if (device->events_wq) { + destroy_workqueue(device->events_wq); + device->events_wq = NULL; + } kgsl_pwrctrl_close(device); error: @@ -4573,7 +4571,10 @@ error: void kgsl_device_platform_remove(struct kgsl_device *device) { - kthread_destroy_worker(device->events_worker); + if (device->events_wq) { + destroy_workqueue(device->events_wq); + device->events_wq = NULL; + } kgsl_device_snapshot_close(device); diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h index e86051f9aa57..0f0721522574 100644 --- a/drivers/gpu/msm/kgsl.h +++ b/drivers/gpu/msm/kgsl.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __KGSL_H #define __KGSL_H @@ -295,7 +295,7 @@ typedef void (*kgsl_event_func)(struct kgsl_device *, struct kgsl_event_group *, * @priv: Private data passed to the callback function * @node: List node for the kgsl_event_group list * @created: Jiffies when the event was created - * @work: kthread_work struct for dispatching the callback + * @work: Work struct for dispatching the callback * @result: KGSL event result type to pass to the callback * group: The event group this event belongs to */ @@ -307,7 +307,7 @@ struct kgsl_event { void *priv; struct list_head node; unsigned int created; - struct kthread_work work; + struct work_struct work; int result; struct kgsl_event_group *group; }; @@ -473,8 +473,6 @@ void kgsl_mmu_remove_global(struct kgsl_device *device, struct kgsl_memdesc *memdesc); /* Helper functions */ -unsigned long kgsl_get_align(struct kgsl_memdesc *memdesc); - int kgsl_request_irq(struct platform_device *pdev, const char *name, irq_handler_t handler, void *data); diff --git a/drivers/gpu/msm/kgsl_debugfs.c b/drivers/gpu/msm/kgsl_debugfs.c index 1298f6247c9e..a90636a16f82 100644 --- a/drivers/gpu/msm/kgsl_debugfs.c +++ b/drivers/gpu/msm/kgsl_debugfs.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2002,2008-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -147,7 +146,7 @@ static const char *memtype_str(int memtype) static char get_alignflag(const struct kgsl_memdesc *m) { - u32 align = kgsl_memdesc_get_align(m); + int align = kgsl_memdesc_get_align(m); if (align >= ilog2(SZ_1M)) return 'L'; diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h index 0b4a6c01d1d0..3d3cfdab5128 100644 --- a/drivers/gpu/msm/kgsl_device.h +++ b/drivers/gpu/msm/kgsl_device.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __KGSL_DEVICE_H #define __KGSL_DEVICE_H @@ -294,7 +293,7 @@ struct kgsl_device { struct kgsl_pwrscale pwrscale; int reset_counter; /* Track how many GPU core resets have occurred */ - struct kthread_worker *events_worker; + struct workqueue_struct *events_wq; /* Number of active contexts seen globally for this device */ int active_context_count; diff --git a/drivers/gpu/msm/kgsl_events.c b/drivers/gpu/msm/kgsl_events.c index 674a3dc13e2c..891c662ea339 100644 --- a/drivers/gpu/msm/kgsl_events.c +++ b/drivers/gpu/msm/kgsl_events.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -22,17 +21,17 @@ static inline void signal_event(struct kgsl_device *device, { list_del(&event->node); event->result = result; - kthread_queue_work(device->events_worker, &event->work); + queue_work(device->events_wq, &event->work); } /** * _kgsl_event_worker() - Work handler for processing GPU event callbacks - * @work: Pointer to the kthread_work for the event + * @work: Pointer to the work_struct for the event * - * Each event callback has its own kthread_work struct and is run on a event specific - * worker thread. This is the worker that queues up the event callback function. + * Each event callback has its own work struct and is run on a event specific + * workqeuue. This is the worker that queues up the event callback function. */ -static void _kgsl_event_worker(struct kthread_work *work) +static void _kgsl_event_worker(struct work_struct *work) { struct kgsl_event *event = container_of(work, struct kgsl_event, work); int id = KGSL_CONTEXT_ID(event->context); @@ -269,7 +268,7 @@ int kgsl_add_event(struct kgsl_device *device, struct kgsl_event_group *group, event->created = jiffies; event->group = group; - kthread_init_work(&event->work, _kgsl_event_worker); + INIT_WORK(&event->work, _kgsl_event_worker); trace_kgsl_register_event(KGSL_CONTEXT_ID(context), timestamp, func); @@ -284,7 +283,7 @@ int kgsl_add_event(struct kgsl_device *device, struct kgsl_event_group *group, if (timestamp_cmp(retired, timestamp) >= 0) { event->result = KGSL_EVENT_RETIRED; - kthread_queue_work(device->events_worker, &event->work); + queue_work(device->events_wq, &event->work); spin_unlock(&group->lock); return 0; } diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c index 25a5750e452a..690ffe008811 100644 --- a/drivers/gpu/msm/kgsl_iommu.c +++ b/drivers/gpu/msm/kgsl_iommu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2229,7 +2229,8 @@ static int kgsl_iommu_get_gpuaddr(struct kgsl_pagetable *pagetable, size = kgsl_memdesc_footprint(memdesc); - align = kgsl_get_align(memdesc); + align = max_t(uint64_t, 1 << kgsl_memdesc_get_align(memdesc), + PAGE_SIZE); if (memdesc->flags & KGSL_MEMFLAGS_FORCE_32BIT) { start = pt->compat_va_start; diff --git a/drivers/gpu/msm/kgsl_sharedmem.h b/drivers/gpu/msm/kgsl_sharedmem.h index 1f55ffcfb265..389fd86078ff 100644 --- a/drivers/gpu/msm/kgsl_sharedmem.h +++ b/drivers/gpu/msm/kgsl_sharedmem.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef __KGSL_SHAREDMEM_H #define __KGSL_SHAREDMEM_H @@ -158,7 +157,7 @@ void kgsl_free_globals(struct kgsl_device *device); * * Returns the alignment requested, as power of 2 exponent. */ -static inline u32 +static inline int kgsl_memdesc_get_align(const struct kgsl_memdesc *memdesc) { return MEMFLAGS(memdesc->flags, KGSL_MEMALIGN_MASK, diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c index ac7dc35b1e89..477b082aa6a8 100644 --- a/drivers/hid/hid-logitech-hidpp.c +++ b/drivers/hid/hid-logitech-hidpp.c @@ -3743,12 +3743,10 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) if (hidpp->quirks & HIDPP_QUIRK_CLASS_G920) { ret = hidpp_ff_init(hidpp, &data); - if (ret) { + if (ret) hid_warn(hidpp->hid_dev, "Unable to initialize force feedback support, errno %d\n", ret); - ret = 0; - } } return ret; diff --git a/drivers/hid/hidraw.c b/drivers/hid/hidraw.c index 97a4eb4ca1fb..f8ef6268f3f2 100644 --- a/drivers/hid/hidraw.c +++ b/drivers/hid/hidraw.c @@ -472,7 +472,9 @@ static const struct file_operations hidraw_ops = { .release = hidraw_release, .unlocked_ioctl = hidraw_ioctl, .fasync = hidraw_fasync, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = hidraw_ioctl, +#endif .llseek = noop_llseek, }; diff --git a/drivers/hwtracing/coresight/coresight-byte-cntr.c b/drivers/hwtracing/coresight/coresight-byte-cntr.c index a58649c839dc..d85b769ea9ce 100644 --- a/drivers/hwtracing/coresight/coresight-byte-cntr.c +++ b/drivers/hwtracing/coresight/coresight-byte-cntr.c @@ -80,7 +80,7 @@ static ssize_t tmc_etr_byte_cntr_read(struct file *fp, char __user *data, size_t len, loff_t *ppos) { struct byte_cntr *byte_cntr_data = fp->private_data; - char *bufp = NULL; + char *bufp; int ret = 0; if (!data) return -EINVAL; diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 243a1600096a..485b2e6748c5 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -1612,7 +1612,7 @@ static const struct file_operations iio_buffer_fileops = { .owner = THIS_MODULE, .llseek = noop_llseek, .unlocked_ioctl = iio_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = iio_ioctl, }; static int iio_check_unique_scan_index(struct iio_dev *indio_dev) diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c index d46ea235c216..af6dedabd6a5 100644 --- a/drivers/infiniband/core/uverbs_main.c +++ b/drivers/infiniband/core/uverbs_main.c @@ -1135,7 +1135,7 @@ static const struct file_operations uverbs_fops = { .release = ib_uverbs_close, .llseek = no_llseek, .unlocked_ioctl = ib_uverbs_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = ib_uverbs_ioctl, }; static const struct file_operations uverbs_mmap_fops = { @@ -1146,7 +1146,7 @@ static const struct file_operations uverbs_mmap_fops = { .release = ib_uverbs_close, .llseek = no_llseek, .unlocked_ioctl = ib_uverbs_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = ib_uverbs_ioctl, }; static int ib_uverbs_get_nl_info(struct ib_device *ibdev, void *client_data, diff --git a/drivers/input/misc/ets_bix_mmi/etxxx_fp.c b/drivers/input/misc/ets_bix_mmi/etxxx_fp.c index e5caee6a476d..1384c113b690 100755 --- a/drivers/input/misc/ets_bix_mmi/etxxx_fp.c +++ b/drivers/input/misc/ets_bix_mmi/etxxx_fp.c @@ -1543,7 +1543,7 @@ egistec_probe_failed: return status; } -static int __init egisfp_init(void) +int __init egisfp_init(void) { int status; INFO_PRINT(" %s : module init \n", __func__); @@ -1556,7 +1556,7 @@ static int __init egisfp_init(void) INFO_PRINT(" %s : module init OK ! \n", __func__); return status; } -static void __exit egisfp_exit(void) +void __exit egisfp_exit(void) { INFO_PRINT("module exit \n"); platform_driver_unregister(&egisfp_driver); diff --git a/drivers/input/misc/rbs_fod_mmi/etxxx_fp.c b/drivers/input/misc/rbs_fod_mmi/etxxx_fp.c index fdee9e03ebc4..b4e4068acd8b 100644 --- a/drivers/input/misc/rbs_fod_mmi/etxxx_fp.c +++ b/drivers/input/misc/rbs_fod_mmi/etxxx_fp.c @@ -1473,7 +1473,7 @@ egistec_probe_failed: return status; } -static int __init egisfp_init(void) +int __init egisfp_init(void) { int status; INFO_PRINT(" %s : module init \n", __func__); @@ -1486,7 +1486,7 @@ static int __init egisfp_init(void) INFO_PRINT(" %s : module init OK ! \n", __func__); return status; } -static void __exit egisfp_exit(void) +void __exit egisfp_exit(void) { INFO_PRINT("module exit \n"); platform_driver_unregister(&egisfp_driver); diff --git a/drivers/input/misc/rbs_fps_mmi/etxxx_fp.c b/drivers/input/misc/rbs_fps_mmi/etxxx_fp.c index 9ca505d7575b..f75ffeedd2e3 100644 --- a/drivers/input/misc/rbs_fps_mmi/etxxx_fp.c +++ b/drivers/input/misc/rbs_fps_mmi/etxxx_fp.c @@ -1389,7 +1389,7 @@ egistec_probe_failed: return status; } -static int __init egisfp_init(void) +int __init egisfp_init(void) { int status; INFO_PRINT(" %s : module init \n", __func__); @@ -1402,7 +1402,7 @@ static int __init egisfp_init(void) INFO_PRINT(" %s : module init OK ! \n", __func__); return status; } -static void __exit egisfp_exit(void) +void __exit egisfp_exit(void) { INFO_PRINT("module exit \n"); platform_driver_unregister(&egisfp_driver); diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 6eaeaefb4e7f..7e234defdc6b 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -1333,8 +1333,6 @@ source "drivers/input/touchscreen/synaptics_dsx/Kconfig" source "drivers/input/touchscreen/nt36xxx/Kconfig" -source "drivers/input/touchscreen/chipone_tddi_mmi/Kconfig" - source "drivers/input/touchscreen/chipone_tddi_v2_mmi/Kconfig" source "drivers/input/touchscreen/focaltech_0flash_v2_mmi/Kconfig" diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index 5fb2875e98bd..32a9a17a8867 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -116,7 +116,6 @@ obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_TCM) += synaptics_tcm/ obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_DSX) += synaptics_dsx/ obj-$(CONFIG_TOUCHSCREEN_NT36XXX) += nt36xxx/ -obj-$(CONFIG_TOUCHSCREEN_CHIPONE_TDDI) += chipone_tddi_mmi/ obj-$(CONFIG_TOUCHSCREEN_CHIPONE_V2_MMI) += chipone_tddi_v2_mmi/ obj-$(CONFIG_TOUCHSCREEN_FTS_0FLASH_MMI_V2) += focaltech_0flash_v2_mmi/ obj-$(CONFIG_TOUCHSCREEN_FTS_V3) += focaltech_touch_v3/ diff --git a/drivers/input/touchscreen/chipone_tddi_mmi/Kbuild b/drivers/input/touchscreen/chipone_tddi_mmi/Kbuild index 4f6f559957d3..f6b80347f77f 100644 --- a/drivers/input/touchscreen/chipone_tddi_mmi/Kbuild +++ b/drivers/input/touchscreen/chipone_tddi_mmi/Kbuild @@ -1,6 +1,12 @@ -ccflags-$(CONFIG_TOUCHSCREEN_CHIPONE_TDDI_ESD) += -DCONFIG_CTS_ESD_PROTECTION +# add -Wall to try to catch everything we can. +EXTRA_CFLAGS += -Wall +EXTRA_CFLAGS += -I$(ANDROID_BUILD_TOP)/motorola/kernel/modules/include \ + -I$(ANDROID_BUILD_TOP)/motorola/kernel/modules/drivers/input/touchscreen/chipone_tddi_mmi +ifneq ($(filter m y,$(CONFIG_CHIPONE_ESD)),) +EXTRA_CFLAGS += -DCONFIG_CTS_ESD_PROTECTION +endif -obj-$(CONFIG_TOUCHSCREEN_CHIPONE_TDDI) := chipone_tddi_mmi.o +obj-m := chipone_tddi_mmi.o chipone_tddi_mmi-objs += cts_i2c_driver.o chipone_tddi_mmi-objs += cts_core.o diff --git a/drivers/input/touchscreen/chipone_tddi_mmi/Kconfig b/drivers/input/touchscreen/chipone_tddi_mmi/Kconfig deleted file mode 100644 index b9e57e39ea35..000000000000 --- a/drivers/input/touchscreen/chipone_tddi_mmi/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -config TOUCHSCREEN_CHIPONE_TDDI - tristate "CHIPONE TDDI Touchscreen" - default n - help - Say Y here if you have a Chipone flash touchscreen connected - to your system by SPI bus. - - If unsure, say N. - -config TOUCHSCREEN_CHIPONE_TDDI_ESD - bool "ESD Detection" - depends on TOUCHSCREEN_CHIPONE_TDDI - default n - help - Say Y here if you want to have ESD Detection support. - - If unsure, say N. diff --git a/drivers/input/touchscreen/touchscreen_mmi/touchscreen_mmi_notif.c b/drivers/input/touchscreen/touchscreen_mmi/touchscreen_mmi_notif.c index 4d4319bb175e..5caa363a95bc 100644 --- a/drivers/input/touchscreen/touchscreen_mmi/touchscreen_mmi_notif.c +++ b/drivers/input/touchscreen/touchscreen_mmi/touchscreen_mmi_notif.c @@ -187,17 +187,15 @@ static void ts_mmi_panel_cb(enum panel_event_notifier_tag tag, dev_dbg(DEV_MMI, "%s: %s Notify_type=%d, early=%d, ctrl_dsi=%d\n", __func__, EVENT_PRE_DISPLAY_OFF ? "EVENT_PRE_DISPLAY_OFF" : - (EVENT_DISPLAY_LP ? "EVENT_DISPLAY_LP" : (EVENT_DISPLAY_OFF ? "EVENT_DISPLAY_OFF" : (EVENT_PRE_DISPLAY_ON ? "EVENT_PRE_DISPLAY_ON" : - (EVENT_DISPLAY_ON ? "EVENT_DISPLAY_ON" : "Unknown")))), + (EVENT_DISPLAY_ON ? "EVENT_DISPLAY_ON" : "Unknown"))), event, (evdata.early_trigger ? 1 : 0), touch_cdev->pdata.ctrl_dsi); panel_event = EVENT_PRE_DISPLAY_OFF ? TS_MMI_EVENT_PRE_DISPLAY_OFF : - (EVENT_DISPLAY_LP ? TS_MMI_EVENT_PRE_DISPLAY_OFF : (EVENT_DISPLAY_OFF ? TS_MMI_EVENT_DISPLAY_OFF : (EVENT_PRE_DISPLAY_ON ? TS_MMI_EVENT_PRE_DISPLAY_ON : - (EVENT_DISPLAY_ON ? TS_MMI_EVENT_DISPLAY_ON : TS_MMI_EVENT_UNKNOWN)))); + (EVENT_DISPLAY_ON ? TS_MMI_EVENT_DISPLAY_ON : TS_MMI_EVENT_UNKNOWN))); ts_mmi_panel_event_handle(touch_cdev, panel_event); @@ -220,20 +218,18 @@ static int ts_mmi_panel_cb(struct notifier_block *nb, dev_dbg(DEV_MMI,"%s: %s event(%lu), ctrl_dsi=%d, idx=%d\n", __func__, EVENT_PRE_DISPLAY_OFF ? "EVENT_PRE_DISPLAY_OFF" : - (EVENT_DISPLAY_LP ? "EVENT_DISPLAY_LP" : (EVENT_DISPLAY_OFF ? "EVENT_DISPLAY_OFF" : (EVENT_PRE_DISPLAY_ON ? "EVENT_PRE_DISPLAY_ON" : - (EVENT_DISPLAY_ON ? "EVENT_DISPLAY_ON" : "Unknown")))), + (EVENT_DISPLAY_ON ? "EVENT_DISPLAY_ON" : "Unknown"))), event, touch_cdev->pdata.ctrl_dsi, idx); if (touch_cdev->pdata.ctrl_dsi != idx) return 0; panel_event = EVENT_PRE_DISPLAY_OFF ? TS_MMI_EVENT_PRE_DISPLAY_OFF : - (EVENT_DISPLAY_LP ? TS_MMI_EVENT_PRE_DISPLAY_OFF : (EVENT_DISPLAY_OFF ? TS_MMI_EVENT_DISPLAY_OFF : (EVENT_PRE_DISPLAY_ON ? TS_MMI_EVENT_PRE_DISPLAY_ON : - (EVENT_DISPLAY_ON ? TS_MMI_EVENT_DISPLAY_ON : TS_MMI_EVENT_UNKNOWN)))); + (EVENT_DISPLAY_ON ? TS_MMI_EVENT_DISPLAY_ON : TS_MMI_EVENT_UNKNOWN))); ret = ts_mmi_panel_event_handle(touch_cdev, panel_event); diff --git a/drivers/iommu/dma-mapping-fast.c b/drivers/iommu/dma-mapping-fast.c index 947ba3ca140d..3dbaef99d89c 100644 --- a/drivers/iommu/dma-mapping-fast.c +++ b/drivers/iommu/dma-mapping-fast.c @@ -244,12 +244,8 @@ static void fast_smmu_unmap_page(struct device *dev, dma_addr_t iova, } spin_lock_irqsave(&mapping->lock, flags); - - if (unlikely(!av8l_fast_unmap_public(mapping->pgtbl_ops, iova, len))) - goto fail; - + av8l_fast_unmap_public(mapping->pgtbl_ops, iova, len); __fast_smmu_free_iova(mapping, iova, len); -fail: spin_unlock_irqrestore(&mapping->lock, flags); trace_unmap(to_msm_iommu_domain(mapping->domain), iova - offset, len, @@ -389,8 +385,7 @@ static void fast_smmu_unmap_sg(struct device *dev, len = ALIGN(sg_dma_address(sg) + sg_dma_len(sg) - (start - offset), FAST_PAGE_SIZE); - if (unlikely(!av8l_fast_unmap_public(mapping->pgtbl_ops, start, len))) - return; + av8l_fast_unmap_public(mapping->pgtbl_ops, start, len); spin_lock_irqsave(&mapping->lock, flags); __fast_smmu_free_iova(mapping, start, len); @@ -658,10 +653,7 @@ static void fast_smmu_free(struct device *dev, size_t size, size = ALIGN(size, FAST_PAGE_SIZE); spin_lock_irqsave(&mapping->lock, flags); - - if (unlikely(!av8l_fast_unmap_public(mapping->pgtbl_ops, dma_handle, size))) - goto fail; - + av8l_fast_unmap_public(mapping->pgtbl_ops, dma_handle, size); __fast_smmu_free_iova(mapping, dma_handle, size); spin_unlock_irqrestore(&mapping->lock, flags); @@ -682,11 +674,6 @@ static void fast_smmu_free(struct device *dev, size_t size, if (page) dma_free_contiguous(dev, page, size); - - return; - -fail: - spin_unlock_irqrestore(&mapping->lock, flags); } static int fast_smmu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, diff --git a/drivers/iommu/io-pgtable-fast.c b/drivers/iommu/io-pgtable-fast.c index 67ca5c20c521..a9159c012106 100644 --- a/drivers/iommu/io-pgtable-fast.c +++ b/drivers/iommu/io-pgtable-fast.c @@ -127,14 +127,7 @@ #define PTE_SH_IDX(pte) (pte & AV8L_FAST_PTE_SH_MASK) -#define iopte_pmd_offset(pmds, base, iova) \ -({ \ - typeof(iova) __iova = (iova); \ - typeof(base) __base = (base); \ - typeof(pmds) __pmds = (pmds); \ - (__iova < __base) ? ERR_PTR(-EINVAL) : \ - __pmds + ((__iova - ALIGN_DOWN(__base, SZ_2M)) >> AV8L_FAST_PAGE_SHIFT); \ -}) +#define iopte_pmd_offset(pmds, base, iova) (pmds + ((iova - base) >> 12)) static inline dma_addr_t av8l_dma_addr(void *addr) { @@ -209,12 +202,6 @@ void av8l_fast_clear_stale_ptes(struct io_pgtable_ops *ops, u64 base, struct io_pgtable *iop = iof_pgtable_ops_to_pgtable(ops); av8l_fast_iopte *pmdp = iopte_pmd_offset(data->pmds, data->base, base); - if (IS_ERR(pmdp)) { - pr_err("Invalid iova : 0x%lx, as it is less than base : 0x%llx\n", - iova, data->base); - return; - } - for (i = base >> AV8L_FAST_PAGE_SHIFT; i <= (end >> AV8L_FAST_PAGE_SHIFT); ++i) { if (!(*pmdp & AV8L_FAST_PTE_VALID)) { @@ -267,12 +254,6 @@ static int av8l_fast_map(struct io_pgtable_ops *ops, unsigned long iova, unsigned long i, nptes = size >> AV8L_FAST_PAGE_SHIFT; av8l_fast_iopte pte; - if (IS_ERR(ptep)) { - pr_err("Invalid iova : 0x%lx, as it is less than base : 0x%llx\n", - iova, data->base); - return -EINVAL; - } - pte = av8l_fast_prot_to_pte(data, prot); paddr &= AV8L_FAST_PTE_ADDR_MASK; for (i = 0; i < nptes; i++, paddr += SZ_4K) { @@ -305,12 +286,6 @@ __av8l_fast_unmap(struct io_pgtable_ops *ops, unsigned long iova, ptep = iopte_pmd_offset(data->pmds, data->base, iova); nptes = size >> AV8L_FAST_PAGE_SHIFT; - if (IS_ERR(ptep)) { - pr_err("Invalid iova : 0x%lx, as it is less than base : 0x%llx\n", - iova, data->base); - return 0; - } - memset(ptep, val, sizeof(*ptep) * nptes); av8l_clean_range(&iop->cfg, ptep, ptep + nptes); if (!allow_stale_tlb) @@ -320,10 +295,10 @@ __av8l_fast_unmap(struct io_pgtable_ops *ops, unsigned long iova, } /* caller must take care of tlb cache maintenance */ -size_t av8l_fast_unmap_public(struct io_pgtable_ops *ops, unsigned long iova, +void av8l_fast_unmap_public(struct io_pgtable_ops *ops, unsigned long iova, size_t size) { - return __av8l_fast_unmap(ops, iova, size, true); + __av8l_fast_unmap(ops, iova, size, true); } static size_t av8l_fast_unmap(struct io_pgtable_ops *ops, unsigned long iova, @@ -408,12 +383,6 @@ static bool av8l_fast_iova_coherent(struct io_pgtable_ops *ops, struct av8l_fast_io_pgtable *data = iof_pgtable_ops_to_data(ops); av8l_fast_iopte *ptep = iopte_pmd_offset(data->pmds, data->base, iova); - if (IS_ERR(ptep)) { - pr_err("Invalid iova : 0x%lx, as it is less than base : 0x%llx\n", - iova, data->base); - return false; - } - return ((PTE_MAIR_IDX(*ptep) == AV8L_FAST_MAIR_ATTR_IDX_CACHE) && ((PTE_SH_IDX(*ptep) == AV8L_FAST_PTE_SH_OS) || (PTE_SH_IDX(*ptep) == AV8L_FAST_PTE_SH_IS))); diff --git a/drivers/media/platform/msm/cvp/cvp.c b/drivers/media/platform/msm/cvp/cvp.c index 76f7444a43b8..87adb4fbd975 100644 --- a/drivers/media/platform/msm/cvp/cvp.c +++ b/drivers/media/platform/msm/cvp/cvp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -135,8 +135,6 @@ static int msm_cvp_initialize_core(struct platform_device *pdev, INIT_LIST_HEAD(&core->instances); mutex_init(&core->lock); mutex_init(&core->clk_lock); - mutex_init(&core->idr_mtx); - idr_init(&core->sess_idr); core->state = CVP_CORE_UNINIT; for (i = SYS_MSG_INDEX(SYS_MSG_START); @@ -508,8 +506,6 @@ static int msm_cvp_remove(struct platform_device *pdev) msm_cvp_free_platform_resources(&core->resources); sysfs_remove_group(&pdev->dev.kobj, &msm_cvp_core_attr_group); dev_set_drvdata(&pdev->dev, NULL); - idr_destroy(&core->sess_idr); - mutex_destroy(&core->idr_mtx); mutex_destroy(&core->lock); mutex_destroy(&core->clk_lock); kfree(core); diff --git a/drivers/media/platform/msm/cvp/cvp_hfi.c b/drivers/media/platform/msm/cvp/cvp_hfi.c index df430d2235f7..22340456d275 100644 --- a/drivers/media/platform/msm/cvp/cvp_hfi.c +++ b/drivers/media/platform/msm/cvp/cvp_hfi.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -30,7 +29,6 @@ #include "cvp_hfi_helper.h" #include "cvp_hfi_io.h" #include "msm_cvp_dsp.h" -#include "msm_cvp.h" #define FIRMWARE_SIZE 0X00A00000 #define REG_ADDR_OFFSET_BITMASK 0x000FFFFF @@ -471,7 +469,6 @@ static int __dsp_suspend(struct iris_hfi_device *device, bool force, u32 flags) { int rc; struct cvp_hal_session *temp; - struct msm_cvp_inst *inst = NULL; if (msm_cvp_dsp_disable) return 0; @@ -483,10 +480,9 @@ static int __dsp_suspend(struct iris_hfi_device *device, bool force, u32 flags) /* don't suspend if cvp session is not paused */ if (!(temp->flags & SESSION_PAUSE)) { - inst = (struct msm_cvp_inst *)temp->session_id; dprintk(CVP_DSP, "%s: cvp session %x not paused\n", - __func__, inst->sess_id); + __func__, hash32_ptr(temp)); return -EBUSY; } } @@ -2228,17 +2224,12 @@ static void __session_clean(struct cvp_hal_session *session) { struct cvp_hal_session *temp, *next; struct iris_hfi_device *device; - struct msm_cvp_core *core = NULL; - struct msm_cvp_inst *inst = NULL; - void *tmp = NULL; if (!session || !session->device) { dprintk(CVP_WARN, "%s: invalid params\n", __func__); return; } device = session->device; - core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list); - inst = (struct msm_cvp_inst *) session->session_id; dprintk(CVP_SESS, "deleted the session: %pK\n", session); /* * session might have been removed from the device list in @@ -2250,13 +2241,6 @@ static void __session_clean(struct cvp_hal_session *session) break; } } - /* Remove the IDR id assigned to this session */ - mutex_lock(&core->idr_mtx); - tmp = idr_remove(&core->sess_idr, inst->sess_id); - if (tmp != session) - dprintk(CVP_WARN, "%s: session\n", __func__); - mutex_unlock(&core->idr_mtx); - /* Poison the session handle with zeros */ *session = (struct cvp_hal_session){ {0} }; kfree(session); @@ -2294,9 +2278,6 @@ static int iris_hfi_session_init(void *device, void *session_id, struct cvp_hfi_cmd_sys_session_init_packet pkt; struct iris_hfi_device *dev; struct cvp_hal_session *s; - struct msm_cvp_core *core; - struct msm_cvp_inst *inst; - int id = 0; if (!device || !new_session) { dprintk(CVP_ERR, "%s - invalid input\n", __func__); @@ -2304,8 +2285,6 @@ static int iris_hfi_session_init(void *device, void *session_id, } dev = device; - core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list); - inst = session_id; mutex_lock(&dev->lock); s = kzalloc(sizeof(*s), GFP_KERNEL); @@ -2316,35 +2295,15 @@ static int iris_hfi_session_init(void *device, void *session_id, s->session_id = session_id; s->device = dev; - - mutex_lock(&core->idr_mtx); - idr_preload(GFP_KERNEL); - - /* Need to think if we can use core->lock or dev->lock or need a - * different new lock for this? - */ - id = idr_alloc(&core->sess_idr, (void *)s, 0x7FFF0000, INT_MAX, GFP_NOWAIT); - idr_preload_end(); - mutex_unlock(&core->idr_mtx); - if (id < 0) { - dprintk(CVP_ERR, - "%s: idr allocation failed for session %pK of inst %pK\n", - __func__, s, session_id); - goto err_session_init_fail; - } - dprintk(CVP_SESS, - "%s: inst %pK, session %pK, idr_id = 0x%x\n", __func__, session_id, s, id); + "%s: inst %pK, session %pK\n", __func__, session_id, s); list_add_tail(&s->list, &dev->sess_head); __set_default_sys_properties(device); - inst->sess_id = id; - if (call_hfi_pkt_op(dev, session_init, &pkt, s)) { dprintk(CVP_ERR, "session_init: failed to create packet\n"); - inst->sess_id = 0x0000DEAD; goto err_session_init_fail; } @@ -2358,7 +2317,6 @@ static int iris_hfi_session_init(void *device, void *session_id, err_session_init_fail: if (s) __session_clean(s); - inst->sess_id = 0; *new_session = NULL; mutex_unlock(&dev->lock); return -EINVAL; @@ -2920,11 +2878,9 @@ static struct cvp_hal_session *__get_session(struct iris_hfi_device *device, u32 session_id) { struct cvp_hal_session *temp = NULL; - struct msm_cvp_inst *inst = NULL; list_for_each_entry(temp, &device->sess_head, list) { - inst = (struct msm_cvp_inst *)temp->session_id; - if (session_id == inst->sess_id) + if (session_id == hash32_ptr(temp)) return temp; } @@ -3103,7 +3059,6 @@ static int __response_handler(struct iris_hfi_device *device) /* Process the packet types that we're interested in */ process_system_msg(info, device, raw_packet); - /* This session_id is a double pointer to the idr_id of session */ session_id = get_session_id(info); /* * hfi_process_msg_packet provides a session_id that's a hashed @@ -3115,6 +3070,11 @@ static int __response_handler(struct iris_hfi_device *device) if (session_id) { struct cvp_hal_session *session = NULL; + if (upper_32_bits((uintptr_t)*session_id) != 0) { + dprintk(CVP_ERR, + "Upper 32-bits != 0 for sess_id=%pK\n", + *session_id); + } session = __get_session(device, (u32)(uintptr_t)*session_id); if (!session) { diff --git a/drivers/media/platform/msm/cvp/cvp_hfi_api.h b/drivers/media/platform/msm/cvp/cvp_hfi_api.h index 0606cbd865e1..0a5ae01af744 100644 --- a/drivers/media/platform/msm/cvp/cvp_hfi_api.h +++ b/drivers/media/platform/msm/cvp/cvp_hfi_api.h @@ -357,8 +357,10 @@ struct cvp_hfi_device { int (*validate_session)(void *sess, const char *func); }; -typedef void (*hfi_cmd_response_callback) (u32 cmd, void *data); -typedef void (*msm_cvp_callback) (u32 response, void *callback); +typedef void (*hfi_cmd_response_callback) (enum hal_command_response cmd, + void *data); +typedef void (*msm_cvp_callback) (enum hal_command_response response, + void *callback); struct cvp_hfi_device *cvp_hfi_initialize(enum msm_cvp_hfi_type hfi_type, u32 device_id, struct msm_cvp_platform_resources *res, diff --git a/drivers/media/platform/msm/cvp/hfi_packetization.c b/drivers/media/platform/msm/cvp/hfi_packetization.c index edb6caaf1d34..107e2d744fff 100644 --- a/drivers/media/platform/msm/cvp/hfi_packetization.c +++ b/drivers/media/platform/msm/cvp/hfi_packetization.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include "hfi_packetization.h" @@ -209,7 +208,7 @@ inline int cvp_create_pkt_cmd_sys_session_init( pkt->size = sizeof(struct cvp_hfi_cmd_sys_session_init_packet); pkt->packet_type = HFI_CMD_SYS_SESSION_INIT; - pkt->session_id = inst->sess_id; + pkt->session_id = hash32_ptr(session); pkt->session_type = inst->prop.type; pkt->session_kmask = inst->prop.kernel_mask; pkt->session_prio = inst->prop.priority; @@ -267,14 +266,13 @@ int cvp_create_pkt_cmd_session_cmd(struct cvp_hal_session_cmd_pkt *pkt, int pkt_type, struct cvp_hal_session *session) { int rc = 0; - struct msm_cvp_inst *inst = session->session_id; if (!pkt) return -EINVAL; pkt->size = sizeof(struct cvp_hal_session_cmd_pkt); pkt->packet_type = pkt_type; - pkt->session_id = inst->sess_id; + pkt->session_id = hash32_ptr(session); return rc; } @@ -307,14 +305,13 @@ int cvp_create_pkt_cmd_session_set_buffers( { int rc = 0; struct cvp_hfi_cmd_session_set_buffers_packet *pkt; - struct msm_cvp_inst *inst = session->session_id; - if (!cmd || !session || !inst) + if (!cmd || !session) return -EINVAL; pkt = (struct cvp_hfi_cmd_session_set_buffers_packet *)cmd; pkt->packet_type = HFI_CMD_SESSION_CVP_SET_BUFFERS; - pkt->session_id = inst->sess_id; + pkt->session_id = hash32_ptr(session); pkt->buf_type.iova = iova; pkt->buf_type.size = size; pkt->size = sizeof(struct cvp_hfi_cmd_session_set_buffers_packet); @@ -327,14 +324,13 @@ int cvp_create_pkt_cmd_session_release_buffers( struct cvp_hal_session *session) { struct cvp_session_release_buffers_packet *pkt; - struct msm_cvp_inst *inst = session->session_id; - if (!cmd || !session || !inst) + if (!cmd || !session) return -EINVAL; pkt = (struct cvp_session_release_buffers_packet *)cmd; pkt->packet_type = HFI_CMD_SESSION_CVP_RELEASE_BUFFERS; - pkt->session_id = inst->sess_id; + pkt->session_id = hash32_ptr(session); pkt->num_buffers = 1; pkt->buffer_type = 0; pkt->size = sizeof(struct cvp_session_release_buffers_packet) + @@ -351,7 +347,6 @@ int cvp_create_pkt_cmd_session_send( int def_idx; struct cvp_hal_session_cmd_pkt *ptr = (struct cvp_hal_session_cmd_pkt *)in_pkt; - struct msm_cvp_inst *inst = session->session_id; if (!out_pkt || !in_pkt || !session) return -EINVAL; @@ -359,7 +354,7 @@ int cvp_create_pkt_cmd_session_send( if (ptr->size > MAX_HFI_PKT_SIZE * sizeof(unsigned int)) goto error_hfi_packet; - if (ptr->session_id != inst->sess_id) + if (ptr->session_id != hash32_ptr(session)) goto error_hfi_packet; def_idx = get_pkt_index(ptr); diff --git a/drivers/media/platform/msm/cvp/hfi_response_handler.c b/drivers/media/platform/msm/cvp/hfi_response_handler.c index 3e0d3b717dc1..61a5aadbe34a 100644 --- a/drivers/media/platform/msm/cvp/hfi_response_handler.c +++ b/drivers/media/platform/msm/cvp/hfi_response_handler.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -462,7 +462,7 @@ static struct msm_cvp_inst *cvp_get_inst_from_id(struct msm_cvp_core *core, retry: if (mutex_trylock(&core->lock)) { list_for_each_entry(inst, &core->instances, list) { - if (inst->sess_id == session_id) { + if (hash32_ptr(inst->session) == session_id) { match = true; break; } diff --git a/drivers/media/platform/msm/cvp/msm_cvp.c b/drivers/media/platform/msm/cvp/msm_cvp.c index 346f21641519..fefc06d6aee2 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp.c +++ b/drivers/media/platform/msm/cvp/msm_cvp.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include "msm_cvp.h" @@ -15,47 +14,6 @@ struct cvp_power_level { unsigned long bw_sum; }; -void *get_sessObj_from_idr(struct msm_cvp_inst *inst) -{ - void *sessObj = NULL; - struct msm_cvp_core *core = NULL; - - if (!inst || !inst->core) { - dprintk(CVP_ERR, "%s: invalid params\n", __func__); - return NULL; - } - - core = inst->core; - mutex_lock(&core->idr_mtx); - sessObj = idr_find(&core->sess_idr, inst->sess_id); - mutex_unlock(&core->idr_mtx); - if (!sessObj) - dprintk(CVP_ERR, "%s: Could not find the sess obj for given idr id\n", - __func__); - - return sessObj; -} - -u32 get_sessId_from_idr(void *session) -{ - void *ptr = NULL; - u32 sess_id = -1; - struct msm_cvp_core *core = NULL; - - core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list); - if (!session || !core) - return -EINVAL; - mutex_lock(&core->idr_mtx); - idr_for_each_entry(&core->sess_idr, ptr, sess_id) { - if (ptr == session) { - mutex_unlock(&core->idr_mtx); - return sess_id; - } - } - mutex_unlock(&core->idr_mtx); - return sess_id; -} - static int msm_cvp_get_session_info(struct msm_cvp_inst *inst, struct cvp_kmd_session_info *session) { @@ -72,7 +30,7 @@ static int msm_cvp_get_session_info(struct msm_cvp_inst *inst, return -ECONNRESET; s->cur_cmd_type = CVP_KMD_GET_SESSION_INFO; - session->session_id = inst->sess_id; + session->session_id = hash32_ptr(inst->session); dprintk(CVP_SESS, "%s: id 0x%x\n", __func__, session->session_id); s->cur_cmd_type = 0; @@ -741,13 +699,6 @@ static int msm_cvp_session_process_hfi_fence(struct msm_cvp_inst *inst, f->output_index = kfc->output_index; } - if (f->num_fences >= (MAX_HFI_FENCE_SIZE / 2)) { - dprintk(CVP_ERR, "%s: Max number of fences exceeded! Max number supported: %d", - __func__, (MAX_HFI_FENCE_SIZE / 2)); - cvp_free_fence_data(f); - msm_cvp_unmap_frame(inst, pkt->client_data.kdata); - goto exit; - } dprintk(CVP_SYNX, "%s: frameID %llu ktid %llu\n", __func__, f->frame_id, pkt->client_data.kdata); @@ -1276,7 +1227,7 @@ static int msm_cvp_session_stop(struct msm_cvp_inst *inst, sq->state = QUEUE_STOP; pr_info(CVP_DBG_TAG "Stop session: %pK session_id = %d\n", - "sess", inst, inst->sess_id); + "sess", inst, hash32_ptr(inst->session)); spin_unlock(&sq->lock); wake_up_all(&inst->session_queue.wq); @@ -1300,7 +1251,7 @@ int msm_cvp_session_queue_stop(struct msm_cvp_inst *inst) sq->state = QUEUE_STOP; dprintk(CVP_SESS, "Stop session queue: %pK session_id = %d\n", - inst, inst->sess_id); + inst, hash32_ptr(inst->session)); spin_unlock(&sq->lock); wake_up_all(&inst->session_queue.wq); @@ -1600,7 +1551,7 @@ static void cvp_clean_fence_queue(struct msm_cvp_inst *inst, int synx_state) ktid = f->pkt->client_data.kdata & (FENCE_BIT - 1); dprintk(CVP_SYNX, "%s: (%#x) flush frame %llu %llu wait_list\n", - __func__, inst->sess_id, ktid, f->frame_id); + __func__, hash32_ptr(inst->session), ktid, f->frame_id); list_del_init(&f->list); msm_cvp_unmap_frame(inst, f->pkt->client_data.kdata); @@ -1613,7 +1564,7 @@ static void cvp_clean_fence_queue(struct msm_cvp_inst *inst, int synx_state) ktid = f->pkt->client_data.kdata & (FENCE_BIT - 1); dprintk(CVP_SYNX, "%s: (%#x)flush frame %llu %llu sched_list\n", - __func__, inst->sess_id, ktid, f->frame_id); + __func__, hash32_ptr(inst->session), ktid, f->frame_id); cvp_cancel_synx(inst, CVP_INPUT_SYNX, f, synx_state); } @@ -1661,14 +1612,14 @@ static int cvp_flush_all(struct msm_cvp_inst *inst) return -ECONNRESET; dprintk(CVP_SESS, "session %llx (%#x)flush all starts\n", - inst, inst->sess_id); + inst, hash32_ptr(inst->session)); q = &inst->fence_cmd_queue; hdev = inst->core->device; cvp_clean_fence_queue(inst, SYNX_STATE_SIGNALED_CANCEL); dprintk(CVP_SESS, "%s: (%#x) send flush to fw\n", - __func__, inst->sess_id); + __func__, hash32_ptr(inst->session)); /* Send flush to FW */ rc = call_hfi_op(hdev, session_flush, (void *)inst->session); @@ -1685,7 +1636,7 @@ static int cvp_flush_all(struct msm_cvp_inst *inst) __func__, rc); dprintk(CVP_SESS, "%s: (%#x) received flush from fw\n", - __func__, inst->sess_id); + __func__, hash32_ptr(inst->session)); exit: rc = cvp_drain_fence_sched_list(inst); @@ -1908,10 +1859,10 @@ int msm_cvp_session_deinit(struct msm_cvp_inst *inst) return -EINVAL; } dprintk(CVP_SESS, "%s: inst %pK (%#x)\n", __func__, - inst, inst->sess_id); + inst, hash32_ptr(inst->session)); - session = (struct cvp_hal_session *)get_sessObj_from_idr(inst); - if (!session || session != inst->session) + session = (struct cvp_hal_session *)inst->session; + if (!session) return rc; rc = msm_cvp_comm_try_state(inst, MSM_CVP_CLOSE_DONE); @@ -1932,7 +1883,7 @@ int msm_cvp_session_init(struct msm_cvp_inst *inst) } dprintk(CVP_SESS, "%s: inst %pK (%#x)\n", __func__, - inst, inst->sess_id); + inst, hash32_ptr(inst->session)); /* set default frequency */ inst->clk_data.core_id = 0; diff --git a/drivers/media/platform/msm/cvp/msm_cvp.h b/drivers/media/platform/msm/cvp/msm_cvp.h index b8ae6068de35..b21864b46f1c 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp.h +++ b/drivers/media/platform/msm/cvp/msm_cvp.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef _MSM_CVP_H_ @@ -35,6 +34,4 @@ int msm_cvp_session_init(struct msm_cvp_inst *inst); int msm_cvp_session_deinit(struct msm_cvp_inst *inst); int msm_cvp_session_queue_stop(struct msm_cvp_inst *inst); int cvp_stop_clean_fence_queue(struct msm_cvp_inst *inst); -void *get_sessObj_from_idr(struct msm_cvp_inst *inst); -u32 get_sessId_from_idr(void *session); #endif diff --git a/drivers/media/platform/msm/cvp/msm_cvp_buf.c b/drivers/media/platform/msm/cvp/msm_cvp_buf.c index c16eed33efd3..995c111edb7d 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp_buf.c +++ b/drivers/media/platform/msm/cvp/msm_cvp_buf.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "msm_cvp_common.h" @@ -14,7 +14,7 @@ do { \ clear_bit(idx, &inst->dma_cache.usage_bitmap); \ dprintk(CVP_MEM, "clear %x bit %d dma_cache bitmap 0x%llx\n", \ - inst->sess_id, smem->bitmap_index, \ + hash32_ptr(inst->session), smem->bitmap_index, \ inst->dma_cache.usage_bitmap); \ } while (0) @@ -22,7 +22,7 @@ do { \ set_bit(idx, &inst->dma_cache.usage_bitmap); \ dprintk(CVP_MEM, "Set %x bit %d dma_cache bitmap 0x%llx\n", \ - inst->sess_id, idx, \ + hash32_ptr(inst->session), idx, \ inst->dma_cache.usage_bitmap); \ } while (0) @@ -36,7 +36,7 @@ void print_smem(u32 tag, const char *str, struct msm_cvp_inst *inst, if (smem->dma_buf) { dprintk(tag, "%s: %x : %s size %d flags %#x iova %#x idx %d ref %d", - str, inst->sess_id, smem->dma_buf->name, + str, hash32_ptr(inst->session), smem->dma_buf->name, smem->size, smem->flags, smem->device_addr, smem->bitmap_index, smem->refcount); } @@ -51,13 +51,13 @@ static void print_internal_buffer(u32 tag, const char *str, if (cbuf->smem->dma_buf) { dprintk(tag, "%s: %x : fd %d off %d %s size %d iova %#x", - str, inst->sess_id, cbuf->fd, + str, hash32_ptr(inst->session), cbuf->fd, cbuf->offset, cbuf->smem->dma_buf->name, cbuf->size, cbuf->smem->device_addr); } else { dprintk(tag, "%s: %x : idx %2d fd %d off %d size %d iova %#x", - str, inst->sess_id, cbuf->fd, + str, hash32_ptr(inst->session), cbuf->fd, cbuf->offset, cbuf->size, cbuf->smem->device_addr); } } @@ -77,7 +77,7 @@ void print_client_buffer(u32 tag, const char *str, dprintk(tag, "%s: %x : idx %2d fd %d off %d size %d type %d flags 0x%x\n", - str, inst->sess_id, cbuf->index, cbuf->fd, + str, hash32_ptr(inst->session), cbuf->index, cbuf->fd, cbuf->offset, cbuf->size, cbuf->type, cbuf->flags); } @@ -154,7 +154,7 @@ int msm_cvp_map_buf_dsp(struct msm_cvp_inst *inst, struct cvp_kmd_buffer *buf) } if (buf->index) { - rc = cvp_dsp_register_buffer(inst->sess_id, buf->fd, + rc = cvp_dsp_register_buffer(hash32_ptr(session), buf->fd, smem->dma_buf->size, buf->size, buf->offset, buf->index, (uint32_t)smem->device_addr); if (rc) { @@ -227,7 +227,7 @@ int msm_cvp_unmap_buf_dsp(struct msm_cvp_inst *inst, struct cvp_kmd_buffer *buf) } if (buf->index) { - rc = cvp_dsp_deregister_buffer(inst->sess_id, buf->fd, + rc = cvp_dsp_deregister_buffer(hash32_ptr(session), buf->fd, cbuf->smem->dma_buf->size, buf->size, buf->offset, buf->index, (uint32_t)cbuf->smem->device_addr); if (rc) { @@ -545,7 +545,7 @@ void msm_cvp_unmap_frame(struct msm_cvp_inst *inst, u64 ktid) ktid &= (FENCE_BIT - 1); dprintk(CVP_MEM, "%s: (%#x) unmap frame %llu\n", - __func__, inst->sess_id, ktid); + __func__, hash32_ptr(inst->session), ktid); found = false; mutex_lock(&inst->frames.lock); @@ -587,7 +587,7 @@ int msm_cvp_unmap_user_persist(struct msm_cvp_inst *inst, smem = pbuf->smem; dprintk(CVP_MEM, "unmap persist: %x %d %d %#x", - inst->sess_id, pbuf->fd, + hash32_ptr(inst->session), pbuf->fd, pbuf->size, smem->device_addr); if (smem->bitmap_index >= MAX_DMABUF_NUMS) { @@ -785,7 +785,7 @@ int msm_cvp_session_deinit_buffers(struct msm_cvp_inst *inst) list_for_each_entry_safe(cbuf, dummy, &inst->cvpdspbufs.list, list) { print_internal_buffer(CVP_MEM, "remove dspbufs", inst, cbuf); - rc = cvp_dsp_deregister_buffer(inst->sess_id, + rc = cvp_dsp_deregister_buffer(hash32_ptr(session), cbuf->fd, cbuf->smem->dma_buf->size, cbuf->size, cbuf->offset, cbuf->index, (uint32_t)cbuf->smem->device_addr); @@ -955,7 +955,7 @@ int cvp_release_arp_buffers(struct msm_cvp_inst *inst) if (buf->ownership == DRIVER) { dprintk(CVP_MEM, "%s: %x : fd %d %s size %d", - "free arp", inst->sess_id, buf->fd, + "free arp", hash32_ptr(inst->session), buf->fd, smem->dma_buf->name, buf->size); msm_cvp_smem_free(smem); kmem_cache_free(cvp_driver->smem_cache, smem); diff --git a/drivers/media/platform/msm/cvp/msm_cvp_common.c b/drivers/media/platform/msm/cvp/msm_cvp_common.c index 75c9fe378f7b..69787e51cc3d 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp_common.c +++ b/drivers/media/platform/msm/cvp/msm_cvp_common.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -196,31 +195,23 @@ struct msm_cvp_inst *cvp_get_inst_validate(struct msm_cvp_core *core, { int rc = 0; struct cvp_hfi_device *hdev; - struct msm_cvp_inst *inst; - void *sessObj = NULL; + struct msm_cvp_inst *s; - inst = cvp_get_inst(core, session_id); - if (!inst) { - dprintk(CVP_ERR, "%s Inst doesn't exit\n", + s = cvp_get_inst(core, session_id); + if (!s) { + dprintk(CVP_ERR, "%s session doesn't exit\n", __builtin_return_address(0)); return NULL; } - sessObj = get_sessObj_from_idr(inst); - if (!sessObj || sessObj != inst->session) { - dprintk(CVP_ERR, - "Either sessionObj is null or not matching with inst->session\n"); - return NULL; - } - - hdev = inst->core->device; - rc = call_hfi_op(hdev, validate_session, sessObj, __func__); + hdev = s->core->device; + rc = call_hfi_op(hdev, validate_session, s->session, __func__); if (rc) { - cvp_put_inst(inst); - inst = NULL; + cvp_put_inst(s); + s = NULL; } - return inst; + return s; } static void cvp_handle_session_cmd_done(enum hal_command_response cmd, @@ -495,7 +486,7 @@ static void handle_session_init_done(enum hal_command_response cmd, void *data) } dprintk(CVP_SESS, "%s: cvp session %#x\n", __func__, - inst->sess_id); + hash32_ptr(inst->session)); signal_session_msg_receipt(cmd, inst); cvp_put_inst(inst); @@ -577,7 +568,7 @@ static void handle_session_error(enum hal_command_response cmd, void *data) hdev = inst->core->device; dprintk(CVP_ERR, "Session error received for inst %pK session %x\n", - inst, inst->sess_id); + inst, hash32_ptr(inst->session)); if (response->status == CVP_ERR_MAX_CLIENTS) { dprintk(CVP_WARN, "Too many clients, rejecting %pK", inst); @@ -767,7 +758,7 @@ static void handle_session_close(enum hal_command_response cmd, void *data) cvp_put_inst(inst); } -void cvp_handle_cmd_response(u32 cmd, void *data) +void cvp_handle_cmd_response(enum hal_command_response cmd, void *data) { dprintk(CVP_HFI, "Command response = %d\n", cmd); switch (cmd) { @@ -910,7 +901,7 @@ static int msm_comm_session_abort(struct msm_cvp_inst *inst) abort_completion = SESSION_MSG_INDEX(HAL_SESSION_ABORT_DONE); dprintk(CVP_WARN, "%s: inst %pK session %x\n", __func__, - inst, inst->sess_id); + inst, hash32_ptr(inst->session)); rc = call_hfi_op(hdev, session_abort, (void *)inst->session); if (rc) { dprintk(CVP_ERR, @@ -923,7 +914,7 @@ static int msm_comm_session_abort(struct msm_cvp_inst *inst) inst->core->resources.msm_cvp_hw_rsp_timeout)); if (!rc) { dprintk(CVP_ERR, "%s: inst %pK session %x abort timed out\n", - __func__, inst, inst->sess_id); + __func__, inst, hash32_ptr(inst->session)); call_hfi_op(hdev, flush_debug_queue, hdev->hfi_device_data); dump_hfi_queue(hdev->hfi_device_data); msm_cvp_comm_generate_sys_error(inst); @@ -1277,7 +1268,7 @@ int msm_cvp_comm_try_state(struct msm_cvp_inst *inst, int state) } dprintk(CVP_SESS, "Trying to move inst: %pK (%#x) from: %#x to %#x\n", - inst, inst->sess_id, inst->state, state); + inst, hash32_ptr(inst->session), inst->state, state); mutex_lock(&inst->sync_lock); if (inst->state == MSM_CVP_CORE_INVALID) { @@ -1290,7 +1281,7 @@ int msm_cvp_comm_try_state(struct msm_cvp_inst *inst, int state) flipped_state = get_flipped_state(inst->state, state); dprintk(CVP_SESS, "inst: %pK (%#x) flipped_state = %#x %x\n", - inst, inst->sess_id, flipped_state, state); + inst, hash32_ptr(inst->session), flipped_state, state); switch (flipped_state) { case MSM_CVP_CORE_UNINIT_DONE: case MSM_CVP_CORE_INIT: @@ -1500,7 +1491,7 @@ int msm_cvp_comm_kill_session(struct msm_cvp_inst *inst) return 0; } dprintk(CVP_WARN, "%s: inst %pK, session %x state %d\n", __func__, - inst, inst->sess_id, inst->state); + inst, hash32_ptr(inst->session), inst->state); /* * We're internally forcibly killing the session, if fw is aware of * the session send session_abort to firmware to clean up and release @@ -1512,7 +1503,7 @@ int msm_cvp_comm_kill_session(struct msm_cvp_inst *inst) if (rc) { dprintk(CVP_ERR, "%s: inst %pK session %x abort failed\n", - __func__, inst, inst->sess_id); + __func__, inst, hash32_ptr(inst->session)); change_cvp_inst_state(inst, MSM_CVP_CORE_INVALID); } else { change_cvp_inst_state(inst, MSM_CVP_CORE_UNINIT); diff --git a/drivers/media/platform/msm/cvp/msm_cvp_core.c b/drivers/media/platform/msm/cvp/msm_cvp_core.c index b98d43730988..5347eade1782 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp_core.c +++ b/drivers/media/platform/msm/cvp/msm_cvp_core.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -166,7 +165,7 @@ void *msm_cvp_open(int core_id, int session_type) list_for_each_entry(inst, &core->instances, list) dprintk(CVP_ERR, "inst %pK, cmd %d id %d\n", inst, inst->cur_cmd_type, - inst->sess_id); + hash32_ptr(inst->session)); mutex_unlock(&core->lock); return NULL; @@ -370,7 +369,7 @@ int msm_cvp_destroy(struct msm_cvp_inst *inst) synx_uninitialize(inst->synx_session_id); pr_info(CVP_DBG_TAG "Closed cvp instance: %pK session_id = %d\n", - "sess", inst, inst->sess_id); + "sess", inst, hash32_ptr(inst->session)); if (inst->cur_cmd_type) dprintk(CVP_ERR, "deleted instance has pending cmd %d\n", inst->cur_cmd_type); diff --git a/drivers/media/platform/msm/cvp/msm_cvp_internal.h b/drivers/media/platform/msm/cvp/msm_cvp_internal.h index 8bd02fce164e..533e16cfce56 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp_internal.h +++ b/drivers/media/platform/msm/cvp/msm_cvp_internal.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef _MSM_CVP_INTERNAL_H_ @@ -291,8 +290,6 @@ struct msm_cvp_core { unsigned long curr_freq; struct cvp_cycle_info dyn_clk; atomic64_t kernel_trans_id; - struct idr sess_idr; - struct mutex idr_mtx; }; struct msm_cvp_inst { @@ -304,7 +301,6 @@ struct msm_cvp_inst { struct cvp_session_queue session_queue_fence; struct cvp_session_event event_handler; void *session; - u32 sess_id; enum instance_state state; struct msm_cvp_list freqs; struct msm_cvp_list persistbufs; @@ -326,7 +322,7 @@ struct msm_cvp_inst { extern struct msm_cvp_drv *cvp_driver; -void cvp_handle_cmd_response(u32 cmd, void *data); +void cvp_handle_cmd_response(enum hal_command_response cmd, void *data); int msm_cvp_trigger_ssr(struct msm_cvp_core *core, enum hal_ssr_trigger_type type); int msm_cvp_noc_error_info(struct msm_cvp_core *core); diff --git a/drivers/media/platform/msm/cvp/msm_cvp_synx.c b/drivers/media/platform/msm/cvp/msm_cvp_synx.c index 4580c582174b..f70fb4013058 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp_synx.c +++ b/drivers/media/platform/msm/cvp/msm_cvp_synx.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include "msm_cvp_common.h" @@ -21,7 +20,7 @@ void cvp_dump_fence_queue(struct msm_cvp_inst *inst) ssid = inst->synx_session_id; mutex_lock(&q->lock); dprintk(CVP_WARN, "inst %x fence q mode %d, ssid %d\n", - inst->sess_id, q->mode, ssid.client_id); + hash32_ptr(inst->session), q->mode, ssid.client_id); dprintk(CVP_WARN, "fence cmdq wait list:\n"); list_for_each_entry(f, &q->wait_list, list) { diff --git a/drivers/media/platform/qcom/venus/hfi_msgs.c b/drivers/media/platform/qcom/venus/hfi_msgs.c index 990c53398b9b..5694d18b43d5 100644 --- a/drivers/media/platform/qcom/venus/hfi_msgs.c +++ b/drivers/media/platform/qcom/venus/hfi_msgs.c @@ -27,10 +27,8 @@ static void event_seq_changed(struct venus_core *core, struct venus_inst *inst, struct hfi_colour_space *colour_info; struct hfi_buffer_requirements *bufreq; struct hfi_extradata_input_crop *crop; - struct hfi_dpb_counts *dpb_count; - u32 ptype, rem_bytes; - u32 size_read = 0; u8 *data_ptr; + u32 ptype; inst->error = HFI_ERR_NONE; @@ -40,120 +38,80 @@ static void event_seq_changed(struct venus_core *core, struct venus_inst *inst, break; default: inst->error = HFI_ERR_SESSION_INVALID_PARAMETER; - inst->ops->event_notify(inst, EVT_SYS_EVENT_CHANGE, &event); - return; + goto done; } event.event_type = pkt->event_data1; num_properties_changed = pkt->event_data2; - if (!num_properties_changed) - goto error; + if (!num_properties_changed) { + inst->error = HFI_ERR_SESSION_INSUFFICIENT_RESOURCES; + goto done; + } data_ptr = (u8 *)&pkt->ext_event_data[0]; - rem_bytes = pkt->shdr.hdr.size - sizeof(*pkt); - do { - if (rem_bytes < sizeof(u32)) - goto error; ptype = *((u32 *)data_ptr); - - data_ptr += sizeof(u32); - rem_bytes -= sizeof(u32); - switch (ptype) { case HFI_PROPERTY_PARAM_FRAME_SIZE: - if (rem_bytes < sizeof(struct hfi_framesize)) - goto error; - + data_ptr += sizeof(u32); frame_sz = (struct hfi_framesize *)data_ptr; event.width = frame_sz->width; event.height = frame_sz->height; - size_read = sizeof(struct hfi_framesize); + data_ptr += sizeof(*frame_sz); break; case HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT: - if (rem_bytes < sizeof(struct hfi_profile_level)) - goto error; - + data_ptr += sizeof(u32); profile_level = (struct hfi_profile_level *)data_ptr; event.profile = profile_level->profile; event.level = profile_level->level; - size_read = sizeof(struct hfi_profile_level); + data_ptr += sizeof(*profile_level); break; case HFI_PROPERTY_PARAM_VDEC_PIXEL_BITDEPTH: - if (rem_bytes < sizeof(struct hfi_bit_depth)) - goto error; - + data_ptr += sizeof(u32); pixel_depth = (struct hfi_bit_depth *)data_ptr; event.bit_depth = pixel_depth->bit_depth; - size_read = sizeof(struct hfi_bit_depth); + data_ptr += sizeof(*pixel_depth); break; case HFI_PROPERTY_PARAM_VDEC_PIC_STRUCT: - if (rem_bytes < sizeof(struct hfi_pic_struct)) - goto error; - + data_ptr += sizeof(u32); pic_struct = (struct hfi_pic_struct *)data_ptr; event.pic_struct = pic_struct->progressive_only; - size_read = sizeof(struct hfi_pic_struct); + data_ptr += sizeof(*pic_struct); break; case HFI_PROPERTY_PARAM_VDEC_COLOUR_SPACE: - if (rem_bytes < sizeof(struct hfi_colour_space)) - goto error; - + data_ptr += sizeof(u32); colour_info = (struct hfi_colour_space *)data_ptr; event.colour_space = colour_info->colour_space; - size_read = sizeof(struct hfi_colour_space); + data_ptr += sizeof(*colour_info); break; case HFI_PROPERTY_CONFIG_VDEC_ENTROPY: - if (rem_bytes < sizeof(u32)) - goto error; - + data_ptr += sizeof(u32); event.entropy_mode = *(u32 *)data_ptr; - size_read = sizeof(u32); + data_ptr += sizeof(u32); break; case HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS: - if (rem_bytes < sizeof(struct hfi_buffer_requirements)) - goto error; - + data_ptr += sizeof(u32); bufreq = (struct hfi_buffer_requirements *)data_ptr; event.buf_count = HFI_BUFREQ_COUNT_MIN(bufreq, ver); data_ptr += sizeof(*bufreq); - event.buf_count = hfi_bufreq_get_count_min(bufreq, ver); - size_read = sizeof(struct hfi_buffer_requirements); break; case HFI_INDEX_EXTRADATA_INPUT_CROP: - if (rem_bytes < sizeof(struct hfi_extradata_input_crop)) - goto error; - + data_ptr += sizeof(u32); crop = (struct hfi_extradata_input_crop *)data_ptr; event.input_crop.left = crop->left; event.input_crop.top = crop->top; event.input_crop.width = crop->width; event.input_crop.height = crop->height; - size_read = sizeof(struct hfi_extradata_input_crop); - break; - case HFI_PROPERTY_PARAM_VDEC_DPB_COUNTS: - if (rem_bytes < sizeof(struct hfi_dpb_counts)) - goto error; - - dpb_count = (struct hfi_dpb_counts *)data_ptr; - event.buf_count = dpb_count->fw_min_cnt; - size_read = sizeof(struct hfi_dpb_counts); + data_ptr += sizeof(*crop); break; default: - size_read = 0; break; } - data_ptr += size_read; - rem_bytes -= size_read; num_properties_changed--; } while (num_properties_changed > 0); - inst->ops->event_notify(inst, EVT_SYS_EVENT_CHANGE, &event); - return; - -error: - inst->error = HFI_ERR_SESSION_INSUFFICIENT_RESOURCES; +done: inst->ops->event_notify(inst, EVT_SYS_EVENT_CHANGE, &event); } diff --git a/drivers/media/rc/lirc_dev.c b/drivers/media/rc/lirc_dev.c index 1d554bba567e..aeff7d7155fd 100644 --- a/drivers/media/rc/lirc_dev.c +++ b/drivers/media/rc/lirc_dev.c @@ -724,7 +724,9 @@ static const struct file_operations lirc_fops = { .owner = THIS_MODULE, .write = ir_lirc_transmit_ir, .unlocked_ioctl = ir_lirc_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = ir_lirc_ioctl, +#endif .read = ir_lirc_read, .poll = ir_lirc_poll, .open = ir_lirc_open, diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 198d22d73724..f1bfaad2ce27 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -379,21 +379,9 @@ static int olaps_cmp(const void *a, const void *b) return st == 0 ? ed : st; } -/** - * fastrpc_get_buff_overlaps - Detect and handle buffer overlaps in RPC args - * @ctx: The invoke context containing buffer information - * - * This function detects overlapping memory regions in the RPC arguments and - * adjusts the memory mapping accordingly. It handles ION and non-ION buffers - * separately to prevent incorrect overlap detection between different buf types. - * For each buffer type: - * - If a buffer overlaps with a previous buffer of the same type, it adjusts - * the mapping to avoid the overlap - * - If no overlap is detected, it uses the full buffer range - */ static void fastrpc_get_buff_overlaps(struct fastrpc_invoke_ctx *ctx) { - u64 ion_buf_end_pos = 0, non_ion_buf_end_pos = 0; + u64 max_end = 0; int i; for (i = 0; i < ctx->nbufs; ++i) { @@ -405,29 +393,24 @@ static void fastrpc_get_buff_overlaps(struct fastrpc_invoke_ctx *ctx) sort(ctx->olaps, ctx->nbufs, sizeof(*ctx->olaps), olaps_cmp, NULL); for (i = 0; i < ctx->nbufs; ++i) { - /* Separate ION and non-ION buffers; fd <= 0 indicates non-ION */ - u64 *last_buf_end = (ctx->args[ctx->olaps[i].raix].fd <= 0) ? - &non_ion_buf_end_pos : &ion_buf_end_pos; - - if (ctx->olaps[i].start < *last_buf_end) { - /* Overlap detected within same buffer type */ - ctx->olaps[i].mstart = *last_buf_end; + /* Falling inside previous range */ + if (ctx->olaps[i].start < max_end) { + ctx->olaps[i].mstart = max_end; ctx->olaps[i].mend = ctx->olaps[i].end; - ctx->olaps[i].offset = *last_buf_end - ctx->olaps[i].start; + ctx->olaps[i].offset = max_end - ctx->olaps[i].start; - if (ctx->olaps[i].end > *last_buf_end) { - *last_buf_end = ctx->olaps[i].end; + if (ctx->olaps[i].end > max_end) { + max_end = ctx->olaps[i].end; } else { ctx->olaps[i].mend = 0; ctx->olaps[i].mstart = 0; } } else { - /* No overlap, assign full range */ ctx->olaps[i].mend = ctx->olaps[i].end; ctx->olaps[i].mstart = ctx->olaps[i].start; ctx->olaps[i].offset = 0; - *last_buf_end = ctx->olaps[i].end; + max_end = ctx->olaps[i].end; } } } @@ -727,12 +710,8 @@ static u64 fastrpc_get_payload_size(struct fastrpc_invoke_ctx *ctx, int metalen) if (ctx->args[i].fd == 0 || ctx->args[i].fd == -1) { - if (ctx->olaps[oix].offset == 0) { - /* Check for overflow before align. */ - if (size > (ULLONG_MAX - (FASTRPC_ALIGN - 1))) - return 0; + if (ctx->olaps[oix].offset == 0) size = ALIGN(size, FASTRPC_ALIGN); - } size += (ctx->olaps[oix].mend - ctx->olaps[oix].mstart); } @@ -830,22 +809,6 @@ static int fastrpc_get_args(u32 kernel, struct fastrpc_invoke_ctx *ctx) PAGE_SHIFT; pages[i].size = (pg_end - pg_start + 1) * PAGE_SIZE; - /* - * Check for page range overflow and validate page - * range is not greater than map buffer range. - * This prevents potential buffer overflow - * and memory corruption that could be exploited. - */ - if (pages[i].addr > (ULLONG_MAX - pages[i].size) || - (pages[i].addr + pages[i].size) > - (ctx->maps[i]->phys + ctx->maps[i]->size)) { - err = -EFAULT; - dev_err(dev, - "Invalid buffer addr 0x%llx len 0x%llx IPA 0x%llx size 0x%llx fd %d\n", - ctx->args[i].ptr, len, ctx->maps[i]->phys, - ctx->maps[i]->size, ctx->maps[i]->fd); - goto bail; - } } else { if (ctx->olaps[oix].offset == 0) { diff --git a/drivers/misc/vmw_vmci/vmci_host.c b/drivers/misc/vmw_vmci/vmci_host.c index c7c98d50d9fe..6eddb805642e 100644 --- a/drivers/misc/vmw_vmci/vmci_host.c +++ b/drivers/misc/vmw_vmci/vmci_host.c @@ -968,7 +968,7 @@ static const struct file_operations vmuser_fops = { .release = vmci_host_close, .poll = vmci_host_poll, .unlocked_ioctl = vmci_host_unlocked_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = vmci_host_unlocked_ioctl, }; static struct miscdevice vmci_host_miscdev = { diff --git a/drivers/mtd/devices/msm_qpic_nand.c b/drivers/mtd/devices/msm_qpic_nand.c index eb45e4908968..329e7ebbd191 100644 --- a/drivers/mtd/devices/msm_qpic_nand.c +++ b/drivers/mtd/devices/msm_qpic_nand.c @@ -2,7 +2,7 @@ /* * Copyright (C) 2007 Google, Inc. * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "msm_qpic_nand.h" @@ -1944,7 +1944,7 @@ free_dma: if (last_pos < ecc_bytes_percw_in_bits) num_zero_bits++; - if (num_zero_bits > info->flash_dev.ecc_capability) { + if (num_zero_bits > 4) { *erased_page = false; goto free_mem; } @@ -1955,8 +1955,8 @@ free_dma: num_zero_bits = last_pos = next_pos = 0; ecc_temp += chip->ecc_parity_bytes; } - if ((n == cwperpage) && - (num_zero_bits <= info->flash_dev.ecc_capability)) + + if ((n == cwperpage) && (num_zero_bits <= 4)) *erased_page = true; free_mem: kfree(ecc); @@ -2163,33 +2163,6 @@ static int msm_nand_read_pagescope(struct mtd_info *mtd, loff_t from, goto free_dma; /* Check for flash status errors */ pageerr = rawerr = 0; - - /* - * PAGE_ERASED bit will set only if all - * CODEWORD_ERASED bit of all codewords - * of the page is set. - * - * PAGE_ERASED bit is a 'logical and' of all - * CODEWORD_ERASED bit of all codewords i.e. - * even if one codeword is detected as not - * an erased codeword, PAGE_ERASED bit will unset. - */ - for (n = rw_params.start_sector; n < cwperpage; n++) { - if ((dma_buffer->result[n].erased_cw_status & - (1 << PAGE_ERASED)) && - (dma_buffer->result[n].buffer_status & - NUM_ERRORS)) { - err = msm_nand_is_erased_page_ps(mtd, - from, ops, - &rw_params, - &erased_page); - if (err) - goto free_dma; - if (erased_page) - rawerr = -EIO; - break; - } - } for (n = rw_params.start_sector; n < cwperpage; n++) { if (dma_buffer->result[n].flash_status & (FS_OP_ERR | FS_MPU_ERR)) { @@ -2581,7 +2554,7 @@ free_dma: if (last_pos < ecc_bytes_percw_in_bits) num_zero_bits++; - if (num_zero_bits > info->flash_dev.ecc_capability) { + if (num_zero_bits > 4) { *erased_page = false; goto free_mem; } @@ -2593,8 +2566,7 @@ free_dma: ecc_temp += chip->ecc_parity_bytes; } - if ((n == cwperpage) && - (num_zero_bits <= info->flash_dev.ecc_capability)) + if ((n == cwperpage) && (num_zero_bits <= 4)) *erased_page = true; free_mem: kfree(ecc); @@ -2788,33 +2760,6 @@ static int msm_nand_read_oob(struct mtd_info *mtd, loff_t from, goto free_dma; /* Check for flash status errors */ pageerr = rawerr = 0; - - /* - * PAGE_ERASED bit will set only if all - * CODEWORD_ERASED bit of all codewords - * of the page is set. - * - * PAGE_ERASED bit is a 'logical and' of all - * CODEWORD_ERASED bit of all codewords i.e. - * even if one codeword is detected as not - * an erased codeword, PAGE_ERASED bit will unset. - */ - for (n = rw_params.start_sector; n < cwperpage; n++) { - if ((dma_buffer->result[n].erased_cw_status & - (1 << PAGE_ERASED)) && - (dma_buffer->result[n].buffer_status & - NUM_ERRORS)) { - err = msm_nand_is_erased_page(mtd, - from, ops, - &rw_params, - &erased_page); - if (err) - goto free_dma; - if (erased_page) - rawerr = -EIO; - break; - } - } for (n = rw_params.start_sector; n < cwperpage; n++) { if (dma_buffer->result[n].flash_status & (FS_OP_ERR | FS_MPU_ERR)) { diff --git a/drivers/mtd/devices/msm_qpic_nand.h b/drivers/mtd/devices/msm_qpic_nand.h index 0297ad9697c4..cc1df16f5b3d 100644 --- a/drivers/mtd/devices/msm_qpic_nand.h +++ b/drivers/mtd/devices/msm_qpic_nand.h @@ -154,10 +154,7 @@ #define RESET_ERASED_DET (1 << AUTO_DETECT_RES) #define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES) #define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC) -#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC | SET_N_MAX_ZEROS) -#define N_MAX_ZEROS 2 -#define MAX_ECC_BIT_FLIPS 4 -#define SET_N_MAX_ZEROS (MAX_ECC_BIT_FLIPS << N_MAX_ZEROS) +#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC) #define MSM_NAND_ERASED_CW_DETECT_STATUS(info) MSM_NAND_REG(info, 0x300EC) #define PAGE_ALL_ERASED 7 @@ -166,7 +163,6 @@ #define CODEWORD_ERASED 4 #define ERASED_PAGE ((1 << PAGE_ALL_ERASED) | (1 << PAGE_ERASED)) #define ERASED_CW ((1 << CODEWORD_ALL_ERASED) | (1 << CODEWORD_ERASED)) -#define NUM_ERRORS 0x1f #define MSM_NAND_CTRL(info) MSM_NAND_REG(info, 0x30F00) #define BAM_MODE_EN 0 diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index bccbde286233..83012d74dcd5 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -1948,8 +1948,6 @@ static struct backing_dev_info * __init mtd_bdi_init(char *name) bdi = bdi_alloc(GFP_KERNEL); if (!bdi) return ERR_PTR(-ENOMEM); - bdi->ra_pages = 0; - bdi->io_pages = 0; bdi->name = name; /* diff --git a/drivers/net/wireless/cnss/Makefile b/drivers/net/wireless/cnss/Makefile index 567ef214d7dd..c1ca4c3821e6 100644 --- a/drivers/net/wireless/cnss/Makefile +++ b/drivers/net/wireless/cnss/Makefile @@ -3,9 +3,7 @@ # Makefile for CNSS platform driver # -obj-$(CONFIG_CNSS) += cnss.o - -cnss-$(CONFIG_CNSS_PCI) += cnss_pci.o -cnss-$(CONFIG_CNSS_SDIO) += cnss_sdio.o -cnss-y += cnss_common.o -obj-$(CONFIG_CNSS_LOGGER) += logger/ +obj-$(CONFIG_CNSS_PCI) += cnss_pci.o +obj-$(CONFIG_CNSS_SDIO) += cnss_sdio.o +obj-$(CONFIG_CNSS) += cnss_common.o +obj-$(CONFIG_CNSS_LOGGER) += logger/ diff --git a/drivers/net/wireless/cnss/cnss_common.c b/drivers/net/wireless/cnss/cnss_common.c index 534f81f320a6..dbdd13e0abca 100644 --- a/drivers/net/wireless/cnss/cnss_common.c +++ b/drivers/net/wireless/cnss/cnss_common.c @@ -242,21 +242,13 @@ int cnss_set_cpus_allowed_ptr(struct task_struct *task, ulong cpu) } EXPORT_SYMBOL(cnss_set_cpus_allowed_ptr); -#define ENTRIES_COUNT 32 +/* wlan prop driver cannot invoke show_stack + * function directly, so to invoke this function it + * call wcnss_dump_stack function + */ void cnss_dump_stack(struct task_struct *task) { - const int cnss_spaces = 4; - unsigned long cnss_entries[ENTRIES_COUNT] = {0}; - struct stack_trace cnss_trace = { - .nr_entries = 0, - .skip = 0, - .entries = &cnss_entries[0], - .max_entries = ENTRIES_COUNT, - }; - - save_stack_trace_tsk(task, &cnss_trace); - stack_trace_print(cnss_entries, cnss_trace.nr_entries, - cnss_spaces); + show_stack(task, NULL); } EXPORT_SYMBOL(cnss_dump_stack); diff --git a/drivers/net/wireless/cnss/cnss_pci.c b/drivers/net/wireless/cnss/cnss_pci.c index 623149274fa3..9d588b5ed6d8 100644 --- a/drivers/net/wireless/cnss/cnss_pci.c +++ b/drivers/net/wireless/cnss/cnss_pci.c @@ -31,8 +31,6 @@ #include #include #include -#include -#include #include #include #include @@ -1620,43 +1618,6 @@ static void cnss_pcie_reset_platform_ops(struct device *dev) dev->platform_data = NULL; } -#if IS_ENABLED(CONFIG_ARCH_QCOM) -/** - * cnss_pci_of_reserved_mem_device_init() - Assign reserved memory region - * to given PCI device - * @pdev: context pointer of pdev - * - * This function shall call corresponding of_reserved_mem_device* API to - * assign reserved memory region to PCI device based on where the memory is - * defined and attached to (platform device of_node or PCI device of_node) - * in device tree. - * - * Return: 0 for success, negative value for error - */ -static int cnss_pci_of_reserved_mem_device_init(struct pci_dev *pdev) -{ - struct device *dev_pci = &pdev->dev; - int ret; - - /* Use of_reserved_mem_device_init_by_idx() if reserved memory is - * attached to platform device of_node. - */ - ret = of_reserved_mem_device_init(dev_pci); - if (ret) - pr_err("Failed to init reserved mem device, err = %d\n", - ret); - if (dev_pci->cma_area) - pr_debug("CMA area is %s\n", cma_get_name(dev_pci->cma_area)); - - return ret; -} -#else -static int cnss_pci_of_reserved_mem_device_init(struct pci_dev *pdev) -{ - return 0; -} -#endif - static int cnss_wlan_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { @@ -1673,7 +1634,6 @@ static int cnss_wlan_pci_probe(struct pci_dev *pdev, atomic_set(&penv->fw_available, 0); penv->device_id = pdev->device; - cnss_pci_of_reserved_mem_device_init(pdev); if (penv->smmu_iova_len) { ret = cnss_smmu_init(&pdev->dev); if (ret) { diff --git a/drivers/nvdimm/bus.c b/drivers/nvdimm/bus.c index 4600f80fb250..56f189c3129a 100644 --- a/drivers/nvdimm/bus.c +++ b/drivers/nvdimm/bus.c @@ -1229,7 +1229,7 @@ static const struct file_operations nvdimm_bus_fops = { .owner = THIS_MODULE, .open = nd_open, .unlocked_ioctl = bus_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = bus_ioctl, .llseek = noop_llseek, }; @@ -1237,7 +1237,7 @@ static const struct file_operations nvdimm_fops = { .owner = THIS_MODULE, .open = nd_open, .unlocked_ioctl = dimm_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = dimm_ioctl, .llseek = noop_llseek, }; diff --git a/drivers/nvdimm/pmem.c b/drivers/nvdimm/pmem.c index 0f94658af4e7..7e65306b2bf2 100644 --- a/drivers/nvdimm/pmem.c +++ b/drivers/nvdimm/pmem.c @@ -137,25 +137,9 @@ static blk_status_t read_pmem(struct page *page, unsigned int off, return BLK_STS_OK; } -static blk_status_t pmem_do_read(struct pmem_device *pmem, - struct page *page, unsigned int page_off, - sector_t sector, unsigned int len) -{ - blk_status_t rc; - phys_addr_t pmem_off = sector * 512 + pmem->data_offset; - void *pmem_addr = pmem->virt_addr + pmem_off; - - if (unlikely(is_bad_pmem(&pmem->bb, sector, len))) - return BLK_STS_IOERR; - - rc = read_pmem(page, page_off, pmem_addr, len); - flush_dcache_page(page); - return rc; -} - -static blk_status_t pmem_do_write(struct pmem_device *pmem, - struct page *page, unsigned int page_off, - sector_t sector, unsigned int len) +static blk_status_t pmem_do_bvec(struct pmem_device *pmem, struct page *page, + unsigned int len, unsigned int off, unsigned int op, + sector_t sector) { blk_status_t rc = BLK_STS_OK; bool bad_pmem = false; @@ -165,25 +149,34 @@ static blk_status_t pmem_do_write(struct pmem_device *pmem, if (unlikely(is_bad_pmem(&pmem->bb, sector, len))) bad_pmem = true; - /* - * Note that we write the data both before and after - * clearing poison. The write before clear poison - * handles situations where the latest written data is - * preserved and the clear poison operation simply marks - * the address range as valid without changing the data. - * In this case application software can assume that an - * interrupted write will either return the new good - * data or an error. - * - * However, if pmem_clear_poison() leaves the data in an - * indeterminate state we need to perform the write - * after clear poison. - */ - flush_dcache_page(page); - write_pmem(pmem_addr, page, page_off, len); - if (unlikely(bad_pmem)) { - rc = pmem_clear_poison(pmem, pmem_off, len); - write_pmem(pmem_addr, page, page_off, len); + if (!op_is_write(op)) { + if (unlikely(bad_pmem)) + rc = BLK_STS_IOERR; + else { + rc = read_pmem(page, off, pmem_addr, len); + flush_dcache_page(page); + } + } else { + /* + * Note that we write the data both before and after + * clearing poison. The write before clear poison + * handles situations where the latest written data is + * preserved and the clear poison operation simply marks + * the address range as valid without changing the data. + * In this case application software can assume that an + * interrupted write will either return the new good + * data or an error. + * + * However, if pmem_clear_poison() leaves the data in an + * indeterminate state we need to perform the write + * after clear poison. + */ + flush_dcache_page(page); + write_pmem(pmem_addr, page, off, len); + if (unlikely(bad_pmem)) { + rc = pmem_clear_poison(pmem, pmem_off, len); + write_pmem(pmem_addr, page, off, len); + } } return rc; @@ -205,12 +198,8 @@ static blk_qc_t pmem_make_request(struct request_queue *q, struct bio *bio) do_acct = nd_iostat_start(bio, &start); bio_for_each_segment(bvec, bio, iter) { - if (op_is_write(bio_op(bio))) - rc = pmem_do_write(pmem, bvec.bv_page, bvec.bv_offset, - iter.bi_sector, bvec.bv_len); - else - rc = pmem_do_read(pmem, bvec.bv_page, bvec.bv_offset, - iter.bi_sector, bvec.bv_len); + rc = pmem_do_bvec(pmem, bvec.bv_page, bvec.bv_len, + bvec.bv_offset, bio_op(bio), iter.bi_sector); if (rc) { bio->bi_status = rc; break; @@ -235,12 +224,9 @@ static int pmem_rw_page(struct block_device *bdev, sector_t sector, struct pmem_device *pmem = bdev->bd_queue->queuedata; blk_status_t rc; - if (op_is_write(op)) - rc = pmem_do_write(pmem, page, 0, sector, - hpage_nr_pages(page) * PAGE_SIZE); - else - rc = pmem_do_read(pmem, page, 0, sector, - hpage_nr_pages(page) * PAGE_SIZE); + rc = pmem_do_bvec(pmem, page, hpage_nr_pages(page) * PAGE_SIZE, + 0, op, sector); + /* * The ->rw_page interface is subtle and tricky. The core * retries on any error, so we can only invoke page_endio() in @@ -283,16 +269,6 @@ static const struct block_device_operations pmem_fops = { .revalidate_disk = nvdimm_revalidate_disk, }; -static int pmem_dax_zero_page_range(struct dax_device *dax_dev, pgoff_t pgoff, - size_t nr_pages) -{ - struct pmem_device *pmem = dax_get_private(dax_dev); - - return blk_status_to_errno(pmem_do_write(pmem, ZERO_PAGE(0), 0, - PFN_PHYS(pgoff) >> SECTOR_SHIFT, - PAGE_SIZE)); -} - static long pmem_dax_direct_access(struct dax_device *dax_dev, pgoff_t pgoff, long nr_pages, void **kaddr, pfn_t *pfn) { @@ -324,7 +300,6 @@ static const struct dax_operations pmem_dax_ops = { .dax_supported = generic_fsdax_supported, .copy_from_iter = pmem_copy_from_iter, .copy_to_iter = pmem_copy_to_iter, - .zero_page_range = pmem_dax_zero_page_range, }; static const struct attribute_group *pmem_attribute_groups[] = { diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c index d1a369c619dc..94c8ef4a54d3 100644 --- a/drivers/nvme/host/core.c +++ b/drivers/nvme/host/core.c @@ -3062,7 +3062,7 @@ static const struct file_operations nvme_dev_fops = { .open = nvme_dev_open, .release = nvme_dev_release, .unlocked_ioctl = nvme_dev_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = nvme_dev_ioctl, }; static ssize_t nvme_sysfs_reset(struct device *dev, diff --git a/drivers/pci/switch/switchtec.c b/drivers/pci/switch/switchtec.c index 1b30d08e1867..0b8325235852 100644 --- a/drivers/pci/switch/switchtec.c +++ b/drivers/pci/switch/switchtec.c @@ -1025,7 +1025,7 @@ static const struct file_operations switchtec_fops = { .read = switchtec_dev_read, .poll = switchtec_dev_poll, .unlocked_ioctl = switchtec_dev_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = switchtec_dev_ioctl, }; static void link_event_work(struct work_struct *work) diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index cef10b457073..c8e23ac53d2f 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -2179,11 +2179,6 @@ int ep_pcie_core_disable_endpoint(void) if (atomic_read(&dev->host_wake_pending)) { EP_PCIE_DBG(dev, "PCIe V%d: wake pending, init wakeup\n", dev->rev); - /* - * Clear the wake pending otherwise ep_pcie_core_wakeup_host_internal - * will return without WAKE toggle - */ - atomic_set(&dev->host_wake_pending, 0); ep_pcie_core_wakeup_host_internal(EP_PCIE_EVENT_PM_D3_COLD); } diff --git a/drivers/platform/msm/mhi_dev/mhi.c b/drivers/platform/msm/mhi_dev/mhi.c index 141ce1157e9c..d7d9ecad8d73 100644 --- a/drivers/platform/msm/mhi_dev/mhi.c +++ b/drivers/platform/msm/mhi_dev/mhi.c @@ -39,7 +39,7 @@ /* Wait time on the device for Host to set BHI_INTVEC */ #define MHI_BHI_INTVEC_MAX_CNT 200 #define MHI_BHI_INTVEC_WAIT_MS 50 -#define MHI_WAKEUP_TIMEOUT_CNT 25 +#define MHI_WAKEUP_TIMEOUT_CNT 20 #define MHI_MASK_CH_EV_LEN 32 #define MHI_RING_CMD_ID 0 #define MHI_RING_PRIMARY_EVT_ID 1 diff --git a/drivers/platform/msm/mhi_dev/mhi_sm.c b/drivers/platform/msm/mhi_dev/mhi_sm.c index e8d9300c7812..89190bfeadfc 100644 --- a/drivers/platform/msm/mhi_dev/mhi_sm.c +++ b/drivers/platform/msm/mhi_dev/mhi_sm.c @@ -12,7 +12,6 @@ #include "mhi_hwio.h" #include "mhi_sm.h" #include -#include #define MHI_SM_DBG(fmt, args...) \ mhi_log(MHI_MSG_DBG, fmt, ##args) @@ -29,11 +28,7 @@ #define PCIE_EP_TIMER_US 500000000 #define MHI_IPA_DISABLE_DELAY_MS 10 #define MHI_IPA_DISABLE_COUNTER 20 -/* Maximum wait time for D state transitions to D3hot */ -#define M3_DO_WAKEUP_TIMEOUT_MS 2500 -static void wait_d3_and_wakeup(struct work_struct *work); -static int mhi_dev_sm_get_mhi_pcie_states(uint32_t *mstate, uint32_t *dstate); static inline const char *mhi_sm_dev_event_str(enum mhi_dev_event state) { @@ -240,8 +235,6 @@ struct mhi_sm_dev { struct mutex mhi_state_lock; bool syserr_occurred; struct workqueue_struct *mhi_sm_wq; - struct workqueue_struct *mhi_wake_wq; - struct work_struct mhi_wake_work; atomic_t pending_device_events; atomic_t pending_pcie_events; struct mhi_sm_stats stats; @@ -741,12 +734,12 @@ exit: * mhi_sm_wakeup_host() - wakeup MHI-host *@event: MHI state chenge event * - * Sends wakeup event to MHI-host via EP-PCIe, in case MHI is in M3 state. + * Sends wekup event to MHI-host via EP-PCIe, in case MHI is in M3 state. * * Return: 0:success * negative: failure */ -static int mhi_sm_wakeup_host(void) +static int mhi_sm_wakeup_host(enum mhi_dev_event event) { int res = 0; enum ep_pcie_event pcie_event; @@ -761,8 +754,7 @@ static int mhi_sm_wakeup_host(void) } else if (mhi_sm_ctx->mhi_state == MHI_DEV_M3_STATE) { /* * Check and send D3_HOT to enable waking up the host - * using inband PME if the host is in D3_HOT state, otherwise - * send D3_COLD to wake up the host. + * using inband PME. */ if (mhi_sm_ctx->d_state == MHI_SM_EP_PCIE_D3_HOT_STATE) pcie_event = EP_PCIE_EVENT_PM_D3_HOT; @@ -914,7 +906,9 @@ static void mhi_sm_dev_event_manager(struct work_struct *work) break; case MHI_DEV_EVENT_HW_ACC_WAKEUP: case MHI_DEV_EVENT_CORE_WAKEUP: - queue_work(mhi_sm_ctx->mhi_wake_wq, &mhi_sm_ctx->mhi_wake_work); + res = mhi_sm_wakeup_host(chg_event->event); + if (res) + MHI_SM_ERR("Failed to wakeup MHI host\n"); break; case MHI_DEV_EVENT_CTRL_TRIG: case MHI_DEV_EVENT_M1_STATE: @@ -1125,19 +1119,9 @@ int mhi_dev_sm_init(struct mhi_dev *mhi_dev) if (!mhi_sm_ctx->mhi_sm_wq) { MHI_SM_ERR("Failed to create singlethread_workqueue: sm_wq\n"); res = -ENOMEM; - goto fail_init_sm_wq; + goto fail_init_wq; } - if (!mhi_sm_ctx->mhi_wake_wq) - mhi_sm_ctx->mhi_wake_wq = alloc_workqueue( - "mhi_wake_wq", WQ_HIGHPRI | WQ_UNBOUND, 1); - if (!mhi_sm_ctx->mhi_wake_wq) { - MHI_SM_ERR("Failed to create singlethread_workqueue: wake_wq\n"); - res = -ENOMEM; - goto fail_init_wake_wq; - } - INIT_WORK(&mhi_sm_ctx->mhi_wake_work, wait_d3_and_wakeup); - mutex_init(&mhi_sm_ctx->mhi_state_lock); mhi_sm_ctx->mhi_dev = mhi_dev; mhi_sm_ctx->mhi_state = MHI_DEV_RESET_STATE; @@ -1150,10 +1134,7 @@ int mhi_dev_sm_init(struct mhi_dev *mhi_dev) MHI_SM_FUNC_EXIT(); return 0; -fail_init_wake_wq: - flush_workqueue(mhi_sm_ctx->mhi_sm_wq); - destroy_workqueue(mhi_sm_ctx->mhi_sm_wq); -fail_init_sm_wq: +fail_init_wq: mhi_sm_ctx = NULL; mhi_sm_debugfs_destroy(); return res; @@ -1181,20 +1162,20 @@ int mhi_dev_sm_exit(struct mhi_dev *mhi_dev) EXPORT_SYMBOL(mhi_dev_sm_exit); /** - * mhi_dev_sm_get_mhi_pcie_states() -Get current MHI and Pcie states. + * mhi_dev_sm_get_mhi_state() -Get current MHI state. * @state: return param * - * Returns the current MHI and PCIe states of the state machine. + * Returns the current MHI state of the state machine. * * Return: 0 success * -EINVAL: invalid param * -EFAULT: state machine isn't initialized */ -static int mhi_dev_sm_get_mhi_pcie_states(uint32_t *mstate, uint32_t *dstate) +int mhi_dev_sm_get_mhi_state(enum mhi_dev_state *state) { MHI_SM_FUNC_ENTRY(); - if (!mstate || !dstate) { + if (!state) { MHI_SM_ERR("Fail: Null argument\n"); return -EINVAL; } @@ -1202,60 +1183,15 @@ static int mhi_dev_sm_get_mhi_pcie_states(uint32_t *mstate, uint32_t *dstate) MHI_SM_ERR("Fail: MHI SM is not initialized\n"); return -EFAULT; } - mutex_lock(&mhi_sm_ctx->mhi_state_lock); - *mstate = mhi_sm_ctx->mhi_state; - *dstate = mhi_sm_ctx->d_state; - mutex_unlock(&mhi_sm_ctx->mhi_state_lock); + *state = mhi_sm_ctx->mhi_state; MHI_SM_DBG("state machine states are: %s and %s\n", - mhi_sm_mstate_str(*mstate), - mhi_sm_dstate_str(*dstate)); + mhi_sm_mstate_str(*state), + mhi_sm_dstate_str(mhi_sm_ctx->d_state)); MHI_SM_FUNC_EXIT(); return 0; } - -static void wait_d3_and_wakeup(struct work_struct *work) -{ - struct mhi_sm_dev *mhi_sm_ctx = container_of(work, struct mhi_sm_dev, mhi_wake_work); - enum mhi_dev_state mstate; - enum mhi_sm_ep_pcie_state dstate; - ktime_t timeout = 0; - - if (mhi_dev_sm_get_mhi_pcie_states(&mstate, &dstate)) { - MHI_SM_ERR("Unable to read states\n"); - return; - } - /* - * Handle host wakeup in M3 + D0 states. - * When a MHI WAKE request is received while device is in D0, - * wait for D3 and wakeup the host using inband PME. - * If the MHI state changes to M0 while waiting for D3, - * exit, since both MHI and the device are in active state - */ - if (dstate == MHI_SM_EP_PCIE_D0_STATE) { - timeout = ktime_add_ms(ktime_get(), M3_DO_WAKEUP_TIMEOUT_MS); - while (1) { - mhi_dev_sm_get_mhi_pcie_states(&mstate, &dstate); - if (mstate == MHI_DEV_M0_STATE) { - MHI_SM_DBG("M0 state received\n"); - return; - } - if (dstate == MHI_SM_EP_PCIE_D3_HOT_STATE || - dstate == MHI_SM_EP_PCIE_D3_COLD_STATE) { - MHI_SM_DBG("D3 state received\n"); - goto send_host_wakeup; - } - if (ktime_after(ktime_get(), timeout)) { - MHI_SM_ERR("Neither received D3 nor M0 in stipulated time\n"); - return; - } - usleep_range(1000, 2000); - } - } -send_host_wakeup: - if (dstate == MHI_SM_EP_PCIE_D3_HOT_STATE || dstate == MHI_SM_EP_PCIE_D3_COLD_STATE) - mhi_sm_wakeup_host(); -} +EXPORT_SYMBOL(mhi_dev_sm_get_mhi_state); /** * mhi_dev_sm_set_ready() -Set MHI state to ready. diff --git a/drivers/platform/msm/mhi_dev/mhi_sm.h b/drivers/platform/msm/mhi_dev/mhi_sm.h index 24e6daf46777..80ed0086472f 100644 --- a/drivers/platform/msm/mhi_dev/mhi_sm.h +++ b/drivers/platform/msm/mhi_dev/mhi_sm.h @@ -42,6 +42,7 @@ int mhi_dev_sm_init(struct mhi_dev *dev); int mhi_dev_sm_exit(struct mhi_dev *dev); int mhi_dev_sm_set_ready(void); int mhi_dev_notify_sm_event(enum mhi_dev_event event); +int mhi_dev_sm_get_mhi_state(enum mhi_dev_state *state); int mhi_dev_sm_syserr(void); void mhi_dev_sm_pcie_handler(struct ep_pcie_notify *notify); diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c index 2acdbf93088d..66cfc35e4e3d 100644 --- a/drivers/platform/x86/wmi.c +++ b/drivers/platform/x86/wmi.c @@ -912,7 +912,7 @@ static const struct file_operations wmi_fops = { .read = wmi_char_read, .open = wmi_char_open, .unlocked_ioctl = wmi_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = wmi_ioctl, }; static int wmi_dev_probe(struct device *dev) diff --git a/drivers/rpmsg/rpmsg_char.c b/drivers/rpmsg/rpmsg_char.c index c503829fb307..ac50ed757765 100644 --- a/drivers/rpmsg/rpmsg_char.c +++ b/drivers/rpmsg/rpmsg_char.c @@ -292,7 +292,7 @@ static const struct file_operations rpmsg_eptdev_fops = { .write_iter = rpmsg_eptdev_write_iter, .poll = rpmsg_eptdev_poll, .unlocked_ioctl = rpmsg_eptdev_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = rpmsg_eptdev_ioctl, }; static ssize_t name_show(struct device *dev, struct device_attribute *attr, @@ -446,7 +446,7 @@ static const struct file_operations rpmsg_ctrldev_fops = { .open = rpmsg_ctrldev_open, .release = rpmsg_ctrldev_release, .unlocked_ioctl = rpmsg_ctrldev_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = rpmsg_ctrldev_ioctl, }; static void rpmsg_ctrldev_release_device(struct device *dev) diff --git a/drivers/sbus/char/display7seg.c b/drivers/sbus/char/display7seg.c index fad936eb845f..971fe074d7c9 100644 --- a/drivers/sbus/char/display7seg.c +++ b/drivers/sbus/char/display7seg.c @@ -156,7 +156,7 @@ static long d7s_ioctl(struct file *file, unsigned int cmd, unsigned long arg) static const struct file_operations d7s_fops = { .owner = THIS_MODULE, .unlocked_ioctl = d7s_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = d7s_ioctl, .open = d7s_open, .release = d7s_release, .llseek = noop_llseek, diff --git a/drivers/sbus/char/envctrl.c b/drivers/sbus/char/envctrl.c index 12d66aa61ede..a63d5e402ff2 100644 --- a/drivers/sbus/char/envctrl.c +++ b/drivers/sbus/char/envctrl.c @@ -715,7 +715,9 @@ static const struct file_operations envctrl_fops = { .owner = THIS_MODULE, .read = envctrl_read, .unlocked_ioctl = envctrl_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = envctrl_ioctl, +#endif .open = envctrl_open, .release = envctrl_release, .llseek = noop_llseek, diff --git a/drivers/scsi/3w-xxxx.c b/drivers/scsi/3w-xxxx.c index 211a25351e7d..75290aabd543 100644 --- a/drivers/scsi/3w-xxxx.c +++ b/drivers/scsi/3w-xxxx.c @@ -1049,7 +1049,9 @@ static int tw_chrdev_open(struct inode *inode, struct file *file) static const struct file_operations tw_fops = { .owner = THIS_MODULE, .unlocked_ioctl = tw_chrdev_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = tw_chrdev_ioctl, +#endif .open = tw_chrdev_open, .release = NULL, .llseek = noop_llseek, diff --git a/drivers/scsi/cxlflash/main.c b/drivers/scsi/cxlflash/main.c index 6f45074ee895..67d681c53c29 100644 --- a/drivers/scsi/cxlflash/main.c +++ b/drivers/scsi/cxlflash/main.c @@ -3593,7 +3593,7 @@ static const struct file_operations cxlflash_chr_fops = { .owner = THIS_MODULE, .open = cxlflash_chr_open, .unlocked_ioctl = cxlflash_chr_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = cxlflash_chr_ioctl, }; /** diff --git a/drivers/scsi/esas2r/esas2r_main.c b/drivers/scsi/esas2r/esas2r_main.c index 80c5a235d193..fdbda5c05aa0 100644 --- a/drivers/scsi/esas2r/esas2r_main.c +++ b/drivers/scsi/esas2r/esas2r_main.c @@ -613,7 +613,7 @@ static int __init esas2r_init(void) /* Handle ioctl calls to "/proc/scsi/esas2r/ATTOnode" */ static const struct file_operations esas2r_proc_fops = { - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = esas2r_proc_ioctl, .unlocked_ioctl = esas2r_proc_ioctl, }; diff --git a/drivers/scsi/pmcraid.c b/drivers/scsi/pmcraid.c index 4dc316ca5d28..f95a970db8fd 100644 --- a/drivers/scsi/pmcraid.c +++ b/drivers/scsi/pmcraid.c @@ -3973,7 +3973,9 @@ static const struct file_operations pmcraid_fops = { .open = pmcraid_chr_open, .fasync = pmcraid_chr_fasync, .unlocked_ioctl = pmcraid_chr_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = pmcraid_chr_ioctl, +#endif .llseek = noop_llseek, }; diff --git a/drivers/staging/android/ion/heaps/msm_ion_dma_buf.c b/drivers/staging/android/ion/heaps/msm_ion_dma_buf.c index 7e9f518001e8..6bd9dd286057 100644 --- a/drivers/staging/android/ion/heaps/msm_ion_dma_buf.c +++ b/drivers/staging/android/ion/heaps/msm_ion_dma_buf.c @@ -500,12 +500,11 @@ static int ion_sgl_sync_range(struct device *dev, struct scatterlist *sgl, break; if (i > 0) { - if (!get_dma_ops(dev)) - return 0; - - pr_warn_ratelimited("Partial cmo only supported with 1 segment\n" - "is dma_set_max_seg_size being set on dev:%s\n", - dev_name(dev)); + if (get_dma_ops(dev)) { + pr_warn_ratelimited("Partial cmo only supported with 1 segment\n" + "is dma_set_max_seg_size being set on dev:%s\n", + dev_name(dev)); + } return -EINVAL; } } diff --git a/drivers/staging/android/ion/ion.c b/drivers/staging/android/ion/ion.c index 343957103791..ce974bdfc7d0 100644 --- a/drivers/staging/android/ion/ion.c +++ b/drivers/staging/android/ion/ion.c @@ -221,7 +221,9 @@ static long ion_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) static const struct file_operations ion_fops = { .owner = THIS_MODULE, .unlocked_ioctl = ion_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = ion_ioctl, +#endif }; static int debug_shrink_set(void *data, u64 val) diff --git a/drivers/staging/fw-api/fw/enet.h b/drivers/staging/fw-api/fw/enet.h index d8f84c595287..54a561eb1db8 100644 --- a/drivers/staging/fw-api/fw/enet.h +++ b/drivers/staging/fw-api/fw/enet.h @@ -92,8 +92,8 @@ typedef PREPACK struct { } POSTPACK vlan_hdr_t; #define ETHERTYPE_IS_EAPOL_WAPI(typeorlen) \ - ((typeorlen) == ETHERTYPE_PAE || \ - (typeorlen) == ETHERTYPE_WAI) + ((typeorlen) == ETHERTYPE_PAE || \ + (typeorlen) == ETHERTYPE_WAI) #define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600) @@ -102,11 +102,11 @@ typedef PREPACK struct { #endif #ifndef ETHERTYPE_AARP -#define ETHERTYPE_AARP 0x80f3 /* Internal QCA AARP protocol */ +#define ETHERTYPE_AARP 0x80f3 /* Internal QCA AARP protocol */ #endif #ifndef ETHERTYPE_IPX -#define ETHERTYPE_IPX 0x8137 /* IPX over DIX protocol */ +#define ETHERTYPE_IPX 0x8137 /* IPX over DIX protocol */ #endif #ifndef ETHERTYPE_ARP @@ -133,18 +133,6 @@ typedef PREPACK struct { #define ETHERTYPE_PAE 0x888E /* EAP over LAN (EAPOL) */ #endif - #ifndef EAPOL_KEY_TYPE - #define EAPOL_KEY_TYPE 0x3 /* EAP over LAN (EAPOL) */ - #endif - - #ifndef EAPOL_PAIRKEY - #define EAPOL_PAIRKEY 0x008 - #endif - - #ifndef EAPOL_GRPKEY - #define EAPOL_GRPKEY 0x00 - #endif - #ifndef ETHERTYPE_WAI #define ETHERTYPE_WAI 0x88B4 /* WAPI */ #endif diff --git a/drivers/staging/fw-api/fw/htc_services.h b/drivers/staging/fw-api/fw/htc_services.h index 3e4fca244b1e..50d57596a0b0 100644 --- a/drivers/staging/fw-api/fw/htc_services.h +++ b/drivers/staging/fw-api/fw/htc_services.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012, 2014-2017, 2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -64,9 +64,7 @@ typedef enum { /* WMI_CONTROL_SVC_WMAC3,4: WMI service for MACs 3 and 4 (where applicable) */ #define WMI_CONTROL_SVC_WMAC3 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,9) #define WMI_CONTROL_SVC_WMAC4 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,10) -/* SMD high prio service - common for all macs */ -#define WMI_CONTROL_SMD_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,11) -#define WMI_MAX_SERVICES 12 +#define WMI_MAX_SERVICES 11 #define NMI_CONTROL_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,0) #define NMI_DATA_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,1) @@ -95,18 +93,6 @@ typedef enum { */ #define HTT_DATA3_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,2) -/* HTT_DATA4_MSG_SVC - * H2T channel to transfer MSDU/MPDU queue info from host to target - */ -#define HTT_DATA4_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,3) - -/* H2T - Telemetry channel */ -#define HTT_TELEMETRY_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,4) -/* T2H - Telemetry channel 1 */ -#define HTT_TELEMETRY1_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,5) -/* T2H - Telemetry channel 2 */ -#define HTT_TELEMETRY2_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,6) - /* raw stream service (i.e. flash, tcmd, calibration apps) */ #define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0) diff --git a/drivers/staging/fw-api/fw/htt.h b/drivers/staging/fw-api/fw/htt.h index 7234768e9b81..e9d34066ff72 100644 --- a/drivers/staging/fw-api/fw/htt.h +++ b/drivers/staging/fw-api/fw/htt.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -266,29 +266,9 @@ * 3.136 Add htt_ext_present flag in htt_tx_tcl_global_seq_metadata. * 3.137 Add more HTT_SDWF_MSDUQ_CFG_IND_ERROR codes. * 3.138 Add T2H MLO_LATENCY_REQ, H2T _RESP msg defs. - * 3.139 Add CLASS_INFO_IDX field in MLO_R_PEER_MAP msg. - * 3.140 Add H2T MPDUQ_AND_MSDUQ_INFO_HDR and MPDUQ_OF_MSDUQ_INFO defs. - * 3.141 Add H2T HTT_AST_INFO for RxOLE. - * 3.142 Add T2H GLOBAL_PEER_ID_UNMAP def, update H2T MPDUQ_OR_MSDUQ_INFO def. - * 3.143 Add T2H HAPS msg def. - * 3.144 Add svc_inst_req_type in htt_h2t_mpduq_or_msduq_info. - * 3.145 Add 3rd bit for rx_hdr_len in RX_RING_SELECTION_CFG - * 3.146 Add HTT_RXOLE_ASE_STATUS_RING def. - * 3.147 Add direct_refill flag in SRING_SETUP msg. - * 3.148 Add HTT_PEER_CFR_CAPTURE_BW_320MHZ def. - * 3.149 Add SAM fields in MPDUQ_OR_MSDUQ_INFO. - * 3.150 Add htt_reg_write_selection definitions. - * 3.151 Add HTT_H2T DAL_MODE_INFO def. - * 3.152 Add decap_type in htt_rx_peer_metadata_v1b. - * 3.153 Add passthru_pkt flag in rx_peer_metadata structs. - * 3.154 Add T2H PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP msg def. - * 3.155 Add rxmon hdrlen specs in rx_ring_selection_cfg_t. - * 3.156 Add qdata_consent_pkt flag in rx_peer_metadata_v1a and v2. - * 3.157 Add TCL_METADATA_V3 defs. - * 3.158 Add more fields in htt_tx_monitor_cfg_t. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 158 +#define HTT_CURRENT_VERSION_MINOR 138 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -585,7 +565,6 @@ PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t { * should be used: * V1 -> use htt_tx_tcl_metadata struct * V2 -> use htt_tx_tcl_metadata_v2 struct - * V3 -> use htt_tx_tcl_metadata_v3 struct * Old FW will only support V1. * New FW will support V2. New FW will still support V1, at least during * a transition period. @@ -611,17 +590,11 @@ PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t { * and the FW will crash in wal_tx_de_fast.c. For version 2.1 and * above we will use htt_tx_tcl_svc_class_id_metadata.ast_index * in TCLV2 command and do the dynamic AST allocations. - * - * Apr 2026: Added HTT_OPTION_TLV_TCL_METADATA_V3. - * This version supports the updated tcl_data_cmd introduced in Boron. - * All fields are identical to V2; however, the field ordering has been - * modified to accommodate MAC requirements. */ enum HTT_OPTION_TLV_TCL_METADATA_VER_VALUES { HTT_OPTION_TLV_TCL_METADATA_V1 = 1, HTT_OPTION_TLV_TCL_METADATA_V2 = 2, - HTT_OPTION_TLV_TCL_METADATA_V3 = 3, - /* values 4-20 reserved */ + /* values 3-20 reserved */ HTT_OPTION_TLV_TCL_METADATA_V21 = 21, }; @@ -794,10 +767,7 @@ typedef enum { HTT_STATS_AST_ENTRY_TAG = 132, /* htt_ast_entry_tlv */ HTT_STATS_TX_PDEV_BE_DL_MU_OFDMA_STATS_TAG = 133, /* htt_tx_pdev_dl_be_mu_ofdma_sch_stats_tlv, TOPIC=advanced */ HTT_STATS_TX_PDEV_BE_UL_MU_OFDMA_STATS_TAG = 134, /* htt_tx_pdev_ul_be_mu_ofdma_sch_stats_tlv, TOPIC=advanced */ - HTT_STATS_TX_PDEV_RATE_BE_BN_OFDMA_TAG = 135, /* htt_stats_tx_pdev_rate_be_bn_ofdma_tlv */ - /* retain deprecated name as an alias */ - HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = - HTT_STATS_TX_PDEV_RATE_BE_BN_OFDMA_TAG, + HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135, /* htt_tx_pdev_rate_stats_be_ofdma_tlv */ HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG = 136, /* htt_rx_pdev_ul_mumimo_trig_be_stats_tlv, TOPIC=advanced */ HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, /* htt_tx_selfgen_be_err_stats_tlv, TOPIC=advanced */ HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, /* htt_tx_selfgen_be_stats_tlv, TOPIC=advanced */ @@ -805,10 +775,7 @@ typedef enum { HTT_STATS_TX_PDEV_BE_UL_MU_MIMO_STATS_TAG = 140, /* htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv */ HTT_STATS_RX_PDEV_BE_UL_MIMO_USER_STATS_TAG = 141, /* htt_rx_pdev_be_ul_mimo_user_stats_tlv */ HTT_STATS_RX_RING_STATS_TAG = 142, /* htt_rx_fw_ring_stats_tlv_v */ - HTT_STATS_RX_PDEV_BE_BN_UL_TRIG_TAG = 143, /* htt_stats_rx_pdev_be_bn_ul_trig_tlv, TOPIC=advanced */ - /* retain deprecated name as an alias */ - HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG = - HTT_STATS_RX_PDEV_BE_BN_UL_TRIG_TAG, + HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG = 143, /* htt_rx_pdev_be_ul_trigger_stats_tlv, TOPIC=advanced */ HTT_STATS_TX_PDEV_SAWF_RATE_STATS_TAG = 144, /* htt_tx_pdev_rate_stats_sawf_tlv, TOPIC=advanced */ HTT_STATS_STRM_GEN_MPDUS_TAG = 145, /* htt_stats_strm_gen_mpdus_tlv_t */ HTT_STATS_STRM_GEN_MPDUS_DETAILS_TAG = 146, /* htt_stats_strm_gen_mpdus_details_tlv_t */ @@ -839,8 +806,7 @@ typedef enum { HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG = 171, /* htt_tx_pdev_ap_edca_params_stats_tlv_v, TOPIC=advanced */ HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172, /* htt_txbf_ofdma_ax_steer_mpdu_stats_tlv, TOPIC=advanced */ HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG = 173, /* htt_txbf_ofdma_be_steer_mpdu_stats_tlv, TOPIC=advanced */ - HTT_STATS_PEER_OFDMA_STATS_TAG = 174, /* htt_stats_peer_ofdma_stats_tlv */ - HTT_STATS_PEER_AX_OFDMA_STATS_TAG = HTT_STATS_PEER_OFDMA_STATS_TAG, /* DEPRECATED */ + HTT_STATS_PEER_AX_OFDMA_STATS_TAG = 174, /* htt_peer_ax_ofdma_stats_tlv */ HTT_STATS_TX_PDEV_MU_EDCA_PARAMS_STATS_TAG = 175, /* htt_tx_pdev_mu_edca_params_stats_tlv_v, TOPIC=advanced */ HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, /* htt_pdev_mbssid_ctrl_frame_stats_tlv */ HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */ @@ -874,77 +840,10 @@ typedef enum { HTT_STATS_PDEV_RTT_DELAY_TAG = 205, /* htt_stats_pdev_rtt_delay_tlv */ HTT_STATS_PDEV_AOA_TAG = 206, /* htt_stats_pdev_aoa_tlv */ HTT_STATS_PDEV_FTM_TPCCAL_TAG = 207, /* htt_stats_pdev_ftm_tpccal_tlv */ - HTT_STATS_PDEV_UL_MUMIMO_GRP_STATS_TAG = 208, /* htt_stats_pdev_ul_mumimo_grp_stats_tlv */ - HTT_STATS_PDEV_UL_MUMIMO_DENYLIST_STATS_TAG = 209, /* htt_stats_pdev_ul_mumimo_denylist_stats_tlv */ - HTT_STATS_PDEV_UL_MUMIMO_SEQ_TERM_STATS_TAG = 210, /* htt_stats_pdev_ul__mumimo_seq_term_stats_tlv */ - HTT_STATS_PDEV_UL_MUMIMO_HIST_INELIGIBILITY_TAG = 211, /* htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv */ - HTT_STATS_PHY_PAPRD_PB_TAG = 212, /* htt_stats_phy_paprd_pb_tlv */ - HTT_STATS_HDS_PROF_STATS_TAG = 213, /* htt_stat_hds_prof_stats_tlv */ - HTT_STATS_TX_PDEV_MDSB_NUM_USERS_HISTOGRAM_TAG = 214, /* htt_stats_tx_pdev_mdsb_num_users_histogram_tlv */ - /* preserve old name as an alias for the corrected name */ - HTT_STATS_TX_PDEV_MDSB_NUM_USERS_HISTOGRAM_TLV_TAG = - HTT_STATS_TX_PDEV_MDSB_NUM_USERS_HISTOGRAM_TAG, - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_TAG = 215, /* htt_stats_tx_pdev_pending_seq_cnt_on_sched_post_hist_tlv */ - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_TAG = 216, /* htt_stats_tx_pdev_pending_seq_cnt_in_hwq_hist_tlv */ - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_TAG = 217, /* htt_stats_tx_pdev_pending_seq_cnt_in_txq_hist_tlv */ - HTT_STATS_SCHED_TXQ_EARLY_COMPL_TAG = 218, /* htt_stats_sched_txq_early_compl_tlv */ - HTT_STATS_RX_PDEV_BN_UL_OFDMA_USER_TAG = 219, /* htt_stats_rx_pdev_bn_ul_ofdma_user_tlv */ - HTT_STATS_TX_SELFGEN_BN_ERR_TAG = 220, /* htt_stats_tx_selfgen_bn_err_tlv, TOPIC=advanced */ - HTT_STATS_TX_SELFGEN_BN_TAG = 221, /* htt_stats_tx_selfgen_bn_tlv, TOPIC=advanced */ - HTT_STATS_TX_SELFGEN_BN_SCHED_STATUS_TAG = 222, /* htt_stats_tx_selfgen_bn_sched_status_tlv, TOPIC=advanced */ - HTT_STATS_TX_PDEV_BN_DL_MU_OFDMA_STATS_TAG = 223, /* htt_stats_tx_pdev_bn_dl_mu_ofdma_stats_tlv, TOPIC=advanced */ - HTT_STATS_TX_PDEV_BN_UL_MU_OFDMA_STATS_TAG = 224, /* htt_stats_tx_pdev_bn_ul_mu_ofdma_stats_tlv, TOPIC=advanced */ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TAG = 225, /* htt_stats_rx_peer_tid_reo_queue_ba_tlv */ - HTT_STATS_TXBF_OFDMA_BN_NDPA_TAG = 226, /* htt_stats_txbf_ofdma_bn_ndpa_tlv */ - HTT_STATS_TXBF_OFDMA_BN_NDP_TAG = 227, /* htt_stats_txbf_ofdma_bn_ndp_tlv */ - HTT_STATS_TXBF_OFDMA_BN_BRP_TAG = 228, /* htt_stats_txbf_ofdma_bn_brp_tlv */ - HTT_STATS_TXBF_OFDMA_BN_STEER_TAG = 229, /* htt_stats_txbf_ofdma_bn_steer_tlv */ - HTT_STATS_TXBF_OFDMA_BN_STEER_MPDU_TAG = 230, /* htt_stats_txbf_ofdma_bn_steer_mpdu_tlv */ - HTT_STATS_TXBF_OFDMA_BN_PARBW_TAG = 231, /* htt_stats_txbf_ofdma_bn_parbw_tlv */ - HTT_STATS_OPTIONAL_CONFIGS_TAG = 232, /* htt_stats_optional_configs_tlv */ - HTT_STATS_PDEV_SAM_TAG = 233, /* htt_stats_pdev_sam_tlv */ - HTT_STATS_FTM_TAG = 234, /* htt_stats_ftm_tlv */ - HTT_STATS_PDEV_FTM_TPCCAL_EXT_TAG = 235, /* htt_stats_pdev_ftm_tpccal_ext_tlv */ - HTT_STATS_TX_PDEV_BN_RATE_TAG = 236, /* htt_stats_tx_pdev_bn_rate_tlv */ - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BN_TAG = 237, /* htt_stats_rx_pdev_ul_mumimo_trig_bn_tlv, TOPIC=advanced */ - HTT_STATS_RX_PDEV_BN_UL_MIMO_USER_TAG = 238, /* htt_stats_rx_pdev_bn_ul_mimo_user_tlv */ - HTT_STATS_TX_PDEV_BN_UL_MU_MIMO_TAG = 239, /* htt_stats_tx_pdev_bn_ul_mu_mimo_tlv */ - /* HTT_STATS_PDEV_ANI_HIST_TAG: - * htt_stats_pdev_ani_hist_tlv - * ani_hist_type: - * 0 = 1 sec, - * 1 = granular - * 2 = 1 sec disabled - * 3 = granular disabled - */ - HTT_STATS_PDEV_ANI_HIST_TAG = 240, - HTT_STATS_ANI_SCALAR_TAG = 241, /* htt_stats_ani_scalar_tlv */ - HTT_STATS_ANI_PKT_CNT_TAG = 242, /* htt_stats_ani_pkt_cnt_tlv */ - HTT_STATS_ANI_CRC_PASS_TAG = 243, /* htt_stats_ani_crc_pass_tlv */ - HTT_STATS_ANI_PER_BLK_ERR_TAG = 244, /* htt_stats_ani_per_blk_err_tlv */ - HTT_STATS_ANI_OTA_ERR_TAG = 245, /* htt_stats_ani_ota_err_tlv */ - HTT_STATS_RESET_HISTORY_TAG = 246, /* htt_stats_reset_history_tlv */ - HTT_STATS_REGDB_CTRY_TAG = 247, /* htt_stats_regdb_ctry_tlv */ - HTT_STATS_REGDB_REGDOMAIN_TAG = 248, /* htt_stats_regdb_regdomain_tlv */ - HTT_STATS_REG_6G_TAG = 249, /* htt_stats_reg_6g_tlv*/ - HTT_STATS_REG_6G_CH_PWR_INFO_TAG = 250, /* htt_stats_reg_6g_ch_power_info_tlv */ - HTT_STATS_REG_6G_OOBE_TAG = 251, /* htt_stats_reg_6g_oobe_tlv*/ - HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_TAG = 252, /* htt_stats_tx_selfgen_resp_frame_stats_tlv */ - HTT_STATS_DPD_HALPHY_TAG = 253, /* htt_stats_dpd_halphy_tlv */ - HTT_STATS_DPD_HW_CAL_PARAMS_TAG = 254, /* htt_stats_dpd_hw_cal_params_tlv */ - HTT_STATS_DPD_HW_CAL_RESULTS_TAG = 255, /* htt_stats_dpd_hw_cal_results_tlv */ - HTT_STATS_TX_PDEV_TXOP_DUR_TAG = 256, /* htt_stats_tx_pdev_txop_dur_tlv */ - HTT_STATS_TXQ_COMBINED_SEQ_STATE_TAG = 257, /* htt_stats_txq_combined_seq_state_tlv */ - HTT_STATS_CTL_TAG = 258, /* htt_stats_ctl_tlv */ - HTT_STATS_ENHANCED_CTL_TAG = 259, /* htt_stats_enhanced_ctl_tlv */ - HTT_STATS_NPCA_TAG = 260, /* htt_stats_npca_tlv */ - HTT_STATS_SCHED_TXQ_TX_MODE_SIMPLIFIED_TAG = 261, /* htt_stats_sched_txq_tx_mode_simplified_tlv */ - HTT_STATS_SCHED_TXQ_TX_MODE_WINNER_TAG = 262, /* htt_stats_sched_txq_tx_mode_winner_tlv */ - HTT_STATS_DFS_RADAR_HISTORY_TAG = 263, /* htt_stats_dfs_radar_history_tlv */ - HTT_STATS_DFS_INI_TAG = 264, /* htt_stats_dfs_ini_tlv */ - HTT_STATS_DFS_IPC_RING_TAG = 265, /* htt_stats_dfs_ipc_ring_tlv */ - HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_TAG = 266, /* htt_stats_phy_dpd_debug_chain_v1_tlv */ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TAG = 267, /* htt_stats_phy_tpc_debug_chain_v1_tlv */ + HTT_STATS_PDEV_UL_MUMIMO_GRP_STATS_TAG = 208, /* htt_stats_pdev_ulmumimo_grp_stats_tlv */ + HTT_STATS_PDEV_UL_MUMIMO_DENYLIST_STATS_TAG = 209, /* htt_stats_pdev_ulmumimo_denylist_stats_tlv */ + HTT_STATS_PDEV_UL_MUMIMO_SEQ_TERM_STATS_TAG = 210, /* htt_stats_pdev_ulmumimo_seq_term_stats_tlv */ + HTT_STATS_PDEV_UL_MUMIMO_HIST_INELIGIBILITY_TAG = 211, /* htt_stats_pdev_ulmumimo_hist_ineligibility_tlv */ HTT_STATS_MAX_TAG, } htt_stats_tlv_tag_t; @@ -979,51 +878,47 @@ typedef htt_stats_tlv_tag_t htt_tlv_tag_t; /*=== host -> target messages ===============================================*/ enum htt_h2t_msg_type { - HTT_H2T_MSG_TYPE_VERSION_REQ = 0x0, - HTT_H2T_MSG_TYPE_TX_FRM = 0x1, - HTT_H2T_MSG_TYPE_RX_RING_CFG = 0x2, - HTT_H2T_MSG_TYPE_STATS_REQ = 0x3, - HTT_H2T_MSG_TYPE_SYNC = 0x4, - HTT_H2T_MSG_TYPE_AGGR_CFG = 0x5, - HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 0x6, - DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX = 0x7, /* no longer used */ - HTT_H2T_MSG_TYPE_WDI_IPA_CFG = 0x8, - HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ = 0x9, - HTT_H2T_MSG_TYPE_AGGR_CFG_EX = 0xa, /* per vdev amsdu subfrm limit */ - HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, - HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, - HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY = 0xd, - HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY = 0xe, - HTT_H2T_MSG_TYPE_RFS_CONFIG = 0xf, - HTT_H2T_MSG_TYPE_EXT_STATS_REQ = 0x10, - HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, - HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG = 0x12, - HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG = 0x13, - HTT_H2T_MSG_TYPE_CHAN_CALDATA = 0x14, - HTT_H2T_MSG_TYPE_RX_FISA_CFG = 0x15, - HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG = 0x16, - HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, - HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE = 0x18, - HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG = 0x19, - HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG = 0x1a, - HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, - HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ = 0x1c, - HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ = 0x1d, - HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ = 0x1e, - HTT_H2T_MSG_TYPE_MSI_SETUP = 0x1f, - HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ = 0x20, - HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21, + HTT_H2T_MSG_TYPE_VERSION_REQ = 0x0, + HTT_H2T_MSG_TYPE_TX_FRM = 0x1, + HTT_H2T_MSG_TYPE_RX_RING_CFG = 0x2, + HTT_H2T_MSG_TYPE_STATS_REQ = 0x3, + HTT_H2T_MSG_TYPE_SYNC = 0x4, + HTT_H2T_MSG_TYPE_AGGR_CFG = 0x5, + HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 0x6, + DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX = 0x7, /* no longer used */ + HTT_H2T_MSG_TYPE_WDI_IPA_CFG = 0x8, + HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ = 0x9, + HTT_H2T_MSG_TYPE_AGGR_CFG_EX = 0xa, /* per vdev amsdu subfrm limit */ + HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, + HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, + HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY = 0xd, + HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY = 0xe, + HTT_H2T_MSG_TYPE_RFS_CONFIG = 0xf, + HTT_H2T_MSG_TYPE_EXT_STATS_REQ = 0x10, + HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, + HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG = 0x12, + HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG = 0x13, + HTT_H2T_MSG_TYPE_CHAN_CALDATA = 0x14, + HTT_H2T_MSG_TYPE_RX_FISA_CFG = 0x15, + HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG = 0x16, + HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, + HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE = 0x18, + HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG = 0x19, + HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG = 0x1a, + HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, + HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ = 0x1c, + HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ = 0x1d, + HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ = 0x1e, + HTT_H2T_MSG_TYPE_MSI_SETUP = 0x1f, + HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ = 0x20, + HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21, HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22, - HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23, - HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24, - HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG = 0x25, - HTT_H2T_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP = 0x26, - HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ = 0x27, - HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_RESP = 0x28, - HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR = 0x29, - HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO = 0x2a, - HTT_H2T_MSG_TYPE_AST_INFO = 0x2b, - HTT_H2T_MSG_TYPE_DAL_MODE_INFO = 0x2c, + HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23, + HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24, + HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG = 0x25, + HTT_H2T_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP = 0x26, + HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ = 0x27, + HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_RESP = 0x28, /* keep this last */ HTT_H2T_NUM_MSGS @@ -2967,231 +2862,6 @@ PREPACK struct htt_tx_tcl_metadata_v2 { * End V2 Version of TCL Data Command *-----------------------------------------------------------------*/ - -/*------------------------------------------------------------------ - * V3 Version of TCL Data Command - * V3 Version to support peer_id, vdev_id, svc_class_id and - * MLO global_seq all flavours of TCL Data Cmd. same fields as V2, - * but the ordering of the fields changes. - *-----------------------------------------------------------------*/ - -typedef struct { - A_UINT32 - valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ - vdev_id: 8, - pdev_id: 2, - host_inspected:1, - rsvd: 2, - /* type: vdev_id based or peer_id or svc_id or global seq based */ - type: 2, - /* padding: these 16 bits cannot be used by FW for the tcl command */ - padding: 16; -} htt_tx_tcl_vdev_metadata_v3; - -typedef struct { - A_UINT32 - valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ - peer_id: 13, - /* type: vdev_id based or peer_id or svc_id or global seq based */ - type: 2, - /* padding: these 16 bits cannot be used by FW for the tcl command */ - padding: 16; -} htt_tx_tcl_peer_metadata_v3; - -typedef struct { - A_UINT32 - valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ - svc_class_id: 8, - /* ast_index: - * Indicates to firmware the AST index to be used for AST Override - */ - ast_index: 3, - rsvd: 2, - /* type: vdev_id based or peer_id or svc_id or global seq based */ - type: 2, - /* padding: these 16 bits cannot be used by FW for the tcl command */ - padding: 16; -} htt_tx_tcl_svc_class_id_metadata_v3; - -typedef struct { - A_UINT32 - global_seq_no: 12, - host_inspected: 1, - htt_ext_present:1, - /* type: vdev_id based or peer_id or svc_id or global seq based */ - type: 2, - /* padding: these 16 bits cannot be used by FW for the tcl command */ - padding: 16; -} htt_tx_tcl_global_seq_metadata_v3; - -PREPACK struct htt_tx_tcl_metadata_v3 { - union { - htt_tx_tcl_vdev_metadata_v3 vdev_meta_v3; - htt_tx_tcl_peer_metadata_v3 peer_meta_v3; - htt_tx_tcl_svc_class_id_metadata_v3 svc_class_id_meta_v3; - htt_tx_tcl_global_seq_metadata_v3 global_seq_meta_v3; - }; -} POSTPACK; - -/* ===================================================================== - * Common fields - * ===================================================================== */ - -/* type field */ -#define HTT_TX_TCL_METADATA_TYPE_V3_M 0x0000C000 -#define HTT_TX_TCL_METADATA_TYPE_V3_S 14 - -/* valid htt ext (used by VDEV / PEER / SVC metadata) */ -#define HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_M 0x00000001 -#define HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_S 0 - - -/* ===================================================================== - * VDEV V3 metadata - * ===================================================================== */ - -#define HTT_TX_TCL_METADATA_V3_VDEV_ID_M 0x000001FE -#define HTT_TX_TCL_METADATA_V3_VDEV_ID_S 1 - -#define HTT_TX_TCL_METADATA_V3_PDEV_ID_M 0x00000600 -#define HTT_TX_TCL_METADATA_V3_PDEV_ID_S 9 - -#define HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_M 0x00000800 -#define HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_S 11 - - -/* ===================================================================== - * PEER V3 metadata - * ===================================================================== */ - -#define HTT_TX_TCL_METADATA_V3_PEER_ID_M 0x00003FFE -#define HTT_TX_TCL_METADATA_V3_PEER_ID_S 1 - - -/* ===================================================================== - * SVC CLASS ID metadata - * ===================================================================== */ - -#define HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_M 0x000001FE -#define HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_S 1 - -#define HTT_TX_TCL_METADATA_AST_INDEX_M 0x00000E00 -#define HTT_TX_TCL_METADATA_AST_INDEX_S 9 - - -/* ===================================================================== - * Global Sequence Number metadata - * ===================================================================== */ - -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_M 0x00000FFF -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_S 0 - -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_M 0x00001000 -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_S 12 - -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_M 0x00002000 -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_S 13 - -/*----- Get and Set V3 type field in Vdev, Peer, Svc_Class_Id, Global_seq_no */ -#define HTT_TX_TCL_METADATA_TYPE_V3_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_TYPE_V3_M) >> \ - HTT_TX_TCL_METADATA_TYPE_V3_S) -#define HTT_TX_TCL_METADATA_TYPE_V3_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_TYPE_V3, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_TYPE_V3_S)); \ - } while (0) - -#define HTT_TX_TCL_METADATA_V3_VALID_HTT_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_M) >> \ - HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_S) -#define HTT_TX_TCL_METADATA_V3_VALID_HTT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_S)); \ - } while (0) - -/*----- Get and Set V3 type field in Vdev meta fields ----*/ -#define HTT_TX_TCL_METADATA_V3_VDEV_ID_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_VDEV_ID_M) >> \ - HTT_TX_TCL_METADATA_V3_VDEV_ID_S) -#define HTT_TX_TCL_METADATA_V3_VDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_VDEV_ID_S)); \ - } while (0) - -#define HTT_TX_TCL_METADATA_V3_PDEV_ID_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_PDEV_ID_M) >> \ - HTT_TX_TCL_METADATA_V3_PDEV_ID_S) -#define HTT_TX_TCL_METADATA_V3_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_PDEV_ID_S)); \ - } while (0) - -#define HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_M) >> \ - HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_S) -#define HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_HOST_INSPECTED, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_S)); \ - } while (0) - -/*----- Get and Set V3 type field in Peer meta fields ----*/ -#define HTT_TX_TCL_METADATA_V3_PEER_ID_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_PEER_ID_M) >> \ - HTT_TX_TCL_METADATA_V3_PEER_ID_S) -#define HTT_TX_TCL_METADATA_V3_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_PEER_ID_S)); \ - } while (0) - -/*----- Get and Set V3 type field in Service Class fields ----*/ -#define HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_M) >> \ - HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_S) -#define HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_S)); \ - } while (0) - -/*----- Get and Set V3 type field in Global sequence fields ----*/ -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_M) >> \ - HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_S) -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_S)); \ - } while (0) - -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_M) >> \ - HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_S) -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_S)); \ - } while (0) - -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_M) >> \ - HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_S) -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_S)); \ - } while (0) - -/*------------------------------------------------------------------ - * End V3 Version of TCL Data Command - *-----------------------------------------------------------------*/ - - typedef enum { HTT_TX_FW2WBM_TX_STATUS_OK, HTT_TX_FW2WBM_TX_STATUS_DROP, @@ -5786,8 +5456,7 @@ PREPACK struct htt_sring_setup_t { prefetch_timer_cfg: 3, response_required: 1, ipa_drop_flag: 1, - direct_refill: 1, - reserved1: 10; + reserved1: 11; A_UINT32 ipa_drop_low_threshold: 8, ipa_drop_high_threshold: 8, reserved: 16; @@ -5817,10 +5486,6 @@ enum htt_srng_ring_id { HTT_LPASS_TO_FW_RXBUF_RING, /* new LPASS to FW refill ring to recycle rx buffers */ HTT_HOST3_TO_FW_RXBUF_RING, /* used by host for EasyMesh feature */ HTT_HOST4_TO_FW_RXBUF_RING, /* fourth ring used by host to provide buffers for MGMT packets */ - HTT_RXDMA_WBM_BUF0_RING, /* used for SFE Datapath */ - HTT_RXDMA_WBM_BUF1_RING, /* used for MGMT Datapath */ - HTT_RXDMA_WBM_BUF2_RING, /* used for PPE path */ - HTT_RXOLE_ASE_STATUS_RING, /* RxOLE2SW ASE Status ring */ /* Add Other SRING which can't be directly configured by host software above this line */ }; @@ -6145,27 +5810,6 @@ enum htt_srng_ring_id { ((_var) |= ((_val) << HTT_SRING_SETUP_RESPONSE_REQUIRED_S)); \ } while (0) -#define HTT_SRING_SETUP_IPA_DROP_FLAG_M 0x00100000 -#define HTT_SRING_SETUP_IPA_DROP_FLAG_S 20 -#define HTT_SRING_SETUP_IPA_DROP_FLAG_GET(_var) \ - (((_var) & HTT_SRING_SETUP_IPA_DROP_FLAG_M) >> \ - HTT_SRING_SETUP_IPA_DROP_FLAG_S) -#define HTT_SRING_SETUP_IPA_DROP_FLAG_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_IPA_DROP_FLAG, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_IPA_DROP_FLAG_S)); \ - } while (0) - -#define HTT_SRING_SETUP_DIRECT_REFILL_M 0x00200000 -#define HTT_SRING_SETUP_DIRECT_REFILL_S 21 -#define HTT_SRING_SETUP_DIRECT_REFILL_GET(_var) \ - (((_var) & HTT_SRING_SETUP_DIRECT_REFILL_M) >> \ - HTT_SRING_SETUP_DIRECT_REFILL_S) -#define HTT_SRING_SETUP_DIRECT_REFILL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DIRECT_REFILL, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_DIRECT_REFILL_S)); \ - } while (0) /** * @brief host -> target RX ring selection config message @@ -6184,7 +5828,7 @@ enum htt_srng_ring_id { * |-----+--+--+--+--+--+-----------------+----+---+---+---+---------------| * |rsvd1|ED|DT|OV|PS|SS| ring_id | pdev_id | msg_type | * |--------------------------+-----+-----+--------------------------------| - * |rsvd2|HE|RX|RXHDL| CLD | CLC | CLM | ring_buffer_size | + * | rsvd2 |RX|RXHDL| CLD | CLC | CLM | ring_buffer_size | * |-----------------------------------------------------------------------| * | packet_type_enable_flags_0 | * |-----------------------------------------------------------------------| @@ -6218,7 +5862,6 @@ enum htt_srng_ring_id { * CLD = config_length_data * RXHDL = rx_hdr_len * RX = rxpcu_filter_enable_flag - * HE = rx_hdr_len extension * The message is interpreted as follows: * dword0 - b'0:7 - msg_type: This will be set to * 0xc (HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG) @@ -6243,11 +5886,7 @@ enum htt_srng_ring_id { * newer packet_type_enable_data_flags_* are valid or not * If not set, will use pkt_type_enable_flags for both status * and full pkt buffer configuration. - * b'30 - is_monitor_mode: specify whether monitor mode is enabled. - * Helpful to configure monitor-mode related filters. - * These filters cause throughput dip if enabled in - * non-monitor mode. - * b'31 - rsvd1: reserved for future use + * b'30:31 - rsvd1: reserved for future use * dword1 - b'0:15 - ring_buffer_size: size of bufferes referenced by rx ring, * in byte units. * Valid only for HW_TO_SW_RING and SW_TO_HW_RING @@ -6288,18 +5927,7 @@ enum htt_srng_ring_id { * be zero which means allow all frames for MD at RxOLE * host wil fiter out frames. * RxPCU (Filter IN) -> RxOLE (Filter In/Filter Out) - * b'28 - rx_hdr_len_ext: - * Extend rx_hdr_len to 3 bits with b'28 as MSb. - * Valid combined values: - * 001 - 64bytes - * 010 - 128bytes - * 011 - 256bytes - * 100 - 512bytes - * 101 - 1024bytes - * 110 - 2048bytes - * 111 - max bytes supported by HW - * default - 128 bytes - * b'29:31 - rsvd2: Reserved for future use + * b'28:31 - rsvd2: Reserved for future use * dword2 - b'0:31 - packet_type_enable_flags_0: * Enable MGMT packet from 0b0000 to 0b1001 * bits from low to high: FP, MD, MO - 3 bits @@ -6448,11 +6076,6 @@ enum htt_srng_ring_id { * dword28- b'0-31 - packet_type_enable_data_fpmo_flags_1 - filter bmap for * full pkt buffer each mode ctrl/data type/subtype for * fpmo mode - * dword29- b'0-31 - rdi_based_source_cfg - * Each bit maps to an RDI; if set, the corresponding - * ring ID is configured as a source buffer. - * Applies only to HTT_RXDMA_WBM_BUF0/1/2_RING. - * dword30- b'0-31 - wifi8 header length configurations. */ PREPACK struct htt_rx_ring_selection_cfg_t { A_UINT32 msg_type: 8, @@ -6464,16 +6087,14 @@ PREPACK struct htt_rx_ring_selection_cfg_t { drop_thresh_valid: 1, rx_mon_global_en: 1, packet_type_enable_data: 1, - is_monitor_mode: 1, - rsvd1: 1; + rsvd1: 2; A_UINT32 ring_buffer_size: 16, config_length_mgmt:3, config_length_ctrl:3, config_length_data:3, rx_hdr_len: 2, rxpcu_filter_enable_flag:1, - rx_hdr_len_ext: 1, - rsvd2: 3; + rsvd2: 4; A_UINT32 packet_type_enable_flags_0; A_UINT32 packet_type_enable_flags_1; A_UINT32 packet_type_enable_flags_2; @@ -6526,58 +6147,8 @@ PREPACK struct htt_rx_ring_selection_cfg_t { A_UINT32 packet_type_enable_data_flags_3; A_UINT32 packet_type_enable_data_fpmo_flags0; A_UINT32 packet_type_enable_data_fpmo_flags1; - - /* rdi_based_source_cfg: - * Each bit position in rdi_based_source_cfg represents RDI - * (REO Destination Indication). - * - * 1 in specific RDI position represents, for the given RDI position, - * ring id in the ring setup msg has to be configured as source buf. - * - * Below Field only applies for HTT_RXDMA_WBM_BUF0/1/2_RING - */ - A_UINT32 rdi_based_source_cfg; - - A_UINT32 rxmon_fpmo_data_hdrlen : 2, - rxmon_fpmo_ctrl_hdrlen : 2, - rxmon_fpmo_mgmt_hdrlen : 2, - rxmon_fp_data_hdrlen : 2, - rxmon_fp_ctrl_hdrlen : 2, - rxmon_fp_mgmt_hdrlen : 2, - rxmon_mo_data_hdrlen : 2, - rxmon_mo_ctrl_hdrlen : 2, - rxmon_mo_mgmt_hdrlen : 2, - rxmon_md_data_hdrlen : 2, - rxmon_md_ctrl_hdrlen : 2, - rxmon_md_mgmt_hdrlen : 2, - rxmon_enable_hdr_per_ppdu : 1, - rxmon_rsvd : 7; } POSTPACK; -/** - * Enumeration for Reg Write block index selection - * Each Enum position corresponds to respective - * UMAC_UMCMN_R0_REG_ADDR_LSB_IX_n - * UMAC_UMCMN_R0_REG_ADDR_MSB_IX_n - * UMAC_UMCMN_R2_REG_VALUE_IX_n - * - * Any value written to the value register will be copied by - * Reg Writer Block to Address written in Reg Address Register. - * - * NOTE: Only value Registers defined in the enum should be used by the Host. - * Rest are unconfigured, and if used may result in invalid memory access - */ -enum htt_reg_write_selection { - HTT_REG_WRITER_RXMON_SW2MON_BUF_RING, - HTT_REG_WRITER_TXMON_SW2MON_BUF_RING, - HTT_REG_WRITER_RXMON_M0_MON2SW_DEST_RING, - HTT_REG_WRITER_RXMON_M1_MON2SW_DEST_RING, - HTT_REG_WRITER_TXMON_M0_MON2SW_DEST_RING, - HTT_REG_WRITER_TXMON_M1_MON2SW_DEST_RING, - HTT_REG_WRITER_RXOLE2SW_ASE_DEST_RING, -}; - - #define HTT_RX_RING_SELECTION_CFG_SZ (sizeof(struct htt_rx_ring_selection_cfg_t)) #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_M 0x0000ff00 @@ -6668,18 +6239,6 @@ enum htt_reg_write_selection { ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_S)); \ } while (0) -#define HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_M 0x40000000 -#define HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_S 30 -#define HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_M) >> \ - HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_S) -#define HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_S)); \ - } while (0) - - #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M 0x0000ffff #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S 0 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_GET(_var) \ @@ -6726,25 +6285,14 @@ enum htt_reg_write_selection { #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M 0x06000000 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S 25 -#define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_M 0x10000000 -#define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_S 28 -#define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_CHK_M 0x7 -#define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_CHK_S 0 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_GET(_var) \ - ((((_var) & HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_M) >> \ - (HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_S-2)) | \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S)) + (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S) #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_CHK, _val); \ - ((_var) |= (((_val) << \ - HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S) & \ - HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M)); \ - ((_var) |= (((_val) << \ - (HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_S-2)) & \ - HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_M)); \ - } while(0) + do { \ + HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S));\ + } while(0) #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M 0x08000000 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S 27 @@ -7247,150 +6795,6 @@ enum htt_reg_write_selection { } while (0) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_M 0x00000003 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S 0 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_M 0x0000000C -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S 2 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_M 0x00000030 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S 4 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_M 0x000000C0 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S 6 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_M 0x00000300 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S 8 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_M 0x00000C00 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S 10 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_M 0x00003000 -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S 12 -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_M 0x0000C000 -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S 14 -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_M 0x00030000 -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S 16 -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_M 0x000C0000 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S 18 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_M 0x00300000 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S 20 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_M 0x00C00000 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S 22 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_M 0x01000000 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S 24 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S) -#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S)); \ - } while (0) - - /* * Subtype based MGMT frames enable bits. * FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other @@ -8116,10 +7520,7 @@ PREPACK struct htt_tx_monitor_cfg_t { pkt_swap: 1, tx_mon_global_en: 1, mac_addr_filter_en: 1, - addr_filter_peer_bitmap_ppdu_drop: 1, - type_based_mpdu_stat_filter_en: 1, - special_pkt_filtering_en: 1, - pkt_buf_cnt_en: 1; + rsvd1: 4; A_UINT32 ring_buffer_size: 16, config_length_mgmt: 3, config_length_ctrl: 3, @@ -8163,23 +7564,6 @@ PREPACK struct htt_tx_monitor_cfg_t { response_end_status_word_mask: 16; A_UINT32 fes_status_prot_word_mask: 11, rsvd6: 21; - A_UINT32 phy_tx_pkt_end: 8, - mac_tx_user_desc_common: 8, - mac_tx_mu_uplink_user_setup: 8, - pdg_response: 8; - A_UINT32 received_response_info: 8, - rx_response_required_info: 8, - ranging_user_details: 8, - mactx_pre_phy_desc: 8; - A_UINT32 ofdma_trigger_details: 16, - tqm_update_tx_mpdu_count_status: 16; - A_UINT32 phytx_location: 16, - rsvd7: 16; - A_UINT32 received_response_info_part2; - A_UINT32 type_en_mgmt; - A_UINT32 type_en_ctrl; - A_UINT32 type_en_data; - A_UINT32 tlv_filter_mask_in4; } POSTPACK; #define HTT_TX_MONITOR_CFG_SZ (sizeof(struct htt_tx_monitor_cfg_t)) @@ -8250,51 +7634,6 @@ PREPACK struct htt_tx_monitor_cfg_t { ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_S)); \ } while (0) -#define HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_M 0x10000000 -#define HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_S 28 -#define HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_M) >> \ - HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_S) -#define HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_M 0x20000000 -#define HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_S 29 -#define HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_M) >> \ - HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_S) -#define HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_M 0x40000000 -#define HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_S 30 -#define HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_M) >> \ - HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_S) -#define HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_M 0x80000000 -#define HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_S 31 -#define HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_M) >> \ - HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_S) -#define HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_S)); \ - } while (0) - - #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M 0x0000ffff #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S 0 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_GET(_var) \ @@ -8681,132 +8020,6 @@ PREPACK struct htt_tx_monitor_cfg_t { ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S)); \ } while (0) - -#define HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_M 0x000000ff -#define HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_S 0 -#define HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_M) >> \ - HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_S) -#define HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PHY_TX_PKT_END, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_M 0x0000ff00 -#define HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_S 8 -#define HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_M) >> \ - HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_S) -#define HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_M 0x00ff0000 -#define HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_S 16 -#define HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_M) >> \ - HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_S) -#define HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_PDG_RESPONSE_M 0xff000000 -#define HTT_TX_MONITOR_CFG_PDG_RESPONSE_S 24 -#define HTT_TX_MONITOR_CFG_PDG_RESPONSE_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_PDG_RESPONSE_M) >> \ - HTT_TX_MONITOR_CFG_PDG_RESPONSE_S) -#define HTT_TX_MONITOR_CFG_PDG_RESPONSE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PDG_RESPONSE, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PDG_RESPONSE_S)); \ - } while (0) - - -#define HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_M 0x000000ff -#define HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_S 0 -#define HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_M) >> \ - HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_S) -#define HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_M 0x0000ff00 -#define HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_S 8 -#define HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_M) >> \ - HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_S) -#define HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_M 0x00ff0000 -#define HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_S 16 -#define HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_M) >> \ - HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_S) -#define HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_M 0xff000000 -#define HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_S 24 -#define HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_M) >> \ - HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_S) -#define HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_S)); \ - } while (0) - - -#define HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_M 0x0000ffff -#define HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_S 0 -#define HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_M) >> \ - HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_S) -#define HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_M 0xffff0000 -#define HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_S 16 -#define HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_M) >> \ - HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_S) -#define HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_S)); \ - } while (0) - - -#define HTT_TX_MONITOR_CFG_PHYTX_LOCATION_M 0x0000ffff -#define HTT_TX_MONITOR_CFG_PHYTX_LOCATION_S 0 -#define HTT_TX_MONITOR_CFG_PHYTX_LOCATION_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_PHYTX_LOCATION_M) >> \ - HTT_TX_MONITOR_CFG_PHYTX_LOCATION_S) -#define HTT_TX_MONITOR_CFG_PHYTX_LOCATION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PHYTX_LOCATION, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PHYTX_LOCATION_S)); \ - } while (0) - - /* * pkt_type_enable_flags */ @@ -12371,755 +11584,6 @@ PREPACK struct htt_h2t_mlo_latency_stats { ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_NUM_OF_TX_PKT_S)); \ } while (0) -/** - * @brief host -> target msg to provide MSDUQ or MPDUQ for new TID in a peer - * - * MSG_TYPE => HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR - * - * @details - * struct htt_h2t_mpduq_and_msduq_info_hdr: - * HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR message is sent by the host to - * target to tell how many mpduq and msduq info TLVs, in units of bytes, - * are present in the htt payload - * Example message contents: - *------------------------------------------------------------------- - *| htt_h2t_mpduq_and_msduq_info_hdr | - *------------------------------------------------------------------- - *| mpduq_info_tlv -> tid 0 , peer_id 1 | - *------------------------------------------------------------------- - *| mpduq_info_tlv -> tid 6, peer_id 1 | - *------------------------------------------------------------------- - *| msduq_info_tlv -> tid 0, peer_id 1 | - *------------------------------------------------------------------- - *| msduq_info_tlv -> tid 0, peer_id 1 | - *------------------------------------------------------------------- - *| msduq_info_tlv -> tid 6, peer_id 1 | - *------------------------------------------------------------------- - * - * As shown in the above exampple, a single htt buffer can hold multiple mpduq - * and msduq info tlvs, the info within the tlvs will indicate the peer and tid - * to which they belong. - */ - -/* HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR */ -PREPACK struct htt_h2t_mpduq_and_msduq_info_hdr { - A_UINT32 msg_type: 8, /* bits 7:0 */ - payload_size_bytes: 12, /* bits 19:8 */ - reserved_1a: 12; /* bits 31:20 */ -} POSTPACK; - -#define HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_M 0x000FFF00 -#define HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_S 8 -#define HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_S)); \ - } while (0) - - -/** - * @brief host -> target message to provide mpduq for a tid in a peer - * - * MSG_TYPE => HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO - * - * @details - * struct htt_h2t_mpduq_or_msduq_info: - * HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO message is sent by the host to - * specify the configuration of new MPDUQ/MSDUQ for a tid in a peer. - * This message supports the following configuration information: - * 1. Info provided per MPDUQ: - * upper 32 bit address of 256 byte aligned physical address for mpduq - * mpduq number - * pn address space - * 2. Info provided per MSDUQ: - * upper 32 bit address of 256 byte aligned physical address for msduq - * msduq_number - * service class id - * - * The message is interpreted as follows for mpduq type: - * dword0 - b'7:0 - msg_type: Identifies msduq and mpduq info to FW - * This will be set to 0x2a - * (HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO) - * b'12:8 - msduq_mpduq_type: Indicate whether this TLV is for - * a MPDU queue or MSDU queue, and if for a MSDU queue, - * what type. - * For an MPDU queue, it will be fixed value of 30 based - * on enum HTT_H2T_TID_MSDUQ_MPDUQ_TYPE. - * b'16:13 - hw_link_id: Indicates which HW link the message is for. - * This HW link ID is mainly relevant for split PHY - * usecases to identify the correct link in same SOC. - * dword1 - b'31:0 - mpduq_address_39_8: 256 byte aligned mpduq physical - * address, since lowest octet is zero for 256 byte aligned - * physical addresses just passing upper 32 bits of - * 40 bit address - * dword2 - b'11:0 – peer_id - * b'16:12 – tid_num - * b'23:17 – reserved - * b'31:24 - pn_addr_32_39: Upper 8 bits of 40 bit pn physical address - * Note that the mpduq_number is formed from the combination of - * peer_id (in bits 11:0) - * tid_num (in bits 16:12) - * msduq_mpduq_type (in bits 21:17) - * dword3 - b'31:0 - pn_addr_0_31: Lower 32 bits of 40 bit pn physical address - * dword4 - b'0:0 - sam_mpduq_allocated: Indicates whether a SAM MPDUQ has - * been allocated for this TQM MPDUQ. - * b'11:1 - sam_mpduq_id: The SAM MPDUQ ID assigned by the host for - * this TQM MPDUQ. The value in this field is ignored if - * sam_mpduq_allocated is 0. - * b'13:12 - sam_mpduq_priority: The SAM priority assigned by the - * host. A SAM priority MUST ALWAYS be provided for chipsets - * that have SAM support, regardless of whether or not a SAM - * MPDUQ has been allocated. - * b'14:14 - sam_mpduq_sched_eligible: Indicates that this SAM MPDUQ - * is eligible for autonomous SAM scheduling. The value in - * this field is ignored if sam_mpduq_allocated is 0. - * b'31:15 – reserved - * Additional reserved dwords for future use cases - * - * - * The message is interpreted as follows for any msduq type: - * dword0 - b'7:0 - msg_type: Identifies msduq info to fw - * This will be set to 0x2A - * (HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO) - * b'12:8 - msduq_mpduq_type: type of the msduq based on - * enum HTT_H2T_TID_MSDUQ_MPDUQ_TYPE - * b'16:13 - hw_link_id: Indicates which HW link the message is - * intended for. - * This HW link ID is mainly relevant for split PHY - * usecases to identify the correct link in same SOC. - * dword1 - b'11:0 – peer_id - * b'16:12 – tid_num - * b'23:17 – reserved - * b'31:24 - svc_class_id : service class id of the msduq - * Note that the tx_msduq_number is formed from the combination of - * peer_id (in bits 11:0) - * tid_num (in bits 16:12) - * msduq_mpduq_type (in bits 21:17) - * dword2 - b'31:0 - msduq_address_39_8: 256 byte aligned msduq physical - * address, since lowest octet is zero for 256 byte aligned - * addresses just passing upper 32 bits of 40 bit address - * dword3 - b'0:0 - svc_inst_req_type_valid: Indicates whether - * svc_inst_req_type is valid. - * b'3:1 - svc_inst_req_type: Contains one of the values from - * HTT_SAWF_SVC_INST_REQ_TYPE. Only valid if - * svc_inst_req_type_valid is 1. - * b'4:4 - sam_msduq_allocated: Indicates whether a SAM MSDUQ has - * been allocated for this TQM MSDUQ. - * b'17:5 - sam_msduq_id: The SAM MSDUQ ID assigned by the host for - * this TQM MSDUQ. The value in this field is ignored if - * sam_msduq_allocated is 0. - * b'19:18 - sam_msduq_priority: The SAM priority assigned by the - * host. A SAM priority MUST ALWAYS be provided for chipsets - * that have SAM support, regardless of whether or not a SAM - * MSDUQ has been allocated. - * b'20:20 - sam_msduq_sched_eligible: Indicates that this SAM MSDUQ - * is eligible for autonomous SAM scheduling. The value in - * this field is ignored if sam_msduq_allocated is 0. - * b'31:21 – reserved - * Additional reserved dwords for future use cases - */ - -/* - * Enum describes the various msduq/mpduq types, - * First 8 types correspond to the standard msduq types for data - * Next come custom flows for specific purposes. - * Values 23-29 will be used for MGMT flows. - * The value 30 is reserved for mpduq type - */ -typedef enum { - HTT_H2T_TID_MSDUQ_NONUDP, /* 0 */ - HTT_H2T_TID_MSDUQ_UDP, /* 1 */ - HTT_H2T_TID_MSDUQ_CUSTOM_0, /* 2 */ - HTT_H2T_TID_MSDUQ_CUSTOM_1, /* 3 */ - HTT_H2T_TID_MSDUQ_CUSTOM_2, /* 4 */ - HTT_H2T_TID_MSDUQ_CUSTOM_3, /* 5 */ - HTT_H2T_TID_MSDUQ_CUSTOM_4, /* 6 */ - HTT_H2T_TID_MSDUQ_CUSTOM_5, /* 7 */ - - HTT_H2T_TID_MISC_MSDUQ_TYPE_START, /* 8 */ - HTT_H2T_TID_MSDUQ_HOL = HTT_H2T_TID_MISC_MSDUQ_TYPE_START, /* also 8 */ - HTT_H2T_TID_MSDUQ_MCAST, /* 9 */ - HTT_H2T_TID_MSDUQ_FAST_ROAMING, /* 10 */ - - HTT_H2T_TID_MSDUQ_DATA_TYPE_END = 23, /* 23 */ - - HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_0, /* 24 */ - HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_1, /* 25 */ - HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_2, /* 26 */ - HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_3, /* 27 */ - HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_4, /* 28 */ - HTT_H2T_TID_MSDUQ_MGMT_LINK_AGNOSTIC, /* 29 */ - - HTT_H2T_TID_MPDUQ_TYPE, /* 30 */ - HTT_H2T_TID_MSDUQ_MPDUQ_TYPE_END, /* 31 */ -} HTT_H2T_TID_MSDUQ_MPDUQ_TYPE; - -/* - * Enum to denote tid nums that can be used - * first 8 {0 - 7} numbers correspond to data access category - * {8 - 15} are for user defined usecases - * 16 is used to denote the non-qos tid - */ -typedef enum { - HTT_H2T_DEFAULT_TID_NUM = 0, - HTT_H2T_MAX_VALID_DATA_TID_NUM = 7, - HTT_H2T_NON_QOS_TID_NUM = 16, - HTT_H2T_MAX_TID_NUM = 31, -} H2T_TX_TID; - -typedef enum { - HTT_SAWF_SVC_INST_CREATE_REQ = 0, - HTT_SAWF_SVC_INST_DEACTIVATE_REQ, - HTT_SAWF_SVC_INST_REACTIVATE_REQ, - HTT_SAWF_SVC_INST_DELETE_REQ, -} HTT_SAWF_SVC_INST_REQ_TYPE; - -/* HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO */ -PREPACK struct htt_h2t_mpduq_or_msduq_info { - A_UINT32 msg_type: 8, /* bits 7:0 */ - msduq_mpduq_type: 5, /* bits 12:8 */ - hw_link_id: 4, /* bits 16:13 */ - reserved0: 15; /* bits 31:17 */ - - union { - struct { - A_UINT32 mpduq_address_39_8; /* bits 31:0 */ - A_UINT32 mpduq_number: 24, /* bits 23:0 */ - pn_addr_39_32: 8; /* bits 31:24 */ - A_UINT32 pn_addr_31_0; /* bits 31:0 */ - A_UINT32 sam_mpduq_allocated: 1, /* bit 0 */ - sam_mpduq_id: 11, /* bits 11:1 */ - sam_mpduq_priority: 2, /* bits 13:12 */ - sam_mpduq_sched_eligible: 1, /* bit 14 */ - reserved1a: 17; /* bits 31:15 */ - A_UINT32 reserved1b; /* bits 31:0 */ - A_UINT32 reserved1c; /* bits 31:0 */ - A_UINT32 reserved1d; /* bits 31:0 */ - A_UINT32 reserved1e; /* bits 31:0 */ - A_UINT32 reserved1f; /* bits 31:0 */ - }; - struct { - A_UINT32 tx_msduq_number: 24, /* bits 23:0 */ - svc_class_id: 8; /* bits 31:24 */ - A_UINT32 msduq_address_39_8; /* bits 31:0 */ - A_UINT32 svc_inst_req_type_valid: 1, /* bit 0 */ - /* svc_inst_req_type: - * contains a HTT_SAWF_SVC_INST_REQ_TYPE value - */ - svc_inst_req_type: 3, /* bits 3:1 */ - sam_msduq_allocated: 1, /* bit 4 */ - sam_msduq_id: 13, /* bits 17:5 */ - sam_msduq_priority: 2, /* bits 19:18 */ - sam_msduq_sched_eligible: 1, /* bit 20 */ - reserved2a: 11; /* bits 31:21 */ - A_UINT32 reserved2b; /* bits 31:0 */ - A_UINT32 reserved2c; /* bits 31:0 */ - A_UINT32 reserved2d; /* bits 31:0 */ - A_UINT32 reserved2e; /* bits 31:0 */ - A_UINT32 reserved2f; /* bits 31:0 */ - A_UINT32 reserved2g; /* bits 31:0 */ - }; - }; -} POSTPACK; - -/* MPDUQ/MSDUQ shared fields of HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO */ - -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_M 0x00001F00 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_S 8 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_M 0x0001E000 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_S 13 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_S)); \ - } while (0) - - -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_M 0x00000FFF -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_S 0 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_M 0x0001F000 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_S 12 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_S)); \ - } while (0) - - -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_M 0x003E0000 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_S 17 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_S)); \ - } while (0) - - -/* MPDUQ Variant of HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO */ - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_M 0xFFFFFFFF -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_S 0 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_S)); \ - } while (0) - - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER_M 0x00FFFFFF -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER_S 0 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER_GET(_var) \ - (((_var) & HTT_H2T_MSG_MPDUQ_INFO_MPDUQ_NUMBER_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER_S)); \ - } while (0) - - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_M 0xFF000000 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_S 24 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_M 0xFFFFFFFF -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_S 0 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_M 0x00000001 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_S 0 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_M 0x00000FFE -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_S 1 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_M 0x00003000 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_S 12 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_M 0x00004000 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_S 14 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_S)); \ - } while (0) - - -/* MSDUQ Variant of HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO */ - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_M 0x00FFFFFF -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_S 0 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_M 0xFF000000 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_S 24 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_M 0xFFFFFFFF -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_S 0 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_M 0x00000001 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_S 0 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_M 0x0000000E -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_S 1 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_M 0x00000010 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_S 4 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_M 0x0003FFE0 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_S 5 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_M 0x000C0000 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_S 18 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_M 0x00100000 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_S 20 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_S)); \ - } while (0) - - -/* - * @brief host -> target HTT_AST_INFO message - * - * MSG_TYPE => HTT_H2T_MSG_TYPE_AST_INFO - * - * The message would appear as follows: - * |31 24|23 21|20|19|18|17|16|15 8|7 0| - * |--------------+-------------------------------------+-------------------| - * |ast_max_search| ast_table_size | msg_type | - * |------------------------------------------------------------------------| - * | ast_base_addr_31_0 | - * |------------------------------------------------------------------------| - * | ase_hash_key1 | - * |------------------------------------------------------------------------| - * | ase_hash_key2 | - * |------------------------------------------------------------------------| - * | ase_hash_key3 | - * |--------------------+--+--+--+--+--+----------------+-------------------| - * | reserved |L |K |J |I |H | tmo |ast_base_addr_39_32| - * |--------------------+--+--+--+--+--+----------------+-------------------| - * - * The message is interpreted as follows: - * dword0 b'7:0 - msg_type - * 0 b'23:8 - ast table size - * b'31:24 - ast max search - * dword1 - b'31:0 - ast table base address - * dword2 - b'31:0 - ase hash key 1 - * dword3 - b'31:0 - ase hash key 2 - * dword4 - b'31:0 - ase hash key 3 - * dword5 - b'7:0 - ast_base_addr_39_32 - * b'15:8 - ast_timeout_threshold - * b'16 - H - ast cache disable knob - * b'17 - I - ast cache faluires disable knob - * b'18 - J - ast cache cmd read bypass - * Bypassing the reads from memory when an entry is not - * found in cache, in case of full cache commands, - * write back or invalidate commands. - * b'19 - K - ast cache write back fx - * If this fix is disabled, then any write back command - * for a cache line will also lead to invalidation of - * that cache line. - * b'20 - L - ast cache only entry command fix - * If enabled, a new cache entry will always be created - * for requests for which matching data was found - * neither in cache nor in memory. - */ -PREPACK struct htt_ast_info_t { - A_UINT32 msg_type: 8, - ast_table_size: 16, /* number of entries in AST */ - ast_max_search: 8; - A_UINT32 ast_base_addr; /* base address of the AST table */ - A_UINT32 ase_hash_key1; - A_UINT32 ase_hash_key2; - A_UINT32 ase_hash_key3; - A_UINT32 ast_base_addr_39_32: 8, /* 7:0 */ - ast_timeout_threshold: 8, /* 15:8 */ - ast_cache_disable: 1, /* 16 */ - ast_cache_failures_disable: 1, /* 17 */ - ast_cache_cmd_read_bypass_dis: 1, /* 18 */ - ast_cache_write_back_fix_dis: 1, /* 19 */ - ast_cache_only_entry_cmd_fix_dis: 1, /* 20 */ - reserved: 11; -} POSTPACK; - - -#define HTT_AST_INFO_SZ (sizeof(struct htt_ast_info_t)) - -/* DWORD0 */ -#define HTT_AST_INFO_AST_TABLE_SIZE_M 0x00ffff00 -#define HTT_AST_INFO_AST_TABLE_SIZE_S 8 -#define HTT_AST_INFO_AST_TABLE_SIZE_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_TABLE_SIZE_M) >> \ - HTT_AST_INFO_AST_TABLE_SIZE_S) -#define HTT_AST_INFO_AST_TABLE_SIZE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_TABLE_SIZE, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_TABLE_SIZE__S)); \ - } while (0) - -#define HTT_AST_INFO_AST_MAX_SEARCH_M 0xff000000 -#define HTT_AST_INFO_AST_MAX_SEARCH_S 24 -#define HTT_AST_INFO_AST_MAX_SEARCH_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_MAX_SEARCH_M) >> \ - HTT_AST_INFO_AST_MAX_SEARCH_S) -#define HTT_AST_INFO_AST_MAX_SEARCH_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_MAX_SEARCH, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_MAX_SEARCH_S)); \ - } while (0) - - -/* DWORD5 */ - -#define HTT_AST_INFO_AST_BASE_ADDR_39_32_M 0x000000ff -#define HTT_AST_INFO_AST_BASE_ADDR_39_32_S 0 -#define HTT_AST_INFO_AST_BASE_ADDR_39_32_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_BASE_ADDR_39_32_M) >> \ - HTT_AST_INFO_AST_BASE_ADDR_39_32_S) -#define HTT_AST_INFO_AST_BASE_ADDR_39_32_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_BASE_ADDR_39_32, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_BASE_ADDR_39_32_S)); \ - } while (0) - -#define HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_M 0x0000ff00 -#define HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_S 8 -#define HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_M) >> \ - HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_S) -#define HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_TIMEOUT_THRESHOLD, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_S)); \ - } while (0) - -#define HTT_AST_INFO_AST_CACHE_DISABLE_M 0x00010000 -#define HTT_AST_INFO_AST_CACHE_DISABLE_s 16 -#define HTT_AST_INFO_AST_CACHE_DISABLE_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_CACHE_DISABLE_M) >> \ - HTT_AST_INFO_AST_CACHE_DISABLE_s) -#define HTT_AST_INFO_AST_CACHE_DISABLE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_CACHE_DISABLE, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_CACHE_DISABLE_S)); \ - } while (0) - -#define HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_M 0x00020000 -#define HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_s 17 -#define HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_M) >> \ - HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_s) -#define HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_S)); \ - } while (0) - -#define HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_M 0x00040000 -#define HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_s 18 -#define HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_M) >> \ - HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_s) -#define HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_S)); \ - } while (0) - -#define HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_M 0x00080000 -#define HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_s 19 -#define HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_M) >> \ - HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_s) -#define HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_S)); \ - } while (0) - -#define HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_M 0x00100000 -#define HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_s 20 -#define HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_M) >> \ - HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_s) -#define HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_S)); \ - } while (0) - - -/* - * @brief host -> target HTT_H2T_MSG_TYPE_DAL_MODE_INFO message - * - * MSG_TYPE => HTT_H2T_MSG_TYPE_DAL_MODE_INFO (0x2C) - * - * The message would appear as follows: - * |31 16|15 8|7 0| - * |--------------------+-----------------+-------------------| - * | mode | pdev_id | msg_type | - * |----------------------------------------------------------| - * | write_data_addr_lo | - * |----------------------------------------------------------| - * | write_data_addr_hi | - * |----------------------------------------------------------| - * | write_msi_addr_lo | - * |----------------------------------------------------------| - * | write_msi_addr_hi | - * |----------------------------------------------------------| - * | write_msi_data | - * |----------------------------------------------------------| - * - * The message is interpreted as follows: - * dword0 - b'7:0 - msg_type - * b'15:8 - pdev_id - * b'31:16 - mode - * dword1 - b'31:0 - write_data_addr_lo - * dword2 - b'31:0 - write_data_addr_hi - * dword3 - b'31:0 - write_msi_addr_lo - * dword4 - b'31:0 - write_msi_addr_hi - * dword5 - b'31:0 - write_msi_data - */ -PREPACK struct htt_h2t_msg_dal_mode_info { - A_UINT32 msg_type: 8, - pdev_id: 8, - mode: 16; - A_UINT32 write_data_addr_lo; - A_UINT32 write_data_addr_hi; - A_UINT32 write_msi_addr_lo; - A_UINT32 write_msi_addr_hi; - A_UINT32 write_msi_data; -} POSTPACK; - -#define HTT_H2T_MSG_DAL_MODE_INFO_SZ (sizeof(struct htt_h2t_msg_dal_mode_info)) - -/* DWORD0 */ -#define HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_M 0x0000ff00 -#define HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_S 8 - -#define HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_GET(_var) \ - (((_var) & HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_M) >> \ - HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_S) -#define HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_S)); \ - } while (0) - -#define HTT_H2T_MSG_DAL_MODE_INFO_MODE_M 0xffff0000 -#define HTT_H2T_MSG_DAL_MODE_INFO_MODE_S 16 - -#define HTT_H2T_MSG_DAL_MODE_INFO_MODE_GET(_var) \ - (((_var) & HTT_H2T_MSG_DAL_MODE_INFO_MODE_M) >> \ - HTT_H2T_MSG_DAL_MODE_INFO_MODE_S) -#define HTT_H2T_MSG_DAL_MODE_INFO_MODE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_DAL_MODE_INFO_MODE, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_DAL_MODE_INFO_MODE_S)); \ - } while (0) - /*=== target -> host messages ===============================================*/ @@ -13195,9 +11659,6 @@ enum htt_t2h_msg_type { HTT_T2H_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP_DONE = 0x3b, HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND = 0x3c, HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ = 0x3d, - HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP = 0x3e, - HTT_T2H_MSG_TYPE_HAPS = 0x3f, - HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP = 0x40, HTT_T2H_MSG_TYPE_TEST, @@ -16200,41 +14661,40 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t * with, so that the host can use that MLO peer ID to determine which peer * transmitted the rx frame. * - * |31 |29 27|26|25|24|23 20|19 17|16|15 8|7 0| - * |--------------------------------------------------------------------------| - * |RSVD | PRC | NUMLINK| MLO peer ID | msg type | - * |--------------------------------------------------------------------------| - * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | - * |--------------------------------------------------------------------------| - * | RSVD_25_31 |CV| CLASS_INFO_IDX | MAC addr 5 | MAC addr 4 | - * |--------------------------------------------------------------------------| - * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 0 | - * |--------------------------------------------------------------------------| - * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 1 | - * |--------------------------------------------------------------------------| - * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 2 | - * |--------------------------------------------------------------------------| - * |RSVD | - * |--------------------------------------------------------------------------| - * |RSVD | - * |--------------------------------------------------------------------------| - * | htt_tlv_hdr_t | - * |--------------------------------------------------------------------------| - * |RSVD_27_31 | CHIPID | VDEVID | SW peer ID | - * |--------------------------------------------------------------------------| - * | htt_tlv_hdr_t | - * |--------------------------------------------------------------------------| - * |RSVD_27_31 | CHIPID | VDEVID | SW peer ID | - * |--------------------------------------------------------------------------| - * | htt_tlv_hdr_t | - * |--------------------------------------------------------------------------| - * |RSVD_27_31 | CHIPID | VDEVID | SW peer ID | - * |--------------------------------------------------------------------------| + * |31 |29 27|26 24|23 20|19 17|16|15 8|7 0| + * |-------------------------------------------------------------------------| + * |RSVD | PRC |NUMLINK| MLO peer ID | msg type | + * |-------------------------------------------------------------------------| + * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | + * |-------------------------------------------------------------------------| + * | RSVD_16_31 | MAC addr 5 | MAC addr 4 | + * |-------------------------------------------------------------------------| + * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 0 | + * |-------------------------------------------------------------------------| + * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 1 | + * |-------------------------------------------------------------------------| + * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 2 | + * |-------------------------------------------------------------------------| + * |RSVD | + * |-------------------------------------------------------------------------| + * |RSVD | + * |-------------------------------------------------------------------------| + * | htt_tlv_hdr_t | + * |-------------------------------------------------------------------------| + * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | + * |-------------------------------------------------------------------------| + * | htt_tlv_hdr_t | + * |-------------------------------------------------------------------------| + * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | + * |-------------------------------------------------------------------------| + * | htt_tlv_hdr_t | + * |-------------------------------------------------------------------------| + * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | + * |-------------------------------------------------------------------------| * * Where: * PRC - Primary REO CHIPID - 3 Bits Bit24,25,26 * NUMLINK - NUM_LOGICAL_LINKS - 3 Bits Bit27,28,29 - * CV - CLASSIFY_INFO_IDX_VALID - 1 Bit Bit24 * V (valid) - 1 Bit Bit17 * CHIPID - 3 Bits * TIDMASK - 8 Bits @@ -16274,16 +14734,6 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t * Purpose: Identifies which peer node the peer ID is for. * Value: upper 2 bytes of peer node's MAC address * - * - CLASS_INFO_IDX - * Bits 23:16 - * Purpose: Classify info index assists TCL-L Block in certain families of - * WLAN chips to start finding the flow from the corresponding - * entry in the FLOW LOOK UP TABLE in MLO case - * - CV (CLASS_INFO_IDX_VALID) - * Bit 24 - * Purpose: if set indicates that the CLASS_INFO_IDX is valid, - * else ignore the value reported - * * - PRIMARY_TCL_AST_IDX * Bits 15:0 * Purpose: Primary TCL AST index for this peer. @@ -16355,11 +14805,6 @@ typedef enum { #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_M 0x0000ffff #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_S 0 -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_M 0x00ff0000 -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_S 16 -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_M 0x01000000 -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_S 24 - #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_M 0x0000ffff #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S 0 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_M 0x00010000 @@ -16408,30 +14853,6 @@ typedef enum { #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_GET(word) \ (((word) & HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M) >> HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S) -#define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID, value); \ - (word) |= (value) << HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S; \ - } while (0) -#define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_GET(word) \ - (((word) & HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M) >> HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S) - -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX, value); \ - (word) |= (value) << HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_S; \ - } while (0) -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_GET(word) \ - (((word) & HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_M) >> HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_S) - -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG, value); \ - (word) |= (value) << HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_S; \ - } while (0) -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_GET(word) \ - (((word) & HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_M) >> HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_S) - #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_SET(word, value) \ do { \ HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX, value); \ @@ -16514,8 +14935,6 @@ typedef enum { #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */ -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_OFFSET 8 /* bytes */ -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_OFFSET 8 /* bytes */ #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_0_OFFSET 12 /* bytes */ #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_1_OFFSET 16 /* bytes */ #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_2_OFFSET 20 /* bytes */ @@ -20976,7 +19395,6 @@ typedef enum { HTT_PEER_CFR_CAPTURE_BW_80MHZ = 2, HTT_PEER_CFR_CAPTURE_BW_160MHZ = 3, HTT_PEER_CFR_CAPTURE_BW_80_80MHZ = 4, - HTT_PEER_CFR_CAPTURE_BW_320MHZ = 5, HTT_PEER_CFR_CAPTURE_BW_MAX, } HTT_PEER_CFR_CAPTURE_BW; @@ -22452,23 +20870,20 @@ PREPACK struct htt_rx_peer_metadata_v1 { * * The following diagram shows the format of the RX PEER METADATA V1A format. * - * |31 |29|28 26|25 22|21 14| 13 |12 0| - * |----------------------------------------------------------------------| - * |Rsvd2|PT|CHIP ID|logical_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| - * |----------------------------------------------------------------------| - * Where: - * PT = passthrough packet + * |31 29|28 26|25 22|21 14| 13 |12 0| + * |-------------------------------------------------------------------| + * |Rsvd2|CHIP ID|logical_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| + * |-------------------------------------------------------------------| */ PREPACK struct htt_rx_peer_metadata_v1a { A_UINT32 - peer_id: 13, - ml_peer_valid: 1, - vdev_id: 8, - logical_link_id: 4, - chip_id: 3, - qdata_refill: 1, - passthru_pkt: 1, - qdata_consent_pkt: 1; + peer_id: 13, + ml_peer_valid: 1, + vdev_id: 8, + logical_link_id: 4, + chip_id: 3, + qdata_refill: 1, + reserved2: 2; } POSTPACK; #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_S 0 @@ -22537,28 +20952,6 @@ PREPACK struct htt_rx_peer_metadata_v1a { ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_S)); \ } while (0) -#define HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_S 30 -#define HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_M 0x40000000 -#define HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_M) >> HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_S) - -#define HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_S 31 -#define HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_M 0x80000000 -#define HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_M) >> HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_S) - -#define HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_S)); \ - } while (0) - /** * @brief target -> RX PEER METADATA V1B format @@ -22569,10 +20962,10 @@ PREPACK struct htt_rx_peer_metadata_v1a { * * The following diagram shows the format of the RX PEER METADATA V1B format. * - * |31 |30 29|28 26|25 22|21 14| 13 |12 0| - * |--------------------------------------------------------------------| - * |Rsvd2|DECAP|CHIP ID|hw_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| - * |--------------------------------------------------------------------| + * |31 29|28 26|25 22|21 14| 13 |12 0| + * |--------------------------------------------------------------| + * |Rsvd2|CHIP ID|hw_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| + * |--------------------------------------------------------------| */ PREPACK struct htt_rx_peer_metadata_v1b { A_UINT32 @@ -22581,8 +20974,7 @@ PREPACK struct htt_rx_peer_metadata_v1b { vdev_id: 8, hw_link_id: 4, chip_id: 3, - decap_type: 2, - reserved2: 1; + reserved2: 3; } POSTPACK; #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_S 0 @@ -22640,138 +21032,6 @@ PREPACK struct htt_rx_peer_metadata_v1b { ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S)); \ } while (0) -#define HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_S 29 -#define HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_M 0x60000000 -#define HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_M) >> HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_S) - -#define HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_S)); \ - } while (0) - -/* - * htt_rx_peer_metadata_v2 - HTT RX peer metadata version 2 - * - * |31 22|21|20 13|12|11 9|8 6| 5 |4 0| - * |---------+--+--------+--+-----+-----+-----+-----| - * |reserved |PT|peer |Q | Log |VDEV | ML |Peer | - * | | |session |D |Link | ID |Peer | ID | - * | | |ID |R | ID | |Valid| | - * |---------+--+--------+--+-----+-----+-----+-----| - * Where: - * QDR = queue data refill - * PT = passthrough packet - */ -PREPACK struct htt_rx_peer_metadata_v2 { - A_UINT32 - peer_id: 5, - ml_peer_valid: 1, - vdev_id: 3, - logical_link_id: 3, - qdata_refill: 1, - peer_session_id: 8, - passthru_pkt: 1, - qdata_consent_pkt: 1, - reserved: 9; -} POSTPACK; - -#define HTT_RX_PEER_META_DATA_V2_PEER_ID_S 0 -#define HTT_RX_PEER_META_DATA_V2_PEER_ID_M 0x0000001f - -#define HTT_RX_PEER_META_DATA_V2_PEER_ID_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_PEER_ID_M) >> \ - HTT_RX_PEER_META_DATA_V2_PEER_ID_S) -#define HTT_RX_PEER_META_DATA_V2_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_PEER_ID_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_S 5 -#define HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_M 0x00000020 -#define HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_M) >> \ - HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_S) -#define HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_VDEV_ID_S 6 -#define HTT_RX_PEER_META_DATA_V2_VDEV_ID_M 0x000001c0 - -#define HTT_RX_PEER_META_DATA_V2_VDEV_ID_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_VDEV_ID_M) >> \ - HTT_RX_PEER_META_DATA_V2_VDEV_ID_S) -#define HTT_RX_PEER_META_DATA_V2_VDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_VDEV_ID_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_S 9 -#define HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_M 0x00000e00 - -#define HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_M) >> \ - HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_S) -#define HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_S 12 -#define HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_M 0x00001000 - -#define HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_M) >> \ - HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_S) -#define HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_QDATA_REFILL, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_S 13 -#define HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_M 0x001fe000 - -#define HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_M) >> \ - HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_S) -#define HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_S 21 -#define HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_M 0x00200000 - -#define HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_M) >> \ - HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_S) -#define HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_S 22 -#define HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_M 0x00400000 -#define HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_M) >> HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_S) - -#define HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_S)); \ - } while (0) - - /* generic variables for masks and shifts for various fields */ extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_S; extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_M; @@ -22804,15 +21064,6 @@ extern void (*HTT_RX_PEER_META_DATA_HW_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val extern A_UINT32 (*HTT_RX_PEER_META_DATA_QDATA_REFILL_GET) (A_UINT32 var); extern void (*HTT_RX_PEER_META_DATA_QDATA_REFILL_SET) (A_UINT32 *var, A_UINT32 val); -extern A_UINT32 (*HTT_RX_PEER_META_DATA_PEER_SESSION_ID_GET) (A_UINT32 var); -extern void (*HTT_RX_PEER_META_DATA_PEER_SESSION_ID_SET) (A_UINT32 *var, A_UINT32 val); - -extern A_UINT32 (*HTT_RX_PEER_META_DATA_DECAP_TYPE_GET) (A_UINT32 var); -extern void (*HTT_RX_PEER_META_DATA_DECAP_TYPE_SET) (A_UINT32 *var, A_UINT32 val); - -extern A_UINT32 (*HTT_RX_PEER_META_DATA_PASSTHRU_PKT_GET) (A_UINT32 var); -extern void (*HTT_RX_PEER_META_DATA_PASSTHRU_PKT_SET) (A_UINT32 *var, A_UINT32 val); - /* * In some systems, the host SW wants to specify priorities between @@ -22859,25 +21110,18 @@ enum HTT_MSDU_QTYPE { HTT_MSDU_QTYPE_HI_PRIO, /* Specifies MSDUQ index used for high priority flow type */ HTT_MSDU_QTYPE_LO_PRIO, /* Specifies MSDUQ index used for low priority flow type */ - HTT_MSDU_QTYPE_MAX, /* legacy limit (based on ROM compatibility) */ - - HTT_MSDU_QTYPE_LATENCY_CRIT_2, - HTT_MSDU_QTYPE_LATENCY_CRIT_3, - HTT_MSDU_QTYPE_LATENCY_CRIT_4, - HTT_MSDU_QTYPE_LATENCY_CRIT_5, /* New MSDU_QTYPE should be added above this line */ /* - * Below QTYPE_MAX_EXT will increase if additional QTYPEs are defined - * in the future. Hence HTT_MSDU_QTYPE_MAX_EXT can't be used in - * any host/target message definitions. The QTYPE_MAX_EXT value can + * Below QTYPE_MAX will increase if additional QTYPEs are defined + * in the future. Hence HTT_MSDU_QTYPE_MAX can't be used in + * any host/target message definitions. The QTYPE_MAX value can * only be used internally within the host or within the target. - * If host or target find a qtype value is >= HTT_MSDU_QTYPE_MAX_EXT + * If host or target find a qtype value is >= HTT_MSDU_QTYPE_MAX * it must regard the unexpected value as a default qtype value, * or ignore it. */ - HTT_MSDU_QTYPE_MAX_EXT, - + HTT_MSDU_QTYPE_MAX, HTT_MSDU_QTYPE_NOT_IN_USE = 255, /* corresponding MSDU index is not in use */ }; @@ -25205,228 +23449,4 @@ PREPACK struct htt_t2h_mlo_latency_req_t { } while (0) -/* MSG_TYPE => HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP - * - * The following diagram shows the format of the global peer unmap message sent - * from the target to the host. This message is used to send unmap event to host - * after tid and msduq/mpduq cleanup in FW, host cleans up msduq/mpduq based on - * message. - * - * |31 24|23 20|19 8|7 0| - * |-----------------------------------------------------------------------| - * | reserved | hw_link_id | global_peer_id | msg type | - * |-----------------------------------------------------------------------| - * @details - * struct htt_t2h_global_peer_id_unmap_t: - * - * The message is interpreted as follows: - * dword0 - b'7:0 - msg_type: Identifies a request for MLO latency stats - * This will be set to 0x3e - * (HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP) - * b'19:8 - global_peer_id : global peer id assigned by host - * b'23:20 - hw_link_id : hw link id for which unmap is being sent - * - */ - - -/* HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP */ -PREPACK struct htt_t2h_global_peer_id_unmap_t { - A_UINT32 msg_type: 8, /* bits 7:0 */ - global_peer_id: 12, /* bits 19:8 */ - hw_link_id: 4, /* bits 23:20 */ - reserved: 8; /* bits 31:16 */ -} POSTPACK; - -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_M 0x000FFF00 -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_S 8 -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_GET(_var) \ - (((_var) & HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_M) >> \ - HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_S) -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_S)); \ - } while (0) - -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_M 0x00F00000 -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_S 20 -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_GET(_var) \ - (((_var) & HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_M) >> \ - HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_S) -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID, _val); \ - ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_S)); \ - } while (0) - - -/* - * @brief target -> pause/unpause host tx queues based on FW indication - * MSG_TYPE => HTT_T2H_MSG_TYPE_HAPS - * - * @details * Header fields: - * - * |31 22|21 20|19 16|15 8|7 0| - * |---------+-------------+-----------+------------------+---------------| - * | RSVD |time_type |action_code| vdev_id | msg type | - * |----------------------------------------------------------------------| - * | time_high | - * |----------------------------------------------------------------------| - * | time_low | - * |----------------------------------------------------------------------| - * - * dword0 - b'7:0 - msg_type: This will be set to - * 0x3f (HTT_T2H_MSG_TYPE_HAPS) - * b'15:8 - vdev_id - * b'19:16 - action_code (HTT_T2H_HAPS_ACTION_CODE): - * b'0000: Pause - * b'0001: Pause with One-Shot Unpause - * b'0010: Unpause - * values 3-15: reserved - * b'21:20 - time_type - * b'31:22 - rsvd - * reverse action_code at time specified below - * (units are specified by the type_type bitfield) - * dword1 - b'31:0 uint32_t time_high - * dword2 - b'31:0 uint32_t time_low - */ -typedef enum { - HTT_T2H_HAPS_ACTION_PAUSE = 0x00, - HTT_T2H_HAPS_ACTION_PAUSE_WITH_ONESHOT_UNPAUSE = 0x01, - HTT_T2H_HAPS_ACTION_UNPAUSE = 0x02, -} HTT_T2H_HAPS_ACTION_CODE; - -typedef enum { - HTT_T2H_HAPS_TIME_TYPE_HOST_QTIME = 0x00, - HTT_T2H_HAPS_TIME_TYPE_TSF = 0x01, -} HTT_T2H_HAPS_TIME_TYPE; - -PREPACK struct htt_t2h_power_state_info { - uint32_t msg_type : 8, /* [7:0] */ - vdev_id : 8, /* [15:8] */ - action_code : 4, /* [19:16] */ - time_type: 2, /* [21:20] */ - rsvd: 10; /* [31:22] */ - uint32_t time_low; - uint32_t time_high; -} POSTPACK; - -#define HTT_T2H_POWER_STATE_INFO_SIZE (sizeof(struct htt_t2h_power_state_info)) - -#define HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_M 0x0000FF00 -#define HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_S 8 - -#define HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_GET(_var) \ - (((_var) & HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_M) >> \ - HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_S) -#define HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_S));\ - } while (0) - -#define HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_M 0x000F0000 -#define HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_S 16 - -#define HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_GET(_var) \ - (((_var) & HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_M) >> \ - HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_S) -#define HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE, _val); \ - ((_var) |= ((_val) << HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_S));\ - } while (0) - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_M 0x00300000 -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_S 20 - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_GET(_var) \ - (((_var) & HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_M) >> \ - HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_S) - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE, _val); \ - ((_var) |= ((_val) << HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_S));\ - } while (0) - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_M 0xFFFFFFFF -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_S 0 - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_GET(_var) \ - (((_var) & HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_M) >> \ - HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_S) - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH, _val); \ - ((_var) |= ((_val) << HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_S));\ - } while (0) - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_M 0xFFFFFFFF -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_S 0 - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_GET(_var) \ - (((_var) & HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_M) >> \ - HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_S) - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW, _val); \ - ((_var) |= ((_val) << HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_S));\ - } while (0) - - -/* MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP - * - * The following diagram shows the format of the peer delete all global vdev - * unmap message sent from the target to the host. This message is used to - * send unmap event to host after tid and msduq/mpduq cleanup of all peers - * associated to a vdev, in FW, host cleans up msduq/mpduq based on message. - * - * |31 20|19 16|15 8|7 0| - * |------------------------+----------+-----------------+-----------------| - * | reserved |hw_link_id| global_vdev_id | msg type | - * |-----------------------------------------------------------------------| - * @details - * struct htt_t2h_peer_del_all_global_vdev_id_unmap_t: - * - * The message is interpreted as follows: - * dword0 - b'7:0 - msg_type: This will be set to 0x40 - * (HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP) - * b'15:8 - global_vdev_id : global vdev id assigned by host - * b'19:16 - hw_link_id : hw link id for which unmap is being sent - * b'31:20 - reserved - */ -/* HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP */ -PREPACK struct htt_t2h_peer_del_all_global_vdev_id_unmap_t { - A_UINT32 msg_type: 8, /* bits 7:0 */ - global_vdev_id: 8, /* bits 15:8 */ - hw_link_id: 4, /* bits 19:16 */ - reserved: 12; /* bits 31:20 */ -} POSTPACK; - -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_M 0x0000FF00 -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_S 8 -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_GET(_var) \ - (((_var) & HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_M) >> \ - HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_S) -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_S)); \ - } while (0) - -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_M 0x000F0000 -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_S 16 -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_GET(_var) \ - (((_var) & HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_M) >> \ - HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_S) -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID, _val); \ - ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_S)); \ - } while (0) - - #endif diff --git a/drivers/staging/fw-api/fw/htt_ppdu_stats.h b/drivers/staging/fw-api/fw/htt_ppdu_stats.h index 7f0fb14620de..d1575d7c91ba 100644 --- a/drivers/staging/fw-api/fw/htt_ppdu_stats.h +++ b/drivers/staging/fw-api/fw/htt_ppdu_stats.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -501,11 +501,6 @@ enum HTT_PPDU_STATS_SEQ_TYPE { HTT_SEQTYPE_BE_UL_MU_OFDMA_TRIG = 13, HTT_SEQTYPE_BE_UL_MU_MIMO_TRIG = 14, HTT_SEQTYPE_BE_UL_BSR_TRIG = 15, - HTT_SEQTYPE_BN_MU_MIMO = 16, - HTT_SEQTYPE_BN_MU_OFDMA = 17, - HTT_SEQTYPE_BN_UL_MU_OFDMA_TRIG = 18, - HTT_SEQTYPE_BN_UL_MU_MIMO_TRIG = 19, - HTT_SEQTYPE_BN_UL_BSR_TRIG = 20, }; typedef enum HTT_PPDU_STATS_SEQ_TYPE HTT_PPDU_STATS_SEQ_TYPE; @@ -712,58 +707,6 @@ typedef enum HTT_PPDU_STATS_SPATIAL_REUSE HTT_PPDU_STATS_SPATIAL_REUSE; (((_val) & HTT_PPDU_STATS_COMMON_TRIG_COOKIE_M) >> \ HTT_PPDU_STATS_COMMON_TRIG_COOKIE_S) -#define HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_M 0x00000001 -#define HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_S 0 - -#define HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_GET(_var) \ - (((_var) & HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_M) >> \ - HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_S) - -#define HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE, _val); \ - ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_S)); \ - } while (0) - -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_M 0x00000002 -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_S 1 - -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_GET(_var) \ - (((_var) & HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_M) >> \ - HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_S) - -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER, _val); \ - ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_S)); \ - } while (0) - -#define HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_M 0x00000004 -#define HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_S 2 - -#define HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_GET(_var) \ - (((_var) & HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_M) >> \ - HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_S) - -#define HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER, _val); \ - ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_S)); \ - } while (0) - -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_M 0x00000008 -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_S 3 - -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_GET(_var) \ - (((_var) & HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_M) >> \ - HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_S) - -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER, _val); \ - ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_S)); \ - } while (0) - enum HTT_SEQ_TYPE { WAL_PPDU_SEQ_TYPE = 0, HTT_PPDU_SEQ_TYPE = 1, @@ -959,57 +902,28 @@ typedef struct { * HTT_PPDU_SEQ_TYPE then decoder should interpret the * seq type as HTT_PPDU_STATS_SEQ_TYPE. * htt_seq_type field will be set to HTT_PPDU_SEQ_TYPE in - * BIT [1 : 1] - is_combined_ul_basic_trigger - Flag to indicate if a - * given UL OFDMA/MU-MIMO Basic trigger is sent combined - * as part of existing DL data sequence. - * BIT [2 : 2] - is_manual_ulofdma_trigger - Flag to indicate if a - * given UL OFDMA trigger is manually triggered from the Host. - * BIT [3 : 3] - is_combined_ul_bsrp_trigger - Flag to indicate if a - * given UL BSRP trigger is sent combined as part of - * an existing DL/UL data sequence - * BIT [4 : 4] - is_sta_dps_seq - Flag to indicate if a TX is to a STA with - * active Dynamic Power Save state (DPS) - * BIT [5 : 5] - is_allow_comb_sched_cmd - Flag to indicate if a given TX - * is part of a allowed combined sched_cmd sequence - * BIT [6 : 6] - is_abort_comb_sched_cmd - Flag to indicate if a given TX - * is part of a aborted combined sched_cmd sequence - * BIT [7 : 7] - is_comb_sched_cmd_pending - Flag to indicate if a the - * first sched_cmd of a combined sched_cmd sequence is - * pending in the current ring. - * BIT [31: 8] - reserved + * firmware versions where this field is defined. + * BIT [31: 1] - reserved */ union { A_UINT32 reserved__htt_seq_type; struct { A_UINT32 htt_seq_type: 1, - is_combined_ul_basic_trigger: 1, - is_manual_ulofdma_trigger: 1, - is_combined_ul_bsrp_trigger: 1, - is_sta_dps_seq: 1, - is_allow_comb_sched_cmd: 1, - is_abort_comb_sched_cmd: 1, - is_comb_sched_cmd_pending: 1, - is_sched_cmd_combined: 1, - reserved3: 23; + reserved3: 31; }; }; + /* is_manual_ulofdma_trigger: + * Flag to indicate if a given UL OFDMA trigger is manually triggered + * from the Host + */ + A_UINT32 is_manual_ulofdma_trigger; + /* is_combined_ul_bsrp_trigger: + * Flag to indicate if a given UL BSRP trigger is sent combined as + * part of existing DL/UL data sequence + */ + A_UINT32 is_combined_ul_bsrp_trigger; /* Flag to indicate if the channel chosen is 320_1 / 320_2 */ A_UINT32 chan_type_320mhz; - - /* - * BIT [15 : 0] - obss_dur_us reports the remaining OBSS dur when - * this FES started OTA. - * BIT [16 : 16] - oprim indicates M/O primary FES. - * BIT [31 : 17] - reserved - */ - union { - A_UINT32 reserved__oprim__obss_dur; - struct { - A_UINT32 obss_dur_us: 16, - oprim: 1, - reserved4: 15; - }; - }; } htt_ppdu_stats_common_tlv; #define HTT_PPDU_STATS_USER_COMMON_TLV_TID_NUM_M 0x000000ff @@ -1974,32 +1888,6 @@ typedef enum HTT_PPDU_STATS_RESP_PPDU_TYPE HTT_PPDU_STATS_RESP_PPDU_TYPE; ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S)); \ } while (0) -#define HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_M 0x00040000 -#define HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_S 18 - -#define HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_GET(_var) \ - (((_var) & HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_M) >> \ - HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_S) - -#define HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_SET (_var , _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_RATE_TLV_2XLDPC, _val); \ - ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_S)); \ - } while (0) - -#define HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_M 0x00080000 -#define HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_S 19 - -#define HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_GET(_var) \ - (((_var) & HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_M) >> \ - HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_S) - -#define HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_SET (_var , _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED, _val); \ - ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_S)); \ - } while (0) - typedef enum HTT_PPDU_STATS_RU_SIZE { HTT_PPDU_STATS_RU_26, HTT_PPDU_STATS_RU_52, @@ -2019,14 +1907,6 @@ typedef enum HTT_PPDU_STATS_RU_SIZE { HTT_PPDU_STATS_RU_996x4, } HTT_PPDU_STATS_RU_SIZE; -typedef enum HTT_PPDU_STATS_DRU_SIZE { - HTT_PPDU_STATS_DRU_26, - HTT_PPDU_STATS_DRU_52, - HTT_PPDU_STATS_DRU_106, - HTT_PPDU_STATS_DRU_242, - HTT_PPDU_STATS_DRU_484, -} HTT_PPDU_STATS_DRU_SIZE; - typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -2064,7 +1944,6 @@ typedef struct { * Discriminant is field ru_format: * - ru_format = 0: ru_end, ru_start * - ru_format = 1: ru_index, ru_size - * - ru_format = 2: dru_index, dru_size, dru_sbw, dru_sbw_idx * - ru_format = other: reserved for future expansion * * ru_start and ru_end are RU 26 indices @@ -2097,15 +1976,10 @@ typedef struct { * * resp_ru_size is an HTT_PPDU_STATS_RU_SIZE, resp_ru_index * is a size specific index for the given ru_size. - * - * 'is_dru' field indicates if the current RU allocation - * is a distributed RU allocation or not. - * 'dru_sbw' is the spreading BW size of current dru_size. */ union { A_UINT32 resp_ru_start__ru_end; A_UINT32 resp_ru_size__ru_index; - A_UINT32 dru_size__dru_index__dru_sbw_idx__dru_sbw__is_dru; struct { A_UINT32 resp_ru_end: 16, resp_ru_start: 16; @@ -2114,14 +1988,6 @@ typedef struct { A_UINT32 resp_ru_index: 16, resp_ru_size: 16; }; - struct { - A_UINT32 is_dru: 1, - dru_sbw: 3, - dru_sbw_idx: 2, - dru_index: 16, - dru_size: 4, - reserved5: 6; - }; }; /* BIT [ 0 : 0 ] :- resp_type_valid @@ -2209,16 +2075,11 @@ typedef struct { * punctured. * BIT 16 :- flag showing whether EHT extra LTF is applied * for current PPDU - * BIT 17 :- flag to show is_min_rate - * BIT 18 :- flag showing whether PPDU is transmitted with 2xLDPC - * BIT 19 :- flag showing whether PPDU is transmitted with NPCA enabled */ A_UINT32 punc_pattern_bitmap: 16, - extra_eht_ltf: 1, - is_min_rate: 1, - is_2xldpc: 1, - is_npca_enabled: 1, - reserved4: 12; + extra_eht_ltf: 1, + is_min_rate: 1, + reserved4: 14; } htt_ppdu_stats_user_rate_tlv; #define HTT_PPDU_STATS_USR_RATE_VALID_M 0x80000000 diff --git a/drivers/staging/fw-api/fw/htt_stats.h b/drivers/staging/fw-api/fw/htt_stats.h index 28d4c2f06ad1..5a57e7f9f171 100644 --- a/drivers/staging/fw-api/fw/htt_stats.h +++ b/drivers/staging/fw-api/fw/htt_stats.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -186,7 +186,6 @@ enum htt_dbg_ext_stats_type { * 7 bit htt_peer_sched_stats_tlv * 8 bit htt_peer_ax_ofdma_stats_tlv * 9 bit htt_peer_be_ofdma_stats_tlv - * 10 bit htt_stats_rx_peer_tid_reo_queue_ba_tlv * - config_param2: [Bit31 : Bit0] mac_addr31to0 * - config_param3: [Bit15 : Bit0] mac_addr47to32 * [Bit 16] If this bit is set, reset per peer stats @@ -681,27 +680,23 @@ enum htt_dbg_ext_stats_type { HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS = HTT_DBG_EXT_STATS_ODD_PDEV_BE_TX_MU_OFDMA, - /** HTT_DBG_EXT_STATS_ODD_UL_BE_BN_OFDMA + /** HTT_DBG_EXT_STATS_ODD_UL_BE_OFDMA * PARAMS: * - No Params * RESP MSG: * - htt_rx_pdev_be_ul_ofdma_user_stats_tlv */ - HTT_DBG_EXT_STATS_ODD_UL_BE_BN_OFDMA = 60, - /* retain deprecated names as aliases */ - HTT_DBG_EXT_STATS_ODD_UL_BE_OFDMA = - HTT_DBG_EXT_STATS_ODD_UL_BE_BN_OFDMA, + HTT_DBG_EXT_STATS_ODD_UL_BE_OFDMA = 60, + /* retain the deprecated name as an alias */ HTT_DBG_ODD_UL_BE_OFDMA_STATS = - HTT_DBG_EXT_STATS_ODD_UL_BE_BN_OFDMA, + HTT_DBG_EXT_STATS_ODD_UL_BE_OFDMA, - /** HTT_DBG_EXT_STATS_ODD_BE_BN_TXBF_OFDMA_STATS + /** HTT_DBG_EXT_STATS_ODD_BE_TXBF_OFDMA */ - HTT_DBG_EXT_STATS_ODD_BE_BN_TXBF_OFDMA_STATS = 61, - /* retain the deprecated names as aliases */ - HTT_DBG_EXT_STATS_ODD_BE_TXBF_OFDMA = - HTT_DBG_EXT_STATS_ODD_BE_BN_TXBF_OFDMA_STATS, + HTT_DBG_EXT_STATS_ODD_BE_TXBF_OFDMA = 61, + /* retain the deprecated name as an alias */ HTT_DBG_ODD_BE_TXBF_OFDMA_STATS = - HTT_DBG_EXT_STATS_ODD_BE_BN_TXBF_OFDMA_STATS, + HTT_DBG_EXT_STATS_ODD_BE_TXBF_OFDMA, /** HTT_DBG_EXT_STATS_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG * PARAMS: @@ -834,141 +829,6 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_ELIGIBLE = 74, - /** HTT_DBG_EXT_STATS_PAPRD_PB - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_phy_paprd_pb_tlv - */ - HTT_DBG_EXT_STATS_PAPRD_PB = 75, - - /** HTT_DBG_EXT_STATS_HDS_PROF - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_hds_prof_stats_tlv - */ - HTT_DBG_EXT_STATS_HDS_PROF = 76, - - /** HTT_DBG_EXT_STATS_OPTIONAL_CONFIGS - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_optional_configs_tlv - */ - HTT_DBG_EXT_STATS_OPTIONAL_CONFIGS = 77, - - /** HTT_DBG_EXT_STATS_PDEV_SAM - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_pdev_sam_tlv - */ - HTT_DBG_EXT_STATS_PDEV_SAM = 78, - - /** HTT_DBG_EXT_STATS_FTM - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_ftm_tlv - */ - HTT_DBG_EXT_STATS_FTM = 79, - - /** HTT_DBG_EXT_STATS_PDEV_FTM_TPCCAL_EXT - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_pdev_ftm_tpccal_ext_tlv - */ - HTT_DBG_EXT_STATS_PDEV_FTM_TPCCAL_EXT = 80, - - /** HTT_DBG_EXT_STATS_ANI_HISTOGRAM - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_phy_ani_hist_tlv - * */ - HTT_DBG_EXT_STATS_ANI_HISTOGRAM = 81, - - /** HTT_DBG_EXT_STATS_RESET_HISTORY - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_reset_history_tlv - */ - HTT_DBG_EXT_STATS_RESET_HISTORY = 82, - - /** HTT_DBG_EXT_STATS_REGULATORY - * PARAMS: - * - config_param0 : Regulatory stats subtype: - * htt_stats_regulatory_subtype_t - * - config_param1 : (Depends on Subtype) - * RESP MSG: - * - * if (subtype == HTT_STATS_REGULATORY_SUBTYPE_REGDB): - * config_param1 - Bitmap of Regdomains to include - * [bit 0 - 2G, - * bit 1 - 5G, - * bit 2 - unused - * bits 3-5 - 6G AP (LPI/SP/VLP) - * bits 6-8 - 6G CLIENT 1 (LPI/SP/VLP) - * bits 9-11- 6G CLIENT 2 (LPI/SP/VLP)] - * RESP Tags: - * - htt_stats_regdb_ctry_tlv - * - htt_stats_regdb_regdomain_tlv * n (based on config_param1) - * else if (subtype == HTT_STATS_REGULATORY_SUBTYPE_6GHZ): - * no params - * RESP Tags: - * - htt_stats_reg_6g_tlv - * - htt_stats_reg_6g_ch_power_info_tlv * n - * - htt_stats_reg_6g_oobe_tlv - * else if (subtype == HTT_STATS_REGULATORY_SUBTYPE_CTL): - * no params - * RESP Tags: - * - htt_stats_ctl_tlv - * - htt_stats_enhanced_ctl_tlv - * else if (subtype == HTT_STATS_REGULATORY_SUBTYPE_DFS): - * no params - * RESP Tags: - * - htt_stats_dfs_radar_history_tlv - * - htt_stats_dfs_ini_tlv - * - htt_stats_dfs_ipc_ring_tlv - */ - HTT_DBG_EXT_STATS_REGULATORY = 83, - - /** HTT_DBG_EXT_STATS_TX_SELFGEN_RESP_FRAME_STATS - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_tx_selfgen_resp_frame_stats_tlv - */ - HTT_DBG_EXT_STATS_TX_SELFGEN_RESP_FRAME_STATS = 84, - - /** HTT_DBG_EXT_STATS_DPD - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_dpd_halphy_tlv - * - htt_stats_dpd_hw_cal_params_tlv - * - htt_stats_dpd_hw_cal_results_tlv - */ - HTT_DBG_EXT_STATS_DPD = 85, - - HTT_DBG_EXT_STATS_NPCA = 86, - - /** HTT_DBG_EXT_STATS_PHY_DPD_TPC_DEBUG - * PARAMS: - * - config_param0: subtype: htt_stats_phy_dpd_tpc_debug_subtype_t - * 0 = DPD debug, 1 = TPC debug - * - config_param1: chain bitmask (0 = default to chain 0 only) - * RESP MSG: - * if (subtype == HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_DPD): - * - htt_stats_phy_dpd_debug_chain_v1_tlv (one per requested chain) - * if (subtype == HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_TPC): - * - htt_stats_phy_tpc_debug_chain_v1_tlv (one per requested chain) - */ - HTT_DBG_EXT_STATS_PHY_DPD_TPC_DEBUG = 87, - /* keep this last */ HTT_DBG_NUM_EXT_STATS = 256, @@ -1041,25 +901,6 @@ typedef enum { * TLV: htt_tx_pdev_ul_be_mu_ofdma_sch_stats_tlv */ HTT_UPLOAD_BE_UL_MU_OFDMA_STATS, - - /* - * Upload BN UL MU-OFDMA + BN DL MU-OFDMA stats, - * TLV: htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv and - * htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv - */ - HTT_UPLOAD_BN_MU_OFDMA_STATS, - - /* - * Upload BN DL MU-OFDMA - * TLV: htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv - */ - HTT_UPLOAD_BN_DL_MU_OFDMA_STATS, - - /* - * Upload BN UL MU-OFDMA - * TLV: htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv - */ - HTT_UPLOAD_BN_UL_MU_OFDMA_STATS, } htt_mu_stats_upload_t; /* htt_tx_rate_stats_upload_t @@ -1074,14 +915,11 @@ typedef enum { HTT_TX_RATE_STATS_DEFAULT, /* - * Upload 11be and 11bn OFDMA TX stats + * Upload 11be OFDMA TX stats * * TLV: htt_tx_pdev_rate_stats_be_ofdma_tlv */ - HTT_TX_RATE_STATS_UPLOAD_11BE_11BN_OFDMA, - /* retain prior name as an alias */ - HTT_TX_RATE_STATS_UPLOAD_11BE_OFDMA = - HTT_TX_RATE_STATS_UPLOAD_11BE_11BN_OFDMA, + HTT_TX_RATE_STATS_UPLOAD_11BE_OFDMA, } htt_tx_rate_stats_upload_t; /* htt_rx_ul_trigger_stats_upload_t @@ -1096,14 +934,11 @@ typedef enum { HTT_RX_UL_TRIGGER_STATS_UPLOAD_11AX_OFDMA, /* - * Upload 11be and 11bn UL OFDMA RX Trigger stats + * Upload 11be UL OFDMA RX Trigger stats * * TLV: htt_rx_pdev_be_ul_trigger_stats_tlv */ - HTT_RX_UL_TRIGGER_STATS_UPLOAD_11BE_11BN_OFDMA, - /* retain prior name as an alias */ - HTT_RX_UL_TRIGGER_STATS_UPLOAD_11BE_OFDMA = - HTT_RX_UL_TRIGGER_STATS_UPLOAD_11BE_11BN_OFDMA, + HTT_RX_UL_TRIGGER_STATS_UPLOAD_11BE_OFDMA, } htt_rx_ul_trigger_stats_upload_t; /* @@ -1124,11 +959,6 @@ typedef enum { * TLV: htt_rx_pdev_ul_mumimo_trig_be_stats_tlv */ HTT_RX_UL_MUMIMO_TRIGGER_STATS_UPLOAD_11BE, - /* - * Upload 11bn UL MUMIMO RX Trigger stats - * TLV: htt_rx_pdev_ul_mumimo_trig_bn_stats_tlv - */ - HTT_RX_UL_MUMIMO_TRIGGER_STATS_UPLOAD_11BN, } htt_rx_ul_mumimo_trigger_stats_upload_t; /* htt_tx_pdev_txbf_ofdma_stats_upload_t @@ -1143,13 +973,11 @@ typedef enum { HTT_UPLOAD_AX_TXBF_OFDMA_STATS, /* - * Upload 11be and 11bn TXBF OFDMA stats + * Upload 11be TXBF OFDMA stats * * TLV: htt_tx_pdev_be_txbf_ofdma_stats_t */ - HTT_UPLOAD_BE_BN_TXBF_OFDMA_STATS, - /* retain previous name as alias */ - HTT_UPLOAD_BE_TXBF_OFDMA_STATS = HTT_UPLOAD_BE_BN_TXBF_OFDMA_STATS, + HTT_UPLOAD_BE_TXBF_OFDMA_STATS, } htt_tx_pdev_txbf_ofdma_stats_upload_t; /* htt_tx_pdev_puncture_stats_upload_t @@ -1174,15 +1002,7 @@ typedef enum { #define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5 #define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10 #define HTT_PDEV_STATS_PPDU_DUR_HIST_BINS 16 -#define HTT_PDEV_STATS_PPDU_DUR_HIST_EXT_BINS 6 #define HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US 250 -/* Max seq ctrl can be active in txq at a given instant */ -#define HTT_PDEV_STATS_MAX_SEQ_CTRL_HIST 4 -/* For BE max active seq_ctrl that can be in HWQ */ -#define HTT_PDEV_STATS_MAX_ACTIVE_SEQ_IN_HWQ_HIST 2 -#define HTT_PDEV_STATS_TXOP_DUR_HIST_BINS 12 -#define HTT_PDEV_STATS_TXOP_DUR_HIST_INTERVAL_US 1000 -#define HTT_PDEV_STATS_MAX_DATA_TID_COUNT 8 typedef enum { HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, @@ -1218,9 +1038,7 @@ typedef struct { #define HTT_TX_PDEV_STATS_CMN_MAC_ID_GET(_var) \ (((_var) & HTT_TX_PDEV_STATS_CMN_MAC_ID_M) >> \ HTT_TX_PDEV_STATS_CMN_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_PDEV_CMN_MAC_ID_GET(_var) \ - HTT_TX_PDEV_STATS_CMN_MAC_ID_GET(_var) + #define HTT_TX_PDEV_STATS_CMN_MAC_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_CMN_MAC_ID, _val); \ @@ -1235,13 +1053,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Num PPDUs queued to HW */ A_UINT32 hw_queued; /** Num PPDUs reaped from HW */ @@ -1419,47 +1231,10 @@ typedef struct { /* upper 32 bits of the tx_bytes value */ A_UINT32 high_32; } bytes_sent; - /* increment array based on AC */ - A_UINT32 num_ppdu_tried_ota_per_ac[HTT_NUM_AC_WMM]; - /** Number of hardware reaped (Tx completed) packets in LPI mode */ - A_UINT32 hw_reaped_lpi; - /** Number of hardware reaped (Tx completed) packets in SP mode */ - A_UINT32 hw_reaped_sp; - /** Number of hardware reaped (Tx completed) packets in VLP mode */ - A_UINT32 hw_reaped_vlp; - A_UINT32 avg_channel_access_latency_per_ac[HTT_NUM_AC_WMM]; /* usec units */ - A_UINT32 seq_posted_per_tid[HTT_PDEV_STATS_MAX_DATA_TID_COUNT]; } htt_stats_tx_pdev_cmn_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_cmn_tlv htt_tx_pdev_stats_cmn_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - A_UINT32 pdev_id__word; - struct { - A_UINT32 - pdev_id: 8, - reserved: 24; - }; - }; - A_UINT32 pending_seq_on_sched_post_hist[HTT_PDEV_STATS_MAX_SEQ_CTRL_HIST]; -} htt_stats_tx_pdev_pending_seq_cnt_on_sched_post_hist_tlv; - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_M 0x000000ff -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_S 0 - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_GET(_var) \ - (((_var) & HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_M) >> \ - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_S) - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_S)); \ - } while (0) - - #define HTT_TX_PDEV_STATS_URRN_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { @@ -1482,13 +1257,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_flush_tlv htt_tx_pdev_stats_flush_tlv_v; -#define HTT_TX_PDEV_MDSB_MAX_NUM_USERS 8 -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 pdev_id; - A_UINT32 mdsb_num_users_histogram[HTT_TX_PDEV_MDSB_MAX_NUM_USERS]; -} htt_stats_tx_pdev_mdsb_num_users_histogram_tlv; - #define HTT_TX_PDEV_STATS_MLO_ABORT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { @@ -1644,11 +1412,6 @@ typedef struct { A_UINT32 mu_mimo_num_seq_posted[HTT_STATS_NUM_NR_BINS]; A_UINT32 mu_mimo_num_ppdu_posted_per_burst[HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST_WORDS]; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_mu_ppdu_dist_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_mu_ppdu_dist_tlv htt_pdev_mu_ppdu_dist_tlv_v; @@ -1698,7 +1461,6 @@ typedef htt_stats_pdev_ctrl_path_tx_stats_tlv htt_pdev_ctrl_path_tx_stats_tlv_v; * - HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG * - HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG * - HTT_STATS_MU_PPDU_DIST_TAG - * - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_TAG */ /* NOTE: * This structure is for documentation, and cannot be safely used directly. @@ -1716,8 +1478,6 @@ typedef struct _htt_tx_pdev_stats { htt_stats_tx_pdev_tried_mpdu_cnt_hist_tlv tried_mpdu_cnt_hist_tlv; htt_stats_pdev_ctrl_path_tx_stats_tlv ctrl_path_tx_tlv; htt_stats_mu_ppdu_dist_tlv mu_ppdu_dist_tlv; - htt_stats_tx_pdev_pending_seq_cnt_on_sched_post_hist_tlv - pending_seq_cnt_on_sched_post_hist_tlv; } htt_tx_pdev_stats_t; #endif /* ATH_TARGET */ @@ -1761,17 +1521,10 @@ typedef htt_stats_hw_wd_timeout_tlv htt_hw_stats_wd_timeout_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /** - * BIT [ 7 : 0] :- mac_id + /* BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 tx_abort; A_UINT32 tx_abort_fail_count; A_UINT32 rx_abort; @@ -1835,23 +1588,13 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_hw_pdev_errs_tlv htt_hw_stats_pdev_errs_tlv; -#define HTT_STATS_HW_PDEV_ERRS_MAC_ID_GET(word) \ - ((word >> 0) & 0xff) - typedef struct { htt_tlv_hdr_t tlv_hdr; - /** - * BIT [ 7 : 0] :- mac_id + /* BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 last_unpause_ppdu_id; A_UINT32 hwsch_unpause_wait_tqm_write; A_UINT32 hwsch_dummy_tlv_skipped; @@ -1867,9 +1610,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_whal_tx_tlv htt_hw_stats_whal_tx_tlv; -#define HTT_STATS_WHAL_TX_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -1944,9 +1684,6 @@ typedef struct _htt_pdev_err_stats { #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_GET(_var) \ (((_var) & HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_M) >> \ HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PEER_MSDU_FLOWQ_TX_FLOW_NUMBER_GET(_var) \ - HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_GET(_var) #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_SET(_var, _val) \ do { \ @@ -1957,9 +1694,6 @@ typedef struct _htt_pdev_err_stats { #define HTT_MSDU_FLOW_STATS_TID_NUM_GET(_var) \ (((_var) & HTT_MSDU_FLOW_STATS_TID_NUM_M) >> \ HTT_MSDU_FLOW_STATS_TID_NUM_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PEER_MSDU_FLOWQ_TID_NUM_GET(_var) \ - HTT_MSDU_FLOW_STATS_TID_NUM_GET(_var) #define HTT_MSDU_FLOW_STATS_TID_NUM_SET(_var, _val) \ do { \ @@ -1970,9 +1704,6 @@ typedef struct _htt_pdev_err_stats { #define HTT_MSDU_FLOW_STATS_DROP_GET(_var) \ (((_var) & HTT_MSDU_FLOW_STATS_DROP_M) >> \ HTT_MSDU_FLOW_STATS_DROP_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PEER_MSDU_FLOWQ_DROP_RULE_GET(_var) \ - HTT_MSDU_FLOW_STATS_DROP_GET(_var) #define HTT_MSDU_FLOW_STATS_DROP_SET(_var, _val) \ do { \ @@ -1996,15 +1727,7 @@ typedef struct _htt_msdu_flow_stats_tlv { * BIT [20 : 20] :- drop_rule * BIT [31 : 21] :- reserved */ - union { - struct { - A_UINT32 tx_flow_number : 16; - A_UINT32 tid_num : 4; - A_UINT32 drop_rule : 1; - A_UINT32 reserved : 11; - }; - A_UINT32 tx_flow_no__tid_num__drop_rule; - }; + A_UINT32 tx_flow_no__tid_num__drop_rule; A_UINT32 last_cycle_enqueue_count; A_UINT32 last_cycle_dequeue_count; A_UINT32 last_cycle_drop_count; @@ -2028,9 +1751,7 @@ typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv; #define HTT_TX_TID_STATS_SW_PEER_ID_GET(_var) \ (((_var) & HTT_TX_TID_STATS_SW_PEER_ID_M) >> \ HTT_TX_TID_STATS_SW_PEER_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TID_DETAILS_SW_PEER_ID_GET(_var) \ - HTT_TX_TID_STATS_SW_PEER_ID_GET(_var) + #define HTT_TX_TID_STATS_SW_PEER_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_SW_PEER_ID, _val); \ @@ -2040,9 +1761,7 @@ typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv; #define HTT_TX_TID_STATS_TID_NUM_GET(_var) \ (((_var) & HTT_TX_TID_STATS_TID_NUM_M) >> \ HTT_TX_TID_STATS_TID_NUM_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TID_DETAILS_TID_NUM_GET(_var) \ - HTT_TX_TID_STATS_TID_NUM_GET(_var) + #define HTT_TX_TID_STATS_TID_NUM_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_TID_NUM, _val); \ @@ -2058,9 +1777,7 @@ typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv; #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_GET(_var) \ (((_var) & HTT_TX_TID_STATS_NUM_SCHED_PENDING_M) >> \ HTT_TX_TID_STATS_NUM_SCHED_PENDING_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TID_DETAILS_NUM_SCHED_PENDING_GET(_var) \ - HTT_TX_TID_STATS_NUM_SCHED_PENDING_GET(_var) + #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_SCHED_PENDING, _val); \ @@ -2070,9 +1787,7 @@ typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv; #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_GET(_var) \ (((_var) & HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_M) >> \ HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TID_DETAILS_NUM_PPDU_IN_HWQ_GET(_var) \ - HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_GET(_var) + #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ, _val); \ @@ -2089,26 +1804,13 @@ typedef struct _htt_tx_tid_stats_tlv { * BIT [15 : 0] :- sw_peer_id * BIT [31 : 16] :- tid_num */ - union { - struct { - A_UINT32 sw_peer_id : 16; - A_UINT32 tid_num : 16; - }; - A_UINT32 sw_peer_id__tid_num; - }; + A_UINT32 sw_peer_id__tid_num; /** * BIT [ 7 : 0] :- num_sched_pending * BIT [15 : 8] :- num_ppdu_in_hwq * BIT [31 : 16] :- reserved */ - union { - struct { - A_UINT32 num_sched_pending : 8; - A_UINT32 num_ppdu_in_hwq : 8; - A_UINT32 reserved : 16; - }; - A_UINT32 num_sched_pending__num_ppdu_in_hwq; - }; + A_UINT32 num_sched_pending__num_ppdu_in_hwq; A_UINT32 tid_flags; /** per tid # of hw_queued ppdu */ A_UINT32 hw_queued; @@ -2138,26 +1840,13 @@ typedef struct _htt_tx_tid_stats_v1_tlv { * BIT [15 : 0] :- sw_peer_id * BIT [31 : 16] :- tid_num */ - union { - struct { - A_UINT32 sw_peer_id : 16; - A_UINT32 tid_num : 16; - }; - A_UINT32 sw_peer_id__tid_num; - }; + A_UINT32 sw_peer_id__tid_num; /** * BIT [ 7 : 0] :- num_sched_pending * BIT [15 : 8] :- num_ppdu_in_hwq * BIT [31 : 16] :- reserved */ - union { - struct { - A_UINT32 num_sched_pending : 8; - A_UINT32 num_ppdu_in_hwq : 8; - A_UINT32 reserved : 16; - }; - A_UINT32 num_sched_pending__num_ppdu_in_hwq; - }; + A_UINT32 num_sched_pending__num_ppdu_in_hwq; A_UINT32 tid_flags; /** Max qdepth in bytes reached by this tid */ A_UINT32 max_qdepth_bytes; @@ -2204,21 +1893,10 @@ typedef struct _htt_tx_tid_stats_v1_tlv { */ A_UINT32 head_msdu_tqm_timestamp_us; A_UINT32 head_msdu_tqm_latency_us; - A_UINT32 pause_module_id_ext; - A_UINT32 block_module_id_ext; } htt_stats_tx_tid_details_v1_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_tid_details_v1_tlv htt_tx_tid_stats_v1_tlv; -#define HTT_STATS_TX_TID_DETAILS_V1_SW_PEER_ID_GET(word) \ - (((word) >> 0) & 0xffff) -#define HTT_STATS_TX_TID_DETAILS_V1_TID_NUM_GET(word) \ - (((word) >> 16) & 0xffff) -#define HTT_STATS_TX_TID_DETAILS_V1_NUM_SCHED_PENDING_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_TX_TID_DETAILS_V1_NUM_PPDU_IN_HWQ_GET(word) \ - (((word) >> 8) & 0xff) - #define HTT_RX_TID_STATS_SW_PEER_ID_M 0x0000ffff #define HTT_RX_TID_STATS_SW_PEER_ID_S 0 #define HTT_RX_TID_STATS_TID_NUM_M 0xffff0000 @@ -2227,9 +1905,7 @@ typedef htt_stats_tx_tid_details_v1_tlv htt_tx_tid_stats_v1_tlv; #define HTT_RX_TID_STATS_SW_PEER_ID_GET(_var) \ (((_var) & HTT_RX_TID_STATS_SW_PEER_ID_M) >> \ HTT_RX_TID_STATS_SW_PEER_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RX_TID_DETAILS_SW_PEER_ID_GET(_var) \ - HTT_RX_TID_STATS_SW_PEER_ID_GET(_var) + #define HTT_RX_TID_STATS_SW_PEER_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_SW_PEER_ID, _val); \ @@ -2239,9 +1915,7 @@ typedef htt_stats_tx_tid_details_v1_tlv htt_tx_tid_stats_v1_tlv; #define HTT_RX_TID_STATS_TID_NUM_GET(_var) \ (((_var) & HTT_RX_TID_STATS_TID_NUM_M) >> \ HTT_RX_TID_STATS_TID_NUM_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RX_TID_DETAILS_TID_NUM_GET(_var) \ - HTT_RX_TID_STATS_TID_NUM_GET(_var) + #define HTT_RX_TID_STATS_TID_NUM_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_TID_NUM, _val); \ @@ -2255,13 +1929,7 @@ typedef struct _htt_rx_tid_stats_tlv { * BIT [15 : 0] : sw_peer_id * BIT [31 : 16] : tid_num */ - union { - struct { - A_UINT32 sw_peer_id : 16; - A_UINT32 tid_num : 16; - }; - A_UINT32 sw_peer_id__tid_num; - }; + A_UINT32 sw_peer_id__tid_num; /** Stored as little endian */ A_UINT8 tid_name[MAX_HTT_TID_NAME]; /** @@ -2279,251 +1947,6 @@ typedef struct _htt_rx_tid_stats_tlv { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_tid_details_tlv htt_rx_tid_stats_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - /* Lower 4 bytes (bytes 0-3) of the MAC address */ - A_UINT32 peer_mac_addr_31_0; - /* Upper 2 bytes (bytes 4-5) of MAC, and TID (1 byte) */ - A_UINT32 peer_mac_addr_47_32_and_tid_num; - - /** - * BIT [11: 0] : Starting Sequence number of the session, - * this changes whenever window moves - * BIT [21:12] : Points to last forwarded packet - */ - union { - A_UINT32 ssn_current_index; - struct { - A_UINT32 ssn : 12, - current_index : 10, - reserved_0 : 10; - }; - }; - - /** Current PN number */ - A_UINT32 pn_31_0; - A_UINT32 pn_63_32; - A_UINT32 pn_95_64; - A_UINT32 pn_127_96; - - /** - * Timestamp of arrival of the last MPDU for this queue (in microseconds) - */ - A_UINT32 last_rx_enqueue_timestamp_us; - - /** Timestamp of forwarding an MPDU (in microseconds) */ - A_UINT32 last_rx_dequeue_timestamp_us; - - /** The number of MPDUs, MSDUs in the queue */ - union { - A_UINT32 mpdu_msdu_cnt; - struct { - A_UINT32 current_mpdu_cnt : 16, - current_msdu_cnt : 16; - }; - }; - - /** The number of times the window moved more then 2K */ - A_UINT32 window_jump_2k_cnt; - - /** - * The number of times that REO started forwarding frames even though - * there is a hole in the bitmap. - * Forwarding reason is Timeout. - */ - A_UINT32 timeout_cnt; - - /** - * The number of times that REO started forwarding frames even though - * there is a hole in the bitmap. - * Forwarding reason is reception of BAR frame. - */ - A_UINT32 forward_due_to_bar_cnt; - - /** The number of duplicate frames that have been detected */ - A_UINT32 duplicate_cnt; - - /** - * The number of frames that have been received in order without a hole - * that prevented them from being forwarded immediately. - */ - A_UINT32 frames_in_order_cnt; - - /** The number of times a BAR frame is received. */ - A_UINT32 bar_received_cnt; - - /** - * The total number of MPDU frames that have been processed, - * this includes the duplicates. - */ - A_UINT32 mpdu_frames_processed_cnt; - - /** - * The total number of MSDU frames that have been processed, - * this includes the duplicates. - */ - A_UINT32 msdu_frames_processed_cnt; - - /** - * An approximation of the number of bytes received for - * this queue, in 64 byte units. - */ - A_UINT32 total_processed_byte_cnt; - - /** The number of MPDUs received after the window had already moved on */ - A_UINT32 late_receive_mpdu_cnt; - - /** The number of times a hole was created in the receive bitmap */ - A_UINT32 hole_cnt; - - /** - * The number of holes in the bitmap that moved due to aging - * counter expiry - */ - A_UINT32 aging_drop_mpdu_cnt; - - /** - * The number of times holes got removed from the bitmap due to - * aging counter expiry - */ - A_UINT32 aging_drop_interval_cnt; - - /** The number of ADDBA Req received */ - A_UINT32 addba_req_cnt; - - /** The number of ADDBA Resp replied for RX ADDBA Req */ - A_UINT32 addba_resp_cnt; - - /** The number of ADDBA Resp sent successfully */ - A_UINT32 addba_rsp_success_cnt; - - /** The number of ADDBA Resp sent failed */ - A_UINT32 addba_rsp_fail_cnt; - - /** The number of DELBA Req received */ - A_UINT32 delba_req_cnt; - - /** The number of DELBA Req sent successfully */ - A_UINT32 delba_tx_success_cnt; - - /** The number of DELBA Req sent failed */ - A_UINT32 delba_tx_fail_cnt; - - /** BA window size established */ - A_UINT32 ba_win_size; - - /** PN size established */ - A_UINT32 pn_size; -} htt_stats_rx_peer_tid_reo_queue_ba_tlv; - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MAC_ADDR_SET(_tlv_ptr, _mac_addr_ptr) \ - do { \ - A_UINT32 __packed_mac_47_32; \ - /* Pack MAC addr bytes [0-3] into peer_mac_addr_31_0 */ \ - (_tlv_ptr)->peer_mac_addr_31_0 = (A_UINT32) \ - (((_mac_addr_ptr)[0] << 0) | \ - ((_mac_addr_ptr)[1] << 8) | \ - ((_mac_addr_ptr)[2] << 16) | \ - ((_mac_addr_ptr)[3] << 24)); \ - /* - * Pack MAC addr bytes [4-5] into the LOWER 16 bits of - * peer_mac_addr_47_32_and_tid_num - */ \ - __packed_mac_47_32 = (A_UINT32) \ - (((_mac_addr_ptr)[4] << 0) | \ - ((_mac_addr_ptr)[5] << 8)); \ - /* - * Set lower 16 bits of peer_mac_addr_47_32_and_tid_num, - * preserving upper 16 bits (which includes the TID) if already set - */ \ - (_tlv_ptr)->peer_mac_addr_47_32_and_tid_num &= ~0x0000FFFF; /* Clear existing MAC addr bits (lower 16) */ \ - (_tlv_ptr)->peer_mac_addr_47_32_and_tid_num |= __packed_mac_47_32; \ - } while (0) -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MAC_ADDR_GET(_tlv_ptr, _dest_mac_addr_ptr) \ - do { \ - A_UINT32 __mac_31_0_val = (_tlv_ptr)->peer_mac_addr_31_0; \ - /* Extract MAC bytes [4-5] from the LOWER 16 bits of peer_mac_addr_47_32_and_tid */ \ - A_UINT32 __mac_47_32_val = ((_tlv_ptr)->peer_mac_addr_47_32_and_tid_num) & 0xFFFF; \ - (_dest_mac_addr_ptr)[0] = (A_UINT8)((__mac_31_0_val >> 0) & 0xFF); \ - (_dest_mac_addr_ptr)[1] = (A_UINT8)((__mac_31_0_val >> 8) & 0xFF); \ - (_dest_mac_addr_ptr)[2] = (A_UINT8)((__mac_31_0_val >> 16) & 0xFF); \ - (_dest_mac_addr_ptr)[3] = (A_UINT8)((__mac_31_0_val >> 24) & 0xFF); \ - (_dest_mac_addr_ptr)[4] = (A_UINT8)((__mac_47_32_val >> 0) & 0xFF); \ - (_dest_mac_addr_ptr)[5] = (A_UINT8)((__mac_47_32_val >> 8) & 0xFF); \ - } while (0) - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_M 0x00FF0000 /* Mask for TID_NUM */ -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_S 16 /* Shift for TID_NUM */ - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_GET(_var) \ - (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_M) >> \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_S) - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM, _val); \ - ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_S)); \ - } while (0) - -/* Macros for ssn and current_index */ -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_M 0x00000fff -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_S 0 -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_M 0x003ff000 -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_S 12 - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_GET(_var) \ - (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_M) >> \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_S) - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN, _val); \ - ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_S)); \ - } while (0) - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_GET(_var) \ - (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_M) >> \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_S) - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX, _val); \ - ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_S)); \ - } while (0) - -/* Macros for mpdu/msdu count */ -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_M 0x0000ffff -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_S 0 -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_M 0xffff0000 -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_S 16 - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_GET(_var) \ - (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_M) >> \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_MPDU_CNT_GET(_var) \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_GET(_var) -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT, _val); \ - ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_S)); \ - } while (0) - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_GET(_var) \ - (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_M) >> \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_MSDU_CNT_GET(_var) \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_GET(_var) -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT, _val); \ - ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_S)); \ - } while (0) - - #define HTT_MAX_COUNTER_NAME 8 typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -2542,9 +1965,9 @@ typedef struct { A_UINT32 mpdu_cnt; /** Number of rx MSDU */ A_UINT32 msdu_cnt; - /** lower 32 bits of pause bitmap */ + /** pause bitmap */ A_UINT32 pause_bitmap; - /** lower 32 bits of block bitmap */ + /** block bitmap */ A_UINT32 block_bitmap; /** current timestamp */ A_UINT32 current_timestamp; @@ -2574,10 +1997,6 @@ typedef struct { A_UINT32 inactive_time; /** Number of MPDUs dropped after max retries */ A_UINT32 remove_mpdus_max_retries; - /** extension with upper 32 bits of pause bitmap */ - A_UINT32 pause_bitmap_ext; - /** extension with upper 32 bits of block bitmap */ - A_UINT32 block_bitmap_ext; } htt_stats_peer_stats_cmn_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_peer_stats_cmn_tlv htt_peer_stats_cmn_tlv; @@ -2597,22 +2016,6 @@ typedef htt_stats_peer_stats_cmn_tlv htt_peer_stats_cmn_tlv; #define HTT_PEER_DETAILS_SRC_INFO_M 0x00000fff #define HTT_PEER_DETAILS_SRC_INFO_S 0 -#define HTT_PEER_DETAILS_PEER_PS_ENTRY_M 0x000000ff -#define HTT_PEER_DETAILS_PEER_PS_ENTRY_S 0 -#define HTT_PEER_DETAILS_PEER_PS_EXIT_M 0x0000ff00 -#define HTT_PEER_DETAILS_PEER_PS_EXIT_S 8 -#define HTT_PEER_DETAILS_PEER_PSPOLL_TRIGGER_M 0x00ff0000 -#define HTT_PEER_DETAILS_PEER_PSPOLL_TRIGGER_S 16 -#define HTT_PEER_DETAILS_PEER_UAPSD_TRIGGER_M 0xff000000 -#define HTT_PEER_DETAILS_PEER_UAPSD_TRIGGER_S 24 - -#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_0_M 0x000003ff -#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_0_S 0 -#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_1_M 0x000ffc00 -#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_1_S 10 -#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_2_M 0x3ff00000 -#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_2_S 20 - #define HTT_PEER_DETAILS_SET(word, httsym, val) \ do { \ @@ -2658,34 +2061,6 @@ typedef struct { rsvd1 : 20; /* [31:12] */ }; }; - - /* Dword 10 */ - union { - A_UINT32 word__peer_ps_entry__peer_ps_exit__peer_pspoll_trigger_received__peer_uapsd_trigger_received; - struct { - A_UINT32 peer_ps_entry : 8, /* [7:0] */ - peer_ps_exit : 8, /* [15:8] */ - peer_pspoll_trigger_received : 8, /* [23:16] */ - peer_uapsd_trigger_received : 8; /* [31:24] */ - }; - }; - - /* Dword 11 */ - union { - A_UINT32 word__peer_ps_histogram_0__peer_ps_histogram_1__peer_ps_histogram_2; - struct { - /* - * This word holds 3 10-bit histograms of power-save durations: - * bits 9:0 - count of durations < 200 ms - * bits 19:10 - count of durations between 200 to 500 ms - * bits 29:20 - count of durations > 500 ms - */ - A_UINT32 peer_ps_histogram_0 : 10, /* [9:0] */ - peer_ps_histogram_1 : 10, /* [19:10] */ - peer_ps_histogram_2 : 10, /* [29:20] */ - rsvd2 : 2; /* [31:30] */ - }; - }; } htt_stats_peer_details_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_peer_details_tlv htt_peer_details_tlv; @@ -2697,44 +2072,23 @@ typedef htt_stats_peer_details_tlv htt_peer_details_tlv; #define HTT_STATS_PEER_DETAILS_SRC_INFO_GET(word) ((word >> 0) & 0xfff) -#define HTT_STATS_PEER_DETAILS_PEER_PS_ENTRY_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_PS_ENTRY) -#define HTT_STATS_PEER_DETAILS_PEER_PS_EXIT_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_PS_EXIT) -#define HTT_STATS_PEER_DETAILS_PEER_PSPOLL_TRIGGER_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_PSPOLL_TRIGGER) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PEER_DETAILS_PEER_PSPOLL_TRIGGER_RECEIVED_GET(word) \ - HTT_STATS_PEER_DETAILS_PEER_PSPOLL_TRIGGER_GET(word) -#define HTT_STATS_PEER_DETAILS_PEER_UAPSD_TRIGGER_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_UAPSD_TRIGGER) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PEER_DETAILS_PEER_UAPSD_TRIGGER_RECEIVED_GET(word) \ - HTT_STATS_PEER_DETAILS_PEER_UAPSD_TRIGGER_GET(word) -#define HTT_STATS_PEER_DETAILS_PEER_PS_HISTOGRAM_0_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_PS_HISTOGRAM_0) -#define HTT_STATS_PEER_DETAILS_PEER_PS_HISTOGRAM_1_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_PS_HISTOGRAM_1) -#define HTT_STATS_PEER_DETAILS_PEER_PS_HISTOGRAM_2_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_PS_HISTOGRAM_2) - typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 sw_peer_id; A_UINT32 ast_index; htt_mac_addr mac_addr; A_UINT32 - pdev_id : 2, /* bits 1:0 */ - vdev_id : 8, /* bits 9:2 */ - next_hop : 1, /* bit 10 */ - mcast : 1, /* bit 11 */ - monitor_direct : 1, /* bit 12 */ - mesh_sta : 1, /* bit 13 */ - mec : 1, /* bit 14 */ - intra_bss : 1, /* bit 15 */ - chip_id : 2, /* bit 17:16 */ - ml_peer_id : 13, /* bit 30:18 */ - on_chip : 1; /* bit 31 */ + pdev_id : 2, + vdev_id : 8, + next_hop : 1, + mcast : 1, + monitor_direct : 1, + mesh_sta : 1, + mec : 1, + intra_bss : 1, + chip_id : 2, + ml_peer_id : 13, + on_chip : 1; A_UINT32 tx_monitor_override_sta : 1, rx_monitor_override_sta : 1, @@ -2743,34 +2097,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_ast_entry_tlv htt_ast_entry_tlv; -#define HTT_STATS_AST_ENTRY_PDEV_ID_GET(word32) \ - ((word32 >> 0) & 0x3) -#define HTT_STATS_AST_ENTRY_VDEV_ID_GET(word32) \ - ((word32 >> 2) & 0xff) -#define HTT_STATS_AST_ENTRY_NEXT_HOP_GET(word32) \ - ((word32 >> 10) & 0x1) -#define HTT_STATS_AST_ENTRY_MCAST_GET(word32) \ - ((word32 >> 11) & 0x1) -#define HTT_STATS_AST_ENTRY_MONITOR_DIRECT_GET(word32) \ - ((word32 >> 12) & 0x1) -#define HTT_STATS_AST_ENTRY_MESH_STA_GET(word32) \ - ((word32 >> 13) & 0x1) -#define HTT_STATS_AST_ENTRY_MEC_GET(word32) \ - ((word32 >> 14) & 0x1) -#define HTT_STATS_AST_ENTRY_INTRA_BSS_GET(word32) \ - ((word32 >> 15) & 0x1) -#define HTT_STATS_AST_ENTRY_CHIP_ID_GET(word32) \ - ((word32 >> 16) & 0x3) -#define HTT_STATS_AST_ENTRY_ML_PEER_ID_GET(word32) \ - ((word32 >> 18) & 0x1fff) -#define HTT_STATS_AST_ENTRY_ON_CHIP_GET(word32) \ - ((word32 >> 31) & 0x1) - -#define HTT_STATS_AST_ENTRY_TX_MONITOR_OVERRIDE_STA_GET(word32) \ - ((word32 >> 0) & 0x1) -#define HTT_STATS_AST_ENTRY_RX_MONITOR_OVERRIDE_STA_GET(word32) \ - ((word32 >> 1) & 0x1) - typedef enum { HTT_STATS_DIRECTION_TX, HTT_STATS_DIRECTION_RX, @@ -2791,7 +2117,7 @@ typedef enum { HTT_STATS_PREAM_VHT, HTT_STATS_PREAM_HE, HTT_STATS_PREAM_EHT, - HTT_STATS_PREAM_UHR, + HTT_STATS_PREAM_RSVD1, HTT_STATS_PREAM_COUNT, } HTT_STATS_PREAM_TYPE; @@ -2882,9 +2208,6 @@ typedef struct _htt_tx_peer_rate_stats_tlv { A_UINT32 tx_bw_320mhz; /* MCS 14,15 */ A_UINT32 tx_mcs_ext_2[HTT_TX_PEER_STATS_NUM_EXTRA2_MCS_COUNTERS]; - A_UINT32 peer_tx_ppdu_cnt; - A_UINT32 peer_tx_mpdu_try_cnt; - A_UINT32 peer_tx_mpdu_success_cnt; } htt_stats_peer_tx_rate_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_peer_tx_rate_stats_tlv htt_tx_peer_rate_stats_tlv; @@ -2969,8 +2292,6 @@ typedef struct _htt_rx_peer_rate_stats_tlv { A_UINT32 rx_bw_320mhz; /* MCS 14,15 */ A_UINT32 rx_mcs_ext_2[HTT_RX_PEER_STATS_NUM_EXTRA2_MCS_COUNTERS]; - A_UINT32 tot_rx_ppdu_bytes; - A_UINT32 rx_mpdu_try_cnt; } htt_stats_peer_rx_rate_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_peer_rx_rate_stats_tlv htt_rx_peer_rate_stats_tlv; @@ -2990,10 +2311,8 @@ typedef enum { HTT_RX_TID_STATS_TLV = 5, HTT_MSDU_FLOW_STATS_TLV = 6, HTT_PEER_SCHED_STATS_TLV = 7, - HTT_PEER_OFDMA_STATS_TLV = 8, - HTT_PEER_AX_OFDMA_STATS_TLV = HTT_PEER_OFDMA_STATS_TLV, /* DEPRECATED */ - HTT_PEER_BE_OFDMA_STATS_TLV = 9, /* DEPRECATED */ - HTT_PEER_RX_REO_STATS_TLV = 10, + HTT_PEER_AX_OFDMA_STATS_TLV = 8, + HTT_PEER_BE_OFDMA_STATS_TLV = 9, HTT_PEER_STATS_MAX_TLV = 31, } htt_peer_stats_tlv_enum; @@ -3016,46 +2335,18 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_peer_sched_stats_tlv htt_peer_sched_stats_tlv; -/* Retaining the old structure defs for compatibility */ typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 peer_id; - union{ - A_UINT32 ax_basic_trig_count; /* retaining the older alias */ - A_UINT32 basic_trig_count; - }; - union{ - A_UINT32 ax_basic_trig_err; /* retaining the older alias */ - A_UINT32 basic_trig_err; - }; - union{ - A_UINT32 ax_bsr_trig_count; /* retaining the older alias */ - A_UINT32 bsr_trig_count; - }; - union{ - A_UINT32 ax_bsr_trig_err; /* retaining the older alias */ - A_UINT32 bsr_trig_err; - }; - union{ - A_UINT32 ax_mu_bar_trig_count; /* retaining the older alias */ - A_UINT32 mu_bar_trig_count; - }; - union{ - A_UINT32 ax_mu_bar_trig_err; /* retaining the older alias */ - A_UINT32 mu_bar_trig_err; - }; - union{ - A_UINT32 ax_basic_trig_with_per; /* retaining the older alias */ - A_UINT32 basic_trig_with_per; - }; - union{ - A_UINT32 ax_bsr_trig_with_per; /* retaining the older alias */ - A_UINT32 bsr_trig_with_per; - }; - union{ - A_UINT32 ax_mu_bar_trig_with_per; /* retaining the older alias */ - A_UINT32 mu_bar_trig_with_per; - }; + A_UINT32 ax_basic_trig_count; + A_UINT32 ax_basic_trig_err; + A_UINT32 ax_bsr_trig_count; + A_UINT32 ax_bsr_trig_err; + A_UINT32 ax_mu_bar_trig_count; + A_UINT32 ax_mu_bar_trig_err; + A_UINT32 ax_basic_trig_with_per; + A_UINT32 ax_bsr_trig_with_per; + A_UINT32 ax_mu_bar_trig_with_per; /* is_airtime_large_for_dl_ofdma, is_airtime_large_for_ul_ofdma * These fields contain 2 counters each. The first element in each * array counts how many times the airtime is short enough to use @@ -3067,22 +2358,13 @@ typedef struct { /* Last updated value of DL and UL queue depths for each peer per AC */ A_UINT32 last_updated_dl_qdepth[HTT_NUM_AC_WMM]; A_UINT32 last_updated_ul_qdepth[HTT_NUM_AC_WMM]; - - /* Per peer Manual UL OFDMA trigger and trigger error counts */ - union{ - A_UINT32 ax_manual_ulofdma_trig_count; /* retaining the older alias */ - A_UINT32 manual_ulofdma_trig_count; - }; - union{ - A_UINT32 ax_manual_ulofdma_trig_err_count; /* retaining the older alias */ - A_UINT32 manual_ulofdma_trig_err_count; - }; -} htt_stats_peer_ofdma_stats_tlv; + /* Per peer Manual 11ax UL OFDMA trigger and trigger error counts */ + A_UINT32 ax_manual_ulofdma_trig_count; + A_UINT32 ax_manual_ulofdma_trig_err_count; +} htt_stats_peer_ax_ofdma_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_peer_ofdma_stats_tlv htt_peer_ax_ofdma_stats_tlv; -typedef htt_stats_peer_ofdma_stats_tlv htt_stats_peer_ax_ofdma_stats_tlv; +typedef htt_stats_peer_ax_ofdma_stats_tlv htt_peer_ax_ofdma_stats_tlv; -/* DEPRECATED */ typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 peer_id; @@ -3164,8 +2446,7 @@ typedef htt_stats_peer_be_ofdma_stats_tlv htt_peer_be_ofdma_stats_tlv; * - HTT_STATS_PEER_MSDU_FLOWQ_TAG (multiple) * - HTT_STATS_TX_TID_DETAILS_V1_TAG (multiple) * - HTT_STATS_PEER_SCHED_STATS_TAG - * - HTT_STATS_PEER_OFDMA_STATS_TAG / HTT_STATS_PEER_AX_OFDMA_STATS_TAG - * - HTT_STATS_PEER_BE_OFDMA_STATS_TAG + * - HTT_STATS_PEER_AX_OFDMA_STATS_TAG */ /* NOTE: * This structure is for documentation, and cannot be safely used directly. @@ -3184,12 +2465,8 @@ typedef struct _htt_peer_stats { htt_stats_peer_msdu_flowq_tlv msdu_flowq[1]; htt_stats_tx_tid_details_v1_tlv tx_tid_stats_v1[1]; htt_stats_peer_sched_stats_tlv peer_sched_stats; - union { - htt_stats_peer_ofdma_stats_tlv peer_ofdma_stats; - /* ax_ofdma_stats: DEPRECATED, but retained as alias */ - htt_stats_peer_ax_ofdma_stats_tlv ax_ofdma_stats; - }; - htt_stats_peer_be_ofdma_stats_tlv be_ofdma_stats; /* DEPRECATED */ + htt_stats_peer_ax_ofdma_stats_tlv ax_ofdma_stats; + htt_stats_peer_be_ofdma_stats_tlv be_ofdma_stats; } htt_peer_stats_t; #endif /* ATH_TARGET */ @@ -3501,58 +2778,6 @@ typedef struct { typedef htt_stats_tx_hwq_txop_used_cnt_hist_tlv htt_tx_hwq_txop_used_cnt_hist_tlv_v; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - A_UINT32 pdev_id__word; - struct { - A_UINT32 - pdev_id: 8, - reserved: 24; - }; - }; - A_UINT32 active_seq_in_hwq_hist[HTT_PDEV_STATS_MAX_ACTIVE_SEQ_IN_HWQ_HIST]; -} htt_stats_tx_pdev_pending_seq_cnt_in_hwq_hist_tlv; - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_M 0x000000ff -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_S 0 - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_GET(_var) \ - (((_var) & HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_M) >> \ - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_S) - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_S)); \ - } while (0) - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - A_UINT32 pdev_id__word; - struct { - A_UINT32 - pdev_id: 8, - reserved: 24; - }; - }; - A_UINT32 active_seq_in_txq_hist[HTT_PDEV_STATS_MAX_SEQ_CTRL_HIST]; -} htt_stats_tx_pdev_pending_seq_cnt_in_txq_hist_tlv; - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_M 0x000000ff -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_S 0 - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_GET(_var) \ - (((_var) & HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_M) >> \ - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_S) - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_S)); \ - } while (0) - /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_HWQ * TLV_TAGS: * - HTT_STATS_STRING_TAG @@ -3563,8 +2788,6 @@ typedef struct { * - HTT_STATS_TX_HWQ_FES_STATUS_TAG * - HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG * - HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG - * - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_TAG - * - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_TAG */ /* NOTE: * This structure is for documentation, and cannot be safely used directly. @@ -3585,10 +2808,6 @@ typedef struct _htt_tx_hwq_stats { htt_stats_tx_hwq_fes_status_tlv fes_stats_tlv; htt_stats_tx_hwq_tried_mpdu_cnt_hist_tlv tried_mpdu_tlv; htt_stats_tx_hwq_txop_used_cnt_hist_tlv txop_used_tlv; - htt_stats_tx_pdev_pending_seq_cnt_in_hwq_hist_tlv - active_pending_seq_cnt_in_hwq_hist_tlv; - htt_stats_tx_pdev_pending_seq_cnt_in_txq_hist_tlv - active_pending_seq_cnt_in_txq_hist_tlv; } htt_tx_hwq_stats_t; #endif /* ATH_TARGET */ @@ -3661,9 +2880,7 @@ typedef enum { #define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4 #define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8 #define HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS 8 -#define HTT_TX_PDEV_STATS_NUM_BN_MUMIMO_USER_STATS 8 #define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74 -#define HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS 16 #define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8 #define HTT_STATS_MAX_MUMIMO_GRP_SZ 8 /* @@ -3680,64 +2897,14 @@ typedef enum { #define HTT_MAX_NUM_SBT_INTR 4 -typedef enum { - HTT_RU_ALLOC_MODE_PF, - HTT_RU_ALLOC_MODE_QOS, - HTT_RU_ALLOC_MODE_STATIC, - HTT_RU_ALLOC_MODE_EQUAL, - HTT_RU_ALLOC_MODE_SIMPLIFIED, - - /* Reserving additional modes for future use */ - HTT_RU_ALLOC_MODE_RESERVED_1, - HTT_RU_ALLOC_MODE_RESERVED_2, - - HTT_RU_ALLOC_NUM_MODES -} HTT_RU_ALLOC_MODE; - -typedef enum { - HTT_TX_PDEV_STATS_BN_DRU_SIZE_26, - HTT_TX_PDEV_STATS_BN_DRU_SIZE_52, - HTT_TX_PDEV_STATS_BN_DRU_SIZE_106, - HTT_TX_PDEV_STATS_BN_DRU_SIZE_242, - HTT_TX_PDEV_STATS_BN_DRU_SIZE_484, - - HTT_TX_PDEV_STATS_NUM_BN_DRU_SIZE_COUNTERS -} HTT_TX_PDEV_STATS_BN_DRU_SIZE; - -typedef enum { - HTT_BN_UL_OFDMA_RRU_ONLY_ALLOC_MODE, - HTT_BN_UL_OFDMA_DRU_ONLY_ALLOC_MODE, - HTT_BN_UL_OFDMA_HYBRID_RU_ALLOC_MODE, - - /* Reserving additional modes for future use */ - HTT_BN_UL_OFDMA_RU_ALLOC_MODE_RESERVED_1, - HTT_BN_UL_OFDMA_RU_ALLOC_MODE_RESERVED_2, - - HTT_BN_UL_OFDMA_NUM_RU_ALLOC_MODES -} HTT_BN_UL_OFDMA_RU_ALLOC_MODE; - -typedef enum { - HTT_BN_UL_OFDMA_DRU_SBW_20MHZ, - HTT_BN_UL_OFDMA_DRU_SBW_40MHZ, - HTT_BN_UL_OFDMA_DRU_SBW_80MHZ, - - HTT_BN_UL_OFDMA_NUM_DRU_SBW_COUNT -} HTT_BN_UL_OFDMA_DRU_SBW_SIZE; - typedef struct { htt_tlv_hdr_t tlv_hdr; - /** + /* * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** BAR sent out for SU transmission */ A_UINT32 su_bar; /** SW generated RTS frame sent */ @@ -3795,17 +2962,10 @@ typedef struct { * (Smart basic triggers are only used with intervals <= 40 ms.) */ A_UINT32 smart_basic_trig_sch_histogram[HTT_MAX_NUM_SBT_INTR]; - A_UINT32 ru_alloc_mode_cnt[HTT_RU_ALLOC_NUM_MODES]; - A_UINT32 mu_bar_pipeline_seq_cnt; - A_UINT32 mu_bar_pipeline_resume_cnt; - A_UINT32 mu_bar_pipeline_resume_fail_cnt; } htt_stats_tx_selfgen_cmn_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_selfgen_cmn_stats_tlv htt_tx_selfgen_cmn_stats_tlv; -#define HTT_STATS_TX_SELFGEN_CMN_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - typedef struct { htt_tlv_hdr_t tlv_hdr; /** 11AC VHT SU NDPA frame sent over the air */ @@ -3913,22 +3073,6 @@ typedef struct { A_UINT32 ax_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM]; /** 11AX HE MU-BAR Trigger frames per AC completed with error(s) */ A_UINT32 ax_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM]; - /** 11AX HE MU Combined UL OFDMA Basic Trigger frame sent over the air */ - A_UINT32 combined_ax_ulofdma_trigger_tried[HTT_NUM_AC_WMM]; - /** 11AX HE MU Combined UL OFDMA Basic Trigger completed with error(s) */ - A_UINT32 combined_ax_ulofdma_trigger_err[HTT_NUM_AC_WMM]; - /** 11AX HE MU Standalone UL OFDMA Basic Trigger frame sent over the air */ - A_UINT32 standalone_ax_ulofdma_trigger_tried[HTT_NUM_AC_WMM]; - /** 11AX HE MU Standalone UL OFDMA Basic Trigger completed with error(s) */ - A_UINT32 standalone_ax_ulofdma_trigger_err[HTT_NUM_AC_WMM]; - /** 11AX HE MU Combined UL MU-MIMO Basic Trigger frame sent over the air */ - A_UINT32 combined_ax_ulmumimo_trigger_tried[HTT_NUM_AC_WMM]; - /** 11AX HE MU Combined UL MU-MIMO Basic Trigger completed with error(s) */ - A_UINT32 combined_ax_ulmumimo_trigger_err[HTT_NUM_AC_WMM]; - /** 11AX HE MU Standalone UL MU-MIMO Basic Trigger frame sent over the air*/ - A_UINT32 standalone_ax_ulmumimo_trigger_tried[HTT_NUM_AC_WMM]; - /** 11AX HE MU Standalone UL MU-MIMO Basic Trigger completed with error(s)*/ - A_UINT32 standalone_ax_ulmumimo_trigger_err[HTT_NUM_AC_WMM]; } htt_stats_tx_selfgen_ax_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_selfgen_ax_stats_tlv htt_tx_selfgen_ax_stats_tlv; @@ -3994,97 +3138,10 @@ typedef struct { A_UINT32 be_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM]; /** 11BE EHT MU-BAR Trigger frames per AC completed with error(s) */ A_UINT32 be_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Combined UL OFDMA Basic Trigger frame sent over the air */ - A_UINT32 combined_be_ulofdma_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Combined UL OFDMA Basic Trigger completed with error(s) */ - A_UINT32 combined_be_ulofdma_trigger_err[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Standalone UL OFDMA Basic Trigger frame sent over the air */ - A_UINT32 standalone_be_ulofdma_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Standalone UL OFDMA Basic Trigger completed with error(s) */ - A_UINT32 standalone_be_ulofdma_trigger_err[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Combined UL MU-MIMO Basic Trigger frame sent over the air */ - A_UINT32 combined_be_ulmumimo_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Combined UL MU-MIMO Basic Trigger completed with error(s) */ - A_UINT32 combined_be_ulmumimo_trigger_err[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Standalone UL MU-MIMO Basic Trigger frame sent over the air */ - A_UINT32 standalone_be_ulmumimo_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Standalone UL MU-MIMO Basic Trigger completed with error(s) */ - A_UINT32 standalone_be_ulmumimo_trigger_err[HTT_NUM_AC_WMM]; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_selfgen_be_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_selfgen_be_stats_tlv htt_tx_selfgen_be_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** 11bn UHR MU Basic Trigger frame sent over the air */ - A_UINT32 bn_basic_trigger; - /** 11bn UHR MU BSRP Trigger frame sent over the air */ - A_UINT32 bn_bsr_trigger; - /** 11bn UHR MU BAR Trigger frame sent over the air */ - A_UINT32 bn_mu_bar_trigger; - /** 11bn UHR MU RTS Trigger frame sent over the air */ - A_UINT32 bn_mu_rts_trigger; - - /** 11BN UHR MU Combined Freq. BSRP Trigger frame sent over the air */ - A_UINT32 combined_bn_bsr_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BN UHR MU Combined Freq. BSRP Trigger completed with error(s) */ - A_UINT32 combined_bn_bsr_trigger_err[HTT_NUM_AC_WMM]; - /** 11BN UHR MU Standalone Freq. BSRP Trigger frame sent over the air */ - A_UINT32 standalone_bn_bsr_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BN UHR MU Standalone Freq. BSRP Trigger completed with error(s) */ - A_UINT32 standalone_bn_bsr_trigger_err[HTT_NUM_AC_WMM]; - /** 11BN UHR Manual Single-User UL OFDMA Trigger frame sent over the air */ - A_UINT32 manual_bn_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; - /** 11BN UHR Manual Single-User UL OFDMA Trigger completed with error(s) */ - A_UINT32 manual_bn_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; - /** 11BN UHR Manual Multi-User UL OFDMA Trigger frame sent over the air */ - A_UINT32 manual_bn_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; - /** 11BN UHR Manual Multi-User UL OFDMA Trigger completed with error(s) */ - A_UINT32 manual_bn_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; - - /** 11BN UHR UL OFDMA RU allocation mode */ - A_UINT32 bn_basic_trig_ru_alloc_mode[HTT_BN_UL_OFDMA_NUM_RU_ALLOC_MODES]; - - /** 11bn UHR MU UL-MUMIMO Trigger frame sent over the air */ - A_UINT32 bn_ulmumimo_trigger; - /** - * 11bn UHR UL-MUMIMO Trigger frame for users 0 - 7 - * successfully sent over the air - */ - A_UINT32 bn_ul_mumimo_trigger[HTT_TX_PDEV_STATS_NUM_BN_MUMIMO_USER_STATS]; - /** 11BN UHR MU Combined UL MU-MIMO Basic Trigger frame sent over the air */ - A_UINT32 combined_bn_ulmumimo_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BN UHR MU Combined UL MU-MIMO Basic Trigger completed with error(s) */ - A_UINT32 combined_bn_ulmumimo_trigger_err[HTT_NUM_AC_WMM]; - /** - * 11BN UHR MU Standalone UL MU-MIMO Basic Trigger frame - * sent over the air - */ - A_UINT32 standalone_bn_ulmumimo_trigger_tried[HTT_NUM_AC_WMM]; - /** - * 11BN UHR MU Standalone UL MU-MIMO Basic Trigger - * completed with error(s) - */ - A_UINT32 standalone_bn_ulmumimo_trigger_err[HTT_NUM_AC_WMM]; - - /** 11bn UHR BSRP trigger to DPS client sent over the air */ - A_UINT32 sta_dps_bn_bsr_trigger[HTT_NUM_AC_WMM]; - /** 11bn UHR MU RTS trigger to DPS client sent over the air */ - A_UINT32 sta_dps_bn_mu_rts_trigger[HTT_NUM_AC_WMM]; - /** 11bn UHR BSRP trigger to DPS client completed with error(s) */ - A_UINT32 sta_dps_bn_bsr_trigger_err[HTT_NUM_AC_WMM]; - /** 11bn UHR MU RTS trigger to DPS client completed with errors(s) */ - A_UINT32 sta_dps_bn_mu_rts_trigger_err[HTT_NUM_AC_WMM]; - - /** 11BN UHR UL OFDMA RU allocation mode - trigger error count */ - A_UINT32 bn_basic_trig_ru_alloc_mode_err[HTT_BN_UL_OFDMA_NUM_RU_ALLOC_MODES]; -} htt_stats_tx_selfgen_bn_tlv; - typedef struct { /* DEPRECATED */ htt_tlv_hdr_t tlv_hdr; /** 11AX HE OFDMA NDPA frame queued to the HW */ @@ -4498,165 +3555,6 @@ typedef struct { A_UINT32 be_ofdma_total_cv; } htt_stats_txbf_ofdma_be_parbw_tlv; -typedef struct { - /** 11BN UHR OFDMA NDPA frame queued to the HW */ - A_UINT32 bn_ofdma_ndpa_queued; - /** 11BN UHR OFDMA NDPA frame sent over the air */ - A_UINT32 bn_ofdma_ndpa_tried; - /** 11BN UHR OFDMA NDPA frame flushed by HW */ - A_UINT32 bn_ofdma_ndpa_flushed; - /** 11BN UHR OFDMA NDPA frame completed with error(s) */ - A_UINT32 bn_ofdma_ndpa_err; -} htt_txbf_ofdma_bn_ndpa_stats_elem_t; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * This field is populated with the num of elems in the bn_ndpa[] - * variable length array. - */ - A_UINT32 num_elems_bn_ndpa_arr; - /** - * This field will be filled by target with value of - * sizeof(htt_txbf_ofdma_bn_ndpa_stats_elem_t). - * This is for allowing host to infer how much data target has provided, - * even if it using different version of the struct than what target - * had used. - */ - A_UINT32 arr_elem_size_bn_ndpa; - HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_bn_ndpa_stats_elem_t, bn_ndpa); -} htt_stats_txbf_ofdma_bn_ndpa_tlv; - -typedef struct { - /** 11BN UHR OFDMA NDP frame queued to the HW */ - A_UINT32 bn_ofdma_ndp_queued; - /** 11BN UHR OFDMA NDPA frame sent over the air */ - A_UINT32 bn_ofdma_ndp_tried; - /** 11BN UHR OFDMA NDPA frame flushed by HW */ - A_UINT32 bn_ofdma_ndp_flushed; - /** 11BN UHR OFDMA NDPA frame completed with error(s) */ - A_UINT32 bn_ofdma_ndp_err; -} htt_txbf_ofdma_bn_ndp_stats_elem_t; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * This field is populated with the num of elems in the bn_ndp[] - * variable length array. - */ - A_UINT32 num_elems_bn_ndp_arr; - /** - * This field will be filled by target with value of - * sizeof(htt_txbf_ofdma_bn_ndp_stats_elem_t). - * This is for allowing host to infer how much data target has provided, - * even if it using different version of the struct than what target - * had used. - */ - A_UINT32 arr_elem_size_bn_ndp; - HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_bn_ndp_stats_elem_t, bn_ndp); -} htt_stats_txbf_ofdma_bn_ndp_tlv; - -typedef struct { - /** 11BN UHR OFDMA MU BRPOLL frame queued to the HW */ - A_UINT32 bn_ofdma_brpoll_queued; - /** 11BN UHR OFDMA MU BRPOLL frame sent over the air */ - A_UINT32 bn_ofdma_brpoll_tried; - /** 11BN UHR OFDMA MU BRPOLL frame flushed by HW */ - A_UINT32 bn_ofdma_brpoll_flushed; - /** 11BN UHR OFDMA MU BRPOLL frame completed with error(s) */ - A_UINT32 bn_ofdma_brp_err; - /** - * Number of CBF(s) received when 11BN UHR OFDMA MU BRPOLL frame - * completed with error(s) - */ - A_UINT32 bn_ofdma_brp_err_num_cbf_rcvd; -} htt_txbf_ofdma_bn_brp_stats_elem_t; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * This field is populated with the num of elems in the bn_brp[] - * variable length array. - */ - A_UINT32 num_elems_bn_brp_arr; - /** - * This field will be filled by target with value of - * sizeof(htt_txbf_ofdma_bn_brp_stats_elem_t). - * This is for allowing host to infer how much data target has provided, - * even if it using different version of the struct than what target - * had used - */ - A_UINT32 arr_elem_size_bn_brp; - HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_bn_brp_stats_elem_t, bn_brp); -} htt_stats_txbf_ofdma_bn_brp_tlv; - -typedef struct { - /** - * 11BN UHR OFDMA PPDUs that were sent over the air with steering - * (TXBF + OFDMA) - */ - A_UINT32 bn_ofdma_num_ppdu_steer; - /** 11BN UHR OFDMA PPDUs that were sent over the air in open loop */ - A_UINT32 bn_ofdma_num_ppdu_ol; - /** - * 11BN UHR OFDMA number of users for which CBF prefetch was initiated - * to PHY HW during TX - */ - A_UINT32 bn_ofdma_num_usrs_prefetch; - /** - * 11BN UHR OFDMA number of users for which sounding was initiated - * during TX - */ - A_UINT32 bn_ofdma_num_usrs_sound; - /** - * 11BN UHR OFDMA number of users for which sounding was forced during TX - */ - A_UINT32 bn_ofdma_num_usrs_force_sound; -} htt_txbf_ofdma_bn_steer_stats_elem_t; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * This field is populated with the num of elems in the bn_steer[] - * variable length array. - */ - A_UINT32 num_elems_bn_steer_arr; - /** - * This field will be filled by target with value of - * sizeof(htt_txbf_ofdma_bn_steer_stats_elem_t). - * This is for allowing host to infer how much data target has provided, - * even if it using different version of the struct than what target - * had used. - */ - A_UINT32 arr_elem_size_bn_steer; - HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_bn_steer_stats_elem_t, bn_steer); -} htt_stats_txbf_ofdma_bn_steer_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* 11BN UHR OFDMA MPDUs tried in rbo steering */ - A_UINT32 bn_ofdma_rbo_steer_mpdus_tried; - /* 11BN UHR OFDMA MPDUs failed in rbo steering */ - A_UINT32 bn_ofdma_rbo_steer_mpdus_failed; - /* 11BN UHR OFDMA MPDUs tried in sifs steering */ - A_UINT32 bn_ofdma_sifs_steer_mpdus_tried; - /* 11BN UHR OFDMA MPDUs failed in sifs steering */ - A_UINT32 bn_ofdma_sifs_steer_mpdus_failed; -} htt_stats_txbf_ofdma_bn_steer_mpdu_tlv; - -/* HTT_STATS_TXBF_OFDMA_BN_PARBW_TAG stats TLV: - * Sent by target in response to HTT_DBG_EXT_STATS_TXBF_OFDMA stats ID request. - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* Num of UHR TxBF Partial Bandwidth soundings */ - A_UINT32 bn_ofdma_parbw_user_snd; - /* Num of UHR Partial Bandwidth Sounded CVs received */ - A_UINT32 bn_ofdma_parbw_cv; - /* Num of 11BN EHT Total CVs received */ - A_UINT32 bn_ofdma_total_cv; -} htt_stats_txbf_ofdma_bn_parbw_tlv; - /* STATS_TYPE : HTT_DBG_EXT_STATS_TXBF_OFDMA * TLV_TAGS: * - HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG @@ -4669,11 +3567,6 @@ typedef struct { * - HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG * - HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG * - HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG - * - HTT_STATS_TXBF_OFDMA_BN_NDPA_TAG - * - HTT_STATS_TXBF_OFDMA_BN_NDP_TAG - * - HTT_STATS_TXBF_OFDMA_BN_BRP_TAG - * - HTT_STATS_TXBF_OFDMA_BN_STEER_TAG - * - HTT_STATS_TXBF_OFDMA_BN_STEER_MPDU_TAG */ typedef struct { @@ -4826,45 +3719,10 @@ typedef struct { A_UINT32 be_mu_rts_trigger_blocked; /** 11BE EHT MU BSR Trigger frame blocked due to partner link TX/RX(eMLSR) */ A_UINT32 be_bsr_trigger_blocked; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_selfgen_be_err_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_selfgen_be_err_stats_tlv htt_tx_selfgen_be_err_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** 11BN UHR MU Basic Trigger frame completed with error(s) */ - A_UINT32 bn_basic_trigger_err; - /** 11BN UHR MU BSRP Trigger frame completed with error(s) */ - A_UINT32 bn_bsr_trigger_err; - /** 11BN UHR MU BAR Trigger frame completed with error(s) */ - A_UINT32 bn_mu_bar_trigger_err; - /** 11BN UHR MU RTS Trigger frame completed with error(s) */ - A_UINT32 bn_mu_rts_trigger_err; - - /** 11BN UHR MU OFDMA Basic Trigger frame completed with partial user response */ - A_UINT32 bn_basic_trigger_partial_resp; - /** 11BN UHR MU BSRP Trigger frame completed with partial user response */ - A_UINT32 bn_bsr_trigger_partial_resp; - /** 11BN UHR MU BAR Trigger frame completed with partial user response */ - A_UINT32 bn_mu_bar_trigger_partial_resp; - /** 11BN UHR MU RTS Trigger frame blocked due to partner link TX/RX(eMLSR) */ - A_UINT32 bn_mu_rts_trigger_blocked; - /** 11BN UHR MU BSR Trigger frame blocked due to partner link TX/RX(eMLSR) */ - A_UINT32 bn_bsr_trigger_blocked; - - /** 11BN UHR MU ULMUMIMO Trigger frame completed with error(s) */ - A_UINT32 bn_ulmumimo_trigger_err; - /** - * 11BN UHR UL-MUMIMO Trigger frame for users 0 - 7 completed with error(s) - */ - A_UINT32 bn_ul_mumimo_trigger_err[HTT_TX_PDEV_STATS_NUM_BN_MUMIMO_USER_STATS]; -} htt_stats_tx_selfgen_bn_err_tlv; - /* * Scheduler completion status reason code. * (0) HTT_TXERR_NONE - No error (Success). @@ -4991,29 +3849,11 @@ typedef struct { A_UINT32 be_ulmumimo_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; /** 11BE EHT UL MUMIMO Basic Trigger scheduler error code */ A_UINT32 be_ulmumimo_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_selfgen_be_sched_status_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_selfgen_be_sched_status_stats_tlv htt_tx_selfgen_be_sched_status_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** 11BN UHR MU BAR scheduler completion status reason code */ - A_UINT32 bn_mu_bar_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /** 11BN UHR MU BAR scheduler error code */ - A_UINT32 bn_mu_bar_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - - /** 11BN UHR UL OFDMA Basic Trigger scheduler completion status reason code */ - A_UINT32 bn_basic_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /** 11BN UHR UL OFDMA Basic Trigger scheduler error code */ - A_UINT32 bn_basic_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; -} htt_stats_tx_selfgen_bn_sched_status_tlv; - /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SELFGEN_INFO * TLV_TAGS: * - HTT_STATS_TX_SELFGEN_CMN_STATS_TAG @@ -5026,9 +3866,6 @@ typedef struct { * - HTT_STATS_TX_SELFGEN_BE_STATS_TAG * - HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG * - HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG - * - HTT_STATS_TX_SELFGEN_BN_TAG - * - HTT_STATS_TX_SELFGEN_BN_ERR_TAG - * - HTT_STATS_TX_SELFGEN_BN_SCHED_STATUS_TAG */ /* NOTE: * This structure is for documentation, and cannot be safely used directly. @@ -5046,9 +3883,6 @@ typedef struct { htt_stats_tx_selfgen_be_stats_tlv be_tlv; htt_stats_tx_selfgen_be_err_stats_tlv be_err_tlv; htt_stats_tx_selfgen_be_sched_status_stats_tlv be_sched_status_tlv; - htt_stats_tx_selfgen_bn_tlv bn_tlv; - htt_stats_tx_selfgen_bn_err_tlv bn_err_tlv; - htt_stats_tx_selfgen_bn_sched_status_tlv bn_sched_status_tlv; } htt_tx_pdev_selfgen_stats_t; #endif /* ATH_TARGET */ @@ -5104,11 +3938,6 @@ typedef struct { A_UINT32 be_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; /** Number of 11AC DL MU MIMO schedules posted per group size (4-7) */ A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz_ext[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_pdev_mu_mimo_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_mu_mimo_stats_tlv htt_tx_pdev_mu_mimo_sch_stats_tlv; @@ -5168,11 +3997,6 @@ typedef struct { A_UINT32 be_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; /** Number of 11AC DL MU MIMO schedules posted per group size (4 - 7)*/ A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz_ext[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_pdev_dl_mu_mimo_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_dl_mu_mimo_stats_tlv @@ -5196,15 +4020,6 @@ typedef struct { typedef htt_stats_tx_pdev_be_dl_mu_ofdma_stats_tlv htt_tx_pdev_be_dl_mu_ofdma_sch_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** Represents the count for 11BN DL MU OFDMA sequences */ - A_UINT32 bn_mu_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS]; -} htt_stats_tx_pdev_bn_dl_mu_ofdma_stats_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_tx_pdev_bn_dl_mu_ofdma_stats_tlv - htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv; - typedef struct { htt_tlv_hdr_t tlv_hdr; /** @@ -5251,28 +4066,6 @@ typedef struct { typedef htt_stats_tx_pdev_be_ul_mu_ofdma_stats_tlv htt_tx_pdev_be_ul_mu_ofdma_sch_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * Represents the count for 11BN UL MU OFDMA sequences with Basic Triggers - */ - A_UINT32 bn_ul_mu_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS]; - /** - * Represents the count for 11BN UL MU OFDMA sequences with BSRP Triggers - */ - A_UINT32 bn_ul_mu_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS]; - /** - * Represents the count for 11BN UL MU OFDMA sequences with BAR Triggers - */ - A_UINT32 bn_ul_mu_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS]; - /** - * TODO_BORON_OFDMA : Add array for BN_BRP number of users - */ -} htt_stats_tx_pdev_bn_ul_mu_ofdma_stats_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_tx_pdev_bn_ul_mu_ofdma_stats_tlv - htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv; - typedef struct { htt_tlv_hdr_t tlv_hdr; /** @@ -5303,18 +4096,6 @@ typedef struct { typedef htt_stats_tx_pdev_be_ul_mu_mimo_stats_tlv htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * Represents the count for 11BN UL MU MIMO sequences with Basic Triggers - */ - A_UINT32 bn_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; - /** - * Represents the count for 11BN UL MU MIMO sequences with BRP Triggers - */ - A_UINT32 bn_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; -} htt_stats_tx_pdev_bn_ul_mu_mimo_tlv; - typedef struct { htt_tlv_hdr_t tlv_hdr; /** 11AC DL MU MIMO number of mpdus queued to HW, per user */ @@ -5371,7 +4152,6 @@ typedef htt_stats_tx_pdev_mumimo_mpdu_stats_tlv #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX 3 /* SCHED_TX_MODE_MU_OFDMA_AX */ #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BE 4 /* SCHED_TX_MODE_MU_OFDMA_BE */ #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_BE 5 /* SCHED_TX_MODE_MU_MIMO_BE */ -#define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BN 6 /* SCHED_TX_MODE_MU_OFDMA_BN */ typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -5386,11 +4166,6 @@ typedef struct { A_UINT32 user_index; /** HTT_STATS_TX_SCHED_MODE_xxx */ A_UINT32 tx_sched_mode; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_pdev_mpdu_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_mpdu_stats_tlv htt_tx_pdev_mpdu_stats_tlv; @@ -5427,8 +4202,8 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /** Scheduler command posted per tx_mode (length = num tx modes) */ - HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_cmd_posted); + /** Scheduler command posted per tx_mode */ + A_UINT32 sched_cmd_posted[1/* length = num tx modes */]; } htt_stats_sched_txq_cmd_posted_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_sched_txq_cmd_posted_tlv htt_sched_txq_cmd_posted_tlv_v; @@ -5438,8 +4213,8 @@ typedef htt_stats_sched_txq_cmd_posted_tlv htt_sched_txq_cmd_posted_tlv_v; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /** Scheduler command reaped per tx_mode (length = num tx modes) */ - HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_cmd_reaped); + /** Scheduler command reaped per tx_mode */ + A_UINT32 sched_cmd_reaped[1/* length = num tx modes */]; } htt_stats_sched_txq_cmd_reaped_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_sched_txq_cmd_reaped_tlv htt_sched_txq_cmd_reaped_tlv_v; @@ -5467,35 +4242,6 @@ typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 htt_stats_type; } htt_stats_error_tlv_v; -/* Multiple TLV tag values - * (HTT_STATS_UNSUPPORTED_ERROR_STATS_TAG, - * HTT_STATS_UNAVAILABLE_ERROR_STATS_TAG) - * correspond to this htt_stats_error_tlv_v struct. - * Provide aliases that have the expected names - * that are consistent with the TLV tag enum names. - */ -typedef htt_stats_error_tlv_v - htt_stats_unsupported_error_stats_tlv; -typedef htt_stats_error_tlv_v - htt_stats_unavailable_error_stats_tlv; - -/* NOTE: Variable length TLV, use length spec to infer array size */ -#define HTT_STATS_SCHED_TXQ_TX_MODE_SIMPLIFIED_TLV_SZ(_num_elems) \ - (sizeof(A_UINT32) * (_num_elems)) -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** Scheduler command posted per tx_mode (length = num tx modes+1) */ - HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_tx_mode_simplified); -} htt_stats_sched_txq_tx_mode_simplified_tlv; - -/* NOTE: Variable length TLV, use length spec to infer array size */ -#define HTT_STATS_SCHED_TXQ_TX_MODE_WINNER_TLV_SZ(_num_elems) \ - (sizeof(A_UINT32) * (_num_elems)) -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** Scheduler command posted per tx_mode (length = num tx modes+1) */ - HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_tx_mode_winner); -} htt_stats_sched_txq_tx_mode_winner_tlv; typedef enum { HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0, /* Skip the tid when WAL_TID_DISABLE_TX_SCHED_MASK is true */ @@ -5587,107 +4333,12 @@ typedef struct { * These supercycle trigger counts are not automatically reset, but * are reset upon request. */ - HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, supercycle_triggers); + A_UINT32 supercycle_triggers[1/*HTT_SCHED_SUPERCYCLE_TRIGGER_MAX*/]; } htt_stats_sched_txq_supercycle_trigger_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_sched_txq_supercycle_trigger_tlv htt_sched_txq_supercycle_triggers_tlv_v; -/* htt_tx_pdev_txq_stats_upload_t - * Enumerations for specifying which stats to upload in response to - * HTT_DBG_PDEV_TXQ_STATS. - */ -typedef enum { - /* upload all data TXQ stats */ - HTT_UPLOAD_DATA_TXQ_STATS, - /* upload MGMT/TWT TXQ stats */ - HTT_UPLOAD_MGMT_TWT_TXQ_STATS, -} htt_tx_pdev_txq_stats_upload_t; - -typedef enum { - /* Sequence combine successful */ - HTT_SCHED_COMBINED_SEQ_STATUS_SUCCESS = 0, - - /* Seq combine abort due to no prev sequence */ - HTT_SCHED_COMBINED_SEQ_STATUS_NO_ACTIVE_PREV_SEQ, - - /* Seq combine abort due to back to back allow flag set */ - HTT_SCHED_COMBINED_SEQ_STATUS_B2B_ALLOW_FLAG, - - /* combining will be disabled if sounding sequence is to be combined */ - HTT_SCHED_COMBINED_SEQ_STATUS_SOUNDING_SEQ_ABORT, - - /* Seq combine abort due to seq not constructed */ - HTT_SCHED_COMBINED_SEQ_STATUS_SEQ_NOT_CONSTRUCTED, - - /* Seq combine abort and subring change */ - HTT_SCHED_COMBINED_SEQ_STATUS_HW_PAUSED_SEQ_CONSRUCTED, - - /* Seq combine abort and indicate TAC */ - HTT_SCHED_COMBINED_SEQ_STATUS_HW_PAUSED_SEQ_NOT_CONSTRUCTED, - - /* Seq combine abort and seq restart */ - HTT_SCHED_COMBINED_SEQ_STATUS_HW_PAUSED_SEQ_POSTED, - - HTT_SCHED_COMBINED_SEQ_STATUS_MAX -} htt_sched_txq_combined_seq_status_tlv_enum; - -#define HTT_SCHED_TXQ_COMBINED_SEQ_STATE_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) - -/* NOTE: Variable length TLV, use length spec to infer array size */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * combined_seq_state counts the number of occurrences of different - * reasons for aborting combining two different sequence in TAC - * during posting - * - * Indexed by htt_sched_txq_combined_seq_status_tlv_enum. - */ - HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, combined_seq_state); -} htt_stats_txq_combined_seq_state_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_txq_combined_seq_state_tlv - htt_stats_sched_txq_combined_seq_state_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - A_UINT32 pdev_id__word; - struct { - A_UINT32 - pdev_id: 8, - reserved: 24; - }; - }; - A_UINT32 ist_txop_end_indicated_cnt; - A_UINT32 ist_txop_end_notify_at_cmd_status_end; - A_UINT32 ist_txop_end_notify_at_isr_end; - A_UINT32 sched_cmd_post_skip_on_seq_unavail; - A_UINT32 ist_txop_end_skip_on_seq_unavail; - A_UINT32 ist_txop_end_skip_on_mpdu_ownership; - A_UINT32 skip_early_schedule_due_to_per; - A_UINT32 sched_cmd_posted_at_hw_txop_end; - A_UINT32 sched_cmd_missed_at_hw_txop_end; - A_UINT32 sched_cmd_posted_at_sched_cmd_compl; - A_UINT32 sched_cmd_missed_at_sched_cmd_compl; - A_UINT32 num_QoS_sched_runs; -} htt_stats_sched_txq_early_compl_tlv; - -#define HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_M 0x000000ff -#define HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_S 0 - -#define HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_GET(_var) \ - (((_var) & HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_M) >> \ - HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_S) - -#define HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_S)); \ - } while (0) - - #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_M 0x000000ff #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S 0 @@ -5782,30 +4433,6 @@ typedef struct { A_UINT32 num_subcycles_with_sort; /** Num of subcycles without sort for this Txq */ A_UINT32 num_subcycles_no_sort; - /** num of times DPS client is scheduled */ - A_UINT32 num_dps_client_scheduled; - /** - * Number of first sched_cmd allowed for DL+UL/UL+DL sched_cmd combining - */ - A_UINT32 num_allowed_first_sched_command_for_combining; - /** - * Number of second sched_cmd allowed for DL+UL/UL+DL sched_cmd combining - */ - A_UINT32 num_allowed_second_command_for_combining; - /** - * Number of first sched_cmd aborted to avoid DL+UL/UL+DL sched_cmd - * combining - */ - A_UINT32 num_aborted_first_sched_command; - /** - * Number of second sched_cmd aborted to avoid DL+UL/UL+DL sched_cmd - * combining - */ - A_UINT32 num_aborted_second_sched_command; - /** Number combined sched_cmds sucessfully transmitted */ - A_UINT32 total_combined_sched_cmds_success; - /** Number combined sched_cmds failed to transmit */ - A_UINT32 total_combined_sched_cmds_failed; } htt_stats_tx_pdev_scheduler_txq_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_scheduler_txq_stats_tlv @@ -5831,13 +4458,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Current timestamp */ A_UINT32 current_timestamp; } htt_stats_tx_sched_cmn_tlv; @@ -5851,28 +4472,22 @@ typedef struct { * - HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG * - HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG * - HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG - * - HTT_STATS_SCHED_TXQ_EARLY_COMPL_TAG */ /* NOTE: * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ -#ifdef ATH_TARGET typedef struct { htt_stats_tx_sched_cmn_tlv cmn_tlv; struct { - htt_stats_tx_pdev_scheduler_txq_stats_tlv txq_tlv; - htt_stats_sched_txq_cmd_posted_tlv cmd_posted_tlv; - htt_stats_sched_txq_cmd_reaped_tlv cmd_reaped_tlv; + htt_stats_tx_pdev_scheduler_txq_stats_tlv txq_tlv; + htt_stats_sched_txq_cmd_posted_tlv cmd_posted_tlv; + htt_stats_sched_txq_cmd_reaped_tlv cmd_reaped_tlv; htt_stats_sched_txq_sched_order_su_tlv sched_order_su_tlv; htt_stats_sched_txq_sched_ineligibility_tlv sched_ineligibility_tlv; - htt_stats_sched_txq_supercycle_trigger_tlv - htt_sched_txq_sched_ineligibility_tlv_esched_supercycle_trigger_tlv; - htt_stats_sched_txq_early_compl_tlv early_compl_tlv; - htt_stats_sched_txq_combined_seq_state_tlv combined_seq_state_tlv; + htt_stats_sched_txq_supercycle_trigger_tlv htt_sched_txq_sched_ineligibility_tlv_esched_supercycle_trigger_tlv; } txq[1]; } htt_stats_tx_sched_t; -#endif /* == TQM STATS == */ @@ -5964,15 +4579,6 @@ typedef struct { A_UINT32 tqm_enqueue_msdu_count; A_UINT32 tqm_dropped_msdu_count; A_UINT32 tqm_dequeue_msdu_count; - - A_UINT32 tqm_enqueue_msdu_count_ac[HTT_NUM_AC_WMM]; - A_UINT32 tqm_dropped_msdu_count_ac[HTT_NUM_AC_WMM]; - A_UINT32 tqm_dequeue_msdu_count_ac[HTT_NUM_AC_WMM]; - A_UINT32 remove_msdu_ac[HTT_NUM_AC_WMM]; - A_UINT32 remove_mpdu_ac[HTT_NUM_AC_WMM]; - A_UINT32 remove_msdu_ttl_ac[HTT_NUM_AC_WMM]; - A_UINT32 remove_mpdu_ttl_ac[HTT_NUM_AC_WMM]; - A_UINT32 remove_mpdu_retries_ac[HTT_NUM_AC_WMM]; } htt_stats_tx_tqm_pdev_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_tqm_pdev_tlv htt_tx_tqm_pdev_stats_tlv_v; @@ -5983,9 +4589,7 @@ typedef htt_stats_tx_tqm_pdev_tlv htt_tx_tqm_pdev_stats_tlv_v; #define HTT_TX_TQM_CMN_STATS_MAC_ID_GET(_var) \ (((_var) & HTT_TX_TQM_CMN_STATS_MAC_ID_M) >> \ HTT_TX_TQM_CMN_STATS_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TQM_CMN_MAC_ID_GET(_var) \ - HTT_TX_TQM_CMN_STATS_MAC_ID_GET(_var) + #define HTT_TX_TQM_CMN_STATS_MAC_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TQM_CMN_STATS_MAC_ID, _val); \ @@ -5999,13 +4603,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 max_cmdq_id; A_UINT32 list_mpdu_cnt_hist_intvl; @@ -6096,9 +4694,7 @@ typedef struct { #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_GET(_var) \ (((_var) & HTT_TX_TQM_CMDQ_STATUS_MAC_ID_M) >> \ HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TQM_CMDQ_STATUS_MAC_ID_GET(_var) \ - HTT_TX_TQM_CMDQ_STATUS_MAC_ID_GET(_var) + #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_MAC_ID, _val); \ @@ -6108,9 +4704,7 @@ typedef struct { #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_GET(_var) \ (((_var) & HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_M) >> \ HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TQM_CMDQ_STATUS_CMDQ_ID_GET(_var) \ - HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_GET(_var) + #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID, _val); \ @@ -6125,14 +4719,7 @@ typedef struct { * BIT [15 : 8] :- cmdq_id * BIT [31 : 16] :- reserved */ - union { - struct { - A_UINT32 mac_id : 8; - A_UINT32 cmdq_id : 8; - A_UINT32 reserved : 16; - }; - A_UINT32 mac_id__cmdq_id__word; - }; + A_UINT32 mac_id__cmdq_id__word; A_UINT32 sync_cmd; A_UINT32 write_cmd; A_UINT32 gen_mpdu_cmd; @@ -6368,13 +4955,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /* Global Stats */ A_UINT32 tcl2fw_entry_count; @@ -6391,38 +4972,8 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_de_cmn_tlv htt_tx_de_cmn_stats_tlv; -#define HTT_STATS_TX_DE_CMN_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - #define HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) ((dword >> 0) & 0xffff) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_RX_RING_STATS_SW2RXDMA_MAX_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_RXDMA2REO_MAX_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REO2SW1_MAX_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REO2SW4_MAX_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REFILLRINGIPA_MAX_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REFILLRINGHOST_MAX_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) - #define HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) ((dword >> 16) & 0xffff) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_RX_RING_STATS_SW2RXDMA_CURR_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_RXDMA2REO_CURR_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REO2SW1_CURR_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REO2SW4_CURR_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REFILLRINGIPA_CURR_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REFILLRINGHOST_CURR_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) /* Rx debug info for status rings */ typedef struct { @@ -6432,54 +4983,12 @@ typedef struct { * (size of the ring in terms of entries) * BIT [16 : 31] :- current number of entries occupied in respective ring */ - union { - A_UINT32 entry_status_sw2rxdma; - struct { - A_UINT32 - max_num_entries: 16, - curr_num_entries: 16; - } sw2rxdma; - }; - union { - A_UINT32 entry_status_rxdma2reo; - struct { - A_UINT32 - max_num_entries: 16, - curr_num_entries: 16; - } rxdma2reo; - }; - union { - A_UINT32 entry_status_reo2sw1; - struct { - A_UINT32 - max_num_entries: 16, - curr_num_entries: 16; - } reo2sw1; - }; - union { - A_UINT32 entry_status_reo2sw4; - struct { - A_UINT32 - max_num_entries: 16, - curr_num_entries: 16; - } reo2sw4; - }; - union { - A_UINT32 entry_status_refillringipa; - struct { - A_UINT32 - max_num_entries: 16, - curr_num_entries: 16; - } refillringipa; - }; - union { - A_UINT32 entry_status_refillringhost; - struct { - A_UINT32 - max_num_entries: 16, - curr_num_entries: 16; - } refillringhost; - }; + A_UINT32 entry_status_sw2rxdma; + A_UINT32 entry_status_rxdma2reo; + A_UINT32 entry_status_reo2sw1; + A_UINT32 entry_status_reo2sw4; + A_UINT32 entry_status_refillringipa; + A_UINT32 entry_status_refillringhost; /** datarate - Moving Average of Number of Entries */ A_UINT32 datarate_refillringipa; A_UINT32 datarate_refillringhost; @@ -6654,47 +5163,23 @@ typedef struct { * BIT [15 : 0] :- num_elems * BIT [31 : 16] :- prefetch_tail_idx */ - union { - struct { - A_UINT32 num_elems : 16; - A_UINT32 prefetch_tail_idx : 16; - }; - A_UINT32 num_elems__prefetch_tail_idx; - }; + A_UINT32 num_elems__prefetch_tail_idx; /** * BIT [15 : 0] :- head_idx * BIT [31 : 16] :- tail_idx */ - union { - struct { - A_UINT32 head_idx : 16; - A_UINT32 tail_idx : 16; - }; - A_UINT32 head_idx__tail_idx; - }; + A_UINT32 head_idx__tail_idx; /** * BIT [15 : 0] :- shadow_head_idx * BIT [31 : 16] :- shadow_tail_idx */ - union { - struct { - A_UINT32 shadow_head_idx : 16; - A_UINT32 shadow_tail_idx : 16; - }; - A_UINT32 shadow_head_idx__shadow_tail_idx; - }; + A_UINT32 shadow_head_idx__shadow_tail_idx; A_UINT32 num_tail_incr; /** * BIT [15 : 0] :- lwm_thresh * BIT [31 : 16] :- hwm_thresh */ - union { - struct { - A_UINT32 lwm_thresh : 16; - A_UINT32 hwm_thresh : 16; - }; - A_UINT32 lwm_thresh__hwm_thresh; - }; + A_UINT32 lwm_thresh__hwm_thresh; A_UINT32 overrun_hit_count; A_UINT32 underrun_hit_count; A_UINT32 prod_blockwait_count; @@ -6711,9 +5196,6 @@ typedef htt_stats_ring_if_tlv htt_ring_if_stats_tlv; #define HTT_RING_IF_CMN_MAC_ID_GET(_var) \ (((_var) & HTT_RING_IF_CMN_MAC_ID_M) >> \ HTT_RING_IF_CMN_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RING_IF_CMN_MAC_ID_GET(_var) \ - HTT_RING_IF_CMN_MAC_ID_GET(_var) #define HTT_RING_IF_CMN_MAC_ID_SET(_var, _val) \ do { \ @@ -6728,13 +5210,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 num_records; } htt_stats_ring_if_cmn_tlv; /* preserve old name alias for new name consistent with the tag name */ @@ -6800,9 +5276,7 @@ typedef htt_stats_sfm_client_tlv htt_sfm_client_tlv; #define HTT_SFM_CMN_MAC_ID_GET(_var) \ (((_var) & HTT_SFM_CMN_MAC_ID_M) >> \ HTT_SFM_CMN_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SFM_CMN_MAC_ID_GET(_var) \ - HTT_SFM_CMN_MAC_ID_GET(_var) + #define HTT_SFM_CMN_MAC_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SFM_CMN_MAC_ID, _val); \ @@ -6816,13 +5290,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** * Indicates the total number of 128 byte buffers in the CMEM * that are available for buffer sharing @@ -6881,9 +5349,7 @@ typedef struct { #define HTT_SRING_STATS_MAC_ID_GET(_var) \ (((_var) & HTT_SRING_STATS_MAC_ID_M) >> \ HTT_SRING_STATS_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_MAC_ID_GET(_var) \ - HTT_SRING_STATS_MAC_ID_GET(_var) + #define HTT_SRING_STATS_MAC_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_MAC_ID, _val); \ @@ -6893,9 +5359,7 @@ typedef struct { #define HTT_SRING_STATS_RING_ID_GET(_var) \ (((_var) & HTT_SRING_STATS_RING_ID_M) >> \ HTT_SRING_STATS_RING_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_RING_ID_GET(_var) \ - HTT_SRING_STATS_RING_ID_GET(_var) + #define HTT_SRING_STATS_RING_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_RING_ID, _val); \ @@ -6905,9 +5369,7 @@ typedef struct { #define HTT_SRING_STATS_ARENA_GET(_var) \ (((_var) & HTT_SRING_STATS_ARENA_M) >> \ HTT_SRING_STATS_ARENA_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_ARENA_GET(_var) \ - HTT_SRING_STATS_ARENA_GET(_var) + #define HTT_SRING_STATS_ARENA_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_ARENA, _val); \ @@ -6917,9 +5379,7 @@ typedef struct { #define HTT_SRING_STATS_EP_TYPE_GET(_var) \ (((_var) & HTT_SRING_STATS_EP_TYPE_M) >> \ HTT_SRING_STATS_EP_TYPE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_EP_GET(_var) \ - HTT_SRING_STATS_EP_TYPE_GET(_var) + #define HTT_SRING_STATS_EP_TYPE_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_EP_TYPE, _val); \ @@ -6936,9 +5396,7 @@ typedef struct { #define HTT_SRING_STATS_NUM_AVAIL_WORDS_GET(_var) \ (((_var) & HTT_SRING_STATS_NUM_AVAIL_WORDS_M) >> \ HTT_SRING_STATS_NUM_AVAIL_WORDS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_NUM_AVAIL_WORDS_GET(_var) \ - HTT_SRING_STATS_NUM_AVAIL_WORDS_GET(_var) + #define HTT_SRING_STATS_NUM_AVAIL_WORDS_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_AVAIL_WORDS, _val); \ @@ -6948,9 +5406,7 @@ typedef struct { #define HTT_SRING_STATS_NUM_VALID_WORDS_GET(_var) \ (((_var) & HTT_SRING_STATS_NUM_VALID_WORDS_M) >> \ HTT_SRING_STATS_NUM_VALID_WORDS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_NUM_VALID_WORDS_GET(_var) \ - HTT_SRING_STATS_NUM_VALID_WORDS_GET(_var) + #define HTT_SRING_STATS_NUM_VALID_WORDS_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_VALID_WORDS, _val); \ @@ -6967,9 +5423,7 @@ typedef struct { #define HTT_SRING_STATS_HEAD_PTR_GET(_var) \ (((_var) & HTT_SRING_STATS_HEAD_PTR_M) >> \ HTT_SRING_STATS_HEAD_PTR_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_HEAD_PTR_GET(_var) \ - HTT_SRING_STATS_HEAD_PTR_GET(_var) + #define HTT_SRING_STATS_HEAD_PTR_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_HEAD_PTR, _val); \ @@ -6979,9 +5433,7 @@ typedef struct { #define HTT_SRING_STATS_TAIL_PTR_GET(_var) \ (((_var) & HTT_SRING_STATS_TAIL_PTR_M) >> \ HTT_SRING_STATS_TAIL_PTR_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_TAIL_PTR_GET(_var) \ - HTT_SRING_STATS_TAIL_PTR_GET(_var) + #define HTT_SRING_STATS_TAIL_PTR_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_TAIL_PTR, _val); \ @@ -6998,9 +5450,7 @@ typedef struct { #define HTT_SRING_STATS_CONSUMER_EMPTY_GET(_var) \ (((_var) & HTT_SRING_STATS_CONSUMER_EMPTY_M) >> \ HTT_SRING_STATS_CONSUMER_EMPTY_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_CONSUMER_EMPTY_GET(_var) \ - HTT_SRING_STATS_CONSUMER_EMPTY_GET(_var) + #define HTT_SRING_STATS_CONSUMER_EMPTY_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_CONSUMER_EMPTY, _val); \ @@ -7010,9 +5460,7 @@ typedef struct { #define HTT_SRING_STATS_PRODUCER_FULL_GET(_var) \ (((_var) & HTT_SRING_STATS_PRODUCER_FULL_M) >> \ HTT_SRING_STATS_PRODUCER_FULL_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_PRODUCER_FULL_GET(_var) \ - HTT_SRING_STATS_PRODUCER_FULL_GET(_var) + #define HTT_SRING_STATS_PRODUCER_FULL_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_PRODUCER_FULL, _val); \ @@ -7029,9 +5477,7 @@ typedef struct { #define HTT_SRING_STATS_PREFETCH_COUNT_GET(_var) \ (((_var) & HTT_SRING_STATS_PREFETCH_COUNT_M) >> \ HTT_SRING_STATS_PREFETCH_COUNT_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_PREFETCH_COUNT_GET(_var) \ - HTT_SRING_STATS_PREFETCH_COUNT_GET(_var) + #define HTT_SRING_STATS_PREFETCH_COUNT_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_PREFETCH_COUNT, _val); \ @@ -7041,9 +5487,7 @@ typedef struct { #define HTT_SRING_STATS_INTERNAL_TP_GET(_var) \ (((_var) & HTT_SRING_STATS_INTERNAL_TP_M) >> \ HTT_SRING_STATS_INTERNAL_TP_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_INTERNAL_TAIL_PTR_GET(_var) \ - HTT_SRING_STATS_INTERNAL_TP_GET(_var) + #define HTT_SRING_STATS_INTERNAL_TP_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_INTERNAL_TP, _val); \ @@ -7060,16 +5504,7 @@ typedef struct { * BIT [24 : 24] :- EP 0 -consumer, 1 - producer * BIT [31 : 25] :- reserved */ - union { - struct { - A_UINT32 mac_id : 8; - A_UINT32 ring_id : 8; - A_UINT32 arena : 8; - A_UINT32 ep : 1; - A_UINT32 reserved : 7; - }; - A_UINT32 mac_id__ring_id__arena__ep; - }; + A_UINT32 mac_id__ring_id__arena__ep; /** DWORD aligned base memory address of the ring */ A_UINT32 base_addr_lsb; A_UINT32 base_addr_msb; @@ -7083,49 +5518,25 @@ typedef struct { * BIT [15 : 0] :- num_avail_words * BIT [31 : 16] :- num_valid_words */ - union { - struct { - A_UINT32 num_avail_words : 16; - A_UINT32 num_valid_words : 16; - }; - A_UINT32 num_avail_words__num_valid_words; - }; + A_UINT32 num_avail_words__num_valid_words; /** Index of head and tail * BIT [15 : 0] :- head_ptr * BIT [31 : 16] :- tail_ptr */ - union { - struct { - A_UINT32 head_ptr : 16; - A_UINT32 tail_ptr : 16; - }; - A_UINT32 head_ptr__tail_ptr; - }; + A_UINT32 head_ptr__tail_ptr; /** Empty or full counter of rings * BIT [15 : 0] :- consumer_empty * BIT [31 : 16] :- producer_full */ - union { - struct { - A_UINT32 consumer_empty : 16; - A_UINT32 producer_full : 16; - }; - A_UINT32 consumer_empty__producer_full; - }; + A_UINT32 consumer_empty__producer_full; /** Prefetch status of consumer ring * BIT [15 : 0] :- prefetch_count * BIT [31 : 16] :- internal_tail_ptr */ - union { - struct { - A_UINT32 prefetch_count : 16; - A_UINT32 internal_tail_ptr : 16; - }; - A_UINT32 prefetch_count__internal_tail_ptr; - }; + A_UINT32 prefetch_count__internal_tail_ptr; } htt_stats_sring_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_sring_stats_tlv htt_sring_stats_tlv; @@ -7162,9 +5573,7 @@ typedef struct { #define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ #define HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ -#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 /* 0-13 */ #define HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */ -#define HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS 4 /* 1.1, 3.1, 4.1, 7.1 */ #define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4 #define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5 #define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 @@ -7175,7 +5584,6 @@ typedef struct { #define HTT_TX_PDEV_STATS_NUM_LTF 4 #define HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES 6 #define HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES 6 -#define HTT_TX_PDEV_STATS_NUM_11BN_TRIGGER_TYPES 6 #define HTT_TX_VDEV_STATS_NUM_SPATIAL_STREAMS 4 #define HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \ (HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \ @@ -7194,19 +5602,6 @@ typedef struct { ((_var) |= ((_val) << HTT_TX_PDEV_RATE_STATS_MAC_ID_S)); \ } while (0) -#define HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_M 0x00000f00 -#define HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_S 8 - -#define HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_GET(_var) \ - (((_var) & HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_M) >> \ - HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_S) - -#define HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_PDEV_RATE_STATS_WIFI_VERSION, _val); \ - ((_var) |= ((_val) << HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_S)); \ - } while (0) - #define HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS \ (HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + \ HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + \ @@ -7232,13 +5627,9 @@ typedef enum { /* 11be related updates */ #define HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS 16 /* 0...13,-2,-1 */ #define HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ -/* 11bn MCS counters: all BE MCS indices and 4 UHR iMCS */ -#define HTT_TX_PDEV_STATS_NUM_BN_MCS_COUNTERS 20 -#define HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ #define HTT_TX_PDEV_STATS_NUM_HE_SIG_B_MCS_COUNTERS 6 #define HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS 4 -#define HTT_TX_PDEV_STATS_NUM_UHR_SIG_MCS_COUNTERS 4 typedef enum { HTT_TX_PDEV_STATS_AX_RU_SIZE_26, @@ -7271,39 +5662,14 @@ typedef enum { HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, } HTT_TX_PDEV_STATS_BE_RU_SIZE; -#define HTT_TX_PDEV_STATS_NUM_BN_RU_SIZE_COUNTERS \ - HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS - -typedef enum { - HTT_WIFI_VER_UNKNOWN = 0, - HTT_WIFI_VER_11N = 4, - HTT_WIFI_VER_11AC = 5, - HTT_WIFI_VER_11AX = 6, - HTT_WIFI_VER_11BE = 7, - HTT_WIFI_VER_11BN = 8, -} HTT_RX_TX_PDEV_STATS_WIFI_VERSION; - typedef struct { htt_tlv_hdr_t tlv_hdr; /** * BIT [ 7 : 0] :- mac_id - * BIT [11 : 8] :- wifi_version - * BIT [31 : 12] :- reserved + * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - /* wifi_version: - * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value. - * Refer to HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_GET - * / _SET macros for accessing this bitfield. - */ - wifi_version: 4, - reserved: 20; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Number of tx ldpc packets */ A_UINT32 tx_ldpc; /** Number of tx rts packets */ @@ -7426,7 +5792,7 @@ typedef struct { A_UINT32 ax_su_embedded_trigger_data_ppdu; /** 11AX HE SU data + embedded trigger PPDU failure stats (stats for HETP ack failure PPDU cnt) */ A_UINT32 ax_su_embedded_trigger_data_ppdu_err; - /** STA side trigger stats */ + /** sta side trigger stats */ A_UINT32 trigger_type_11be[HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES]; /** Stats for Extra EHT LTF */ A_UINT32 extra_eht_ltf; @@ -7434,51 +5800,10 @@ typedef struct { A_UINT32 extra_eht_ltf_ofdma; /** 11AX HE UL_BA RU Size stats */ A_UINT32 ofdma_ba_ru_size[HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS]; - /** Number of tx 2xldpc packets */ - A_UINT32 tx_2xldpc; - A_UINT32 rc_state_probe_mismatched; - /* npca_tx_bw: NPCA bw info - * element 0: 20 MHz - * element 1: 40 MHz - * element 2: 80 MHz - * element 3: 160 MHz - * element 4: 320 MHz - */ - A_UINT32 npca_tx_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - /* npca_tx_su_punctured_mode: NPCA punctured mode info - * element 0: no puncture - * element 1: 20 MHz punctured - * element 2: 40 MHz punctured - * element 3: 80 MHz punctured - * element 4: 120 MHz punctured - */ - A_UINT32 npca_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; - /* STA side trigger stats */ - A_UINT32 trigger_type_11bn[HTT_TX_PDEV_STATS_NUM_11BN_TRIGGER_TYPES]; -#if 0 - /* NOTE: - * The tx_mcs_ext_3 field is being reverted at least temporarily, - * to work around message size limits in certain targets. - * If/when this revert becomes permanent, this "#if 0" block will - * be removed altogether. - */ - /* Stats for iMCS 1.1, 3.1, 4.1, 7.1 */ - A_UINT32 tx_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS]; -#endif - -/* - * NOTE: THIS STRUCT HAS ONLY 20 BYTES OF SPACE LEFT - * WITHIN THE TARGET'S HTT_STATS_TLV_MAX_LEN SIZE LIMIT. - */ } htt_stats_tx_pdev_rate_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_rate_stats_tlv htt_tx_pdev_rate_stats_tlv; -#define HTT_STATS_TX_PDEV_RATE_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_TX_PDEV_RATE_STATS_WIFI_VERSION_GET(word) \ - (((word) >> 8) & 0xf) - typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 vdev_id; /* which vdev produced these per-Nss tx stats */ @@ -7506,11 +5831,6 @@ typedef struct { A_UINT32 be_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; /** 11BE DL MU MIMO LDPC count */ A_UINT32 be_mu_mimo_tx_ldpc; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_pdev_be_rate_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_be_rate_stats_tlv htt_tx_pdev_rate_stats_be_tlv; @@ -7564,13 +5884,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** 11BE EHT DL MU OFDMA LDPC count */ A_UINT32 be_ofdma_tx_ldpc; @@ -7588,44 +5902,17 @@ typedef struct { A_UINT32 be_ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; /** 11BE EHT DL MU OFDMA EHT-SIG MCS stats */ A_UINT32 be_ofdma_eht_sig_mcs[HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS]; - /** 11BE UHT DL MU OFDMA BA RU size stats */ A_UINT32 be_ofdma_ba_ru_size[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; - - /** 11BN UHR DL MU OFDMA LDPC count */ - A_UINT32 bn_ofdma_tx_ldpc; - /** 11BE UHR DL MU OFDMA TX MCS stats */ - A_UINT32 bn_ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_BN_MCS_COUNTERS]; - /** - * 11BN UHR DL MU OFDMA TX NSS stats (Indicates NSS for individual users) - */ - A_UINT32 bn_ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - /** 11BN UHR DL MU OFDMA TX BW stats */ - A_UINT32 bn_ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - /** 11BN UHR DL MU OFDMA TX guard interval stats */ - A_UINT32 bn_ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BN_MCS_COUNTERS]; - /** 11BN UHR DL MU OFDMA TX RU Size stats */ - A_UINT32 bn_ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_BN_RU_SIZE_COUNTERS]; - /** 11BN UHR DL MU OFDMA UHR-SIG MCS stats */ - A_UINT32 bn_ofdma_uhr_sig_mcs[HTT_TX_PDEV_STATS_NUM_UHR_SIG_MCS_COUNTERS]; - /** 11BN UHR DL MU OFDMA BA RU size stats */ - A_UINT32 bn_ofdma_ba_ru_size[HTT_TX_PDEV_STATS_NUM_BN_RU_SIZE_COUNTERS]; -} htt_stats_tx_pdev_rate_be_bn_ofdma_tlv; -/* preserve old names as aliases */ -typedef htt_stats_tx_pdev_rate_be_bn_ofdma_tlv - htt_stats_tx_pdev_rate_stats_be_ofdma_tlv; -typedef htt_stats_tx_pdev_rate_be_bn_ofdma_tlv +} htt_stats_tx_pdev_rate_stats_be_ofdma_tlv; +/* preserve old name alias for new name consistent with the tag name */ +typedef htt_stats_tx_pdev_rate_stats_be_ofdma_tlv htt_tx_pdev_rate_stats_be_ofdma_tlv; -#define HTT_STATS_TX_PDEV_RATE_BE_BN_OFDMA_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - typedef struct { htt_tlv_hdr_t tlv_hdr; /** tx_ppdu_dur_hist: * Tx PPDU duration histogram, which holds the tx duration of PPDUs * under histogram bins of interval 250us - * - * Note that this histogram is extended by tx_ppdu_dur_hist_ext[] below. */ A_UINT32 tx_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS]; A_UINT32 tx_success_time_us_low; @@ -7639,83 +5926,10 @@ typedef struct { * OFDMA PPDUs under histogram bins of interval 250us */ A_UINT32 tx_ofdma_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS]; - /* tx_ppdu_dur_hist_ext: - * This array extends the PPDU duration histogram contained in the - * tx_ppdu_dur_hist[] array from 4 ms to 5.5 ms. - */ - A_UINT32 tx_ppdu_dur_hist_ext[HTT_PDEV_STATS_PPDU_DUR_HIST_EXT_BINS]; } htt_stats_tx_pdev_ppdu_dur_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_ppdu_dur_tlv htt_tx_pdev_ppdu_dur_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** tx_txop_dur_hist: - * Tx txop duration histogram, which holds the total txop used - * under histogram bins of interval 1ms - */ - A_UINT32 tx_su_mdsb_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS]; - A_UINT32 tx_ofdma_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS]; - A_UINT32 tx_mimo_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS]; - A_UINT32 combined_sched_cmd_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS]; -} htt_stats_tx_pdev_txop_dur_tlv; - -#define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_M 0x000000ff -#define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_S 0 -#define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_GET(_var) \ - (((_var) & HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_M) >> \ - HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_PDEV_BN_RATE_MAC_ID_GET(_var) \ - HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_GET(_var) -#define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_PDEV_BN_RATE_STATS_MAC_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_S)); \ - } while (0) - -#define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_M 0x00000f00 -#define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_S 8 -#define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_GET(_var) \ - (((_var) & HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_M) >> \ - HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_PDEV_BN_RATE_WIFI_VERSION_GET(_var) \ - HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_GET(_var) -#define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION, _val); \ - ((_var) |= ((_val) << HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_S)); \ - } while (0) - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * BIT [ 7 : 0] :- mac_id - * BIT [11 : 8] :- wifi_version - * BIT [31 : 12] :- reserved - */ - union { - struct { - A_UINT32 mac_id: 8, - /* wifi_version: - * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value. - * Refer to HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_GET - * / _SET macros for accessing this bitfield. - */ - wifi_version: 4, - reserved: 20; - }; - A_UINT32 mac_id__word; - }; - /* Stats for iMCS 1.1, 3.1, 4.1, 7.1 */ - A_UINT32 tx_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS]; - A_UINT32 tx_gi_ext_3[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS]; - A_UINT32 tx_stbc_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS]; - /* Stats for UHR ELR */ - A_UINT32 tx_11bn_su_elr; -} htt_stats_tx_pdev_bn_rate_tlv; - /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE * TLV_TAGS: * - HTT_STATS_TX_PDEV_RATE_STATS_TAG @@ -7726,12 +5940,10 @@ typedef struct { */ #ifdef ATH_TARGET typedef struct { - htt_stats_tx_pdev_bn_rate_tlv rate_bn_tlv; htt_stats_tx_pdev_rate_stats_tlv rate_tlv; htt_stats_tx_pdev_be_rate_stats_tlv rate_be_tlv; htt_stats_tx_pdev_sawf_rate_stats_tlv rate_sawf_tlv; htt_stats_tx_pdev_ppdu_dur_tlv tx_ppdu_dur_tlv; - htt_stats_tx_pdev_txop_dur_tlv tx_txop_dur_tlv; } htt_tx_pdev_rate_stats_t; #endif /* ATH_TARGET */ @@ -7742,7 +5954,6 @@ typedef struct { #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ #define HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ #define HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */ -#define HTT_RX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS 4 /* 1.1, 3.1, 4.1, 7.1 */ #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 /* 0-13 */ #define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4 #define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5 @@ -7758,9 +5969,6 @@ typedef struct { #define HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS 16 #define HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS 16 /* 0-13, -2, -1 */ #define HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ -/* 802.11BN MCS: all 16 EHT MCS indices and 4 UHR iMCS */ -#define HTT_RX_PDEV_STATS_NUM_BN_MCS_COUNTERS 20 -#define HTT_RX_PDEV_STATS_NUM_BN_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ /* HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS: * RU size index 0: HTT_UL_OFDMA_V0_RU_SIZE_RU_26 @@ -7802,9 +6010,6 @@ typedef enum { HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, } HTT_RX_PDEV_STATS_BE_RU_SIZE; -#define HTT_RX_PDEV_STATS_NUM_BN_RU_SIZE_COUNTERS \ - HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS - #define HTT_RX_PDEV_RATE_STATS_MAC_ID_M 0x000000ff #define HTT_RX_PDEV_RATE_STATS_MAC_ID_S 0 @@ -7837,13 +6042,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 nsts; /** Number of rx ldpc packets */ @@ -7985,7 +6184,6 @@ typedef struct { /* Stats for MCS 12/13 */ A_UINT32 rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; - A_UINT32 rx_11bn_su_elr; /* * NOTE - this TLV is already large enough that it causes the HTT message * carrying it to be nearly at the message size limit that applies to @@ -7997,9 +6195,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_rate_stats_tlv htt_rx_pdev_rate_stats_tlv; -#define HTT_STATS_RX_PDEV_RATE_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - typedef struct { htt_tlv_hdr_t tlv_hdr; /** Tx PPDU duration histogram **/ @@ -8043,22 +6238,6 @@ typedef struct { } htt_rx_pdev_rate_stats_t; #endif /* ATH_TARGET */ -#define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_M 0x0000000f -#define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_S 0 - -#define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_GET(_var) \ - (((_var) & HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_M) >> \ - HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RX_PDEV_RATE_EXT_STATS_WIFI_VERSION_GET(_var) \ - HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_GET(_var) - -#define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION, _val); \ - ((_var) |= ((_val) << HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_S)); \ - } while (0) - typedef struct { htt_tlv_hdr_t tlv_hdr; /** units = dB above noise floor */ @@ -8088,29 +6267,6 @@ typedef struct { A_UINT32 reduced_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; A_UINT8 rssi_chain_ext_2[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS]; /* units = dB above noise floor */ A_INT8 rx_per_chain_rssi_ext_2_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS]; - /** - * BIT [ 3 : 0] :- wifi_version - * BIT [31 : 4] :- reserved - */ - union { - struct { - A_UINT32 - /* wifi_version: - * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value. - * Refer to HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_GET - * / _SET macros for accessing this bitfield. - */ - wifi_version: 4, - reserved: 28; - }; - A_UINT32 wifi_version__word; - }; - /** Number of rx 2xldpc packets */ - A_UINT32 rx_2xldpc; - A_UINT32 npca_rx_bw_ext[HTT_RX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - A_UINT32 npca_rx_su_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; - /* Stats for iMCS 1.1, 3.1, 4.1, 7.1 */ - A_UINT32 rx_mcs_ext_3[HTT_RX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS]; } htt_stats_rx_pdev_rate_ext_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_rate_ext_stats_tlv htt_rx_pdev_rate_ext_stats_tlv; @@ -8144,8 +6300,6 @@ typedef struct { #define HTT_RX_UL_MAX_UPLINK_RSSI_TRACK 5 -#define HTT_STATS_MAX_NUM_TCP_IMPLICIT_TRIG_INTR 12 - typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -8153,13 +6307,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 rx_11ax_ul_ofdma; @@ -8209,27 +6357,10 @@ typedef struct { * response to basic trigger. Typically a data response is expected. */ A_UINT32 ul_ofdma_basic_trigger_rx_qos_null_only; - - /* tcp_aware_implicit_trig_hist_ms: - * Each histogram bin represents a 3 ms range: - * tcp_aware_implicit_trig_hist_ms[0] -> 0-3 ms, - * tcp_aware_implicit_trig_hist_ms[1] -> 3-6 ms, - * etc. - */ - A_UINT32 tcp_aware_implicit_trig_hist_ms[HTT_STATS_MAX_NUM_TCP_IMPLICIT_TRIG_INTR]; - - A_UINT32 ulofdma_implicit_trig_tried; - A_UINT32 ulofdma_implicit_trig_qos_null; - - /* Txop duration history from 0 to 12 ms with interval of 1000us */ - A_UINT32 ul_ofdma_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS]; } htt_stats_rx_pdev_ul_trig_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_ul_trig_stats_tlv htt_rx_pdev_ul_trigger_stats_tlv; -#define HTT_STATS_RX_PDEV_UL_TRIG_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS * TLV_TAGS: * - HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG @@ -8250,13 +6381,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 rx_11be_ul_ofdma; @@ -8313,72 +6438,14 @@ typedef struct { A_UINT32 ul_mlo_proc_qdepth_params_count; A_UINT32 ul_mlo_proc_accepted_qdepth_params_count; A_UINT32 ul_mlo_proc_discarded_qdepth_params_count; - - A_UINT32 rx_11bn_ul_ofdma; - - A_UINT32 bn_ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_BN_MCS_COUNTERS]; - A_UINT32 bn_ul_ofdma_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_BN_MCS_COUNTERS]; - A_UINT32 bn_ul_ofdma_rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - A_UINT32 bn_ul_ofdma_rx_bw[HTT_RX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - A_UINT32 bn_ul_ofdma_rx_stbc; - A_UINT32 bn_ul_ofdma_rx_ldpc; - - /* - * These are arrays to hold the number of PPDUs that we received per RU. - * E.g. PPDUs (data or non data) received in RU26 will be incremented in - * array offset 0 and similarly RU52 will be incremented in array offset 1 - */ - /** PPDU level */ - A_UINT32 bn_rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BN_RU_SIZE_COUNTERS]; - /** PPDU level */ - A_UINT32 bn_rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BN_RU_SIZE_COUNTERS]; - - /** - * STA AID array for identifying which STA the - * Target-RSSI / FD-RSSI / pwr headroom stats are for - */ - A_UINT32 bn_uplink_sta_aid[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - /** - * Trig Target RSSI for STA AID in same index - UNIT(dBm) - */ - A_INT32 bn_uplink_sta_target_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - /** - * Trig FD RSSI from STA AID in same index - UNIT(dBm) - */ - A_INT32 bn_uplink_sta_fd_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - /** - * Trig power headroom for STA AID in same idx - UNIT(dB) - */ - A_UINT32 bn_uplink_sta_power_headroom[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - - /* - * Number of UHR UL OFDMA per-user responses containing only a QoS null in - * response to basic trigger. Typically a data response is expected. - */ - A_UINT32 bn_ul_ofdma_basic_trigger_rx_qos_null_only; - - /* UL OFDMA DRU spreading BW size */ - A_UINT32 bn_ul_ofdma_rx_dru_sbw[HTT_BN_UL_OFDMA_NUM_DRU_SBW_COUNT]; - /* UL OFDMA DRU size of data PPDU */ - A_UINT32 bn_rx_ulofdma_data_dru_size_ppdu[HTT_TX_PDEV_STATS_NUM_BN_DRU_SIZE_COUNTERS]; - - A_UINT32 be_ulofdma_implicit_trig_tried; - A_UINT32 be_ulofdma_implicit_trig_qos_null; - A_UINT32 bn_ulofdma_implicit_trig_tried; - A_UINT32 bn_ulofdma_implicit_trig_qos_null; -} htt_stats_rx_pdev_be_bn_ul_trig_tlv; -/* preserve old names as aliases */ -typedef htt_stats_rx_pdev_be_bn_ul_trig_tlv - htt_stats_rx_pdev_be_ul_trig_stats_tlv; -typedef htt_stats_rx_pdev_be_bn_ul_trig_tlv +} htt_stats_rx_pdev_be_ul_trig_stats_tlv; +/* preserve old name alias for new name consistent with the tag name */ +typedef htt_stats_rx_pdev_be_ul_trig_stats_tlv htt_rx_pdev_be_ul_trigger_stats_tlv; -#define HTT_STATS_RX_PDEV_BE_BN_UL_TRIG_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS * TLV_TAGS: - * - HTT_STATS_RX_PDEV_BE_BN_UL_TRIG_TAG + * - HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG * NOTE: * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. @@ -8427,22 +6494,6 @@ typedef struct { typedef htt_stats_rx_pdev_be_ul_ofdma_user_stats_tlv htt_rx_pdev_be_ul_ofdma_user_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - A_UINT32 user_index; - /** PPDU level */ - A_UINT32 bn_rx_ulofdma_non_data_ppdu; - /** PPDU level */ - A_UINT32 bn_rx_ulofdma_data_ppdu; - /** MPDU level */ - A_UINT32 bn_rx_ulofdma_mpdu_ok; - /** MPDU level */ - A_UINT32 bn_rx_ulofdma_mpdu_fail; - A_UINT32 bn_rx_ulofdma_non_data_nusers; - A_UINT32 bn_rx_ulofdma_data_nusers; -} htt_stats_rx_pdev_bn_ul_ofdma_user_tlv; - typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -8477,39 +6528,18 @@ typedef struct { typedef htt_stats_rx_pdev_be_ul_mimo_user_stats_tlv htt_rx_pdev_be_ul_mimo_user_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - A_UINT32 user_index; - /** PPDU level */ - A_UINT32 bn_rx_ulmumimo_non_data_ppdu; - /** PPDU level */ - A_UINT32 bn_rx_ulmumimo_data_ppdu; - /** MPDU level */ - A_UINT32 bn_rx_ulmumimo_mpdu_ok; - /** MPDU level */ - A_UINT32 bn_rx_ulmumimo_mpdu_fail; -} htt_stats_rx_pdev_bn_ul_mimo_user_tlv; - - /* == RX PDEV/SOC STATS == */ typedef struct { htt_tlv_hdr_t tlv_hdr; /** - * BIT [ 7 : 0] :- mac_id - * BIT [31 : 8] :- reserved + * BIT [7:0] :- mac_id + * BIT [31:8] :- reserved * * Refer to HTT_STATS_CMN_MAC_ID_GET/SET macros. */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Number of times UL MUMIMO RX packets received */ A_UINT32 rx_11ax_ul_mumimo; @@ -8554,32 +6584,21 @@ typedef struct { * response to basic trigger. Typically a data response is expected. */ A_UINT32 ul_mumimo_basic_trigger_rx_qos_null_only; - /* Txop duration history from 0 to 12 ms with interval of 1000us */ - A_UINT32 ul_mimo_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS]; } htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv htt_rx_pdev_ul_mumimo_trig_stats_tlv; -#define HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - typedef struct { htt_tlv_hdr_t tlv_hdr; /** - * BIT [ 7 : 0] :- mac_id - * BIT [31 : 8] :- reserved + * BIT [7:0] :- mac_id + * BIT [31:8] :- reserved * * Refer to HTT_STATS_CMN_MAC_ID_GET/SET macros. */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Number of times UL MUMIMO RX packets received */ A_UINT32 rx_11be_ul_mumimo; @@ -8626,81 +6645,15 @@ typedef struct { typedef htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv htt_rx_pdev_ul_mumimo_trig_be_stats_tlv; -#define HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - /** - * BIT [ 7 : 0] :- mac_id - * BIT [31 : 8] :- reserved - * - * Refer to HTT_STATS_CMN_MAC_ID_GET/SET macros. - */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; - - /** Number of times UL MUMIMO RX packets received */ - A_UINT32 rx_11bn_ul_mumimo; - - /** 11BN UHR UL MU-MIMO RX TB PPDU MCS stats */ - A_UINT32 bn_ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_BN_MCS_COUNTERS]; - /** - * 11BN UHR UL MU-MIMO RX GI & LTF stats. - * Index 0 indicates 1xLTF + 1.6 msec GI - * Index 1 indicates 2xLTF + 1.6 msec GI - * Index 2 indicates 4xLTF + 3.2 msec GI - */ - A_UINT32 bn_ul_mumimo_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_BN_MCS_COUNTERS]; - /** - * 11BN UHR UL MU-MIMO RX TB PPDU NSS stats - * (Increments the individual user NSS in the UL MU MIMO PPDU received) - */ - A_UINT32 bn_ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; - /** 11BN UHR UL MU-MIMO RX TB PPDU BW stats */ - A_UINT32 bn_ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - /** Number of times UL MUMIMO TB PPDUs received with STBC */ - A_UINT32 bn_ul_mumimo_rx_stbc; - /** Number of times UL MUMIMO TB PPDUs received with LDPC */ - A_UINT32 bn_ul_mumimo_rx_ldpc; - - /** RSSI in dBm for Rx TB PPDUs */ - A_INT8 bn_rx_ul_mumimo_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; - /** Target RSSI programmed in UL MUMIMO triggers (units dBm) */ - A_INT8 bn_rx_ul_mumimo_target_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; - /** FD RSSI measured for Rx UL TB PPDUs (units dBm) */ - A_INT8 bn_rx_ul_mumimo_fd_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; - /** Average pilot EVM measued for RX UL TB PPDU */ - A_INT8 bn_rx_ulmumimo_pilot_evm_dB_mean[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; - /** Number of times UL MUMIMO TB PPDUs received in a punctured mode */ - A_UINT32 bn_rx_ul_mumimo_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; - /* - * Number of UHR UL MU-MIMO per-user responses containing only a QoS null - * in response to basic trigger. Typically a data response is expected. - */ - A_UINT32 bn_ul_mumimo_basic_trigger_rx_qos_null_only; -} htt_stats_rx_pdev_ul_mumimo_trig_bn_tlv; - -#define HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BN_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS * TLV_TAGS: * - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG * - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG - * - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BN_TAG */ #ifdef ATH_TARGET typedef struct { htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv ul_mumimo_trig_tlv; htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv ul_mumimo_trig_be_tlv; - htt_stats_rx_pdev_ul_mumimo_trig_bn_tlv ul_mumimo_trig_bn_tlv; } htt_rx_pdev_ul_mumimo_trig_stats_t; #endif /* ATH_TARGET */ @@ -8884,9 +6837,7 @@ typedef struct { #define HTT_RX_PDEV_FW_STATS_MAC_ID_GET(_var) \ (((_var) & HTT_RX_PDEV_FW_STATS_MAC_ID_M) >> \ HTT_RX_PDEV_FW_STATS_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RX_PDEV_FW_STATS_MAC_ID_GET(_var) \ - HTT_RX_PDEV_FW_STATS_MAC_ID_GET(_var) + #define HTT_RX_PDEV_FW_STATS_MAC_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_RX_PDEV_FW_STATS_MAC_ID, _val); \ @@ -8900,13 +6851,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Num PPDU status processed from HW */ A_UINT32 ppdu_recvd; /** Num MPDU across PPDUs with FCS ok */ @@ -9011,7 +6956,6 @@ typedef struct { /* upper 32 bits of the rx_bytes value */ A_UINT32 high_32; } bytes_received; - A_UINT32 rx_msdu_cnt_ac[HTT_NUM_AC_WMM]; } htt_stats_rx_pdev_fw_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_fw_stats_tlv htt_rx_pdev_fw_stats_tlv; @@ -9038,13 +6982,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Num of phy err */ A_UINT32 total_phy_err_cnt; /** Counts of different types of phy errs @@ -9100,9 +7038,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_fw_stats_phy_err_tlv htt_rx_pdev_fw_stats_phy_err_tlv; -#define HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - #define HTT_RX_PDEV_FW_RING_MPDU_ERR_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) /* NOTE: Variable length TLV, use length spec to infer array size */ @@ -10175,36 +8110,6 @@ typedef enum { HTT_STATS_RU_TYPE_SINGLE_AND_MULTI_RU = 2, } htt_stats_ru_type; -typedef enum { - HTT_TX_PER_RATE_STATS_LOW_QUEUE_DEPTH = 0, - HTT_TX_PER_RATE_STATS_HIGH_QUEUE_DEPTH = 1, - - HTT_TX_PER_RATE_STATS_NUM_QUEUE_DEPTH_COUNTERS = 2 -} HTT_TX_PER_RATE_STATS_NUM_QUEUE_DEPTH_TYPE; - -typedef enum { - HTT_TX_PER_RATE_STATS_MLO_RA_DD_NO_MCS_DROP = 0, - HTT_TX_PER_RATE_STATS_MLO_RA_DD_ONE_OR_MORE_MCS_DROP = 1, - - HTT_TX_PER_RATE_STATS_NUM_MLO_RA_DD_MCS_DROP_COUNTERS = 2 -} HTT_TX_PER_RATE_STATS_NUM_MLO_RA_DD_MCS_DROP_TYPE; - -#define HTT_PER_RATE_STATS_WIFI_VERSION_M 0x0000000f -#define HTT_PER_RATE_STATS_WIFI_VERSION_S 0 - -#define HTT_PER_RATE_STATS_WIFI_VERSION_GET(_var) \ - (((_var) & HTT_PER_RATE_STATS_WIFI_VERSION_M) >> \ - HTT_PER_RATE_STATS_WIFI_VERSION_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PER_RATE_STATS_WIFI_VERSION_GET(_var) \ - HTT_PER_RATE_STATS_WIFI_VERSION_GET(_var) - -#define HTT_PER_RATE_STATS_WIFI_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PER_RATE_STATS_WIFI_VERSION, _val); \ - ((_var) |= ((_val) << HTT_PER_RATE_STATS_WIFI_VERSION_S)); \ - } while (0) - typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -10230,49 +8135,6 @@ typedef struct { A_UINT32 ru_type; /* refer to htt_stats_ru_type enum */ htt_tx_rate_stats_t per_ru[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; - - htt_tx_rate_stats_t per_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; - - /* mlo_ra_queue_depth_status: - * MLO SU Tx low/high queue depth PPDU counter, - * mlo_ra_queue_depth_status[0]: lowq depth - * mlo_ra_queue_depth_status[1]: high queue depth - */ - A_UINT32 mlo_ra_queue_depth_status[HTT_TX_PER_RATE_STATS_NUM_QUEUE_DEPTH_COUNTERS]; - /* mlo_rate_drop_down: - * MLO RA MCS drop counter, - * mlo_rate_drop_down[0]: No MCS drop - * mlo_rate_drop_down[1]: MCS drop counter - */ - A_UINT32 mlo_rate_drop_down[HTT_TX_PER_RATE_STATS_NUM_MLO_RA_DD_MCS_DROP_COUNTERS]; - - /** - * BIT [ 3 : 0] :- wifi_version - * BIT [31 : 4] :- reserved - */ - union { - struct { - A_UINT32 - /* wifi_version: - * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value. - * Refer to HTT_PER_RATE_STATS_WIFI_VERSION_GET - * / _SET macros for accessing this bitfield. - */ - wifi_version: 4, - reserved: 28; - }; - A_UINT32 wifi_version__word; - }; - - htt_tx_rate_stats_t npca_per_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - - htt_tx_rate_stats_t npca_per_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; - - /* PER stats for iMCS 1.1, 3.1, 4.1, 7.1 */ - htt_tx_rate_stats_t per_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS]; - - /* PER stats per DRU size */ - htt_tx_rate_stats_t per_dru[HTT_TX_PDEV_STATS_NUM_BN_DRU_SIZE_COUNTERS]; } htt_stats_per_rate_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_per_rate_stats_tlv htt_tx_rate_stats_per_tlv; @@ -11288,10 +9150,7 @@ typedef struct { A_UINT32 mu_grp_candidate_skip_1ss [HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS] [HTT_STATS_CANDIDATE_SKIP_REASON_MAX]; -} htt_stats_pdev_ul_mumimo_grp_stats_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_pdev_ul_mumimo_grp_stats_tlv - htt_stats_pdev_ulmumimo_grp_stats_tlv; +} htt_stats_pdev_ulmumimo_grp_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -11302,10 +9161,7 @@ typedef struct { A_UINT32 trig_bitmap_fail_cnt; /* Num of times peer denylisted due to trigger consecutive failure */ A_UINT32 trig_consecutive_fail_cnt; -} htt_stats_pdev_ul_mumimo_denylist_stats_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_pdev_ul_mumimo_denylist_stats_tlv - htt_stats_pdev_ulmumimo_denylist_stats_tlv; +} htt_stats_pdev_ulmumimo_denylist_stats_tlv; #define HTT_STATS_SEQ_EFFICIENCY_HISTOGRAM 10 typedef struct { @@ -11319,33 +9175,7 @@ typedef struct { A_UINT32 num_terminate_seq_inefficient; /* Histogram of sequence inefficiency */ A_UINT32 hist_seq_efficiency[HTT_STATS_SEQ_EFFICIENCY_HISTOGRAM]; - /* CTS2SELF sequences posted */ - A_UINT32 num_cts2self_ulmumimo_seq_posted; - /* Number of times ULMUMIMO classification is set to high */ - A_UINT32 num_ulmumimo_high_traffic; - /* Number of times ULMUMIMO classification is set to medium */ - A_UINT32 num_ulmumimo_medium_traffic; - /* Number of times ULMUMIMO classification is set to low */ - A_UINT32 num_ulmumimo_low_traffic; - /* - * Number of times ULMUMIMO sequence is terminated - * for high traffic classification - */ - A_UINT32 num_terminate_seq_high_traffic; - /* - * Number of times ULMUMIMO sequence is terminated - * for medium traffic classification - */ - A_UINT32 num_terminate_seq_medium_traffic; - /* - * Number of times ULMUMIMO sequence is terminated - * for low traffic classification - */ - A_UINT32 num_terminate_seq_low_traffic; -} htt_stats_pdev_ul_mumimo_seq_term_stats_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_pdev_ul_mumimo_seq_term_stats_tlv - htt_stats_pdev_ulmumimo_seq_term_stats_tlv; +} htt_stats_pdev_ulmumimo_seq_term_stats_tlv; #define HTT_STATS_MAX_ULMUMIMO_TRIGGERS 6 #define HTT_STATS_TXOP_HISTOGRAM_BINS 24 @@ -11373,10 +9203,7 @@ typedef struct { * Checks for 8 eligible instances of ULMUMIMO in the past 32 instances. */ A_UINT32 history_ineligibility; -} htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv - htt_stats_pdev_ulmumimo_hist_ineligibility_tlv; +} htt_stats_pdev_ulmumimo_hist_ineligibility_tlv; /* RTT VREG MASK */ @@ -11459,9 +9286,6 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv #define HTT_STATS_TPCCAL_POSTPROC_CHANNEL_GET(_var) \ (((_var) & HTT_STATS_TPCCAL_POSTPROC_CHANNEL_M) >> \ HTT_STATS_TPCCAL_POSTPROC_CHANNEL_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_CHANNEL_GET(_var) \ - HTT_STATS_TPCCAL_POSTPROC_CHANNEL_GET(_var) #define HTT_STATS_TPCCAL_POSTPROC_CHAIN_M 0x00ff0000 #define HTT_STATS_TPCCAL_POSTPROC_CHAIN_S 16 @@ -11469,9 +9293,6 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv #define HTT_STATS_TPCCAL_POSTPROC_CHAIN_GET(_var) \ (((_var) & HTT_STATS_TPCCAL_POSTPROC_CHAIN_M) >> \ HTT_STATS_TPCCAL_POSTPROC_CHAIN_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_CHAIN_GET(_var) \ - HTT_STATS_TPCCAL_POSTPROC_CHAIN_GET(_var) #define HTT_STATS_TPCCAL_POSTPROC_BAND_M 0xff000000 #define HTT_STATS_TPCCAL_POSTPROC_BAND_S 24 @@ -11479,9 +9300,6 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv #define HTT_STATS_TPCCAL_POSTPROC_BAND_GET(_var) \ (((_var) & HTT_STATS_TPCCAL_POSTPROC_BAND_M) >> \ HTT_STATS_TPCCAL_POSTPROC_BAND_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_BAND_GET(_var) \ - HTT_STATS_TPCCAL_POSTPROC_BAND_GET(_var) #define HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_M 0x000000ff #define HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_S 0 @@ -11489,9 +9307,6 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv #define HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_GET(_var) \ (((_var) & HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_M) >> \ HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_NUMGAIN_GET(_var) \ - HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_GET(_var) #define HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_M 0x0000ff00 #define HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_S 8 @@ -11499,9 +9314,6 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv #define HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_GET(_var) \ (((_var) & HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_M) >> \ HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_CALDBSTATUS_GET(_var) \ - HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_GET(_var) /* STATS_TYPE : HTT_DBG_EXT_PDEV_STATS_FTM_TPCCAL * TLV_TAGS: @@ -11509,8 +9321,6 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv */ #define HTT_MAX_TPCCAL_STATS 25 #define HTT_STATS_TPC_CAL_MAX_NUM_POINTS 64 -#define HTT_STATS_NUM_CAL_GAINS_SELECTED_4_GLUT 16 -#define HTT_STATS_NUM_CAL_GAINS_SELECTED_4_PLUT 10 typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -11643,225 +9453,8 @@ typedef struct { }; }; } tpccal_stats_postproc; - - /* cal DB timeout in ms */ - A_UINT32 calDbTimeoutMs; - - struct{ - /* tgtMeasPwr uses dBm units */ - A_INT32 tgtMeasPwr[HTT_STATS_NUM_CAL_GAINS_SELECTED_4_GLUT]; - A_UINT32 tgtPdadc[HTT_STATS_NUM_CAL_GAINS_SELECTED_4_PLUT]; - } tpcTargets; } htt_stats_pdev_ftm_tpccal_tlv; -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_PDADC_TPCCAL_PDADC_NUMGAIN_GET(word) \ - (((word) >> 0) & 0xff) - -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_PDADC_BAND_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_PDADC_CHANNEL_GET(word) \ - (((word) >> 8) & 0xffff) -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_PDADC_CHAIN_GET(word) \ - (((word) >> 24) & 0xff) - -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_TPCCALRESULT_GAINIDX_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_TPCCALRESULT_PDADC_GET(word) \ - (((word) >> 8) & 0xff) - -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_TPCCALRESULT_MEASPWR_GET(word) \ - (((word) >> 0) & 0xffff) - -#define HTT_STATS_TPCCAL_PDADC_LAST_IDX_M 0x000000ff -#define HTT_STATS_TPCCAL_PDADC_LAST_IDX_S 0 - -#define HTT_STATS_TPCCAL_PDADC_LAST_IDX_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_PDADC_LAST_IDX_M) >> \ - HTT_STATS_TPCCAL_PDADC_LAST_IDX_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_LAST_IDX_GET(_var) \ - HTT_STATS_TPCCAL_PDADC_LAST_IDX_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_PDADC_LAST_IDX_GET(_var) \ - HTT_STATS_TPCCAL_PDADC_LAST_IDX_GET(_var) - -#define HTT_STATS_TPCCAL_PDADC_NUMGAIN_M 0x000000ff -#define HTT_STATS_TPCCAL_PDADC_NUMGAIN_S 0 - -#define HTT_STATS_TPCCAL_PDADC_NUMGAIN_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_PDADC_NUMGAIN_M) >> \ - HTT_STATS_TPCCAL_PDADC_NUMGAIN_S) - -#define HTT_STATS_TPCCAL_PDADC_BAND_M 0x000000ff -#define HTT_STATS_TPCCAL_PDADC_BAND_S 0 - -#define HTT_STATS_TPCCAL_PDADC_BAND_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_PDADC_BAND_M) >> \ - HTT_STATS_TPCCAL_PDADC_BAND_S) - -#define HTT_STATS_TPCCAL_PDADC_CHANNEL_M 0x00ffff00 -#define HTT_STATS_TPCCAL_PDADC_CHANNEL_S 8 - -#define HTT_STATS_TPCCAL_PDADC_CHANNEL_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_PDADC_CHANNEL_M) >> \ - HTT_STATS_TPCCAL_PDADC_CHANNEL_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_CHANNEL_GET(_var) \ - HTT_STATS_TPCCAL_PDADC_CHANNEL_GET(_var) - -#define HTT_STATS_TPCCAL_PDADC_CHAIN_M 0xff000000 -#define HTT_STATS_TPCCAL_PDADC_CHAIN_S 24 - -#define HTT_STATS_TPCCAL_PDADC_CHAIN_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_PDADC_CHAIN_M) >> \ - HTT_STATS_TPCCAL_PDADC_CHAIN_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_CHAIN_GET(_var) \ - HTT_STATS_TPCCAL_PDADC_CHAIN_GET(_var) - -#define HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_M 0x000000ff -#define HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_S 0 - -#define HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_M) >> \ - HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_GAININDEX_GET(_var) \ - HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_GET(_var) - -#define HTT_STATS_TPCCAL_RES_PDADC_VAL_M 0x0000ff00 -#define HTT_STATS_TPCCAL_RES_PDADC_VAL_S 8 - -#define HTT_STATS_TPCCAL_RES_PDADC_VAL_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_RES_PDADC_VAL_M) >> \ - HTT_STATS_TPCCAL_RES_PDADC_VAL_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_PDADC_GET(_var) \ - HTT_STATS_TPCCAL_RES_PDADC_VAL_GET(_var) - -#define HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_M 0x0000ffff -#define HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_S 0 - -#define HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_M) >> \ - HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_MEASPWR_GET(_var) \ - HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_GET(_var) - - -#define HTT_STATS_TPC_CAL_PDADC_BUF_LEN 3 - -#define HTT_STATS_FTM_TPCCAL_CALDATA (1 << 0) -#define HTT_STATS_FTM_TPCCAL_CALINFO (1 << 1) -#define HTT_STATS_FTM_TPCCAL_CALERROR (1 << 2) - -#define HTT_STATS_FTM_TPCCAL_DONE_MASK (1 << 7) - -#define HTT_STATS_FTM_TPCCALRSP_MISCFLAGS_CALERROR_GLUTS_NOT_FILLED (1 << 16) -#define HTT_STATS_FTM_TPCCALRSP_MISCFLAGS_CALERROR_PLUT_NON_LINEAR (1 << 17) -#define HTT_STATS_FTM_TPCCALRSP_MISCFLAGS_CALERROR_ATTEMPTS_EXCEEDED (1 << 18) -#define HTT_STATS_FTM_TPCCALRSP_MISCFLAGS_CALERROR_PLUT_NOT_FILLED (1 << 19) - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - /* - * calStatus can be intrepreted with the below values: - * TPCCAL_CALDATA (1 << 0) - * TPCCAL_CALINFO (1 << 1) - * TPCCAL_CALERROR (1 << 2) - * bits 6:4 - reserved - * TPCCAL_DONE_MASK (1 << 7) - * bits 15:8 - reserved - * TPCCALRSP_MISCFLAGS_CALERROR_GLUTS_NOT_FILLED (1 << 16) - * TPCCALRSP_MISCFLAGS_CALERROR_PLUT_NON_LINEAR (1 << 17) - * TPCCALRSP_MISCFLAGS_CALERROR_ATTEMPTS_EXCEEDED (1 << 18) - * TPCCALRSP_MISCFLAGS_CALERROR_PLUT_NOT_FILLED (1 << 19) - * bits 31:20 - reserved - */ - A_UINT32 calStatus; - - /* dword__tpccal_pdadc_last_idx: - * Hold the last updated index for pdadc buffer which holds - * band,chain,chanIdx,gainIdx for pdadc non-linearity - * BIT [7 : 0] :- tpcccal_pdadc_last_idx - * BIT [31 : 8] :- rsvd - */ - union { - A_UINT32 dword__tpccal_pdadc_last_idx; - struct { - A_UINT32 tpccal_pdadc_last_idx:8, - rsvd:24; - }; - }; - - struct { - /* dword__tpccal_pdadc_numgain: - * Hold the number of gainIdx for band for which PDADC - * non-linearity is observed - * BIT [7 : 0] :- tpccal_pdadc_numgain - * BIT [31 : 8] :- rsvd1 - */ - union { - A_UINT32 dword__tpccal_pdadc_numgain; - struct { - A_UINT32 tpccal_pdadc_numgain:8, - rsvd1:24; - }; - }; - - /* - * dword__band_channel_chain: - * band, channel, chain for which pdadc is non-linear - * BIT [7 : 0] :- band - * BIT [23 : 8] :- channel - * BIT [31 : 24] :- chain - */ - union { - A_UINT32 dword__band_channel_chain; - struct { - A_UINT32 band:8, - channel:16, - chain:8; - }; - }; - } tpccal_stats_pdadc[HTT_STATS_TPC_CAL_PDADC_BUF_LEN]; - - struct { - /* dword__calres_gainIdx_pdadc: - * holds pdadc, gainindex from tpcCalResult for - * band, channel, chain, gainIdx for which pdadc is non-linear - * dword__calres_gainIdx_pdadc - * BIT [7 : 0] :- gainIdx - * BIT [15 : 8] :- pdadc - * BIT [31 : 16] :- rsvd2 - */ - union { - A_UINT32 dword__calres_gainIdx_pdadc; - struct { - A_UINT32 gainIdx:8, - pdadc:8, - rsvd2:16; - }; - }; - - /* - * dword__measPwr: - * BIT [15 : 0] :- measPwr - * BIT [31 : 16] :- rsvd3 - */ - union { - A_INT32 dword__measPwr; - struct { - A_INT32 measPwr:16, /* dBm units */ - rsvd3:16; - }; - }; - } tpccal_stats_tpcCalResult[HTT_STATS_TPC_CAL_PDADC_BUF_LEN][HTT_STATS_TPC_CAL_MAX_NUM_POINTS]; -} htt_stats_pdev_ftm_tpccal_ext_tlv; - - #define HTT_DLPAGER_STATS_MAX_HIST 10 #define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M 0x000000FF #define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S 0 @@ -12224,9 +9817,6 @@ typedef htt_stats_phy_counters_tlv htt_phy_counters_tlv; #define HTT_STATS_ANI_MODE_GET(_var) \ (((_var) & HTT_STATS_ANI_MODE_M) >> \ HTT_STATS_ANI_MODE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_STATS_ANI_MODE_GET(_var) \ - HTT_STATS_ANI_MODE_GET(_var) #define HTT_STATS_ANI_MODE_SET(_var, _val) \ do { \ @@ -12234,16 +9824,6 @@ typedef htt_stats_phy_counters_tlv htt_phy_counters_tlv; ((_var) |= ((_val) << HTT_STATS_ANI_MODE_S)); \ } while (0) -#define HTT_STATS_CURR_EANI_MODE_M 0x000000ff -#define HTT_STATS_CURR_EANI_MODE_S 0 - -#define HTT_STATS_CURR_EANI_MODE_GET(_var) \ - (((_var) & HTT_STATS_CURR_EANI_MODE_M) >> \ - HTT_STATS_CURR_EANI_MODE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_STATS_CUREANIMODE_GET(_var) \ - HTT_STATS_CURR_EANI_MODE_GET(_var) - typedef struct { htt_tlv_hdr_t tlv_hdr; /** per chain hw noise floor values in dBm */ @@ -12314,36 +9894,6 @@ typedef struct { reserved: 24; }; }; - - /* dl_max_ANI: - * Maximum ANI level that would be allowable for algorithm - * to choose the desense levels and its in dB units, - * higher values indicating more noise interference/more desense. - */ - A_INT32 dl_max_ANI; - - /* Minimum RSSI of connected clients - dBm units */ - A_INT32 ani_dl_max_for_rssi; - - /* - * BIT [ 7 : 0] :- curEANIMode - * BIT [31 : 8] :- rsvd - * - * curEANIMode: - * EANI_MODE_MIN_DESENSE = 0, - * EANI_MODE_MAX_DESENSE = 1, - * EANI_MODE_DEFAULT_DESENSE = 2, - * EANI_MODE_MAX, - * EANI_MODE_TYPE_INVALID = 0xFF - */ - union { - A_UINT32 dword_curEANIMode; - struct { - A_UINT32 - curEANIMode: 8, - rsvd: 24; - }; - }; } htt_stats_phy_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv; @@ -12354,223 +9904,160 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv; #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_M) >> \ HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_CALDATA_COMPRESSED_GET(_var) \ - HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_GET(_var) #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_CAL_DATA_COMPRESSED_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_M 0x00000006 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S 1 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_M) >> \ HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_CALDATASOURCE_GET(_var) \ - HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_GET(_var) #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_SOURCE, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_CAL_DATA_SOURCE_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_XTALCAL_M 0x00000008 #define HTT_STATS_PHY_RESET_XTALCAL_S 3 #define HTT_STATS_PHY_RESET_XTALCAL_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_XTALCAL_M) >> \ HTT_STATS_PHY_RESET_XTALCAL_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_XTALCAL_GET(_var) \ - HTT_STATS_PHY_RESET_XTALCAL_GET(_var) #define HTT_STATS_PHY_RESET_XTALCAL_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTALCAL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_XTALCAL_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_XTALCAL_S)); \ } while (0) - -#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_M 0x00000010 -#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_S 4 -#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_GET(_var) \ - (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GFPC_M) >> \ - HTT_STATS_PHY_RESET_TPCCAL2GFPC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_TPCCAL2GFPC_GET(_var) \ - HTT_STATS_PHY_RESET_TPCCAL2GFPC_GET(_var) -#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GFPC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL2GFPC_S)); \ - } while (0) - -#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_M 0x00000020 -#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_S 5 +#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_M 0x00000010 +#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_S 4 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GOPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL2GOPC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_TPCCAL2GOPC_GET(_var) \ - HTT_STATS_PHY_RESET_TPCCAL2GOPC_GET(_var) #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GOPC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL2GOPC_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL2GOPC_S)); \ } while (0) - -#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_M 0x00000040 -#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_S 6 -#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_GET(_var) \ - (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GFPC_M) >> \ - HTT_STATS_PHY_RESET_TPCCAL5GFPC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_TPCCAL5GFPC_GET(_var) \ - HTT_STATS_PHY_RESET_TPCCAL5GFPC_GET(_var) -#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_SET(_var, _val) \ +#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_M 0x00000020 +#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_S 5 +#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_GET(_var) \ + (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GFPC_M) >> \ + HTT_STATS_PHY_RESET_TPCCAL2GFPC_S) +#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GFPC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL5GFPC_S)); \ + HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GFPC, _val); \ + ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL2GFPC_S)); \ } while (0) - -#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_M 0x00000080 -#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_S 7 +#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_M 0x00000040 +#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_S 6 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GOPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL5GOPC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_TPCCAL5GOPC_GET(_var) \ - HTT_STATS_PHY_RESET_TPCCAL5GOPC_GET(_var) #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GOPC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL5GOPC_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL5GOPC_S)); \ } while (0) - -#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_M 0x00000100 -#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_S 8 -#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_GET(_var) \ - (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GFPC_M) >> \ - HTT_STATS_PHY_RESET_TPCCAL6GFPC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_TPCCAL6GFPC_GET(_var) \ - HTT_STATS_PHY_RESET_TPCCAL6GFPC_GET(_var) -#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_SET(_var, _val) \ +#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_M 0x00000080 +#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_S 7 +#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_GET(_var) \ + (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GFPC_M) >> \ + HTT_STATS_PHY_RESET_TPCCAL5GFPC_S) +#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GFPC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL6GFPC_S)); \ + HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GFPC, _val); \ + ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL5GFPC_S)); \ } while (0) - -#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_M 0x00000200 -#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_S 9 +#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_M 0x00000100 +#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_S 8 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GOPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL6GOPC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_TPCCAL6GOPC_GET(_var) \ - HTT_STATS_PHY_RESET_TPCCAL6GOPC_GET(_var) #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GOPC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL6GOPC_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL6GOPC_S)); \ + } while (0) +#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_M 0x00000200 +#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_S 9 +#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_GET(_var) \ + (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GFPC_M) >> \ + HTT_STATS_PHY_RESET_TPCCAL6GFPC_S) +#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GFPC, _val); \ + ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL6GFPC_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_RXGAINCAL2G_M 0x00000400 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_S 10 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL2G_M) >> \ HTT_STATS_PHY_RESET_RXGAINCAL2G_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_RXGAINCAL2G_GET(_var) \ - HTT_STATS_PHY_RESET_RXGAINCAL2G_GET(_var) #define HTT_STATS_PHY_RESET_RXGAINCAL2G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL2G, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_RXGAINCAL2G_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL2G_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_RXGAINCAL5G_M 0x00000800 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_S 11 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL5G_M) >> \ HTT_STATS_PHY_RESET_RXGAINCAL5G_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_RXGAINCAL5G_GET(_var) \ - HTT_STATS_PHY_RESET_RXGAINCAL5G_GET(_var) #define HTT_STATS_PHY_RESET_RXGAINCAL5G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL5G, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_RXGAINCAL5G_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL5G_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_RXGAINCAL6G_M 0x00001000 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_S 12 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL6G_M) >> \ HTT_STATS_PHY_RESET_RXGAINCAL6G_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_RXGAINCAL6G_GET(_var) \ - HTT_STATS_PHY_RESET_RXGAINCAL6G_GET(_var) #define HTT_STATS_PHY_RESET_RXGAINCAL6G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL6G, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_RXGAINCAL6G_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL6G_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_AOACAL2G_M 0x00002000 #define HTT_STATS_PHY_RESET_AOACAL2G_S 13 #define HTT_STATS_PHY_RESET_AOACAL2G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_AOACAL2G_M) >> \ HTT_STATS_PHY_RESET_AOACAL2G_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_AOACAL2G_GET(_var) \ - HTT_STATS_PHY_RESET_AOACAL2G_GET(_var) #define HTT_STATS_PHY_RESET_AOACAL2G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL2G, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_AOACAL2G_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL2G_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_AOACAL5G_M 0x00004000 #define HTT_STATS_PHY_RESET_AOACAL5G_S 14 #define HTT_STATS_PHY_RESET_AOACAL5G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_AOACAL5G_M) >> \ HTT_STATS_PHY_RESET_AOACAL5G_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_AOACAL5G_GET(_var) \ - HTT_STATS_PHY_RESET_AOACAL5G_GET(_var) #define HTT_STATS_PHY_RESET_AOACAL5G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL5G, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_AOACAL5G_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL5G_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_AOACAL6G_M 0x00008000 #define HTT_STATS_PHY_RESET_AOACAL6G_S 15 #define HTT_STATS_PHY_RESET_AOACAL6G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_AOACAL6G_M) >> \ HTT_STATS_PHY_RESET_AOACAL6G_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_AOACAL6G_GET(_var) \ - HTT_STATS_PHY_RESET_AOACAL6G_GET(_var) #define HTT_STATS_PHY_RESET_AOACAL6G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL6G, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_AOACAL6G_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL6G_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_M 0x00010000 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S 16 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_XTAL_FROM_OTP_M) >> \ HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_XTAL_FROM_OTP_GET(_var) \ - HTT_STATS_PHY_RESET_XTAL_FROM_OTP_GET(_var) #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTAL_FROM_OTP, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_XTAL_FROM_OTP_S)); \ } while (0) #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_M 0x000000FF @@ -12578,41 +10065,30 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv; #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_GLUT_LINEARITY_M) >> \ HTT_STATS_PHY_RESET_GLUT_LINEARITY_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_GLUT_LINEARITY_GET(_var) \ - HTT_STATS_PHY_RESET_GLUT_LINEARITY_GET(_var) #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_GLUT_LINEARITY, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_GLUT_LINEARITY_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_GLUT_LINEARITY_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_M 0x0000FF00 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_S 8 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_PLUT_LINEARITY_M) >> \ HTT_STATS_PHY_RESET_PLUT_LINEARITY_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_PLUT_LINEARITY_GET(_var) \ - HTT_STATS_PHY_RESET_PLUT_LINEARITY_GET(_var) #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_PLUT_LINEARITY, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_PLUT_LINEARITY_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_PLUT_LINEARITY_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_M 0x00FF0000 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_S 16 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_WLANDRIVERMODE_M) >> \ HTT_STATS_PHY_RESET_WLANDRIVERMODE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_WLANDRIVERMODE_GET(_var) \ - HTT_STATS_PHY_RESET_WLANDRIVERMODE_GET(_var) #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_WLANDRIVERMODE, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_WLANDRIVERMODE_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_WLANDRIVERMODE_S)); \ } while (0) @@ -12959,11 +10435,6 @@ typedef struct { * tx_power_neg[9]: cnt of PPDUs with tx pwr < -9 dBm */ A_UINT32 tx_power_neg[HTT_MAX_NEGATIVE_POWER_LEVEL]; - /* - * Tx Power computed for TPC IE for Beacon and related frames, - * in 0.25 dBm units - */ - A_UINT32 tpc_ie_power; } htt_stats_phy_tpc_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_phy_tpc_stats_tlv htt_phy_tpc_stats_tlv; @@ -12993,856 +10464,6 @@ typedef struct { } htt_vdevs_txrx_stats_t; #endif /* ATH_TARGET */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** The channel number on which these stats were collected */ - A_UINT32 chan_num; - /** num of records provided */ - A_UINT32 num_records; - /** Indicates the stats collection interval - * Valid Values: - * 100 - For the 100 ms interval stats histogram - * 1000 - For 1 sec interval histogram - */ - A_UINT32 collection_interval; - /** ani_hist_type: - * single flag to differentiate histogram type - * Valid Values: - * 0 - (default) For 1 sec interval histogram - * 1 - For granular (100 ms) interval histogram - * 2 - 1 sec histogram not enabled - * 3 - Granular histogram not enabled - */ - A_UINT32 ani_hist_type; -} htt_stats_pdev_ani_hist_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 rx_ofdma_timing_err_cnt; - A_UINT32 rx_cck_fail_cnt; - A_UINT32 rx_cck1_fail_cnt; - A_UINT32 rx_cck2_fail_cnt; - A_UINT32 rx_cck7_fail_cnt; - A_UINT32 mactx_abort_cnt; - A_UINT32 macrx_abort_cnt; - A_UINT32 phytx_abort_cnt; - A_UINT32 phyrx_abort_cnt; - A_UINT32 phyrx_defer_abort_cnt; - A_UINT32 rx_sizing1_event_cnt; /* a.k.a sizing1 */ - A_UINT32 rx_sizing2_event_cnt; /* a.k.a sizing2 */ -} htt_stats_ani_scalar_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* rx_pkt_cnt - - * Received EOP (end-of-packet) count per packet type; - * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; - * [5] = GF; [6] = EHT; [7] = WUR; [8] = AZ - */ - A_UINT32 rx_pkt_cnt[9]; -} htt_stats_ani_pkt_cnt_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* rx_pkt_crc_pass_cnt - - * CRC pass count per packet type; - * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; - * [5] = GF; [6] = EHT; [7] = WUR; [8] = AZ - */ - A_UINT32 rx_pkt_crc_pass_cnt[9]; -} htt_stats_ani_crc_pass_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* per_blk_err_cnt - - * Error count per error source; - * [0] = unknown; [1] = LSIG; [2] = HTSIG; [3] = VHTSIG; [4] = HESIG; - * [5] = RXTD_OTA; [6] = RXTD_FATAL; [7] = DEMF; [8] = ROBE; - * [9] = PMI; [10] = TXFD; [11] = TXTD; [12] = PHYRF - * [13-15]=RSVD - */ - A_UINT32 per_blk_err_cnt[16]; -} htt_stats_ani_per_blk_err_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* rx_ota_err_cnt - - * RXTD OTA (over-the-air) error count per error reason; - * [0] = voting fail; [1] = weak det fail; [2] = strong sig fail; - * [3] = cck fail; [4] = power surge; - * [5] = btcf timing timeout error; [6] = btcf packet detect error; - * [7] = coarse timing timeout error - * [8-9]=RSVD - */ - A_UINT32 rx_ota_err_cnt[10]; -} htt_stats_ani_ota_err_tlv; - - -/* PAPRD and power boost stats and counters */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - /** current pdev_id */ - A_UINT32 pdev_id; - /** DPD and PowerBoost trigger count */ - A_UINT32 total_dpd_cal_count; - A_UINT32 chan_change_dpd_cal_count; - A_UINT32 thermal_dpd_cal_count; - A_UINT32 recovery_dpd_cal_count; - A_UINT32 pb_cal_count; - /** DPD and PowerBoost Fail Count */ - A_UINT32 total_dpd_fail_count; - A_UINT32 chan_change_dpd_fail_count; - A_UINT32 thermal_dpd_fail_count; - A_UINT32 recovery_dpd_fail_count; - A_UINT32 pb_fail_count; - - /* - * DPD and Power Boost validity status - * - * BIT 0 - DPD_CAL_STATUS - * BIT 1 - PB_CAL_STATUS - * - * CAL_STATUS can be interpreted as below - * CAL_SUCCESS = 1 - * CAL_FAIL = 0 - */ - union { - A_UINT32 dpd_pb_validity_status; - struct { - A_UINT32 is_dpd_valid:1, - is_pb_valid:1, - rsvd:30; - }; - }; - - /** Last DPD cal time in ms */ - A_UINT32 last_dpd_cal_time; - - /** Last Power Boost cal time in ms */ - A_UINT32 last_pb_cal_time; - - /** Power Boost gain per BW and MCS, in 0.25 dB units - * For example, a value of 2 represents a 0.5 dB gain. - */ - A_UINT32 power_boost_gain[HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; -} htt_stats_phy_paprd_pb_tlv; - -#define HTT_STATS_PHY_PAPRD_PB_IS_DPD_VALID_GET(word) \ - (((word) >> 0) & 0x1) - -#define HTT_STATS_PHY_PAPRD_PB_IS_PB_VALID_GET(word) \ - (((word) >> 1) & 0x1) - -#define HTT_STATS_HDS_PROF_STATS_CIRCULAR_BUF_LEN 10 - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - struct { - union { - A_UINT32 channel_info; - struct { - A_UINT32 bandwidth_mhz:16, - band_center_freq1:16; /* MHz units */ - }; - }; - - union { - A_UINT32 channel_config; - struct { - A_UINT32 phyMode:8, /* phyMode - WLAN_PHY_MODE enum type */ - txChainmask:8, - rxChainmask:8, - swProfile:8; - }; - }; - - A_UINT32 channelSwitchTime; - A_UINT32 calModuleTime; - A_UINT32 iniModuleTime; - A_UINT32 tpcModuleTime; - A_UINT32 miscModuleTime; - A_UINT32 ctlModuleTime; - A_UINT32 reserved; - } channelChange_stats[HTT_STATS_HDS_PROF_STATS_CIRCULAR_BUF_LEN]; - - A_UINT32 idx; /* shows how many channel changes have occurred */ -} htt_stats_hds_prof_stats_tlv; - -#define HTT_STATS_HDS_PROF_BANDWIDTH_MHZ_GET(word) \ - ((word) & 0x0000ffff) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_BANDWIDTH_MHZ_GET(word) \ - HTT_STATS_HDS_PROF_BANDWIDTH_MHZ_GET(word) -#define HTT_STATS_HDS_PROF_BANDWIDTH_MHZ_SET(word, value) \ - ((word) |= ((value) & 0x0000ffff)) - -#define HTT_STATS_HDS_PROF_BAND_CENTER_FREQ1_GET(word) \ - (((word) & 0xffff0000) >> 16) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_BAND_CENTER_FREQ1_GET(word) \ - HTT_STATS_HDS_PROF_BAND_CENTER_FREQ1_GET(word) -#define HTT_STATS_HDS_PROF_BAND_CENTER_FREQ1_SET(word, value) \ - ((word) |= (((value) << 16) & 0xffff0000)) - -#define HTT_STATS_HDS_PROF_PHY_MODE_GET(word) \ - (((word) & 0x000000ff) >> 0) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_PHYMODE_GET(word) \ - HTT_STATS_HDS_PROF_PHY_MODE_GET(word) -#define HTT_STATS_HDS_PROF_PHY_MODE_SET(word, value) \ - ((word) |= (((value) << 0) & 0x000000ff)) - -#define HTT_STATS_HDS_PROF_TX_CHAINMASK_GET(word) \ - (((word) & 0x0000ff00) >> 8) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_TXCHAINMASK_GET(word) \ - HTT_STATS_HDS_PROF_TX_CHAINMASK_GET(word) -#define HTT_STATS_HDS_PROF_TX_CHAINMASK_SET(word, value) \ - ((word) |= (((value) << 8) & 0x0000ff00)) - -#define HTT_STATS_HDS_PROF_RX_CHAINMASK_GET(word) \ - (((word) & 0x00ff0000) >> 16) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_RXCHAINMASK_GET(word) \ - HTT_STATS_HDS_PROF_RX_CHAINMASK_GET(word) -#define HTT_STATS_HDS_PROF_RX_CHAINMASK_SET(word, value) \ - ((word) |= (((value) << 16) & 0x00ff0000)) - -#define HTT_STATS_HDS_PROF_SW_PROFILE_GET(word) \ - (((word) & 0xff000000) >> 24) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_SWPROFILE_GET(word) \ - HTT_STATS_HDS_PROF_SW_PROFILE_GET(word) -#define HTT_STATS_HDS_PROF_SW_PROFILE_SET(word, value) \ - ((word) |= (((value) << 24) & 0xff000000)) - - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - A_UINT32 flags; - struct { - /* - * bit 0: Dynamic ED CCA status flag - * bit 1: LPI status flag - * bit 2: Green Tx status flag - * bit 3: ANI status flag - * bit 4: Static ANI status flag - * bit 5: ANN Powerboost status flag - * bit 6: EANI status flag - * bit 7: Spur Mitigation status flag - * bit 8: Multigain RSSI status flag - */ - A_UINT32 - is_dyn_cca_enabled: 1, /* bit 0 */ - is_lpi_enabled: 1, /* bit 1 */ - is_gtx_enabled: 1, /* bit 2 */ - is_ani_enabled: 1, /* bit 3 */ - is_static_ani_enabled: 1, /* bit 4 */ - is_ann_pbt_enabled: 1, /* bit 5 */ - is_e_ani_enabled: 1, /* bit 6 */ - is_spur_mit_enabled: 1, /* bit 7 */ - is_multigain_rssi_enabled: 1, /* bit 8 */ - is_olpc_clpc: 1, /* bit 9 */ - is_abi_en_dis: 1, /* bit 10 */ - is_str_sig_rec: 1, /* bit 11 */ - is_verbose_enabled: 1, /* bit 12 */ - is_dyn_ant_sel_supported: 1, /* bit 13 */ - is_dfs_punc_enabled: 1, /* bit 14 */ - dpd_pow_bo_status: 1, /* bit 15 */ - is_eeprom_compressed: 1, /* bit 16 */ - reserved: 15; /* bits 31:17 */ - }; - }; - - union { - A_UINT32 rxsop_config; - struct { - A_UINT32 - is_rxsop_enabled: 1, /* bit 0 */ - rxsop_config_value: 8, /* bit 8:1 */ - rxsop_reserved: 23; /* bits 31:9 */ - }; - }; - - A_UINT32 abi_max_rg_gain; /* dB units */ - A_UINT32 abi_max_lg_gain; /* dB units */ - A_UINT32 abi_max_vlg_gain; /* dB units */ - /* abi_hold_mode: - * Controls how long gain table decisions are held: - * 0: Cleared each packet - * 1: Held for timer value - * 2: Gain table choices are under CSR control - */ - A_UINT32 abi_hold_mode; - A_UINT32 abi_hold_count; - A_INT32 rssi_temp_offset; /* dB units */ - A_INT32 rssi_xlna_bypass_offset; /* dB units */ - A_INT32 rssi_cbw_offset; /* dB units */ - A_INT32 rssi_chan_freq_offset; /* dB units */ - A_UINT32 otp_version; - A_UINT32 cfr_clip_factor[4]; - union { - A_UINT32 hc__premcs__pkt_type__word32; - struct { - A_UINT32 - hc_premcs: 16, /* bits 15:0 */ - hc_pkt_type: 16; /* bits 31:16 */ - }; - }; - union { - A_UINT32 hc_nss_thr__is_rx_gain_forced__rx_gain_forced_val__word32; - struct { - A_UINT32 - hc_nss_thr: 8, /* bits 7:0 */ - is_rx_gain_forced: 8, /* bits 15:8 */ - rx_gain_forced_val: 8, /* bits 23:16 */ - reserved2: 8; /* bits 31:24 */ - }; - }; -} htt_stats_optional_configs_tlv; - -#define HTT_STATS_OPT_CONF_GET_DYN_CCA(word) \ - (((word) & 0x1) >> 0) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_DYN_CCA_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_DYN_CCA(word) -#define HTT_STATS_OPT_CONF_SET_DYN_CCA(word, value) \ - ((word) = ((word) & ~0x1) | (((value) & 0x1) << 0)) - -#define HTT_STATS_OPT_CONF_GET_LPI(word) \ - (((word) & 0x2) >> 1) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_LPI_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_LPI(word) -#define HTT_STATS_OPT_CONF_SET_LPI(word, value) \ - ((word) = ((word) & ~0x2) | (((value) & 0x1) << 1)) - -#define HTT_STATS_OPT_CONF_GET_GTX(word) \ - (((word) & 0x4) >> 2) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_GTX_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_GTX(word) -#define HTT_STATS_OPT_CONF_SET_GTX(word, value) \ - ((word) = ((word) & ~0x4) | (((value) & 0x1) << 2)) - -#define HTT_STATS_OPT_CONF_GET_ANI(word) \ - (((word) & 0x8) >> 3) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_ANI_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_ANI(word) -#define HTT_STATS_OPT_CONF_SET_ANI(word, value) \ - ((word) = ((word) & ~0x8) | (((value) & 0x1) << 3)) - -#define HTT_STATS_OPT_CONF_GET_STATIC_ANI(word) \ - (((word) & 0x10) >> 4) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_STATIC_ANI_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_STATIC_ANI(word) -#define HTT_STATS_OPT_CONF_SET_STATIC_ANI(word, value) \ - ((word) = ((word) & ~0x10) | (((value) & 0x1) << 4)) - -#define HTT_STATS_OPT_CONF_GET_ANN_PBT(word) \ - (((word) & 0x20) >> 5) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_ANN_PBT_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_ANN_PBT(word) -#define HTT_STATS_OPT_CONF_SET_ANN_PBT(word, value) \ - ((word) = ((word) & ~0x20) | (((value) & 0x1) << 5)) - -#define HTT_STATS_OPT_CONF_GET_EANI(word) \ - (((word) & 0x40) >> 6) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_E_ANI_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_EANI(word) -#define HTT_STATS_OPT_CONF_SET_EANI(word, value) \ - ((word) = ((word) & ~0x40) | (((value) & 0x1) << 6)) - -#define HTT_STATS_OPT_CONF_GET_SPUR_MIT(word) \ - (((word) & 0x80) >> 7) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_SPUR_MIT_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_SPUR_MIT(word) -#define HTT_STATS_OPT_CONF_SET_SPUR_MIT(word, value) \ - ((word) = ((word) & ~0x80) | (((value) & 0x1) << 7)) - -#define HTT_STATS_OPT_CONF_GET_MULTIGAIN_RSSI(word) \ - (((word) & 0x100) >> 8) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_MULTIGAIN_RSSI_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_MULTIGAIN_RSSI(word) -#define HTT_STATS_OPT_CONF_SET_MULTIGAIN_RSSI(word, value) \ - ((word) = ((word) & ~0x100) | (((value) & 0x1) << 8)) - -#define HTT_STATS_OPT_CONF_GET_OLPC_CLPC(word) \ - (((word) & 0x200) >> 9) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_OLPC_CLPC_GET(word) \ - HTT_STATS_OPT_CONF_GET_OLPC_CLPC(word) -#define HTT_STATS_OPT_CONF_SET_OLPC_CLPC(word, value) \ - ((word) = ((word) & ~0x200) | (((value) & 0x1) << 9)) - -#define HTT_STATS_OPT_CONF_GET_ABI_EN_DIS(word) \ - (((word) & 0x400) >> 10) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_ABI_EN_DIS_GET(word) \ - HTT_STATS_OPT_CONF_GET_ABI_EN_DIS(word) -#define HTT_STATS_OPT_CONF_SET_ABI_EN_DIS(word, value) \ - ((word) = ((word) & ~0x400) | (((value) & 0x1) << 10)) - -#define HTT_STATS_OPT_CONF_GET_STR_SIG_REC(word) \ - (((word) & 0x800) >> 11) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_STR_SIG_REC_GET(word) \ - HTT_STATS_OPT_CONF_GET_STR_SIG_REC(word) -#define HTT_STATS_OPT_CONF_SET_STR_SIG_REC(word, value) \ - ((word) = ((word) & ~0x800) | (((value) & 0x1) << 11)) - -#define HTT_STATS_OPT_CONF_GET_VERBOSE(word) \ - (((word) & 0x1000) >> 12) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_VERBOSE_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_VERBOSE(word) -#define HTT_STATS_OPT_CONF_SET_VERBOSE(word, value) \ - ((word) = ((word) & ~0x1000) | (((value) & 0x1) << 12)) - -#define HTT_STATS_OPT_CONF_GET_DYN_ANT_SEL(word) \ - (((word) & 0x2000) >> 13) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_DYN_ANT_SEL_SUPPORTED_GET(word) \ - HTT_STATS_OPT_CONF_GET_DYN_ANT_SEL(word) -#define HTT_STATS_OPT_CONF_SET_DYN_ANT_SEL(word, value) \ - ((word) = ((word) & ~0x2000) | (((value) & 0x1) << 13)) - -#define HTT_STATS_OPT_CONF_GET_DFS_PUNC(word) \ - (((word) & 0x4000) >> 14) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_DFS_PUNC_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_DFS_PUNC(word) -#define HTT_STATS_OPT_CONF_SET_DFS_PUNC(word, value) \ - ((word) = ((word) & ~0x4000) | (((value) & 0x1) << 14)) - -#define HTT_STATS_OPT_CONF_GET_DPD_POW_BO(word) \ - (((word) & 0x8000) >> 15) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_DPD_POW_BO_STATUS_GET(word) \ - HTT_STATS_OPT_CONF_GET_DPD_POW_BO(word) -#define HTT_STATS_OPT_CONF_SET_DPD_POW_BO(word, value) \ - ((word) = ((word) & ~0x8000) | (((value) & 0x1) << 15)) - -#define HTT_STATS_OPT_CONF_GET_EEPROM_COMPRESSED(word) \ - (((word) & 0x10000) >> 16) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_EEPROM_COMPRESSED_GET(word) \ - HTT_STATS_OPT_CONF_GET_EEPROM_COMPRESSED(word) -#define HTT_STATS_OPT_CONF_SET_EEPROM_COMPRESSED(word, value) \ - ((word) = ((word) & ~0x10000) | (((value) & 0x1) << 16)) - - -#define HTT_STATS_OPT_CONF_GET_RXSOP_ENABLED(word) \ - (((word) & 0x1) >> 0) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_RXSOP_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_RXSOP_ENABLED(word) -#define HTT_STATS_OPT_CONF_SET_RXSOP_ENABLED(word, value) \ - ((word) = ((word) & ~0x1) | (((value) & 0x1) << 0)) - -#define HTT_STATS_OPT_CONF_GET_RXSOP_CONFIG_VALUE(word) \ - (((word) & 0x1FE) >> 1) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_RXSOP_CONFIG_VALUE_GET(word) \ - HTT_STATS_OPT_CONF_GET_RXSOP_CONFIG_VALUE(word) -#define HTT_STATS_OPT_CONF_SET_RXSOP_CONFIG_VALUE(word, value) \ - ((word) = ((word) & ~0x1FE) | (((value) & 0xFF) << 1)) - -#define HTT_STATS_OPT_CONF_GET_HC_PREMCS(word) \ - ((word) & 0xFFFF) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_HC_PREMCS_GET(word) \ - HTT_STATS_OPT_CONF_GET_HC_PREMCS(word) -#define HTT_STATS_OPT_CONF_SET_HC_PREMCS(word, value) \ - ((word) = ((value) & 0xFFFF)) - -#define HTT_STATS_OPT_CONF_GET_HC_PKT_TYPE(word) \ - (((word) & 0xFFFF0000) >> 16) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_HC_PKT_TYPE_GET(word) \ - HTT_STATS_OPT_CONF_GET_HC_PKT_TYPE(word) -#define HTT_STATS_OPT_CONF_SET_HC_PKT_TYPE(word, value) \ - ((word) = ((word) & ~0xFFFF0000) | (((value) & 0xFFFF) << 16)) - -#define HTT_STATS_OPT_CONF_GET_HC_NSS_THR(word) \ - (((word) & 0x000000FF) >> 0) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_HC_NSS_THR_GET(word) \ - HTT_STATS_OPT_CONF_GET_HC_NSS_THR(word) -#define HTT_STATS_OPT_CONF_SET_HC_NSS_THR(word, value) \ - ((word) = ((word) & ~0x000000FF) | (((value) & 0xFF) << 0)) - -#define HTT_STATS_OPT_CONF_GET_IS_RX_GAIN_FORCED(word) \ - (((word) & 0x0000FF00) >> 8) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_RX_GAIN_FORCED_GET(word) \ - HTT_STATS_OPT_CONF_GET_IS_RX_GAIN_FORCED(word) -#define HTT_STATS_OPT_CONF_SET_IS_RX_GAIN_FORCED(word, value) \ - ((word) = ((word) & ~0x0000FF00) | (((value) & 0xFF) << 8)) - -#define HTT_STATS_OPT_CONF_GET_RX_GAIN_FORCED_VAL(word) \ - (((word) & 0x00FF0000) >> 16) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_RX_GAIN_FORCED_VAL_GET(word) \ - HTT_STATS_OPT_CONF_GET_RX_GAIN_FORCED_VAL(word) -#define HTT_STATS_OPT_CONF_SET_RX_GAIN_FORCED_VAL(word, value) \ - ((word) = ((word) & ~0x00FF0000) | (((value) & 0xFF) << 16)) - - -/* FTM STATS */ -/* ================= dword_txparams ================= */ -#define HTT_STATS_XTAL_GAIN_IDX_M 0x000000FF -#define HTT_STATS_XTAL_GAIN_IDX_S 0 -#define HTT_STATS_GET_XTAL_GAIN_IDX(word) \ - (((word) & HTT_STATS_XTAL_GAIN_IDX_M) >> HTT_STATS_XTAL_GAIN_IDX_S) - -#define HTT_STATS_INFINITE_BURST_MODE_M 0x0000FF00 -#define HTT_STATS_INFINITE_BURST_MODE_S 8 -#define HTT_STATS_GET_INFINITE_BURST_MODE(word) \ - (((word) & HTT_STATS_INFINITE_BURST_MODE_M) >> HTT_STATS_INFINITE_BURST_MODE_S) - -#define HTT_STATS_FTM_MODE_M 0x00FF0000 -#define HTT_STATS_FTM_MODE_S 16 -#define HTT_STATS_GET_FTM_MODE(word) \ - (((word) & HTT_STATS_FTM_MODE_M) >> HTT_STATS_FTM_MODE_S) - -#define HTT_STATS_SIFS_US_M 0xFF000000 -#define HTT_STATS_SIFS_US_S 24 -#define HTT_STATS_GET_SIFS_US(word) \ - (((word) & HTT_STATS_SIFS_US_M) >> HTT_STATS_SIFS_US_S) - -/* ================= dword_txparams_ext_1 ================= */ -#define HTT_STATS_AGG_STATUS_M 0x00000001 -#define HTT_STATS_AGG_STATUS_S 0 -#define HTT_STATS_GET_AGG_STATUS(word) \ - (((word) & HTT_STATS_AGG_STATUS_M) >> HTT_STATS_AGG_STATUS_S) - -#define HTT_STATS_DPD_FLAG_M 0x00000002 -#define HTT_STATS_DPD_FLAG_S 1 -#define HTT_STATS_GET_DPD_FLAG(word) \ - (((word) & HTT_STATS_DPD_FLAG_M) >> HTT_STATS_DPD_FLAG_S) - -/* Bits [9:2] -> 8-bit field */ -#define HTT_STATS_PPDU_DUR_LAST_IDX_M 0x000003FC -#define HTT_STATS_PPDU_DUR_LAST_IDX_S 2 -#define HTT_STATS_GET_PPDU_DUR_LAST_IDX(word) \ - (((word) & HTT_STATS_PPDU_DUR_LAST_IDX_M) >> HTT_STATS_PPDU_DUR_LAST_IDX_S) - -/* ================= dword_txparams_ext_2 ================= */ -#define HTT_STATS_TARGET_TX_DUTY_M 0x000000FF -#define HTT_STATS_TARGET_TX_DUTY_S 0 -#define HTT_STATS_GET_TARGET_TX_DUTY(word) \ - (((word) & HTT_STATS_TARGET_TX_DUTY_M) >> HTT_STATS_TARGET_TX_DUTY_S) - -#define HTT_STATS_PPDU_TYPE_M 0x0000FF00 -#define HTT_STATS_PPDU_TYPE_S 8 -#define HTT_STATS_GET_PPDU_TYPE(word) \ - (((word) & HTT_STATS_PPDU_TYPE_M) >> HTT_STATS_PPDU_TYPE_S) - -#define HTT_STATS_NUM_USERS_OFDMA_M 0x00FF0000 -#define HTT_STATS_NUM_USERS_OFDMA_S 16 -#define HTT_STATS_GET_NUM_USERS_OFDMA(word) \ - (((word) & HTT_STATS_NUM_USERS_OFDMA_M) >> HTT_STATS_NUM_USERS_OFDMA_S) - -#define HTT_STATS_NUM_USERS_OFDMA_EHT_M 0xFF000000 -#define HTT_STATS_NUM_USERS_OFDMA_EHT_S 24 -#define HTT_STATS_GET_NUM_USERS_OFDMA_EHT(word) \ - (((word) & HTT_STATS_NUM_USERS_OFDMA_EHT_M) >> HTT_STATS_NUM_USERS_OFDMA_EHT_S) - -/* ================= dword_TimingStats ================= */ -#define HTT_STATS_TLV_TIMESTAMP_CNT_M 0x000000FF -#define HTT_STATS_TLV_TIMESTAMP_CNT_S 0 -#define HTT_STATS_GET_TLV_TIMESTAMP_CNT(word) \ - (((word) & HTT_STATS_TLV_TIMESTAMP_CNT_M) >> HTT_STATS_TLV_TIMESTAMP_CNT_S) - -/* ================= dword_TlvcmdInfo ================= */ -#define HTT_STATS_TLV_CMD_ENTRY_M 0x0000FFFF -#define HTT_STATS_TLV_CMD_ENTRY_S 0 -#define HTT_STATS_GET_TLV_CMD_ENTRY(word) \ - (((word) & HTT_STATS_TLV_CMD_ENTRY_M) >> HTT_STATS_TLV_CMD_ENTRY_S) - -#define HTT_STATS_TLV_CAL_TYPE_M 0x00FF0000 -#define HTT_STATS_TLV_CAL_TYPE_S 16 -#define HTT_STATS_GET_TLV_CAL_TYPE(word) \ - (((word) & HTT_STATS_TLV_CAL_TYPE_M) >> HTT_STATS_TLV_CAL_TYPE_S) - -/* ================= dword_TlvCmdParsing ================= */ -#define HTT_STATS_FLAG_TLV_CMD_PARSING_M 0x00000001 -#define HTT_STATS_FLAG_TLV_CMD_PARSING_S 0 -#define HTT_STATS_GET_FLAG_TLV_CMD_PARSING(word) \ - (((word) & HTT_STATS_FLAG_TLV_CMD_PARSING_M) >> HTT_STATS_FLAG_TLV_CMD_PARSING_S) - -#define HTT_STATS_NUM_TLV_CMD_DROPPED_M 0x000001FE -#define HTT_STATS_NUM_TLV_CMD_DROPPED_S 1 -#define HTT_STATS_GET_NUM_TLV_CMD_DROPPED(word) \ - (((word) & HTT_STATS_NUM_TLV_CMD_DROPPED_M) >> HTT_STATS_NUM_TLV_CMD_DROPPED_S) - -/* ================= dword_rxGaincalMaxNumchan ================= */ -#define HTT_STATS_RXGAINCAL_MAX_NUMCHAN_M 0x000000FF -#define HTT_STATS_RXGAINCAL_MAX_NUMCHAN_S 0 -#define HTT_STATS_GET_RXGAINCAL_MAX_NUMCHAN(word) \ - (((word) & HTT_STATS_RXGAINCAL_MAX_NUMCHAN_M) >> HTT_STATS_RXGAINCAL_MAX_NUMCHAN_S) - -/* ================= dword_rxgainCalRefISS ================= */ -#define HTT_STATS_RXGAINCAL_REF_ISS_M 0x000000FF -#define HTT_STATS_RXGAINCAL_REF_ISS_S 0 -#define HTT_STATS_GET_RXGAINCAL_REF_ISS(word) \ - (((word) & HTT_STATS_RXGAINCAL_REF_ISS_M) >> HTT_STATS_RXGAINCAL_REF_ISS_S) - - -#define HTT_STATS_FTM_TIMESTAMP_TOTAL_CNT 50 -#define HTT_STATS_FTM_PPDU_DUR_CIRCULAR_BUF_CNT 10 -#define HTT_STATS_FTM_RXGAINCAL_MAX_NUM_CHAN_TLV2 16 -#define HTT_STATS_FTM_FPC_TIMING_SHIFT 32ULL - - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - struct { - /* TX PARAMS - * - * BIT [7 : 0] :- gain idx used for xtal cal CW tone - * BIT [15 : 8] :- infinite_bursting_mode - * BIT [23 : 16] :- ftm_mode - * BIT [31 : 24] :- sifs_us - */ - union { - A_UINT32 dword_txparams; - struct { - A_UINT32 - xtalCal_gain_idx: 8, - infinite_bursting_mode: 8, - ftm_mode: 8, - sifs_us: 8; - }; - }; - - /* dword_txparams_ext_1 - * BIT [0] :- agg_status - * BIT [1] :- dpdFlag - * BIT [9 : 2] :- ppdu_dur_buf_last_idx (last idx of ppdu duration - * circular buffer - 'actual_ppdu_dur_us') - * BIT [31 : 10] :- rsvd - */ - union { - A_UINT32 dword_txparams_ext_1; - struct { - A_UINT32 - agg_status: 1, - dpdFlag: 1, - ppdu_dur_buf_last_idx: 8, - rsvd: 22; - }; - }; - - /* Circular buffer containing actual ppdu duration_us */ - A_UINT32 actual_ppdu_dur_us[HTT_STATS_FTM_PPDU_DUR_CIRCULAR_BUF_CNT]; - - A_UINT32 target_fes_duration_us; /* TX time */ - A_UINT32 target_txoff_duration_us; /* TX OFF duration */ - A_UINT32 phy_mode; /* PHY mode selected */ - A_UINT32 pkt_len_post_truncation; /* Packet length post truncation */ - - /* dword_txparams_ext_2 - * BIT [7 : 0] :- target_tx_duty (TX ON ratio) - * BIT [15 : 8] :- PpduType - * BIT [23 : 16] :- numUsers_ofdmaTonePlan - * BIT [31 : 24] :- numUsers_ofdmaTonePlanEHT - */ - union { - A_UINT32 dword_txparams_ext_2; - struct { - A_UINT32 - target_tx_duty: 8, - PpduType: 8, - numUsers_ofdmaTonePlan: 8, - numUsers_ofdmaTonePlanEHT: 8; - }; - }; - } tx_params; - - /* CALIBRATION VERIFICATION FW ONLY TIMING STATS (uS) */ - struct { - /* - * ts_FPC - 64 bits, - * ts_FPC_low - bits[31:0] of 64 bits - * ts_FPC_high - bits[63:32] of 64 bits - */ - A_UINT32 ts_FPC_low; - A_UINT32 ts_FPC_high; - - A_UINT32 ts_calDbRegenTime; /* calDb regeneration time for FPC */ - A_UINT32 ts_OPC; - A_UINT32 ts_xtalcal; - A_UINT32 ts_rxgaincal; - A_UINT32 ts_nfcal; - A_UINT32 ts_tx_ver; - A_UINT32 ts_rx_ver; - - /* Overall channel change time for tx/rx verification */ - A_UINT32 tx_ver_OverallChanChangeTiming_ts; - A_UINT32 rx_ver_OverallChanChangeTiming_ts; - - /* dword_TimingStats: - * Number of TLVs for which TlvCmdInfo to be dumped - * BIT [7:0] :- TlvTimeStampCntFilled - * BIT [31 :8] :- rsvd1 - */ - union { - A_UINT32 dword_TimingStats; - struct { - A_UINT32 - TlvTimeStampCntFilled: 8, - rsvd1: 24; - }; - }; - - /* TLV cmd and timing info */ - struct { - A_UINT32 TlvTimeStamp_delta; /* Time of TLV CMD entry in ts */ - - /* dword_TlvcmdInfo - * TLV CMD ID and calType corresponding to TLV - * BIT [15:0] :- TlvCmd_entry - TLV cmd ID - * BIT [23 : 16] :- TlvCalType - calType - * BIT [31 : 24] :- rsvd2 - */ - union { - A_UINT32 dword_TlvcmdInfo; - struct { - A_UINT32 - TlvCmd_entry: 16, - TlvCalType: 8, - rsvd2: 8; - }; - }; - } TlvCmdTimingInfo[HTT_STATS_FTM_TIMESTAMP_TOTAL_CNT]; - } timingStats; - - /* TLV params */ - struct { - /* Total number of TLV parameters for last TLV */ - A_UINT32 LastTlv_numParams; - - /* Number of TLV params parsed for last TLV */ - A_UINT32 LastTlv_numParamsParsed; - - A_UINT32 LastTlvCmd; /* Last TLV CMD being executed */ - A_UINT32 LastTlvRspCmd; /* Last TLV CMD for which RSP is sent */ - - /* dword_TlvCmdParsing - * BIT [0] :- flagTlvCmdParsing - Flag indicating entire TLV CMD - * being parsed/dropped - * BIT [8 : 1] :- numTlvCmdDropped - count of entire TLV CMDs dropped - * BIT [31 : 9] :- rsvd3 - */ - union { - A_UINT32 dword_TlvCmdParsing; - struct { - A_UINT32 - flagTlvCmdParsing: 1, - numTlvCmdDropped: 8, - rsvd3: 23; - }; - }; - - A_UINT32 LastTlvCmdDropped; /* Last TLV CMD dropped */ - } tlvParams; - - /* RX gain cal params */ - struct{ - /* dword_rxGaincalMaxNumchan - * Num channels for which goodPktCnt for RX gain cal to be dumped - * BIT [7 : 0] :- rxGaincalMaxNumchan - * BIT [31 : 8] :- rsvd4 - */ - union { - A_UINT32 dword_rxGaincalMaxNumchan; - struct { - A_UINT32 - rxGaincalMaxNumchan: 8, - rsvd4: 24; - }; - }; - - A_UINT32 goodPktCnt[HTT_STATS_FTM_RXGAINCAL_MAX_NUM_CHAN_TLV2]; - - /* dword_rxgainCalRefISS - * Reference Input Signal Strength for Rx gain cal in dBm - * BIT [7 : 0] :- RxGainCal_refISS - * BIT [31 : 8] :- rsvd - */ - union { - A_INT32 dword_rxgainCalRefISS; - struct { - A_INT32 - RxGainCal_refISS: 8, - rsvd5: 24; - }; - }; - } rxGainCalParams; - - /* Miscellaneous params */ - - A_UINT32 bdReadRsp; -} htt_stats_ftm_tlv; - -#define HTT_STATS_FTM_TX_PARAMS_XTALCAL_GAIN_IDX_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_FTM_TX_PARAMS_INFINITE_BURSTING_MODE_GET(word) \ - (((word) >> 8) & 0xff) -#define HTT_STATS_FTM_TX_PARAMS_FTM_MODE_GET(word) \ - (((word) >> 16) & 0xff) -#define HTT_STATS_FTM_TX_PARAMS_SIFS_US_GET(word) \ - (((word) >> 24) & 0xff) - -#define HTT_STATS_FTM_TX_PARAMS_AGG_STATUS_GET(word) \ - (((word) >> 0) & 0x1) -#define HTT_STATS_FTM_TX_PARAMS_DPDFLAG_GET(word) \ - (((word) >> 1) & 0x1) -#define HTT_STATS_FTM_TX_PARAMS_PPDU_DUR_BUF_LAST_IDX_GET(word) \ - (((word) >> 2) & 0xff) - -#define HTT_STATS_FTM_TX_PARAMS_TARGET_TX_DUTY_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_FTM_TX_PARAMS_PPDUTYPE_GET(word) \ - (((word) >> 8) & 0xff) -#define HTT_STATS_FTM_TX_PARAMS_NUMUSERS_OFDMATONEPLAN_GET(word) \ - (((word) >> 16) & 0xff) -#define HTT_STATS_FTM_TX_PARAMS_NUMUSERS_OFDMATONEPLANEHT_GET(word) \ - (((word) >> 24) & 0xff) - -#define HTT_STATS_FTM_TIMINGSTATS_TLVTIMESTAMPCNTFILLED_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_FTM_TIMINGSTATS_TLVCMDTIMINGINFO_TLVCMD_ENTRY_GET(word) \ - (((word) >> 0) & 0xffff) -#define HTT_STATS_FTM_TIMINGSTATS_TLVCMDTIMINGINFO_TLVCALTYPE_GET(word) \ - (((word) >> 16) & 0xff) - -#define HTT_STATS_FTM_TIMINGSTATS_TLVCMD_ENTRY_GET(word) \ - (((word) >> 0) & 0xffff) -#define HTT_STATS_FTM_TIMINGSTATS_TLVCALTYPE_GET(word) \ - (((word) >> 16) & 0xff) - -#define HTT_STATS_FTM_TLVPARAMS_FLAGTLVCMDPARSING_GET(word) \ - (((word) >> 0) & 0x1) -#define HTT_STATS_FTM_TLVPARAMS_NUMTLVCMDDROPPED_GET(word) \ - (((word) >> 1) & 0xff) - -#define HTT_STATS_FTM_RXGAINCALPARAMS_RXGAINCALMAXNUMCHAN_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_FTM_RXGAINCALPARAMS_RXGAINCAL_REFISS_GET(word) \ - (((word) >> 0) & 0xff) - typedef struct { union { A_UINT32 word32; @@ -14247,26 +10868,6 @@ typedef struct { #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M 0x0FFFF000 #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S 12 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_M 0x00000007 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_S 0 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_M 0x00000038 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_S 3 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_M 0x000001C0 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_S 6 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_M 0x00000E00 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_S 9 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_M 0x00007000 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_S 12 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_M 0x00038000 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_S 15 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_M 0x001C0000 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_S 18 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_M 0x00E00000 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_S 21 -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_M 0x07000000 -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_S 24 - - #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_GET(_var) \ (((_var) & HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M) >> \ HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S) @@ -14309,160 +10910,6 @@ typedef struct { ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S)); \ } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_S)); \ - } while (0) - typedef struct { htt_tlv_hdr_t tlv_hdr; union { @@ -14474,51 +10921,6 @@ typedef struct { }; A_UINT32 msg_dword_1; }; - union { - struct { - A_UINT32 tid0_tqm_link0_id : 3, - tid1_tqm_link0_id : 3, - tid2_tqm_link0_id : 3, - tid3_tqm_link0_id : 3, - tid4_tqm_link0_id : 3, - tid5_tqm_link0_id : 3, - tid6_tqm_link0_id : 3, - tid7_tqm_link0_id : 3, - mlo_mgmt_tid_tqm_link0_id : 3, - reserved_tqm_link0 : 5; - }; - A_UINT32 msg_dword_tqm_link0; - }; - union { - struct { - A_UINT32 tid0_tqm_link1_id : 3, - tid1_tqm_link1_id : 3, - tid2_tqm_link1_id : 3, - tid3_tqm_link1_id : 3, - tid4_tqm_link1_id : 3, - tid5_tqm_link1_id : 3, - tid6_tqm_link1_id : 3, - tid7_tqm_link1_id : 3, - mlo_mgmt_tid_tqm_link1_id : 3, - reserved_tqm_link1 : 5; - }; - A_UINT32 msg_dword_tqm_link1; - }; - union { - struct { - A_UINT32 tid0_tqm_link2_id : 3, - tid1_tqm_link2_id : 3, - tid2_tqm_link2_id : 3, - tid3_tqm_link2_id : 3, - tid4_tqm_link2_id : 3, - tid5_tqm_link2_id : 3, - tid6_tqm_link2_id : 3, - tid7_tqm_link2_id : 3, - mlo_mgmt_tid_tqm_link2_id : 3, - reserved_tqm_link2 : 5; - }; - A_UINT32 msg_dword_tqm_link2; - }; } htt_stats_ml_peer_ext_details_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; @@ -14545,16 +10947,11 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_ANCHOR_LINK_S 21 #define HTT_ML_LINK_INFO_INITIALIZED_M 0x00400000 #define HTT_ML_LINK_INFO_INITIALIZED_S 22 -#define HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_M 0x00800000 -#define HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_S 23 #define HTT_ML_LINK_INFO_SW_PEER_ID_M 0x0000ffff #define HTT_ML_LINK_INFO_SW_PEER_ID_S 0 #define HTT_ML_LINK_INFO_VDEV_ID_M 0x00ff0000 #define HTT_ML_LINK_INFO_VDEV_ID_S 16 -#define HTT_STATS_ML_LINK_INFO_PS_STATE_M 0x01000000 -#define HTT_STATS_ML_LINK_INFO_PS_STATE_S 24 - #define HTT_ML_LINK_INFO_VALID_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_VALID_M) >> \ @@ -14710,21 +11107,6 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; ((_var) |= ((_val) << HTT_ML_LINK_INFO_INITIALIZED_S)); \ } while (0) - -#define HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_GET(_var) \ - (((_var) & HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_M) >> \ - HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_ML_LINK_INFO_DETAILS_BRIDGE_PEER_GET(_var) \ - HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_GET(_var) -#define HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_LINK_INFO_BRIDGE_PEER, _val); \ - ((_var) &= ~(HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_S)); \ - } while (0) - - #define HTT_ML_LINK_INFO_SW_PEER_ID_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_SW_PEER_ID_M) >> \ HTT_ML_LINK_INFO_SW_PEER_ID_S) @@ -14753,20 +11135,6 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; ((_var) |= ((_val) << HTT_ML_LINK_INFO_VDEV_ID_S)); \ } while (0) -#define HTT_STATS_ML_LINK_INFO_PS_STATE_GET(_var) \ - (((_var) & HTT_STATS_ML_LINK_INFO_PS_STATE_M) >> \ - HTT_STATS_ML_LINK_INFO_PS_STATE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_ML_LINK_INFO_DETAILS_PS_GET(_var) \ - HTT_STATS_ML_LINK_INFO_PS_STATE_GET(_var) -#define HTT_STATS_ML_LINK_INFO_PS_STATE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_LINK_INFO_PS_STATE, _val); \ - ((_var) &= ~(HTT_STATS_ML_LINK_INFO_PS_STATE_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_LINK_INFO_PS_STATE_S)); \ - } while (0) - - typedef struct { htt_tlv_hdr_t tlv_hdr; union { @@ -14782,8 +11150,7 @@ typedef struct { master_link : 1, anchor_link : 1, initialized : 1, - bridge_peer : 1, - reserved : 8; + reserved : 9; }; A_UINT32 msg_dword_1; }; @@ -14792,8 +11159,7 @@ typedef struct { struct { A_UINT32 sw_peer_id : 16, vdev_id : 8, - ps : 1, - reserved1 : 7; + reserved1 : 8; }; A_UINT32 msg_dword_2; }; @@ -14831,8 +11197,6 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M 0x000000ff #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S 0 -#define HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_M 0x0000ff00 -#define HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_S 8 #define HTT_ML_PEER_DETAILS_NUM_LINKS_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_NUM_LINKS_M) >> \ @@ -15018,17 +11382,6 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S)); \ } while (0) -#define HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_M) >> \ - HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_S) -#define HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_S)); \ - } while (0) - - typedef struct { htt_tlv_hdr_t tlv_hdr; htt_mac_addr remote_mld_mac_addr; @@ -15061,19 +11414,8 @@ typedef struct { union { struct { - A_UINT32 participating_chips_bitmap : 8, - /* status_required: - * Bitmap of status-required flags for each chip. - * Bit 0 is always the chip with the primary link. - * The remaining bits are for the other chips, - * in increasing order of chip ID, wrapping around - * to cover the chips whose IDs are smaller than the - * primary link's chip. - * Thus, bit 1 is for the chip whose ID is next after - * the primary link's chip ID, etc. - */ - status_required : 8, - reserved1 : 16; + A_UINT32 participating_chips_bitmap : 8, + reserved1 : 24; }; A_UINT32 msg_dword_2; }; @@ -15364,16 +11706,6 @@ typedef struct { * only for UL BSR TX mode. */ A_UINT32 running_ul_scheduler_for_bsrp_cnt[HTT_NUM_AC_WMM]; - /** - * Number of instances where we populated TX mode and candidate lists - * only for DL, due to skipping UL voluntarily. - */ - A_UINT32 running_dl_scheduler_due_to_skip_ul[HTT_NUM_AC_WMM]; - /** - * Number of instances where we populated TX mode and candidate lists - * only for UL, due to skipping DL voluntarily. - */ - A_UINT32 running_ul_scheduler_due_to_skip_dl[HTT_NUM_AC_WMM]; } htt_stats_pdev_sched_algo_ofdma_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_pdev_sched_algo_ofdma_stats_tlv @@ -15389,13 +11721,7 @@ typedef struct { * read/write this bitfield. * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 basic_trigger_across_bss; A_UINT32 basic_trigger_within_bss; A_UINT32 bsr_trigger_across_bss; @@ -15408,8 +11734,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_pdev_mbssid_ctrl_frame_stats_tlv htt_pdev_mbssid_ctrl_frame_stats_tlv; -#define HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -15476,15 +11800,9 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv; #define HTT_BW_MGR_STATS_STATIC_PATTERN_M 0x00ffff00 #define HTT_BW_MGR_STATS_STATIC_PATTERN_S 8 -#define HTT_BW_MGR_STATS_WIFI_VERSION_M 0x0000000f -#define HTT_BW_MGR_STATS_WIFI_VERSION_S 0 - #define HTT_BW_MGR_STATS_MAC_ID_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_MAC_ID_M) >> \ HTT_BW_MGR_STATS_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_MAC_ID_GET(_var) \ - HTT_BW_MGR_STATS_MAC_ID_GET(_var) #define HTT_BW_MGR_STATS_MAC_ID_SET(_var, _val) \ do { \ @@ -15496,142 +11814,69 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv; #define HTT_BW_MGR_STATS_PRI20_IDX_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_PRI20_IDX_M) >> \ HTT_BW_MGR_STATS_PRI20_IDX_S) -#define HTT_BW_MGR_STATS_NPCA_PRI20_IDX_GET(_var) \ - HTT_BW_MGR_STATS_PRI20_IDX_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_PRI20_IDX_GET(_var) \ - HTT_BW_MGR_STATS_PRI20_IDX_GET(_var) #define HTT_BW_MGR_STATS_PRI20_IDX_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_PRI20_IDX, _val); \ ((_var) |= ((_val) << HTT_BW_MGR_STATS_PRI20_IDX_S)); \ } while (0) -#define HTT_BW_MGR_STATS_NPCA_PRI20_IDX_SET(_var, _val) \ - HTT_BW_MGR_STATS_PRI20_IDX_SET(_var, _val) #define HTT_BW_MGR_STATS_PRI20_FREQ_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_PRI20_FREQ_M) >> \ HTT_BW_MGR_STATS_PRI20_FREQ_S) -#define HTT_BW_MGR_STATS_NPCA_PRI20_FREQ_GET(_var) \ - HTT_BW_MGR_STATS_PRI20_FREQ_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_PRI20_FREQ_MHZ_GET(_var) \ - HTT_BW_MGR_STATS_PRI20_FREQ_GET(_var) #define HTT_BW_MGR_STATS_PRI20_FREQ_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_PRI20_FREQ, _val); \ ((_var) |= ((_val) << HTT_BW_MGR_STATS_PRI20_FREQ_S)); \ } while (0) -#define HTT_BW_MGR_STATS_NPCA_PRI20_FREQ_SET(_var, _val) \ - HTT_BW_MGR_STATS_PRI20_FREQ_SET(_var, _val) #define HTT_BW_MGR_STATS_CENTER_FREQ1_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_CENTER_FREQ1_M) >> \ HTT_BW_MGR_STATS_CENTER_FREQ1_S) -#define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ1_GET(_var) \ - HTT_BW_MGR_STATS_CENTER_FREQ1_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_CENTRE_FREQ1_GET(_var) \ - HTT_BW_MGR_STATS_CENTER_FREQ1_GET(_var) #define HTT_BW_MGR_STATS_CENTER_FREQ1_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CENTER_FREQ1, _val); \ ((_var) |= ((_val) << HTT_BW_MGR_STATS_CENTER_FREQ1_S)); \ } while (0) -#define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ1_SET(_var, _val) \ - HTT_BW_MGR_STATS_CENTER_FREQ1_SET(_var, _val) #define HTT_BW_MGR_STATS_CENTER_FREQ2_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_CENTER_FREQ2_M) >> \ HTT_BW_MGR_STATS_CENTER_FREQ2_S) -#define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ2_GET(_var) \ - HTT_BW_MGR_STATS_CENTER_FREQ2_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_CENTRE_FREQ2_GET(_var) \ - HTT_BW_MGR_STATS_CENTER_FREQ2_GET(_var) #define HTT_BW_MGR_STATS_CENTER_FREQ2_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CENTER_FREQ2, _val); \ ((_var) |= ((_val) << HTT_BW_MGR_STATS_CENTER_FREQ2_S)); \ } while (0) -#define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ2_SET(_var, _val) \ - HTT_BW_MGR_STATS_CENTER_FREQ2_SET(_var, _val) #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_CHAN_PHY_MODE_M) >> \ HTT_BW_MGR_STATS_CHAN_PHY_MODE_S) -#define HTT_BW_MGR_STATS_CHAN_NPCA_PHY_MODE_GET(_var) \ - HTT_BW_MGR_STATS_CHAN_PHY_MODE_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_PHY_MODE_GET(_var) \ - HTT_BW_MGR_STATS_CHAN_PHY_MODE_GET(_var) #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CHAN_PHY_MODE, _val); \ ((_var) |= ((_val) << HTT_BW_MGR_STATS_CHAN_PHY_MODE_S)); \ } while (0) -#define HTT_BW_MGR_STATS_CHAN_NPCA_PHY_MODE_SET(_var, _val) \ - HTT_BW_MGR_STATS_CHAN_PHY_MODE_SET(_var, _val) #define HTT_BW_MGR_STATS_STATIC_PATTERN_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_STATIC_PATTERN_M) >> \ HTT_BW_MGR_STATS_STATIC_PATTERN_S) -#define HTT_BW_MGR_STATS_NPCA_STATIC_PATTERN_GET(_var) \ - HTT_BW_MGR_STATS_STATIC_PATTERN_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_STATIC_PATTERN_GET(_var) \ - HTT_BW_MGR_STATS_STATIC_PATTERN_GET(_var) #define HTT_BW_MGR_STATS_STATIC_PATTERN_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_STATIC_PATTERN, _val); \ ((_var) |= ((_val) << HTT_BW_MGR_STATS_STATIC_PATTERN_S)); \ } while (0) -#define HTT_BW_MGR_STATS_NPCA_STATIC_PATTERN_SET(_var, _val) \ - HTT_BW_MGR_STATS_STATIC_PATTERN_SET(_var, _val) -#define HTT_BW_MGR_STATS_WIFI_VERSION_GET(_var) \ - (((_var) & HTT_BW_MGR_STATS_WIFI_VERSION_M) >> \ - HTT_BW_MGR_STATS_WIFI_VERSION_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_WIFI_VERSION_GET(_var) \ - HTT_BW_MGR_STATS_WIFI_VERSION_GET(_var) - -#define HTT_BW_MGR_STATS_WIFI_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_WIFI_VERSION, _val); \ - ((_var) |= ((_val) << HTT_BW_MGR_STATS_WIFI_VERSION_S)); \ - } while (0) - -#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_PRI20_IDX_GET(_var) \ - (((_var) >> 8) & 0xff) - -#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_PRI20_FREQ_MHZ_GET(_var) \ - (((_var) >> 16) & 0xffff) - -#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_CENTRE_FREQ1_GET(_var) \ - (((_var) >> 0) & 0xffff) - -#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_CENTRE_FREQ2_GET(_var) \ - (((_var) >> 16) & 0xffff) - -#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_PHY_MODE_GET(_var) \ - (((_var) >> 0) & 0xff) - -#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_STATIC_PATTERN_GET(_var) \ - (((_var) >> 8) & 0xffff) - typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -15639,76 +11884,17 @@ typedef struct { * BIT [ 15 : 8] :- pri20_index * BIT [ 31 : 16] :- pri20_freq in Mhz */ - union { - struct { - A_UINT32 mac_id : 8; - A_UINT32 pri20_idx : 8; - A_UINT32 pri20_freq_mhz : 16; - }; - A_UINT32 mac_id__pri20_idx__freq; - }; + A_UINT32 mac_id__pri20_idx__freq; /* BIT [ 15 : 0] :- centre_freq1 * BIT [ 31 : 16] :- centre_freq2 */ - union { - struct { - A_UINT32 centre_freq1 : 16; - A_UINT32 centre_freq2 : 16; - }; - A_UINT32 centre_freq1__freq2; - }; + A_UINT32 centre_freq1__freq2; /* BIT [ 7 : 0] :- channel_phy_mode * BIT [ 23 : 8] :- static_pattern */ - union { - struct { - A_UINT32 phy_mode : 8; - A_UINT32 static_pattern : 16; - A_UINT32 reserved : 8; - }; - A_UINT32 phy_mode__static_pattern; - }; - - /* - * BIT [ 3 : 0] :- wifi_version - * BIT [ 7 : 4] :- Reserved - * BIT [ 15 : 8] :- NPCA_pri20_index - * BIT [ 31 : 16] :- NPCA_pri20_freq in Mhz - */ - union { - struct { - A_UINT32 wifi_version : 4; - A_UINT32 reserved2 : 4; - A_UINT32 npca_pri20_idx : 8; - A_UINT32 npca_pri20_freq_mhz : 16; - }; - A_UINT32 npca__wifi_version__pri20_idx__freq; - }; - - /* BIT [ 15 : 0] :- NPCA_centre_freq1 - * BIT [ 31 : 16] :- NPCA_centre_freq2 - */ - union { - struct { - A_UINT32 npca_centre_freq1 : 16; - A_UINT32 npca_centre_freq2 : 16; - }; - A_UINT32 npca__centre_freq1__freq2; - }; - - /* BIT [ 7 : 0] :- NPCA_channel_phy_mode - * BIT [ 23 : 8] :- NPCA_pattern - */ - union { - struct { - A_UINT32 npca_phy_mode : 8; - A_UINT32 npca_static_pattern : 16; - A_UINT32 reserved3 : 8; - }; - A_UINT32 npca__phy_mode__static_pattern; - }; + A_UINT32 phy_mode__static_pattern; } htt_stats_pdev_bw_mgr_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_pdev_bw_mgr_stats_tlv htt_pdev_bw_mgr_stats_tlv; @@ -15857,61 +12043,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word) \ - (((word) >> 0) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_PMACS_HWMLOS_GET(word) \ - (((word) >> 1) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_GLOBAL_WSI_GET(word) \ - (((word) >> 2) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_PMACS_DMAC_GET(word) \ - (((word) >> 3) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_TCL_GET(word) \ - (((word) >> 4) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_TQM_GET(word) \ - (((word) >> 5) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_WBM_GET(word) \ - (((word) >> 6) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_REO_GET(word) \ - (((word) >> 7) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_HOST_GET(word) \ - (((word) >> 8) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_PREREQUISITES_GET(word) \ - (((word) >> 9) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_PRE_RING_RESET_GET(word) \ - (((word) >> 10) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_APPLY_SOFT_RESET_GET(word) \ - (((word) >> 11) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_POST_RING_RESET_GET(word) \ - (((word) >> 12) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_FW_TQM_CMDQS_GET(word) \ - (((word) >> 13) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_HOST_GET(word) \ - (((word) >> 14) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_UMAC_INTERRUPTS_GET(word) \ - (((word) >> 15) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_WBM_GET(word) \ - (((word) >> 16) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_REO_GET(word) \ - (((word) >> 17) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_TQM_GET(word) \ - (((word) >> 18) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_PMACS_DMAC_GET(word) \ - (((word) >> 19) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_TQM_SYNC_CMD_GET(word) \ - (((word) >> 20) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_GLOBAL_WSI_GET(word) \ - (((word) >> 21) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_PMACS_HWMLOS_GET(word) \ - (((word) >> 22) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word) \ - (((word) >> 23) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_TCL_GET(word) \ - (((word) >> 24) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_HOST_ENQ_GET(word) \ - (((word) >> 25) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word) \ - (((word) >> 26) & 0x1) - /* dword0 - b'0 - PRE_RESET_DISABLE_RXDMA_PREFETCH */ #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M 0x1 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S 0 @@ -16528,9 +12659,6 @@ typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv; #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_GET(_var) \ (((_var) & HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_M) >> \ HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_CODEL_MSDUQ_TX_FLOW_NUM_GET(_var) \ - HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_GET(_var) #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM, _val); \ @@ -16543,9 +12671,6 @@ typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv; #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_GET(_var) \ (((_var) & HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_M) >> \ HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_CODEL_MSDUQ_SVC_CLASS_ID_GET(_var) \ - HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_GET(_var) #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID, _val); \ @@ -16558,9 +12683,6 @@ typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv; #define HTT_CODEL_MSDUQ_STATS_DROPS_GET(_var) \ (((_var) & HTT_CODEL_MSDUQ_STATS_DROPS_M) >> \ HTT_CODEL_MSDUQ_STATS_DROPS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_CODEL_MSDUQ_CODEL_DROPS_GET(_var) \ - HTT_CODEL_MSDUQ_STATS_DROPS_GET(_var) #define HTT_CODEL_MSDUQ_STATS_DROPS_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_DROPS, _val); \ @@ -16573,9 +12695,6 @@ typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv; #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_GET(_var) \ (((_var) & HTT_CODEL_MSDUQ_STATS_NO_DROPS_M) >> \ HTT_CODEL_MSDUQ_STATS_NO_DROPS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_CODEL_MSDUQ_CODEL_NO_DROPS_GET(_var) \ - HTT_CODEL_MSDUQ_STATS_NO_DROPS_GET(_var) #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_NO_DROPS, _val); \ @@ -16740,2406 +12859,13 @@ static INLINE A_UINT8 *htt_ctrl_path_cal_type_id_to_name(A_UINT32 cal_type_id) /*===================== Start GTX stats ====================*/ #define HTT_NUM_MCS_PER_NSS 16 - -#define HTT_NUM_EXTRA_MCS_PER_NSS 4 /* Stores iMCS index 1.1, 3.1, 4.1, 7.1 */ - -#define HTT_STATS_GTX_WIFI_VERSION_M 0x0000000f -#define HTT_STATS_GTX_WIFI_VERSION_S 0 - -#define HTT_STATS_GTX_WIFI_VERSION_GET(_var) \ - (((_var) & HTT_STATS_GTX_WIFI_VERSION_M) >> \ - HTT_STATS_GTX_WIFI_VERSION_S) -#define HTT_STATS_GTX_WIFI_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_GTX_WIFI_VERSION, _val); \ - ((_var) |= ((_val) << HTT_STATS_GTX_WIFI_VERSION_S)); \ - } while (0) - typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 gtx_enabled; /* shows whether Green Tx feature is enabled */ - - /* shows current MCS's minimum TPC in 0.25dBm units */ - A_INT32 mcs_tpc_min[HTT_NUM_MCS_PER_NSS]; - - /* shows current MCS's maximum TPC in 0.25dBm units */ - A_INT32 mcs_tpc_max[HTT_NUM_MCS_PER_NSS]; - - /* - * shows current MCS's difference between maximum and minimum TPC - * in 0.25dB units - */ - A_UINT32 mcs_tpc_diff[HTT_NUM_MCS_PER_NSS]; - /** - * BIT [ 3 : 0] :- wifi_version - * BIT [31 : 4] :- reserved - */ - union { - struct { - A_UINT32 - /* wifi_version: - * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value. - * Refer to HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_GET - * / _SET macros for accessing this bitfield. - */ - wifi_version: 4, - reserved: 28; - }; - A_UINT32 wifi_version__word; - }; - - /* shows current MCS's minimum TPC in 0.25dBm units for iMCS cases */ - A_INT32 mcs_tpc_min_ext[HTT_NUM_EXTRA_MCS_PER_NSS]; - - /* shows current MCS's maximum TPC in 0.25dBm units for iMCS cases */ - A_INT32 mcs_tpc_max_ext[HTT_NUM_EXTRA_MCS_PER_NSS]; - - /* - * shows current MCS's difference between maximum and minimum TPC - * in 0.25dB units for iMCS cases - */ - A_UINT32 mcs_tpc_diff_ext[HTT_NUM_EXTRA_MCS_PER_NSS]; + A_INT32 mcs_tpc_min[HTT_NUM_MCS_PER_NSS]; /* shows current MCS's minimum TPC in 0.25dBm units */ + A_INT32 mcs_tpc_max[HTT_NUM_MCS_PER_NSS]; /* shows current MCS's maximum TPC in 0.25dBm units */ + A_UINT32 mcs_tpc_diff[HTT_NUM_MCS_PER_NSS]; /* shows current MCS's difference between maximum and minimum TPC in 0.25dB unit*/ } htt_stats_gtx_tlv; /*===================== End GTX stats ====================*/ - -#define HTT_TX_PDEV_SAM_STATS_MAX_CMD_STATUS_TYPE 16 - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 pdev_id; - /* - * Number of commands posted on the FW -> SAM Command Ring. The index has - * an internal firmware meaning (this stat is primarily provided for - * internal debug), but is related to the type of command that has been - * posted. - */ - A_UINT32 cmd_posted[HTT_TX_PDEV_SAM_STATS_MAX_CMD_STATUS_TYPE]; - /* - * Number of statuses reaped on the SAM -> FW Status Ring. The index has an - * internal firmware meaning (this stat is primarily provided for internal - * debug), but is related to the type of status that is being processed. - */ - A_UINT32 status_reaped[HTT_TX_PDEV_SAM_STATS_MAX_CMD_STATUS_TYPE]; - /* - * Incremented each time a first_summary_bitmap_change_seen TLV is - * processed on the SAM -> FW Status ring. - */ - A_UINT32 first_seen_tlv_reaped; - /* - * Number of MSDUQ Empty -> Not Empty transitions observed through SAM - * Queue Bitmaps. - */ - A_UINT32 msduq_to_not_empty_cnt; - /* - * Number of MSDUQ Not Empty -> Empty transitions observed through SAM - * Queue Bitmaps. - */ - A_UINT32 msduq_to_empty_cnt; - /* - * Number of MPDUQ Empty -> Not Empty transitions observed through SAM - * Queue Bitmaps. - */ - A_UINT32 mpduq_to_not_empty_cnt; - /* - * Number of MPDUQ Not Empty -> Empty transitions observed through SAM - * Queue Bitmaps. - */ - A_UINT32 mpduq_to_empty_cnt; -} htt_stats_pdev_sam_tlv; - - -#define HTT_STATS_RESET_HISTORY_MAX_ENTRIES 10 - -/** - * @brief TLV structure for wifistats 82 (reset history) - * - * This structure holds the last 10 reset history entries. - * The entries are copied from the firmware's internal circular buffer. - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * @brief An array of structures, each holding the details of a single - * reset event. The entries are ordered chronologically from - * oldest to newest. - */ - struct { - A_UINT32 timestamp_ms; - /* reset_flags is only for debugging, not for host interpretation */ - A_UINT32 reset_flags; - /* reset_cause is only for debugging, not for host interpretation */ - A_UINT32 reset_cause; - /* reset_reason is only for debugging, not for host interpretation */ - A_UINT32 reset_reason; - A_UINT32 phy_mode; - union { - A_UINT32 channel_freq; - struct { - A_UINT32 - mhz: 16, - band_center_freq1:16; - }; - }; - union { - A_UINT32 channel_info; - struct { - A_UINT32 - flags: 16, /* only for debug, not for host interpret */ - phy_id: 8, - swprofile: 8; /* only for debug, not for host interpret */ - }; - }; - union { - A_UINT32 home_channel_info; - struct { - A_UINT32 - is_home_chan: 1, - reserved: 31; - }; - }; - A_UINT32 reserved_dwords[2]; /* reserved for future use */ - } reset_history[HTT_STATS_RESET_HISTORY_MAX_ENTRIES]; - A_UINT32 idx; /** Current write index of the circular buffer */ - A_UINT32 count; /** Total number of resets captured (up to 10) */ -} htt_stats_reset_history_tlv; - -#define HTT_STATS_RESET_HISTORY_MHZ_GET(word) \ - ((word) & 0x0000ffff) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_MHZ_GET(word) \ - HTT_STATS_RESET_HISTORY_MHZ_GET(word) -#define HTT_STATS_RESET_HISTORY_MHZ_SET(word, value) \ - ((word) |= ((value) & 0x0000ffff)) - -#define HTT_STATS_RESET_HISTORY_BAND_CENTER_FREQ1_GET(word) \ - (((word) & 0xffff0000) >> 16) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_BAND_CENTER_FREQ1_GET(word) \ - HTT_STATS_RESET_HISTORY_BAND_CENTER_FREQ1_GET(word) -#define HTT_STATS_RESET_HISTORY_BAND_CENTER_FREQ1_SET(word, value) \ - ((word) |= (((value) << 16) & 0xffff0000)) - -#define HTT_STATS_RESET_HISTORY_FLAGS_GET(word) \ - ((word) & 0x0000ffff) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_FLAGS_GET(word) \ - HTT_STATS_RESET_HISTORY_FLAGS_GET(word) -#define HTT_STATS_RESET_HISTORY_FLAGS_SET(word, value) \ - ((word) |= ((value) & 0x0000ffff)) - -#define HTT_STATS_RESET_HISTORY_PHY_ID_GET(word) \ - (((word) & 0x00ff0000) >> 16) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_PHY_ID_GET(word) \ - HTT_STATS_RESET_HISTORY_PHY_ID_GET(word) -#define HTT_STATS_RESET_HISTORY_PHY_ID_SET(word, value) \ - ((word) |= (((value) << 16) & 0x00ff0000)) - -#define HTT_STATS_RESET_HISTORY_SWPROFILE_GET(word) \ - (((word) & 0xff000000) >> 24) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_SWPROFILE_GET(word) \ - HTT_STATS_RESET_HISTORY_SWPROFILE_GET(word) -#define HTT_STATS_RESET_HISTORY_SWPROFILE_SET(word, value) \ - ((word) |= (((value) << 24) & 0xff000000)) - -#define HTT_STATS_RESET_HISTORY_IS_HOME_CHAN_GET(word) \ - (((word) & 0x00000001) >> 0) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_IS_HOME_CHAN_GET(word) \ - HTT_STATS_RESET_HISTORY_IS_HOME_CHAN_GET(word) -#define HTT_STATS_RESET_HISTORY_IS_HOME_CHAN_SET(word, value) \ - ((word) |= (((value) << 0) & 0x00000001)) - - -/*===================== Start Regulatory stats ==================== { */ - -typedef enum { - HTT_STATS_REGULATORY_SUBTYPE_REGDB = 0, - HTT_STATS_REGULATORY_SUBTYPE_6GHZ = 1, - HTT_STATS_REGULATORY_SUBTYPE_CTL = 2, - HTT_STATS_REGULATORY_SUBTYPE_DFS = 3, - HTT_STATS_REGULATORY_SUBTYPE_MAX -} htt_stats_regulatory_subtype_t; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - struct { - A_UINT32 major_version : 8, - minor_version : 8, - custom_version: 8, - rsvd : 8; - }; - A_UINT32 regdb_version; - }; - A_UINT32 country_code; - A_UINT32 alpha_code; /* [7:0]->alpha[0], [15:8]->alpha[1] and so on */ - /* RegDomain and SuperDomain IDs are from Regdb */ - A_UINT32 reg_domain_pair_id; - A_UINT32 super_domain_id; - A_UINT32 phymode_bitmap; /* WMI_REGULATORY_PHYBITMAP */ - A_UINT32 chan_priority_freq; /* in MHz */ - A_UINT32 tpc_region; - A_UINT32 max_bw_2g; /* in MHz */ - A_UINT32 max_bw_5g; /* in MHz */ - A_UINT32 max_bw_6g; /* in MHz */ -} htt_stats_regdb_ctry_tlv; - -#define HTT_STATS_GET_FIELD(mask,shift,word) (((word) & (mask)) >> (shift)) -#define HTT_STATS_SET_FIELD(mask,shift,word,value) \ - (word) = (((word) & ~((mask))) | (((value) << (shift)) & (mask))) - -#define HTT_STATS_REGDB_CTRY_GET_MAJOR_VERSION(word) \ - HTT_STATS_GET_FIELD(0xFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_CTRY_MAJOR_VERSION_GET(word) \ - HTT_STATS_REGDB_CTRY_GET_MAJOR_VERSION(word) -#define HTT_STATS_REGDB_CTRY_SET_MAJOR_VERSION(word,value) \ - HTT_STATS_SET_FIELD(0xFF, 0, (word), (value)) - -#define HTT_STATS_REGDB_CTRY_GET_MINOR_VERSION(word) \ - HTT_STATS_GET_FIELD(0xFF00, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_CTRY_MINOR_VERSION_GET(word) \ - HTT_STATS_REGDB_CTRY_GET_MINOR_VERSION(word) -#define HTT_STATS_REGDB_CTRY_SET_MINOR_VERSION(word,value) \ - HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value)) - -#define HTT_STATS_REGDB_CTRY_GET_CUSTOM_VERSION(word) \ - HTT_STATS_GET_FIELD(0xFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_CTRY_CUSTOM_VERSION_GET(word) \ - HTT_STATS_REGDB_CTRY_GET_CUSTOM_VERSION(word) -#define HTT_STATS_REGDB_CTRY_SET_CUSTOM_VERSION(word,value) \ - HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value)) - -#define HTT_STATS_REGDB_CTRY_GET_ALPHA_CODE_CHAR(word, idx) \ - HTT_STATS_GET_FIELD((0xFF << (8*(idx))), (8*(idx)), (word)) -#define HTT_STATS_REGDB_CTRY_SET_ALPHA_CODE_CHAR(word, idx, value) \ - HTT_STATS_SET_FIELD((0xFF << (8*(idx))), (8*(idx)), (word), (value)) - -typedef struct { - union { - struct { - A_UINT32 start_freq : 16, /* in MHz */ - end_freq : 16; /* in MHz */ - }; - A_UINT32 freq_info; - }; - union { - struct { - A_UINT32 max_bw : 16, /* in MHz */ - reg_power : 8, /* in dBm */ - ant_gain : 8; /* in dB */ - }; - A_UINT32 bw_pwr_info; - }; - union { - struct { - A_UINT32 flags : 16, /* enum WMI_REGULATORY_FLAGS */ - ctl_region : 8, /* enum RegdbCtl */ - rsvd : 8; - }; - A_UINT32 flag_info; - }; - union { - struct { - A_UINT32 is_psd : 1, - rsvd1 : 15, - psd_power : 16; /* dBm / MHz */ - }; - A_UINT32 psd_power_info; - }; -} htt_stats_regdb_reg_rule_t; - -#define HTT_STATS_REGDB_REG_RULE_GET_START_FREQ(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_START_FREQ(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_END_FREQ(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_END_FREQ(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_MAX_BW(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_MAX_BW(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_REG_POWER(word) \ - HTT_STATS_GET_FIELD(0xFF0000, 16, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_REG_POWER(word, value) \ - HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_ANT_GAIN(word) \ - HTT_STATS_GET_FIELD(0xFF000000, 24, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_ANT_GAIN(word, value) \ - HTT_STATS_SET_FIELD(0xFF000000, 24, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_FLAGS(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_FLAGS(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_CTL_REGION(word) \ - HTT_STATS_GET_FIELD(0xFF0000, 16, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_CTL_REGION(word, value) \ - HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_IS_PSD(word) \ - HTT_STATS_GET_FIELD(0x1, 0, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_IS_PSD(word, value) \ - HTT_STATS_SET_FIELD(0x1, 0, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_PSD_POWER(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_PSD_POWER(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -typedef enum { - HTT_STATS_REGULATORY_REG_DMN_2G = 0, - HTT_STATS_REGULATORY_REG_DMN_5G = 1, - /* 2 is unused to allow octal grouping for 6G */ - HTT_STATS_REGULATORY_REG_DMN_6G_AP_LPI = 3, - HTT_STATS_REGULATORY_REG_DMN_6G_AP_SP = 4, - HTT_STATS_REGULATORY_REG_DMN_6G_AP_VLP = 5, - HTT_STATS_REGULATORY_REG_DMN_6G_CL1_LPI = 6, - HTT_STATS_REGULATORY_REG_DMN_6G_CL1_SP = 7, - HTT_STATS_REGULATORY_REG_DMN_6G_CL1_VLP = 8, - HTT_STATS_REGULATORY_REG_DMN_6G_CL2_LPI = 9, - HTT_STATS_REGULATORY_REG_DMN_6G_CL2_SP = 10, - HTT_STATS_REGULATORY_REG_DMN_6G_CL2_VLP = 11, -} htt_stats_regulatory_rd_type; - -#define HTT_STATS_REGULATORY_REG_DMN_6G_AP(power_mode) \ - (HTT_STATS_REGULATORY_REG_DMN_6G_AP_LPI + (power_mode)) -#define HTT_STATS_REGULATORY_REG_DMN_6G_CL(cl,power_mode) \ - (HTT_STATS_REGULATORY_REG_DMN_6G_CL1_LPI +(cl)*3 + (power_mode)) - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 rd_type; /* enum htt_stats_regulatory_rd_type */ - union { - struct { - A_UINT32 ctl_region : 8, /* enum RegdbCtl */ - cca_region : 8, /* enum CCA_REGION_MAP */ - dfs_region : 8, /* enum WMI_REG_DFS_REGION */ - domain_ctl_index : 8; - }; - A_UINT32 ctl_cca_dfs; - }; - A_UINT32 rd_code; /* from regdb.bin */ - /* - * Due to variable length array at end, this struture cannot be extended - * further. Hence use this reserved for any future parameters. - */ - A_UINT32 reserved; - union { - struct { - A_UINT32 num_rules : 16, /* number of elements in 'rules' array */ - rule_size : 16; /* size of single 'rule' in bytes */ - }; - A_UINT32 rule_num_and_size; - }; - htt_stats_regdb_reg_rule_t rules[1]; -} htt_stats_regdb_regdomain_tlv; - -#define HTT_STATS_REGDB_REGDOMAIN_GET_CTL_REGION(word) \ - HTT_STATS_GET_FIELD(0xFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_REGDOMAIN_CTL_REGION_GET(word) \ - HTT_STATS_REGDB_REGDOMAIN_GET_CTL_REGION(word) -#define HTT_STATS_REGDB_REGDOMAIN_SET_CTL_REGION(word,value) \ - HTT_STATS_SET_FIELD(0xFF, 0, (word), (value)) - -#define HTT_STATS_REGDB_REGDOMAIN_GET_CCA_REGION(word) \ - HTT_STATS_GET_FIELD(0xFF00, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_REGDOMAIN_CCA_REGION_GET(word) \ - HTT_STATS_REGDB_REGDOMAIN_GET_CCA_REGION(word) -#define HTT_STATS_REGDB_REGDOMAIN_SET_CCA_REGION(word,value) \ - HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value)) - -#define HTT_STATS_REGDB_REGDOMAIN_GET_DFS_REGION(word) \ - HTT_STATS_GET_FIELD(0xFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_REGDOMAIN_DFS_REGION_GET(word) \ - HTT_STATS_REGDB_REGDOMAIN_GET_DFS_REGION(word) -#define HTT_STATS_REGDB_REGDOMAIN_SET_DFS_REGION(word,value) \ - HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value)) - -#define HTT_STATS_REGDB_REGDOMAIN_GET_DOMAIN_CTL_INDEX(word) \ - HTT_STATS_GET_FIELD(0xFF000000, 24, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_REGDOMAIN_DOMAIN_CTL_INDEX_GET(word) \ - HTT_STATS_REGDB_REGDOMAIN_GET_DOMAIN_CTL_INDEX(word) -#define HTT_STATS_REGDB_REGDOMAIN_SET_DOMAIN_CTL_INDEX(word,value) \ - HTT_STATS_SET_FIELD(0xFF000000, 24, (word), (value)) - - -#define HTT_STATS_REGDB_REGDOMAIN_GET_NUM_RULES(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_REGDOMAIN_NUM_RULES_GET(word) \ - HTT_STATS_REGDB_REGDOMAIN_GET_NUM_RULES(word) -#define HTT_STATS_REGDB_REGDOMAIN_SET_NUM_RULES(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REGDB_REGDOMAIN_GET_RULE_SIZE(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_REGDOMAIN_RULE_SIZE_GET(word) \ - HTT_STATS_REGDB_REGDOMAIN_GET_RULE_SIZE(word) -#define HTT_STATS_REGDB_REGDOMAIN_SET_RULE_SIZE(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - struct { - A_UINT32 afc_local_rsvd : 8, /* bits 7:0 */ - /* enum WMI_AFC_FEATURE_6G_DEPLOYMENT_TYPE */ - deployment_type: 8, /* bits 15:8 */ - /* Bit 0 : LPI, Bit 1 : SP, Bit 2 : VLP, others: rsvd */ - power_mode_mask: 8, /* bits 23:16 */ - reserved: 8; - }; - A_UINT32 afc_ini_params; /* AFC_INI_CONFIG */ - }; - A_UINT32 tx_allowed_reason_code; - union { - struct { - A_UINT32 set_tpc_count : 16, - set_tpc_pass_count : 16; - }; - A_UINT32 set_tpc_counters; - }; - union { - struct { - A_UINT32 - /* enum WMI_6GHZ_REG_PWRMODE_TYPE */ - current_power_mode : 4, - /* enum WMI_6GHZ_REG_PWRMODE_TYPE */ - last_best_power_mode : 4, - is_current_mode_best_power_mode : 1, - rsvd1 : 7, - best_power_mode_count : 16; - }; - A_UINT32 power_mode_stats; - }; -} htt_stats_reg_6g_tlv; - -#define HTT_STATS_REG_6G_GET_AFC_LOCAL_RSVD(word) \ - HTT_STATS_GET_FIELD(0x000000FF, 0, (word)) -#define HTT_STATS_REG_6G_SET_AFC_LOCAL_RSVD(word,value) \ - HTT_STATS_SET_FIELD(0x000000FF, 0, (word), (value)) - -#define HTT_STATS_REG_6G_GET_DEPLOYMENT_TYPE(word) \ - HTT_STATS_GET_FIELD(0x0000FF00, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_DEPLOYMENT_TYPE_GET(word) \ - HTT_STATS_REG_6G_GET_DEPLOYMENT_TYPE(word) -#define HTT_STATS_REG_6G_SET_DEPLOYMENT_TYPE(word,value) \ - HTT_STATS_SET_FIELD(0x0000FF00, 8, (word), (value)) - -#define HTT_STATS_REG_6G_GET_POWER_MODE_MASK(word) \ - HTT_STATS_GET_FIELD(0x00FF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_POWER_MODE_MASK_GET(word) \ - HTT_STATS_REG_6G_GET_POWER_MODE_MASK(word) -#define HTT_STATS_REG_6G_SET_POWER_MODE_MASK(word,value) \ - HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value)) - -#define HTT_STATS_REG_6G_GET_SET_TPC_COUNT(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_SET_TPC_COUNT_GET(word) \ - HTT_STATS_REG_6G_GET_SET_TPC_COUNT(word) -#define HTT_STATS_REG_6G_SET_SET_TPC_COUNT(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REG_6G_GET_SET_TPC_PASS_COUNT(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_SET_TPC_PASS_COUNT_GET(word) \ - HTT_STATS_REG_6G_GET_SET_TPC_PASS_COUNT(word) -#define HTT_STATS_REG_6G_SET_SET_TPC_PASS_COUNT(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -#define HTT_STATS_REG_6G_GET_CURRENT_POWER_MODE(word) \ - HTT_STATS_GET_FIELD(0xF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CURRENT_POWER_MODE_GET(word) \ - HTT_STATS_REG_6G_GET_CURRENT_POWER_MODE(word) -#define HTT_STATS_REG_6G_SET_CURRENT_POWER_MODE(word,value) \ - HTT_STATS_SET_FIELD(0xF, 0, (word), (value)) - -#define HTT_STATS_REG_6G_GET_LAST_BEST_POWER_MODE(word) \ - HTT_STATS_GET_FIELD(0xF0, 4, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_LAST_BEST_POWER_MODE_GET(word) \ - HTT_STATS_REG_6G_GET_LAST_BEST_POWER_MODE(word) -#define HTT_STATS_REG_6G_SET_LAST_BEST_POWER_MODE(word,value) \ - HTT_STATS_SET_FIELD(0xF0, 4, (word), (value)) - -#define HTT_STATS_REG_6G_GET_IS_CURRENT_POWER_MODE_BEST(word) \ - HTT_STATS_GET_FIELD(0x100, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_IS_CURRENT_MODE_BEST_POWER_MODE_GET(word) \ - HTT_STATS_REG_6G_GET_IS_CURRENT_POWER_MODE_BEST(word) -#define HTT_STATS_REG_6G_SET_IS_CURRENT_POWER_MODE_BEST(word,value) \ - HTT_STATS_SET_FIELD(0x100, 8, (word), (value)) - -#define HTT_STATS_REG_6G_GET_BEST_POWER_MODE_COUNT(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_BEST_POWER_MODE_COUNT_GET(word) \ - HTT_STATS_REG_6G_GET_BEST_POWER_MODE_COUNT(word) -#define HTT_STATS_REG_6G_SET_BEST_POWER_MODE_COUNT(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -#define HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS 16 - - -typedef struct { - union { - struct { - A_UINT32 freq : 16, /* in MHz */ - power : 16; /* in 0.25 dBm signed */ - }; - A_UINT32 freq_power_pair; - }; - /* - * NOTE: no new fields can be added to this struct - * due to backwards-compatibility constraints. - */ -} htt_stats_reg_freq_power_pair_t; - -#define HTT_STATS_REG_FREQ_POWER_PAIR_GET_FREQ_VALUE(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_TX_POWER_FREQ_PAIR_FREQ_GET(word) \ - HTT_STATS_REG_FREQ_POWER_PAIR_GET_FREQ_VALUE(word) -#define HTT_STATS_REG_6G_CH_PWR_INFO_PSD_POWER_FREQ_PAIR_FREQ_GET(word) \ - HTT_STATS_REG_FREQ_POWER_PAIR_GET_FREQ_VALUE(word) -#define HTT_STATS_REG_6G_CH_PWR_INFO_EIRP_POWER_FREQ_PAIR_FREQ_GET(word) \ - HTT_STATS_REG_FREQ_POWER_PAIR_GET_FREQ_VALUE(word) -#define HTT_STATS_REG_FREQ_POWER_PAIR_SET_FREQ_VALUE(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REG_FREQ_POWER_PAIR_GET_POWER_VALUE(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_TX_POWER_FREQ_PAIR_POWER_GET(word) \ - HTT_STATS_REG_FREQ_POWER_PAIR_GET_POWER_VALUE(word) -#define HTT_STATS_REG_6G_CH_PWR_INFO_PSD_POWER_FREQ_PAIR_POWER_GET(word) \ - HTT_STATS_REG_FREQ_POWER_PAIR_GET_POWER_VALUE(word) -#define HTT_STATS_REG_6G_CH_PWR_INFO_EIRP_POWER_FREQ_PAIR_POWER_GET(word) \ - HTT_STATS_REG_FREQ_POWER_PAIR_GET_POWER_VALUE(word) -#define HTT_STATS_REG_FREQ_POWER_PAIR_SET_POWER_VALUE(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 index; - union { - A_UINT32 power_info_word; - struct { - A_UINT32 power_type_6ghz : 8, /* enum WMI_6GHZ_REG_PWRMODE_TYPE */ - eirp_power : 8, /* in dBm */ - is_psd_power : 1, - both_psd_eirp_support : 1, - rsvd :14; - }; - }; - union { - A_UINT32 num_levels_word; - struct { - A_UINT32 num_power_levels : 8, - num_psd_levels : 8, - num_eirp_levels : 8, - unused : 8; - }; - }; - A_UINT32 puncture_bitmap; - htt_stats_reg_freq_power_pair_t - tx_power_freq_pair[HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS]; - htt_stats_reg_freq_power_pair_t - psd_power_freq_pair[HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS]; - htt_stats_reg_freq_power_pair_t - eirp_power_freq_pair[HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS]; -} htt_stats_reg_6g_ch_pwr_info_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_reg_6g_ch_pwr_info_tlv - htt_stats_reg_6g_ch_power_info_tlv; - -#define HTT_STATS_REG_6G_GET_POWER_TYPE(word) \ - HTT_STATS_GET_FIELD(0xFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_POWER_TYPE_6GHZ_GET(word) \ - HTT_STATS_REG_6G_GET_POWER_TYPE(word) -#define HTT_STATS_REG_6G_SET_POWER_TYPE(word,value) \ - HTT_STATS_SET_FIELD(0xFF, 0, (word), (value)) - -#define HTT_STATS_REG_6G_GET_EIRP_POWER(word) \ - HTT_STATS_GET_FIELD(0xFF00, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_EIRP_POWER_GET(word) \ - HTT_STATS_REG_6G_GET_EIRP_POWER(word) -#define HTT_STATS_REG_6G_SET_EIRP_POWER(word,value) \ - HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value)) - -#define HTT_STATS_REG_6G_GET_IS_PSD(word) \ - HTT_STATS_GET_FIELD(0x10000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_IS_PSD_POWER_GET(word) \ - HTT_STATS_REG_6G_GET_IS_PSD(word) -#define HTT_STATS_REG_6G_SET_IS_PSD(word,value) \ - HTT_STATS_SET_FIELD(0x10000, 16, (word), (value)) - -#define HTT_STATS_REG_6G_GET_BOTH_PSD_EIRP_SUPPORT(word) \ - HTT_STATS_GET_FIELD(0x20000, 17, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_BOTH_PSD_EIRP_SUPPORT_GET(word) \ - HTT_STATS_REG_6G_GET_BOTH_PSD_EIRP_SUPPORT(word) -#define HTT_STATS_REG_6G_SET_BOTH_PSD_EIRP_SUPPORT(word,value) \ - HTT_STATS_SET_FIELD(0x20000, 17, (word), (value)) - -#define HTT_STATS_REG_6G_GET_NUM_POWER_LEVELS(word) \ - HTT_STATS_GET_FIELD(0xFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_NUM_POWER_LEVELS_GET(word) \ - HTT_STATS_REG_6G_GET_NUM_POWER_LEVELS(word) -#define HTT_STATS_REG_6G_SET_NUM_POWER_LEVELS(word,value) \ - HTT_STATS_SET_FIELD(0xFF, 0, (word), (value)) - -#define HTT_STATS_REG_6G_GET_NUM_PSD_LEVELS(word) \ - HTT_STATS_GET_FIELD(0xFF00, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_NUM_PSD_LEVELS_GET(word) \ - HTT_STATS_REG_6G_GET_NUM_PSD_LEVELS(word) -#define HTT_STATS_REG_6G_SET_NUM_PSD_LEVELS(word,value) \ - HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value)) - -#define HTT_STATS_REG_6G_GET_NUM_EIRP_LEVELS(word) \ - HTT_STATS_GET_FIELD(0xFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_NUM_EIRP_LEVELS_GET(word) \ - HTT_STATS_REG_6G_GET_NUM_EIRP_LEVELS(word) -#define HTT_STATS_REG_6G_SET_NUM_EIRP_LEVELS(word,value) \ - HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value)) - -#define HTT_STATS_REG_OOBE_MAX_BW 5 -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_INT32 oobe_psd[HTT_STATS_REG_OOBE_MAX_BW]; /* dBm / MHz */ - union { - struct { - A_INT32 oobe_limit_offset : 16, /* in MHz */ - oobe_limit_psd : 16; /* in dBr */ - }; - A_UINT32 offset_mask_pair; - } oobe_limit[HTT_STATS_REG_OOBE_MAX_BW]; -} htt_stats_reg_6g_oobe_tlv; - -#define HTT_STATS_REG_6G_GET_OOBE_LIMIT_OFFSET(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_OOBE_OOBE_LIMIT_OOBE_LIMIT_OFFSET_GET(word) \ - HTT_STATS_REG_6G_GET_OOBE_LIMIT_OFFSET(word) -#define HTT_STATS_REG_6G_SET_OOBE_LIMIT_OFFSET(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REG_6G_GET_OOBE_LIMIT_PSD(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_OOBE_OOBE_LIMIT_OOBE_LIMIT_PSD_GET(word) \ - HTT_STATS_REG_6G_GET_OOBE_LIMIT_PSD(word) -#define HTT_STATS_REG_6G_SET_OOBE_LIMIT_PSD(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_INT32 array_gain_cap[HTT_STATS_MAX_CHAINS * ((HTT_STATS_MAX_CHAINS/2)+1)]; - union { - struct { - A_UINT32 - /** To indicate Reg rule Index picked from Reg rules */ - regRuleIndex:16, - /** To indicate Power rule Index picked from Reg rules */ - powerRuleIndex:8, - reserved:8; - }; - A_UINT32 ctl_args; - }; -} htt_stats_ctl_tlv; - -#define HTT_STATS_CTL_GET_REG_RULE_INDEX(word) \ - HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_CTL_REGRULEINDEX_GET(word) \ - HTT_STATS_CTL_GET_REG_RULE_INDEX(word) -#define HTT_STATS_CTL_SET_REG_RULE_INDEX(word,value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value)) - -#define HTT_STATS_CTL_GET_POWER_RULE_INDEX(word) \ - HTT_STATS_GET_FIELD(0x00FF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_CTL_POWERRULEINDEX_GET(word) \ - HTT_STATS_CTL_GET_POWER_RULE_INDEX(word) -#define HTT_STATS_CTL_SET_POWER_RULE_INDEX(word,value) \ - HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value)) - - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - struct { - A_UINT32 - /** To indicate enablement of enhanced CTL */ - enhancedCtlEnable:1, - rsvd:7, - domainCtlIndex:8, /** Domain CTL Index */ - array_gain_cap_ctlRegion:8, /** Array gain CapCTLregion */ - exceptionCtlRegion:8; /** Exception CTL region */ - }; - A_UINT32 enhanced_ctl_args; - }; -} htt_stats_enhanced_ctl_tlv; - -#define HTT_STATS_ENHANCED_CTL_GET_ENHANCED_CTL_ENABLE(word) \ - HTT_STATS_GET_FIELD(0x00000001, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_ENHANCED_CTL_ENHANCEDCTLENABLE_GET(word) \ - HTT_STATS_ENHANCED_CTL_GET_ENHANCED_CTL_ENABLE(word) -#define HTT_STATS_ENHANCED_CTL_SET_ENHANCED_CTL_ENABLE(word,value) \ - HTT_STATS_SET_FIELD(0x00000001, 0, (word), (value)) - -#define HTT_STATS_ENHANCED_CTL_GET_DOMAIN_CTL_INDEX(word) \ - HTT_STATS_GET_FIELD(0x0000FF00, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_ENHANCED_CTL_DOMAINCTLINDEX_GET(word) \ - HTT_STATS_ENHANCED_CTL_GET_DOMAIN_CTL_INDEX(word) -#define HTT_STATS_ENHANCED_CTL_SET_DOMAIN_CTL_INDEX(word,value) \ - HTT_STATS_SET_FIELD(0x0000FF00, 8, (word), (value)) - -#define HTT_STATS_ENHANCED_CTL_GET_ARRAY_GAIN_CAP_CTL_REGION(word) \ - HTT_STATS_GET_FIELD(0x00FF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_ENHANCED_CTL_ARRAY_GAIN_CAP_CTLREGION_GET(word) \ - HTT_STATS_ENHANCED_CTL_GET_ARRAY_GAIN_CAP_CTL_REGION(word) -#define HTT_STATS_ENHANCED_CTL_SET_ARRAY_GAIN_CAP_CTL_REGION(word,value) \ - HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value)) - -#define HTT_STATS_ENHANCED_CTL_GET_EXCEPTION_CTL_REGION(word) \ - HTT_STATS_GET_FIELD(0xFF000000, 24, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_ENHANCED_CTL_EXCEPTIONCTLREGION_GET(word) \ - HTT_STATS_ENHANCED_CTL_GET_EXCEPTION_CTL_REGION(word) -#define HTT_STATS_ENHANCED_CTL_SET_EXCEPTION_CTL_REGION(word,value) \ - HTT_STATS_SET_FIELD(0xFF000000, 24, (word), (value)) - - -#define HTT_STATS_DFS_RADAR_HISTORY_MAX_ENTRIES 5 - -/** - * @brief TLV structure for wifistats 83 (radar history) - * This structure holds the last 5 radar history detected. - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - struct { - union { - A_UINT32 freq_det_info; - struct { - A_UINT32 chan_freq:16, /* MHz units */ - detector_id:8, - is_chirp:1, /* Chirp radar pulse detected */ - rsvd1:7; - }; - }; - union { - A_UINT32 rssi_pulse_info; - struct { - A_UINT32 rf_pulseid:16, - radar_rssi_dbm:8, - rsvd2:8; - }; - }; - union { - A_UINT32 domain_type_info; - struct { - A_UINT32 domain:8, - type:8, - rf_radar_type:8, - rsvd3:8; - }; - }; - union { - A_UINT32 sidx_freq_info; - struct { - A_UINT32 sidx:16, - freq_offset:16; - }; - }; - union { - A_UINT32 dur_info; - struct { - A_UINT32 rf_mindur:16, /* us */ - rf_maxdur:16; /* us */ - }; - }; - union { - A_UINT32 threshold_info; - struct { - A_UINT32 rf_threshold:16, /* units = dBm */ - rsvd4:16; - }; - }; - union { - A_UINT32 pri_info; - struct { - A_UINT32 rf_minpri:16, /* us */ - rf_maxpri:16; /* us */ - }; - }; - } radar_entry_stats[HTT_STATS_DFS_RADAR_HISTORY_MAX_ENTRIES]; - A_UINT32 idx; /* next write position */ - A_UINT32 count; /* valid entries in buffer */ -} htt_stats_dfs_radar_history_tlv; - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * freq_det_info (word 0) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_CHAN_FREQ_GET(word) \ - HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_CHAN_FREQ_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_DETECTOR_ID_GET(word) \ - HTT_STATS_GET_FIELD(0x00FF0000, 16, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_DETECTOR_ID_SET(word, value) \ - HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_IS_CHIRP_GET(word) \ - HTT_STATS_GET_FIELD(0x01000000, 24, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_IS_CHIRP_SET(word, value) \ - HTT_STATS_SET_FIELD(0x01000000, 24, (word), (value)) - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * rssi_pulse_info (word 1) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_PULSEID_GET(word) \ - HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_PULSEID_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RADAR_RSSI_DBM_GET(word) \ - ((A_INT8)HTT_STATS_GET_FIELD(0x00FF0000, 16, (word))) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RADAR_RSSI_DBM_SET(word, value) \ - HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (A_UINT8)(value)) - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * domain_type_info (word 2) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_DOMAIN_GET(word) \ - HTT_STATS_GET_FIELD(0x000000FF, 0, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_DOMAIN_SET(word, value) \ - HTT_STATS_SET_FIELD(0x000000FF, 0, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_TYPE_GET(word) \ - HTT_STATS_GET_FIELD(0x0000FF00, 8, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_TYPE_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FF00, 8, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_RADAR_TYPE_GET(word) \ - HTT_STATS_GET_FIELD(0x00FF0000, 16, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_RADAR_TYPE_SET(word, value) \ - HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value)) - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * sidx_freq_info (word 3) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_SIDX_GET(word) \ - ((A_INT16)HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word))) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_SIDX_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (A_UINT16)(value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_FREQ_OFFSET_GET(word) \ - ((A_INT16)HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_FREQ_OFFSET_SET(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (A_UINT16)(value)) - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * dur_info (word 4) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MINDUR_GET(word) \ - HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MINDUR_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MAXDUR_GET(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MAXDUR_SET(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * threshold_info (word 5) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_THRESHOLD_GET(word) \ - HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_THRESHOLD_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value)) - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * pri_info (word 6) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MINPRI_GET(word) \ - HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MINPRI_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MAXPRI_GET(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MAXPRI_SET(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -/* - * Sign-extend helper for signed bitfields in DFS radar entries. - * Used for radar_rssi_dbm (8-bit), sidx (16-bit), freq_offset (16-bit). - */ -#define HTT_STATS_SIGN_EXT(val, nbits) \ - (((val) & (1u << ((nbits)-1))) ? \ - ((val) | (~0u << (nbits))) : (val)) - -/* - * Indices into htt_stats_dfs_ini_tlv.reg_val[] - * (same order as wfax_dfs_common[]) - */ -enum htt_stats_dfs_ini_reg_idx { - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_POW_DET_L = 0, /* offset 0xBC0 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_DETECTION_U = 1, /* offset 0xBB4 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_PULSE_THR_L = 2, /* offset 0xBF8 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_POW_DET_U = 3, /* offset 0xBC4 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_PULSE_THR_U = 4, /* offset 0xBFC */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_SRCH_FFT_CTRL2_0_L = 5, /* offset 0xBD8 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_SRCH_FFT_CTRL1_U = 6, /* offset 0xBD4 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_SRCH_FFT_CTRL2_1_L = 7, /* offset 0xBE0 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_DETECTION_L = 8, /* offset 0xBB0 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_SRCH_FFT_CTRL2_1_U = 9, /* offset 0xBE4 */ - - HTT_STATS_DFS_INI_NUM_REGS = 10 -}; - - -/* - * htt_stats_dfs_ini_tlv - DFS common register - * - * Captures current live values of the 10 wfax_dfs_common HW registers. - * reg_val[i]: current value read from hardware - * - * Use enum htt_stats_dfs_ini_reg_idx for reg_val[] index interpretation. - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 reg_val[HTT_STATS_DFS_INI_NUM_REGS]; -} htt_stats_dfs_ini_tlv; - - -/* ======================= End DFS Channel Register Snapshot TLV ========== } */ - -/* ======================= DFS IPC Ring Stats TLV ========================= { - * Head/tail index state for the 3 DFS IPC rings read at stats query time. - * Use enum htt_stats_dfs_ipc_ring_idx for ipc_ring_stats[] index - * interpretation. - */ - -/* Indices into htt_stats_dfs_ipc_ring_tlv.ipc_ring_stats[] */ -enum htt_stats_dfs_ipc_ring_idx { - HTT_STATS_DFS_IPC_RING_DFS0 = 0, /* IPC_DFS0_RINGID (2) */ - HTT_STATS_DFS_IPC_RING_DFS1 = 1, /* IPC_DFS1_RINGID (3) */ - HTT_STATS_DFS_IPC_RING_DFS2 = 2, /* IPC_DFS2_RINGID (4) */ - - HTT_STATS_DFS_IPC_RING_COUNT = 3 /* DFS0, DFS1, DFS2 */ -}; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - struct { - A_UINT32 head_idx; - A_UINT32 shadow_head_idx; - A_UINT32 tail_idx; - A_UINT32 shadow_tail_idx; - } ipc_ring_stats[HTT_STATS_DFS_IPC_RING_COUNT]; -} htt_stats_dfs_ipc_ring_tlv; - - -/*======================= End Regulatory stats ==================== } */ - -/* - * Self response frame types. Aligning with - * WHAL_RESP_FRAMES (WHAL_MAX_RESP_FRAMES). - */ -typedef enum { - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_11L_MBPS = 0, - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_5_5L_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_2L_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_1L_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_11S_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_5_5S_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_2S_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_6_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_9_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_12_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_18_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_24_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_36_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_48_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_54_MBPS, - HTT_RESP_FRAME_TYPE_CBF_11AC, - HTT_RESP_FRAME_TYPE_CBF_11AX, - HTT_RESP_FRAME_TYPE_CBF_11BE, - HTT_RESP_FRAME_TYPE_CBF_11AX_EXT, - HTT_RESP_FRAME_TYPE_ACK_CTS_11AX_EXT_DCM, - HTT_RESP_FRAME_TYPE_RTT_11N_MCS0, - HTT_RESP_FRAME_TYPE_RTT_11N_MCS1, - HTT_RESP_FRAME_TYPE_RTT_11N_MCS3, - HTT_RESP_FRAME_TYPE_RTT_11AC_MCS0, - HTT_RESP_FRAME_TYPE_RTT_11AC_MCS1, - HTT_RESP_FRAME_TYPE_RTT_11AC_MCS3, - HTT_RESP_FRAME_TYPE_RTT_11A_6_MBPS, - HTT_RESP_FRAME_TYPE_RTT_11A_12_MBPS, - HTT_RESP_FRAME_TYPE_RTT_11A_24_MBPS, - HTT_RESP_FRAME_TYPE_RTT_11AX_MCS0, - HTT_RESP_FRAME_TYPE_RTT_11AX_MCS1, - HTT_RESP_FRAME_TYPE_RTT_11AX_MCS3, - HTT_RESP_FRAME_TYPE_AX_BE_EXT_DEF, - HTT_RESP_FRAME_TYPE_11BE_MCS14_MCS15, - HTT_RESP_FRAME_TYPE_MAX -} HTT_RESP_FRAME_TYPES; - -/* - * This structure stores the essential fields from WHAL_RESP_FRAME_PARAMS - * that are accessed in the WHAL SELFGEN RESP FRAME STATS. - */ -typedef struct { - union { - A_UINT32 type_rate_chainmask; - struct { - A_UINT32 - /* pkt_type: - * 0 = CCK, 1 = OFDM, 2 = HT, - * 3 = VHT, 4 = HE, 5 = EHT, - */ - pkt_type : 4, /* 0-3 */ - nss : 3, /* 4-6: Number of spatial streams */ - rate_mcs : 4, /* 7-10: Rate/MCS value */ - /* bandwith: - * 0 = 20 MHz, 1 = 40 MHz, 2 = 80 MHz, 3 = 160 MHz, 4 = 320 MHz - */ - bandwidth : 3, /* 11-13 */ - chain_mask : 8, /* 14-21: Primary chain mask */ - alt_chain_mask : 8, /* 22-29: Alternate chain mask */ - reserved : 2; /* 30-31: Reserved for future use */ - }; - }; - - union { - A_UINT32 tx_pwr_alt; - struct { - A_UINT32 - tx_pwr : 8, /* 0-7: Primary TX power (dBm) */ - tx_pwr_1 : 8, /* 8-15: Secondary TX power (dBm) */ - alt_tx_pwr : 8, /* 16-23: Alternate TX power (dBm) */ - alt_tx_pwr_1 : 8; /* 24-31: Alternate secondary TX pwr (dBm) */ - }; - }; -/* - * NOTE: due to backwards-compatibility constraints, - * this struct cannot be expanded. - */ -} HTT_STATS_WHAL_SELFGEN_RESP_FRAME_ENTRY; - -/* Mask and shift definitions for type_rate_chainmask fields */ -#define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_M 0x0000000F -#define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_S 0 -#define HTT_STATS_WHAL_SELFGEN_NSS_M 0x00000070 -#define HTT_STATS_WHAL_SELFGEN_NSS_S 4 -#define HTT_STATS_WHAL_SELFGEN_RATE_MCS_M 0x00000780 -#define HTT_STATS_WHAL_SELFGEN_RATE_MCS_S 7 -#define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_M 0x00003800 -#define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_S 11 -#define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_M 0x003FC000 -#define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_S 14 -#define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_M 0x3FC00000 -#define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_S 22 - -#define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_PKT_TYPE_M) >> \ - HTT_STATS_WHAL_SELFGEN_PKT_TYPE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_PKT_TYPE_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_PKT_TYPE_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_PKT_TYPE, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_PKT_TYPE_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_NSS_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_NSS_M) >> \ - HTT_STATS_WHAL_SELFGEN_NSS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_NSS_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_NSS_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_NSS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_NSS, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_NSS_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_RATE_MCS_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_RATE_MCS_M) >> \ - HTT_STATS_WHAL_SELFGEN_RATE_MCS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_RATE_MCS_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_RATE_MCS_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_RATE_MCS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_RATE_MCS, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_RATE_MCS_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_BANDWIDTH_M) >> \ - HTT_STATS_WHAL_SELFGEN_BANDWIDTH_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_BANDWIDTH_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_BANDWIDTH_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_BANDWIDTH, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_BANDWIDTH_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_M) >> \ - HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_CHAIN_MASK_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_CHAIN_MASK, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_M) >> \ - HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_ALT_CHAIN_MASK_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_S)); \ - } while (0) - -/* Mask and shift definitions for tx_pwr_alt fields */ -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_M 0x000000FF -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_S 0 -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_M 0x0000FF00 -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_S 8 -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_M 0x00FF0000 -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_S 16 -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_M 0xFF000000 -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_S 24 - -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_TX_PWR_M) >> \ - HTT_STATS_WHAL_SELFGEN_TX_PWR_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_TX_PWR_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_TX_PWR_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_TX_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_TX_PWR_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_TX_PWR_1_M) >> \ - HTT_STATS_WHAL_SELFGEN_TX_PWR_1_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_TX_PWR_1_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_TX_PWR_1_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_TX_PWR_1, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_TX_PWR_1_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_M) >> \ - HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_ALT_TX_PWR_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_M) >> \ - HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_ALT_TX_PWR_1_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_S)); \ - } while (0) - -/** - * HTT_STATS_WHAL_SELFGEN_CHANNEL_CONTEXT - Channel context information - * - * This structure stores common channel context information that is - * NOT per frame. - * It contains channel frequency, flags, and PHY mode information that applies - * to all self-generated response frames. - */ -typedef struct { - union { - A_UINT32 channel_info; - struct { - A_UINT32 - mhz : 16, /* 0-15: Channel frequency in MHz */ - /* flags: - * Channel flags, with a FW-internal definition of flag values. - * This fields is intended only for debugging, since the - * definitions of the flag values are not provided. - */ - flags : 16; /* 16-31 */ - }; - }; - A_UINT32 phy_mode; /* PHY mode (WLAN_PHY_MODE: 11a/11g/11ax/11be etc.) */ -/* - * NOTE: due to backwards-compatibility constraints, - * this struct cannot be expanded. - */ -} HTT_STATS_WHAL_SELFGEN_CHANNEL_CONTEXT; - -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_M 0x0000FFFF -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_S 0 -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_M 0xFFFF0000 -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_S 16 - -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_GET(_var) \ - (((_var).channel_context.channel_info & \ - HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_M) >> \ - HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_S) -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_CHANNEL_CONTEXT_MHZ_GET(word) \ - (((word) >> 0) & 0xffff) -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ, _val); \ - ((_var).channel_context.channel_info |= \ - ((_val) << HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_GET(_var) \ - (((_var).channel_context.channel_info & \ - HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_M) >> \ - HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_S) -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_CHANNEL_CONTEXT_FLAGS_GET(word) \ - (((word) >> 16) & 0xffff) -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS, _val); \ - ((_var).channel_context.channel_info |= \ - ((_val) << HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_S)); \ - } while (0) - -/* - * Statistics for self-generated response frames Rate, Pkt type, Chainmask. - * Has context that was captured when it was programmed. - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* Common channel context - NOT per frame */ - HTT_STATS_WHAL_SELFGEN_CHANNEL_CONTEXT channel_context; - /* Array indexed by WHAL_RESP_FRAMES enum values */ - HTT_STATS_WHAL_SELFGEN_RESP_FRAME_ENTRY frame_data[HTT_RESP_FRAME_TYPE_MAX]; -} htt_stats_tx_selfgen_resp_frame_stats_tlv; - - -#define HTT_STATS_NUM_DPD_CAL_TABLE 12 - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 pdev_id; - A_UINT32 dpd_cal_start_time; /* ms units */ - A_UINT32 dpd_cal_end_time; /* ms units */ - A_UINT32 total_tx_pass_cnt; - A_UINT32 total_tx_fail_cnt; - /* dpd_trigger_reason: - * The definition of trigger reasons is internal to the - * target FW, hence, this field is opaque to the host and cannot be - * interpreted; this field is intended only for manual debugging. - */ - A_UINT32 dpd_trigger_reason; - /* dpd_training_temp: units = Celsius degrees */ - A_INT32 dpd_training_temp[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - A_INT32 cal_start_temp; /* Celsius degrees */ - A_INT32 cal_end_temp; /* Celsius degrees */ - A_UINT32 cal_channel; /* MHz */ - A_UINT32 cal_phy_mode; /* WLAN_PHY_MODE */ - A_UINT32 cal_chan_flags; /* HTT_STATS_CHANNEL_FLAGS */ - A_UINT32 mem_dpd_post_proc_trigger_cnt; - A_UINT32 mem_dpd_post_proc_complete_cnt; - /* sch_cmd_result_per_chain: - * The definition of scheduler command results is internal to the - * target FW, hence, this field is opaque to the host and cannot be - * interpreted; this field is intended only for manual debugging. - */ - A_UINT32 sch_cmd_result_per_chain[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - /* tx_status_per_chain: 0 = success, 1 = abort, 2 = error */ - A_UINT32 tx_status_per_chain[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - /* dpd_cal_state: - * The definition of cal states is internal to the - * target FW, hence, this field is opaque to the host and cannot be - * interpreted; this field is intended only for manual debugging. - */ - A_UINT32 dpd_cal_state; - A_UINT32 dpd_cal_status; /* 1 = success, 0 = failure */ - /* dpd_fail_reason: - * The definition of DPD cal failure reasons is internal to the - * target FW, hence, this field is opaque to the host and cannot be - * interpreted; this field is intended only for manual debugging. - */ - A_UINT32 dpd_fail_reason; -} htt_stats_dpd_halphy_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 dpd_rx_gain[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - A_UINT32 tpc_gain_idx[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - A_UINT32 tpc_glut[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; -} htt_stats_dpd_hw_cal_params_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* Signal Quality */ - A_UINT32 sq_value[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - A_UINT32 sq_idx[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - A_INT32 nmse_chain[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; -} htt_stats_dpd_hw_cal_results_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 mu_rts_tx_success; - A_UINT32 mu_rts_tx_fail; - A_UINT32 mu_rts_rx_success; - A_UINT32 bsrp_ntb_tx_success; - A_UINT32 bsrp_ntb_tx_fail; - A_UINT32 bsrp_ntb_rx_success; - A_UINT32 bsrp_tx_success; - A_UINT32 bsrp_tx_fail; - A_UINT32 bsrp_rx_success; - A_UINT32 npca_tx_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - A_UINT32 npca_su_tx_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; - A_UINT32 npca_rx_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - A_UINT32 npca_su_rx_punctured_mode[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - A_UINT32 schd_cmd_result_npca[HTT_STATS_MAX_SCH_CMD_RESULT]; - htt_tx_rate_stats_t npca_per_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - htt_tx_rate_stats_t npca_per_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; -} htt_stats_npca_tlv; - - -/*===================== Start PHY DPD/TPC Debug stats ==================== { */ - -typedef enum { - HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_DPD = 0, - HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_TPC = 1, - HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_MAX -} htt_stats_phy_dpd_tpc_debug_subtype_t; - -/* - * htt_stats_phy_dpd_debug_params_v1 - * Per-table DPD debug parameters. All fields packed into A_UINT32 words. - * - * Word 0: dpd_out_nmse_x10 (signed 32-bit, 1/10 dB units) - * Word 1: pa_max_avg_tx (unsigned 32-bit, dBm units) - * Word 2: dpd_training_cnt (unsigned 32-bit) - * Word 3: dpd_scaling (unsigned 32-bit) - * Word 4: BIT[15:0] dpd_training_power_db8 (signed 16-bit, 1/8 dB units) - * BIT[31:16] dpd_out_sq (unsigned 16-bit) - * Word 5: BIT[ 7:0] dpd_state - * BIT[15:8] dpd_in_glut - * BIT[23:16] dpd_in_tx_gain - * BIT[31:24] dpd_out_train_dac_gain (signed 8-bit) - * Word 6: BIT[ 7:0] dpd_in_gc (signed 8-bit) - * BIT[15:8] dpd_out_sq_idx - * BIT[23:16] dpd_out_train_rx_gain_idx - * BIT[31:24] dpd_in_kernel_sel - */ -typedef struct { - A_INT32 dpd_out_nmse_x10; - A_UINT32 pa_max_avg_tx; - A_UINT32 dpd_training_cnt; - A_UINT32 dpd_scaling; - union { - A_UINT32 dpd_training_power_db8__dpd_out_sq; - struct { - A_UINT32 - dpd_training_power_db8: 16, - dpd_out_sq: 16; - }; - }; - union { - A_UINT32 dpd_state__dpd_in_glut__dpd_in_tx_gain__dpd_out_train_dac_gain; - struct { - A_UINT32 - dpd_state: 8, - dpd_in_glut: 8, - dpd_in_tx_gain: 8, - dpd_out_train_dac_gain: 8; - }; - }; - union { - A_UINT32 dpd_in_gc__dpd_out_sq_idx__dpd_out_train_rx_gain_idx__dpd_in_kernel_sel; - struct { - A_UINT32 - dpd_in_gc: 8, - dpd_out_sq_idx: 8, - dpd_out_train_rx_gain_idx: 8, - dpd_in_kernel_sel: 8; - }; - }; -} htt_stats_phy_dpd_debug_params_v1; - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_M 0x0000ffff -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_S 0 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_M 0xffff0000 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_S 16 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_M 0x000000ff -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_S 0 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_M 0x0000ff00 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_S 8 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_M 0x00ff0000 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_S 16 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_M 0xff000000 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_S 24 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_M 0x000000ff -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_S 0 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_M 0x0000ff00 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_S 8 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_M 0x00ff0000 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_S 16 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_M 0xff000000 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_S 24 - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_TRAINING_POWER_DB8_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_OUT_SQ_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_STATE_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_IN_GLUT_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_IN_TX_GAIN_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_OUT_TRAIN_DAC_GAIN_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_IN_GC_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_GET(_var) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_OUT_SQ_IDX_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_OUT_TRAIN_RX_GAIN_IDX_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_IN_KERNEL_SEL_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_S)); \ - } while (0) - -/* - * htt_stats_phy_dpd_debug_chain_v1_tlv - * One TLV per chain. chain_idx identifies which chain this TLV carries. - * - * Word 0 (after tlv_hdr): - * BIT[ 7: 0] - chain_idx - * BIT[15: 8] - version - * BIT[31:16] - chainmask - * Word 1: - * BIT[ 7: 0] - num_gain_idx - * BIT[31: 8] - reserved - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - A_UINT32 chain_idx__version__chainmask; - struct { - A_UINT32 - chain_idx: 8, - version: 8, - chainmask: 16; - }; - }; - union { - A_UINT32 num_gain_idx__reserved; - struct { - A_UINT32 - num_gain_idx: 8, - reserved: 24; - }; - }; - htt_stats_phy_dpd_debug_params_v1 dpd_debug_params[HTT_STATS_NUM_DPD_CAL_TABLE]; -} htt_stats_phy_dpd_debug_chain_v1_tlv; - -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_M 0x000000ff -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_S 0 -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_M 0x0000ff00 -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_S 8 -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_M 0xffff0000 -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_S 16 - -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_M 0x000000ff -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_S 0 - -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_S) -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_S) -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_S) -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_S) -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_S)); \ - } while (0) - -/* - * htt_stats_phy_tpc_debug_chain_v1_tlv - * One TLV per chain. All sub-byte/sub-word fields packed into A_UINT32 words. - * - * Word 0 (after tlv_hdr): - * BIT[ 7: 0] - chain_idx - * BIT[15: 8] - version - * BIT[31:16] - chainmask - * - * Words 1-11: TPC per-chain debug params (all A_UINT32) - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* - * Word 0: BIT[ 7: 0]=chain_idx - * BIT[15: 8]=version - * BIT[31:16]=chainmask - */ - union { - A_UINT32 chain_idx__version__chainmask; - struct { - A_UINT32 - chain_idx: 8, - version: 8, - chainmask: 16; - }; - }; - /* - * Word 1: BIT[7:0]=lat_glut_idx, - * BIT[15:8]=lat_tx_gain_idx, - * BIT[23:16]=lat_dac_gain(s8), - * BIT[31:24]=lat_target_power(s8) - */ - union { - A_UINT32 lat_glut_idx__lat_tx_gain_idx__lat_dac_gain__lat_target_power; - struct { - A_UINT32 - lat_glut_idx: 8, - lat_tx_gain_idx: 8, - lat_dac_gain: 8, - lat_target_power: 8; - }; - }; - /* - * Word 2: BIT[15:0]=lat_acc_clpc_error(s16), - * BIT[31:16]=lat_clpc_err(s16) - */ - union { - A_UINT32 lat_acc_clpc_error__lat_clpc_err; - struct { - A_UINT32 - lat_acc_clpc_error: 16, - lat_clpc_err: 16; - }; - }; - /* - * Word 3: BIT[15:0]=lat_meas_pwr(s16), - * BIT[23:16]=lat_wsi_temp_valid, - * BIT[31:24]=lat_wsi_full_pkt_pwr_valid - */ - union { - A_UINT32 lat_meas_pwr__lat_wsi_temp_valid__lat_wsi_full_pkt_pwr_valid; - struct { - A_UINT32 - lat_meas_pwr: 16, - lat_wsi_temp_valid: 8, - lat_wsi_full_pkt_pwr_valid: 8; - }; - }; - /* - * Word 4: BIT[7:0]=lat_wsi_pream_pwr_valid, - * BIT[23:8]=lat_wsi_temp(s16), - * BIT[31:24]=lat_wsi_full_pkt_pwr - */ - union { - A_UINT32 lat_wsi_pream_pwr_valid__lat_wsi_temp__lat_wsi_full_pkt_pwr; - struct { - A_UINT32 - lat_wsi_pream_pwr_valid: 8, - lat_wsi_temp: 16, - lat_wsi_full_pkt_pwr: 8; - }; - }; - /* - * Word 5: BIT[7:0]=lat_wsi_pream_pwr, - * BIT[15:8]=lat_wsi_tx_gain_idx, - * BIT[23:16]=lat_wsi_tpc_pdet_gain_idx, - * BIT[31:24]=lat_wsi_tpc_attn - */ - union { - A_UINT32 lat_wsi_pream_pwr__lat_wsi_tx_gain_idx__lat_wsi_tpc_pdet_gain_idx__lat_wsi_tpc_attn; - struct { - A_UINT32 - lat_wsi_pream_pwr: 8, - lat_wsi_tx_gain_idx: 8, - lat_wsi_tpc_pdet_gain_idx: 8, - lat_wsi_tpc_attn: 8; - }; - }; - /* - * Word 6: BIT[7:0]=glut_dac_gain_cal(s8), - * BIT[15:8]=glut_max_dac_gain_cal(s8), - * BIT[23:16]=dpd_dac_gain_cal(s8), - * BIT[31:24]=dpd_tx_gain_idx_cal - */ - union { - A_UINT32 glut_dac_gain_cal__glut_max_dac_gain_cal__dpd_dac_gain_cal__dpd_tx_gain_idx_cal; - struct { - A_UINT32 - glut_dac_gain_cal: 8, - glut_max_dac_gain_cal: 8, - dpd_dac_gain_cal: 8, - dpd_tx_gain_idx_cal: 8; - }; - }; - /* - * Word 7: BIT[7:0]=target_pwr_clpc_thr_corr(s8), - * BIT[15:8]=olpc_mode, - * BIT[23:16]=wsi_timeout, - * BIT[31:24]=target_pwr_clpc_thr_update(s8) - */ - union { - A_UINT32 target_pwr_clpc_thr_corr__olpc_mode__wsi_timeout__target_pwr_clpc_thr_update; - struct { - A_UINT32 - target_pwr_clpc_thr_corr: 8, - olpc_mode: 8, - wsi_timeout: 8, - target_pwr_clpc_thr_update: 8; - }; - }; - /* - * Word 8: BIT[7:0]=ro_temp_valid, - * BIT[15:8]=ro_full_pkt_pwr_valid, - * BIT[23:16]=ro_pream_pwr_valid, - * BIT[31:24]=reserved - */ - union { - A_UINT32 ro_temp_valid__ro_full_pkt_pwr_valid__ro_pream_pwr_valid; - struct { - A_UINT32 - ro_temp_valid: 8, - ro_full_pkt_pwr_valid: 8, - ro_pream_pwr_valid: 8, - reserved: 8; - }; - }; - /* - * Word 9: BIT[15:0]=ro_temp(s16), - * BIT[23:16]=ro_full_pkt_pwr, - * BIT[31:24]=ro_pream_pwr - */ - union { - A_UINT32 ro_temp__ro_full_pkt_pwr__ro_pream_pwr; - struct { - A_UINT32 - ro_temp: 16, - ro_full_pkt_pwr: 8, - ro_pream_pwr: 8; - }; - }; - /* - * Word 10: BIT[7:0]=ro_tpc_fe_sel, - * BIT[15:8]=ro_full_pkt_avg_out, - * BIT[23:16]=ro_lat_dc, - * BIT[31:24]=ro_pdacc_avg_out - */ - union { - A_UINT32 ro_tpc_fe_sel__ro_full_pkt_avg_out__ro_lat_dc__ro_pdacc_avg_out; - struct { - A_UINT32 - ro_tpc_fe_sel: 8, - ro_full_pkt_avg_out: 8, - ro_lat_dc: 8, - ro_pdacc_avg_out: 8; - }; - }; - /* - * Word 11: BIT[15:0]=temp_per_chain, - * BIT[23:16]=cal_cmd, - * BIT[31:24]=cal_time - */ - union { - A_UINT32 temp_per_chain__cal_cmd__cal_time; - struct { - A_UINT32 - temp_per_chain: 16, - cal_cmd: 8, - cal_time: 8; - }; - }; - /* - * Word 12: BIT[7:0]=cal_result, - * BIT[31:8]=reserved - */ - union { - A_UINT32 cal_result__reserved; - struct { - A_UINT32 - cal_result: 8, - reserved2: 24; - }; - }; -} htt_stats_phy_tpc_debug_chain_v1_tlv; - -/* TPC chain header GET/SET macros */ -/* word 0 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_M 0xffff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_S 16 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_S)); \ - } while (0) - -/* word 1 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_S)); \ - } while (0) - -/* word 2 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_M 0x0000ffff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_M 0xffff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_S 16 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_S)); \ - } while (0) - -/* word 3 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_M 0x0000ffff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_S)); \ - } while (0) - -/* word 4 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_M 0x00ffff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_S)); \ - } while (0) - -/* word 5 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_S)); \ - } while (0) - -/* word 6 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_S)); \ - } while (0) - -/* word 7 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_S)); \ - } while (0) - -/* word 8 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_S 16 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_S)); \ - } while (0) - -/* word 9 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_M 0x0000ffff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_S)); \ - } while (0) - -/* word 10 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_S)); \ - } while (0) - -/* word 11 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_M 0x0000ffff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_S)); \ - } while (0) - -/* word 12 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_S 0 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_S)); \ - } while (0) - -/*===================== End PHY DPD/TPC Debug stats ==================== } */ - - #endif /* __HTT_STATS_H__ */ diff --git a/drivers/staging/fw-api/fw/wlan_defs.h b/drivers/staging/fw-api/fw/wlan_defs.h index 2e7a28ec2a7d..2e8db1346a90 100755 --- a/drivers/staging/fw-api/fw/wlan_defs.h +++ b/drivers/staging/fw-api/fw/wlan_defs.h @@ -75,6 +75,19 @@ */ #define CONFIG_160MHZ_SUPPORT_UNDEF_WAR #endif +#else + /* + * For backwards compatibility, if CONFIG_160MHZ_SUPPORT is not defined, + * default it to 0, if this is either a host build or a Rome target build. + * This maintains the prior behavior for the host and Rome target builds. + */ + #if defined(AR6320) || !defined(ATH_TARGET) + /* + * Set a flag to indicate that at the end of the file, + * CONFIG_160MHZ_SUPPORT should be set to 0. + */ + #define CONFIG_160MHZ_SUPPORT_UNDEF_WAR + #endif #endif #ifndef SUPPORT_11AX @@ -148,18 +161,6 @@ typedef enum { MODE_11BE_EHT40_2G = 32, /* For WIN */ #endif -#if defined(SUPPORT_11BN) && SUPPORT_11BN - MODE_11BN_UHR20 = 33, - MODE_11BN_UHR40 = 34, - MODE_11BN_UHR80 = 35, - MODE_11BN_UHR80_80 = 36, - MODE_11BN_UHR160 = 37, - MODE_11BN_UHR160_160 = 38, - MODE_11BN_UHR320 = 39, - MODE_11BN_UHR20_2G = 40, - MODE_11BN_UHR40_2G = 41, -#endif - /* * MODE_UNKNOWN should not be used within the host / target interface. * Thus, it is permissible for MODE_UNKNOWN to be conditionally-defined, @@ -257,38 +258,10 @@ typedef enum { ((mode) == MODE_11BE_EHT320) || \ ((mode) == MODE_11BE_EHT20_2G) || \ ((mode) == MODE_11BE_EHT40_2G)) -#define IS_MODE_EHT_5G_6G(mode) (((mode) == MODE_11BE_EHT20) || \ - ((mode) == MODE_11BE_EHT40) || \ - ((mode) == MODE_11BE_EHT80) || \ - ((mode) == MODE_11BE_EHT80_80) || \ - ((mode) == MODE_11BE_EHT160) || \ - ((mode) == MODE_11BE_EHT160_160)|| \ - ((mode) == MODE_11BE_EHT320)) #define IS_MODE_EHT_2G(mode) (((mode) == MODE_11BE_EHT20_2G) || \ ((mode) == MODE_11BE_EHT40_2G)) #endif /* SUPPORT_11BE */ -#if defined(SUPPORT_11BN) && SUPPORT_11BN -#define IS_MODE_UHR(mode) (((mode) == MODE_11BN_UHR20) || \ - ((mode) == MODE_11BN_UHR40) || \ - ((mode) == MODE_11BN_UHR80) || \ - ((mode) == MODE_11BN_UHR80_80) || \ - ((mode) == MODE_11BN_UHR160) || \ - ((mode) == MODE_11BN_UHR160_160)|| \ - ((mode) == MODE_11BN_UHR320) || \ - ((mode) == MODE_11BN_UHR20_2G) || \ - ((mode) == MODE_11BN_UHR40_2G)) -#define IS_MODE_UHR_5G_6G(mode) (((mode) == MODE_11BN_UHR20) || \ - ((mode) == MODE_11BN_UHR40) || \ - ((mode) == MODE_11BN_UHR80) || \ - ((mode) == MODE_11BN_UHR80_80) || \ - ((mode) == MODE_11BN_UHR160) || \ - ((mode) == MODE_11BN_UHR160_160)|| \ - ((mode) == MODE_11BN_UHR320)) -#define IS_MODE_UHR_2G(mode) (((mode) == MODE_11BN_UHR20_2G) || \ - ((mode) == MODE_11BN_UHR40_2G)) -#endif /* SUPPORT_11BN */ - #define IS_MODE_VHT_2G(mode) (((mode) == MODE_11AC_VHT20_2G) || \ ((mode) == MODE_11AC_VHT40_2G) || \ ((mode) == MODE_11AC_VHT80_2G)) diff --git a/drivers/staging/fw-api/fw/wlan_module_ids.h b/drivers/staging/fw-api/fw/wlan_module_ids.h index fc65f819f510..981bbaef3451 100644 --- a/drivers/staging/fw-api/fw/wlan_module_ids.h +++ b/drivers/staging/fw-api/fw/wlan_module_ids.h @@ -196,9 +196,6 @@ typedef enum { WLAN_MODULE_C2C, /* 0x98 */ WLAN_MODULE_VBSS, /* 0x99 */ WLAN_MODULE_OPT_DATA, /* 0x9a */ - WLAN_MODULE_ASD, /* 0x9b */ - WLAN_MODULE_ENERGY_MGMT, /* 0x9c */ - WLAN_MODULE_SMD, /* 0x9d */ WLAN_MODULE_ID_MAX, WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX, diff --git a/drivers/staging/fw-api/fw/wmi_services.h b/drivers/staging/fw-api/fw/wmi_services.h index 18acd1f63fd7..b82c7bd1fc45 100644 --- a/drivers/staging/fw-api/fw/wmi_services.h +++ b/drivers/staging/fw-api/fw/wmi_services.h @@ -695,168 +695,6 @@ typedef enum { WMI_SERVICE_UMAC_MIGRATION_SUPPORT = 436, /* Indicates that FW supports UMAC migration */ WMI_SERVICE_STA_TWT_STATS_EXT = 437, /* FW supports additional info in TWT stats and ADD COMPLETION Event */ WMI_SERVICE_OPT_DP_DIAG_SUPPORT = 438, /* FW supports diag QDATA feature */ - WMI_SERVICE_MLO_ROAM_PARTNER_BRINGUP_FROM_HOST = 439, /* Indicates FW supports new design in which FW expects the host to bringup the partner link during roaming */ - WMI_SERVICE_CTRL_PATH_PEER_BA_STATS = 440, /* FW supports retrieving BlockAck stats through WMI_REQUEST_CTRL_PATH_PEER_STAT */ - WMI_SERVICE_CTRL_PATH_STA_DAR_STATS_SUPPORT = 441, /* FW supports DAR stats reporting for STA mode */ - WMI_SERVICE_APF_DATA_OFFLOAD_SUPPORT_ENABLED = 442, /* Indicates FW support for APFv6 handling offloads and disable QC data offloads */ - WMI_SERVICE_PER_VDEV_TWT_RESP_DISABLE_SUPPORT = 443, /* FW supports vdev level TWT responder disable */ - WMI_SERVICE_VENDOR_OUI_ACTION_V2 = 444, /* FW supports vendor OUI action version 2 */ - WMI_SERVICE_HW_BLACKLIST_CHAN_SUPPORT = 445, /* Indicates FW support for computing and sending the HW channel blacklist for the current country and applicable power mode */ - WMI_SERVICE_NDP_DFS_CHANNEL_SUPPORT = 446, /* FW supports forming NDP on DFS channels */ - WMI_SERVICE_WFD_R2 = 447, /* Indicates FW supports WiFi-Direct R2 */ - WMI_SERVICE_STA_MLO_RCFG_SUPPORT = 448, /* FW supports STA ML reconfig op */ - WMI_SERVICE_PDEV_SUSPEND_EVENT_SUPPORT = 449, /* FW supports PDEV_SUSPEND event */ - WMI_SERVICE_PCC_MODE = 450, /* Indicates FW support for PCC (P2P Connection Compatibility) Mode */ - WMI_SERVICE_TDLS_NSS_CONFIRM_SUPPORT = 451, /* FW supports confirmation to host requested TDLS NSS operation */ - - WMI_SERVICE_EM_PCIE_CONFIG_CBW_SUPPORT = 452, /* Indicates support for channel bandwidth based PCIe config adjustment */ - WMI_SERVICE_EM_PCIE_CONFIG_LPM_SUPPORT = 453, /* Indicates support for PCIe low power mode L0S/L1 */ - WMI_SERVICE_EM_DCVS_SUPPORT = 454, /* Indicates support for Dynamic clock and voltage scaling */ - WMI_SERVICE_EM_EDPS_SUPPORT = 455, /* Indicates support for Dynamic AP power save */ - WMI_SERVICE_EM_PUO_SUPPORT = 456, /* Indicates support for TWT based periodic unavailability operation. */ - WMI_SERVICE_EM_ECO_MODE_SUPPORT = 457, /* Indicates support for ECO mode config (LP BBF+ADC+SYNCT) */ - - WMI_SERVICE_11BN = 458, /* Indicates FW supports 802.11bn */ - WMI_SERVICE_HOST_AWARE_POWERSAVE = 459, /* FW supports indicating the powerstate of FW to host */ - WMI_SERVICE_PDEV_DIV_STATES_REPORT = 460, /* FW supports reporting antenna diversity states */ - WMI_SERVICE_EAPOL_OVER_RAW = 461, /* FW supports sending EAPOL frames in raw mode even when the vdev is brought up in nwifi/ethernet mode */ - WMI_SERVICE_MLO_SAP_LINK_REMOVAL_SUPPORT = 462, /* Indicates FW supports MLO SAP link removal operation */ - WMI_SERVICE_TX_POWER_LIMIT = 463, /* FW supports temporary tx power limit indication to HALPHY */ - WMI_SERVICE_NPCA_SUPPORT = 464, /* Indicates FW supports NPCA (Non-Primary Channel Access) */ - WMI_SERVICE_EXT_TLV_SUPPORT = 465, /* FW supports WMI_MAX_NUM_EXT_TLVS */ - WMI_SERVICE_VDEV_TRAFFIC_MONITORING = 466, /* FW supports traffic monitoring */ - WMI_SERVICE_EM_DPS_ASSISTING_ROLE_SUPPORT = 467, /* Indicates support for Energy Mgmt DPS assisting role operation */ - WMI_SERVICE_XPAN_SAP_STA_PWRSAVE_SUPPORT = 468, /* Indicates support for power optimization in XPAN + STA */ - WMI_SERVICE_CFP_SUPPORT = 469, /* FW supports control frame protection */ - WMI_SERVICE_CFP_PADDING_SUPPORT = 470, /* FW supports control frame protection padding */ - - /* Service caps related to 11BI */ - WMI_SERVICE_11BI_EPPKE_SUPPORT = 471, - WMI_SERVICE_11BI_1X_OVER_AUTH_SUPPORT = 472, - WMI_SERVICE_11BI_PMKID_PRIVACY_SUPPORT = 473, - WMI_SERVICE_11BI_DS_MAC_ADDR_SUPPORT = 474, - - WMI_SERVICE_CCK_RX_SUPPORT_5GHZ = 475, /* Indicates FW supports CCK RX in 5 GHz band */ - WMI_SERVICE_CCK_TX_SUPPORT_5GHZ = 476, /* Indicates FW supports CCK TX in 5 GHZ band */ - WMI_SERVICE_DIRECT_REFILL_SUPPORT = 477, /* Indicates FW supports direct refill for RX buffer ring */ - WMI_SERVICE_NAN_STANDARD_MODE_SUPPORT = 478, /* Indicates FW supports NAN in standard mode (supplicant-based NAN architecture model) */ - WMI_SERVICE_CONC_2VDEV_DCS_STATS_SUPPORT = 479, /* Indicate FW support for collecting DCS stats for more than 1 vdev (max 2 concurrent vdevs) */ - WMI_SERVICE_CFR_UNASSOC_RX_CAPTURE_SUPPORT = 480, /* Indicates FW supports RX-based unassociated CFR capture */ - WMI_SERVICE_CFR_ASSOC_TX_CAPTURE_SUPPORT = 481, /* Indicates FW supports TX-based CFR capture */ - WMI_SERVICE_VDEV_UNIFIED_CONNECT_DISCONNECT_SUPPORT = 482, /* Indicates FW support for unified connect and disconnect vdev cmds for link switch */ - WMI_SERVICE_ENHANCED_STATS_SUPPORT = 483, /* Indicates FW supports "enhanced stats" */ - WMI_SERVICE_RADAR_FLAGS_RSSI_DBM_SUPPORT = 484, /* Indicates FW support to add RSSI in dBm units in WMI radar event */ - WMI_SERVICE_WOW_STA_PS_PARAM_CACHE_SUPPORT = 485, /* Indicates FW support for WOW timeline optimization feature */ - WMI_SERVICE_VENDOR_OUI_SUPPORT_EXCLUSIVE_MAC_ADDRESS = 486, /* FW supports parse exclusive_mac_address in wmi_vendor_oui_ext */ - WMI_SERVICE_P2P_CANCEL_ONE_SHOT_NOA_SUPPORT = 487, /* Indicates FW support for P2P GO/GC cancel one-shot NOA feature */ - WMI_SERVICE_SMD_BSS_TRANSITION_SUPPORT = 488, /* Indicates FW supports S(eamless)M(obility)D(omain) BSS transition */ - - /* Service caps related to SMD Roaming - start */ - WMI_SERVICE_SMD_SUPPORT_ROAMING = 489, - WMI_SERVICE_SMD_SUPPORT_DL_FORWARD = 490, - WMI_SERVICE_SMD_SUPPORT_UL_FORWARD = 491, - /* Service caps related to SMD Roaming - end */ - - WMI_SERVICE_PEER_METADATA_V2_SUPPORT = 492, /* Support rx peer meta data v2 */ - /* WMI_SERVICE_HANDLE_ROAMING_WITHOUT_RSO_STOP_FOR_4WAY_HS_OFFLOAD_DISABLE: - * Indicates support to handle roaming triggers while host is doing - * the EAPOL process for 4way HS offload disable case. - * FW needs to disable the roam triggers except deauth roaming. - */ - WMI_SERVICE_HANDLE_ROAMING_WITHOUT_RSO_STOP_FOR_4WAY_HS_OFFLOAD_DISABLE = 493, - /* Indicates FW support for populating vdev operating param stats */ - WMI_SERVICE_VDEV_OPERATING_PARAMS_EVENT_SUPPORT = 494, - WMI_SERVICE_SUPPORT_WOW_OLE_DAL = 495, - /* Indicate FW support for PASSTHRU VDEV Channel Hopping Schedule */ - WMI_SERVICE_PASSTHRU_VDEV_CHAN_HOP_SCHEDULE_SUPPORT = 496, - /* - * Indicates FW support for shared memory model to pass - * ongoing TBTT count downs to Host. - */ - WMI_SERVICE_SHARED_MEM_MODEL_TBTT_COUNT_DOWN = 497, - /* Indicate FW support for IPI (Idle Power Indicate) stats collection */ - WMI_SERVICE_IDLE_POWER_INDICATE_SUPPORT = 498, - /* Indicates FW support to add Radar type and domain in WMI radar event */ - WMI_SERVICE_RADAR_FLAGS_TYPE_SUPPORT = 499, - /* Indicates FW support to perform Master migration when master peer gets deleted */ - WMI_SERVICE_ML_PEER_MASTER_MIGRATION_SUPPORT = 500, - WMI_SERVICE_NAN_AP_ASSISTED_DFS_OPERATION_SUPPORT = 501, /* Indicates FW supports NAN DFS operation */ - /* - * Indicates FW supports TDLS Stats command/event, - * used for sending TDLS connect info and TDLS data stats - */ - WMI_SERVICE_TDLS_STATS_SUPPORT = 502, - WMI_SERVICE_L3_HEADER_PADDING_ENABLE = 503, - - /* Indicates FW supports Extended OUI Action IDs */ - WMI_SERVICE_SUPPORTED_EXT_OUI_ACTION_IDS = 504, - - /* - * Indicates FW supports cloud based control for whitelist or blacklist - * AP configuration - */ - WMI_SERVICE_SUPPORT_WHITELIST_BLACKLIST_AP_CONFIG = 505, - /* - * Indicate FW support for PASSTHRU VDEV AMPDU Aggregation - * and Rate Adaptation - */ - WMI_SERVICE_PASSTHRU_VDEV_AMPDU_RA_SUPPORT = 506, - /* FW supports CalDB transmission over WMI */ - WMI_SERVICE_CALDB_OVER_WMI = 507, - /* Indicates FW Supports RTT Proximity Detection (USD ranging) */ - WMI_SERVICE_RTT_PD = 508, - /* Indicates FW support for Channel Hopping Status Report*/ - WMI_SERVICE_VDEV_CHAN_HOP_STATUS_REPORT = 509, - /* Indicates FW support for Predictive roaming */ - WMI_SERVICE_ROAMING_PREDICTIVE = 510, - - /* Services related to MAPC / C-TDMA (802.11bn) */ - WMI_SERVICE_CO_AP_CTDMA_SUPPORT = 511, - WMI_SERVICE_UHR_CO_AP_CTDMA_TB_PPDU_SUPPORT = 512, - WMI_SERVICE_UHR_CO_AP_CTDMA_TXOP_RETURN_SUPPORT = 513, - - /* - * Indicates FW supports cloud based control for Uplink Tx Beamformer - * AP configuration - */ - WMI_SERVICE_SUPPORT_UL_TX_BEAMFORMER_AP_CONFIG = 514, - - /* Indicates FW supports enable/disable TWT per vdev */ - WMI_SERVICE_STA_TWT_EN_DIS_VDEV_SUPPORT = 515, - - /* - * Indicates FW supports AWGN interference status request via - * WMI_PDEV_PARAM_AWGN_INT_STATUS_REQUEST, allowing host to query - * the current AWGN CCA segment bitmap (awgn_prev_int_seg) which - * is sent back immediately via WMI_DCS_INTERFERENCE_EVENTID. - */ - WMI_SERVICE_AWGN_INT_STATUS_REQUEST_SUPPORT = 516, - - WMI_SERVICE_WMI_ANOMALY_REPORTING = 517, - - /* - * Indicates that FW supports C-TAS power indication reporting and - * power limit enquiring through cmds WMI_SET_MODIFY_TX_PLIM_CMDID, - * WMI_GET_AVG_TX_POWER_CMDID and WMI_GET_TX_POWER_CALLING_CMDID. - */ - WMI_SERVICE_CTAS_PLIM_INDICATION_SUPPORT = 518, - - /* - * Indicates FW supports NAN in offload mode - * (supplicant-based NAN offload mode architecture). - */ - WMI_SERVICE_NAN_OFFLOAD_MODE_SUPPORT = 519, - - /* WMI_SERVICE_PDEV_SET_CUMAC_CHIP_CMD_SUPPORT: - * FW supports handling WMI_PDEV_SET_CUMAC_CHIP_CMDID. - * When this service bit is set in wmi_service_ready, the host can - * set WMI_RSRC_CFG_HOST_SERVICE_FLAG_CUMAC_CMD_SUPPORT in - * wmi_resource_config.host_service_flags to indicate it will send - * WMI_PDEV_SET_CUMAC_CHIP_CMDID to trigger wal_mlo_cumac_init(). - * If the host does not set this flag, FW will call wal_mlo_cumac_init() - * from wal_mlo_soc_init() with the default chip id. - */ - WMI_SERVICE_PDEV_SET_CUMAC_CHIP_CMD_SUPPORT = 520, WMI_MAX_EXT2_SERVICE diff --git a/drivers/staging/fw-api/fw/wmi_tlv_defs.h b/drivers/staging/fw-api/fw/wmi_tlv_defs.h index 05e4a9aaa6c5..e8c306dbcb7f 100644 --- a/drivers/staging/fw-api/fw/wmi_tlv_defs.h +++ b/drivers/staging/fw-api/fw/wmi_tlv_defs.h @@ -1200,8 +1200,6 @@ typedef enum { WMITLV_TAG_STRUC_wmi_ctrl_path_dfs_channel_stats_struct, WMITLV_TAG_STRUC_wmi_twt_ack_event_fixed_param, WMITLV_TAG_STRUC_wmi_twt_caps_param, - WMITLV_TAG_STRUC_wmi_twt_caps_params = /* alias */ - WMITLV_TAG_STRUC_wmi_twt_caps_param, WMITLV_TAG_STRUC_wmi_vdev_enable_disable_intra_bss_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_peer_enable_disable_intra_bss_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_aoa_phasedelta_evt_fixed_param, @@ -1223,8 +1221,6 @@ typedef enum { WMITLV_TAG_STRUC_wmi_dbs_or_sbs_cap_ext, WMITLV_TAG_STRUC_wmi_roam_set_param_cmd_fixed_param, WMITLV_TAG_STRUC_cust_bdf_version_capabilities, - WMITLV_TAG_STRUC_wmi_cust_bdf_version_capabilities = /* alias */ - WMITLV_TAG_STRUC_cust_bdf_version_capabilities, WMITLV_TAG_STRUC_wmi_pdev_fips_extend_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_fips_extend_cmd_init_params, WMITLV_TAG_STRUC_wmi_pdev_fips_extend_event_fixed_param, @@ -1432,8 +1428,6 @@ typedef enum { WMITLV_TAG_STRUC_wmi_dcs_obss_int_t, WMITLV_TAG_STRUC_wmi_pdev_wifi_radar_cal_completion_status_event_param, WMITLV_TAG_STRUC_wmi_sar_flags, - WMITLV_TAG_STRUC_wmi_sar_flag_tlv_param = /* alias */ - WMITLV_TAG_STRUC_wmi_sar_flags, WMITLV_TAG_STRUC_wmi_pdev_enable_xlna_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_enable_xlna_event_fixed_param, WMITLV_TAG_STRUC_wmi_reg_chan_list_cc_event_ext2_fixed_param, @@ -1464,11 +1458,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_scan_cache_result_event_fixed_param, WMITLV_TAG_STRUC_wmi_scan_cache_info, WMITLV_TAG_STRUC_wmi_POWER_BOOST_CAPABILITIES, - WMITLV_TAG_STRUC_WMI_POWER_BOOST_CAPABILITIES = /* alias */ - WMITLV_TAG_STRUC_wmi_POWER_BOOST_CAPABILITIES, WMITLV_TAG_STRUC_wmi_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES, - WMITLV_TAG_STRUC_WMI_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES = /* alias */ - WMITLV_TAG_STRUC_wmi_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES, WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_start_indication_event_fixed_param, WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_fixed_param, WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_complete_fixed_param, @@ -1486,178 +1476,6 @@ typedef enum { WMITLV_TAG_STRUC_wmi_vdev_vbss_peer_sn_info, WMITLV_TAG_STRUC_wmi_vdev_vbss_config_event_fixed_param, WMITLV_TAG_STRUC_wmi_stats_ext_event_vdev_ext2_t, - WMITLV_TAG_STRUC_wmi_ndp_set_latency_tput_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_partner_link_param, - WMITLV_TAG_STRUC_wmi_mlo_link_ttlm_complete_fixed_param, - WMITLV_TAG_STRUC_wmi_ctrl_path_sta_dar_stats_struct, - WMITLV_TAG_STRUC_wmi_bpf_set_supported_offload_bitmap_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_hw_blacklist_chan_fixed_param, - WMITLV_TAG_STRUC_wmi_hw_blacklist_chan_data, - WMITLV_TAG_STRUC_wmi_pdev_suspend_event_fixed_param, - WMITLV_TAG_STRUC_wmi_bpf_set_apf_mode_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_assoc_operating_mode_params, - WMITLV_TAG_STRUC_wmi_recv_bcn_stats, - WMITLV_TAG_STRUC_wmi_vdev_vbss_peer_dyn_info, - WMITLV_TAG_STRUC_wmi_energy_mgmt_pcie_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_energy_mgmt_pcie_lpm_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_energy_mgmt_dcvs_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_energy_mgmt_edps_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_energy_mgmt_puo_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_energy_mgmt_eco_mode_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_assoc_mgmt_mpduq_params, - WMITLV_TAG_STRUC_wmi_peer_assoc_mgmt_msduq_params, - WMITLV_TAG_STRUC_wmi_peer_assoc_hol_msduq_params, - /* for backwards-compatibility, maintain old name (with "mdsu" typo) */ - WMITLV_TAG_STRUC_wmi_peer_assoc_hol_mdsuq_params = - WMITLV_TAG_STRUC_wmi_peer_assoc_hol_msduq_params, - WMITLV_TAG_STRUC_wmi_peer_tid_rate_custom_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_co_located_chan_info, - WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_cmd_fixed_param, /* deprecated */ - WMITLV_TAG_STRUC_wmi_peer_uhr_npca_cap_params, - WMITLV_TAG_STRUC_wmi_peer_uhr_mode_update_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_resp_event_fixed_param, /*deprecated*/ - WMITLV_TAG_STRUC_wmi_wfa_config_ml, - WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_ac_info, - WMITLV_TAG_STRUC_wmi_vdev_get_tpc_ie_power_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_coex_stats, - WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, - WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES_EXT2, - WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, - WMITLV_TAG_STRUC_wmi_pdev_set_tx_chainmask_comp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_fw_ready_ind_event_fixed_param, - WMITLV_TAG_STRUC_wmi_wlan_mode_req_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_wlan_mode_resp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_ctrl_config_param, - WMITLV_TAG_STRUC_wmi_nan_disc_band_config_param, - WMITLV_TAG_STRUC_wmi_nan_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_enable_rsp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_next_dw_info_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disable_cnf_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disable_ind_fixed_param, - WMITLV_TAG_STRUC_wmi_cfr_capture_filter_resp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_unified_connect_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_unified_connect_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_beacon_stats, - WMITLV_TAG_STRUC_wmi_vdev_congestion_stats, - WMITLV_TAG_STRUC_wmi_vdev_data_stats, - WMITLV_TAG_STRUC_wmi_em_pcie_stats, - WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, - WMITLV_TAG_STRUC_wmi_roam_smd_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_repurpose_resp_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_repurpose_request_tlv_param, - WMITLV_TAG_STRUC_wmi_vdev_repurpose_response_tlv_param, - WMITLV_TAG_STRUC_wmi_roam_smd_start_status_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_prep_resp_status_list, - WMITLV_TAG_STRUC_wmi_ipa_ring_stats_req_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ipa_ring_stats_conf_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ipa_ring_stat_entry, - WMITLV_TAG_STRUC_wmi_em_dcvs_stats, - WMITLV_TAG_STRUC_wmi_uhr_ap_dps_params, - WMITLV_TAG_STRUC_wmi_uhr_ap_npca_params, - WMITLV_TAG_STRUC_wmi_uhr_ap_duo_params, - WMITLV_TAG_STRUC_wmi_uhr_ap_pedca_params, - WMITLV_TAG_STRUC_wmi_uhr_ap_dbe_params, - WMITLV_TAG_STRUC_wmi_uhr_ap_puo_params, - WMITLV_TAG_STRUC_wmi_uhr_ap_elr_reception_params, - WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_status, - WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_event_fixed_param, - WMITLV_TAG_STRUC_wmi_cfr_capture_fix_agc_gain_config, - WMITLV_TAG_STRUC_wmi_cfr_capture_fix_agc_gain_info, - WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_power_stats_info, - WMITLV_TAG_STRUC_wmi_pdev_tx_rate_info, - WMITLV_TAG_STRUC_wmi_vdev_start_smd_params, - WMITLV_TAG_STRUC_wmi_smd_roam_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_smd_roam_config_event_fixed_param, - WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_complete_event_fixed_param, - WMITLV_TAG_STRUC_wmi_smd_roam_peer_tid_info, - WMITLV_TAG_STRUC_wmi_uhr_ap_mode_tup_enable_disable_update_param, - WMITLV_TAG_STRUC_wmi_scan_suppress_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_get_scan_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_soc_get_conc_info_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_get_scan_stats_resp_fixed_param, - WMITLV_TAG_STRUC_wmi_soc_get_conc_info_resp_fixed_param, - WMITLV_TAG_STRUC_wmi_conc_info, - WMITLV_TAG_STRUC_wmi_nan_local_schedule_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_peer_params_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_local_schedule_cnf_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cnf_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_peer_params_cnf_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_channel, - WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_fixed_param, - WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_channel_hopping_schedule_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_current_operating_param_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ch_usage_add_dialog_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_coex_policy_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_coex_policy_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_channel_hopping_channel_params, - WMITLV_TAG_STRUC_wmi_uhr_rate_set, - WMITLV_TAG_STRUC_wmi_shared_mem_model_tbtt_count_down_config, - WMITLV_TAG_STRUC_wmi_vdev_create_tbtt_count_down_offset_info, - WMITLV_TAG_STRUC_wmi_vdev_start_uhr_config, - WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param, - WMITLV_TAG_STRUC_wmi_iface_ipi_stats, - WMITLV_TAG_STRUC_wmi_peer_uhr_npca_op_params, - WMITLV_TAG_STRUC_wmi_ndp_channel_info_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_uhr_omp_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_uhr_omp_npca_params, - WMITLV_TAG_STRUC_wmi_nan_dfs_channel_availability_ind_event_fixed_param, - WMITLV_TAG_STRUC_wmi_request_tdls_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_tdls_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_tdls_connect_info_stats, - WMITLV_TAG_STRUC_wmi_tdls_data_stats, - WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_anomaly_report_hdr, - WMITLV_TAG_STRUC_wmi_anomaly_entry_t, - WMITLV_TAG_STRUC_wmi_peer_uhr_omp_sta_dps_params, - WMITLV_TAG_STRUC_wmi_rtt_peer_meas_capabilities, - WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_peer_info, - WMITLV_TAG_STRUC_wmi_rtt_peer_meas_cancel_meas_cmd_fix_param, - WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_event_fixed_param, - WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_peer_meas_result_info, - WMITLV_TAG_STRUC_wmi_vdev_get_chan_hop_status_report_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_chan_hop_slot_status, - WMITLV_TAG_STRUC_wmi_vdev_chan_hop_status_report_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_set_mapc_params_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mapc_cmn_params, - WMITLV_TAG_STRUC_wmi_mapc_cotdma_params, - WMITLV_TAG_STRUC_wmi_mapc_cosr_params, - WMITLV_TAG_STRUC_wmi_mapc_cobf_params, - WMITLV_TAG_STRUC_wmi_mapc_cortwt_params, - WMITLV_TAG_STRUC_wmi_lpi_scan_result_ind_fixed_param, - WMITLV_TAG_STRUC_wmi_lpi_ap_info_t, - WMITLV_TAG_STRUC_wmi_nan_disc_service_rsp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disc_match_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disc_service_req_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disc_cancel_service_req_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disc_service_req_terminated_event_fixed_param, - WMITLV_TAG_STRUC_wmi_set_modify_tx_plim_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_get_avg_tx_power_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_get_tx_power_calling_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_modify_tx_plim_event_fixed_param, - WMITLV_TAG_STRUC_wmi_avg_tx_power_event_fixed_param, - WMITLV_TAG_STRUC_wmi_avg_tx_power_region_per_antenna_chain, - WMITLV_TAG_STRUC_wmi_plimit_table_event_fixed_param, - WMITLV_TAG_STRUC_wmi_tx_power_per_antenna_chain, - WMITLV_TAG_STRUC_wmi_athdiag_read_write_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_athdiag_read_write_event_fixed_param, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -2219,62 +2037,6 @@ typedef enum { OP(WMI_MLO_LINK_RECONFIG_COMPLETE_CMDID) \ OP(WMI_SAWF_EZMESH_HOP_COUNT_CMDID) \ OP(WMI_VDEV_VBSS_CONFIG_CMDID) \ - OP(WMI_NDP_SET_LATENCY_TPUT_CMDID) \ - OP(WMI_MLO_LINK_TTLM_COMPLETE_CMDID) \ - OP(WMI_BPF_SET_SUPPORTED_OFFLOAD_BITMAP_CMDID) \ - OP(WMI_BPF_SET_APF_MODE_CMDID) \ - OP(WMI_ENERGY_MGMT_PCIE_CONFIG_CMDID) \ - OP(WMI_ENERGY_MGMT_PCIE_LPM_CMDID) \ - OP(WMI_ENERGY_MGMT_DCVS_CONFIG_CMDID) \ - OP(WMI_ENERGY_MGMT_EDPS_CONFIG_CMDID) \ - OP(WMI_ENERGY_MGMT_PUO_CONFIG_CMDID) \ - OP(WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID) \ - OP(WMI_PEER_TID_RATE_CUSTOM_CMDID) \ - OP(WMI_PEER_UHR_MODE_UPDATE_CMDID) \ - OP(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID) \ - OP(WMI_VDEV_GET_TPC_IE_POWER_CMDID) \ - OP(WMI_PEER_ASSOC_V2_CMDID) \ - OP(WMI_VDEV_TRAFFIC_MONITORING_CMDID) \ - OP(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID) \ - OP(WMI_WLAN_MODE_REQ_CMDID) \ - OP(WMI_NAN_ENABLE_CMDID) \ - OP(WMI_NAN_CONFIG_CMDID) \ - OP(WMI_NAN_DISABLE_CMDID) \ - OP(WMI_VDEV_UNIFIED_CONNECT_CMDID) \ - OP(WMI_VDEV_UNIFIED_DISCONNECT_CMDID) \ - OP(WMI_ROAM_SMD_CONFIG_CMDID) \ - OP(WMI_ROAM_SMD_START_STATUS_CMDID) \ - OP(WMI_VDEV_REPURPOSE_RESP_CMDID) \ - OP(WMI_IPA_RING_STATS_REQ_CMDID) \ - OP(WMI_VDEV_UHR_CU_CMDID) \ - OP(WMI_PDEV_UHR_CU_CMDID) \ - OP(WMI_PDEV_POWER_DATAPATH_STATS_CMDID) \ - OP(WMI_SMD_ROAM_CONFIG_CMDID) \ - OP(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID) \ - OP(WMI_SCAN_SUPPRESS_CMDID) \ - OP(WMI_GET_SCAN_STATS_CMDID) \ - OP(WMI_SOC_GET_CONC_INFO_CMDID) \ - OP(WMI_NAN_LOCAL_SCHEDULE_CMDID) \ - OP(WMI_NAN_PEER_SCHEDULE_CMDID) \ - OP(WMI_NAN_PEER_PARAMS_CMDID) \ - OP(WMI_ENERGY_MGMT_OEM_DATA_CMDID) \ - OP(WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID) \ - OP(WMI_TWT_ADD_CH_USAGE_CMDID) \ - OP(WMI_COEX_GET_POLICY_STATS_CMDID) \ - OP(WMI_PDEV_SET_CUMAC_CHIP_CMDID) \ - OP(WMI_PEER_UHR_OMP_CMDID) \ - OP(WMI_REQUEST_TDLS_STATS_CMDID) \ - OP(WMI_GET_CHIPSET_LOGGING_STATS_CMDID) \ - OP(WMI_RTT_PEER_MEAS_REQ_CMDID) \ - OP(WMI_RTT_PEER_MEAS_CANCEL_CMDID) \ - OP(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID) \ - OP(WMI_PEER_SET_MAPC_PARAMS_CMDID) \ - OP(WMI_NAN_DISC_SERVICE_REQ_CMDID) \ - OP(WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID) \ - OP(WMI_SET_MODIFY_TX_PLIM_CMDID) \ - OP(WMI_GET_AVG_TX_POWER_CMDID) \ - OP(WMI_GET_TX_POWER_CALLING_CMDID) \ - OP(WMI_ATHDIAG_READ_WRITE_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -2610,49 +2372,6 @@ typedef enum { OP(WMI_PDEV_WIFI_RADAR_CAPABILITIES_EVENTID) \ OP(WMI_VDEV_VBSS_CONFIG_EVENTID) \ OP(WMI_OPT_DP_DIAG_EVENTID) \ - OP(WMI_HW_BLACKLIST_CHAN_EVENTID) \ - OP(WMI_PDEV_SUSPEND_EVENTID) \ - OP(WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID) \ - OP(WMI_VDEV_TPC_IE_POWER_EVENTID) \ - OP(WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID) \ - OP(WMI_FW_READY_IND_EVENTID) \ - OP(WMI_WLAN_MODE_RESP_EVENTID) \ - OP(WMI_NAN_ENABLE_RSP_EVENTID) \ - OP(WMI_NAN_NEXT_DW_INFO_EVENTID) \ - OP(WMI_NAN_DISABLE_CNF_EVENTID) \ - OP(WMI_NAN_DISABLE_IND_EVENTID) \ - OP(WMI_CFR_CAPTURE_FILTER_RESP_EVENTID) \ - OP(WMI_VDEV_UNIFIED_CONNECT_EVENTID) \ - OP(WMI_VDEV_UNIFIED_DISCONNECT_EVENTID) \ - OP(WMI_IPA_RING_STATS_CONF_EVENTID) \ - OP(WMI_PDEV_UHR_CU_EVENTID) \ - OP(WMI_PDEV_POWER_DATAPATH_STATS_EVENTID) \ - OP(WMI_SMD_ROAM_CONFIG_EVENTID) \ - OP(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID) \ - OP(WMI_GET_SCAN_STATS_RESP_EVENTID) \ - OP(WMI_SOC_GET_CONC_INFO_RESP_EVENTID) \ - OP(WMI_NAN_LOCAL_SCHEDULE_CNF_EVENTID) \ - OP(WMI_NAN_PEER_SCHEDULE_CNF_EVENTID) \ - OP(WMI_NAN_PEER_PARAMS_CNF_EVENTID) \ - OP(WMI_ENERGY_MGMT_OEM_DATA_EVENTID) \ - OP(WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID) \ - OP(WMI_COEX_GET_POLICY_STATS_EVENTID) \ - OP(WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID) \ - OP(WMI_NDP_CHANNEL_INFO_EVENTID) \ - OP(WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID) \ - OP(WMI_TDLS_STATS_EVENTID) \ - OP(WMI_GET_CHIPSET_LOGGING_STATS_EVENTID) \ - OP(WMI_ANOMALY_REPORT_EVENTID) \ - OP(WMI_RTT_PEER_MEAS_REPORT_EVENTID) \ - OP(WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID) \ - OP(WMI_LPI_SCAN_RESULT_EVENTID_V2) \ - OP(WMI_NAN_DISC_SERVICE_RSP_EVENTID) \ - OP(WMI_NAN_DISC_MATCH_EVENTID) \ - OP(WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID) \ - OP(WMI_MODIFY_TX_PLIM_EVENTID) \ - OP(WMI_AVG_TX_POWER_EVENTID) \ - OP(WMI_PLIMIT_TABLE_EVENTID) \ - OP(WMI_ATHDIAG_READ_WRITE_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -2673,41 +2392,14 @@ WMITLV_CREATE_PARAM_STRUC(WMI_INIT_CMDID); #define WMITLV_TABLE_WMI_PEER_CREATE_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, mlo_params, WMITLV_SIZE_VAR) -/* NOTE: - * To maintain compatibility, any new TLV addition in WMI_PEER_CREATE_CMDID - * needs to also be included as a TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID and - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID. - * - * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_VDEV_START_REQUEST_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_UP_CMDID - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID substitutes for 4 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_INSTALL_KEY - */ + WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CREATE_CMDID); /* Peer delete Cmd */ #define WMITLV_TABLE_WMI_PEER_DELETE_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param, wmi_peer_delete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_delete_mlo_params, mlo_params, WMITLV_SIZE_VAR) -/* NOTE: - * Any new TLV addition in WMI_PEER_DELETE_CMDID needs to be included as - * TLV in WMI_VDEV_UNIFIED_DISCONNECT_CMDID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_DISCONNECT_CMDID substitutes for 3 disconnection related - * cmds: - * WMI_PEER_DELETE_CMDID, - * WMI_VDEV_STOP_CMDID, - * WMI_VDEV_DOWN_CMDID - */ + WMITLV_CREATE_PARAM_STRUC(WMI_PEER_DELETE_CMDID); /* Delete all peer Cmd */ @@ -3065,22 +2757,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_WMM_PARAMS_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_mlo_params, mlo_params, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_partner_link_params, partner_link_params, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, dbw_chan, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_smd_params, smd_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_uhr_config, uhr_config, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_npca_params, npca_params, WMITLV_SIZE_VAR) -/* NOTE: - * Any new TLV addition in WMI_VDEV_START_REQUEST_CMDID needs to be included as - * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_VDEV_START_REQUEST_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_UP_CMDID - */ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR) + WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_START_REQUEST_CMDID); /* Vdev restart request cmd */ @@ -3159,16 +2837,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_FD_TMPL_CMDID); #define WMITLV_TABLE_WMI_VDEV_INSTALL_KEY_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param, wmi_vdev_install_key_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, key_data, WMITLV_SIZE_VAR) -/* NOTE: - * To maintain compatibility, any new TLV added in WMI_VDEV_INSTALL_KEY_CMDID - * needs to be included as a TLV in WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID too. - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID substitutes for 4 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_INSTALL_KEY - */ + WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_INSTALL_KEY_CMDID); /* VDEV set LTF key seed Cmd */ @@ -3198,72 +2867,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, mlo_params, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_eht_rates, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, operating_mode_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, mgmt_mpduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, mgmt_msduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, hol_mdsuq_params, WMITLV_SIZE_VAR) -/* NOTE: - * No further TLVs can be added to this message; - * it is already at the target's WMI_MAX_NUM_TLVS limit (13). - * - * Note that the WMI_PEER_ASSOC_V2_CMDID (below) can support additional TLVs. - */ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_tid_to_link_map, WMITLV_SIZE_VAR) + WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID); -/* WMI_PEER_ASSOC_V2_CMD - version 2 of the PEER_ASSOC cmd, allowing more TLVs - * This cmd message mirrors the WMI_PEER_ASSOC_CMDID message, but has the - * capacity for extra TLVs beyond those in the WMI_PEER_ASSOC_CMDID definition. - * This message can only be used if the target advertises support for - * WMI_MAX_NUM_EXT_TLVS (via the WMI_SERVICE_EXT_TLV_SUPPORT flag). - */ -#define WMITLV_TABLE_WMI_PEER_ASSOC_V2_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_legacy_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_ht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_vht_rates, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_he_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_eht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, operating_mode_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, mgmt_mpduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, mgmt_msduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, hol_mdsuq_params, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, create_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, cfp_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_op_params, npca_op_params, WMITLV_SIZE_VAR) -/* NOTE: - * To maintain compatibility, any new TLV added in WMI_PEER_ASSOC_V2_CMDID - * needs to be also included as a TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID and - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID. - * - * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_VDEV_START_REQUEST_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_UP_CMDID - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID substitutes for 4 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_INSTALL_KEY - */ -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_V2_CMDID); - -#define WMITLV_TABLE_WMI_PEER_UHR_OMP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_uhr_omp_cmd_fixed_param, wmi_peer_uhr_omp_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_omp_npca_params, peer_omp_npca_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_omp_sta_dps_params, peer_omp_dps_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_UHR_OMP_CMDID); - /* Peer Set Rate Report Condition Cmd */ #define WMITLV_TABLE_WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_set_rate_report_condition_fixed_param, wmi_peer_set_rate_report_condition_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -3484,12 +3091,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_UNIFIED_LL_GET_STA_CMDID); WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_WLM_STATS_CMDID); -/* Get chipset debug log stats Cmd */ -#define WMITLV_TABLE_WMI_GET_CHIPSET_LOGGING_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_cmd_fixed_param, wmi_get_chipset_logging_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) - -WMITLV_CREATE_PARAM_STRUC(WMI_GET_CHIPSET_LOGGING_STATS_CMDID); - /* Network list offload config Cmd */ #define WMITLV_TABLE_WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nlo_config_cmd_fixed_param, wmi_nlo_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ @@ -3834,8 +3435,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_AP_PROFILE); /* Roam sync complete Cmd */ #define WMITLV_TABLE_WMI_ROAM_SYNCH_COMPLETE(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_synch_complete_fixed_param, wmi_roam_synch_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_response_tlv_param, vdev_repurpose_response_tlv, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_synch_complete_fixed_param, wmi_roam_synch_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_COMPLETE); @@ -3999,8 +3599,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param, wmi_vdev_create_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_txrx_streams, cfg_txrx_streams, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_create_mlo_params, mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_create_wfdr2_mode_params, wfdr2_mode, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_create_tbtt_count_down_offset_info, offset_info, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_create_wfdr2_mode_params, wfdr2_mode, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CREATE_CMDID); @@ -4012,51 +3611,21 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_CMDID); /* Vdev up Cmd */ #define WMITLV_TABLE_WMI_VDEV_UP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, wmi_vdev_up_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_co_located_chan_info, co_located_chan_info, WMITLV_SIZE_VAR) -/* NOTE: - * Any new TLV addition in WMI_VDEV_UP_CMDID needs to be included as - * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_VDEV_START_REQUEST_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_UP_CMDID - */ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, wmi_vdev_up_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UP_CMDID); /* Vdev stop cmd */ #define WMITLV_TABLE_WMI_VDEV_STOP_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stop_cmd_fixed_param, wmi_vdev_stop_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_stop_mlo_params, mlo_params, WMITLV_SIZE_VAR) -/* NOTE: - * Any new TLV addition in WMI_VDEV_STOP_CMDID needs to be included as - * TLV in WMI_VDEV_UNIFIED_DISCONNECT_CMDID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_DISCONNECT_CMDID substitutes for 3 disconnection related - * cmds: - * WMI_PEER_DELETE_CMDID, - * WMI_VDEV_STOP_CMDID, - * WMI_VDEV_DOWN_CMDID - */ + WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STOP_CMDID); /* Vdev down Cmd */ #define WMITLV_TABLE_WMI_VDEV_DOWN_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_down_cmd_fixed_param, wmi_vdev_down_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * Any new TLV addition in WMI_VDEV_STOP_CMDID needs to be included as - * TLV in WMI_VDEV_UNIFIED_DISCONNECT_CMDID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_DISCONNECT_CMDID substitutes for 3 disconnection related - * cmds: - * WMI_PEER_DELETE_CMDID, - * WMI_VDEV_STOP_CMDID, - * WMI_VDEV_DOWN_CMDID - */ + WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DOWN_CMDID); /* Vdev set param Cmd */ @@ -4074,8 +3643,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UPDATE_MAC_ADDR_CMDID); #define WMITLV_TABLE_WMI_VDEV_VBSS_CONFIG_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vbss_config_cmd_fixed_param, wmi_vdev_vbss_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_pn_info, vbss_peer_pn_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_sn_info, vbss_peer_sn_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_dyn_info, vbss_peer_dyn_info, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_sn_info, vbss_peer_sn_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_VBSS_CONFIG_CMDID); /* Pdev suspend Cmd */ @@ -4095,18 +3663,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_RESUME_CMDID); WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_UPDATE_REQUEST_CMDID); -/* suppress scan Cmd */ -#define WMITLV_TABLE_WMI_SCAN_SUPPRESS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_suppress_cmd_fixed_param, wmi_scan_suppress_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) - -WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_SUPPRESS_CMDID); - -/* get scan stats Cmd */ -#define WMITLV_TABLE_WMI_GET_SCAN_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_scan_stats_cmd_fixed_param, wmi_get_scan_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) - -WMITLV_CREATE_PARAM_STRUC(WMI_GET_SCAN_STATS_CMDID); - #define WMITLV_TABLE_WMI_SCAN_PROB_REQ_OUI_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_prob_req_oui_cmd_fixed_param, wmi_scan_prob_req_oui_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vendor_oui, vendor_oui, WMITLV_SIZE_VAR) @@ -4119,11 +3675,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_PROB_REQ_OUI_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID); -/* get concurrency info Cmd */ -#define WMITLV_TABLE_WMI_SOC_GET_CONC_INFO_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_get_conc_info_cmd_fixed_param, wmi_soc_get_conc_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_SOC_GET_CONC_INFO_CMDID); - #define WMITLV_TABLE_WMI_CHATTER_ADD_COALESCING_FILTER_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_STRUC_wmi_chatter_coalescing_add_filter_cmd_fixed_param, wmi_chatter_coalescing_add_filter_cmd_fixed_param, fixed_param,WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, chatter_pkt_coalescing_filter, coalescing_filter, WMITLV_SIZE_VAR) @@ -4429,20 +3980,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DSM_FILTER_CMDID); WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, non_tx_bssid, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_P2P_GO_DFS_AP_CONFIG_CMDID); -/* Configure roam SMD parameters */ -#define WMITLV_TABLE_WMI_ROAM_SMD_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_smd_config_cmd_fixed_param, wmi_roam_smd_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SMD_CONFIG_CMDID); - -/* SMD preparation completion status command */ -#define WMITLV_TABLE_WMI_ROAM_SMD_START_STATUS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_smd_start_status_cmd_fixed_param, wmi_roam_smd_start_status_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_response_tlv_param, vdev_repurpose_response_tlv, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, smd_transition_ie, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_prep_resp_status_list, status_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, kck, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SMD_START_STATUS_CMDID); - #define WMITLV_TABLE_WMI_ROAM_BLACKLIST_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_blacklist_event_fixed_param, wmi_roam_blacklist_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_blacklist_with_timeout_tlv_param, blacklist_with_timeout, WMITLV_SIZE_VAR) @@ -4459,22 +3996,15 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_PREAUTH_START_EVENTID); WMITLV_CREATE_PARAM_STRUC(WMI_LPI_RESULT_EVENTID); /* LPI Status Event */ -#define WMITLV_TABLE_WMI_LPI_STATUS_EVENTID(id,op,buf,len) \ +#define WMITLV_TABLE_WMI_LPI_STATUS_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_status_event_fixed_param, wmi_lpi_status_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_LPI_STATUS_EVENTID); /* LPI Handoff Event */ -#define WMITLV_TABLE_WMI_LPI_HANDOFF_EVENTID(id,op,buf,len) \ +#define WMITLV_TABLE_WMI_LPI_HANDOFF_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_handoff_event_fixed_param, wmi_lpi_handoff_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_LPI_HANDOFF_EVENTID); -/* LPI Scan Result Indication Event */ -#define WMITLV_TABLE_WMI_LPI_SCAN_RESULT_EVENTID_V2(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_scan_result_ind_fixed_param, wmi_lpi_scan_result_ind_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, freq_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_lpi_ap_info_t, ap_array, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_LPI_SCAN_RESULT_EVENTID_V2); - /* Thermal Manager Params*/ #define WMITLV_TABLE_WMI_THERMAL_MGMT_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_thermal_mgmt_cmd_fixed_param, wmi_thermal_mgmt_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -4505,132 +4035,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_oem_data_buffer, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_OEM_DATA_CMDID); -/* NAN Enable Command */ -#define WMITLV_TABLE_WMI_NAN_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_enable_cmd_fixed_param, wmi_nan_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_ctrl_config_param, nan_ctrl_config, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_disc_band_config_param, nan_disc_band_config, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_ENABLE_CMDID); - -/* NAN Config Command */ -#define WMITLV_TABLE_WMI_NAN_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_config_cmd_fixed_param, wmi_nan_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_ctrl_config_param, nan_ctrl_config, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_disc_band_config_param, nan_disc_band_config, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_availability_attributes_data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_CONFIG_CMDID); - -/* NAN Disable Command */ -#define WMITLV_TABLE_WMI_NAN_DISABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disable_cmd_fixed_param, wmi_nan_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISABLE_CMDID); - -/* NAN local Schedule Command */ -#define WMITLV_TABLE_WMI_NAN_LOCAL_SCHEDULE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_local_schedule_cmd_fixed_param, wmi_nan_local_schedule_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_schedule_chan_bitmap, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_channel, committed_channel_list, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_LOCAL_SCHEDULE_CMDID); - -/* NAN Peer Schedule Command */ -#define WMITLV_TABLE_WMI_NAN_PEER_SCHEDULE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cmd_fixed_param, wmi_nan_peer_schedule_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_schedule_chan_bitmap, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_channel, committed_channel_list, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_SCHEDULE_CMDID); - -/* NAN Peer Params Command */ -#define WMITLV_TABLE_WMI_NAN_PEER_PARAMS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_params_cmd_fixed_param, wmi_nan_peer_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_caps_ie_data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_PARAMS_CMDID); - -/** - * NAN Discovery Service Request Command - * (NL80211_CMD_ADD_NAN_FUNCTION equivalent) - * - * Carries all parameters needed to register a NAN Publish, Subscribe, or - * Follow-up function with the firmware in offload mode. - * - * TLV layout (in order): - * - * [0] wmi_nan_disc_service_req_cmd_fixed_param fixed_param - * All fixed scalar fields: vdev_id, service_req_type, instance_id, ttl, - * publish_type, followup_instance_id, followup_requestor_id, - * followup_dest, sdea_ctrl, pairing_bootstrap_methods, srf_bf_idx, - * srf_include, service_req_flags, and all _len / _num count fields. - * - * [1] A_UINT8 service_id[] - * 6-byte NAN Service ID (SHA-256 of service name, first 6 bytes), - * zero-padded to 8 bytes for 4-byte WMI alignment. - * Maps to: NL80211_ATTR_NAN_FUNC_SERVICE_ID / cfg80211_nan_func.service_id - * - * [2] A_UINT8 serv_spec_info[] - * Service Specific Info — opaque application payload, max 255 bytes. - * Valid byte count given by fixed_param.serv_spec_info_len. - * Maps to: NL80211_ATTR_NAN_FUNC_SERVICE_INFO / - * cfg80211_nan_func.serv_spec_info - * - * [3] A_UINT8 srf_bf[] - * SRF (Service Range Filter) Bloom filter data. - * Valid byte count given by fixed_param.srf_bf_len. - * Maps to: NL80211_ATTR_NAN_FUNC_SRF_BF / cfg80211_nan_func.srf_bf - * - * [4] wmi_mac_addr srf_macs[] - * SRF MAC address filter list (WMITLV_TAG_ARRAY_FIXED_STRUC). - * Entry count given by fixed_param.num_srf_macs. - * Maps to: NL80211_ATTR_NAN_FUNC_SRF_MAC_ADDRS / - * cfg80211_nan_func.srf_macs - * - * [5] A_UINT8 rx_match_filter[] - * RX match filter byte stream (ieee80211 protocol order). - * Valid byte count given by fixed_param.rx_match_filter_len. - * Maps to: NL80211_ATTR_NAN_FUNC_RX_MATCH_FILTER / - * cfg80211_nan_func.rx_filters - * - * [6] A_UINT8 tx_match_filter[] - * TX match filter byte stream (ieee80211 protocol order). - * Valid byte count given by fixed_param.tx_match_filter_len. - * Maps to: NL80211_ATTR_NAN_FUNC_TX_MATCH_FILTER / - * cfg80211_nan_func.tx_filters - * - * [7] A_UINT32 cipher_suites[] - * Array of supported NAN cipher suite IDs (CSIDs). - * Entry count given by fixed_param.num_cipher_suites. - * Maps to: NL80211_ATTR_NAN_FUNC_CIPHER_SUITES / - * cfg80211_nan_func.cipher_suites - * - * [8] A_UINT8 nd_pmk[] - * NAN Data Path PMK, exactly 32 bytes when present. - * Present and valid only when - * WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_ND_PMK_VALID( - * fixed_param.service_req_flags) == 1; - * zero-length TLV otherwise. - * Maps to: NL80211_ATTR_NAN_FUNC_ND_PMK / cfg80211_nan_func.nd_pmk - */ -#define WMITLV_TABLE_WMI_NAN_DISC_SERVICE_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_service_req_cmd_fixed_param, wmi_nan_disc_service_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, service_id, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, serv_spec_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, srf_bf, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, srf_macs, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, rx_match_filter, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, tx_match_filter, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, cipher_suites, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nd_pmk, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, extra_nan_attrs, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_SERVICE_REQ_CMDID); - -/** NAN Discovery Delete Function Cmd - * - * TLV (tag length value) parameters follow the - * wmi_nan_disc_cancel_service_req_cmd_fixed_param structure. The TLV's are: - * wmi_nan_disc_cancel_service_req_cmd_fixed_param fixed_param; - */ -#define WMITLV_TABLE_WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_cancel_service_req_cmd_fixed_param, wmi_nan_disc_cancel_service_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID); - /* NAN Data Get Capabilities Cmd */ #define WMITLV_TABLE_WMI_NDI_GET_CAP_REQ_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndi_get_cap_req_fixed_param, wmi_ndi_get_cap_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) @@ -4695,11 +4099,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NDP_END_REQ_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_cmd_param, wmi_ndp_cmd_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_NDP_CMDID); -/* NDP Set Latency Tput Cmd */ -#define WMITLV_TABLE_WMI_NDP_SET_LATENCY_TPUT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_set_latency_tput_fixed_param, wmi_ndp_set_latency_tput_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NDP_SET_LATENCY_TPUT_CMDID); - /* RCPI Info Request Cmd */ #define WMITLV_TABLE_WMI_REQUEST_RCPI_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_rcpi_cmd_fixed_param, wmi_request_rcpi_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -5104,8 +4503,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_BPF_GET_VDEV_WORK_MEMORY_CMDID); /* Enable/Disable Smart Antenna */ #define WMITLV_TABLE_WMI_PDEV_SMART_ANT_ENABLE_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_smart_ant_enable_cmd_fixed_param, wmi_pdev_smart_ant_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_smart_ant_gpio_handle, gpio_handle, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, pdev_smart_ant_param, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_smart_ant_gpio_handle, gpio_handle, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SMART_ANT_ENABLE_CMDID); /* Set Smart Antenna RX antenna */ @@ -5353,14 +4751,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MNT_FILTER_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_chip_power_stats_cmd_fixed_param, wmi_pdev_get_chip_power_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_CHIP_POWER_STATS_CMDID); -/* - * WMI command for setting the pdev power stats enable/disable - * and getting the pdev power stats - */ -#define WMITLV_TABLE_WMI_PDEV_POWER_DATAPATH_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_cmd_fixed_param, wmi_pdev_power_datapath_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_DATAPATH_STATS_CMDID); - /* WLAN GET mws conflict */ #define WMITLV_TABLE_WMI_VDEV_GET_MWS_COEX_INFO_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_info_cmd_fixed_param, wmi_vdev_get_mws_coex_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -5409,11 +4799,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_CTRL_PATH_STATS_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, mac_addr_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_HALPHY_CTRL_PATH_STATS_CMDID); -/* Request TDLS Stats cmd enabling the monitoring of TDLS stats */ -#define WMITLV_TABLE_WMI_REQUEST_TDLS_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_tdls_stats_cmd_fixed_param, wmi_request_tdls_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_TDLS_STATS_CMDID); - /* Host sets the current country code */ #define WMITLV_TABLE_WMI_SET_CURRENT_COUNTRY_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_current_country_cmd_fixed_param, wmi_set_current_country_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -5466,8 +4851,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MESH_RX_FILTER_ENABLE_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, preferred_tx_stream_list, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, preferred_rx_stream_list, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, dbw_chan, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_npca_params, npca_params, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID); #define WMITLV_TABLE_WMI_PDEV_UPDATE_PKT_ROUTING_CMDID(id,op,buf,len) \ @@ -5604,12 +4988,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_RUNTIME_DPD_RECAL_CMDID); WMITLV_CREATE_PARAM_STRUC(WMI_GET_TPC_POWER_CMDID); -/** Get TPC IE TX power value */ -#define WMITLV_TABLE_WMI_VDEV_GET_TPC_IE_POWER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_tpc_ie_power_cmd_fixed_param, wmi_vdev_get_tpc_ie_power_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) - -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_TPC_IE_POWER_CMDID); - /* TWT enable cmd */ #define WMITLV_TABLE_WMI_TWT_ENABLE_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_twt_enable_cmd_fixed_param, wmi_twt_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -5703,12 +5081,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CHAN_WIDTH_SWITCH_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_list, peer_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_BULK_SET_CMDID); -/* Multi Peer UHR Mode Update command */ -#define WMITLV_TABLE_WMI_PEER_UHR_MODE_UPDATE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_uhr_mode_update_cmd_fixed_param, wmi_peer_uhr_mode_update_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_UHR_MODE_UPDATE_CMDID); - /* OBSS_PD Spatial_Reuse Set Default OBSS Thresholds */ #define WMITLV_TABLE_WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param, wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -5825,8 +5197,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_AUDIO_AGGR_GET_SCHED_METHOD_CMDID); /* CFR Capture Filter cmd */ #define WMITLV_TABLE_WMI_CFR_CAPTURE_FILTER_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_cfr_capture_filter_cmd_fixed_param, wmi_cfr_capture_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cfr_filter_group_config, filter_group_config, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cfr_capture_fix_agc_gain_config, fix_agc_gain_config, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cfr_filter_group_config, filter_group_config, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CFR_CAPTURE_FILTER_CMDID); /* VLAN config */ @@ -5906,8 +5277,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SIMULATION_TEST_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_csa, wfa_config_csa, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ocv, wfa_config_ocv, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_saquery, wfa_config_saquery, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ofdma, wfa_config_ofdma, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ml, wfa_config_ml, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ofdma, wfa_config_ofdma, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_WFA_CONFIG_CMDID); /* SRG OBSS color Enable Bitmap */ @@ -6014,11 +5384,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_RECONFIG_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_complete_fixed_param, wmi_mlo_link_reconfig_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_RECONFIG_COMPLETE_CMDID); -/** WMI cmd to notify fw completion of link TTLM negotiation */ -#define WMITLV_TABLE_WMI_MLO_LINK_TTLM_COMPLETE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_ttlm_complete_fixed_param, wmi_mlo_link_ttlm_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_TTLM_COMPLETE_CMDID); - /* Mcast ipv4 address filter list cmd */ #define WMITLV_TABLE_WMI_VDEV_IGMP_OFFLOAD_CMDID(id,op,buf,len) \ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_igmp_offload_fixed_param, wmi_igmp_offload_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ @@ -6376,308 +5741,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_BOOST_MEM_ADDR_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_scan_cache_result_cmd_fixed_param, wmi_get_scan_cache_result_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GET_SCAN_CACHE_RESULT_CMDID); -#define WMITLV_TABLE_WMI_SET_MODIFY_TX_PLIM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_modify_tx_plim_cmd_fixed_param, wmi_set_modify_tx_plim_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_SET_MODIFY_TX_PLIM_CMDID); - -#define WMITLV_TABLE_WMI_GET_AVG_TX_POWER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_avg_tx_power_cmd_fixed_param, wmi_get_avg_tx_power_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_GET_AVG_TX_POWER_CMDID); - -#define WMITLV_TABLE_WMI_GET_TX_POWER_CALLING_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_tx_power_calling_cmd_fixed_param, wmi_get_tx_power_calling_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_GET_TX_POWER_CALLING_CMDID); - #define WMITLV_TABLE_WMI_SAWF_EZMESH_HOP_COUNT_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sawf_ezmesh_hop_count_cmd_fixed_param, wmi_sawf_ezmesh_hop_count_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SAWF_EZMESH_HOP_COUNT_CMDID); -#define WMITLV_TABLE_WMI_BPF_SET_SUPPORTED_OFFLOAD_BITMAP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bpf_set_supported_offload_bitmap_cmd_fixed_param, wmi_bpf_set_supported_offload_bitmap_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_BPF_SET_SUPPORTED_OFFLOAD_BITMAP_CMDID); - -#define WMITLV_TABLE_WMI_BPF_SET_APF_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bpf_set_apf_mode_cmd_fixed_param, wmi_bpf_set_apf_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_BPF_SET_APF_MODE_CMDID); - -/* WMI cmd used to control PCIe config */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_PCIE_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_pcie_config_cmd_fixed_param, wmi_energy_mgmt_pcie_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_PCIE_CONFIG_CMDID); - -/* WMI cmd used for PCIe LPM config */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_PCIE_LPM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_pcie_lpm_cmd_fixed_param, wmi_energy_mgmt_pcie_lpm_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_PCIE_LPM_CMDID); - -/* WMI cmd used to control DCVS config */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_DCVS_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_dcvs_config_cmd_fixed_param, wmi_energy_mgmt_dcvs_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_DCVS_CONFIG_CMDID); - -/* WMI cmd used to control Dynamic AP Power Save config */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_EDPS_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_edps_config_cmd_fixed_param, wmi_energy_mgmt_edps_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_EDPS_CONFIG_CMDID); - -/* WMI cmd used to control Scheduled AP Power Save config */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_PUO_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_puo_config_cmd_fixed_param, wmi_energy_mgmt_puo_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_PUO_CONFIG_CMDID); - -/* WMI cmd used to control Un-scheduled AP Power Save config */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_eco_mode_config_cmd_fixed_param, wmi_energy_mgmt_eco_mode_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID); - -/* peer tid rate customization cmd */ -#define WMITLV_TABLE_WMI_PEER_TID_RATE_CUSTOM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tid_rate_custom_cmd_fixed_param, wmi_peer_tid_rate_custom_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, rate_code, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TID_RATE_CUSTOM_CMDID); - -/* pdev per-vdev queue depth report request cmd */ -#define WMITLV_TABLE_WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param, wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID); - -/* vdev traffic monitoring request cmd */ -#define WMITLV_TABLE_WMI_VDEV_TRAFFIC_MONITORING_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param, wmi_vdev_traffic_monitoring_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_TRAFFIC_MONITORING_CMDID); - -/* WMI command to control Dynamic Power Save - AP Assisting role config */ -#define WMITLV_TABLE_WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID); - -/* WMI cmd to specify the driver's mode of operation */ -#define WMITLV_TABLE_WMI_WLAN_MODE_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_mode_req_cmd_fixed_param, wmi_wlan_mode_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_REQ_CMDID); - - -/* WMI command for unified connect cmd */ -#define WMITLV_TABLE_WMI_VDEV_UNIFIED_CONNECT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_unified_connect_cmd_fixed_param, wmi_vdev_unified_connect_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, peer_create_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_create_mlo_params, WMITLV_SIZE_VAR) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_request_cmd_fixed_param, wmi_vdev_start_request_cmd_fixed_param, vdev_start_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, vdev_start_chan, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_descriptor, vdev_start_noa_descriptors, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_mlo_params, vdev_start_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_partner_link_params, vdev_start_partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, vdev_start_dbw_chan, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, vdev_start_dbw_chan_info, WMITLV_SIZE_VAR) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, peer_assoc_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_peer_legacy_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_peer_ht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_assoc_peer_vht_rates, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_assoc_peer_he_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, peer_assoc_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_assoc_peer_eht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, peer_assoc_partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_assoc_peer_tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, peer_assoc_operating_mode_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_mgmt_mpduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_mgmt_msduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_hol_mdsuq_params, WMITLV_SIZE_VAR) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, peer_assoc_v2_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_v2_peer_legacy_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_v2_peer_ht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_assoc_v2_peer_vht_rates, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_assoc_v2_peer_he_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, peer_assoc_v2_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_assoc_v2_peer_eht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, peer_assoc_v2_partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_assoc_v2_peer_tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, peer_assoc_v2_operating_mode_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_v2_mgmt_mpduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_v2_mgmt_msduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_v2_hol_mdsuq_params, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_assoc_v2_peer_npca_cap_params, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_assoc_v2_create_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, peer_assoc_v2_cfp_params, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, wmi_vdev_up_cmd_fixed_param, vdev_up_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_co_located_chan_info, vdev_up_co_located_chan_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_smd_params, vdev_smd_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, peer_assoc_v2_smd_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_op_params, npca_op_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_CMDID); - -/* WMI command for unified disconnect cmd */ -#define WMITLV_TABLE_WMI_VDEV_UNIFIED_DISCONNECT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_cmd_fixed_param, wmi_vdev_unified_disconnect_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param, wmi_peer_delete_cmd_fixed_param, peer_delete_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_delete_mlo_params, peer_delete_mlo_params, WMITLV_SIZE_VAR) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stop_cmd_fixed_param, wmi_vdev_stop_cmd_fixed_param, vdev_stop_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_stop_mlo_params, vdev_stop_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_down_cmd_fixed_param, wmi_vdev_down_cmd_fixed_param, vdev_down_fixed_param, WMITLV_SIZE_FIX) - -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_DISCONNECT_CMDID); - -/** WMI cmd for response of wmi_vdev_repurpose_request_tlv_param */ -#define WMITLV_TABLE_WMI_VDEV_REPURPOSE_RESP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_repurpose_resp_cmd_fixed_param, wmi_vdev_repurpose_resp_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_response_tlv_param, vdev_repurpose_response_tlv, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_REPURPOSE_RESP_CMDID); - -/* Get IPA ring stats */ -#define WMITLV_TABLE_WMI_IPA_RING_STATS_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ipa_ring_stats_req_cmd_fixed_param, wmi_ipa_ring_stats_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_IPA_RING_STATS_REQ_CMDID); - -#define WMITLV_TABLE_WMI_VDEV_UHR_CU_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_cmd_fixed_param, wmi_vdev_uhr_cu_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_dps_params, wmi_uhr_ap_dps_params, dps_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_npca_params, wmi_uhr_ap_npca_params, npca_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_duo_params, wmi_uhr_ap_duo_params, duo_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_pedca_params, wmi_uhr_ap_pedca_params, pedca_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_dbe_params, wmi_uhr_ap_dbe_params, dbe_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_puo_params, wmi_uhr_ap_puo_params, puo_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_elr_reception_params, wmi_uhr_ap_elr_reception_params, elr_reception_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_mode_tuple_enable_disable_update_params, mode_tup_enable_disable_update_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UHR_CU_CMDID); - -#define WMITLV_TABLE_WMI_PDEV_UHR_CU_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_cmd_fixed_param, wmi_pdev_uhr_cu_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_dps_params, dps_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_npca_params, npca_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_duo_params, duo_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_pedca_params, pedca_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_dbe_params, dbe_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_puo_params, puo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_elr_reception_params, elr_reception_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_mode_tuple_enable_disable_update_params, mode_tup_enable_disable_update_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UHR_CU_CMDID); - -/* WMI command for unified SMD PEER SETUP cmd */ -#define WMITLV_TABLE_WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_cmd_fixed_param, wmi_smd_roam_peer_unified_setup_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_smd_roam_peer_tid_info, smd_roam_peer_tid_info, WMITLV_SIZE_VAR) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, peer_create_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_create_mlo_params, WMITLV_SIZE_VAR) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, peer_assoc_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_peer_legacy_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_peer_ht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_assoc_peer_vht_rates, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_assoc_peer_he_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, peer_assoc_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_assoc_peer_eht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, peer_assoc_partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_assoc_peer_tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, peer_assoc_operating_mode_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_mgmt_mpduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_mgmt_msduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_hol_mdsuq_params, WMITLV_SIZE_VAR) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, peer_assoc_v2_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_v2_peer_legacy_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_v2_peer_ht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_assoc_v2_peer_vht_rates, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_assoc_v2_peer_he_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, peer_assoc_v2_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_assoc_v2_peer_eht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, peer_assoc_v2_partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_assoc_v2_peer_tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, peer_assoc_v2_operating_mode_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_v2_mgmt_mpduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_v2_mgmt_msduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_v2_hol_mdsuq_params, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_assoc_v2_peer_npca_cap_params, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_assoc_v2_create_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, peer_assoc_v2_cfp_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, peer_assoc_v2_smd_params, WMITLV_SIZE_FIX) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param, wmi_vdev_install_key_cmd_fixed_param, key_install_fixed_param, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, key_data, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_op_params, npca_op_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID); - -/* WMI command for unified SMD Config cmd */ -#define WMITLV_TABLE_WMI_SMD_ROAM_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_smd_roam_config_cmd_fixed_param, wmi_smd_roam_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_smd_roam_peer_tid_info, smd_roam_peer_tid_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_CONFIG_CMDID); - -/* WMI commad to config MAPC params used for co-ordinated AP features in 11bn */ -#define WMITLV_TABLE_WMI_PEER_SET_MAPC_PARAMS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_set_mapc_params_cmd_fixed_param, wmi_peer_set_mapc_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - /*--- Common MAPC params ---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cmn_params, mapc_cmn_params, WMITLV_SIZE_VAR) \ - /*--- Co-TDMA scheme params ---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cotdma_params, cotdma_params, WMITLV_SIZE_VAR) \ - /*--- Co-SR scheme params (future) ---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cosr_params, cosr_params, WMITLV_SIZE_VAR) \ - /*--- Co-BF scheme params (future) ---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cobf_params, cobf_params, WMITLV_SIZE_VAR) \ - /*--- Co-rTWT scheme params (future) ---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cortwt_params, cortwt_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SET_MAPC_PARAMS_CMDID); - -/* WMI Command for Energy management OEM cmd data */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_OEM_DATA_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_fixed_param, wmi_energy_mgmt_oem_data_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_OEM_DATA_CMDID); - -#define WMITLV_TABLE_WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_channel_hopping_schedule_fixed_param, wmi_vdev_channel_hopping_schedule_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) /* DEPRECATED - POPULATE WITH ZERO ELEMS */ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel_hopping_channel_params, channel_param_list, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID); - -/* WMI Command for start ch usage session */ -#define WMITLV_TABLE_WMI_TWT_ADD_CH_USAGE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ch_usage_add_dialog_cmd_fixed_param, wmi_ch_usage_add_dialog_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_TWT_ADD_CH_USAGE_CMDID); - -/* WMI Command to request CoEx Policy Stats data */ -#define WMITLV_TABLE_WMI_COEX_GET_POLICY_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_policy_stats_cmd_fixed_param, wmi_coex_policy_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_COEX_GET_POLICY_STATS_CMDID); - -/* WMI command to set CUMAC chip ID cmd */ -#define WMITLV_TABLE_WMI_PDEV_SET_CUMAC_CHIP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_cmd_fixed_param, wmi_pdev_set_cumac_chip_id_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_CUMAC_CHIP_CMDID); - -/* RTT Peer measurement start request */ -#define WMITLV_TABLE_WMI_RTT_PEER_MEAS_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_cmd_fixed_param, wmi_rtt_peer_meas_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_peer_meas_req_peer_info, peer_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_REQ_CMDID); - -/* RTT Peer measurement cancel request */ -#define WMITLV_TABLE_WMI_RTT_PEER_MEAS_CANCEL_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_peer_meas_cancel_meas_cmd_fix_param, wmi_rtt_peer_meas_cancel_meas_cmd_fix_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_CANCEL_CMDID); - -#define WMITLV_TABLE_WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_chan_hop_status_report_cmd_fixed_param, wmi_vdev_get_chan_hop_status_report_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID); - -/* Athdiag read/write command: fixed_param + optional write data TLV */ -#define WMITLV_TABLE_WMI_ATHDIAG_READ_WRITE_CMDID(id, op, buf, len) \ - WMITLV_ELEM(id, op, buf, len, \ - WMITLV_TAG_STRUC_wmi_athdiag_read_write_cmd_fixed_param, \ - wmi_athdiag_read_write_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id, op, buf, len, \ - WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_ATHDIAG_READ_WRITE_CMDID); - /************************** TLV definitions of WMI events *******************************/ @@ -6720,7 +5787,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID); /* SERVICE_READY_EXT2 event */ #define WMITLV_TABLE_WMI_SERVICE_READY_EXT2_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param, wmi_service_ready_ext2_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param, wmi_service_ready_ext2_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_DMA_RING_CAPABILITIES, dma_ring_caps, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_spectral_bin_scaling_params, wmi_bin_scaling_params, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_MAC_PHY_CAPABILITIES_EXT, mac_phy_caps, WMITLV_SIZE_VAR) \ @@ -6741,10 +5808,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_POWER_BOOST_CAPABILITIES, power_boost_capabilities, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES, rssi_accuracy_improvement_capabilities, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_ltf_length_capabilities, wr_ltf_caps, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_chain_capabilities, wr_chain_caps, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_MAC_PHY_CAPABILITIES_EXT2, mac_phy_caps2, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_shared_mem_model_tbtt_count_down_config, shared_mem_model_tbtt_count_down_config, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_peer_meas_capabilities, rtt_peer_meas_caps, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_chain_capabilities, wr_chain_caps, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID); #define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \ @@ -6928,30 +5992,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_QOS_NULL_FRAME_TX_COMPLETION_EVENTID); /* VDEV Start response Event */ #define WMITLV_TABLE_WMI_VDEV_START_RESP_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_response_event_fixed_param, wmi_vdev_start_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * Any new TLV addition in WMI_VDEV_START_RESP_EVENTID needs to be included - * as TLV in WMI_VDEV_UNIFIED_CONNECT_EVENTID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_CONNECT_EVENTID substitutes for 3 connection related - * events: - * WMI_PEER_CREATE_CONF_EVENTID, - * WMI_VDEV_START_RESP_EVENTID, - * WMI_PEER_ASSOC_CONF_EVENTID - */ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_START_RESP_EVENTID); /* VDEV Stopped Event */ #define WMITLV_TABLE_WMI_VDEV_STOPPED_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stopped_event_fixed_param, wmi_vdev_stopped_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * Any new TLV addition in WMI_VDEV_STOPPED_EVENTID needs to be included as - * TLV in WMI_VDEV_UNIFIED_DISCONNECT_EVENTID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_DISCONNECT_EVENTID substitutes for 2 disconnection related - * events: - * WMI_PEER_DELETE_RESP_EVENTID, - * WMI_VDEV_STOPPED_EVENTID - */ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STOPPED_EVENTID); /* VDEV delete response Event */ @@ -6962,17 +6007,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_RESP_EVENTID); /* VDEV Install Key Complete Event */ #define WMITLV_TABLE_WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param, wmi_vdev_install_key_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * To maintain compatibility, any new TLV added in - * WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID needs to also be included as a TLV in - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID. - * - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID substitutes for - * 3 connection related events: - * WMI_PEER_CREATE_CONF_EVENTID, - * WMI_PEER_ASSOC_CONF_EVENTID, - * WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID - */ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID); /* VDEV disconnect Event */ @@ -7058,10 +6092,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_AGGR_STATE_TRIG_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, deauth_disassoc_frame, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_hw_mode_transition_event_fixed_param, hw_mode_transition_fixed_param, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_bss_info_param, bss_info_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_partner_link_param, partner_link_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_request_tlv_param, vdev_repurpose_request_tlv, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, smd_transition_ie, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_bss_info_param, bss_info_param, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID); /* Roam Synch Event */ @@ -7080,9 +6111,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_pmk_cache_synch_tlv_param, roam_pmk_cache_synch_info, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_ml_setup_links_param, setup_links_param, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_ml_key_material_param, ml_key_material, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_band_to_mac, mac_freq_mapping, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_request_tlv_param, vdev_repurpose_request_tlv, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, kde_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_band_to_mac, mac_freq_mapping, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_EVENTID); /* Roam Synch key Event */ @@ -7336,9 +6365,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_HOST_SWFDA_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pmf_bcn_protect_stats, pmf_bcn_protect_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_extd_stats, vdev_extd_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_extd_stats, pdev_extd_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_telemetry_stats, pdev_telemetry_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_recv_bcn_stats, recv_bcn_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_coex_stats, coex_stats, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_telemetry_stats, pdev_telemetry_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_UPDATE_STATS_EVENTID); /* Update PN response Event */ @@ -7381,9 +6408,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_link_stats, iface_link_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wmm_ac_stats, ac, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_offload_stats, iface_offload_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_powersave_stats, iface_powersave_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_ipi_stats, iface_ipi_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, snr_histogram, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_powersave_stats, iface_powersave_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_IFACE_LINK_STATS_EVENTID); @@ -7592,95 +6617,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_STARTED_CLUSTER_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_joined_cluster_event_fixed_param, wmi_nan_joined_cluster_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_JOINED_CLUSTER_EVENTID); -/* NAN Enable Response Event */ -#define WMITLV_TABLE_WMI_NAN_ENABLE_RSP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_enable_rsp_event_fixed_param, wmi_nan_enable_rsp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_ENABLE_RSP_EVENTID); - -/** NAN Discovery Service Response Event - * - * TLV (tag length value) parameters follow the - * wmi_nan_disc_service_rsp_event_fixed_param structure. The TLV's are: - * wmi_nan_disc_service_rsp_event_fixed_param fixed_param; - */ -#define WMITLV_TABLE_WMI_NAN_DISC_SERVICE_RSP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_service_rsp_event_fixed_param, wmi_nan_disc_service_rsp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_SERVICE_RSP_EVENTID); - -/** NAN Discovery Match Event (NL80211_CMD_NAN_MATCH equivalent) - * - * Unified event covering subscriber match, publisher replied, and follow-up - * received scenarios, discriminated by the type field in fixed_param. - * - * TLV (tag length value) parameters follow the - * wmi_nan_disc_match_event_fixed_param structure. The TLV's are: - * wmi_mac_addr peer_addr[]; - * A_UINT8 service_id[]; - * A_UINT8 serv_spec_info[]; - * A_UINT32 cipher_suites[]; - * A_UINT8 scid[]; - * A_UINT8 extra_info[]; - * A_UINT8 ies[]; - */ -#define WMITLV_TABLE_WMI_NAN_DISC_MATCH_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_match_event_fixed_param, wmi_nan_disc_match_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_addr, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, service_id, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, serv_spec_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, cipher_suites, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, scid, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, extra_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ies, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_MATCH_EVENTID); - -/** NAN Discovery Service Request Terminated Event - * - * TLV (tag length value) parameters follow the - * wmi_nan_disc_service_req_terminated_event_fixed_param structure. The TLV's are: - * wmi_nan_disc_service_req_terminated_event_fixed_param fixed_param; - */ -#define WMITLV_TABLE_WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_service_req_terminated_event_fixed_param, wmi_nan_disc_service_req_terminated_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID); - -/* NAN Next DW Info Event */ -#define WMITLV_TABLE_WMI_NAN_NEXT_DW_INFO_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_next_dw_info_fixed_param, wmi_nan_next_dw_info_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_NEXT_DW_INFO_EVENTID); - -/* NAN Disable Confirm Event */ -#define WMITLV_TABLE_WMI_NAN_DISABLE_CNF_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disable_cnf_fixed_param, wmi_nan_disable_cnf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISABLE_CNF_EVENTID); - -/* NAN Disable Indication Event */ -#define WMITLV_TABLE_WMI_NAN_DISABLE_IND_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disable_ind_fixed_param, wmi_nan_disable_ind_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISABLE_IND_EVENTID); - -/* NAN Local Schedule Confirm Event */ -#define WMITLV_TABLE_WMI_NAN_LOCAL_SCHEDULE_CNF_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_local_schedule_cnf_event_fixed_param, wmi_nan_local_schedule_cnf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_LOCAL_SCHEDULE_CNF_EVENTID); - -/* NAN Peer Schedule Confirm Event */ -#define WMITLV_TABLE_WMI_NAN_PEER_SCHEDULE_CNF_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cnf_event_fixed_param, wmi_nan_peer_schedule_cnf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_SCHEDULE_CNF_EVENTID); - -/* NAN Peer Params Confirm Event */ -#define WMITLV_TABLE_WMI_NAN_PEER_PARAMS_CNF_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_params_cnf_event_fixed_param, wmi_nan_peer_params_cnf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_PARAMS_CNF_EVENTID); - -/* NDP Channel Info Event */ -#define WMITLV_TABLE_WMI_NDP_CHANNEL_INFO_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_channel_info_event_fixed_param, wmi_ndp_channel_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, channel_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, nss_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ndp_channel_info, channel_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NDP_CHANNEL_INFO_EVENTID); - /* Coex report antenna isolation event */ #define WMITLV_TABLE_WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_report_isolation_event_fixed_param, wmi_coex_report_isolation_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -7823,15 +6759,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATE_EVENTID); /* peer delete response Event */ #define WMITLV_TABLE_WMI_PEER_DELETE_RESP_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param, wmi_peer_delete_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * Any new TLV addition in WMI_PEER_DELETE_RESP_EVENTID needs to be included as - * TLV in WMI_VDEV_UNIFIED_DISCONNECT_EVENTID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_DISCONNECT_EVENTID substitutes for 2 disconnection related - * events: - * WMI_PEER_DELETE_RESP_EVENTID, - * WMI_VDEV_STOPPED_EVENTID - */ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_DELETE_RESP_EVENTID); /* delete all peer response Event */ @@ -7842,43 +6769,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_ALL_PEER_RESP_EVENTID); /* peer assoc conf Event */ #define WMITLV_TABLE_WMI_PEER_ASSOC_CONF_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * To maintain compatibility, any new TLV added in WMI_PEER_ASSOC_CONF_EVENTID - * needs to also be included as a TLV in WMI_VDEV_UNIFIED_CONNECT_EVENTID and - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID. - * - * WMI_VDEV_UNIFIED_CONNECT_EVENTID substitutes for 3 connection related - * events: - * WMI_PEER_CREATE_CONF_EVENTID, - * WMI_VDEV_START_RESP_EVENTID, - * WMI_PEER_ASSOC_CONF_EVENTID - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID substitutes for - * 3 connection related events: - * WMI_PEER_CREATE_CONF_EVENTID, - * WMI_PEER_ASSOC_CONF_EVENTID, - * WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID - */ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CONF_EVENTID); /* peer create conf Event */ #define WMITLV_TABLE_WMI_PEER_CREATE_CONF_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_conf_event_fixed_param, wmi_peer_create_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * To maintain compatibility, any new TLV added in WMI_PEER_CREATE_CONF_EVENTID - * needs to also be included as a TLV in WMI_VDEV_UNIFIED_CONNECT_EVENTID and - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID. - * - * WMI_VDEV_UNIFIED_CONNECT_EVENTID substitutes for 3 connection related - * events: - * WMI_PEER_CREATE_CONF_EVENTID, - * WMI_VDEV_START_RESP_EVENTID, - * WMI_PEER_ASSOC_CONF_EVENTID - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID substitutes for - * 3 connection related events: - * WMI_PEER_CREATE_CONF_EVENTID, - * WMI_PEER_ASSOC_CONF_EVENTID, - * WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID - */ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CREATE_CONF_EVENTID); /* D0-WOW Disable Ack event */ @@ -7906,11 +6801,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MDNS_STATS_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_resume_event_fixed_param, wmi_pdev_resume_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_RESUME_EVENTID); -/* pdev suspend event */ -#define WMITLV_TABLE_WMI_PDEV_SUSPEND_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_suspend_event_fixed_param, wmi_pdev_suspend_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SUSPEND_EVENTID); - /* SAP Authentication offload event */ #define WMITLV_TABLE_WMI_SAP_OFL_ADD_STA_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sap_ofl_add_sta_event_fixed_param, wmi_sap_ofl_add_sta_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ @@ -8064,9 +6954,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REG_CHAN_LIST_CC_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_chan_priority_struct, reg_chan_priority, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_fcc_rule_struct, reg_fcc_rule, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_reg_chan_list_cc_ext_additional_params, reg_more_data, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_rule_meta_data, reg_meta_data, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_hw_blacklist_chan_fixed_param, hw_blacklist_chan_fixed_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_hw_blacklist_chan_data, hw_blacklist_chan_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_rule_meta_data, reg_meta_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_REG_CHAN_LIST_CC_EXT_EVENTID); /* WMI AFC info event */ @@ -8076,17 +6964,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REG_CHAN_LIST_CC_EXT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_afc_power_event_param, wmi_afc_power_event_param, afc_power_event_param, WMITLV_SIZE_FIX)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_6g_afc_frequency_info, freq_info_array, WMITLV_SIZE_VAR)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_6g_afc_channel_info, channel_info_array, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_afc_chan_eirp_power_info, chan_eirp_power_info_array, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_hw_blacklist_chan_fixed_param, hw_blacklist_chan_fixed_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_hw_blacklist_chan_data, hw_blacklist_chan_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_afc_chan_eirp_power_info, chan_eirp_power_info_array, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_AFC_EVENTID); -/* HW blacklist channels for the current country code */ -#define WMITLV_TABLE_WMI_HW_BLACKLIST_CHAN_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hw_blacklist_chan_fixed_param, wmi_hw_blacklist_chan_fixed_param, hw_blacklist_chan_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_hw_blacklist_chan_data, hw_blacklist_chan_data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_HW_BLACKLIST_CHAN_EVENTID); - /* Indicate LPI AP detect or not to Host */ #define WMITLV_TABLE_WMI_C2C_DETECT_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_c2c_detect_event_fixed_param, wmi_c2c_detect_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -8121,13 +7001,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, debug_registers, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CHIP_POWER_STATS_EVENTID); -/* WMI event to provide pdev power stats */ -#define WMITLV_TABLE_WMI_PDEV_POWER_DATAPATH_STATS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_event_fixed_param, wmi_pdev_power_datapath_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_power_stats_info, power_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_tx_rate_info, tx_rate_stats, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_DATAPATH_STATS_EVENTID); - #define WMITLV_TABLE_WMI_VDEV_BCN_RECEPTION_STATS_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_bcn_recv_stats_event_fixed_param, wmi_vdev_bcn_recv_stats_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_BCN_RECEPTION_STATS_EVENTID); @@ -8166,10 +7039,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ANI_OFDM_LEVEL_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tpc, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_TPC_EVENTID); -#define WMITLV_TABLE_WMI_VDEV_TPC_IE_POWER_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param, wmi_vdev_tpc_ie_power_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_TPC_IE_POWER_EVENTID); - #define WMITLV_TABLE_WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_event_fixed_param, wmi_pdev_nfcal_power_all_channels_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_nfcal_power_all_channels_nfdBr, nfdbr, WMITLV_SIZE_VAR) \ @@ -8388,13 +7257,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_vdev_bcn_tx_stats_struct, ctrl_path_vdev_bcn_tx_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pdev_bcn_tx_stats_struct, ctrl_path_pdev_bcn_tx_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pdev_conn_stats_struct, ctrl_path_pdev_conn_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_ml_rcfg_stats_struct, ctrl_path_ml_rcfg_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_sta_dar_stats_struct, ctrl_path_sta_dar_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_beacon_stats, vdev_beacon_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_congestion_stats, vdev_congestion_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_data_stats, vdev_data_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_em_pcie_stats, ctrl_path_em_pcie_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_em_dcvs_stats, ctrl_path_em_dcvs_stats, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_ml_rcfg_stats_struct, ctrl_path_ml_rcfg_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID); /* @@ -8419,12 +7282,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_HALPHY_CTRL_PATH_STATS_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_radio_chan_stats, radio_chan_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_RADIO_CHAN_STATS_EVENTID); -#define WMITLV_TABLE_WMI_TDLS_STATS_EVENTID(id, op, buf, len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_stats_event_fixed_param, wmi_tdls_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tdls_connect_info_stats, tdls_connect_info_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tdls_data_stats, tdls_data_stats, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_STATS_EVENTID); - #define WMITLV_TABLE_WMI_PKGID_EVENTID(id, op, buf, len) \ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pkgid_event_fixed_param, wmi_pkgid_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PKGID_EVENTID); @@ -8672,11 +7529,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SSCAN_FW_PARAM_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sscan_evt_message_fixed_param, wmi_sscan_evt_message_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SSCAN_EVT_MESSAGE_EVENTID); -/* Send scan related stats to host */ -#define WMITLV_TABLE_WMI_GET_SCAN_STATS_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_scan_stats_resp_fixed_param, wmi_get_scan_stats_resp_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_GET_SCAN_STATS_RESP_EVENTID); - /* Roam capability report event */ #define WMITLV_TABLE_WMI_ROAM_CAPABILITY_REPORT_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_capability_report_event_fixed_param, wmi_roam_capability_report_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -8694,12 +7546,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_CAPABILITY_REPORT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, ctl_buf, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_TPC_STATS_EVENTID); -/* Send concurrency info to host */ -#define WMITLV_TABLE_WMI_SOC_GET_CONC_INFO_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_get_conc_info_resp_fixed_param, wmi_soc_get_conc_info_resp_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_conc_info, conc_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_SOC_GET_CONC_INFO_RESP_EVENTID); - /* Send Bcn Latency ie related params to host */ #define WMITLV_TABLE_WMI_VDEV_BCN_LATENCY_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_bcn_latency_fixed_param, wmi_vdev_bcn_latency_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -8929,8 +7775,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_EVENTID); #define WMITLV_TABLE_WMI_VDEV_VBSS_CONFIG_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vbss_config_event_fixed_param, wmi_vdev_vbss_config_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_pn_info, vbss_peer_pn_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_sn_info, vbss_peer_sn_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_dyn_info, vbss_peer_dyn_info, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_sn_info, vbss_peer_sn_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_VBSS_CONFIG_EVENTID); /* link switch event */ @@ -9017,157 +7862,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_BOOST_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_cache_info, scan_cache_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_CACHE_RESULT_EVENTID); -#define WMITLV_TABLE_WMI_MODIFY_TX_PLIM_EVENTID(id, op , buf, len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_modify_tx_plim_event_fixed_param, wmi_modify_tx_plim_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_MODIFY_TX_PLIM_EVENTID); - -#define WMITLV_TABLE_WMI_AVG_TX_POWER_EVENTID(id, op , buf, len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_avg_tx_power_event_fixed_param, wmi_avg_tx_power_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_avg_tx_power_region_per_antenna_chain, avg_tx_power_region_per_antenna_chain, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_AVG_TX_POWER_EVENTID); - -#define WMITLV_TABLE_WMI_PLIMIT_TABLE_EVENTID(id, op , buf, len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_plimit_table_event_fixed_param, wmi_plimit_table_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tx_power_per_antenna_chain, tx_power_per_antenna_chain, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PLIMIT_TABLE_EVENTID); - -/* pdev per-vdev queue depth report event */ -#define WMITLV_TABLE_WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param, wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_ac_info, vdev_ac_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID); - -/* WMI Anomaly Report Event */ -#define WMITLV_TABLE_WMI_ANOMALY_REPORT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, \ - WMITLV_TAG_STRUC_wmi_anomaly_report_hdr, \ - wmi_anomaly_report_hdr, hdr, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, \ - WMITLV_TAG_ARRAY_STRUC, \ - wmi_anomaly_entry_t, entries, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_ANOMALY_REPORT_EVENTID); - -#define WMITLV_TABLE_WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_tx_chainmask_comp_event_fixed_param, wmi_pdev_set_tx_chainmask_comp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID); - -/* WMI Event to indicate Firmware is ready for mode configuration by host */ -#define WMITLV_TABLE_WMI_FW_READY_IND_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_fw_ready_ind_event_fixed_param, wmi_fw_ready_ind_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_FW_READY_IND_EVENTID); - -/* WMI Event to acknowledge the driver mode sent by host */ -#define WMITLV_TABLE_WMI_WLAN_MODE_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_mode_resp_event_fixed_param, wmi_wlan_mode_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_RESP_EVENTID); - -/* CFR capture filter response event */ -#define WMITLV_TABLE_WMI_CFR_CAPTURE_FILTER_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_cfr_capture_filter_resp_event_fixed_param, wmi_cfr_capture_filter_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cfr_capture_fix_agc_gain_info, fix_agc_gain_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_CFR_CAPTURE_FILTER_RESP_EVENTID); - - -/* WMI command for unified connect event */ -#define WMITLV_TABLE_WMI_VDEV_UNIFIED_CONNECT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_unified_connect_event_fixed_param, wmi_vdev_unified_connect_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_conf_event_fixed_param, wmi_peer_create_conf_event_fixed_param, peer_create_fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_response_event_fixed_param, wmi_vdev_start_response_event_fixed_param, vdev_start_fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, peer_assoc_fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_EVENTID); - -/* WMI command for unified disconnect event */ -#define WMITLV_TABLE_WMI_VDEV_UNIFIED_DISCONNECT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_event_fixed_param, wmi_vdev_unified_disconnect_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param, wmi_peer_delete_resp_event_fixed_param, peer_delete_fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stopped_event_fixed_param, wmi_vdev_stopped_event_fixed_param, vdev_stop_fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_DISCONNECT_EVENTID); - -/* get IPA ring stats event */ -#define WMITLV_TABLE_WMI_IPA_RING_STATS_CONF_EVENTID(id,op,buf,len) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ipa_ring_stats_conf_event_fixed_param, wmi_ipa_ring_stats_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ipa_ring_stat_entry, ipa_ring_stat_entry, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_IPA_RING_STATS_CONF_EVENTID); - -#define WMITLV_TABLE_WMI_PDEV_UHR_CU_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_event_fixed_param, wmi_pdev_uhr_cu_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_uhr_cu_status, cu_status, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UHR_CU_EVENTID); - -/* WMI unified SMD PEER SETUP event */ -#define WMITLV_TABLE_WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_complete_event_fixed_param, wmi_smd_roam_peer_unified_setup_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_conf_event_fixed_param, wmi_peer_create_conf_event_fixed_param, peer_create_conf_fixed_param, WMITLV_SIZE_FIX) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, peer_assoc_conf_fixed_param, WMITLV_SIZE_FIX)\ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param, wmi_vdev_install_key_complete_event_fixed_param, vdev_install_key_complete_fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID); - -/* WMI unified SMD Config event */ -#define WMITLV_TABLE_WMI_SMD_ROAM_CONFIG_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_smd_roam_config_event_fixed_param, wmi_smd_roam_config_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_CONFIG_EVENTID); - -/* WMI Command for Energy management OEM cmd data */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_OEM_DATA_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_event_fixed_param, wmi_energy_mgmt_oem_data_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_OEM_DATA_EVENTID); - -/* VDEV current operating params event */ -#define WMITLV_TABLE_WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_current_operating_param_event_fixed_param, wmi_vdev_current_operating_param_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID); - -/* WMI Event to provide CoEx Policy Stats data */ -#define WMITLV_TABLE_WMI_COEX_GET_POLICY_STATS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_policy_stats_event_fixed_param, wmi_coex_policy_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_COEX_GET_POLICY_STATS_EVENTID); - -/* WMI unified set CUMAC chip ID confirmation event */ -#define WMITLV_TABLE_WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param, wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID); - -/* NAN DFS Channel Availability Indication Event */ -#define WMITLV_TABLE_WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_dfs_channel_availability_ind_event_fixed_param, wmi_nan_dfs_channel_availability_ind_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID); - -/* Chipset debug log stats event */ -#define WMITLV_TABLE_WMI_GET_CHIPSET_LOGGING_STATS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_event_fixed_param, wmi_get_chipset_logging_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_GET_CHIPSET_LOGGING_STATS_EVENTID); - -/* RTT Peer measurement report event */ -#define WMITLV_TABLE_WMI_RTT_PEER_MEAS_REPORT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_event_fixed_param, wmi_rtt_peer_meas_report_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_peer_meas_report_peer_meas_result_info, peer_meas_result_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_REPORT_EVENTID); - -#define WMITLV_TABLE_WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_chan_hop_status_report_event_fixed_param, wmi_vdev_chan_hop_status_report_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_chan_hop_slot_status, slot_status, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID); - -/* Athdiag read/write event: fixed_param + optional read data TLV */ -#define WMITLV_TABLE_WMI_ATHDIAG_READ_WRITE_EVENTID(id, op, buf, len) \ - WMITLV_ELEM(id, op, buf, len, \ - WMITLV_TAG_STRUC_wmi_athdiag_read_write_event_fixed_param, \ - wmi_athdiag_read_write_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id, op, buf, len, \ - WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_ATHDIAG_READ_WRITE_EVENTID); - #ifdef __cplusplus } diff --git a/drivers/staging/fw-api/fw/wmi_unified.h b/drivers/staging/fw-api/fw/wmi_unified.h index 9c221dab3851..70eaf1826cf7 100644 --- a/drivers/staging/fw-api/fw/wmi_unified.h +++ b/drivers/staging/fw-api/fw/wmi_unified.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2010-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -115,8 +115,6 @@ extern "C" { } #endif -#define WMI_MAX_NUM_EXT_TLVS 50 - #define ATH_MAC_LEN 6 /**< length of MAC in bytes */ #define WMI_EVENT_STATUS_SUCCESS 0 /* Success return status to host */ #define WMI_EVENT_STATUS_FAILURE 1 /* Failure return status to host */ @@ -371,11 +369,7 @@ typedef enum { WMI_GRP_QUIET_OFL, /* 0x4a Quiet offloads */ WMI_GRP_ODD, /* 0x4b ODD */ WMI_GRP_TDMA, /* 0x4c TDMA */ - WMI_GRP_MANUAL_UL_TRIG, /* 0x4d Manual UL OFDMA Trigger */ - WMI_GRP_ENERGY_MGMT, /* 0x4e energy management */ - WMI_GRP_SMD, /* 0x4f SMD Roaming */ - WMI_GRP_CHIPSET_LOG, /* 0x50 Chipset Debug Logging */ - WMI_GRP_MAPC, /* 0x51 MAPC for co-ordinated features */ + WMI_GRP_MANUAL_UL_TRIG /* 0x4d Manual UL OFDMA Trigger */ } WMI_GRP_ID; #define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) @@ -388,9 +382,6 @@ typedef enum { /** initialize the wlan sub system */ WMI_INIT_CMDID = 0x1, - /** WMI command to specify the driver's mode of operation */ - WMI_WLAN_MODE_REQ_CMDID, - /* Scan specific commands */ /** start scan request to FW */ @@ -412,10 +403,6 @@ typedef enum { WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID, /** Only applicable to DBS capable product */ WMI_SET_SCAN_DBS_DUTY_CYCLE_CMDID, - /** enable/disable any scan request **/ - WMI_SCAN_SUPPRESS_CMDID, - /** get scan stats**/ - WMI_GET_SCAN_STATS_CMDID, /* PDEV(physical device) specific commands */ /** set regulatorty ctl id used by FW to determine the exact ctl power limits */ @@ -608,32 +595,7 @@ typedef enum { * for Power Boost feature */ WMI_PDEV_POWER_BOOST_MEM_ADDR_CMDID, - /** - * This command is deprecated - DO NOT USE - * WMI cmd to to Enable/Disable NPCA and its capabilities - */ - WMI_PDEV_NPCA_AP_CAP_CMDID, - /** - * WMI cmd to get the per-vdev, per-access-category queue pending packets - * for the pdev - */ - WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID, - /* WMI_PDEV_RESERVED_CMDID: - * The value is now deprecated / reserved - it was initially erroneously - * given to WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID, but now that - * WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID has been moved to the EVENTID - * enum, this value is available to use for a future PDEV CMDID. - */ - WMI_PDEV_RESERVED_CMDID, - /** - * WMI cmd to send the detailed information of each UHR feature, - * that are applicable for critical update. - */ - WMI_PDEV_UHR_CU_CMDID, - /** WMI cmd used to enable/disable and get power and data path stats */ - WMI_PDEV_POWER_DATAPATH_STATS_CMDID, - /** WMI cmd to get the CUMAC chip ID */ - WMI_PDEV_SET_CUMAC_CHIP_CMDID, + /* VDEV (virtual device) specific commands */ /** vdev create */ @@ -761,31 +723,6 @@ typedef enum { WMI_VDEV_VBSS_CONFIG_CMDID, - WMI_VDEV_GET_TPC_IE_POWER_CMDID, - - /** data traffic monitoring */ - WMI_VDEV_TRAFFIC_MONITORING_CMDID, - - /** WMI cmd used to control DPS Assisting AP role config */ - WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID, - - /** WMI cmd for unified connect */ - WMI_VDEV_UNIFIED_CONNECT_CMDID, - - /** WMI cmd for unified disconnect */ - WMI_VDEV_UNIFIED_DISCONNECT_CMDID, - - /** WMI cmd for response of wmi_vdev_repurpose_request_tlv_param */ - WMI_VDEV_REPURPOSE_RESP_CMDID, - - /** WMI cmd for UHR critical update */ - WMI_VDEV_UHR_CU_CMDID, - - /** WMI cmd for Channel Hopping Schedule */ - WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID, - - /** WMI cmd to request channel hopping per-slot status report */ - WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID, /* peer specific commands */ @@ -914,20 +851,7 @@ typedef enum { /* WMI command to setup reorder queue for multiple TIDs */ WMI_PEER_MULTIPLE_REORDER_QUEUE_SETUP_CMDID, - /** Customize MCS range for specific tid */ - WMI_PEER_TID_RATE_CUSTOM_CMDID, - - /** Peer UHR Mode Update Command **/ - WMI_PEER_UHR_MODE_UPDATE_CMDID, - - /* WMI_PEER_ASSOC_V2_CMDID: extended alternative for WMI_PEER_ASSOC_CMDID */ - WMI_PEER_ASSOC_V2_CMDID, - - /* WMI_PEER_UHR_OMP_CMDID for UHR OMP frame*/ - WMI_PEER_UHR_OMP_CMDID, - - - /*--- beacon/management specific commands ---*/ + /* beacon/management specific commands */ /** transmit beacon by reference . used for transmitting beacon on low latency interface like pcie */ WMI_BCN_TX_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MGMT), @@ -1070,10 +994,6 @@ typedef enum { WMI_ROAM_ENABLE_VENDOR_CONTROL_CMDID, /** Get firmware ini value */ WMI_ROAM_GET_VENDOR_CONTROL_PARAM_CMDID, - /** configure SMD parameters for roaming */ - WMI_ROAM_SMD_CONFIG_CMDID, - /** SMD preparation completion status command */ - WMI_ROAM_SMD_START_STATUS_CMDID, /** offload scan specific commands */ /** set offload scan AP profile */ @@ -1215,10 +1135,6 @@ typedef enum { WMI_RTT_PASN_AUTH_STATUS_CMD, /** RTT 11az PASN deauthentication cmd */ WMI_RTT_PASN_DEAUTH_CMD, - /** request to start peer measurement */ - WMI_RTT_PEER_MEAS_REQ_CMDID, - /** request to cancel an ongoing peer measurement */ - WMI_RTT_PEER_MEAS_CANCEL_CMDID, /** spectral scan command */ /** configure spectral scan */ @@ -1277,8 +1193,6 @@ typedef enum { /** request for HALPHY stats through ctrl path */ WMI_REQUEST_HALPHY_CTRL_PATH_STATS_CMDID, - /** request for TDLS connect info and TDLS data stats */ - WMI_REQUEST_TDLS_STATS_CMDID, /** ARP OFFLOAD REQUEST*/ WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_ARP_NS_OFL), @@ -1441,15 +1355,6 @@ typedef enum { /** WMI command to get scan cached result */ WMI_GET_SCAN_CACHE_RESULT_CMDID, - WMI_SET_MODIFY_TX_PLIM_CMDID, - - WMI_GET_AVG_TX_POWER_CMDID, - - WMI_GET_TX_POWER_CALLING_CMDID, - - /** WMI command for athdiag memory/register read or write */ - WMI_ATHDIAG_READ_WRITE_CMDID, - /* Offload 11k related requests */ WMI_11K_OFFLOAD_REPORT_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_11K_OFFLOAD), @@ -1566,48 +1471,6 @@ typedef enum { WMI_NAN_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_NAN), /** Command to handle OEM's NAN specific opaque data */ WMI_NAN_OEM_DATA_CMDID, - /** Command to enable NAN mode */ - WMI_NAN_ENABLE_CMDID, - /** Command to update NAN configuration */ - WMI_NAN_CONFIG_CMDID, - /** Command to disable NAN mode */ - WMI_NAN_DISABLE_CMDID, - /** - * Command to indicate our committed local discovery schedule - * (pre NAN datapath/ranging setup etc.) which FW needs to follow. - */ - WMI_NAN_LOCAL_SCHEDULE_CMDID, - /** - * Command to indicate negotiated committed schedule which FW - * has to follow with a given peer. - */ - WMI_NAN_PEER_SCHEDULE_CMDID, - /** - * Command to indicate negotiated rate control parameters with a - * given peer (during NAN datapath/ranging setup or schedule - * negotiation etc.). - */ - WMI_NAN_PEER_PARAMS_CMDID, - /** - * Command to request for NAN service discovery operations i.e. - * Publish, Subscribe, Followup to be handled by FW. - * This command carries the full NAN function parameters equivalent - * to NL80211_CMD_ADD_NAN_FUNCTION / cfg80211_nan_func, including - * service ID, SRF filters, match filters, SDEA control, security - * (cipher suites, ND-PMK), and NAN3 pairing configuration. - */ - WMI_NAN_DISC_SERVICE_REQ_CMDID, - /** - * Command to cancel an active NAN discovery service request - * (Publish or Subscribe). - * Equivalent of NL80211_CMD_DEL_NAN_FUNCTION in the cfg80211 - * offload interface. - * Host identifies the service request by instance_id (offload path) - * or cookie (standard path); FW frees the service request and sends - * WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID if the service request - * was active. - */ - WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID, /** Modem power state command */ WMI_MODEM_POWER_STATE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_COEX), @@ -1622,7 +1485,6 @@ typedef enum { WMI_TAS_POWER_HISTORY_CMDID, WMI_ESL_EGID_CMDID, WMI_COEX_MULTIPLE_CONFIG_CMDID, - WMI_COEX_GET_POLICY_STATS_CMDID, /** * OBSS scan offload enable/disable commands @@ -1662,8 +1524,6 @@ typedef enum { /** IPA Offload features related commands */ WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_IPA), - /** WMI cmd to get IPA ring stats */ - WMI_IPA_RING_STATS_REQ_CMDID, /** mDNS responder offload commands */ WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MDNS_OFL), @@ -1699,8 +1559,6 @@ typedef enum { * and specifiy packets of interest for classification. */ WMI_SOC_TX_PACKET_CUSTOM_CLASSIFY_CMDID, - /** WMI cmd to get the concurrency info for all vdevs within the target */ - WMI_SOC_GET_CONC_INFO_CMDID, /* packet filter commands */ WMI_PACKET_FILTER_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_PKT_FILTER), @@ -1721,8 +1579,6 @@ typedef enum { WMI_BPF_SET_VDEV_ENABLE_CMDID, WMI_BPF_SET_VDEV_WORK_MEMORY_CMDID, WMI_BPF_GET_VDEV_WORK_MEMORY_CMDID, - WMI_BPF_SET_SUPPORTED_OFFLOAD_BITMAP_CMDID, - WMI_BPF_SET_APF_MODE_CMDID, /** WMI commands related to monitor mode. */ WMI_MNT_FILTER_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MONITOR), @@ -1745,7 +1601,6 @@ typedef enum { WMI_NDP_RESPONDER_REQ_CMDID, WMI_NDP_END_REQ_CMDID, WMI_NDP_CMDID, - WMI_NDP_SET_LATENCY_TPUT_CMDID, /** WMI commands related to HW data filtering **/ WMI_HW_DATA_FILTER_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_HW_DATA_FILTER), @@ -1766,7 +1621,6 @@ typedef enum { WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID, /* XPAN TWT */ WMI_VDEV_GET_TWT_SESSION_STATS_INFO_CMDID, WMI_TWT_VDEV_CONFIG_CMDID, - WMI_TWT_ADD_CH_USAGE_CMDID, /** WMI commands related to motion detection **/ WMI_MOTION_DET_CONFIG_PARAM_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MOTION_DET), @@ -1848,8 +1702,6 @@ typedef enum { WMI_MLO_LINK_RECONFIG_CMDID, /** WMI cmd to notify fw completion of link reconfig */ WMI_MLO_LINK_RECONFIG_COMPLETE_CMDID, - /** WMI cmd to notify fw completion of negotiated TID to LINK map */ - WMI_MLO_LINK_TTLM_COMPLETE_CMDID, /** WMI commands specific to Service Aware WiFi (SAWF) */ /** configure or reconfigure the parameters for a service class */ @@ -1871,37 +1723,6 @@ typedef enum { /** WMI Command to set Manual MU UL OFDMA trigger parameters */ WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID, - - - /** WMI commands specific to Energy Management **/ - /** WMI cmd used to control PCIe config */ - WMI_ENERGY_MGMT_PCIE_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_ENERGY_MGMT), - /** WMI cmd used to control PCIe LPM */ - WMI_ENERGY_MGMT_PCIE_LPM_CMDID, - /** WMI cmd used to control Clock and Voltage config */ - WMI_ENERGY_MGMT_DCVS_CONFIG_CMDID, - /** WMI cmd used to control AP Dynamic Power Save feature */ - WMI_ENERGY_MGMT_EDPS_CONFIG_CMDID, - /** WMI cmd used to control periodic unavailability operation */ - WMI_ENERGY_MGMT_PUO_CONFIG_CMDID, - /** WMI cmd used to control ECO mode config */ - WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID, - /** Command to Handle Energy Management OEM's opaque data */ - WMI_ENERGY_MGMT_OEM_DATA_CMDID, - - /** WMI cmd used to set the SMD Roam config */ - WMI_SMD_ROAM_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SMD), - /** - * WMI cmd used to set up the peer on the target AP during Prep Phase - * (Combine PeerCreate,Assoc, Key Install) - */ - WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID, - - /** WMI command for host to request chipset debug log stats from FW */ - WMI_GET_CHIPSET_LOGGING_STATS_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_CHIPSET_LOG), - - /** WMI cmds for MAPC (Multi-AP Coordination) */ - WMI_PEER_SET_MAPC_PARAMS_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MAPC), } WMI_CMD_ID; typedef enum { @@ -1920,23 +1741,6 @@ typedef enum { */ WMI_IFACE_COMBINATION_IND_EVENTID, - /** WMI evt that indicates FW basic initializations are done, and FW - * is ready to receive the WLAN mode specification from the host. - * - * mode selection handshake: - * host <-- WMI_FW_READY_IND_EVENTID <---- target - * host --> WMI_WLAN_MODE_REQ_CMDID -----> target - * host <-- WMI_WLAN_MODE_RESP_EVENTID <-- target - * precedes the WLAN initialization handshake: - * host <-- WMI_SERVICE_READY_EVENTID <--- target - * host --> WMI_INIT_CMDID --------------> target - * host <-- WMI_READY_EVENTID <----------- target - */ - WMI_FW_READY_IND_EVENTID, - /* WMI evt to acknowledge the driver mode specified by host */ - WMI_WLAN_MODE_RESP_EVENTID, - - /** Scan specific events */ WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN), @@ -1949,188 +1753,157 @@ typedef enum { /** Spectral scan capabilities advertisement */ WMI_SPECTRAL_CAPABILITIES_EVENTID, - /** Send scan stats to HOST */ - WMI_GET_SCAN_STATS_RESP_EVENTID, - /* PDEV specific events */ /** TPC config for the current operating channel */ - WMI_PDEV_TPC_CONFIG_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PDEV), /* 0 */ + WMI_PDEV_TPC_CONFIG_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PDEV), /** Channel stats event */ - WMI_CHAN_INFO_EVENTID, /* 1 */ + WMI_CHAN_INFO_EVENTID, /** PHY Error specific WMI event */ - WMI_PHYERR_EVENTID, /* 2 */ + WMI_PHYERR_EVENTID, /** eeprom dump event */ - WMI_PDEV_DUMP_EVENTID, /* 3 */ + WMI_PDEV_DUMP_EVENTID, /** traffic pause event */ - WMI_TX_PAUSE_EVENTID, /* 4 */ + WMI_TX_PAUSE_EVENTID, /** DFS radar event */ - WMI_DFS_RADAR_EVENTID, /* 5 */ + WMI_DFS_RADAR_EVENTID, /** track L1SS entry and residency event */ - WMI_PDEV_L1SS_TRACK_EVENTID, /* 6 */ + WMI_PDEV_L1SS_TRACK_EVENTID, /** Report current temperature of the chip in Celcius degree */ - WMI_PDEV_TEMPERATURE_EVENTID, /* 7 */ + WMI_PDEV_TEMPERATURE_EVENTID, /** Extension of WMI_SERVICE_READY msg with extra target capability info */ - WMI_SERVICE_READY_EXT_EVENTID, /* 8 */ + WMI_SERVICE_READY_EXT_EVENTID, /** FIPS test mode event */ - WMI_PDEV_FIPS_EVENTID, /* 9 */ + WMI_PDEV_FIPS_EVENTID, /** Channel hopping avoidance */ - WMI_PDEV_CHANNEL_HOPPING_EVENTID, /* 10 */ + WMI_PDEV_CHANNEL_HOPPING_EVENTID, /** CCK ANI level event */ - WMI_PDEV_ANI_CCK_LEVEL_EVENTID, /* 11 */ + WMI_PDEV_ANI_CCK_LEVEL_EVENTID, /** OFDM ANI level event */ - WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, /* 12 */ + WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, /** Tx PPDU params */ - WMI_PDEV_TPC_EVENTID, /* 13 */ + WMI_PDEV_TPC_EVENTID, /** NF Cal Power in DBR/DBM for all channels */ - WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, /* 14 */ + WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, /** SOC/PDEV events */ - WMI_PDEV_SET_HW_MODE_RESP_EVENTID, /* 15 */ - WMI_PDEV_HW_MODE_TRANSITION_EVENTID, /* 16 */ - WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, /* 17 */ + WMI_PDEV_SET_HW_MODE_RESP_EVENTID, + WMI_PDEV_HW_MODE_TRANSITION_EVENTID, + WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, /** Report ANT DIV feature's status */ - WMI_PDEV_ANTDIV_STATUS_EVENTID, /* 18 */ + WMI_PDEV_ANTDIV_STATUS_EVENTID, /** Chip level Power stats */ - WMI_PDEV_CHIP_POWER_STATS_EVENTID, /* 19 */ + WMI_PDEV_CHIP_POWER_STATS_EVENTID, /** Power Save Failure Detected */ - WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID, /* 20 */ + WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID, /* Event to report the switch count in csa of one or more VDEVs */ - WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID, /* 21 */ + WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID, /** Report the caldata version to host */ - WMI_PDEV_CHECK_CAL_VERSION_EVENTID, /* 22 */ + WMI_PDEV_CHECK_CAL_VERSION_EVENTID, /** Report chain RSSI and antenna index to host */ - WMI_PDEV_DIV_RSSI_ANTID_EVENTID, /* 23 */ + WMI_PDEV_DIV_RSSI_ANTID_EVENTID, /** provide noise floor and cycle counts for a channel */ - WMI_PDEV_BSS_CHAN_INFO_EVENTID, /* 24 */ + WMI_PDEV_BSS_CHAN_INFO_EVENTID, /** Response received the ctl table to host */ - WMI_PDEV_UPDATE_CTLTABLE_EVENTID, /* 25 */ + WMI_PDEV_UPDATE_CTLTABLE_EVENTID, - WMI_PDEV_DMA_RING_CFG_RSP_EVENTID, /* 26 */ + WMI_PDEV_DMA_RING_CFG_RSP_EVENTID, - WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID, /* 27 */ + WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID, /** WMI Event to deliver CTL Failsafe application */ - WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID, /* 28 */ + WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID, /* Event to report the switch count in BSS color of one or more VDEVs */ - WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID, /* 29 */ + WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID, /* Event to send cold boot calibration data */ - WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID, /* 30 */ + WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID, /* Event to report a rogue ap info that is detected in fw */ - WMI_PDEV_RAP_INFO_EVENTID, /* 31 */ + WMI_PDEV_RAP_INFO_EVENTID, - WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, /* 32 */ + WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, /** 2nd extension of SERVICE_READY msg with extra target capability info */ - WMI_SERVICE_READY_EXT2_EVENTID, /* 33 */ + WMI_SERVICE_READY_EXT2_EVENTID, /** * vdev restart response for multiple vdevs in response to * MULTIPLE_VDEV_RESTART_REQUEST */ - WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID, /* 34 */ + WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID, /** WMI event in response to TPC STATS command */ - WMI_PDEV_GET_TPC_STATS_EVENTID, /* 35 */ + WMI_PDEV_GET_TPC_STATS_EVENTID, /* Event to get DPD status from HALPHY */ - WMI_PDEV_GET_DPD_STATUS_EVENTID, /* 36 */ + WMI_PDEV_GET_DPD_STATUS_EVENTID, /* Event to get Calibration status from HALPHY */ - WMI_PDEV_GET_HALPHY_CAL_STATUS_EVENTID, /* 37 */ + WMI_PDEV_GET_HALPHY_CAL_STATUS_EVENTID, /* Event to set halphy cal bitmap */ - WMI_PDEV_SET_HALPHY_CAL_BMAP_EVENTID, /* 38 */ + WMI_PDEV_SET_HALPHY_CAL_BMAP_EVENTID, /* Event to get AOA phasedelta values from HALPHY */ - WMI_PDEV_AOA_PHASEDELTA_EVENTID, /* 39 */ + WMI_PDEV_AOA_PHASEDELTA_EVENTID, - WMI_PDEV_FIPS_EXTEND_EVENTID, /* 40 */ + WMI_PDEV_FIPS_EXTEND_EVENTID, /* Event to send packet log decode information */ - WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID, /* 41 */ + WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID, /** * RSSI dB to dBm conversion params info event * sent to host after channel/bw/chainmask change per pdev. */ - WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID, /* 42 */ + WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID, /* Event to indicate Schedule tid queue suspended info */ - WMI_PDEV_SCHED_TIDQ_SUSP_INFO_EVENTID, /* 43 */ + WMI_PDEV_SCHED_TIDQ_SUSP_INFO_EVENTID, /* Event to send target rate to power table update status */ - WMI_PDEV_SET_TGTR2P_TABLE_EVENTID, /* 44 */ + WMI_PDEV_SET_TGTR2P_TABLE_EVENTID, /* Event to indicate completion on RF path */ - WMI_PDEV_SET_RF_PATH_RESP_EVENTID, /* 45 */ + WMI_PDEV_SET_RF_PATH_RESP_EVENTID, /* Event to get AOA phasedelta values for all gain tables from HALPHY */ - WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID, /* 46 */ + WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID, /* Event to indicate the status of WiFi Radar calibration */ - WMI_PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_EVENTID, /* 47 */ + WMI_PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_EVENTID, /* Event to indicate xLNA is enabled */ - WMI_PDEV_ENABLE_XLNA_EVENTID, /* 48 */ + WMI_PDEV_ENABLE_XLNA_EVENTID, /* Event to indicate ANN Power Boost update status from Target */ - WMI_PDEV_POWER_BOOST_EVENTID, /* 49 */ + WMI_PDEV_POWER_BOOST_EVENTID, /* * WMI event to share Wi-Fi Radar - * monostatic Wi-Fi sensing technique capabalites */ - WMI_PDEV_WIFI_RADAR_CAPABILITIES_EVENTID, /* 50 */ - - /* - * This event is deprecated - DO NOT USE - * WMI_PDEV_NPCA_AP_CAP_CMDID response event - */ - WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID, /* 51 */ - - /* Event to share the per-access-category queue pending packets */ - WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID, /* 52 */ - - /* WMI event for the UHR critical Update */ - WMI_PDEV_UHR_CU_EVENTID, /* 53 */ - - /** - * WMI Event to send power and data path stats info to Host - */ - WMI_PDEV_POWER_DATAPATH_STATS_EVENTID, /* 54 */ - - /** Event to indicate CUMAC Chip ID initialization completed to host */ - WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID, /* 55 */ - - /*** - *** add new WMI_PDEV EVENTID defs directly above here, - *** until EVENTID offset 89 is reached, then continue - *** from 90 below WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID - ***/ - WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID = 0x405a, /* 89 */ - + WMI_PDEV_WIFI_RADAR_CAPABILITIES_EVENTID, /* VDEV specific events */ @@ -2212,15 +1985,6 @@ typedef enum { /** Connect response */ WMI_VDEV_OOB_CONNECTION_RESP_EVENTID, WMI_VDEV_VBSS_CONFIG_EVENTID, - WMI_VDEV_TPC_IE_POWER_EVENTID, - /** WMI event for unified connect */ - WMI_VDEV_UNIFIED_CONNECT_EVENTID, - /** WMI event for unified disconnect */ - WMI_VDEV_UNIFIED_DISCONNECT_EVENTID, - /** WMI event for sending vdev operating params */ - WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID, - /** channel hopping per-slot status report event */ - WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID, /* peer specific events */ /** FW reauet to kick out the station for reasons like inactivity,lack of response ..etc */ @@ -2399,7 +2163,6 @@ typedef enum { /* send pdev resume event to host after pdev resume. */ WMI_PDEV_RESUME_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SUSPEND), - WMI_PDEV_SUSPEND_EVENTID, /** WOW wake up host event.generated in response to WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID. will cary wake reason */ @@ -2419,8 +2182,6 @@ typedef enum { WMI_RTT_PASN_PEER_CREATE_REQ_EVENTID, /** RTT 11az PASN peer delete event */ WMI_RTT_PASN_PEER_DELETE_EVENTID, - /** RTT peer (Proximity Detection) measurement report */ - WMI_RTT_PEER_MEAS_REPORT_EVENTID, /*STATS specific events*/ /** txrx stats event requested by host */ @@ -2487,12 +2248,6 @@ typedef enum { /** FW IPA link stats Event */ WMI_IPA_LINK_STATS_EVENTID, - /* TDLS Stats event having TDLS connect info and data stats */ - WMI_TDLS_STATS_EVENTID, - - /** WMI Anomaly Report Event — single event ID for all FW anomaly types */ - WMI_ANOMALY_REPORT_EVENTID, - /* NLO specific events */ /** NLO match event after the first match */ @@ -2655,15 +2410,6 @@ typedef enum { /** WMI event for FW diagnostic data sent to host */ WMI_OPT_DP_DIAG_EVENTID, - WMI_MODIFY_TX_PLIM_EVENTID, - - WMI_AVG_TX_POWER_EVENTID, - - WMI_PLIMIT_TABLE_EVENTID, - - /** WMI event to deliver athdiag read data or write completion status */ - WMI_ATHDIAG_READ_WRITE_EVENTID, - /* GPIO Event */ WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO), @@ -2718,47 +2464,6 @@ typedef enum { WMI_NAN_DMESG_EVENTID, /** Event to deliver OEM's NAN specific opaque data */ WMI_NAN_OEM_DATA_EVENTID, - /** Event response to NAN enable command */ - WMI_NAN_ENABLE_RSP_EVENTID, - /** Event indicating information about next Discovery Window (DW) */ - WMI_NAN_NEXT_DW_INFO_EVENTID, - /** Event confirmation to NAN disable command */ - WMI_NAN_DISABLE_CNF_EVENTID, - /** Event notifying FW triggered NAN disable indication */ - WMI_NAN_DISABLE_IND_EVENTID, - /** Confirmation event to NAN local schedule command */ - WMI_NAN_LOCAL_SCHEDULE_CNF_EVENTID, - /** Confirmation event to NAN peer schedule command */ - WMI_NAN_PEER_SCHEDULE_CNF_EVENTID, - /* Confirmation event that FW has received WMI_NAN_PEER_PARAMS_CMDID */ - WMI_NAN_PEER_PARAMS_CNF_EVENTID, - /* Indicate negotiated committed NDP channels information. */ - WMI_NDP_CHANNEL_INFO_EVENTID, - /* Event to indicate availability of STA AP connection on DFS channel */ - WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID, - /** - * Event response to NAN discovery service request command - * (WMI_NAN_DISC_SERVICE_REQ_CMDID); - * carries the instance_id assigned by FW and a status code indicating - * whether the Publish / Subscribe service request was accepted - */ - WMI_NAN_DISC_SERVICE_RSP_EVENTID, - /** - * NAN discovery match event; covers two match scenarios: - * subscriber found publisher (type=PUBLISH), publisher received subscribe - * (type=SUBSCRIBE). - * Equivalent of NL80211_CMD_NAN_MATCH in the cfg80211 - * offload interface. - */ - WMI_NAN_DISC_MATCH_EVENTID, - /** - * NAN discovery service request terminated event; sent when a Publish or - * Subscribe service request is cancelled by the host, expires (TTL), or is - * terminated by FW due to an error. - * Equivalent of NL80211_CMD_DEL_NAN_FUNCTION (EVENT: terminated) - * in the cfg80211 offload interface. - */ - WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID, /* Coex Event */ WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_COEX), @@ -2766,17 +2471,11 @@ typedef enum { /** Dedicated BT Antenna Mode (DBAM) complete event */ WMI_COEX_DBAM_COMPLETE_EVENTID, WMI_TAS_POWER_HISTORY_EVENTID, - WMI_COEX_GET_POLICY_STATS_EVENTID, /* LPI Event */ WMI_LPI_RESULT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_LPI), WMI_LPI_STATUS_EVENTID, WMI_LPI_HANDOFF_EVENTID, - /* - * New EVTID added for FW->LOWI intra-LPASS direct scan result delivery - - * replaces QMI path when LOWI-on-FW capability is enabled. - */ - WMI_LPI_SCAN_RESULT_EVENTID_V2, /* ExtScan events */ WMI_EXTSCAN_START_STOP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_EXTSCAN), @@ -2791,9 +2490,6 @@ typedef enum { /* mDNS offload events */ WMI_MDNS_STATS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MDNS_OFL), - /** WMI Event to send IPA ring stats to host */ - WMI_IPA_RING_STATS_CONF_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_IPA), - /* SAP Authentication offload events */ WMI_SAP_OFL_ADD_STA_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SAP_OFL), WMI_SAP_OFL_DEL_STA_EVENTID, @@ -2813,8 +2509,6 @@ typedef enum { WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SOC), WMI_SOC_HW_MODE_TRANSITION_EVENTID, WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID, - /* Event to share the concurrency info to HOST */ - WMI_SOC_GET_CONC_INFO_RESP_EVENTID, /** Motion Aided WiFi Connectivity (MAWC) events */ WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MAWC), @@ -2835,8 +2529,6 @@ typedef enum { WMI_AFC_EVENTID, WMI_REG_CHAN_LIST_CC_EXT2_EVENTID, /* DEPRECATED */ WMI_C2C_DETECT_EVENTID, - /* WMI event to send the HW channel blacklist during the CTL blob update */ - WMI_HW_BLACKLIST_CHAN_EVENTID, /** Events for TWT(Target Wake Time) of STA and AP */ WMI_TWT_ENABLE_COMPLETE_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_TWT), @@ -2875,9 +2567,6 @@ typedef enum { WMI_AUDIO_AGGR_REPORT_STATISTICS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_AUDIO), WMI_AUDIO_AGGR_SCHED_METHOD_EVENTID, - /** WMI events related to CFR capture response event */ - WMI_CFR_CAPTURE_FILTER_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CFR_CAPTURE), - /** Vendor defined WMI events **/ WMI_VENDOR_PDEV_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_VENDOR), WMI_VENDOR_VDEV_EVENTID, @@ -2899,9 +2588,6 @@ typedef enum { WMI_MLO_VDEV_LINK_INFO_EVENTID, /** request host to do T2LM neg to the un-disabled link */ WMI_MLO_LINK_DISABLE_REQUEST_EVENTID, - /* alias */ - WMI_MLO_LINK_TTLM_REQUEST_EVENTID = - WMI_MLO_LINK_DISABLE_REQUEST_EVENTID, /** request host to switch to new link for specified vdev */ WMI_MLO_LINK_SWITCH_REQUEST_EVENTID, /** Response event for WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID */ @@ -2932,19 +2618,6 @@ typedef enum { * WMI Event to send Manual UL OFDMA Trigger frame RX PPDU info to Host */ WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID, - - /* WMI event used during SMD Roaming */ - WMI_SMD_ROAM_CONFIG_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SMD), - /* - * WMI event to indicate the status of the SMD_ROAM_PEER_UNIFIED_SETUP_CMD - * used during SMD Roaming - */ - WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID, - - WMI_ENERGY_MGMT_OEM_DATA_EVENTID =WMI_CMD_GRP_START_ID(WMI_GRP_ENERGY_MGMT), - - /** WMI event to send chipset debug log stats to host */ - WMI_GET_CHIPSET_LOGGING_STATS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CHIPSET_LOG), } WMI_EVT_ID; /* defines for OEM message sub-types */ @@ -3012,7 +2685,6 @@ typedef enum { #define WMI_CHAN_FLAG_NAN_DISABLED 19 /* Indicates that NAN operations are disabled on this channel */ #define WMI_CHAN_FLAG_STA_DFS 20 /* Indicates if STA should process radar signals */ #define WMI_CHAN_FLAG_ALLOW_EHT 21 /* EHT (11be) is allowed on this channel */ -#define WMI_CHAN_FLAG_ALLOW_UHR 22 /* UHR (11bn) is allowed on this channel */ #define WMI_SET_CHANNEL_FLAG(pwmi_channel,flag) do { \ (pwmi_channel)->info |= ((A_UINT32) 1 << flag); \ @@ -3322,16 +2994,6 @@ typedef struct _wmi_ppe_threshold { #define WMI_MAX_EHTCAP_MAC_SIZE 2 #define WMI_MAX_EHTCAP_PHY_SIZE 3 -/* WMI_MAX_UHRCAP_MAC_SIZE: - * Kept as 4 for backwards compatibility, elements [2] and [3] are reserved. - */ -#define WMI_MAX_UHRCAP_MAC_SIZE 4 -#define WMI_MAX_UHRCAP_PHY_SIZE 8 /* as per spec recommendation */ -/* WMI_MAX_UHRCAP_DBE_SIZE: - * B0-B7 header + up to 24+24 bits EHT-MCS maps - */ -#define WMI_MAX_UHRCAP_DBE_SIZE 2 - /* * 0 – index indicated EHT-MCS map for 20Mhz only sta (4 bytes valid) * 1 – index for <= 80MHz bw (only 3 bytes are valid and other is reserved) @@ -3901,25 +3563,6 @@ typedef struct { #define WMI_TARGET_CAP_MPDU_STATS_PER_TX_NSS_SUPPORT_SET(target_cap_flags, value)\ WMI_SET_BITS(target_cap_flags, 16, 1, value) -#define WMI_TARGET_CAP_MAX_ML_STA_BSS_NUM_GET(target_cap_flags) \ - WMI_GET_BITS(target_cap_flags, 17, 3) -#define WMI_TARGET_CAP_MAX_ML_STA_BSS_NUM_SET(target_cap_flags, value) \ - WMI_SET_BITS(target_cap_flags, 17, 3, value) - -#define WMI_TARGET_CAP_MAX_ML_SAP_BSS_NUM_GET(target_cap_flags) \ - WMI_GET_BITS(target_cap_flags, 20, 3) -#define WMI_TARGET_CAP_MAX_ML_SAP_BSS_NUM_SET(target_cap_flags, value) \ - WMI_SET_BITS(target_cap_flags, 20, 3, value) - -#define WMI_TARGET_CAP_TOTAL_ML_LINKS_NUM_GET(target_cap_flags) \ - WMI_GET_BITS(target_cap_flags, 23, 3) -#define WMI_TARGET_CAP_TOTAL_ML_LINKS_NUM_SET(target_cap_flags, value) \ - WMI_SET_BITS(target_cap_flags, 23, 3, value) - -#define WMI_TARGET_CAP_FLAGS_RX_PEER_METADATA_VERSION_EXTENSION_GET(target_cap_flags) \ - WMI_GET_BITS(target_cap_flags, 26, 3) -#define WMI_TARGET_CAP_FLAGS_RX_PEER_METADATA_VERSION_EXTENSION_SET(target_cap_flags, value) \ - WMI_SET_BITS(target_cap_flags, 26, 3, value) /* * wmi_htt_msdu_idx_to_htt_msdu_qtype GET/SET APIs @@ -4032,92 +3675,6 @@ typedef enum { #define WMI_SUPPORTED_WIFI_8_CERTIFIED_GENERATION_SET(wifi_generations, value) \ WMI_SET_BITS(wifi_generations, 4, 1, value) -/* Begin SAM related capabilities */ -#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_PEER_GET(sam_capability_1) \ - WMI_GET_BITS(sam_capability_1, 0, 12) -#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_PEER_SET(sam_capability_1, value) \ - WMI_SET_BITS(sam_capability_1, 0, 12, value) - -#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_MSDUQ_GET(sam_capability_1) \ - WMI_GET_BITS(sam_capability_1, 12, 13) -#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_MSDUQ_SET(sam_capability_1, value) \ - WMI_SET_BITS(sam_capability_1, 12, 13, value) - -#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_MPDUQ_GET(sam_capability_2) \ - WMI_GET_BITS(sam_capability_2, 0, 12) -#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_MPDUQ_SET(sam_capability_2, value) \ - WMI_SET_BITS(sam_capability_2, 0, 12, value) -/* End SAM related capabilities */ - - -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_shared_mem_model_tbtt_count_down_config.*/ - A_UINT32 tlv_header; - /* Indicates what are all the TBTT count down that FW supports */ - union { - struct { - A_UINT32 csa :1, - quiet :1, - max_chan_switch_time :1, - eht_bpcc :1, - ttlm_max_switch_time :1, - ttlm_expected_duration :1, - ml_reconfig :1, - uhr_epbcc :1, - uhr_params_update :1, - rsvd :23; - }; - A_UINT32 config_1; - }; - -} wmi_shared_mem_model_tbtt_count_down_config; - -/* wmi_shared_mem_model_tbtt_count_down_config GET/SET macros */ -#define WMI_TBTT_COUNT_DOWN_CONFIG_CSA_GET(config_1) \ - WMI_GET_BITS(config_1, 0, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_CSA_SET(config_1, value) \ - WMI_SET_BITS(config_1, 0, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_QUIET_GET(config_1) \ - WMI_GET_BITS(config_1, 1, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_QUIET_SET(config_1, value) \ - WMI_SET_BITS(config_1, 1, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_MAX_CHAN_SWITCH_TIME_GET(config_1) \ - WMI_GET_BITS(config_1, 2, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_MAX_CHAN_SWITCH_TIME_SET(config_1, value) \ - WMI_SET_BITS(config_1, 2, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_EHT_BPCC_GET(config_1) \ - WMI_GET_BITS(config_1, 3, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_EHT_BPCC_SET(config_1, value) \ - WMI_SET_BITS(config_1, 3, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_TTLM_MAX_SWITCH_TIME_GET(config_1) \ - WMI_GET_BITS(config_1, 4, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_TTLM_MAX_SWITCH_TIME_SET(config_1, value) \ - WMI_SET_BITS(config_1, 4, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_TTLM_EXPECTED_DURATION_GET(config_1) \ - WMI_GET_BITS(config_1, 5, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_TTLM_EXPECTED_DURATION_SET(config_1, value) \ - WMI_SET_BITS(config_1, 5, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_ML_RECONFIG_GET(config_1) \ - WMI_GET_BITS(config_1, 6, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_ML_RECONFIG_SET(config_1, value) \ - WMI_SET_BITS(config_1, 6, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_UHR_EPBCC_GET(config_1) \ - WMI_GET_BITS(config_1, 7, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_UHR_EPBCC_SET(config_1, value) \ - WMI_SET_BITS(config_1, 7, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_UHR_PARAMS_UPDATE_GET(config_1) \ - WMI_GET_BITS(config_1, 8, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_UHR_PARAMS_UPDATE_SET(config_1, value) \ - WMI_SET_BITS(config_1, 8, 1, value) - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param.*/ @@ -4205,11 +3762,7 @@ typedef struct { * Bit 14 - Support for ML monitor mode * Bit 15 - Support for Qdata Tx LCE filter installation * Bit 16 - Support for MPDU stats per tx Nss capability - * Bits 19:17 - max number of ML STA BSS supported, range [0-7] - * Bits 22:20 - max number of ML SAP BSS supported, range [0-7] - * Bits 25:23 - total number of ML links supported, range [0-7] - * Bits 28:27 - extended rx peer metadata version capabilities - * Bits 31:29 - Reserved + * Bits 31:17 - Reserved */ A_UINT32 target_cap_flags; @@ -4300,54 +3853,6 @@ typedef struct { */ A_UINT32 supported_wifi_certified_generations; - /* - * max number of CFR filter groups supported by FW. - */ - A_UINT32 max_cfr_filter_groups_supp; - - /* - * The maximum number of supported SAM Peer/MSDUQ/MPDUQ elements. This does - * NOT indicate the support limits for the HW, but rather the FW limit. - * Some FW targets may not support the maximum HW capability. - * - * When the host allocates the associated SAM data structure, it should do - * so with IDs strictly less than the limit indicated below. For example if - * only 64 SAM Peers are supported by a target, then only SAM Peer IDs 0-63 - * should be utilized. - * - * If a target does not support utilizing SAM, all of these SAM - * configuration values will be 0. - */ - union { - struct { - A_UINT32 num_supported_sam_peer : 12; /* bits 0:11 */ - A_UINT32 num_supported_sam_msduq : 13; /* bits 12:24 */ - A_UINT32 sam_reserved_1 : 7; /* bits 25:31 */ - A_UINT32 num_supported_sam_mpduq : 12; /* bits 0:11 */ - A_UINT32 sam_reserved_2 : 20; /* bits 12:31 */ - }; - struct { - A_UINT32 sam_capability_1; - A_UINT32 sam_capability_2; - }; - }; - - /* - * UHR MAC Capabilities: total WMI_MAX_UHRCAP_MAC_SIZE*A_UINT32 bits - * those bits actually are max mac capabilities = cap_mac_2g | cap_mac_5g - * The actual cap mac info per mac (2g/5g) in the TLV -- - * WMI_MAC_PHY_CAPABILITIES_EXT2 - */ - A_UINT32 uhr_cap_mac_info[WMI_MAX_UHRCAP_MAC_SIZE]; - - /* - * UHR DBE Capability Parameters: - * total WMI_MAX_UHRCAP_DBE_SIZE * A_UINT32 bits - * Present only when DBE Support bit (B10) in uhr_cap_mac_info is set. - * Carries DBE Maximum Supported Bandwidth and optional EHT-MCS Maps. - */ - A_UINT32 uhr_cap_dbe_info[WMI_MAX_UHRCAP_DBE_SIZE]; - /* Followed by next TLVs: * WMI_DMA_RING_CAPABILITIES dma_ring_caps[]; * wmi_spectral_bin_scaling_params wmi_bin_scaling_params[]; @@ -4355,18 +3860,10 @@ typedef struct { * WMI_HAL_REG_CAPABILITIES_EXT2 hal_reg_caps[]; * wmi_nan_capabilities nan_cap; * WMI_SCAN_RADIO_CAPABILITIES_EXT2 wmi_scan_radio_caps[]; - * wmi_twt_caps_params twt_caps[]; * wmi_htt_msdu_idx_to_htt_msdu_qtype htt_msdu_idx_to_qtype_map[]; * wmi_dbs_or_sbs_cap_ext dbs_or_sbs_cap_ext; - * wmi_cust_bdf_version_capabilities cust_bdf_version_capabilities[]; - * wmi_sw_cal_ver_cap sw_cal_ver_cap[]; * A_INT32 hw_tx_power_signed[WMI_HW_TX_POWER_CAPS_MAX]; - * WMI_COEX_FIX_CHANNEL_CAPABILITIES coex_fix_channel_caps[]; * wmi_aux_dev_capabilities aux_dev_caps[]; - * wmi_enhanced_aoa_caps_param aoa_caps_param[]; - * wmi_enhanced_aoa_per_band_caps_param - * aoa_per_band_caps_param[]; - * wmi_sar_flag_tlv_param sar_flags[]; * WMI_POWER_BOOST_CAPABILITIES power_boost_capabilities[]; * WMI_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES * rssi_accuracy_improvement_capabilities[]; @@ -4374,10 +3871,6 @@ typedef struct { * wifi_radar_ltf_length_capabilities[]; * wmi_wifi_radar_chain_capabilities * wifi_radar_chain_capabilities[]; - * WMI_MAC_PHY_CAPABILITIES_EXT2 mac_phy_caps2[]; - * wmi_shared_mem_model_tbtt_count_down_config - * wmi_shared_mem_model_tbtt_count_down_config[]; - * wmi_rtt_peer_meas_capabilities rtt_peer_meas_caps[]; */ } wmi_service_ready_ext2_event_fixed_param; @@ -5340,24 +4833,8 @@ typedef struct { * 11 -> reserved * Refer to the below WMI_RSRC_CFG_FLAGS2_OPTIMIZE_POWER_GET/SET * macros. - * Bit 25 - enable recv_bcn_stats feature - * 0 -> disable the feature - * 1 -> enable the feature - * Refer to below WMI_RSRC_CFG_FLAGS2_RECV_BCN_STATS_ENABLED_GET/SET - * macros. - * Bits 28:26 - extension bits for specifing the format version of the - * rx peer metadata the target needs to use (to cover versions V2 and - * beyond). - * Bit 29 - enable ipi_stats feature: - * 0 -> disable the feature - * 1 -> enable the feature - * Refer to below WMI_RSRC_CFG_FLAGS2_IPI_STATS_ENABLED_GET/SET macros. - * Bit 30 - enable pcie_oob_wakeup feature: - * 0 -> disable the feature - * 1 -> enable the feature - * Refer to below WMI_RSRC_CFG_FLAGS2_PCIE_OOB_WAKEUP_GET/SET macros. * - * Bit 31 - Reserved + * Bits 31:25 - Reserved */ A_UINT32 flags2; /** @brief host_service_flags - can be used by Host to indicate @@ -5481,69 +4958,7 @@ typedef struct { * So FW will start refilling the buffers. * Refer to the below definitions of WMI_RSRC_CFG_HOST_SERVICE_FLAG * OPT_DP_CTRL_REPLENISH_REFILL_RX_BUFFER_SUPPORT_GET and _SET macros. - * Bit 18 - * This bit will be set by host to inform FW that VBSS feature is - * enabled. - * Bit 19 - * This bit will set by host to inform FW that the bypass approach - * for HLOS TID OVERRIDE feature not working needs to be supported, - * So FW will start handling the PPE2TCL enqueued packets with - * flow_override set. - * Refer to the below definitions of WMI_RSRC_CFG_HOST_SERVICE_FLAG - * OPT_DP_ENABLE_BYPASS_FOR_HLOS_TID_OVERRIDE_GET and _SET macros. - * Bit 20 - * This bit will set by host to inform FW that action OUI v2 is - * enabled by both host configuration and FW capability. - * Refer to the below definitions of - * WMI_RSRC_CFG_HOST_SERVICE_FLAG_ACTION_OUI_V2_GET and SET. - * Bit 21 - * This bit will be set by host to inform FW that HW blacklist - * channel is supported in host. Based on this flag, FW will do - * CTL generation for all the IEEE channels allowed in the VLP - * and SP power for the current county and update host in the - * below WMI Events: - * WMI_REG_CHAN_LIST_CC_EXT_EVENTID, WMI_AFC_EVENTID, and - * WMI_HW_BLACKLIST_CHAN_EVENTID - * Bit 22 - * This bit will be set by host to inform FW that AFC handling - * is supported in the default cc event id. Based on this flag, - * FW will send the AFC event in the default cc event id if the - * country supports SP regulatory rules. - * Refer to the below defintions of WMI_RSRC_CFG_HOST_SERVICE_FLAG - * AFC_TRIGGER_ON_DEFAULT_CC_EVENT_GET and _SET macros. - * Bit 23 - * This bit will set by host to inform FW that direct refill to - * SW2RxDMA ring is supported by the host and the ring which is - * directly refilled by HOST will be indicated in the - * HTT_H2T_MSG_TYPE_SRING_SETUP and FW should refill the Rx buffers - * to the secondary refill ring. - * Refer to the below definitions of WMI_RSRC_CFG_HOST_SERVICE_FLAG - * DIRECT_REFILL_SUPPORT_GET and _SET macros. - * Bit 24 - * This bit will be set by host to inform FW that HOST will be - * expecting and will be able to handle DCS stats event sent - * by FW for concurrent vdevs (event can support max 2 vdevs data). - * Bit 25 - * This bit will be set by host to inform FW that HOST will support - * SMD BSS transition. - * Refer to the below definitions of - * WMI_RSRC_CFG_HOST_SERVICE_FLAG_SMD_BSS_TRANSITION_GET and _SET - * macros. - * Bit 26 - * This bit will be set by host to inform FW that the rx management - * path directly to the host is enabled, so the FW need not forward - * rx mgmt frames to the host. - * Refer to the below definitions of - * WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_RX_MGMT_DIRECT_ENABLE_GET and - * _SET macros. - * Bit 27 - * This bit will be set by host to inform FW that the CUMAC_CMD_ID - * will come post WMI_INIT_CMDID and the MLO_SRNG setup has to be - * done as part of this cmd. - * Refer to the below definitions of - * WMI_RSRC_CFG_HOST_SERVICE_FLAG_CUMAC_CMD_SUPPORT_GET and SET_macros. - * - * Bits 31:28 - Reserved + * Bits 31:18 - Reserved */ A_UINT32 host_service_flags; @@ -5660,93 +5075,8 @@ typedef struct { * BIT 6 : 31 Reserved */ A_UINT32 c2c_int_type_config; - - /** - * @brief apf_data_ofld_enable - * BIT 0 -> enable/disable offload support in apf - * @detail: This flag will indicate during init time - * based on the vendor img version if APF is supporting - * any offloads. - * BIT 1 : 31 Reserved - */ - union { - A_UINT32 apf_data_ofload_enable__word; - struct { - A_UINT32 - apf_data_ofld_enable: 1, - reserved: 31; - }; - }; - /** - * @brief HAPS flags setting for power save config - * bit 0 : Enable disable haps feature - * bit 1 : Sync and update qtime cnss timestamp - * BIT 2-31: Reserved - */ - A_UINT32 dp_haps_config; - - /** - * @brief nan_config_word - * BIT 0 : 7 -> Minimum lead time (in milliseconds) that firmware - * must ensure before sending WMI_NAN_NEXT_DW_INFO_EVENTID, - * as configured via host INI settings. - * BIT 8 : 31 -> Reserved - */ - union { - A_UINT32 nan_config_word; - struct { - A_UINT32 - dw_notif_lead_time: 8, - /* enable supplicant based NAN offload mode */ - enable_nan_ofld_mode: 1, - /* disable/enable temporal IOT mode */ - enable_temporal_iot_mode: 1, - reserved2: 22; - }; - }; } wmi_resource_config; -#define WMI_RSRC_CFG_APF_DATA_OFLD_ENABLE_GET(word32) \ - WMI_GET_BITS(word32, 0, 1) -#define WMI_RSRC_CFG_APF_DATA_OFLD_ENABLE_SET(word32, value) \ - WMI_SET_BITS(word32, 0, 1, value) - -#define WMI_RSRC_CFG_NAN_CONFIG_DW_NOTIF_LEAD_TIME_GET(word32) \ - WMI_GET_BITS(word32, 0, 8) -#define WMI_RSRC_CFG_NAN_CONFIG_DW_NOTIF_LEAD_TIME_SET(word32, value) \ - WMI_SET_BITS(word32, 0, 8, value) - -#define WMI_RSRC_CFG_NAN_CONFIG_ENABLE_NAN_OFLD_MODE_GET(word32) \ - WMI_GET_BITS(word32, 8, 1) -#define WMI_RSRC_CFG_NAN_CONFIG_ENABLE_NAN_OFLD_MODE_SET(word32, value) \ - WMI_SET_BITS(word32, 8, 1, value) - -#define WMI_RSRC_CFG_NAN_CONFIG_ENABLE_NAN_TEMPORAL_IOT_MODE_GET(word32) \ - WMI_GET_BITS(word32, 9, 1) -#define WMI_RSRC_CFG_NAN_CONFIG_ENABLE_NAN_TEMPORAL_IOT_MODE_SET(word32, value) \ - WMI_SET_BITS(word32, 9, 1, value) - - -/* - * WMI_NAN_DISC_COOKIE_GET / WMI_NAN_DISC_COOKIE_SET - * - * Accessor macros for the 64-bit cookie value split across - * cookie_low32 and cookie_high32 fields in WMI NAN disc structs. - * - * Usage (read): - * A_UINT64 c = WMI_NAN_DISC_COOKIE_GET(p->cookie_low32, p->cookie_high32); - * - * Usage (write): - * WMI_NAN_DISC_COOKIE_SET(p->cookie_low32, p->cookie_high32, my_cookie); - */ -#define WMI_NAN_DISC_COOKIE_GET(low32, high32) \ - (((A_UINT64)(high32) << 32) | (A_UINT64)(low32)) -#define WMI_NAN_DISC_COOKIE_SET(low32, high32, cookie64) \ - do { \ - (low32) = (A_UINT32)((cookie64) & 0xFFFFFFFFUL); \ - (high32) = (A_UINT32)(((cookie64) >> 32) & 0xFFFFFFFFUL); \ - } while (0) - #define WMI_MSDU_FLOW_AST_ENABLE_GET(msdu_flow_config0, ast_x) \ (((ast_x) == 0) ? 1 : ((msdu_flow_config0) & (1 << ((ast_x) - 1)))) #define WMI_MSDU_FLOW_AST_ENABLE_SET(msdu_flow_config0, ast_x, enable) \ @@ -6039,26 +5369,6 @@ typedef struct { #define WMI_RSRC_CFG_FLAGS2_OPTIMIZE_POWER_SET(flags2, value) \ WMI_SET_BITS(flags2, 23, 2, value) -#define WMI_RSRC_CFG_FLAGS2_RECV_BCN_STATS_ENABLED_GET(flags2) \ - WMI_GET_BITS(flags2, 25, 1) -#define WMI_RSRC_CFG_FLAGS2_RECV_BCN_STATS_ENABLED_SET(flags2, value) \ - WMI_SET_BITS(flags2, 25, 1, value) - -#define WMI_RSRC_CFG_FLAGS2_RX_PEER_METADATA_EXTENSION_GET(flags2) \ - WMI_GET_BITS(flags2, 26, 3) -#define WMI_RSRC_CFG_FLAGS2_RX_PEER_METADATA_EXTENSION_SET(flags2, value) \ - WMI_SET_BITS(flags2, 26, 3, value) - -#define WMI_RSRC_CFG_FLAGS2_IPI_STATS_ENABLED_GET(flags2) \ - WMI_GET_BITS(flags2, 29, 1) -#define WMI_RSRC_CFG_FLAGS2_IPI_STATS_ENABLED_SET(flags2, value) \ - WMI_SET_BITS(flags2, 29, 1, value) - -#define WMI_RSRC_CFG_FLAGS2_PCIE_OOB_WAKEUP_GET(flags2) \ - WMI_GET_BITS(flags2, 30, 1) -#define WMI_RSRC_CFG_FLAGS2_PCIE_OOB_WAKEUP_SET(flags2, value) \ - WMI_SET_BITS(flags2, 30, 1, value) - #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \ WMI_GET_BITS(host_service_flags, 0, 1) @@ -6166,70 +5476,6 @@ typedef struct { #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_VBSS_ENABLED_SET(host_service_flags, val) \ WMI_SET_BITS(host_service_flags, 18, 1, val) -/* - * This bit is to inform that we need to enable the bypass approach - * (for HLOS TID override feature not working in the target) - * to handle flowq creation from FW when flow override is set and - * frames are recvd from PPE2TCL. - * */ -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_OPT_DP_ENABLE_BYPASS_FOR_HLOS_TID_OVERRIDE_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 19, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_OPT_DP_ENABLE_BYPASS_FOR_HLOS_TID_OVERRIDE_SET(host_service_flags, val) \ - WMI_SET_BITS(host_service_flags, 19, 1, val) - -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_ACTION_OUI_V2_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 20, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_ACTION_OUI_V2_SET(host_service_flags, val) \ - WMI_SET_BITS(host_service_flags, 20, 1, val) - -/* This bit is used to inform FW to send HW Blacklist channels to host */ -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_SUPPORT_HW_BLACKLIST_CHANNEL_SUPPORT_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 21, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_SUPPORT_HW_BLACKLIST_CHANNEL_SUPPORT_SET(host_service_flags, val) \ - WMI_SET_BITS(host_service_flags, 21, 1, val) - -/* This bit is used to inform FW to send AFC event ID in default CC event ID */ -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_AFC_TRIGGER_ON_DEFAULT_CC_EVENT_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 22, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_AFC_TRIGGER_ON_DEFAULT_CC_EVENT_SET(host_service_flags, val) \ - WMI_SET_BITS(host_service_flags, 22, 1, val) - -/* This bit is used to inform FW that HOST supports direct Rx buffers refill to the SW2RxDMA ring*/ -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_DIRECT_REFILL_SUPPORT_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 23, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_DIRECT_REFILL_SUPPORT_SET(host_service_flags, val) \ - WMI_SET_BITS(host_service_flags, 23, 1, val) - -/* This bit will be used to inform FW that HOST will be handling DCS stats for multiple vdevs (max 2) */ -#define WMI_RSRC_CFG_DCS_STATS_FOR_2VDEVS_ENABLE_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 24, 1) -#define WMI_RSRC_CFG_DCS_STATS_FOR_2VDEVS_ENABLE_SET(host_service_flags, value) \ - WMI_SET_BITS(host_service_flags, 24, 1, value) - -/* This bit will be used to inform FW that HOST enables SMD BSS transition */ -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_SMD_BSS_TRANSITION_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 25, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_SMD_BSS_TRANSITION_SET(host_service_flags, value) \ - WMI_SET_BITS(host_service_flags, 25, 1, value) - -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_RX_MGMT_DIRECT_ENABLE_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 26, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_RX_MGMT_DIRECT_ENABLE_SET(host_service_flags, value) \ - WMI_SET_BITS(host_service_flags, 26, 1, value) - -/* - * Bit 27: Host supports WMI_PDEV_SET_CUMAC_CHIP_CMDID. - * When set, FW will call the MLO CUMAC init function from the - * WMI_PDEV_SET_CUMAC_CHIP_CMDID handler instead of the MLO SoC init function. - * Requires WMI_SERVICE_PDEV_SET_CUMAC_CHIP_CMD_SUPPORT to be set in - * wmi_service_ready before the host sets this bit. - */ -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_CUMAC_CMD_SUPPORT_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 27, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_CUMAC_CMD_SUPPORT_SET(host_service_flags, val) \ - WMI_SET_BITS(host_service_flags, 27, 1, val) - - #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_GET(carrier_config) \ WMI_GET_BITS(carrier_config, 0, 1) #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_SET(carrier_config, val) \ @@ -6280,7 +5526,6 @@ typedef enum { WMI_WIFI_STANDARD_6 = 2, WMI_WIFI_STANDARD_6E = 3, WMI_WIFI_STANDARD_7 = 4, - WMI_WIFI_STANDARD_8 = 5, } WMI_WIFI_STANDARD; typedef enum { @@ -6304,8 +5549,6 @@ typedef enum { WMI_VENDOR1_REQ1_VERSION_4_10 = 6, WMI_VENDOR1_REQ1_VERSION_4_20 = 7, WMI_VENDOR1_REQ1_VERSION_4_40 = 8, - WMI_VENDOR1_REQ1_VERSION_4_50 = 9, - WMI_VENDOR1_REQ1_VERSION_4_60 = 10, } WMI_VENDOR1_REQ1_VERSION; typedef enum { @@ -6313,8 +5556,6 @@ typedef enum { WMI_VENDOR1_REQ2_VERSION_3_01 = 1, WMI_VENDOR1_REQ2_VERSION_3_20 = 2, WMI_VENDOR1_REQ2_VERSION_3_50 = 3, - WMI_VENDOR1_REQ2_VERSION_3_61 = 4, - WMI_VENDOR1_REQ2_VERSION_3_70 = 5, } WMI_VENDOR1_REQ2_VERSION; typedef enum { @@ -6721,10 +5962,6 @@ typedef struct { typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tlv_buf_len_param */ A_UINT32 buf_len; /** Length of buf */ -/* NOTE: - * This struct cannot be expanded, due to being used as - * WMITLV_TAG_ARRAY_FIXED_STRUC in WMI_ROAM_INVOKE_CMDID. - */ /** * Following this structure is the TLV byte stream of buf of length buf_len: * A_UINT8 buf[]; @@ -7048,18 +6285,16 @@ typedef struct { #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000 #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000 #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000 +/** pause home channel when scan channel is same as home channel */ +#define WMI_SCAN_FLAG_PAUSE_HOME_CHANNEL 0x200000 +/** + * report CCA busy for each possible 20Mhz subbands of the wideband scan channel + */ +#define WMI_SCAN_FLAG_REPORT_CCA_BUSY_FOREACH_20MHZ 0x400000 + /** for adaptive scan mode using 3 bits (21 - 23 bits) */ #define WMI_SCAN_DWELL_MODE_MASK 0x00E00000 #define WMI_SCAN_DWELL_MODE_SHIFT 21 -/** pause home channel when scan channel is same as home channel (bit 24) */ -#define WMI_SCAN_FLAG_PAUSE_HOME_CHANNEL 0x01000000 -/** - * report CCA busy for each possible 20MHz subband of the wideband scan channel - * (bit 25) - */ -#define WMI_SCAN_FLAG_REPORT_CCA_BUSY_FOREACH_20MHZ 0x02000000 -/* Premium scan to receive higher MCS packets in scan channel */ -#define WMI_SCAN_FLAG_PREMIUM_SCAN 0x04000000 typedef enum { WMI_SCAN_DWELL_MODE_DEFAULT = 0, @@ -7078,11 +6313,7 @@ typedef enum { #define WMI_SCAN_GET_DWELL_MODE(flag) \ (((flag) & WMI_SCAN_DWELL_MODE_MASK) >> WMI_SCAN_DWELL_MODE_SHIFT) -/** - * WMI_SCAN_CLASS_MASK must be the same value as IEEE80211_SCAN_CLASS_MASK - * This bitmask is used to set/get values of req_type variable in - * wmi_stop_scan_cmd_fixed_param. - */ +/** WMI_SCAN_CLASS_MASK must be the same value as IEEE80211_SCAN_CLASS_MASK */ #define WMI_SCAN_CLASS_MASK 0xFF000000 /* @@ -7414,37 +6645,6 @@ typedef struct { A_UINT32 flags; } wmi_scan_event_fixed_param; -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_suppress_cmd_fixed_param */ - - /** suppress_scan: - * set to 0: to enable scan - * set to 1: to suppress scan - */ - A_UINT32 suppress_scan; - /** Scan client id, refer to enum WMI_SCAN_CLIENT_ID */ - A_UINT32 scan_client_id; -} wmi_scan_suppress_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_scan_stats_cmd_fixed_param */ - - /** Scan client id, refer to enum WMI_SCAN_CLIENT_ID */ - A_UINT32 scan_client_id; -} wmi_get_scan_stats_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_stats_rsp_fixed_param */ - - /** Scan client id, refer to enum WMI_SCAN_CLIENT_ID */ - A_UINT32 scan_client_id; - /** scan_count: - * Total number of scans triggered/started for a given scan_clnt_id - * which is requested by scan stats command - */ - A_UINT32 scan_count; -} wmi_get_scan_stats_resp_fixed_param; - /* WMI Diag event */ typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag is WMITLV_TAG_STRUC_wmi_diag_event_fixed_param */ @@ -8403,9 +7603,6 @@ typedef struct { #define WMI_TX_SEND_FLAG_SET_P2P_FRAME_ON_STA_VDEV 0x00000008 #define WMI_TX_SEND_FLAG_SET_P2P_FRAME_ON_STA_VDEV_GET(tx_flags) WMI_GET_BITS(tx_flags, 3, 1) #define WMI_TX_SEND_FLAG_SET_P2P_FRAME_ON_STA_VDEV_SET(tx_flags, value) WMI_SET_BITS(tx_flags, 3, 1, value) -#define WMI_TX_SEND_FLAG_SET_SMD_HIGH_PRIORITY_FRAME 0x00000010 -#define WMI_TX_SEND_FLAG_SET_SMD_HIGH_PRIORITY_FRAME_GET(tx_flags) WMI_GET_BITS(tx_flags, 4, 1) -#define WMI_TX_SEND_FLAG_SET_SMD_HIGH_PRIORITY_FRAME_SET(tx_flags, value) WMI_SET_BITS(tx_flags, 4, 1, value) typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_send_params */ @@ -8751,45 +7948,6 @@ typedef struct { A_UINT32 scan_start; } wmi_pdev_scan_cmd; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_get_conc_info_cmd_fixed_param */ -} wmi_soc_get_conc_info_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_conc_info */ - - A_UINT32 vdev_id; - A_UINT32 type; /* interface type : WMI_VDEV_MODE */ - wmi_mac_addr bssid; - A_UINT32 freq; /* in MHz*/ - /* rssi value (in dBm) valid for STA vdev, for other INVALID_RSSI */ - A_INT32 rssi; -} wmi_conc_info; - -typedef enum { - WMI_VDEV_MODE_STA = 0, - WMI_VDEV_MODE_SAP = 1, - WMI_VDEV_MODE_MLO_STA = 2, - WMI_VDEV_MODE_MLO_SAP = 3, - WMI_VDEV_MODE_P2P_CLI = 4, - WMI_VDEV_MODE_P2P_GO = 5, - WMI_VDEV_MODE_NAN = 6, - WMI_VDEV_MODE_NDI = 7, - - WMI_VDEV_MODE_MAX -} WMI_VDEV_MODE; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_get_conc_info_resp_fixed_param */ - - /* - * Following this fixed_param TLV is a variable-length TLV array: - * wmi_conc_info conc_info_list[]; - */ -} wmi_soc_get_conc_info_resp_fixed_param; - - /* WMI support for setting ratemask in target */ typedef struct { @@ -9050,14 +8208,6 @@ typedef struct { A_UINT32 sw_retry_th; /* max retry count per AC base on ac_type for the vdev mentioned in vdev id*/ } wmi_vdev_set_custom_sw_retry_th_cmd_fixed_param; -typedef enum { - /* Set when user forces the chainmask config */ - WMI_FORCE_CHM_MODE_USER_FORCE = 0, - - /* Set when there is no user force */ - WMI_FORCE_CHM_MODE_DEFAULT_CONFIG = 1, -} WMI_FORCE_CHM_MODE; - typedef struct { /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_chainmask_config_cmd_fixed_param */ A_UINT32 tlv_header; @@ -9100,7 +8250,6 @@ typedef struct { A_UINT32 fast_chain_selection; /* RSSI delta threshold to determine better chain, units: dB */ A_UINT32 better_chain_rssi_threshold; - A_UINT32 force_mode; /* holds a WMI_FORCE_CHM_MODE enum value */ } wmi_vdev_chainmask_config_cmd_fixed_param; /* @@ -9609,11 +8758,6 @@ typedef enum { WMI_SCHED_MODE_UL_OFDMA = 0x00000008, } WMI_SCHED_MODE_FLAGS; -typedef enum { - WMI_PDEV_PARAM_TEMP_TX_POWER_LIMIT_RESET = 0, - WMI_PDEV_PARAM_TEMP_TX_POWER_LIMIT_SET, -} wmi_pdev_param_set_temp_tx_power_limit; - typedef enum { /** TX chain mask */ WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, @@ -10799,67 +9943,6 @@ typedef enum { /* To enable/disable DFS radar detection for scan radio */ WMI_PDEV_PARAM_ENABLE_SCAN_RADIO_DFS, - - /* configure CCE rules based on ethertype match */ - WMI_PDEV_PARAM_CONFIG_CUSTOM_CCE_RULE, - - /* temporary tx power limit */ - WMI_PDEV_PARAM_TEMP_TX_POWER_LIMIT, - - /* configure pdev coex stats period (millisecond units) */ - WMI_PDEV_PARAM_COEX_STATS_UPDATE_PERIOD, - - /* To enable/disable XPAN SAP + STA power optimization */ - WMI_PDEV_PARAM_XPAN_STA_PWRSAVE_ENABLE, - - /** Beacon antenna for smart antenna */ - WMI_PDEV_PARAM_SMART_ANTENNA_BEACON_ANTENNA, - - /* - * The extra early rx duration (in usec units) when - * adaptive early rx is disabled - */ - WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_EXTRA_SLEEP_SLOP, - - /* Set TAS mode after boot up */ - WMI_PDEV_PARAM_SET_TAS_MODE, - - WMI_PDEV_PARAM_L3_HEADER_PADDING_ENABLE, - - /* To enable/ disable beacon LIO update based on screen on/off */ - WMI_PDEV_PARAM_BEACON_LIO_UPDATE_ON_SCREEN_ON_OFF, - - /** - * Configure the CSA wait timeout (in ms) before blocking TX - * after radar detection - */ - WMI_PDEV_PARAM_DFS_NOL_CSA_WAIT_TIMEOUT, - - /** - * Smart antenna MPDU MCS params config. - * bit | purpose - * ------|--------- - * 0:9 | Max MPDU count for training - * 10 | MCS margin enable (0: disable, 1: enable) - * 11:13 | MCS margin value - * 14:31 | Reserved - */ - WMI_PDEV_PARAM_SMART_ANTENNA_CONFIG_MPDU_MCS_PARAMS, - - /** On-demand AWGN interference status request. - * FW reads awgn_prev_int_seg and sends WMI_DCS_INTERFERENCE_EVENTID - * with interference_type=ATH_CAP_DCS_AGWNIM only if interference is - * currently detected (bitmap != 0). A bitmap of 0 means no interference. - * param_value is reserved (set to 1 to trigger the request). - */ - WMI_PDEV_PARAM_AWGN_INT_STATUS_REQUEST, - - /** - * Disable L3 validity check in offload manager. - * 0 - L3_valid check enabled (default) - * 1 - L3_valid check disabled (frames not dropped on L3_valid=false) - */ - WMI_PDEV_PARAM_ENABLE_OFFLD_L3_VALID_CHECK, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) @@ -10944,8 +10027,6 @@ typedef enum { #define WMI_PDEV_UPPER_CAP_DL_DIR_SET(_value, value) WMI_SET_BITS(_value, 18, 1, value) #define WMI_PDEV_UPPER_CAP_UL_DIR_GET(value) WMI_GET_BITS(value, 19, 1) #define WMI_PDEV_UPPER_CAP_UL_DIR_SET(_value, value) WMI_SET_BITS(_value, 19, 1, value) -#define WMI_PDEV_UPPER_CAP_DIR_GET(value) WMI_GET_BITS(value, 18, 1) -#define WMI_PDEV_UPPER_CAP_DIR_SET(_value, value) WMI_SET_BITS(_value, 18, 1, value) #define WMI_PDEV_RATE_DROP_NUM_MCS_GET(value) WMI_GET_BITS(value, 0, 8) #define WMI_PDEV_RATE_DROP_NUM_MCS_SET(_value, value) WMI_SET_BITS(_value, 0, 8, value) @@ -10966,22 +10047,6 @@ typedef enum { #define WMI_PDEV_RATE_MAX_NSS_PROBE_INTERVAL_GET(value) WMI_GET_BITS(value, 16, 16) #define WMI_PDEV_RATE_MAX_NSS_PROBE_INTERVAL_SET(_value, value) WMI_SET_BITS(_value, 16, 16, value) -/* WMI GET/SET macros for WMI_PDEV_PARAM_SMART_ANTENNA_CONFIG_MPDU_MCS_PARAMS */ -#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MAX_TRAIN_MPDU_GET(param) \ - WMI_GET_BITS(param, 0, 10) -#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MAX_TRAIN_MPDU_SET(_param, value) \ - WMI_SET_BITS(_param, 0, 10, value) - -#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MCS_MARGIN_EN_GET(param) \ - WMI_GET_BITS(param, 10, 1) -#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MCS_MARGIN_EN_SET(_param, value) \ - WMI_SET_BITS(_param, 10, 1, value) - -#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MCS_MARGIN_VAL_GET(param) \ - WMI_GET_BITS(param, 11, 3) -#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MCS_MARGIN_VAL_SET(_param, value) \ - WMI_SET_BITS(_param, 11, 3, value) - #define WMI_MBSSID_CTRL_FRAME_BASIC_TRIGGER ((A_UINT32) 1 << 0) #define WMI_MBSSID_CTRL_FRAME_BSR_TRIGGER ((A_UINT32) 1 << 1) #define WMI_MBSSID_CTRL_FRAME_MU_RTS_TRIGGER ((A_UINT32) 1 << 2) @@ -11056,23 +10121,6 @@ typedef struct { A_UINT32 param; } wmi_pdev_get_tpc_config_cmd_fixed_param; -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_tpc_ie_power_cmd_fixed_param */ - A_UINT32 vdev_id; - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - A_UINT32 mgmt_rate; /* Values are sent as Ratecode */ -} wmi_vdev_get_tpc_ie_power_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 pdev_id; - A_INT32 tx_pwr; /* return value will be in unit of 0.25 dBm */ -} wmi_vdev_tpc_ie_power_event_fixed_param; - typedef struct { A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_pdev_div_get_rssi_antid_fixed_param */ /** pdev_id for identifying the MAC */ @@ -11483,21 +10531,6 @@ typedef struct { * ack_rssi is reported in dBm. */ A_INT32 ack_rssi; - - /* ieee_link_id_valid: - * For MLO cases, ieee_link_id_valid is set to 1, which indicates that - * the ieee_link_id field contains a valid value. - * For non-MLO and legacy cases, ieee_link_id_valid is set to 0, which - * means ignore the ieee_link_id field. - */ - A_UINT32 ieee_link_id_valid; - /* ieee_link_id: - * For MLO cases, this indicates the link on which the QoS Null frame - * is sent. - * For non-MLO cases, this is not required because the QoS Null frame - * is sent on the connected link. - */ - A_UINT32 ieee_link_id; } wmi_qos_null_frame_tx_compl_event_fixed_param; typedef struct { @@ -11567,16 +10600,6 @@ typedef struct { */ } wmi_pdev_tpc_config_event_fixed_param; - -typedef enum { - WMI_ASD_PRIMARY_ANT = 0, - WMI_ASD_DIVERSITY_ANT = 1, - WMI_ASD_THIRD_ANT = 2, - WMI_ASD_FOURTH_ANT = 3, - - WMI_ASD_MAX_ANTTYPE = 4 -} WMI_ASD_ANT_TYPE; - typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_div_rssi_antid_event_fixed_param */ A_UINT32 tlv_header; @@ -11590,17 +10613,6 @@ typedef struct { wmi_mac_addr macaddr; /* EVM value for stream0 and stream1 20Mhz, dB units */ A_INT32 chain_evm[WMI_MAX_CHAINS]; - /** num_antennas_valid: - * how many elements in the WMI_ASD_MAX_ANTTYPE arrays below - * contain valid info - */ - A_UINT32 num_antennas_valid; - /** switch count on each antenna attached to each chain */ - A_UINT32 ant_cnt[WMI_MAX_CHAINS][WMI_ASD_MAX_ANTTYPE]; - /** stay duration on each antenna attached to each chain (units: ms) */ - A_UINT32 ant_dur[WMI_MAX_CHAINS][WMI_ASD_MAX_ANTTYPE]; - /** RSSI on each antenna attached to each chain in dbm */ - A_INT32 ant_rssi[WMI_MAX_CHAINS][WMI_ASD_MAX_ANTTYPE]; } wmi_pdev_div_rssi_antid_event_fixed_param; typedef struct { @@ -11959,7 +10971,7 @@ typedef enum { } MCAST_BCAST_RATE_ID; typedef struct { - A_UINT32 rate_id; /* MCAST_BCAST_RATE_ID */ + MCAST_BCAST_RATE_ID rate_id; A_UINT32 rate; } mcast_bcast_rate; @@ -12023,27 +11035,25 @@ typedef struct { } wmi_vdev_get_twt_session_stats_info_cmd_fixed_param; typedef enum { - WMI_REQUEST_PEER_STAT = 0x000001, - WMI_REQUEST_AP_STAT = 0x000002, - WMI_REQUEST_PDEV_STAT = 0x000004, - WMI_REQUEST_VDEV_STAT = 0x000008, - WMI_REQUEST_BCNFLT_STAT = 0x000010, - WMI_REQUEST_VDEV_RATE_STAT = 0x000020, - WMI_REQUEST_INST_STAT = 0x000040, - WMI_REQUEST_MIB_STAT = 0x000080, - WMI_REQUEST_RSSI_PER_CHAIN_STAT = 0x000100, - WMI_REQUEST_CONGESTION_STAT = 0x000200, - WMI_REQUEST_PEER_EXTD_STAT = 0x000400, - WMI_REQUEST_BCN_STAT = 0x000800, - WMI_REQUEST_BCN_STAT_RESET = 0x001000, - WMI_REQUEST_PEER_EXTD2_STAT = 0x002000, - WMI_REQUEST_MIB_EXTD_STAT = 0x004000, - WMI_REQUEST_PMF_BCN_PROTECT_STAT = 0x008000, - WMI_REQUEST_VDEV_EXTD_STAT = 0x010000, - WMI_REQUEST_PDEV_EXTD_STAT = 0x020000, - WMI_REQUEST_PDEV_TELEMETRY_STAT = 0x040000, - WMI_REQUEST_VDEV_RECV_BCN_STAT = 0x080000, - WMI_REQUEST_PDEV_COEX_STAT = 0x100000, + WMI_REQUEST_PEER_STAT = 0x00001, + WMI_REQUEST_AP_STAT = 0x00002, + WMI_REQUEST_PDEV_STAT = 0x00004, + WMI_REQUEST_VDEV_STAT = 0x00008, + WMI_REQUEST_BCNFLT_STAT = 0x00010, + WMI_REQUEST_VDEV_RATE_STAT = 0x00020, + WMI_REQUEST_INST_STAT = 0x00040, + WMI_REQUEST_MIB_STAT = 0x00080, + WMI_REQUEST_RSSI_PER_CHAIN_STAT = 0x00100, + WMI_REQUEST_CONGESTION_STAT = 0x00200, + WMI_REQUEST_PEER_EXTD_STAT = 0x00400, + WMI_REQUEST_BCN_STAT = 0x00800, + WMI_REQUEST_BCN_STAT_RESET = 0x01000, + WMI_REQUEST_PEER_EXTD2_STAT = 0x02000, + WMI_REQUEST_MIB_EXTD_STAT = 0x04000, + WMI_REQUEST_PMF_BCN_PROTECT_STAT = 0x08000, + WMI_REQUEST_VDEV_EXTD_STAT = 0x10000, + WMI_REQUEST_PDEV_EXTD_STAT = 0x20000, + WMI_REQUEST_PDEV_TELEMETRY_STAT = 0x40000, } wmi_stats_id; /* @@ -12061,7 +11071,7 @@ typedef struct { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_request_stats_cmd_fixed_param */ - A_UINT32 stats_id; /* wmi_stats_id */ + wmi_stats_id stats_id; /** unique id identifying the VDEV, generated by the caller */ A_UINT32 vdev_id; /** peer MAC address */ @@ -12753,77 +11763,6 @@ typedef struct { A_UINT32 tot_err_tim_bcn; } wmi_iface_powersave_stats; - -#define WMI_IPI_STATS_SNR_LOWER_BOUND_GET(snr_config) \ - WMI_GET_BITS(snr_config, 0, 8) -#define WMI_IPI_STATS_SNR_LOWER_BOUND_SET(snr_config, value) \ - WMI_SET_BITS(snr_config, 0, 8, value) -#define WMI_IPI_STATS_SNR_UPPER_BOUND_GET(snr_config) \ - WMI_GET_BITS(snr_config, 8, 8) -#define WMI_IPI_STATS_SNR_UPPER_BOUND_SET(snr_config, value) \ - WMI_SET_BITS(snr_config, 8, 8, value) -#define WMI_IPI_STATS_SNR_STEP_GET(snr_config) \ - WMI_GET_BITS(snr_config, 16, 8) -#define WMI_IPI_STATS_SNR_STEP_SET(snr_config, value) \ - WMI_SET_BITS(snr_config, 16, 8, value) -#define WMI_IPI_STATS_SNR_NUM_BINS_GET(snr_config) \ - WMI_GET_BITS(snr_config, 24, 8) -#define WMI_IPI_STATS_SNR_NUM_BINS_SET(snr_config, value) \ - WMI_SET_BITS(snr_config, 24, 8, value) - -/* - * Signal to Noise Ration(SNR) is measured during idle periods and reported - * as a distribution across multiple bins - */ -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_iface_ipi_stats */ - - /* - * Total time in microseconds spent on the channel during which - * these signal-to-noise measurements were collected - */ - A_UINT32 meas_dur_us; - - /* snr_config: - * Contains lower bound, upper bound, step value and total bins for the - * SNR measurements done. - * Firmware collects the SNR data into - * (((upper_bound - lower_bound)/step) + out_of_bound_bins) - * bins and sends to host. - * lower_bound - Lower value of the SNR measurement range - * upper_bound - Upper value of the SNR measurement range - * step - Each bin data range - * num_bins - Number of bins calculated as per above formula, - * represents the number of elements in TLV snr_histogram - * out_of_bound_bins(=2) - Number of bins to carry values below lower - * bound and above upper bound in corresponding bin, - * including lower and upper bound values - * E.g - 1. lower_bound = 0, upper_bound = 100 and step = 10 - * Firmware collects the SNR samples into ((100-0)/10)+2 = 12 bins - * E.g - 2. lower_bound = 10, upper_bound = 90 and step = 20 - * Firmware collects the SNR samples into ((90-10)/20)+2 = 6 bins - */ - A_UINT32 snr_config; - - /* - * This TLV is followed by a snr_histogram TLV containing a variable-length - * array of A_UINT32 to carry data from each bin. - * Bin[0] contains the number of samples with SNR < lower_bound dB - * Bin[1] contains the number of samples with SNR in range - * [lower_bound, lower_bound + step) dB - * Bin[2] contains the number of samples with SNR in range - * [lower_bound + step, lower_bound + 2*step) dB - * ... - * Bin[num_bins - 2] contains the number of samples with SNR in range - * [upper_bound - step, upper_bound) dB - * Bin[num_bins - 1] contains the number of samples with - * SNR >= upper_bound dB - * - * A_UINT32 snr_histogram[num_bins] - */ -} wmi_iface_ipi_stats; - - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ipa_link_stats */ @@ -13037,7 +11976,7 @@ typedef struct { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stats_event_fixed_param */ - A_UINT32 stats_id; /* wmi_stats_id */ + wmi_stats_id stats_id; /** number of pdev stats event structures (wmi_pdev_stats) 0 or 1 */ A_UINT32 num_pdev_stats; /** number of vdev stats event structures (wmi_vdev_stats) 0 or max vdevs */ @@ -13105,14 +12044,6 @@ typedef struct { * wmi_pdev_telemetry_stats wmi_pdev_telemetry_stats[] * follows the other TLVs */ -/* If WMI_REQUEST_VDEV_RECV_BCN_STAT is set in stats_id, then TLV - * wmi_recv_bcn_stats wmi_recv_bcn_stats[] - * follows the other TLVs - */ -/* If WMI_REQUEST_PDEV_COEX_STAT is set in stats_id, then TLV - * wmi_pdev_coex_stats wmi_pdev_coex_stats[] - * follows the other TLVs - */ } wmi_stats_event_fixed_param; /* WLAN channel CCA stats bitmap */ @@ -13614,20 +12545,8 @@ typedef struct { * * b'31-b'29 unused / reserved * b'28 indicate the version of rate-code (1 = RATECODE_V1) - * b'27 unused / reserved - * b'26-b'19 indicate TX power (int8), with 0.25 dBm units - * b'15-b'14 indicate punctured mode as follows: - * 0: NO_PUNCTURE - * 1: PUNCTURED_20MHZ - * 2: PUNCTURED_40MHZ - * 3: PUNCTURED_80MHZ - * 4: PUNCTURED_120MHZ - * b'15-b'14 indicate the guard interval: - * 0: 800us, 1: 400us, 2: 1600us, 3: 3200us - * b'13-b'11 indicate the bandwidth: - * 0: 20MHz, 1: 40MHz, 2: 80MHz, 3: 160MHz, 4: 320MHz - * b'10-b'8 indicate the preamble: - * 0: OFDM, 1: CCK, 2: HT, 3: VHT, 4: HE, 5: EHT + * b'27-b'11 unused / reserved + * b'10-b'8 indicate the preamble (0 OFDM, 1 CCK, 2 HT, 3 VHT) * b'7-b'5 indicate the NSS (0 - 1x1, 1 - 2x2, 2 - 3x3, 3 - 4x4) * b'4-b'0 indicate the rate, which is indicated as follows: * OFDM : 0: OFDM 48 Mbps @@ -13650,9 +12569,6 @@ typedef struct { * 0..7: MCS0..MCS7 (HT) * 0..9: MCS0..MCS9 (11AC VHT) * 0..11: MCS0..MCS11 (11AX VHT) - * HE/EHT (pream == 4/5) - * 0..13: MCS0..MCS13 (11AX EHT) - * 14..15: MCS14..MCS15 (EHT) */ /** rate-code of the last transmission */ A_UINT32 last_tx_rate_code; @@ -13776,240 +12692,224 @@ typedef struct { * number of vdev active count * (WMI_PDEV_STATS_VDEV_UP_CNT_SET,GET) */ - A_UINT32 opaque_debug_num_macs_phy_vdev_up_active; - /** refer wlan_pdev ic flags */ - A_UINT32 opaque_debug_ic_flags; - /** vdev_id that are paused per pdev */ - A_UINT32 opaque_debug_paused_ap_vdev_bitmap; - /** opaque_debug_flags: - * refer to WLAN_PS_DESC_BIN_HWM_HIT or WLAN_PS_DESC_BIN_LWM_HIT - */ - A_UINT32 opaque_debug_flags; - /** wlan_pdev fields remote_peer_cnt, max_rf_chains_2G and max_rf_chains_5G - * remote_peer_cnt_max_rf_chains_2G_5G: - * This word contains the following bitfields: - * max chains supported in the 2.4 GHz band - * (WMI_PDEV_STATS_MAX_RF_CHAIN_2G_SET,GET) - * max chains supported in the 5 GHz band, - * (WMI_PDEV_STATS_MAX_RF_CHAIN_5G_SET,GET) - * number of remote peers - * (WMI_PDEV_STATS_REMOTE_PEER_CNT_SET,GET) - */ - A_UINT32 opaque_debug_remote_peer_cnt_max_rf_chains_2G_5G; - /** wlan_pdev max HT Capability info, WMI_HT_CAP defines */ - A_UINT32 opaque_debug_max_ht_cap_info; - /** wlan_pdev max VHT capability info, WMI_VHT_CAP defines */ - A_UINT32 opaque_debug_max_vht_cap_info; - /** opaque_debug_max_vht_supp_mcs: - * wlan_pdev max VHT Supported MCS which is - * vht_supp_mcs_2G or vht_supp_mcs_5G - */ - A_UINT32 opaque_debug_max_vht_supp_mcs; - /** wlan_pdev max HE capability info, WMI_HE_CAP defines */ - A_UINT32 opaque_debug_max_he_cap_info; - A_UINT32 opaque_debug_max_he_cap_info_ext; - /** the nominal chain mask for transmit */ - A_UINT32 opaque_debug_tx_chain_mask; - /** the nominal chain mask for receive */ - A_UINT32 opaque_debug_rx_chain_mask; - /** opaque_debug_ema_flags: - * This word contains the following bitfields: - * ema_flags: ema_max_vap_cnt and ema_max_profile_period from wlan_pdev - * ema_max_vap_cnt- number of maximum EMA Tx vaps (VAPs having both - * VDEV_FLAGS_EMA_MODE and VDEV_FLAGS_TRANSMIT_AP set) - * (WMI_PDEV_STATS_EMA_MAX_VAP_CNT_SET,GET) - * ema_max_profile_period - maximum profile periodicity - * (maximum number of beacons after which VAP profiles repeat) - * for any EMA VAP on any pdev. - * (WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_SET,GET) - */ - A_UINT32 opaque_debug_ema_flags; - /** wlan_pdev - maximum ML peers supported */ - A_UINT32 opaque_debug_num_ml_peer_entries; - /** This word contains the following bitfields: - * wlan_pdev fields - num_max_hw_links, current_chip_id and max_num_chips - * (related to MLO) - * Max number of HW links - * (WMI_PDEV_STATS_NUM_MAX_HW_LINKS_SET,GET) - * Current Chip Id - * (WMI_PDEV_STATS_CURRENT_CHIP_ID_SET,GET) - * Max number of chips - * (WMI_PDEV_STATS_MAX_NUM_CHIPS_SET,GET) - */ - A_UINT32 opaque_debug_mlo_flags; - /** Indicate beacon size in bytes */ - A_UINT32 opaque_debug_large_bcn_size; - /** proposed by the host value of MSDUQs per each LinkView peer's TID */ - A_UINT32 opaque_debug_num_of_linkview_msduqs_per_tid; - /** bcn_filter_context variables */ - A_UINT32 opaque_debug_bcns_dropped; - A_UINT32 opaque_debug_bcns_recvd; - A_UINT32 opaque_debug_bcns_delivered; - /** - * Lower 32 bits bitmap of pause ids for TIDs that are paused/unpaused - * based on module_id. - */ - A_UINT32 opaque_debug_vdev_all_tid_pause_bitmap; - /** - * Lower 32 bits bitmap of pause ids for TIDs that are blocked/unblocked - * based on module_id. - */ - A_UINT32 opaque_debug_vdev_all_tid_block_bitmap; - /** wal_pdev rx filter, WAL_RX_FILTER_FLAGS defines */ - A_UINT32 opaque_debug_rx_filter; - /** This word contains the following bitfields: - * aggr_nonaggr_retry_th: - * wal_pdev fields - agg_retry_th and non_agg_retry_th - * This value holds max retry threshold up to which a Data packet - * will be retried when ack is not received. - * agg_retry_th - Threshold value used when aggregation is enabled - * (WMI_PDEV_STATS_AGG_RETRY_TH_SET,GET) - * non_agg_retry_th - Threshold value used for non-aggregation. - * (WMI_PDEV_STATS_NON_AGG_RETRY_TH_SET) - */ - A_UINT32 opaque_debug_aggr_nonaggr_retry_th; - /** This word contains the following bitfields: - * num_max_rx_ba_sessions: - * Number of rx BA session establised - * (WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_SET,GET) - * Max number of rx BA session from wal_pdev - * (WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_SET,GET) - */ - A_UINT32 opaque_debug_num_max_rx_ba_sessions; - /** It holds WHAL_CHANNEL_SWITCH_FLAGS values */ - A_UINT32 opaque_debug_chan_switch_flags; - /** reset_cause holds PDEV_RESET_CONSEC_FAILURE or PDEV_RESET_TXQ_TIMEOUT */ - A_UINT32 opaque_debug_consecutive_failure_reset_cause; - /** PPDU duration limit, in us */ - A_UINT32 opaque_debug_mu_ppdu_dur_limit_us; - /** pdev reset in progress */ - A_UINT32 opaque_debug_reset_in_progress; - /** wal_dev - vdev_migrate_state refer to WAL_VDEV_MIGRATE_STATE */ - A_UINT32 opaque_debug_vdev_migrate_state; - /** opaque_debug_rts_rc_flag: - * wal_pdev rts ratecode - this value reflects whatever - * WMI_PDEV_PARAM_RTS_FIXED_RATE value the host has specified for the pdev. - */ - A_UINT32 opaque_debug_rts_rc_flag; - /* Num of peer delete in progress */ - A_UINT32 opaque_debug_num_of_peer_delete_in_progress; - /** wal_pdev total number of active vdev count */ - A_UINT32 opaque_debug_total_active_vdev_cnt; - /** wal_pdev - max number of vdevs per pdev */ - A_UINT32 opaque_debug_max_vdevs; - /* NonOccupancyList(NOL) context */ - A_UINT32 opaque_debug_dfs_nol_count; - /** NOL timeout in seconds */ - A_UINT32 opaque_debug_dfs_nol_timeout; - A_UINT32 opaque_debug_dfs_use_nol; - /** channel availability check mode, refer enum WMI_ADFS_OCAC_MODE */ - A_UINT32 opaque_debug_cac_mode; - A_UINT32 opaque_debug_dyn_ppdu_dur; /* in ms */ - /** This word contains the following bitfields: - * wal_pdev home channel info - * home_chan_mhz_flags: - * primary channel frequency in mhz - * (WMI_PDEV_STATS_HOME_CHAN_MHZ_SET,GET) - * flags to specify other channel attributes - * (WMI_PDEV_STATS_HOME_CHAN_FLAGS_SET, GET) - */ - A_UINT32 opaque_debug_home_chan_mhz_flags; - /** home channel center frequency in MHz */ - A_UINT32 opaque_debug_home_band_center_freq; - /** home channel phy_mode, refer enum WLAN_PHY_MODE */ - A_UINT32 opaque_debug_home_phy_mode; - /** This word contains the following bitfields: - * wal_pdev current channel info - * cur_chan_mhz_flags: - * primary channel frequency in mhz - * (WMI_PDEV_STATS_CUR_CHAN_MHZ_SET,GET) - * flags to specify other channel attributes - * (WMI_PDEV_STATS_CUR_CHAN_FLAGS_SET,GET) - */ - A_UINT32 opaque_debug_cur_chan_mhz_flags; - /** current channel center frequency in MHz */ - A_UINT32 opaque_debug_cur_band_center_freq; - /** current channel phy_mode, refer enum WLAN_PHY_MODE */ - A_UINT32 opaque_debug_cur_phy_mode; - /* Beacon context info */ - A_UINT32 opaque_debug_bcn_q_num_bcns_queued_to_hw; - /** beacon queue AIFS */ - A_UINT32 opaque_debug_aifs; - /** beacon queue cwmin */ - A_UINT32 opaque_debug_cwmin; - /** beacon queue cwmax */ - A_UINT32 opaque_debug_cwmax; - /** FILS discovery period in TU */ - A_UINT32 opaque_debug_fils_period; - /** Beacon interval in TU */ - A_UINT32 opaque_debug_beacon_period; - A_UINT32 opaque_debug_staggered_beacon_intvl; - /** wal_pdev tx context, refer enum WAL_TX_CTXT_FLAGS */ - A_UINT32 opaque_debug_tx_ctxt_flags; - /** opaque_debug_burst_mode_pending_isr - * wal_pdev tx_ctxt fields - burst_mode refer enum WAL_TX_BURST_MODE - * and pending_isr_status count - */ - A_UINT32 opaque_debug_burst_mode_pending_isr; - /** max burst duration from ppdu duration in us */ - A_UINT32 opaque_debug_burst_dur; - /** counter for tx hw stuck */ - A_UINT32 opaque_debug_tx_hw_stuck_cnt; - /** counter for tx consecutive lifetime expiry */ - A_UINT32 opaque_debug_consecutive_lifetime_expiries; - /** wal_pdev rx context, refer enum WAL_RX_CTXT_FLAGS */ - A_UINT32 opaque_debug_rx_ctxt_flags; - /** wal_pdev fields in rx context for rx_suspend or resume count */ - A_UINT32 opaque_debug_rx_suspend_cnt; - A_UINT32 opaque_debug_rx_resume_cnt; - A_UINT32 opaque_debug_rx_pcie_suspend_cnt; - A_UINT32 opaque_debug_rx_pcie_resume_cnt; - /** This word contains the following bitfields: - * wal_pdev fields - * pdev paused - WMI_PDEV_STATS_PAUSED_SET,GET - * pdev suspend - WMI_PDEV_STATS_SUSPENDED_SET,GET - * cac_enabed - MI_PDEV_STATS_CAC_ENABLED_SET,GET - * monitor VAP present - WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_SET,GET - * beacon tx mode - WMI_PDEV_STATS_BCN_TX_MODE_SET,GET - * isTXsuspended - WMI_PDEV_STATS_IS_TXSUSPENDED_SET,GET - * isSCHEDsuspended - WMI_PDEV_STATS_IS_SCHEDSUSPENDED_SET,GET - * sched_algo_resume_needed - - * WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_SET,GET - * abort_reason - WMI_PDEV_STATS_ABORT_REASON_SET,GET - * atf_cfg - WMI_PDEV_STATS_ATF_CONFIG_SET,GET - * Green AP TX chainmask valid- WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_SET,GET - * Green AP RX chainmask valid- WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_SET,GET - * Green AP Phy mode valid - WMI_PDEV_STATS_GAP_PHY_MODE_VALID_SET,GET - * burst_enable - WMI_PDEV_STATS_BURST_ENABLE_SET,GET - */ - A_UINT32 opaque_debug_wal_pdev_bitfield; - /** This word contains the following bitfields: - * gap_phy_mode_freq: - * When GreenAP is enabled, phy_mode (WMI_PDEV_STATS_GAP_PHY_MODE_SET,GET) - * and center freq(MHz) (WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_SET,GET) - * in GAP context is displayed - */ - A_UINT32 opaque_debug_gap_phy_mode_freq; - /** - * The following 5 opaque_debug_reserved_field variables are provided - * purely for debugging by technicians who have outside knowledge of - * what kind of values the target has placed into these fields. - */ - A_UINT32 opaque_debug_reserved_field_1; - A_UINT32 opaque_debug_reserved_field_2; - A_UINT32 opaque_debug_reserved_field_3; - A_UINT32 opaque_debug_reserved_field_4; - A_UINT32 opaque_debug_reserved_field_5; - /** - * Upper 32 bits bitmap of pause ids for TIDs that are paused/unpaused - * based on module_id. - */ - A_UINT32 opaque_debug_vdev_all_tid_pause_bitmap_ext; - /** - * Upper 32 bits bitmap of pause ids for TIDs that are blocked/unblocked - * based on module_id. - */ - A_UINT32 opaque_debug_vdev_all_tid_block_bitmap_ext; + A_UINT32 opaque_debug_num_macs_phy_vdev_up_active; + /** refer wlan_pdev ic flags */ + A_UINT32 opaque_debug_ic_flags; + /** vdev_id that are paused per pdev */ + A_UINT32 opaque_debug_paused_ap_vdev_bitmap; + /** opaque_debug_flags: + * refer to WLAN_PS_DESC_BIN_HWM_HIT or WLAN_PS_DESC_BIN_LWM_HIT + */ + A_UINT32 opaque_debug_flags; + /** wlan_pdev fields remote_peer_cnt, max_rf_chains_2G and max_rf_chains_5G + * remote_peer_cnt_max_rf_chains_2G_5G: + * This word contains the following bitfields: + * max chains supported in the 2.4 GHz band + * (WMI_PDEV_STATS_MAX_RF_CHAIN_2G_SET,GET) + * max chains supported in the 5 GHz band, + * (WMI_PDEV_STATS_MAX_RF_CHAIN_5G_SET,GET) + * number of remote peers + * (WMI_PDEV_STATS_REMOTE_PEER_CNT_SET,GET) + */ + A_UINT32 opaque_debug_remote_peer_cnt_max_rf_chains_2G_5G; + /** wlan_pdev max HT Capability info, WMI_HT_CAP defines */ + A_UINT32 opaque_debug_max_ht_cap_info; + /** wlan_pdev max VHT capability info, WMI_VHT_CAP defines */ + A_UINT32 opaque_debug_max_vht_cap_info; + /** opaque_debug_max_vht_supp_mcs: + * wlan_pdev max VHT Supported MCS which is + * vht_supp_mcs_2G or vht_supp_mcs_5G + */ + A_UINT32 opaque_debug_max_vht_supp_mcs; + /** wlan_pdev max HE capability info, WMI_HE_CAP defines */ + A_UINT32 opaque_debug_max_he_cap_info; + A_UINT32 opaque_debug_max_he_cap_info_ext; + /** the nominal chain mask for transmit */ + A_UINT32 opaque_debug_tx_chain_mask; + /** the nominal chain mask for receive */ + A_UINT32 opaque_debug_rx_chain_mask; + /** opaque_debug_ema_flags: + * This word contains the following bitfields: + * ema_flags: ema_max_vap_cnt and ema_max_profile_period from wlan_pdev + * ema_max_vap_cnt- number of maximum EMA Tx vaps (VAPs having both + * VDEV_FLAGS_EMA_MODE and VDEV_FLAGS_TRANSMIT_AP set) + * (WMI_PDEV_STATS_EMA_MAX_VAP_CNT_SET,GET) + * ema_max_profile_period - maximum profile periodicity + * (maximum number of beacons after which VAP profiles repeat) + * for any EMA VAP on any pdev. + * (WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_SET,GET) + */ + A_UINT32 opaque_debug_ema_flags; + /** wlan_pdev - maximum ML peers supported */ + A_UINT32 opaque_debug_num_ml_peer_entries; + /** This word contains the following bitfields: + * wlan_pdev fields - num_max_hw_links, current_chip_id and max_num_chips + * (related to MLO) + * Max number of HW links + * (WMI_PDEV_STATS_NUM_MAX_HW_LINKS_SET,GET) + * Current Chip Id + * (WMI_PDEV_STATS_CURRENT_CHIP_ID_SET,GET) + * Max number of chips + * (WMI_PDEV_STATS_MAX_NUM_CHIPS_SET,GET) + */ + A_UINT32 opaque_debug_mlo_flags; + /** Indicate beacon size in bytes */ + A_UINT32 opaque_debug_large_bcn_size; + /** proposed by the host value of MSDUQs per each LinkView peer's TID */ + A_UINT32 opaque_debug_num_of_linkview_msduqs_per_tid; + /** bcn_filter_context variables */ + A_UINT32 opaque_debug_bcns_dropped; + A_UINT32 opaque_debug_bcns_recvd; + A_UINT32 opaque_debug_bcns_delivered; + /** Tids that are paused/unpaused based on module_id */ + A_UINT32 opaque_debug_vdev_all_tid_pause_bitmap; + /** Tids that are blocked/unblocked based on module_id */ + A_UINT32 opaque_debug_vdev_all_tid_block_bitmap; + /** wal_pdev rx filter, WAL_RX_FILTER_FLAGS defines */ + A_UINT32 opaque_debug_rx_filter; + /** This word contains the following bitfields: + * aggr_nonaggr_retry_th: + * wal_pdev fields - agg_retry_th and non_agg_retry_th + * This value holds max retry threshold up to which a Data packet + * will be retried when ack is not received. + * agg_retry_th - Threshold value used when aggregation is enabled + * (WMI_PDEV_STATS_AGG_RETRY_TH_SET,GET) + * non_agg_retry_th - Threshold value used for non-aggregation. + * (WMI_PDEV_STATS_NON_AGG_RETRY_TH_SET) + */ + A_UINT32 opaque_debug_aggr_nonaggr_retry_th; + /** This word contains the following bitfields: + * num_max_rx_ba_sessions: + * Number of rx BA session establised + * (WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_SET,GET) + * Max number of rx BA session from wal_pdev + * (WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_SET,GET) + */ + A_UINT32 opaque_debug_num_max_rx_ba_sessions; + /** It holds WHAL_CHANNEL_SWITCH_FLAGS values */ + A_UINT32 opaque_debug_chan_switch_flags; + /** reset_cause holds PDEV_RESET_CONSEC_FAILURE or PDEV_RESET_TXQ_TIMEOUT */ + A_UINT32 opaque_debug_consecutive_failure_reset_cause; + /** PPDU duration limit, in us */ + A_UINT32 opaque_debug_mu_ppdu_dur_limit_us; + /** pdev reset in progress */ + A_UINT32 opaque_debug_reset_in_progress; + /** wal_dev - vdev_migrate_state refer to WAL_VDEV_MIGRATE_STATE */ + A_UINT32 opaque_debug_vdev_migrate_state; + /** opaque_debug_rts_rc_flag: + * wal_pdev rts ratecode - this value reflects whatever + * WMI_PDEV_PARAM_RTS_FIXED_RATE value the host has specified for the pdev. + */ + A_UINT32 opaque_debug_rts_rc_flag; + /* Num of peer delete in progress */ + A_UINT32 opaque_debug_num_of_peer_delete_in_progress; + /** wal_pdev total number of active vdev count */ + A_UINT32 opaque_debug_total_active_vdev_cnt; + /** wal_pdev - max number of vdevs per pdev */ + A_UINT32 opaque_debug_max_vdevs; + /* NonOccupancyList(NOL) context */ + A_UINT32 opaque_debug_dfs_nol_count; + /** NOL timeout in seconds */ + A_UINT32 opaque_debug_dfs_nol_timeout; + A_UINT32 opaque_debug_dfs_use_nol; + /** channel availability check mode, refer enum WMI_ADFS_OCAC_MODE */ + A_UINT32 opaque_debug_cac_mode; + A_UINT32 opaque_debug_dyn_ppdu_dur; /* in ms */ + /** This word contains the following bitfields: + * wal_pdev home channel info + * home_chan_mhz_flags: + * primary channel frequency in mhz + * (WMI_PDEV_STATS_HOME_CHAN_MHZ_SET,GET) + * flags to specify other channel attributes + * (WMI_PDEV_STATS_HOME_CHAN_FLAGS_SET, GET) + */ + A_UINT32 opaque_debug_home_chan_mhz_flags; + /** home channel center frequency in MHz */ + A_UINT32 opaque_debug_home_band_center_freq; + /** home channel phy_mode, refer enum WLAN_PHY_MODE */ + A_UINT32 opaque_debug_home_phy_mode; + /** This word contains the following bitfields: + * wal_pdev current channel info + * cur_chan_mhz_flags: + * primary channel frequency in mhz + * (WMI_PDEV_STATS_CUR_CHAN_MHZ_SET,GET) + * flags to specify other channel attributes + * (WMI_PDEV_STATS_CUR_CHAN_FLAGS_SET,GET) + */ + A_UINT32 opaque_debug_cur_chan_mhz_flags; + /** current channel center frequency in MHz */ + A_UINT32 opaque_debug_cur_band_center_freq; + /** current channel phy_mode, refer enum WLAN_PHY_MODE */ + A_UINT32 opaque_debug_cur_phy_mode; + /* Beacon context info */ + A_UINT32 opaque_debug_bcn_q_num_bcns_queued_to_hw; + /** beacon queue AIFS */ + A_UINT32 opaque_debug_aifs; + /** beacon queue cwmin */ + A_UINT32 opaque_debug_cwmin; + /** beacon queue cwmax */ + A_UINT32 opaque_debug_cwmax; + /** FILS discovery period in TU */ + A_UINT32 opaque_debug_fils_period; + /** Beacon interval in TU */ + A_UINT32 opaque_debug_beacon_period; + A_UINT32 opaque_debug_staggered_beacon_intvl; + /** wal_pdev tx context, refer enum WAL_TX_CTXT_FLAGS */ + A_UINT32 opaque_debug_tx_ctxt_flags; + /** opaque_debug_burst_mode_pending_isr + * wal_pdev tx_ctxt fields - burst_mode refer enum WAL_TX_BURST_MODE + * and pending_isr_status count + */ + A_UINT32 opaque_debug_burst_mode_pending_isr; + /** max burst duration from ppdu duration in us */ + A_UINT32 opaque_debug_burst_dur; + /** counter for tx hw stuck */ + A_UINT32 opaque_debug_tx_hw_stuck_cnt; + /** counter for tx consecutive lifetime expiry */ + A_UINT32 opaque_debug_consecutive_lifetime_expiries; + /** wal_pdev rx context, refer enum WAL_RX_CTXT_FLAGS */ + A_UINT32 opaque_debug_rx_ctxt_flags; + /** wal_pdev fields in rx context for rx_suspend or resume count */ + A_UINT32 opaque_debug_rx_suspend_cnt; + A_UINT32 opaque_debug_rx_resume_cnt; + A_UINT32 opaque_debug_rx_pcie_suspend_cnt; + A_UINT32 opaque_debug_rx_pcie_resume_cnt; + /** This word contains the following bitfields: + * wal_pdev fields + * pdev paused - WMI_PDEV_STATS_PAUSED_SET,GET + * pdev suspend - WMI_PDEV_STATS_SUSPENDED_SET,GET + * cac_enabed - MI_PDEV_STATS_CAC_ENABLED_SET,GET + * monitor VAP present - WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_SET,GET + * beacon tx mode - WMI_PDEV_STATS_BCN_TX_MODE_SET,GET + * isTXsuspended - WMI_PDEV_STATS_IS_TXSUSPENDED_SET,GET + * isSCHEDsuspended - WMI_PDEV_STATS_IS_SCHEDSUSPENDED_SET,GET + * sched_algo_resume_needed - + * WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_SET,GET + * abort_reason - WMI_PDEV_STATS_ABORT_REASON_SET,GET + * atf_cfg - WMI_PDEV_STATS_ATF_CONFIG_SET,GET + * Green AP TX chainmask valid - WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_SET,GET + * Green AP RX chainmask valid - WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_SET,GET + * Green AP Phy mode valid - WMI_PDEV_STATS_GAP_PHY_MODE_VALID_SET,GET + * burst_enable - WMI_PDEV_STATS_BURST_ENABLE_SET,GET + */ + A_UINT32 opaque_debug_wal_pdev_bitfield; + /** This word contains the following bitfields: + * gap_phy_mode_freq: + * When GreenAP is enabled, phy_mode (WMI_PDEV_STATS_GAP_PHY_MODE_SET,GET) + * and center freq(MHz) (WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_SET,GET) + * in GAP context is displayed + */ + A_UINT32 opaque_debug_gap_phy_mode_freq; + /** + * The following 5 opaque_debug_reserved_field variables are provided + * purely for debugging by technicians who have outside knowledge of + * what kind of values the target has placed into these fields. + */ + A_UINT32 opaque_debug_reserved_field_1; + A_UINT32 opaque_debug_reserved_field_2; + A_UINT32 opaque_debug_reserved_field_3; + A_UINT32 opaque_debug_reserved_field_4; + A_UINT32 opaque_debug_reserved_field_5; } wmi_ctrl_path_pdev_stats_struct; #define WMI_PDEV_STATS_NUM_MACS_GET(flag) \ @@ -14544,7 +13444,6 @@ typedef enum { WMI_CTRL_PATH_STATS_CAL_TYPE_PADROOP = 0x17, WMI_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC = 0x18, WMI_CTRL_PATH_STATS_CAL_TYPE_RXSPUR = 0x19, - WMI_CTRL_PATH_STATS_CAL_TYPE_PDADC = 0x1a, /* add new cal types above this line */ WMI_CTRL_PATH_STATS_CAL_TYPE_INVALID = 0xFF @@ -14644,7 +13543,6 @@ static INLINE A_UINT8 *wmi_ctrl_path_cal_type_id_to_name(A_UINT32 cal_type_id) WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_CAL_TYPE_PADROOP); WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC); WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_CAL_TYPE_RXSPUR); - WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_CAL_TYPE_PDADC); } return (A_UINT8 *) "WMI_CTRL_PATH_STATS_CAL_TYPE_UNKNOWN"; @@ -15026,11 +13924,6 @@ typedef struct { * Proxy mode AFC-Response payload clear count */ A_UINT32 payload_clear_count; - - /* - * payload parsing failure count due to platform memory alloc failure - */ - A_UINT32 payload_parser_mem_alloc_failure_count; } wmi_ctrl_path_afc_stats_struct; /* AT - Airtime */ @@ -15471,28 +14364,28 @@ typedef struct { */ A_UINT32 opaque_debug_keyid0_ast_index; /* opaque_debug_all_tids_block_module_bitmap: - * Lower 32 bits bitmap of block IDs requesting block of all TIDs, + * Bitmap of block IDs requesting block of all TIDs, * part of wal_peer. * Refer to enum WLAN_PAUSE_ID. * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. */ A_UINT32 opaque_debug_all_tids_block_module_bitmap; /* opaque_debug_all_tids_pause_module_bitmap: - * Lower 32 bits bitmap of pause IDs requesting block of all TIDs, + * Bitmap of pause IDs requesting block of all TIDs, * part of wal_peer. * Refer to enum WLAN_PAUSE_ID. * This pause ID can be mapped to a WLAN_MODULE_ID module ID. */ A_UINT32 opaque_debug_all_tids_pause_module_bitmap; /* opaque_debug_data_tids_block_module_bitmap: - * Lower 32 bits bitmap of block ids requesting block of data tids, + * Bitmap of block ids requesting block of data tids, * part of wal_peer. * Refer to enum WLAN_PAUSE_ID. * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. */ A_UINT32 opaque_debug_data_tids_block_module_bitmap; /* opaque_debug_data_tids_pause_module_bitmap: - * Lower 32 bits bitmap of pause ids requesting block of data tids, + * Bitmap of pause ids requesting block of data tids, * part of wal_peer. * Refer to enum WLAN_PAUSE_ID. * This pause ID can be mapped to a WLAN_MODULE_ID module ID. @@ -15885,49 +14778,6 @@ typedef struct { A_UINT32 opaque_debug_field_2; A_UINT32 opaque_debug_field_3; A_UINT32 opaque_debug_field_4; - - /* ba_stats - * This word contains the following bitfields: - * bits 15:0 - ba_tx_neg_fail: Blockack Transmit Negotiation failure - * count for the all TIDs in peer. - * Use WMI_PEER_STATS_BA_TX_NEG_FAIL_SET,GET macros. - * bits 31:16 - reserved - */ - union { - A_UINT32 ba_stats__word; - struct { - A_UINT32 ba_tx_neg_fail: 16, - reserved: 16; - }; - }; - /* opaque_debug_all_tids_block_module_bitmap_ext: - * Upper 32 bits bitmap of block IDs requesting block of all TIDs, - * part of wal_peer. - * Refer to enum WLAN_PAUSE_ID. - * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. - */ - A_UINT32 opaque_debug_all_tids_block_module_bitmap_ext; - /* opaque_debug_all_tids_pause_module_bitmap_ext: - * Upper 32 bits bitmap of pause IDs requesting pause of all TIDs, - * part of wal_peer. - * Refer to enum WLAN_PAUSE_ID. - * This pause ID can be mapped to a WLAN_MODULE_ID module ID. - */ - A_UINT32 opaque_debug_all_tids_pause_module_bitmap_ext; - /* opaque_debug_data_tids_block_module_bitmap_ext: - * Upper 32 bits bitmap of block ids requesting block of data tids, - * part of wal_peer. - * Refer to enum WLAN_PAUSE_ID. - * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. - */ - A_UINT32 opaque_debug_data_tids_block_module_bitmap_ext; - /* opaque_debug_data_tids_pause_module_bitmap_ext: - * Upper 32 bits bitmap of pause ids requesting pause of data tids, - * part of wal_peer. - * Refer to enum WLAN_PAUSE_ID. - * This pause ID can be mapped to a WLAN_MODULE_ID module ID. - */ - A_UINT32 opaque_debug_data_tids_pause_module_bitmap_ext; } wmi_ctrl_path_peer_stats_struct; #define WMI_PEER_STATS_SM_MASK_SET(flag, val) \ @@ -16252,12 +15102,6 @@ typedef struct { #define WMI_PEER_STATS_RC_CHAN_FREQ_GET(flag) \ WMI_GET_BITS(flag, 16, 16) -#define WMI_PEER_STATS_PEER_BA_TX_NEG_FAIL_SET(flag, val) \ - WMI_SET_BITS(flag, 0, 16, val) -#define WMI_PEER_STATS_PEER_BA_TX_NEG_FAIL_GET(flag) \ - WMI_GET_BITS(flag, 0, 16) -/* bits 31:16 unused/reserved */ - typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_cfr_stats_struct */ @@ -16368,109 +15212,6 @@ typedef struct { */ } wmi_radio_chan_stats_event_fixed_param; -typedef enum { - WMI_TDLS_CHANNEL_SWITCH_FRAME_TX_RX = 0x0, - WMI_TDLS_BT_COEX_INDICATION = 0x1, -} wmi_tdls_connect_info_stats_reason_code; - -typedef enum { - WMI_TDLS_FRAME_SUBTYPE_REQUEST = 0x0, - WMI_TDLS_FRAME_SUBTYPE_RESPONSE = 0x1, -} wmi_tdls_connect_info_stats_subtype; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_tdls_connect_info_stats */ - A_UINT32 tlv_header; - /* type: - * Type of frame sent to the Peer, will be having value 4, - * i.e TDLS State change - */ - A_UINT32 type; - /* subtype: - * SubType of frame sent to the Peer, eg. req/resp, - * Takes values from enum wmi_tdls_connect_info_stats_subtype. - */ - A_UINT32 subtype; - /* status: - * Completion status of this frame, required only for Tx frames - * to know if frame is sent out successfully - * 0 - status is success - * 1 - status is failure - */ - A_UINT32 status; - /* reason_code: - * Reason code for the reason of sending this TLV, eg. for TDLS - * channel switch req/resp or for BT running indication - * Takes values from enum wmi_tdls_connect_info_stats_reason_code. - */ - A_UINT32 reason_code; - /* tx_rx: - * Indicates whether we are sender or receiver of this frame, - * 1 value means Tx, 0 value means Rx. - */ - A_UINT32 tx_rx; - /* Current operating channel frequency */ - A_UINT32 op_freq_mhz; - /* Peer MAC address for which this stats is being logged */ - wmi_mac_addr peer_mac_addr; - /* The timestamp at which the WMI event is reported. */ - A_UINT32 timestamp; - /* Last known RSSI */ - A_INT32 rssi; /* dBm units */ - /* Peer Dialog token */ - A_UINT32 peer_dialog_token; -} wmi_tdls_connect_info_stats; - -/* max MCS counters supported for enhance stats */ -#define WMI_ENHANCE_STATS_MAX_MCS_COUNTERS 16 - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_tdls_data_stats */ - A_UINT32 tlv_header; - /* Current operating channel frequency */ - A_UINT32 op_freq_mhz; - /* Peer MAC address for which this stats is being logged */ - wmi_mac_addr peer_mac_addr; - /* The timestamp at which the WMI event is reported. */ - A_UINT32 timestamp; - /* Last known RSSI */ - A_INT32 rssi; /* dBm units */ - /* Last Tx Data rate */ - A_UINT32 data_rate; - /* tx_ppdus_cumulative: - * Total PPDUs Tx-ed combining all the MCS rates over the last 15 secs - */ - A_UINT32 tx_ppdus_cumulative; - /* tx_mcs_data_ppdu: - * PPDUs Txed over each MCS rate for all the supported MCS - * over the last 15 secs - */ - A_UINT32 tx_mcs_data_ppdu[WMI_ENHANCE_STATS_MAX_MCS_COUNTERS]; - /* Total PPDU Tx failures seen over the last 15 secs */ - A_UINT32 tx_ppdu_failures; - /* Total PPDUs Rx-ed combining all the MCS rates over the last 15 secs */ - A_UINT32 rx_ppdus_cumulative; - /* rx_mcs_data_ppdu: - * PPDUs Rxed over each MCS rate for all the supported MCS - * over the last 15 secs - */ - A_UINT32 rx_mcs_data_ppdu[WMI_ENHANCE_STATS_MAX_MCS_COUNTERS]; - /* Total Rx PPDU failures seen over the last 15 secs */ - A_UINT32 rx_ppdu_failures; -} wmi_tdls_data_stats; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_tdls_stats_event_fixed_param */ - A_UINT32 tlv_header; - /** VDEV identifier */ - A_UINT32 vdev_id; - /* Total TDLS Peers this VDEV is connected to */ - A_UINT32 peer_cnt; -} wmi_tdls_stats_event_fixed_param; - /** * PDEV statistics * @@ -16557,11 +15298,6 @@ typedef struct { * (end of packet) */ A_UINT32 rx_other_11ax_msdu_cnt; - /* pending_mpdu_msdus: - * count of the pending MPDUs + MSDUs for all TIDs within all peers - * for all the vdev under the specified pdev - */ - A_UINT32 pending_mpdu_msdus; } wmi_pdev_extd_stats; /** @@ -16590,30 +15326,6 @@ typedef struct{ A_UINT32 estimated_air_time_per_ac; } wmi_pdev_telemetry_stats; - -#define WMI_MAX_BCN_HISTORY 10 /* max beacon history entry */ - -typedef struct { - /* Beacon real RSSI, non-averaged rssi, dBm units; -128 means invalid */ - A_INT32 bcn_rssi; - /* Beacon tsf, 0 means invalid */ - A_UINT32 bcn_tsf; - /* NOTE: - * Due to backwards-compatibility requirements, no new fields - * can be added to this struct. - */ -} wmi_bcn_his_info; - -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_recv_bcn_stats */ - A_UINT32 tlv_header; - /* Vdev id */ - A_UINT32 vdev_id; - /* Received History of last ten Beacon of the connected Bss */ - wmi_bcn_his_info bcn_history[WMI_MAX_BCN_HISTORY]; -} wmi_recv_bcn_stats; - - /** * VDEV statistics * @todo @@ -16654,16 +15366,6 @@ typedef struct { A_UINT32 tx_bcn_outage_cnt; /* Total number of failed beacons */ } wmi_bcn_stats; -/* - * pdev coex stats - */ -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_coex_stats */ - A_UINT32 pdev_id; - A_UINT32 cur_btc_mode; /* 0 - TDD; 1 - FDD; 2 - Hybrid; 3 - DBAM */ - A_UINT32 cur_btc_policy; /* 0 - FR; */ -} wmi_pdev_coex_stats; - #define WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_BIT 0 #define WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_MASK \ (1 << WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_BIT) @@ -16672,10 +15374,6 @@ typedef struct { #define WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_MASK \ (1 << WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_BIT) -#define WMI_VDEV_STATS_FLAGS_CHANNEL_STATS_PRESENT_BIT 2 -#define WMI_VDEV_STATS_FLAGS_CHANNEL_STATS_PRESENT_MASK \ - (1 << WMI_VDEV_STATS_FLAGS_CHANNEL_STATS_PRESENT_BIT) - /** * vdev extension statistics */ @@ -16698,34 +15396,10 @@ typedef struct { * 1: the "is link active" flag is valid * bit 1: WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE, * 1:link_active; 0:link_inactive - * bit 2: WMI_VDEV_STATS_FLAGS_CHANNEL_STATS_PRESENT, - * 0: new stats fields are not present. - * 1: new rx/tx/on/cca time stats fields present; * Refer to WMI_VDEV_STATS_FLAGS_ defs. */ A_UINT32 flags; A_INT32 vdev_tx_power; /* dBm units */ - /** rx_time: - * How many msecs vdev is in active receive on channel - * (32 bits number accruing over time) - */ - A_UINT32 rx_time; - /** tx_time: - * How many msecs vdev is transmitting on channel - * (32 bits number accruing over time) - */ - A_UINT32 tx_time; - /** on_time: - * How many msecs vdev is awake on channel - * (32 bits number accruing over time) - */ - A_UINT32 on_time; - /** cca_time: - * How many msecs vdev is CCA busy on channel - * (32 bits number accruing over time) - * Includes rx_time but not tx_time. - */ - A_UINT32 cca_time; } wmi_vdev_extd_stats; /** @@ -16820,15 +15494,9 @@ typedef struct { A_UINT32 opaque_debug_rx_pkt_on_channel; /* Contains the value of Target beacon transmission time offset value */ A_UINT32 opaque_debug_tbtt_offset; - /* - * Contains the value of lower 32 bits of tid pause bitmap of the peer - * from wal_vdev - */ + /* Contains the value of tid pause bitmap of the peer from wal_vdev */ A_UINT32 opaque_debug_peer_all_tid_pause_bitmap; - /* - * Contains the value of lower 32 bits of tid block bitmap of the peer - * from wal_vdev - */ + /* Contains the value of tid block bitmap of the peer from wal_vdev */ A_UINT32 opaque_debug_peer_all_tid_block_bitmap; /* Contains the value of tdls peer kickout threshold */ A_UINT32 opaque_debug_tdls_peer_kickout_th; @@ -17182,16 +15850,6 @@ typedef struct { A_UINT32 opaque_debug_field_2; A_UINT32 opaque_debug_field_3; A_UINT32 opaque_debug_field_4; - /* - * Contains the value of upper 32 bits tid pause bitmap of the peer - * from wal_vdev - */ - A_UINT32 opaque_debug_peer_all_tid_pause_bitmap_ext; - /* - * Contains the value of upper 32 bits tid block bitmap of the peer - * from wal_vdev - */ - A_UINT32 opaque_debug_peer_all_tid_block_bitmap_ext; } wmi_ctrl_path_vdev_stats_struct; @@ -17937,40 +16595,6 @@ typedef struct { A_UINT32 dot11RTSFailureCount; } wmi_ctrl_path_sta_rrm_stats_struct; -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_sta_dar_stats_struct */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 stats_granularity; /* Possible values are listed in wmi_ctrl_path_stats_granularity enum. */ - /* transmit_pwr: - * Units are dB w.r.t. a -20 dBm reference. - * For example, if the STA's tx power is 10 dBm, the transmit_pwr field's - * value will be 30. - */ - A_UINT32 transmit_pwr; - A_UINT32 cca_busy_cnt; - A_UINT32 cycle_cnt; - /* - * For the below 8-element arrays, in case of AC-level granularity, - * only the first 4 elements of the array are populated, and are indexed - * by wmi_traffic_ac enum values. - * Otherwise, for TID level granularity all 8 elements of the array will - * be filled by FW, and are indexed by the TID value. - */ - A_UINT32 success_mpdu_tx_cnt[8]; - A_UINT32 dropped_mpdu_tx_cnt[8]; - A_UINT32 rts_success_cnt[8]; - A_UINT32 rts_fail_cnt[8]; - A_UINT32 fcs_fail_cnt[8]; /* number of rx MPDUs whose FCS check failed */ - /* ack_fail_cnt: - * number of tx MPDUs nacked within a block ack, - * or for which no block ack was received. - */ - A_UINT32 ack_fail_cnt[8]; - A_UINT32 ba_nego_fail_cnt; - A_UINT32 beacon_loss_cnt; -} wmi_ctrl_path_sta_dar_stats_struct; - typedef struct { /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_vdev_bcn_stats_struct */ A_UINT32 tlv_header; @@ -18314,61 +16938,6 @@ typedef struct { #define WMI_SCAN_MODE_VDEV_FLAG_ENABLED(flag) ((flag & VDEV_FLAGS_SCAN_MODE_VAP) ? 1 : 0) - -#define WMI_VDEV_START_SMD_FLAGS_GET_ROAM_ENABLED(mlo_flags) WMI_GET_BITS(mlo_flags, 0, 1) -#define WMI_VDEV_START_SMD_FLAGS_SET_ROAM_ENABLED(mlo_flags, value) WMI_SET_BITS(mlo_flags, 0, 1, value) -#define WMI_VDEV_START_SMD_FLAGS_GET_DL_DATA_FORWARDING(mlo_flags) WMI_GET_BITS(mlo_flags, 1, 1) -#define WMI_VDEV_START_SMD_FLAGS_SET_DL_DATA_FORWARDING(mlo_flags, value) WMI_SET_BITS(mlo_flags, 1, 1, value) -#define WMI_VDEV_START_SMD_FLAGS_GET_UL_DATA_FORWARDING(mlo_flags) WMI_GET_BITS(mlo_flags, 2, 1) -#define WMI_VDEV_START_SMD_FLAGS_SET_UL_DATA_FORWARDING(mlo_flags, value) WMI_SET_BITS(mlo_flags, 2, 1, value) -#define WMI_VDEV_START_SMD_FLAGS_GET_PTK_MODE(mlo_flags) WMI_GET_BITS(mlo_flags, 3, 1) -#define WMI_VDEV_START_SMD_FLAGS_SET_PTK_MODE(mlo_flags, value) WMI_SET_BITS(mlo_flags, 3, 1, value) - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len;tag equals WMITLV_TAG_STRUC_wmi_vdev_start_smd_params*/ - /** MLD MAC address */ - wmi_mac_addr smd_macaddr; - union { - struct { - A_UINT32 roam_enabled :1, - dl_data_forwarding :1, - ul_data_forwarding :1, - ptk_mode :1, - reserved :28; - }; - A_UINT32 smd_flags; - }; -} wmi_vdev_start_smd_params; - - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len;tag equals WMITLV_TAG_STRUC_wmi_vdev_start_uhr_config*/ - union { - struct { - A_UINT32 advance_notification_interval : 8, - post_notification_interval : 8, - critical_update_indication_interval : 8, - reserved : 8; - }; - A_UINT32 uhr_cu_intervals; - }; -} wmi_vdev_start_uhr_config; - -#define WMI_VDEV_START_UHR_GET_ADVANCE_NOTIFICATION_INTERVAL(uhr_cu_intervals) \ - WMI_GET_BITS(uhr_cu_intervals, 0, 8) -#define WMI_VDEV_START_UHR_SET_ADVANCE_NOTIFICATION_INTERVAL(uhr_cu_intervals, val) \ - WMI_SET_BITS(uhr_cu_intervals, 0, 8, _val) - -#define WMI_VDEV_START_UHR_GET_POST_NOTIFICATION_INTERVAL(uhr_cu_intervals) \ - WMI_GET_BITS(uhr_cu_intervals, 8, 8) -#define WMI_VDEV_START_UHR_SET_POST_NOTIFICATION_INTERVAL(uhr_cu_intervals, val) \ - WMI_SET_BITS(uhr_cu_intervals, 8, 8, _val) - -#define WMI_VDEV_START_UHR_GET_CRITICAL_UPDATE_INDICATION_INTERVAL(uhr_cu_intervals) \ - WMI_GET_BITS(uhr_cu_intervals, 16, 8) -#define WMI_VDEV_START_UHR_SET_CRITICAL_UPDATE_INDICATION_INTERVAL(uhr_cu_intervals, val) \ - WMI_SET_BITS(uhr_cu_intervals, 16, 8, _val) - typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ @@ -18403,16 +16972,6 @@ typedef struct { * vdev_stats_id_valid field is non-zero. */ A_UINT32 vdev_stats_id; - /** cfp_enable: indicate whether control frame protection is enabled */ - A_UINT32 cfp_enable; - /* - * VDEV ID that will be assigned for both legacy and MLD VAPs. - * This will be configured to rx_meta_data in the AST entry. - * This information will then be used by host to achieve intra-bss - * forwarding for the Rx packets. - */ - A_UINT32 global_vdev_id; - /* This TLV is followed by another TLV of array of structures * wmi_vdev_txrx_streams cfg_txrx_streams[]; * wmi_vdev_create_mlo_params mlo_params[0,1]; @@ -18491,8 +17050,6 @@ typedef struct { #define WMI_MLO_FLAGS_SET_IEEE_LINK_ID_VALID(mlo_flags, value) WMI_SET_BITS(mlo_flags, 18, 1, value) #define WMI_MLO_FLAGS_GET_IEEE_LINK_ID_VALID_PARTNER(mlo_flags) WMI_GET_BITS(mlo_flags, 19, 1) #define WMI_MLO_FLAGS_SET_IEEE_LINK_ID_VALID_PARTNER(mlo_flags, value) WMI_SET_BITS(mlo_flags, 19, 1, value) -#define WMI_MLO_FLAGS_GET_SINGLE_LINK_EMLSR_EN(mlo_flags) WMI_GET_BITS(mlo_flags, 20, 1) -#define WMI_MLO_FLAGS_SET_SINGLE_LINK_EMLSR_EN(mlo_flags, value) WMI_SET_BITS(mlo_flags, 20, 1, value) /* this structure used for passing MLO flags */ typedef struct { @@ -18524,8 +17081,7 @@ typedef struct { start_as_active:1, /* indicate link should be started in active status */ mlo_ieee_link_id_valid:1, /* indicate if the ieee_link_id in wmi_vdev_start_mlo_params is valid */ mlo_ieee_link_id_valid_partner:1, /* indicate if the ieee_link_id in wmi_partner_link_params is valid */ - single_link_emlsr_en:1, /* indicate if emlsr enablement on one link is supported */ - unused: 11; + unused: 12; }; A_UINT32 mlo_flags; }; @@ -18574,123 +17130,6 @@ typedef enum { } WMI_VDEV_CREATE_WFDR2_MODES; -/* - * This TLV structure is used to pass the offsets of each TBTT count down, - * pertaining to advance notification of any BSS parameter change, - * in the host allocated DDR memory, to which FW should copy the - * current count down. - */ -typedef struct { - A_UINT32 tlv_header; /** TLV tag (WMITLV_TAG_STRUC_wmi_vdev_create_tbtt_count_down_offset_info) and len */ - /** - * host_addr_lsb - LSB 32 bits of Host DDR physical address - * host_addr_msb - MSB 32 bits of Host DDR physical address - */ - A_UINT32 host_addr_lsb; - A_UINT32 host_addr_msb; - A_UINT32 size; /** Indicates the total bytes allocated for this VAP */ - /** - * offsets should always start from 1 as 0th offset shall be reserved for - * flags. - * A_UINT32[0] = EHT CU | UHR CU - * So if the below offset infos contain zero, FW shall assume they are - * invalid. - */ - /** offsets of CSA & QUIET count down */ - union { - struct { - A_UINT32 csa : 16, - quiet : 16; - }; - A_UINT32 offset_info_1; - }; - /** offsets of EHT BPCC & ML-RECONFIG count down */ - union { - struct { - A_UINT32 eht_bpcc : 16, - reconfig : 16; - }; - A_UINT32 offset_info_2; - }; - /** - * offsets of TTLM Max Channel Switch Time & - * Expected Duration count down - */ - union { - struct { - A_UINT32 ttlm_max_chan_switch_time : 16, - ttlm_expected_duration : 16; - }; - A_UINT32 offset_info_3; - }; - /** offsets of UHR Param Update count down & EBPCC */ - union { - struct { - A_UINT32 uhr_param_update : 16, - uhr_ebpcc : 16; - }; - A_UINT32 offset_info_4; - }; - /** offsets of Max Channel Switch Timer */ - union { - struct { - A_UINT32 max_chan_switch_time : 16, - reserved_1 : 16; - }; - A_UINT32 offset_info_5; - }; -} wmi_vdev_create_tbtt_count_down_offset_info; - -/* offsets of CSA & Quiet count down */ -#define WMI_TBTT_COUNT_DOWN_OFFSET_CSA_GET(offset_info_1) \ - WMI_GET_BITS(offset_info_1, 0, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_CSA_SET(offset_info_1, value) \ - WMI_SET_BITS(offset_info_1, 0, 16, value) - -#define WMI_TBTT_COUNT_DOWN_OFFSET_QUIET_GET(offset_info_1) \ - WMI_GET_BITS(offset_info_1, 16, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_QUIET_SET(offset_info_1, value) \ - WMI_SET_BITS(offset_info_1, 16, 16, value) - -/* offsets of EHT BPCC & ML-RECONFIG count down */ -#define WMI_TBTT_COUNT_DOWN_OFFSET_EHT_BPCC_GET(offset_info_2) \ - WMI_GET_BITS(offset_info_2, 0, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_EHT_BPCC_SET(offset_info_2, value) \ - WMI_SET_BITS(offset_info_2, 0, 16, value) - -#define WMI_TBTT_COUNT_DOWN_OFFSET_RECONFIG_GET(offset_info_2) \ - WMI_GET_BITS(offset_info_2, 16, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_RECONFIG_SET(offset_info_2, value) \ - WMI_SET_BITS(offset_info_2, 16, 16, value) - -/* offsets of TTLM Max Channel Switch Time & Expected Duration count down */ -#define WMI_TBTT_COUNT_DOWN_OFFSET_TTLM_MAX_CHAN_SWITCH_TIME_GET(offset_info_3) \ - WMI_GET_BITS(offset_info_3, 0, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_TTLM_MAX_CHAN_SWITCH_TIME_SET(offset_info_3, value) \ - WMI_SET_BITS(offset_info_3, 0, 16, value) -#define WMI_TBTT_COUNT_DOWN_OFFSET_TTLM_EXPECTED_DURATION_GET(offset_info_3) \ - WMI_GET_BITS(offset_info_3, 16, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_TTLM_EXPECTED_DURATION_SET(offset_info_3, value) \ - WMI_SET_BITS(offset_info_3, 16, 16, value) - -/* offsets of UHR Param Update count down & EBPCC */ -#define WMI_TBTT_COUNT_DOWN_OFFSET_UHR_PARAM_UPDATE_GET(offset_info_4) \ - WMI_GET_BITS(offset_info_4, 0, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_UHR_PARAM_UPDATE_SET(offset_info_4, value) \ - WMI_SET_BITS(offset_info_4, 0, 16, value) - -#define WMI_TBTT_COUNT_DOWN_OFFSET_UHR_EBPCC_GET(offset_info_4) \ - WMI_GET_BITS(offset_info_4, 16, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_UHR_EBPCC_SET(offset_info_4, value) \ - WMI_SET_BITS(offset_info_4, 16, 16, value) - -/* offsets of Max Channel Switch Time */ -#define WMI_TBTT_COUNT_DOWN_OFFSET_MAX_CHAN_SWITCH_TIME_GET(offset_info_5) \ - WMI_GET_BITS(offset_info_5, 0, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_MAX_CHAN_SWITCH_TIME_SET(offset_info_5, value) \ - WMI_SET_BITS(offset_info_5, 0, 16, value) - - /* this TLV structure used for pass mlo parameters on vdev start*/ typedef struct { A_UINT32 tlv_header; /** TLV tag and len; */ @@ -18701,7 +17140,6 @@ typedef struct { * mlo_ieee_link_id_valid bit set. */ A_UINT32 ieee_link_id; - A_UINT32 mlo_vdev_id; /* deprecated */ } wmi_vdev_start_mlo_params; /* this TLV structure used for passing mlo parameters on vdev stop */ @@ -18744,10 +17182,10 @@ typedef enum { } wmi_vdev_update_mac_addr_conf_status; /** values for vdev_type */ -#define WMI_VDEV_TYPE_AP 0x1 -#define WMI_VDEV_TYPE_STA 0x2 -#define WMI_VDEV_TYPE_IBSS 0x3 -#define WMI_VDEV_TYPE_MONITOR 0x4 +#define WMI_VDEV_TYPE_AP 0x1 +#define WMI_VDEV_TYPE_STA 0x2 +#define WMI_VDEV_TYPE_IBSS 0x3 +#define WMI_VDEV_TYPE_MONITOR 0x4 /** VDEV type is for social wifi interface.This VDEV is Currently mainly needed * by FW to execute the NAN specific WMI commands and also implement NAN specific @@ -18756,16 +17194,14 @@ typedef enum { * WMI command to create this VDEV once during initialization and host is not * expected to use any VDEV specific WMI commands on this VDEV. **/ -#define WMI_VDEV_TYPE_NAN 0x5 +#define WMI_VDEV_TYPE_NAN 0x5 -#define WMI_VDEV_TYPE_OCB 0x6 +#define WMI_VDEV_TYPE_OCB 0x6 /* NAN Data Interface */ -#define WMI_VDEV_TYPE_NDI 0x7 +#define WMI_VDEV_TYPE_NDI 0x7 -#define WMI_VDEV_TYPE_MESH_POINT 0x8 - -#define WMI_VDEV_TYPE_WIFI_PASSTHRU 0x9 +#define WMI_VDEV_TYPE_MESH_POINT 0x8 /* * Param values to be sent for WMI_VDEV_PARAM_SGI command @@ -19475,10 +17911,6 @@ typedef enum { #define WMI_HECAP_MAC_HTVHTTRIGRX_GET_D2(he_cap2) (0) #define WMI_HECAP_MAC_HTVHTTRIGRX_SET_D2(he_cap2, value) {;} -#define WMI_GET_HW_RATECODE_VERSION(_rcode) (((_rcode) >> 28) & 0x1) -#define WMI_SET_HW_RATECODE_VERSION_V1(_rcode) (((1) << 28) | (_rcode)) -#define WMI_GET_HW_RATECODE_GI_V1(_rcode) (((_rcode) >> 14) & 0x3) -#define WMI_GET_HW_RATECODE_BW_V1(_rcode) (((_rcode) >> 11) & 0x7) #define WMI_GET_HW_RATECODE_PREAM_V1(_rcode) (((_rcode) >> 8) & 0x7) #define WMI_GET_HW_RATECODE_NSS_V1(_rcode) (((_rcode) >> 5) & 0x7) #define WMI_GET_HW_RATECODE_RATE_V1(_rcode) (((_rcode) >> 0) & 0x1F) @@ -19544,9 +17976,6 @@ typedef struct { /* Target TSF value by which VDEV restart procedure should be completed in FW */ A_UINT32 target_tsf_us_lo; /* bits 31:0 */ A_UINT32 target_tsf_us_hi; /* bits 63:32 */ - A_UINT32 vdev_op_ul_nss; /* vdev operating uplink nss. 1 ~ n: 1ss ~ nss */ - A_UINT32 vdev_op_dl_nss; /* vdev operating downlink nss. 1 ~ n: 1ss ~ nss */ - A_UINT32 uhr_ops; /* refer to WMI_UHR_OPS_XXX macros */ /* The TLVs follows this structure: * wmi_channel chan; <-- WMI channel @@ -19561,12 +17990,6 @@ typedef struct { * optional TLV for dbw_chan * wmi_dbw_chan_info dbw_chan_info * optional TLV used for dbw_chan_info - * wmi_vdev_start_smd_params smd_params; - * optional TLV used for SMD - * wmi_vdev_start_uhr_config uhr_config_info - * optional TLV used if VAP is 11BN - * wmi_uhr_ap_npca_params npca_params - * optional TLV used to update NPCA information */ } wmi_vdev_start_request_cmd_fixed_param; @@ -19610,18 +18033,8 @@ enum WMI_VDEV_UP_FLAGS { * Valid only for VBSS subtype vaps. */ WMI_VDEV_UP_FLAG_VBSS_PASSIVE = 0x00000004, - /** REDUCE_OFF_DIAGONAL_NULL_THR - * The flag will be set to reduce off diagonal nulling threshold. - */ - WMI_VDEV_UP_FLAG_REDUCE_OFF_DIAGONAL_NULL_THR = 0x00000008, }; -typedef struct{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_co_located_chan_info */ - /* co-located link frequency discovered on connected ap */ - A_UINT32 link_freq; /* MHz units */ -} wmi_co_located_chan_info; - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_up_cmdid_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ @@ -19638,10 +18051,6 @@ typedef struct { A_UINT32 profile_num; /** flags - this is a bitwise-or combination of WMI_VDEV_UP_FLAGS values */ A_UINT32 flags; - /* The below TLVs follow this struct: - * - wmi_co_located_chan_info co_located_chan_info[]; - * Connected AP's co-located channel info - */ } wmi_vdev_up_cmd_fixed_param; typedef struct { @@ -19766,7 +18175,6 @@ typedef enum { WMI_RATE_PREAMBLE_VHT, WMI_RATE_PREAMBLE_HE, WMI_RATE_PREAMBLE_EHT, - WMI_RATE_PREAMBLE_UHR, } WMI_RATE_PREAMBLE; /** Value to disable fixed rate setting */ @@ -19785,8 +18193,6 @@ typedef enum { #define WMI_VDEV_OCE_FILS_DISCOVERY_FRAME_FEATURE_BITMAP 0x10 #define WMI_VDEV_OCE_ESP_FEATURE_BITMAP 0x20 #define WMI_VDEV_OCE_REASSOC_REJECT_FEATURE_BITMAP 0x40 -/* Enable FILS Discovery frame transmission only for 6 GHz SAP */ -#define WMI_VDEV_OCE_FILS_DISCOVERY_FRAME_6G_ONLY_FEATURE_BITMAP 0x80 /** 6 GHZ params **/ /* Control to enable/disable beacon tx in non-HT duplicate */ @@ -20902,83 +19308,6 @@ typedef enum { */ WMI_VDEV_PARAM_CONNECT_EXT_FEATURES, /* 0xC7 */ - /* Allow to tear down TWT on scan start, if corresponding INI is set */ - WMI_VDEV_PARAM_DISABLE_SCAN_START_TWT, /* 0xC8 */ - - /* - * value 0 | default value no opp | controlled from pdev level - * value 1 | disable responder for this vdev - */ - WMI_VDEV_PARAM_TWT_RESP_DISABLE, /* 0xC9 */ - - /* - * Enable or disable 2xLDPC in Fixed rate UHR data packet transmissions. - * valid values: 0 - Disable 2xLDPC, 1 - Enable 2xLDPC. - */ - WMI_VDEV_PARAM_2xLDPC, /* 0xCA */ - - /** - * Self-capability support indication for CCK RX/TX in 5GHz band. - * Use with WMI_VDEV_SET_PARAM_CMDID, value: - * BIT 0 - cck_rx_support_5ghz - * BIT 1 - cck_tx_support_5ghz - * - * Host must only set this param when enabled by ini and - * WMI_SERVICE_CCK_RX_SUPPORT_5GHZ/WMI_SERVICE_CCK_TX_SUPPORT_5GHZ - * (FW capability bits) are present. - */ - WMI_VDEV_PARAM_CCK_SUPPORT, /* 0xCB */ - - /* - * BIT 0: - * value 0 | disable D-SMPS - * value 1 | enable D-SMPS - * BIT 1: - * value 0 | disable dynamic D-SMPS base on RSSI feature - * value 1 | enable dynamic D-SMPS base on RSSI feature - */ - WMI_VDEV_PARAM_DSMPS_CONTROL, /* 0xCC */ - - /* - * Support P2P GO cancel long duration one-shot NOA - * 0 - Disable P2P GO cancel NOA feature - default value - * 1 - Enable P2P GO cancel NOA feature - */ - WMI_VDEV_PARAM_SET_GO_CANCEL_NOA, /* 0xCD */ - - /* - * WMI command to set ACK rate - * param_value refer to rate code (legacy CCK/OFDM rates) definitions - * for ACK Rates - * valid values: - * ACK_RATE_CODE_6MBPS_OFDM (0x003): Set 6Mbps OFDM ACK rate - * ACK_RATE_CODE_12MBPS_OFDM (0x002): Set 12Mbps OFDM ACK rate - * ACK_RATE_CODE_24MBPS_OFDM (0x001): Set 24Mbps OFDM ACK rate - * ... - * ACK_RATE_RESTORE_ORIGINAL (0xFFFF): Restore original rates - */ - WMI_VDEV_PARAM_ACK_RATE, /* 0xCE */ - - /* Enable TWT in Concurrency for this vdev */ - WMI_VDEV_PARAM_ENABLE_TWT_CONCURRENCY, /* 0xCF */ - - /* Use BTWT ID0 for this vdev */ - WMI_VDEV_PARAM_USE_BTWT_ID0, /* 0xD0 */ - - /* - * Enable or disable UHR ELR capability in Auto rate and - * Fixed rate UHR data packet transmissions. - * Enable or disable Enhanced Long range - * valid values: 0 - Disable ELR, 1 - Enable ELR. - */ - WMI_VDEV_PARAM_UHR_ELR, /* 0xD1 */ - - /* - * Enable or disable Non-data UHR Enhanced Long Range - * valid values: 0 - Disable ELR, 1 - Enable ELR. - */ - WMI_VDEV_PARAM_NON_DATA_UHR_ELR, /* 0xD2 */ - /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE === * The below vdev param types are used for prototyping, and are @@ -21145,16 +19474,6 @@ typedef enum { */ WMI_VDEV_PARAM_SET_SAP_PS_WITH_TWT, /* 0x8013 */ - /* - * Support RTT Bandwidth downgrade - * 0 - Disable RTT Bandwidth downgrade - * 1 - Enable RTT Bandwidth downgrade - */ - WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_BW_DOWNGRADE,/* 0x8014 */ - - /* customized txop for vendor configuration in unit of us */ - WMI_VDEV_PARAM_SU_TXOP_BURST_LIMIT_US, /* 0x8015 */ - /*=== END VDEV_PARAM_PROTOTYPE SECTION ===*/ } WMI_VDEV_PARAM; @@ -21314,46 +19633,46 @@ typedef enum { /* commands for 11ax TXBF capabilities */ -#define WMI_TXBF_CONF_11AX_SU_TX_BFER_GET(x) WMI_GET_BITS(x,0,1) +#define WMI_TXBF_CONF_11AX_SU_TX_BFER_GET(x) WMI_GET_BITS((x,0,1) #define WMI_TXBF_CONF_11AX_SU_TX_BFER_SET(x,z) WMI_SET_BITS(x,0,1,z) -#define WMI_TXBF_CONF_11AX_SU_TX_BFEE_GET(x) WMI_GET_BITS(x,1,1) +#define WMI_TXBF_CONF_11AX_SU_TX_BFEE_GET(x) WMI_GET_BITS((x,1,1) #define WMI_TXBF_CONF_11AX_SU_TX_BFEE_SET(x,z) WMI_SET_BITS(x,1,1,z) -#define WMI_TXBF_CONF_11AX_MU_TX_BFER_GET(x) WMI_GET_BITS(x,2,1) +#define WMI_TXBF_CONF_11AX_MU_TX_BFER_GET(x) WMI_GET_BITS((x,2,1) #define WMI_TXBF_CONF_11AX_MU_TX_BFER_SET(x,z) WMI_SET_BITS(x,2,1,z) -#define WMI_TXBF_CONF_11AX_BFEE_NDP_STS_LT_EQ_80_GET(x) WMI_GET_BITS(x,3,3) +#define WMI_TXBF_CONF_11AX_BFEE_NDP_STS_LT_EQ_80_GET(x) WMI_GET_BITS((x,3,3) #define WMI_TXBF_CONF_11AX_BFEE_NDP_STS_LT_EQ_80_SET(x,z) WMI_SET_BITS(x,3,3,z) -#define WMI_TXBF_CONF_11AX_NSTS_LT_EQ_80_GET(x) WMI_GET_BITS(x,6,3) +#define WMI_TXBF_CONF_11AX_NSTS_LT_EQ_80_GET(x) WMI_GET_BITS((x,6,3) #define WMI_TXBF_CONF_11AX_NSTS_LT_EQ_80_SET(x,z) WMI_SET_BITS(x,6,3,z) -#define WMI_TXBF_CONF_11AX_TX_BFEE_NDP_STS_GT_80_GET(x) WMI_GET_BITS(x,9,3) +#define WMI_TXBF_CONF_11AX_TX_BFEE_NDP_STS_GT_80_GET(x) WMI_GET_BITS((x,9,3) #define WMI_TXBF_CONF_11AX_TX_BFEE_NDP_STS_GT_80_SET(x,z) WMI_SET_BITS(x,9,3,z) -#define WMI_TXBF_CONF_11AX_NSTS_GT_80_GET(x) WMI_GET_BITS(x,12,3) +#define WMI_TXBF_CONF_11AX_NSTS_GT_80_GET(x) WMI_GET_BITS((x,12,3) #define WMI_TXBF_CONF_11AX_NSTS_GT_80_SET(x,z) WMI_SET_BITS(x,12,3,z) -#define WMI_TXBF_CONF_AX_BFER_SND_DIM_LT_EQ_80_SND_DIM_GET(x) WMI_GET_BITS(x,15,3) +#define WMI_TXBF_CONF_AX_BFER_SND_DIM_LT_EQ_80_SND_DIM_GET(x) WMI_GET_BITS((x,15,3) #define WMI_TXBF_CONF_AX_BFER_SND_DIM_LT_EQ_80_SND_DIM_SET(x,z) WMI_SET_BITS(x,15,3,z) -#define WMI_TXBF_CONF_AX_BFER_SND_DIM_GT_80_SND_DIM_GET(x) WMI_GET_BITS(x,18,3) +#define WMI_TXBF_CONF_AX_BFER_SND_DIM_GT_80_SND_DIM_GET(x) WMI_GET_BITS((x,18,3) #define WMI_TXBF_CONF_AX_BFER_SND_DIM_GT_80_SND_DIM_SET(x,z) WMI_SET_BITS(x,18,3,z) -#define WMI_TXBF_CONF_AX_SU_BFEE_NG16_FDBK_GET(x) WMI_GET_BITS(x,21,1) +#define WMI_TXBF_CONF_AX_SU_BFEE_NG16_FDBK_GET(x) WMI_GET_BITS((x,21,1) #define WMI_TXBF_CONF_AX_SU_BFEE_NG16_FDBK_SET(x,z) WMI_SET_BITS(x,21,1,z) -#define WMI_TXBF_CONF_AX_MU_BFEE_NG16_FDBK_GET(x) WMI_GET_BITS(x,22,1) +#define WMI_TXBF_CONF_AX_MU_BFEE_NG16_FDBK_GET(x) WMI_GET_BITS((x,22,1) #define WMI_TXBF_CONF_AX_MU_BFEE_NG16_FDBK_SET(x,z) WMI_SET_BITS(x,22,1,z) -#define WMI_TXBF_CONF_AX_SU_BFEE_CDBK_4_2_GET(x) WMI_GET_BITS(x,23,1) +#define WMI_TXBF_CONF_AX_SU_BFEE_CDBK_4_2_GET(x) WMI_GET_BITS((x,23,1) #define WMI_TXBF_CONF_AX_SU_BFEE_CDBK_4_2_SET(x,z) WMI_SET_BITS(x,23,1,z) -#define WMI_TXBF_CONF_AX_MU_BFEE_CDBK_7_5_GET(x) WMI_GET_BITS(x,24,1) +#define WMI_TXBF_CONF_AX_MU_BFEE_CDBK_7_5_GET(x) WMI_GET_BITS((x,24,1) #define WMI_TXBF_CONF_AX_MU_BFEE_CDBK_7_5_SET(x,z) WMI_SET_BITS(x,24,1,z) -#define WMI_TXBF_CONF_AX_FDBK_TRIG_GET(x) WMI_GET_BITS(x,25,1) +#define WMI_TXBF_CONF_AX_FDBK_TRIG_GET(x) WMI_GET_BITS((x,25,1) #define WMI_TXBF_CONF_AX_FDBK_TRIG_SET(x,z) WMI_SET_BITS(x,25,1,z) @@ -21443,7 +19762,7 @@ typedef struct { /** requestor id that requested the VDEV start request */ A_UINT32 requestor_id; /* Respose of Event type START/RESTART */ - A_UINT32 resp_type; /* WMI_START_EVENT_PARAM */ + WMI_START_EVENT_PARAM resp_type; /** status of the response */ A_UINT32 status; /** Vdev chain mask */ @@ -21526,7 +19845,6 @@ typedef struct { #define WMI_VDEV_START_RESPONSE_INCORRECT_CHANNEL_PARAMS 0x9 /** home channel params are incorrect */ #define WMI_VDEV_START_RESPONSE_GENERIC_VDEV_START_FAILURE 0xa /** generic reason code for vdev start request reject */ - /** Beacon processing related command and event structures */ typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bcn_tx_hdr */ @@ -22002,105 +20320,91 @@ enum wmi_sta_ps_scheme_cfg { WMI_STA_PS_OPM_CONSERVATIVE = 0, WMI_STA_PS_OPM_AGGRESSIVE = 1, WMI_STA_PS_USER_DEF = 2, - WMI_STA_PS_LATENCY_DEF = 3, }; enum wmi_sta_powersave_param { - /** - * Controls how frames are retrievd from AP while STA is sleeping - * - * (see enum wmi_sta_ps_param_rx_wake_policy) - */ - WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, +/** + * Controls how frames are retrievd from AP while STA is sleeping + * + * (see enum wmi_sta_ps_param_rx_wake_policy) + */ +WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, - /** - * The STA will go active after this many TX - * - * (see enum wmi_sta_ps_param_tx_wake_threshold) - */ - WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, +/** + * The STA will go active after this many TX + * + * (see enum wmi_sta_ps_param_tx_wake_threshold) + */ +WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, - /** - * Number of PS-Poll to send before STA wakes up - * - * (see enum wmi_sta_ps_param_pspoll_count) - * - */ - WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, +/** + * Number of PS-Poll to send before STA wakes up + * + * (see enum wmi_sta_ps_param_pspoll_count) + * + */ +WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, - /** - * TX/RX inactivity time in msec before going to sleep. - * - * The power save SM will monitor tx/rx activity on the VDEV, if no - * activity for the specified msec of the parameter the Power save SM will - * go to sleep. - */ - WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, +/** + * TX/RX inactivity time in msec before going to sleep. + * + * The power save SM will monitor tx/rx activity on the VDEV, if no + * activity for the specified msec of the parameter the Power save SM will + * go to sleep. + */ +WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, - /** - * Set uapsd configuration. - * - * (see enum wmi_sta_ps_param_uapsd) - */ - WMI_STA_PS_PARAM_UAPSD = 4, +/** + * Set uapsd configuration. + * + * (see enum wmi_sta_ps_param_uapsd) + */ +WMI_STA_PS_PARAM_UAPSD = 4, - /** - * Number of PS-Poll to send before STA wakes up in QPower Mode - */ - WMI_STA_PS_PARAM_QPOWER_PSPOLL_COUNT = 5, +/** + * Number of PS-Poll to send before STA wakes up in QPower Mode + */ +WMI_STA_PS_PARAM_QPOWER_PSPOLL_COUNT = 5, - /** - * Enable OPM - */ - WMI_STA_PS_ENABLE_QPOWER = 6, - WMI_STA_PS_ENABLE_OPM = WMI_STA_PS_ENABLE_QPOWER, /* alias */ +/** + * Enable OPM + */ +WMI_STA_PS_ENABLE_QPOWER = 6, + WMI_STA_PS_ENABLE_OPM = WMI_STA_PS_ENABLE_QPOWER, /* alias */ - /** - * Number of TX frames before the entering the Active state - */ - WMI_STA_PS_PARAM_QPOWER_MAX_TX_BEFORE_WAKE = 7, +/** + * Number of TX frames before the entering the Active state + */ +WMI_STA_PS_PARAM_QPOWER_MAX_TX_BEFORE_WAKE = 7, - /** - * QPower SPEC PSPOLL interval - */ - WMI_STA_PS_PARAM_QPOWER_SPEC_PSPOLL_WAKE_INTERVAL = 8, +/** + * QPower SPEC PSPOLL interval + */ +WMI_STA_PS_PARAM_QPOWER_SPEC_PSPOLL_WAKE_INTERVAL = 8, - /** - * Max SPEC PSPOLL to be sent when the PSPOLL response has - * no-data bit set - */ - WMI_STA_PS_PARAM_QPOWER_SPEC_MAX_SPEC_NODATA_PSPOLL = 9, +/** + * Max SPEC PSPOLL to be sent when the PSPOLL response has + * no-data bit set + */ +WMI_STA_PS_PARAM_QPOWER_SPEC_MAX_SPEC_NODATA_PSPOLL = 9, - /** - * Max value of ITO reset when there is no tx-rx - * after AP has set the TIM bit - */ - WMI_STA_PS_PARAM_MAX_RESET_ITO_COUNT_ON_TIM_NO_TXRX = 10, +/** + * Max value of ITO reset when there is no tx-rx + * after AP has set the TIM bit + */ +WMI_STA_PS_PARAM_MAX_RESET_ITO_COUNT_ON_TIM_NO_TXRX = 10, - /** - * Flag to enable/disable Powersave Optimization - * in WOW - */ - WMI_STA_PS_PARAM_ENABLE_PS_OPT_IN_WOW = 11, +/** + * Flag to enable/disable Powersave Optimization + * in WOW + */ +WMI_STA_PS_PARAM_ENABLE_PS_OPT_IN_WOW = 11, - /** - * Speculative interval in ms - */ - WMI_STA_PS_PARAM_SPEC_WAKE_INTERVAL = 12, +/** + * Speculative interval in ms + */ +WMI_STA_PS_PARAM_SPEC_WAKE_INTERVAL = 12, - /** - * Value determines the ITO level to apply - */ - WMI_STA_PS_PARAM_ITO_LEVEL = 13, - - /** - * TX/RX inactivity time in msec before going to sleep in wow. - * - * The power save SM will monitor tx/rx activity on the VDEV, if no - * activity for the specified msec of the parameter the Power save SM will - * go to sleep. - */ - WMI_STA_PS_PARAM_INACTIVITY_TIME_WOW = 14, }; typedef struct { @@ -22605,7 +20909,6 @@ enum wmi_peer_type { WMI_PEER_TYPE_TRANS_BSS = 5, /* For creating BSS peer when connecting with non-transmit AP */ WMI_PEER_TYPE_PASN = 6, /* Peer is used for Pre-Association Security Negotiation */ WMI_PEER_TYPE_BRIDGE = 7, /* For creating Dummy Peer in case of 4 Link MLO */ - WMI_PEER_TYPE_MAPC = 8, /* Peer is a MAPC Co-ordinated AP */ WMI_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type is assigned up to 127 */ /* Reserved from 128 - 255 for target internal use.*/ WMI_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */ @@ -22617,12 +20920,6 @@ typedef struct { wmi_mlo_flags mlo_flags; /* only mlo enable flag need by STA mode peer create */ } wmi_peer_create_mlo_params; -#define WMI_PEER_CREATE_GET_HW_PEER_ID_VALID(flags) WMI_GET_BITS(flags,0,1) -#define WMI_PEER_CREATE_SET_HW_PEER_ID_VALID(flags) WMI_SET_BITS(flags,0,1,value) - -#define WMI_PEER_CREATE_GET_IS_11BI_PEER(flags) WMI_GET_BITS(flags,1,1) -#define WMI_PEER_CREATE_SET_IS_11BI_PEER(flags) WMI_SET_BITS(flags,1,1,value) - typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ @@ -22631,20 +20928,7 @@ typedef struct { wmi_mac_addr peer_macaddr; /** peer type: see enum values above */ A_UINT32 peer_type; - /** Peer create flags */ - union { - struct { - A_UINT32 hw_peer_id_valid :1, - is_11bi_peer :1, - reserved :30; - }; - A_UINT32 flags; - }; - /** Global sw peer id, valid only if non-zero */ - A_UINT32 sw_peer_id; - /** Global hardware id, valid only if hw_peer_id_valid is set */ - A_UINT32 hw_peer_id; -/* The TLVs follow this structure: +/* The TLVs follows this structure: * wmi_peer_create_mlo_params mlo_params[]; <-- MLO flags on peer_create * Optional TLV, only present for MLO peers. * If the peer is non-MLO, the array length should be 0. @@ -23122,20 +21406,13 @@ typedef struct { #define WMI_PEER_PARAM_UL_OFDMA_RTD 0x2B /* - * Count and Interval to send unsolicited probe response to a connected STA. - * BIT 0-23 - Interval (in us) - * BIT 24-31 - Count (Number of probe response frame to send) - * - * Count : 0 - Stop sending immediately. - * Count : 1-254 - Send a probe response periodically at given interval - * until count expires. - * Count : 255 - Send a probe response periodically at given interval - * until stopped. + * Send unsolicited probe response to a connected STA. + * 0: Send immediately and stop. + * XX: Send every XX ms continuously. + * 0xFFFFFFFF: Stop sending immediately. */ #define WMI_PEER_PARAM_UNSOL_PROBE_RESP_INTVL 0x2C -#define WMI_PEER_PARAM_SET_MESH_NODE 0x2D -#define WMI_PEER_PARAM_SET_QUALCOMM_NODE 0x2E typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */ @@ -23344,19 +21621,14 @@ typedef struct { #define WMI_PEER_SAFEMODE_EN 0x80000000 /* Fips Mode Enabled */ /** define for peer_flags_ext */ -#define WMI_PEER_EXT_EHT 0x00000001 /* EHT enabled */ -#define WMI_PEER_EXT_320MHZ 0x00000002 /* 320Mhz enabled */ -#define WMI_PEER_EXT_DMS_CAPABLE 0x00000004 -#define WMI_PEER_EXT_HE_CAPS_6GHZ_VALID 0x00000008 /* param he_caps_6ghz is valid or not */ -#define WMI_PEER_EXT_IS_QUALCOMM_NODE 0x00000010 /* Indicates if the peer connecting is a qualcomm node */ -#define WMI_PEER_EXT_IS_MESH_NODE 0x00000020 /* Indicates if the peer connecting is a mesh node */ -#define WMI_PEER_EXT_PROTECTED_TWT 0x00000040 /* Protected TWT operation Support field in Extended RSN Capabilities element */ -#define WMI_PEER_EXT_UHR 0x00000080 /* UHR enabled */ -#define WMI_PEER_EXT_2XLDPC 0x00000100 /* Peer supports 2x LDPC (3888-bit codeword) */ - +#define WMI_PEER_EXT_EHT 0x00000001 /* EHT enabled */ +#define WMI_PEER_EXT_320MHZ 0x00000002 /* 320Mhz enabled */ +#define WMI_PEER_EXT_DMS_CAPABLE 0x00000004 +#define WMI_PEER_EXT_HE_CAPS_6GHZ_VALID 0x00000008 /* param he_caps_6ghz is valid or not */ +#define WMI_PEER_EXT_IS_QUALCOMM_NODE 0x00000010 /* Indicates if the peer connecting is a qualcomm node */ +#define WMI_PEER_EXT_IS_MESH_NODE 0x00000020 /* Indicates if the peer connecting is a mesh node */ +#define WMI_PEER_EXT_PROTECTED_TWT 0x00000040 /* Protected TWT operation Support field in Extended RSN Capabilities element */ #define WMI_PEER_EXT_F_CRIT_PROTO_HINT_ENABLED 0x40000000 -#define WMI_PEER_EXT_SMD_ASSOC 0x80000000 - /** * Peer rate capabilities. @@ -23530,175 +21802,6 @@ typedef struct { wmi_mac_addr link_macaddr; } wmi_pdev_mesh_rx_filter_enable_fixed_param; -typedef struct { - A_UINT32 tlv_header; /** TLV tag (WMITLV_TAG_STRUC_wmi_peer_assoc_operating_mode_params) and len */ - /* rx_nss: - * self rx nss indicated to AP through capability IEs or operating mode IE. - * 1 ~ n: 1ss ~ nss - */ - A_UINT32 rx_nss; - /* tx_nss: - * self tx nss indicated to AP through capability IEs or operating mode IE. - * 1 ~ n: 1ss ~ nss - */ - A_UINT32 tx_nss; - /* bw: - * self BW indicated to AP through capability IEs or operating mode IE, - * refer to wmi_channel_width for definition of the values this field - * can hold. - */ - A_UINT32 bw; -} wmi_peer_assoc_operating_mode_params; - - -typedef enum { - WMI_MGMT_TID_MSDUQ_LINK_SPECIFIC,/* legacy and link peer */ - WMI_MGMT_TID_MSDUQ_LINK_AGNOSTIC, - WMI_MGMT_TID_MSDUQ_TYPE_MAX, -} WMI_MGMT_TID_MSDUQ_TYPE; - -#define WMI_MGMT_MSDUQ_GET_LINK_ID(msduq_type) WMI_GET_BITS(msduq_type,0,3) -#define WMI_MGMT_MSDUQ_SET_LINK_ID(msduq_type) WMI_SET_BITS(msduq_type,0,3,value) -#define WMI_MGMT_MSDUQ_GET_FLOW_TYPE(msduq_type) WMI_GET_BITS(msduq_type,3,5) -#define WMI_MGMT_MSDUQ_SET_FLOW_TYPE(msduq_type) WMI_SET_BITS(msduq_type,3,5,value) - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and Len. Tag: WMITLV_TAG_STRUC_wmi_peer_assoc_mgmt_msduq_params*/ - union { - struct { - A_UINT32 link_id : 3, /* HW Link ID */ - flow_type : 5, /* WMI_MGMT_TID_MSDUQ_TYPE */ - reserved : 24; - }; - A_UINT32 msduq_type; - }; - - /* 40 bit physical address, 256 bytes alligned, LSB 8 bits are zero */ - A_UINT32 mgmt_msduq_paddr_39_8; -} wmi_peer_assoc_mgmt_msduq_params; - -typedef struct { - A_UINT32 tlv_header; /* TAG_ID : WMITLV_TAG_STRUC_wmi_peer_assoc_mgmt_mpduq_params */ - /* 40 bit physical address, 256 bytes alligned, LSB 8 bits are zero */ - A_UINT32 mgmt_mpduq_paddr_39_8; - A_UINT32 pn_paddr_31_0; - A_UINT32 pn_paddr_39_32; -} wmi_peer_assoc_mgmt_mpduq_params; - -#define WMI_HOL_QUEUE_GET_PEER_ID(mpduq_msduq_number) \ - WMI_GET_BITS(mpduq_msduq_number,0,12) -#define WMI_HOL_QUEUE_SET_PEER_ID(mpduq_msduq_number) \ - WMI_SET_BITS(mpduq_msduq_number,0,12,value) -#define WMI_HOL_QUEUE_GET_TID_NUM(mpduq_msduq_number) \ - WMI_GET_BITS(mpduq_msduq_number,12,5) -#define WMI_HOL_QUEUE_SET_TID_NUM(mpduq_msduq_number) \ - WMI_SET_BITS(mpduq_msduq_number,12,5,value) -#define WMI_HOL_QUEUE_GET_MPDUQ_TYPE(mpduq_msduq_number) \ - WMI_GET_BITS(mpduq_msduq_number,17,5) -#define WMI_HOL_MSDUQ_SET_MPDUQ_TYPE(mpduq_msduq_number) \ - WMI_SET_BITS(mpduq_msduq_number,17,5,value) -#define WMI_HOL_QUEUE_GET_MSDUQ_TYPE(mpduq_msduq_number) \ - WMI_GET_BITS(mpduq_msduq_number,22,5) -#define WMI_HOL_MSDUQ_SET_MSDUQ_TYPE(mpduq_msduq_number) \ - WMI_SET_BITS(mpduq_msduq_number,22,5,value) - -typedef struct { - A_UINT32 tlv_header; /* TAG_ID : WMITLV_TAG_STRUC_wmi_peer_assoc_hol_msduq_params */ - - /** - * A_UINT32 - * WMI_HOL_MSDUQ_GET_PEER_ID / WMI_HOL_MSDU_SET_PEER_ID - * peer_id:12, - * - * WMI_HOL_MSDUQ_GET_TID_NUM / WMI_HOL_MSDUQ_SET_TID_NUM - * tid_num:5, - * - * WMI_HOL_MPDUQ_GET_QUEUE_TYPE / WMI_HOL_MPDUQ_SET_QUEUE_TYPE - * mpduq_type:5, - * - * WMI_HOL_MSDUQ_GET_QUEUE_TYPE / WMI_HOL_MSDUQ_SET_QUEUE_TYPE - * msduq_type:5, - * - * rsvd:5; - */ - union { - struct { - A_UINT32 peer_id : 12, - tid_num : 5, - mpduq_type : 5, - msduq_type : 5, - reserved : 5; - }; - A_UINT32 mpduq_msduq_number; - }; - - /* 40 bit address, 256 bytes alligned LSB 8 bits are zero */ - A_UINT32 mpduq_paddr_39_8; - - /* 40 bit address, 256 bytes alligned LSB 8 bits are zero */ - A_UINT32 msduq_paddr_39_8; - - /* First 32 bits for pn physical address */ - A_UINT32 pn_paddr_31_0; - - /* Upper 8 bits of 40 bit pn physical address */ - A_UINT32 pn_paddr_39_32; -} wmi_peer_assoc_hol_msduq_params; -/* - * for backwards compatibility, maintain old version of the name - * (with "mdsu" typo) - */ -typedef wmi_peer_assoc_hol_msduq_params wmi_peer_assoc_hol_mdsuq_params; - -typedef struct { - A_UINT32 tlv_header; /* TAG_ID : WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params */ - - /* control frame protection enable/disable per peer */ - A_UINT32 enable_cfp; - - /* - * MIC Padding Delay Field Values: - * - * Value Delay - * ---------------- - * 0 0 us - * 1 4 us - * 2 8 us - * 3 12 us - * 4 16 us - * 5 20 us - * 6 24 us - * 7 28 us - * 8 32 us - * 9-15 Reserved - */ - A_UINT32 cfp_padding_delay; -} wmi_peer_assoc_cfp_params; /* cfp -> control frame protection */ - -#define WMI_PEER_ASSOC_SMD_FLAGS_GET_ROAM_ENABLED(mlo_flags) WMI_GET_BITS(mlo_flags, 0, 1) -#define WMI_PEER_ASSOC_SMD_FLAGS_SET_ROAM_ENABLED(mlo_flags, value) WMI_SET_BITS(mlo_flags, 0, 1, value) -#define WMI_PEER_ASSOC_SMD_FLAGS_GET_DL_DATA_FORWARDING(mlo_flags) WMI_GET_BITS(mlo_flags, 1, 1) -#define WMI_PEER_ASSOC_SMD_FLAGS_SET_DL_DATA_FORWARDING(mlo_flags, value) WMI_SET_BITS(mlo_flags, 1, 1, value) -#define WMI_PEER_ASSOC_SMD_FLAGS_GET_UL_DATA_FORWARDING(mlo_flags) WMI_GET_BITS(mlo_flags, 2, 1) -#define WMI_PEER_ASSOC_SMD_FLAGS_SET_UL_DATA_FORWARDING(mlo_flags, value) WMI_SET_BITS(mlo_flags, 2, 1, value) - -/* This TLV structure used to pass smd Parameters on peer assoc */ -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params */ - /** The SMD Identifier field indicates a unique identifier for the SMD and is in the format of a 48-bit MAC address. */ - wmi_mac_addr smd_identifier; - /** SMD capabilities defined in 802.11BN-SMD Information element */ - A_UINT32 smd_capabilities; - union { - struct { - A_UINT32 roam_enabled :1, - dl_data_forwarding :1, - ul_data_forwarding :1, - reserved :29; - }; - A_UINT32 smd_flags; - }; -} wmi_peer_assoc_smd_params; /* * PEER assoc_flags for assoc complete: @@ -23708,36 +21811,13 @@ typedef struct { #define WMI_ASSOC_FLAG_FLUSH_PEER_DATA_GET(assoc_flags) WMI_GET_BITS(assoc_flags, 0, 1) #define WMI_ASSOC_FLAG_FLUSH_PEER_DATA_SET(assoc_flags, value) WMI_GET_BITS(assoc_flags, 0, 1, value) -enum wmi_peer_new_assoc { - WMI_PEER_REASSOC = 0, /* Peer Reassoc */ - WMI_PEER_ASSOC = 1, /* Peer Assoc */ - WMI_PEER_CREATE_ASSOC = 2, /* Peer Create and Peer Assoc in single command, - * currently used for SMD case */ - - /* Host <-> Target Peer New Assoc is assigned up to 127 */ - WMI_PEER_NEW_ASSOC_MAX = 127 -}; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_uhr_rate_set */ - /** - * B0-B3 indicates max NSS that supports mcs 0-7 - * B4-B7 indicates max NSS that supports mcs 8-9 - * B8-B11 indicates max NSS that supports mcs 10-11 - * B12-B15 indicates max NSS that supports mcs 12-13 - * B16-B31 reserved - */ - A_UINT32 rx_mcs_set; /* Rx max NSS set */ - A_UINT32 tx_mcs_set; /* Tx max NSS set */ -} wmi_uhr_rate_set; - typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param */ /** peer MAC address */ wmi_mac_addr peer_macaddr; /** VDEV id */ A_UINT32 vdev_id; - /* enum wmi_peer_new_assoc: create_assoc = 2, assoc = 1, reassoc = 0 */ + /** assoc = 1 reassoc = 0 */ A_UINT32 peer_new_assoc; /** peer associd (16 bits) */ A_UINT32 peer_associd; @@ -23863,66 +21943,6 @@ typedef struct { A_UINT32 peer_eht_ops; wmi_ppe_threshold peer_eht_ppet; A_UINT32 assoc_flags; - /** maximum number of spatial streams supported by peer for tx */ - A_UINT32 peer_max_tx_nss; - /* max_downlink_nss: - * max downlink nss, intersected between self rx and peer tx. - * 1~N means 1ss~Nss - */ - A_UINT32 max_downlink_nss; - - /** Peer create flags */ - union { - struct { - A_UINT32 hw_peer_id_valid : 1, - peer_type_valid : 1, - /** - * Host sets these peer_cck [rx,tx] support_5ghz fields - * based on the intersection of AP and self-capabilities. - * Example: - * On the STA, if the peer (AP) supports CCK 5GHz RX - * and the STA supports CCK 5GHz TX, then set - * peer_cck_rx_support_5ghz = 1 - */ - peer_cck_rx_support_5ghz : 1, - peer_cck_tx_support_5ghz : 1, - sam_peer_id_valid : 1, - reserved :27; - }; - A_UINT32 flags; - }; - /** Global sw peer id, valid only if non-zero */ - A_UINT32 sw_peer_id; - /** Global hardware id, valid only if hw_peer_id_valid is set */ - A_UINT32 hw_peer_id; - /** peer type: see enum values above */ - A_UINT32 peer_type; - /** Global SAM Peer ID, valid only if sam_peer_id_valid is set */ - A_UINT32 sam_peer_id; - - /** peer_uhr_cap_mac: - * UHR mac capabilities from BSS beacon UHR cap IE, - * total WMI_MAX_UHRCAP_MAC_SIZE*A_UINT32 bits - */ - A_UINT32 peer_uhr_cap_mac[WMI_MAX_UHRCAP_MAC_SIZE]; - /** peer_uhr_cap_phy: - * UHR phy capabilities from BSS beacon UHR cap IE, - * total WMI_MAX_UHRCAP_PHY_SIZE*A_UINT32 bits - */ - A_UINT32 peer_uhr_cap_phy[WMI_MAX_UHRCAP_PHY_SIZE]; - /** refer to WMI_UHR_OPS_XXX macros */ - A_UINT32 peer_uhr_ops; - /** peer_uhr_ppet: - * UHR Packet Padding Extension (PPE) thresholds from BSS beacon UHR cap IE - */ - wmi_ppe_threshold peer_uhr_ppet; - - /** peer_uhr_cap_dbe: - * UHR DBE Capability Parameters from BSS beacon UHR cap IE, - * total WMI_MAX_UHRCAP_DBE_SIZE*A_UINT32 bits. - * Valid only when DBE Support bit (B10) in peer_uhr_cap_mac is set. - */ - A_UINT32 peer_uhr_cap_dbe[WMI_MAX_UHRCAP_DBE_SIZE]; /* Following this struct are the TLV's: * A_UINT8 peer_legacy_rates[]; @@ -23935,354 +21955,9 @@ typedef struct { * wmi_eht_rate_set peer_eht_rates; <-- EHT capabilities of the peer * wmi_peer_assoc_mlo_partner_link_params link_info[] <-- partner link info * wmi_peer_assoc_tid_to_link_map[] <-- tid to link_map info - * wmi_peer_assoc_operating_mode_params <-- operating mode param that - * host sends to AP in peer assoc req, optional TLV - * --- the below only apply to WMI_PEER_ASSOC_V2_CMD, not WMI_PEER_ASSOC_CMDID - * wmi_peer_uhr_npca_cap_params peer_npca_cap_params[]; <-- peer NPCA - * capabilities, host sends NPCA peer capabilities as an optional TLV - * wmi_peer_create_mlo_params mlo_params[]; <-- MLO flags on peer_create - * Optional TLV, only present for MLO peers. - * If the peer is non-MLO, the array length should be 0. - * Only mlo_enable flag required by MCC to decide MAC address - * to be used. - * wmi_peer_assoc_smd_params peer_assoc_smd_params; - * wmi_uhr_rate_set peer_uhr_rates; <-- UHR capabilities of the peer - * wmi_peer_uhr_npca_op_params npca_op_params[0,1] - * Only present if NPCA enable is set in peer_uhr_ops & - * NPCA support is set in peer_uhr_cap_mac of fixed_param. - * Otherwise, array length should be 0. */ } wmi_peer_assoc_complete_cmd_fixed_param; -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_HW_PEER_ID_VALID_GET(flags) WMI_GET_BITS(flags, 0, 1) -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_HW_PEER_ID_VALID_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) - -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_TYPE_VALID_GET(flags) WMI_GET_BITS(flags, 1, 1) -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_TYPE_VALID_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value) - -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_RX_SUPPORT_5GHZ_GET(flags) WMI_GET_BITS(flags, 2, 1) -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_RX_SUPPORT_5GHZ_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value) - -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_TX_SUPPORT_5GHZ_GET(flags) WMI_GET_BITS(flags, 3, 1) -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_TX_SUPPORT_5GHZ_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value) - -typedef struct { - A_UINT32 tlv_header; - A_UINT32 sw_peer_id; - /* - * flags - * Bit 0 : NPCA Cap supported/Not supported - * WMI_NPCA_PEER_CAP_SUPPORTED_GET / _SET - * - * Bit 1 : NPCA Enabled / Disabled - * WMI_NPCA_PEER_CAP_ENABLED_GET / _SET - * - * Bit 2-7 : NPCA Switch Delay - * The time needed by an NPCA STA to switch from the - * BSS primary channel to the NPCA primary channel, - * in units of 4 us. - * WMI_NPCA_PEER_CAP_SWT_DELAY_GET / _SET - * - * Bit 8:13 : NPCA Switch Back Delay - * The time needed by an NPCA STA to switch from the - * NPCA primary channel to the BSS primary channel, - * in units of 4 us. - * WMI_NPCA_PEER_CAP_SWTB_DELAY_GET / _SET - * - * Bit 14:31: Reserved - */ - A_UINT32 npca_cap; -} wmi_peer_uhr_npca_cap_params; - -#define WMI_NPCA_PEER_CAP_SUPPORTED_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_NPCA_PEER_CAP_SUPPORTED_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) -#define WMI_NPCA_PEER_CAP_ENABLED_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_NPCA_PEER_CAP_ENABLED_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) -#define WMI_NPCA_PEER_CAP_SWT_DELAY_GET(_var) WMI_GET_BITS(_var, 2, 6) -#define WMI_NPCA_PEER_CAP_SWT_DELAY_SET(_var, _val) WMI_SET_BITS(_var, 2, 6, _val) -#define WMI_NPCA_PEER_CAP_SWTB_DELAY_GET(_var) WMI_GET_BITS(_var, 8, 6) -#define WMI_NPCA_PEER_CAP_SWTB_DELAY_SET(_var, _val) WMI_SET_BITS(_var, 8, 6, _val) - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_mode_update_cmd_fixed_params */ - A_UINT32 pdev_id; - /* - * Following this structure is the TLV: - * struct wmi_peer_uhr_npca_cap_params peer_npca_cap_params[num_peers]; - */ -} wmi_peer_uhr_mode_update_cmd_fixed_param; - - -/* npca_op_param macros */ -#define WMI_PEER_UHR_NPCA_OP_PARAM_PRIMARY_CHANNEL_GET(_var) \ - WMI_GET_BITS(_var, 0, 4) -#define WMI_PEER_UHR_NPCA_OP_PARAM_PRIMARY_CHANNEL_SET(_var, _val) \ - WMI_SET_BITS(_var, 0, 4, _val) - -#define WMI_PEER_UHR_NPCA_OP_PARAM_MIN_DURATION_THRESHOLD_GET(_var) \ - WMI_GET_BITS(_var, 4, 4) -#define WMI_PEER_UHR_NPCA_OP_PARAM_MIN_DURATION_THRESHOLD_SET(_var, _val) \ - WMI_SET_BITS(_var, 4, 4, _val) - -#define WMI_PEER_UHR_NPCA_OP_PARAM_SWITCH_DELAY_GET(_var) \ - WMI_GET_BITS(_var, 8, 6) -#define WMI_PEER_UHR_NPCA_OP_PARAM_SWITCH_DELAY_SET(_var, _val) \ - WMI_SET_BITS(_var, 8, 6, _val) - -#define WMI_PEER_UHR_NPCA_OP_PARAM_SWITCH_BACK_DELAY_GET(_var) \ - WMI_GET_BITS(_var, 14, 6) -#define WMI_PEER_UHR_NPCA_OP_PARAM_SWITCH_BACK_DELAY_SET(_var, _val) \ - WMI_SET_BITS(_var, 14, 6, _val) - -#define WMI_PEER_UHR_NPCA_OP_PARAM_INITIAL_QSRC_GET(_var) \ - WMI_GET_BITS(_var, 20, 2) -#define WMI_PEER_UHR_NPCA_OP_PARAM_INITIAL_QSRC_SET(_var, _val) \ - WMI_SET_BITS(_var, 20, 2, _val) - -#define WMI_PEER_UHR_NPCA_OP_PARAM_MOPLEN_NPCA_GET(_var) \ - WMI_GET_BITS(_var, 22, 1) -#define WMI_PEER_UHR_NPCA_OP_PARAM_MOPLEN_NPCA_SET(_var, _val) \ - WMI_SET_BITS(_var, 22, 1, _val) - -#define WMI_PEER_UHR_NPCA_OP_PARAM_DIS_SUBCHAN_BMAP_PRESENT_GET(_var) \ - WMI_GET_BITS(_var, 23, 1) -#define WMI_PEER_UHR_NPCA_OP_PARAM_DIS_SUBCHAN_BMAP_PRESENT_SET(_var, _val) \ - WMI_SET_BITS(_var, 23, 1, _val) - -/* npca_op_param1 macros */ -#define WMI_PEER_UHR_NPCA_OP_PARAM1_DISABLED_SUBCHAN_BITMAP_GET(_var) \ - WMI_GET_BITS(_var, 0, 16) -#define WMI_PEER_UHR_NPCA_OP_PARAM1_DISABLED_SUBCHAN_BITMAP_SET(_var, _val) \ - WMI_SET_BITS(_var, 0, 16, _val) - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_npca_op_params */ - /* - * All below fields are advertised by UHR AP in UHR NPCA Op Param Field - * in UHR Operation IE - * - * Bit 0-3 : NPCA Primary Channel. - * Indicates the channel number of a channel within BSS - * bandwidth that both STA and AP switch to for NPCA operation. - * - * Bit 4-7 : NPCA Minimum Duration Threshold (NMDT). - * FW to convert this value into microsecs using - * 512 + (NMDT * 128) usec. - * - * Bit 8-13 : NPCA Switch Delay, in units of 4 us. - * The time needed by an NPCA AP to switch from the BSS - * primary channel to the NPCA primary channel. - * - * Bit 14-19: NPCA Switch Back Delay, in units of 4 us. - * The time needed by an NPCA AP to switch from the NPCA - * primary channel to the BSS primary channel. - * - * Bit 20-21: Initial NPCA QSRC. - * Indicates the value that is used to initialize the EDCAF - * QSRC[AC] variables when an NPCA STA in the BSS switches - * to NPCA operation. - * - * Bit 22 : MOPLEN NPCA. - * Indicates which conditions can be used to initiate an - * NPCA operation. - * Value 1 means both PHYLEN and MOPLEN operations are - * permitted in BSS. - * Value 0 means only PHYLEN operation is allowed in the BSS. - * - * Bit 23 : NPCA Disabled Subchannel Bitmap Present - * - * Bit 24-31: Reserved - */ - /* Use WMI_PEER_UHR_NPCA_OP_PARAM_ GET/SET macros for each field */ - A_UINT32 npca_op_param; - - /* - * Bit 0-15 : NPCA Disabled Subchannel Bitmap. Valid only when - * WMI_PEER_UHR_NPCA_OP_PARAM_DIS_SUBCHAN_BMAP_PRESENT_GET is - * TRUE. - * The bitmap indexes 20 MHz subchannels in ascending frequency - * order, with the LSB representing the lowest frequency. - * A bit set to 1 indicates the subchannel is punctured, - * while 0 indicates it is not. - * - * Bit 16-31: Reserved - */ - /* Use WMI_PEER_UHR_NPCA_OP_PARAM1_ GET/SET macros for each field */ - A_UINT32 npca_op_param1; -} wmi_peer_uhr_npca_op_params; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_omp_cmd_fixed_param */ - A_UINT32 sw_peer_id; - A_UINT32 pdev_id; - - /* - * Variable-length TLV arrays follow this fixed param: - * wmi_peer_uhr_omp_npca_params peer_omp_npca_params[]; - * Place Holder for other TLVs - */ -} wmi_peer_uhr_omp_cmd_fixed_param; - -typedef struct{ - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_omp_npca_params */ - /* - * Bit0:3: NPCA hw_link_id - * WMI_OMP_NPCA_HW_LINK_ID_GET / _SET - * Bit4: Enable/Disable NPCA params - * WMI_OMP_NPCA_ENABLE_GET / _SET - * Bit5: Update NPCA params - * WMI_OMP_NPCA_UPDATE_GET / _SET - * Bit6:31: Reserved - */ - A_UINT32 omp_npca_caps; - /* - * Bit0:5: NPCA Switch Delay - * The time needed by an NPCA STA to switch from the - * BSS primary channel to the NPCA primary channel, - * in units of 4 us. - * WMI_OMP_NPCA_SWITCH_DELAY_GET / _SET - * - * Bit6:11: NPCA Switch Back Delay - * The time needed by an NPCA STA to switch from the - * NPCA primary channel to the BSS primary channel, - * in units of 4 - * WMI_OMP_NPCA_SWITCH_BACK_DELAY_GET / _SET - * - * Bit12:31: Reserved - */ - A_UINT32 omp_npca_param; -} wmi_peer_uhr_omp_npca_params; - -#define WMI_OMP_NPCA_HW_LINK_ID_GET(_var) WMI_GET_BITS(_var, 0, 4) -#define WMI_OMP_NPCA_HW_LINK_ID_SET(_var, _val) WMI_SET_BITS(_var, 0, 4, _val) - -#define WMI_OMP_NPCA_ENABLE_GET(_var) WMI_GET_BITS(_var, 4, 1) -#define WMI_OMP_NPCA_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 4, 1, _val) - -#define WMI_OMP_NPCA_UPDATE_GET(_var) WMI_GET_BITS(_var, 5, 1) -#define WMI_OMP_NPCA_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 5, 1, _val) - -#define WMI_OMP_NPCA_SWITCH_DELAY_GET(_var) \ - WMI_GET_BITS(_var, 0, 6) -#define WMI_OMP_NPCA_SWITCH_DELAY_SET(_var, _val) \ - WMI_SET_BITS(_var, 0, 6, _val) - -#define WMI_OMP_NPCA_SWITCH_BACK_DELAY_GET(_var) \ - WMI_GET_BITS(_var, 6, 6) -#define WMI_OMP_NPCA_SWITCH_BACK_DELAY_SET(_var, _val) \ - WMI_SET_BITS(_var, 6, 6, _val) - - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_omp_sta_dps_params */ - - /* - * Bit0:3: STA DPS hw_link_id - * WMI_OMP_STA_DPS_HW_LINK_ID_GET / _SET - * Bit4: Enable/Disable STA DPS params - * WMI_OMP_STA_DPS_ENABLE_GET / _SET - * Bit5: Update STA DPS params - * WMI_OMP_STA_DPS_UPDATE_GET / _SET - * Bit6:31: Reserved - */ - A_UINT32 omp_sta_dps_caps; - - /* - * Bit0:5: STA DPS Padding Delay - * WMI_OMP_STA_DPS_PADDING_DELAY_GET / _SET - * - * Bit6:7: Reserved - * - * Bit8:13: STA DPS Transition Delay - * WMI_OMP_STA_DPS_TRANSITION_DELAY_GET / _SET - * - * Bit14:15: Reserved - * - * Bit16: ICF Required - * WMI_OMP_STA_DPS_ICF_REQUIRED_GET / _SET - * - * Bit17: Parameterized Mode - * WMI_OMP_STA_DPS_PARAMETERIZED_MODE_GET / _SET - * - * Bit18:20: LC Mode Bandwidth - * WMI_OMP_STA_DPS_LC_MODE_BANDWIDTH_GET / _SET - * 0 : 20 MHz - * 1 : 40 MHz - * 2 : 80 MHz - * 3 : 160 MHz - * 4 : 320 MHz - * 5-7: Reserved - * - * Bit21:24: LC Mode NSS - * WMI_OMP_STA_DPS_LC_MODE_NSS_GET / _SET - * - * Bit25:28: LC Mode MCS - * WMI_OMP_STA_DPS_LC_MODE_MCS_GET / _SET - * - * Bit29: Mobile AP STA DPS Static HCM - * WMI_OMP_STA_DPS_MOBILE_AP_STATIC_HCM_GET / _SET - * - * Bit30:31: Reserved - */ - A_UINT32 omp_sta_dps_param; -} wmi_peer_uhr_omp_sta_dps_params; - -#define WMI_OMP_STA_DPS_HW_LINK_ID_GET(_var) \ - WMI_GET_BITS(_var, 0, 4) -#define WMI_OMP_STA_DPS_HW_LINK_ID_SET(_var, _val) \ - WMI_SET_BITS(_var, 0, 4, _val) - -#define WMI_OMP_STA_DPS_ENABLE_GET(_var) \ - WMI_GET_BITS(_var, 4, 1) -#define WMI_OMP_STA_DPS_ENABLE_SET(_var, _val) \ - WMI_SET_BITS(_var, 4, 1, _val) - -#define WMI_OMP_STA_DPS_UPDATE_GET(_var) \ - WMI_GET_BITS(_var, 5, 1) -#define WMI_OMP_STA_DPS_UPDATE_SET(_var, _val) \ - WMI_SET_BITS(_var, 5, 1, _val) - -#define WMI_OMP_STA_DPS_PADDING_DELAY_GET(_var) \ - WMI_GET_BITS(_var, 0, 6) -#define WMI_OMP_STA_DPS_PADDING_DELAY_SET(_var, _val) \ - WMI_SET_BITS(_var, 0, 6, _val) - -#define WMI_OMP_STA_DPS_TRANSITION_DELAY_GET(_var) \ - WMI_GET_BITS(_var, 8, 6) -#define WMI_OMP_STA_DPS_TRANSITION_DELAY_SET(_var, _val) \ - WMI_SET_BITS(_var, 8, 6, _val) - -#define WMI_OMP_STA_DPS_ICF_REQUIRED_GET(_var) \ - WMI_GET_BITS(_var, 16, 1) -#define WMI_OMP_STA_DPS_ICF_REQUIRED_SET(_var, _val) \ - WMI_SET_BITS(_var, 16, 1, _val) - -#define WMI_OMP_STA_DPS_PARAMETERIZED_MODE_GET(_var) \ - WMI_GET_BITS(_var, 17, 1) -#define WMI_OMP_STA_DPS_PARAMETERIZED_MODE_SET(_var, _val) \ - WMI_SET_BITS(_var, 17, 1, _val) - -#define WMI_OMP_STA_DPS_LC_MODE_BANDWIDTH_GET(_var) \ - WMI_GET_BITS(_var, 18, 3) -#define WMI_OMP_STA_DPS_LC_MODE_BANDWIDTH_SET(_var, _val) \ - WMI_SET_BITS(_var, 18, 3, _val) - -#define WMI_OMP_STA_DPS_LC_MODE_NSS_GET(_var) \ - WMI_GET_BITS(_var, 21, 4) -#define WMI_OMP_STA_DPS_LC_MODE_NSS_SET(_var, _val) \ - WMI_SET_BITS(_var, 21, 4, _val) - -#define WMI_OMP_STA_DPS_LC_MODE_MCS_GET(_var) \ - WMI_GET_BITS(_var, 25, 4) -#define WMI_OMP_STA_DPS_LC_MODE_MCS_SET(_var, _val) \ - WMI_SET_BITS(_var, 25, 4, _val) - -#define WMI_OMP_STA_DPS_MOBILE_AP_STATIC_HCM_GET(_var) \ - WMI_GET_BITS(_var, 29, 1) -#define WMI_OMP_STA_DPS_MOBILE_AP_STATIC_HCM_SET(_var, _val) \ - WMI_SET_BITS(_var, 29, 1, _val) - - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_ap_oper_bw_cmd_fixed_param */ A_UINT32 vdev_id; @@ -24382,19 +22057,6 @@ typedef struct { * If per_chain_noise_floor value is 0 then it should be ignored. */ A_UINT32 per_chain_noise_floor[WMI_MAX_CHAINS]; - /** - * FW will update the Noise Floor in dBr and send it to host - * if this field is set then host will display NF value in dBr - */ - A_UINT32 nf_dbr_is_valid; - /** - * Noise Floor (NF) value in dBr. If the NF is not converged then - * NF value is returned as 0 to host. Theoretical minimum NF value - * is -101 dB for 20 MHz bandwidth and the max value can be 0. - * PHY reports 0 incase of very high NF values. - * This field should be ignored unless the nf_dbr_is_valid flag is set. - */ - A_UINT32 noise_floor_in_dbr; /** * Following this structure is the optional TLV: @@ -24601,24 +22263,6 @@ typedef struct _wlan_dcs_im_tgt_stats { /** BSS rx cycle count */ A_UINT32 my_bss_rx_cycle_count; - - /*------*/ - /* vdev id and pdev id will be added accordingly in each TLV, - * when combined event for 2 vdevs in case of concurrency. - */ - - /* vdev_id_and_pdev_id_valid: - * If set, then the below vdev_id and pdev_id fields have valid values. - * If not set, then the below vdev_id and pdev_id fields must be ignored. - */ - A_UINT32 vdev_id_and_pdev_id_valid; - - /** vdev id **/ - A_UINT32 vdev_id; /* unique vdev id for DCS stats info */ - - /** pdev id **/ - A_UINT32 pdev_id; /* unique pdev id for DCS stats info */ - /*------*/ } wlan_dcs_im_tgt_stats_t; typedef struct wlan_dcs_awgn_info { @@ -24708,10 +22352,7 @@ typedef struct { * elements (not arrays). union { wlan_dcs_cw_int cw_int; wlan_dcs_im_tgt_stats_t wlan_stat; } int_event; * * wlan_dcs_cw_int cw_int[]; <-- cw_interference event - * wlan_dcs_im_tgt_stats_t wlan_stat[]; <-- wlan im interference stats, - * Contains vdev_id + pdev_id - * to specify who the stats - * are for. + * wlan_dcs_im_tgt_stats_t wlan_stat[]; <-- wlan im interference stats * wmi_dcs_awgn_int_t awgn_int[]; <-- Additive white Gaussian noise (AWGN) interference * wmi_dcs_obss_int_t obss_int[]; <-- Overlapping Basic Service Set (OBSS) interference */ @@ -24830,7 +22471,7 @@ typedef struct { /** unique id identifying the VDEV, generated by the caller */ A_UINT32 vdev_id; /** roam scan RSSI threshold */ - A_UINT32 roam_scan_rssi_thresh; /* 2 GHz threshold */ + A_UINT32 roam_scan_rssi_thresh; /** When using Hw generated beacon RSSI interrupts */ A_UINT32 roam_rssi_thresh_diff; /** 5G scan max count */ @@ -24845,15 +22486,6 @@ typedef struct { A_INT32 rssi_thresh_offset_5g; /** flags for WMI_ROAM_SCAN_RSSI_THRESHOLD Command */ A_UINT32 flags; /* see WMI_ROAM_SCAN_RSSI_THRESHOLD_FLAG defs */ - /* - * If roam_scan_rssi_thresh_5ghz and roam_scan_rssi_thresh_6ghz are 0 - * (due to the host not explicitly filling in values for these fields), - * the FW shall apply the roam_scan_rssi_thresh specification to the - * 5 GHz and 6 GHz bands, along with the 2.4 GHz band that the - * roam_scan_rssi_thresh specification is predominantly intended for. - */ - A_UINT32 roam_scan_rssi_thresh_5ghz; /* 5 GHz threshold */ - A_UINT32 roam_scan_rssi_thresh_6ghz; /* 6 GHz threshold */ /* The TLVs will follow. * wmi_roam_scan_extended_threshold_param extended_param; * wmi_roam_earlystop_rssi_thres_param earlystop_param; @@ -24871,22 +22503,14 @@ typedef struct { /** * btm_config.flags * BIT 0 : Enable/Disable the BTM offload. - * BIT 1-2 : Action on non matching candidate with cache. - * Used WMI_ROAM_BTM_OFLD_NON_MATCHING_CND_XXX + * BIT 1-2 : Action on non matching candidate with cache. Used WMI_ROAM_BTM_OFLD_NON_MATCHING_CND_XXX * BIT 3-5 : Roaming handoff decisions. Use WMI_ROAM_BTM_OFLD_CNDS_MATCH_XXX * BIT 6 : Enable/Disable solicited BTM - * BIT 7 : Roam BTM candidates based on the roam score instead of BTM - * preferred value + * BIT 7 : Roam BTM candidates based on the roam score instead of BTM preferred value * BIT 8 : BTM query preference over 11k neighbor report request * BIT 9 : Send BTM query with preferred candidates list - * BIT 10 : Forward MBO BTM Request to Host if MBO ASSOC RETRY attribute - * is set - * BIT 11 : Detect the missing band from BTM request when compared to - * roam scan results and consider them as valid candidate - * BIT 12 : Defer BTM roam scan if another roam scan is in progress. - * Applicable only when BTM Disassoc imminent and BSS termination - * is not set - * BIT 13-31 : Reserved + * BIT 10 : Forward MBO BTM Request to Host if MBO ASSOC RETRY attribute is set + * BIT 11-31 : Reserved */ #define WMI_ROAM_BTM_SET_ENABLE(flags, val) WMI_SET_BITS(flags, 0, 1, val) #define WMI_ROAM_BTM_GET_ENABLE(flags) WMI_GET_BITS(flags, 0, 1) @@ -24902,12 +22526,8 @@ typedef struct { #define WMI_ROAM_BTM_GET_BTM_QUERY_PREFERENCE_OVER_11K(flags) WMI_GET_BITS(flags, 8, 1) #define WMI_ROAM_BTM_SET_BTM_QUERY_WITH_CANDIDATE_LIST(flags, val) WMI_SET_BITS(flags, 9, 1, val) #define WMI_ROAM_BTM_GET_BTM_QUERY_WITH_CANDIDATE_LIST(flags) WMI_GET_BITS(flags, 9, 1) -#define WMI_ROAM_BTM_SET_FORWARD_MBO_ASSOC_RETRY_BTM_REQUEST_TO_HOST(flags, val) WMI_SET_BITS(flags, 10, 1, val) -#define WMI_ROAM_BTM_GET_FORWARD_MBO_ASSOC_RETRY_BTM_REQUEST_TO_HOST(flags) WMI_GET_BITS(flags, 10, 1) -#define WMI_ROAM_BTM_SET_DETECT_CANDIDATE_FROM_MISSING_BAND_IN_BTM_REQUEST(flags, val) WMI_SET_BITS(flags, 11, 1, val) -#define WMI_ROAM_BTM_GET_DETECT_CANDIDATE_FROM_MISSING_BAND_IN_BTM_REQUEST(flags) WMI_GET_BITS(flags, 11, 1) -#define WMI_ROAM_BTM_SET_DEFER_BTM_SCAN_FLAG(flags, val) WMI_SET_BITS(flags, 12, 1, val) -#define WMI_ROAM_BTM_GET_DEFER_BTM_SCAN_FLAG(flags) WMI_GET_BITS(flags, 12, 1) +#define WMI_ROAM_BTM_SET_FORWARD_MBO_ASSOC_RETRY_BTM_REQUEST_TO_HOST(flags, val) WMI_SET_BITS(flags, 10, 1, val) +#define WMI_ROAM_BTM_GET_FORWARD_MBO_ASSOC_RETRY_BTM_REQUEST_TO_HOST(flags) WMI_GET_BITS(flags, 10, 1) /** WMI_ROAM_BTM_SET_NON_MATCHING_CNDS_ACTION definition: When BTM candidate is not matched with cache by WMI_ROAM_BTM_SET_CNDS_MATCH_CONDITION, determine what to do */ @@ -25005,15 +22625,6 @@ typedef struct { A_UINT32 roam_scan_period_after_inactivity; /* units = milliseconds */ /** roam full scan period value */ A_UINT32 roam_full_scan_period; /* units = milliseconds */ - /** roam_periodic_scan_interval: - * Timer value to periodically trigger the roaming process at - * set intervals during low RSSI roaming trigger. - * Low rssi trigger (Partial/full) --> - * 10s (partial) --> - * 20s (partial) --> - * 30s (partial) and so on. - */ - A_UINT32 roam_periodic_scan_interval; /* units = seconds */ } wmi_roam_scan_period_fixed_param; /** @@ -25037,8 +22648,6 @@ typedef struct { #define WMI_ROAM_SCAN_CHAN_LIST_TYPE_NONE 0x1 #define WMI_ROAM_SCAN_CHAN_LIST_TYPE_STATIC 0x2 #define WMI_ROAM_SCAN_CHAN_LIST_TYPE_DYNAMIC 0x3 -/* Restrict RCL to Neighbor Report and BTM request channels only */ -#define WMI_ROAM_SCAN_CHAN_LIST_TYPE_NEIGHBOR_REPORT 0x4 #define WMI_ROAM_SCAN_LIST_FLAG_FLUSH_STATIC 0x1 /* Flush static roam scan channel list in FW */ #define WMI_ROAM_SCAN_LIST_FLAG_FLUSH_DYNAMIC 0x2 /* Flush dynamic roam scan channel list in FW */ @@ -25098,7 +22707,6 @@ enum { WMI_AUTH_WPA3_SAE_SHA384, WMI_AUTH_FT_RSNA_SAE_SHA384, WMI_AUTH_FT_RSNA_PSK_SHA384, - WMI_AUTH_EPPKE, /* For 11BI */ }; typedef enum { @@ -25207,11 +22815,6 @@ typedef struct { #define WMI_ROAM_SET_SECURITY_SCORE_PERCENTAGE(value32, score_pcnt, security_index) \ WMI_SET_BITS(value32, (8 * (security_index)), 8, score_pcnt) -/* Boost the APs that belong to the same SMD as the current AP.*/ -#define WLAN_ROAM_SCORE_INTRA_SMD_INDEX 0 -#define WMI_ROAM_GET_INTRA_SMD_SCORE_PERCENTAGE(value32, index) WMI_GET_BITS(value32, (8 * (index)), 8) -#define WMI_ROAM_SET_INTRA_SMD_SCORE_PERCENTAGE(value32, score_pcnt, index) WMI_SET_BITS(value32, (8 * (index)), 8, score_pcnt) - /** best_rssi_threshold: Roamable AP RSSI equal or better than this threshold, full RSSI score 100. Units in dBm. good_rssi_threshold: Below this threshold, scoring linear percentage between rssi_good_pcnt and 100. Units in dBm. @@ -25487,16 +23090,6 @@ typedef struct { * considered for the candidates for which MCC will be formed. */ A_UINT32 mcc_score_factor_pcnt; - /* Scoring weightage for privacy support like 11bi */ - A_UINT32 privacy_weightage_pcnt; - /* uhr_weightage_pcnt: - * 11bn weightage out of total score in percentage. - */ - A_UINT32 uhr_weightage_pcnt; - /* smd_weightage_pcnt: - * give weightage to candidate based on SMD support. - */ - A_UINT32 smd_weightage_pcnt; } wmi_roam_cnd_scoring_param; typedef struct { @@ -25568,16 +23161,6 @@ typedef struct { * of the currently associated AP. */ A_UINT32 bg_rssi_threshold; - /** - * IEEE value for auth algorithm - * Authentication algorithm number = 3: - * Simultaneous Authentication of Equals (SAE) - * Authentication algorithm number = 8: - * IEEE 802.1X authentication - * Authentication algorithm number = 9: - * EPPKE authentication - */ - A_UINT32 auth_algo; } wmi_ap_profile; typedef struct { @@ -25594,10 +23177,7 @@ typedef struct { * Refer WLAN_ROAM_SCORE_MAX_BAND_INDEX for possible band_idx values. */ A_UINT32 band_idx; - /** - * The below band weight (2.4 GHz, 5 GHz, 6 GHz), RSSI, and CU factor_value - * and factor_score param values are configured by vendor. - */ + /** Below RSSI/CU factor_value & factor_score param values are configured by vendor */ A_UINT32 rssi_factor_value1; A_UINT32 rssi_factor_value2; A_UINT32 rssi_factor_value3; @@ -25612,9 +23192,6 @@ typedef struct { A_UINT32 cu_factor_value2; A_UINT32 cu_factor_score1; A_UINT32 cu_factor_score2; - A_UINT32 band_weight_2GHz; - A_UINT32 band_weight_5GHz; - A_UINT32 band_weight_6GHz; } wmi_roam_cnd_vendor_scoring_param; /** Support early stop roaming scanning when finding a strong candidate AP @@ -25868,7 +23445,6 @@ typedef struct { A_UINT32 no_ack_timeout; /* In msec. duration to wait before another SW retry made if no ack seen for previous frame */ A_UINT32 roam_candidate_validity_time; /* In msec. validity duration of each entry in roam cache. If the value is 0x0, this field should be disregarded. */ A_UINT32 roam_to_current_bss_disable; /* Disable roaming to current bss */ - A_UINT32 mlo_roam_partner_bringup_by_host; } wmi_roam_offload_tlv_param; @@ -26097,76 +23673,6 @@ typedef struct { wmi_mac_addr mac_addr; } wmi_roam_bss_info_param; -typedef struct { - A_UINT32 tlv_header; - /* These params are filled in the new design done for MLO roam - * optimization; only in roam abort cases Fw deletes partner links - * at the start of roam handoff itself. - * Host needs to take care of bringing up the partner link if - * roam fails based on deleted_ieee_link_id_bmap; - * deleted_ieee_link_id_bmap represents the ieee_link_id of the - * links which were deleted at the start of roam handoff. - * This is filled only for MLO and deleted_ieee_link_id_bmap = 0 - * means no link was deleted. - */ - A_UINT32 deleted_ieee_link_id_bmap; -} wmi_roam_partner_link_param; - -/* - * useful macros defined for flags field in wmi_vdev_repurpose_request_tlv_param */ -#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_GET_REQUEST_INACTIVE(flags) \ - WMI_GET_BITS(flags, 0, 1) -#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_SET_REQUEST_INACTIVE(flags, val) \ - WMI_SET_BITS(flags, 0, 1, val) -#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_GET_REQUEST_DISCONNECT(flags) \ - WMI_GET_BITS(flags, 1, 1) -#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_SET_REQUEST_DISCONNECT(flags, val) \ - WMI_SET_BITS(flags, 1, 1, val) -#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_GET_REQUEST_CONNECT(flags) \ - WMI_GET_BITS(flags, 2, 1) -#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_SET_REQUEST_CONNECT(flags, val) \ - WMI_SET_BITS(flags, 2, 1, val) - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_repurpose_request_tlv_param */ - A_UINT32 repurpose_vdev_id; /* repurposed vdev_id */ - /* flags - refer WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_GET and _SET macro - * BIT 0 - - * Host shall inactive link with sending WMI_MLO_LINK_SET_ACTIVE_CMDID - * before issue WMI_VDEV_UNIFIED_DISCONNECT_CMDID if the bit is set. - * BIT 1 - - * Host shall send WMI_VDEV_UNIFIED_DISCONNECT_CMDID on the - * repurpose_vdev_id if the bit is set. - * BIT 2 - - * Host shall send WMI_VDEV_UNIFIED_CONNECT_CMDID on the - * repurpose_vdev_id if the bit is set. - */ - A_UINT32 flags; - /* bassid: - * repurposed AP bssid, valid when BIT2 is set in flags - */ - wmi_mac_addr bssid; - /* mld_addr: - * repurposed AP mld address, valid when BIT2 is set in flags - */ - wmi_mac_addr mld_addr; - /* smd_addr: - * repurposed AP smd address, valid when BIT2 is set in flags - */ - wmi_mac_addr smd_addr; -} wmi_vdev_repurpose_request_tlv_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_repurpose_resp_cmd_fixed_param */ - A_UINT32 vdev_id; -} wmi_vdev_repurpose_resp_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_repurpose_response_tlv_param */ - A_UINT32 repurpose_vdev_id; /* repurposed vdev_id */ - A_UINT32 status; /* 0 is success */ -} wmi_vdev_repurpose_response_tlv_param; - /* roam_reason: bits 0-3 */ #define WMI_ROAM_REASON_INVALID 0x0 /** invalid reason. Do not interpret reason field */ #define WMI_ROAM_REASON_BETTER_AP 0x1 /** found a better AP */ @@ -26226,9 +23732,6 @@ typedef enum (((roam_reason) & WMI_ROAM_REQUEST_HOST_HW_MODE_CHANGE_MASK) >> \ WMI_ROAM_REQUEST_HOST_HW_MODE_CHANGE_SHIFT) -#define WMI_GET_ROAM_SMD_BSS_TRANSITION(roam_reason) WMI_GET_BITS(roam_reason, 16, 1) -#define WMI_SET_ROAM_SMD_BSS_TRANSITION(roam_reason, val) WMI_SET_BITS(roam_reason, 16, 1, val) - /* Bits 0-3: stores 4 LSbs of trigger reason. * Old host will get trigger reasons <= 15 from this bitfield. * Bit 7 will be 1 always to indicate that bits 8-15 are valid. @@ -26258,7 +23761,6 @@ typedef enum #define WMI_ROAM_NOTIF_SCAN_MODE_SUCCESS_WITH_HO_FAIL 0xb /** indicate that roaming scan mode is successful but cause disconnection and subsequent ** WMI_ROAM_REASON_HO_FAILED is event expected */ #define WMI_ROAM_NOTIF_SCAN_END 0xc /** indicate roam scan end, notif_params to be sent as WMI_ROAM_TRIGGER_REASON_ID */ -#define WMI_ROAM_NOTIF_ROAM_SMD_START 0xd /** indicate that SMD BSS transtion is started, notif_params1 to be sent as requested setup ieee links bitmap for target AP MLD */ /**whenever RIC request information change, host driver should pass all ric related information to firmware (now only support tsepc) * Once, 11r roaming happens, firmware can generate RIC request in reassoc request based on this information @@ -26340,14 +23842,8 @@ typedef struct { enum wlan_roam_invoke_reason { ROAM_INVOKE_REASON_UNDEFINED = 0, /* FW will use default parameters to do roam scan, ignore other parameters like WLM, etc. */ - - /* Neighbor Unreachable Detection */ - ROAM_INVOKE_REASON_NUD_FAILURE, - + ROAM_INVOKE_REASON_NUD_FAILURE, /* Neighbor Unreachable Detection */ ROAM_INVOKE_REASON_USER_SPACE, - - /* Trigger for Out-Of-Quality (OOQ) roaming */ - ROAM_INVOKE_REASON_PREDICTIVE, }; /** WMI_ROAM_INVOKE_CMD: command to invoke roaming forcefully @@ -26980,7 +24476,6 @@ typedef enum event_type_e { WOW_P2P_NOA_EVENT, /* 32 + 14 */ WOW_XGAP_EVENT, /* 32 + 15 */ WOW_PAGE_FAULT_EVENT, /* 32 + 16 */ - WOW_ACTION_FRAME_RECV_EVENT, /* 32 + 17 */ } WOW_WAKE_EVENT_TYPE; typedef enum wake_reason_e { @@ -27082,12 +24577,6 @@ typedef enum wake_reason_e { WOW_REASON_PF_BLOCKING_LAST_TIME, /* C2C scan report LPI AP detect or not event */ WOW_REASON_C2C_DETECT_EVENT, - /* wake up the host in case of TDLS packet reception */ - WOW_REASON_TDLS_PACKET_RX, - /* wake up the host when USD is enabled */ - WOW_REASON_USD, - /* wake up the host when MLO link switch happens */ - WOW_REASON_MLO_LINK_SWITCH_EVENT, /* add new WOW_REASON_ defs before this line */ @@ -27191,18 +24680,6 @@ typedef enum { /* WoW error if close to TBTT */ WMI_WOW_NON_ACK_REASON_CLOSE_TO_TBTT = 12, - - /* WoW error if platform not ready */ - WMI_WOW_NON_ACK_REASON_PLATFORM = 13, - - /* WoW error if resume n processs */ - WMI_WOW_NON_ACK_RESUME_IN_PROCESS = 14, - - /* WoW error UT command */ - WMI_WOW_NON_ACK_REASON_UNIT_TEST_CMD = 15, - - /* WoW error if MCC lite mode active */ - WMI_WOW_NON_ACK_REASON_MCC_LITE = 16, } WMI_WOW_NACK_STATUS; typedef struct { @@ -28042,22 +25519,6 @@ typedef struct { A_UINT32 req_type; } wmi_aggr_state_trig_event_fixed_param; -/* - * WMI_KEY_FIPS_STATUS - * - * Reported to the host in WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID via - * bits[4:5] of key_flags. Use WMI_KEY_FLAGS_FIPS_COMPLIANT_GET/SET macros. - */ -typedef enum { - WMI_KEY_FIPS_NOT_APPROVED = 1, - WMI_KEY_FIPS_APPROVED = 2, -} WMI_KEY_FIPS_STATUS; - -#define WMI_KEY_FLAGS_FIPS_COMPLIANT_GET(key_flags) \ - WMI_GET_BITS(key_flags, 4, 2) -#define WMI_KEY_FLAGS_FIPS_COMPLIANT_SET(key_flags, val) \ - WMI_SET_BITS(key_flags, 4, 2, val) - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ @@ -28066,19 +25527,7 @@ typedef struct { wmi_mac_addr peer_macaddr; /** key index */ A_UINT32 key_ix; - /** key flags — bit definitions (see KEY_USAGE enum in wmi.h): - * bit[0]: key usage type - * 0 = PAIRWISE_USAGE — unicast/pairwise key - * 1 = GROUP_USAGE — broadcast/multicast group key - * bit[1]: TX_USAGE (0x02) — default Tx key (static WEP only) - * bit[2]: PMK_USAGE (0x04) — PMK cache entry - * bit[3]: LTF_USAGE (0x08) — LTF key seed - * bits[4:5]: FIPS compliance status (WMI_KEY_FIPS_STATUS enum) - * 1 = WMI_KEY_FIPS_NOT_APPROVED (WEP, TKIP, WAPI) - * 2 = WMI_KEY_FIPS_APPROVED (AES-CCM/GCM/CMAC/GMAC) - * Use WMI_KEY_FLAGS_FIPS_COMPLIANT_GET/SET to access. - * bits[6:31]: reserved - */ + /** key flags */ A_UINT32 key_flags; /** Event status */ A_UINT32 status; @@ -28757,10 +26206,6 @@ typedef struct { #define WMI_MAX_VENDOR_OUI_ACTION_SUPPORTED_PER_ACTION 10 #define WMI_MAX_VENDOR_OUI_DATA_LENGTH 20 -#define WMI_MAX_EXT_ACTION_ID_OUI_COUNT_FOR_ALLOW_DISALLOW_NSS 30 -#define WMI_MAX_EXT_ACTION_ID_OUI_COUNT_FOR_UL_TX_BEAMFORMER 30 -#define WMI_MAX_VENDOR_OUI_EXT_DATA_LENGTH 64 - typedef enum { WMI_VENDOR_OUI_ACTION_CONNECTION_1X1 = 0, /* Connect in 1X1 only */ @@ -28837,42 +26282,9 @@ typedef enum */ WMI_VENDOR_OUI_ACTION_AUTH_ASSOC_6MBPS_2GHZ = 17, - /* - * Disable dynamic SMPS if OUI matches - */ - WMI_VENDOR_OUI_ACTION_DISABLE_DYNAMIC_SMPS = 18, - - /* - * Keep sending qos null frame on P2P interface when final bmiss is - * detected, if specific vendor OUI matches. - * If an ACK is received, suppress reporting the final beacon miss - * to the host to avoid triggering a disconnect. - */ - WMI_VENDOR_OUI_ACTION_FORCE_TX_NULL_FRAME_ON_P2P = 19, - /* Add any action before this line */ - WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID, - - - /* - * 0-127 is reserved for action IDs for which the data is static. - * Size of the data is fixed and is not configurable. - */ - - /* Dynamic length OUIs starts below */ - - /* connection in 4 x 4 */ - WMI_VENDOR_OUI_ACTION_ALLOW_NSS_GREATER_THAN_2 = 128, - - /* connection in 2 x 2 */ - WMI_VENDOR_OUI_ACTION_DISALLOW_NSS_GREATER_THAN_2 = 129, - - WMI_VENDOR_OUI_ACTION_ENABLE_UL_TX_BEAMFORMER = 130, - - - /* Add any new dynamic length action ID before this line */ - WMI_VENDOR_OUI_ACTION_MAX_EXT_ACTION_ID + WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID } wmi_vendor_oui_action_id; typedef struct { @@ -28882,25 +26294,6 @@ typedef struct { A_UINT32 total_num_vendor_oui; /* total number of OUI present in ini for all actions. ** For first command, this value will be used for allocating memory in FW accordingly */ A_UINT32 num_vendor_oui_ext; /* the number of wmi_vendor_oui_ext for action_id */ - /* total_num_vendor_oui_ext: - * Max possible OUIs which HOST can support for all the extended - * ACTION IDs: WMI_MAX_EXT_ACTION_ID_OUI_COUNT_FOR_*. - * The max ext action id should be less than - * WMI_VENDOR_OUI_ACTION_MAX_EXT_ACTION_ID and greater than - * WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID - */ - A_UINT32 total_num_vendor_oui_ext; - /* num_vendor_oui_ext2: - * The number of wmi_vendor_oui_ext_2 for action_id - * (The number of OUIs that HOST could accomodate in current WMI cmd) - */ - A_UINT32 num_vendor_oui_ext2; - /* - * More data indicates that for this action_id, there are more data - * pending to be sent via the next WMI command. - */ - A_UINT32 more_data; - /* followed by TLVs, an array of structure of type wmi_vendor_oui_ext ** wmi_vendor_oui_ext vendor_oui_ext[num_vendor_oui_ext]; */ @@ -28943,50 +26336,26 @@ typedef struct { } wmi_pdev_set_rx_filter_promiscuous_cmd_fixed_param; typedef enum { - WMI_BEACON_INFO_PRESENCE_OUI_EXT = 1 << 0, - WMI_BEACON_INFO_PRESENCE_MAC_ADDRESS = 1 << 1, - WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_NSS = 1 << 2, - WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_HT = 1 << 3, - WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_VHT = 1 << 4, - WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_BAND = 1 << 5, - WMI_BEACON_INFO_PRESENCE_EXCLUSIVE_MAC_ADDRESS = 1 << 6, + WMI_BEACON_INFO_PRESENCE_OUI_EXT = 1 << 0, + WMI_BEACON_INFO_PRESENCE_MAC_ADDRESS = 1 << 1, + WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_NSS = 1 << 2, + WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_HT = 1 << 3, + WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_VHT = 1 << 4, + WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_BAND = 1 << 5, } wmi_beacon_info_presence_items; typedef struct _wmi_vendor_oui_ext { A_UINT32 tlv_header; - - /* length of data in bytes for this OUI including index byte */ - A_UINT32 buf_data_length; - - /* see enum wmi_beacon_info_presence_items */ - A_UINT32 info_presence_bit_mask; - - A_UINT32 oui_header_length; /* either 3 or 5 bytes */ - - /* oui_data_length: - * Length of oui_data to compare in beacon which follows OUI header. - * Max length is capped to WMI_MAX_VENDOR_OUI_DATA_LENGTH bytes, - * for action ids < 127. - * Max length is capped to WMI_MAX_VENDOR_OUI_EXT_DATA_LENGTH bytes, - * for action ids > 127. - */ - A_UINT32 oui_data_length; - - /* mac_address_length: - * MAC address length in bytes - * (This value will always be 6, but is explicitly specified for sake - * of uniformity and completeness). - */ - A_UINT32 mac_address_length; - + A_UINT32 buf_data_length; /* length of data in bytes for this OUI including index byte */ + A_UINT32 info_presence_bit_mask; /* see enum wmi_beacon_info_presence_items */ + A_UINT32 oui_header_length; /* either 3 or 5 bytes */ + A_UINT32 oui_data_length; /* length of oui_data to compare in beacon which follows OUI header. Max length is capped to WMI_MAX_VENDOR_OUI_DATA_LENGTH bytes */ + A_UINT32 mac_address_length; /* MAC address length in bytes + ** (This value will always be 6, + ** but is explicitly specified for sake + ** of uniformity and completeness). + */ A_UINT32 capability_data_length; /* length of capability in bytes */ - - /* exclusive_mac_address_length: - * Exclusive MAC address length in bytes - * (This value will always be 6, but is explicitly specified for sake - * of uniformity and completeness). - */ - A_UINT32 exclusive_mac_address_length; } wmi_vendor_oui_ext; #define WMI_INFO_CAPABILITY_NSS_MASK 0x0f @@ -29370,66 +26739,9 @@ typedef enum WLAN_COEX_EVENT { typedef struct { A_UINT32 tlv_header; - A_UINT32 coex_profile_evt; /* uses the enum values from WLAN_COEX_EVENT */ + A_UINT32 coex_profile_evt; //uses the enum values from WLAN_COEX_EVENT } wmi_coex_bt_activity_event_fixed_param; -typedef struct { - A_UINT32 tlv_header; -} wmi_coex_policy_stats_cmd_fixed_param; - -#define WMI_COEX_POLICY_STATS_GET_BTC_STATE(coex_stats) \ - WMI_GET_BITS(coex_stats, 0, 2) -#define WMI_COEX_POLICY_STATS_SET_BTC_STATE(coex_stats, value) \ - WMI_SET_BITS(coex_stats, 0, 2, value) - -#define WMI_COEX_POLICY_STATS_GET_UWB_STATE(coex_stats) \ - WMI_GET_BITS(coex_stats, 2, 1) -#define WMI_COEX_POLICY_STATS_SET_UWB_STATE(coex_stats, value) \ - WMI_SET_BITS(coex_stats, 2, 1, value) - -#define WMI_COEX_POLICY_STATS_GET_MWS_STATE(coex_stats) \ - WMI_GET_BITS(coex_stats, 3, 1) -#define WMI_COEX_POLICY_STATS_SET_MWS_STATE(coex_stats, value) \ - WMI_SET_BITS(coex_stats, 3, 1, value) - -#define WMI_COEX_POLICY_STATS_GET_OCS_ALGO_DC(coex_stats) \ - WMI_GET_BITS(coex_stats, 8, 8) -#define WMI_COEX_POLICY_STATS_SET_OCS_ALGO_DC(coex_stats, value) \ - WMI_SET_BITS(coex_stats, 8, 8, value) - -#define WMI_COEX_POLICY_STATS_GET_OCS_NON_WLAN_DC(coex_stats) \ - WMI_GET_BITS(coex_stats, 16, 8) -#define WMI_COEX_POLICY_STATS_SET_OCS_NON_WLAN_DC(coex_stats, value) \ - WMI_SET_BITS(coex_stats, 16, 8, value) - -typedef struct { - A_UINT32 tlv_header; - A_UINT32 mon_period; /* milliseconds units */ - /* Following is the definition for bitfields within the coex_stats word: - * bits 1:0 --> Indicates BTC_STATE (0 - Freerun, 1 - OCS, 3 - Inactive). - * bit 2 --> Indicates UWB_STATE (0 - Inactive, 1 - Active conflict). - * bit 3 --> Indicates MWS_STATE (0 - Inactive, 1 - Active conflict). - * bits 15:8 --> Indicates percentage of the time coex chose OCS policy. - * (Ranges from 0 to 100.) - * bits 23:16 --> Indicates percentage of the time DUT is off channel due - * to OCS policy. (Ranges from 0 to 100.) - */ - union { - A_UINT32 coex_stats; - struct { - A_UINT32 btc_state: 2, /* bits 1:0 */ - uwb_state: 1, /* bit 2 */ - mws_state: 1, /* bit 3 */ - reserved1: 4, /* bits 7:4 */ - ocs_algo_dc: 8, /* bits 15:8 */ - ocs_non_wlan_dc: 8, /* bits 23:16 */ - reserved2: 8; /* bits 31:24 */ - }; - }; - A_UINT32 num_data_bytes; -} wmi_coex_policy_stats_event_fixed_param; - - enum wmm_ac_downgrade_policy { WMM_AC_DOWNGRADE_DEPRIO, WMM_AC_DOWNGRADE_DROP, @@ -29597,23 +26909,7 @@ typedef struct { * 0 - need check sub channel marking * 1 - full bandwidth need put to NOL * Refer to WMI_RADAR_FLAGS_FULL_BW_NOL_GET and _SET macros - * - * Bits 1-16: - * RADAR TYPE field (currently reserved for future use) - * When implemented, this field will indicate the type of - * radar detected, and also the domain. - * For example, a value of 0x4001 means domain = 4 and radar type = 1. - * Refer to WMI_RADAR_FLAGS_RADAR_TYPE_GET and _SET macros. - * - * Bits 17-24: - * RADAR RSSI in dBm in the range of -128 to +127. - * This 8-bit value is interpreted as a twos-complement signed number - * (so for example, 0x80 = -128, 0x0 = 0, and 0x7f = 127). - * This bit field is valid only if the - * WMI_SERVICE_RADAR_FLAGS_RSSI_DBM_SUPPORT - * wmi service flag is set. - * - * [25:31] reserved + * [1:31] reserved */ A_UINT32 flags; } WMI_RADAR_FLAGS; @@ -29621,12 +26917,6 @@ typedef struct { #define WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS 0 #define WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS 1 -#define WMI_RADAR_FLAGS_RADAR_TYPE_BITPOS 1 -#define WMI_RADAR_FLAGS_RADAR_TYPE_NUM_BITS 16 - -#define WMI_RADAR_FLAGS_RSSI_DBM_BITPOS 17 -#define WMI_RADAR_FLAGS_RSSI_DBM_NUM_BITS 8 - #define WMI_RADAR_FLAGS_FULL_BW_NOL_GET(flag) \ WMI_GET_BITS(flag, \ WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \ @@ -29636,176 +26926,6 @@ typedef struct { WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \ WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS, val) -#define WMI_RADAR_FLAGS_RADAR_TYPE_GET(flag) \ - WMI_GET_BITS(flag, \ - WMI_RADAR_FLAGS_RADAR_TYPE_BITPOS, \ - WMI_RADAR_FLAGS_RADAR_TYPE_NUM_BITS) -#define WMI_RADAR_FLAGS_RADAR_TYPE_SET(flag, val) \ - WMI_SET_BITS(flag, \ - WMI_RADAR_FLAGS_RADAR_TYPE_BITPOS, \ - WMI_RADAR_FLAGS_RADAR_TYPE_NUM_BITS, val) - -#define WMI_RADAR_FLAGS_RSSI_DBM_GET(flag) \ - ((A_INT8)WMI_GET_BITS(flag, \ - WMI_RADAR_FLAGS_RSSI_DBM_BITPOS, \ - WMI_RADAR_FLAGS_RSSI_DBM_NUM_BITS)) -#define WMI_RADAR_FLAGS_RSSI_DBM_SET(flag, val) \ - WMI_SET_BITS(flag, \ - WMI_RADAR_FLAGS_RSSI_DBM_BITPOS, \ - WMI_RADAR_FLAGS_RSSI_DBM_NUM_BITS, val) - -/* Bitfield layout constants */ -#define WMI_RADAR_DOMAIN_SHIFT 12 -#define WMI_RADAR_DOMAIN_MASK 0xF000 -#define WMI_RADAR_TYPE_MASK 0x0FFF - -/* Helper Macros */ -#define WMI_MAKE_RADAR_TYPE(domain, type) \ - (((domain) << WMI_RADAR_DOMAIN_SHIFT) | ((type) & WMI_RADAR_TYPE_MASK)) - -#define WMI_GET_RADAR_DOMAIN(radar_type) \ - (((radar_type) & WMI_RADAR_DOMAIN_MASK) >> WMI_RADAR_DOMAIN_SHIFT) - -#define WMI_GET_RADAR_TYPE(radar_type) \ - ((radar_type) & WMI_RADAR_TYPE_MASK) - -#define WMI_IS_RADAR_DOMAIN(radar_type, domain) \ - (GET_RADAR_DOMAIN(radar_type) == (domain)) - -/* Regulatory Domain Codes (4 bits = 0-15) */ -#define WMI_RADAR_DOMAIN_FCC 0x0 /* United States */ -#define WMI_RADAR_DOMAIN_ETSI_301 0x1 /* Europe EN 301 893 */ -#define WMI_RADAR_DOMAIN_ETSI_302 0x2 /* Europe EN 302 502 */ -#define WMI_RADAR_DOMAIN_CHINA 0x3 /* China */ -#define WMI_RADAR_DOMAIN_KOREA 0x4 /* Korea */ -#define WMI_RADAR_DOMAIN_JAPAN_W53 0x5 /* Japan W53 band */ -#define WMI_RADAR_DOMAIN_JAPAN_W56 0x6 /* Japan W56 band */ -#define WMI_RADAR_DOMAIN_JAPAN_W564 0x7 /* Japan W56.4 band */ -#define WMI_RADAR_DOMAIN_UNDEFINED 0xF /* Undefined/Unknown */ -/* Reserved for future use: 0x8-0xE */ - -/* Radar Type Codes within each domain (12 bits = 0-4095) */ -/* ===== FCC (United States) Radar Types ===== */ -#define WMI_DFS_RADAR_FCC_TYPE_0 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x001) -#define WMI_DFS_RADAR_FCC_TYPE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x002) -#define WMI_DFS_RADAR_FCC_TYPE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x004) -#define WMI_DFS_RADAR_FCC_TYPE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x008) -#define WMI_DFS_RADAR_FCC_TYPE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x010) -#define WMI_DFS_RADAR_FCC_TYPE_5 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x020) -#define WMI_DFS_RADAR_FCC_TYPE_6 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x040) - -/* ===== ETSI EN 301 893 Radar Types ===== */ -#define WMI_DFS_RADAR_ETSI301_TYPE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x001) -#define WMI_DFS_RADAR_ETSI301_TYPE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x002) -#define WMI_DFS_RADAR_ETSI301_TYPE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x004) -#define WMI_DFS_RADAR_ETSI301_TYPE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x008) -#define WMI_DFS_RADAR_ETSI301_TYPE_52 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x010) -#define WMI_DFS_RADAR_ETSI301_TYPE_62 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x020) -#define WMI_DFS_RADAR_ETSI301_TYPE_1_2 \ - /* Combined Type 1+2 */ \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x003) -#define WMI_DFS_RADAR_ETSI301_TYPE_1_2_6 \ - /* Combined Type 1+2+6 */ \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x023) - -/* ===== ETSI EN 302 502 Radar Types ===== */ -#define WMI_DFS_RADAR_ETSI302_TYPE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x001) -#define WMI_DFS_RADAR_ETSI302_TYPE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x002) -#define WMI_DFS_RADAR_ETSI302_TYPE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x004) -#define WMI_DFS_RADAR_ETSI302_TYPE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x008) -#define WMI_DFS_RADAR_ETSI302_TYPE_5 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x010) -#define WMI_DFS_RADAR_ETSI302_TYPE_6 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x020) -#define WMI_DFS_RADAR_ETSI302_TYPE_1_2 \ - /* Combined Type 1+2 */ \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x003) - -/* ===== China Radar Types ===== */ -#define WMI_DFS_RADAR_CHN_TYPE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x001) -#define WMI_DFS_RADAR_CHN_TYPE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x002) -#define WMI_DFS_RADAR_CHN_TYPE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x004) -#define WMI_DFS_RADAR_CHN_TYPE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x008) -#define WMI_DFS_RADAR_CHN_TYPE_5 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x010) -#define WMI_DFS_RADAR_CHN_TYPE_6 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x020) -#define WMI_DFS_RADAR_CHN_TYPE_1_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x003) /* Combined Type 1+2 */ -#define WMI_DFS_RADAR_CHN_TYPE_1_2_6 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x023) /* Combined Type 1+2+6 */ -#define WMI_DFS_RADAR_CHN_TYPE_3_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x00C) /* Combined Type 3+4 */ - -/* ===== Korea Radar Types ===== */ -#define WMI_DFS_RADAR_KOR_TYPE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_KOREA, 0x001) -#define WMI_DFS_RADAR_KOR_TYPE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_KOREA, 0x002) -#define WMI_DFS_RADAR_KOR_TYPE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_KOREA, 0x004) -#define WMI_DFS_RADAR_KOR_TYPE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_KOREA, 0x008) - -/* ===== Japan W53 Band Radar Types ===== */ -#define WMI_DFS_RADAR_JAP_W53_FIXED_PULSE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W53, 0x001) -#define WMI_DFS_RADAR_JAP_W53_FIXED_PULSE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W53, 0x002) -#define WMI_DFS_RADAR_JAP_W53_VAR_PULSE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W53, 0x004) -#define WMI_DFS_RADAR_JAP_W53_VAR_PULSE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W53, 0x008) - -/* ===== Japan W56 Band Radar Types ===== */ -#define WMI_DFS_RADAR_JAP_W56_FIXED_PULSE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x001) -#define WMI_DFS_RADAR_JAP_W56_FIXED_PULSE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x002) -#define WMI_DFS_RADAR_JAP_W56_FIXED_PULSE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x004) -#define WMI_DFS_RADAR_JAP_W56_VAR_PULSE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x008) -#define WMI_DFS_RADAR_JAP_W56_VAR_PULSE_5 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x010) -#define WMI_DFS_RADAR_JAP_W56_VAR_PULSE_6 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x020) -#define WMI_DFS_RADAR_JAP_W56_CHIRP \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x040) -#define WMI_DFS_RADAR_JAP_W56_FIXED_PULSE_1_2 \ - /* Combined Type 1+2 */ \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x003) - -/* ===== Japan W56.4 Band Radar Types ===== */ -#define WMI_DFS_RADAR_JAP_W564_HOPPING \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W564, 0x001) - -/* ===== Undefined/Unknown ===== */ -#define WMI_DFS_RADAR_TYPE_UNDEF \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_UNDEFINED, 0xFFF) - - typedef enum { OCAC_COMPLETE = 0, OCAC_ABORT, @@ -30050,32 +27170,13 @@ typedef struct { typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdls_peer_update_cmd_fixed_param */ - A_UINT32 tlv_header; + A_UINT32 tlv_header; /** unique id identifying the VDEV */ - A_UINT32 vdev_id; + A_UINT32 vdev_id; /** peer MAC address */ - wmi_mac_addr peer_macaddr; + wmi_mac_addr peer_macaddr; /** new TDLS state for peer (wmi_tdls_peer_state) */ - A_UINT32 peer_state; - /** need_nss_conf: - * only set to 1 when this TDLS peer is required to operating - * in particular HW mode NSS - */ - A_UINT32 need_nss_conf; - /* preferred_tx_nss: - * for peering state, it means advertised nss, - * for connected state, it means final negotiated nss. - * 1 ~ n: 1ss ~ nss - */ - A_UINT32 preferred_tx_nss; - /* preferred_rx_nss: - * for peering state, it means advertised nss, - * for connected state, it means final negotiated nss. - * 1 ~ n: 1ss ~ nss - */ - A_UINT32 preferred_rx_nss; - - + A_UINT32 peer_state; /* The TLV for wmi_tdls_peer_capabilities will follow. * wmi_tdls_peer_capabilities peer_caps; */ @@ -30137,8 +27238,6 @@ enum wmi_tdls_peer_notification { WMI_TDLS_PEER_DISCONNECTED, /** TDLS/BT role change notification for connection tracker */ WMI_TDLS_CONNECTION_TRACKER_NOTIFICATION, - /** resp to WMI_TDLS_PEER_UPDATE_CMDID as host requested */ - WMI_TDLS_PEER_UPDATE_RESP, }; enum wmi_tdls_peer_reason { @@ -30168,8 +27267,6 @@ enum wmi_tdls_peer_reason { WMI_TDLS_SCAN_STARTED_EVENT, /** TDLS module received a scan complete event, TDLS connection tracker needs to handle this */ WMI_TDLS_SCAN_COMPLETED_EVENT, - /** TDLS max supported operating NSS in current HW mode */ - WMI_TDLS_OPERATING_NSS_CONF_EVENT, }; /* WMI_TDLS_PEER_EVENTID */ @@ -30184,10 +27281,6 @@ typedef struct { A_UINT32 peer_reason; /** unique id identifying the VDEV */ A_UINT32 vdev_id; - /** operating TX NSS 1 ~ n: 1ss ~ nss */ - A_UINT32 tx_nss; - /** operating RX NSS 1 ~ n: 1ss ~ nss */ - A_UINT32 rx_nss; } wmi_tdls_peer_event_fixed_param; /* NOTE: wmi_vdev_mcc_bcn_intvl_change_event_fixed_param would be deprecated. Please @@ -30536,8 +27629,6 @@ typedef enum { WMI_STA_SMPS_PARAM_DTIM_1CHRX_ENABLE = 5, /** Enable/Disable dynamic bw feature */ WMI_STA_SMPS_PARAM_DYNAMIC_BW_SWITCH = 6, - /** Enable/Disable dynamic mode sw feature */ - WMI_STA_SMPS_PARAM_DYNAMIC_MODE_SWITCH = 7, } wmi_sta_smps_param; typedef struct { @@ -30668,8 +27759,8 @@ typedef struct #define LPI_IE_BITMAP_CHRE_RADIO_CHAIN 0x01000000 /* include radio chain and RSSI per chain information if this bit is set - for CHRE */ #define LPI_IE_BITMAP_CHRE_SEC_MODE_MRSNO_WIFI6 0x02000000 /* include MRSNO IE's sec_mode information for WiFi6 if this bit is set - for CHRE */ #define LPI_IE_BITMAP_CHRE_SEC_MODE_MRSNO_WIFI7 0x04000000 /* include MRSNO IE's sec_mode information for WiFi7 if this bit is set - for CHRE */ -#define LPI_IE_BITMAP_INTERWORKING_IE_VENUE_INFO 0x08000000 /* interworking IE venue info (2 bytes) will be filled when this bit is enabled */ +/* 0x08000000 is unused / available */ #define LPI_IE_BITMAP_CHRE_ESS 0x10000000 /* ESS capability info for CHRE */ #define LPI_IE_BITMAP_CHRE_SEC_MODE 0x20000000 /* Security capability info for CHRE */ @@ -30740,11 +27831,6 @@ typedef struct { A_UINT32 ie_len; /** Scan control flags extended (see WMI_SCAN_FLAG_EXT_xxx) */ A_UINT32 scan_ctrl_flags_ext; - /** - * dwell time in msec on active 5 GHz channels. - * If 0, dwell_time_active is used for 5 GHz channels as well. - */ - A_UINT32 dwell_time_active_5ghz; /** * TLV (tag length value) parameters follow the scan_cmd @@ -30756,388 +27842,6 @@ typedef struct { */ } wmi_lpi_start_scan_cmd_fixed_param; - -/* WMI_LPI_SCAN_RESULT_EVENTID_V2 - * TLV (tag length value) parameters follow the fixed_param structure: - * wmi_lpi_scan_result_ind_fixed_param fixed_param; - * uint32_t scanned_freq_list[]; - * wmi_lpi_ap_info_t ap_array[]; - */ - -/** - * Maximum number of AP entries accumulated in LOWI per scan - * (across all batched events). - * FW sends ~7 APs per WMI_LPI_RESULT_EVENTID event - * (limited by LPI_RESULT_EVENT_SIZE=1200 bytes); - * LOWI accumulates batches until scan_is_completed is set. - */ -#define WMI_LPI_MAX_AP_NUM 35 -/** Number of radio chains reported per AP in rssi_chain[] */ -#define WMI_LPI_MAX_RADIO_CHAIN 5 -/** Number of A_UINT32 words used to pack the 12-byte MSAP field */ -#define WMI_LPI_MAX_MSAP_LEN_W 3 - -/** - * wmi_lpi_ap_info_t - Per-AP scan record; element type for TLV #3 - * (WMITLV_TAG_ARRAY_STRUC). - * Since this is a TLV struct (starts with tlv_header), new fields can be - * appended at the end in future versions without breaking older receivers. - * - * ap_info field layout: - * bits [3:0] = ap_flags: cur_connected[0], wifi_802_11_mc[1], - * msap_supported[2], is_active[3] - * bits [16:4] = valid_mask (13 bits); - * indicates which optional fields are present - * bits [23:17] = reserved (must be set to 0 by sender; ignored by receiver) - * bits [31:24] = phy_mode (8 bits); contains a WLAN_PHY_MODE value - * (refer enum WLAN_PHY_MODE defined in wlan_defs.h) - * - * scan_info field layout: - * bits [7:0] = scan_module_id; - * identifies which scan module produced this record: - * 0 = WLS_SCAN_MODID_ANY (any/default) - * 1 = WLS_SCAN_MODID_MGMT_RX_HDR_EXTSCAN (extscan module) - * 2 = WLS_SCAN_MODID_MGMT_RX_HDR_ENLO (ENLO module) - * bits [15:8] = scan_id - * bits [23:16] = flags - * bits [31:24] = scan_cache - * - * ESS_and_SEC_info field layout: - * bits [15:0] = ess - * bits [23:16] = sec_mode; - * bitmask of security modes (WLS_AP_SECUTIRY_MODE_* values): - * 0x00=UNKNOWN - * 0x01=OPEN - * 0x02=WEP - * 0x04=PSK(WPA/WPA2) - * 0x08=EAP(Enterprise) - * 0x10=WPA3_SAE - * 0x20=WPA3_SuiteB - * 0x40=WPA3_OWE - * bits [31:24] = reserved - * - * MCS_and_NSS_info field layout: - * bits [7:0] = tx_nss - * bits [15:8] = tx_mcs - * bits [23:16] = rx_nss - * bits [31:24] = rx_mcs - */ - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_lpi_ap_info_t */ - A_UINT32 tlv_header; - /** 6-byte BSSID; uses existing wmi_mac_addr type */ - wmi_mac_addr bssid; - /** ssid: - * length + up to 32 bytes packed as 8 x A_UINT32; - * uses existing wmi_ssid type - */ - wmi_ssid ssid; - /** Primary channel frequency in MHz */ - A_UINT32 frequency; - /** RSSI in dBm */ - A_INT32 rssi; - /** Packed: - * ap_flags[3:0] | - * valid_mask[16:4] | - * phy_mode[31:24] (WLAN_PHY_MODE value); - * use WMI_LPI_AP_INFO_* macros - */ - A_UINT32 ap_info; - /** Actual dwell time on this channel in milliseconds */ - A_UINT32 dwell_time_ms; - /** TSF offset: local TSF minus AP TSF */ - A_UINT32 tsf_offset; - /** Packed: - * scan_module_id[7:0] | - * scan_id[15:8] | - * flags[23:16] | - * scan_cache[31:24]; use WMI_LPI_SCAN_INFO_* macros - */ - A_UINT32 scan_info; - /** Packed: - * ess[15:0] | - * sec_mode[23:16]; use WMI_LPI_ESS_SEC_* macros - */ - A_UINT32 ESS_and_SEC_info; - /** Packed: - * tx_nss[7:0] | - * tx_mcs[15:8] | - * rx_nss[23:16] | - * rx_mcs[31:24]; use WMI_LPI_MCS_NSS_* macros - */ - A_UINT32 MCS_and_NSS_info; - /** Bitmask of active radio chains used to discover this AP */ - A_UINT32 radio_chain_mask; - /** RSSI per radio chain in dBm; 0 if chain not active */ - A_INT32 rssi_chain[WMI_LPI_MAX_RADIO_CHAIN]; - /** TX power in dBm; valid when WMI_LPI_VALID_TX_POWER set in valid_mask */ - A_UINT32 tx_power; - /** TX rate in Mbps; valid when WMI_LPI_VALID_TX_RATE set in valid_mask */ - A_UINT32 tx_rate; - /** - * TSF timestamp bits [31:0]; - * valid when WMI_LPI_VALID_TSF set in valid_mask - */ - A_UINT32 tsf_lo; - /** - * TSF timestamp bits [63:32]; - * valid when WMI_LPI_VALID_TSF set in valid_mask - */ - A_UINT32 tsf_hi; - /** Age of measurement in milliseconds; valid when WMI_LPI_VALID_AGE set in valid_mask */ - A_UINT32 age; - /** - * MSAP data: 12 bytes packed as 3 x A_UINT32; - * valid when WMI_LPI_VALID_MSAP set in valid_mask - */ - A_UINT32 msap[WMI_LPI_MAX_MSAP_LEN_W]; - /** - * Band center frequency 1 in MHz; - * valid when WMI_LPI_VALID_CNT_FREQ1 set in valid_mask - */ - A_UINT32 band_center_freq_1; - /** - * Band center frequency 2 in MHz; - * valid when WMI_LPI_VALID_CNT_FREQ2 set in valid_mask - */ - A_UINT32 band_center_freq_2; - /** Venue info per IEEE 802.11u Table 9-62: - * bits[7:0] = venue_type (e.g. 0=unspecified, 1=assembly, 2=business, - * 3=educational, 4=factory, 5=institutional, 6=mercantile, - * 7=residential, 8=storage, 9=utility, 10=vehicular, - * 11=outdoor) - * bits[15:8] = venue_info - * (venue group/subtype per IEEE 802.11u Table 9-62) - * valid when WMI_LPI_VALID_VENUE set in valid_mask */ - A_UINT32 venue_type_and_info; -} wmi_lpi_ap_info_t; - - -/** - * wmi_lpi_scan_result_ind_fixed_param - - * Fixed params for TLV #1 of WMI_LPI_SCAN_RESULT_EVENTID_V2. - * Tag: WMITLV_TAG_STRUC_wmi_lpi_scan_result_ind_fixed_param. - * TLV #2 (freq_list) and TLV #3 (ap_array) follow this struct - * in the event buffer. - * Scan completion is signalled by WMI_LPI_STATUS_EVENTID (unchanged); - */ -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_lpi_scan_result_ind_fixed_param */ - A_UINT32 tlv_header; - /** - * Request ID echoed from the triggering scan request. - * For snoop scans, WLS substitutes the snoop subscriber's req_id. - */ - A_UINT32 req_id; - /** - * Country code from scanned_freq_list: 4 ASCII bytes packed little-endian - */ - A_UINT32 country_code; - /** Scan type performed: 0=passive, 1=active, 2=active+passive DFS */ - A_UINT32 scan_type_performed; - /** - * Radio chain preference used for this scan: - * 0=default, 1=low-latency, 2=low-power, 3=hi-accuracy - */ - A_UINT32 radio_chain_pref; -/** - * TLV (tag length value) parameters follow the fixed_param structure: - * A_UINT32 freq_list[]; // scanned frequencies in MHz; one per word - * wmi_lpi_ap_info_t ap_array[]; // per-AP scan records; - * // max WMI_LPI_MAX_AP_NUM entries - */ -} wmi_lpi_scan_result_ind_fixed_param; - -/* ---- ap_info field bit positions ---- */ -#define WMI_LPI_AP_INFO_CUR_CONNECTED_S 0 -#define WMI_LPI_AP_INFO_WIFI_MC_S 1 -#define WMI_LPI_AP_INFO_MSAP_SUPPORTED_S 2 -#define WMI_LPI_AP_INFO_IS_ACTIVE_S 3 -/* 13-bit valid_mask starts at bit 4 */ -#define WMI_LPI_AP_INFO_VALID_MASK_S 4 -/* 7-bit reserved field at bits [23:17] */ -#define WMI_LPI_AP_INFO_RESERVED_S 17 -/* 8-bit phy_mode at bits [31:24] */ -#define WMI_LPI_AP_INFO_PHY_MODE_S 24 - -/* ap_info: cur_connected (bit 0) */ -#define WMI_LPI_AP_INFO_SET_CUR_CONNECTED(pap, val) do { \ - (pap)->ap_info |= (((val) & 0x1) << WMI_LPI_AP_INFO_CUR_CONNECTED_S); \ - } while (0) -#define WMI_LPI_AP_INFO_GET_CUR_CONNECTED(pap) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_CUR_CONNECTED_S) & 0x1) - -/* ap_info: wifi_802_11_mc (bit 1) */ -#define WMI_LPI_AP_INFO_SET_WIFI_MC(pap, val) do { \ - (pap)->ap_info |= (((val) & 0x1) << WMI_LPI_AP_INFO_WIFI_MC_S); \ - } while (0) -#define WMI_LPI_AP_INFO_GET_WIFI_MC(pap) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_WIFI_MC_S) & 0x1) - -/* ap_info: msap_supported (bit 2) */ -#define WMI_LPI_AP_INFO_SET_MSAP_SUPPORTED(pap, val) do { \ - (pap)->ap_info |= (((val) & 0x1) << WMI_LPI_AP_INFO_MSAP_SUPPORTED_S); \ - } while (0) -#define WMI_LPI_AP_INFO_GET_MSAP_SUPPORTED(pap) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_MSAP_SUPPORTED_S) & 0x1) - -/* ap_info: is_active (bit 3) */ -#define WMI_LPI_AP_INFO_SET_IS_ACTIVE(pap, val) do { \ - (pap)->ap_info |= (((val) & 0x1) << WMI_LPI_AP_INFO_IS_ACTIVE_S); \ - } while (0) -#define WMI_LPI_AP_INFO_GET_IS_ACTIVE(pap) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_IS_ACTIVE_S) & 0x1) - -/* ap_info: valid_mask (bits [16:4], 13 bits) */ -#define WMI_LPI_AP_INFO_SET_VALID_MASK(pap, val) do { \ - (pap)->ap_info |= (((val) & 0x1FFF) << WMI_LPI_AP_INFO_VALID_MASK_S); \ - } while (0) -#define WMI_LPI_AP_INFO_GET_VALID_MASK(pap) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_VALID_MASK_S) & 0x1FFF) - -/* - * ap_info: reserved (bits [23:17], 7 bits) - * Sender must write 0. Receiver must ignore. - * Reserved for future per-AP flag extensions. - */ - -/* ap_info: phy_mode (bits [31:24], 8 bits) */ -#define WMI_LPI_AP_INFO_SET_PHY_MODE(pap, val) do { \ - (pap)->ap_info |= (((val) & 0xFF) << WMI_LPI_AP_INFO_PHY_MODE_S); \ - } while (0) -#define WMI_LPI_AP_INFO_GET_PHY_MODE(pap) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_PHY_MODE_S) & 0xFF) - -/* Helper: test a valid_mask bit directly in ap_info (valid_mask is at +4) */ -#define WMI_LPI_AP_INFO_VALID(pap, mask) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_VALID_MASK_S) & (mask)) - -/* valid_mask bit values (13-bit field in ap_info[16:4]) */ -#define WMI_LPI_VALID_TX_POWER 0x0001 /* tx_power field present */ -#define WMI_LPI_VALID_TX_RATE 0x0002 /* tx_rate field present */ -#define WMI_LPI_VALID_TSF 0x0004 /* tsf_lo/tsf_hi fields present */ -#define WMI_LPI_VALID_AGE 0x0008 /* age field present */ -#define WMI_LPI_VALID_WIFI_MC 0x0010 /* wifi_802_11_mc value in ap_info[1]*/ -#define WMI_LPI_VALID_MSAP 0x0020 /* msap[] field present */ -#define WMI_LPI_VALID_CNT_FREQ1 0x0040 /* band_center_freq_1 present */ -#define WMI_LPI_VALID_CNT_FREQ2 0x0080 /* band_center_freq_2 present */ -#define WMI_LPI_VALID_VENUE 0x0100 /* venue_type_and_info present */ -#define WMI_LPI_VALID_HT_SCO_BIT0 0x0200 /* HT SCO bit 0 */ -#define WMI_LPI_VALID_HT_SCO_BIT1 0x0400 /* HT SCO bit 1 */ -#define WMI_LPI_VALID_LOC_CIVIC 0x0800 /* Location Civic supported */ -#define WMI_LPI_VALID_LCI 0x1000 /* LCI supported */ - -/* ---- scan_info field bit positions ---- */ -#define WMI_LPI_SCAN_INFO_MODULE_ID_S 0 /* scan_module_id bits [7:0] */ -#define WMI_LPI_SCAN_INFO_SCAN_ID_S 8 /* scan_id bits [15:8] */ -#define WMI_LPI_SCAN_INFO_FLAGS_S 16 /* flags bits [23:16] */ -#define WMI_LPI_SCAN_INFO_CACHE_S 24 /* scan_cache bits [31:24] */ - -/* scan_info: scan_module_id (bits [7:0]) */ -#define WMI_LPI_SCAN_INFO_SET_MODULE_ID(pap, val) do { \ - (pap)->scan_info |= (((val) & 0xFF) << WMI_LPI_SCAN_INFO_MODULE_ID_S); \ - } while (0) -#define WMI_LPI_SCAN_INFO_GET_MODULE_ID(pap) \ - (((pap)->scan_info >> WMI_LPI_SCAN_INFO_MODULE_ID_S) & 0xFF) - -/* scan_info: scan_id (bits [15:8]) */ -#define WMI_LPI_SCAN_INFO_SET_SCAN_ID(pap, val) do { \ - (pap)->scan_info |= (((val) & 0xFF) << WMI_LPI_SCAN_INFO_SCAN_ID_S); \ - } while (0) -#define WMI_LPI_SCAN_INFO_GET_SCAN_ID(pap) \ - (((pap)->scan_info >> WMI_LPI_SCAN_INFO_SCAN_ID_S) & 0xFF) - -/* scan_info: flags (bits [23:16]) */ -#define WMI_LPI_SCAN_INFO_SET_FLAGS(pap, val) do { \ - (pap)->scan_info |= (((val) & 0xFF) << WMI_LPI_SCAN_INFO_FLAGS_S); \ - } while (0) -#define WMI_LPI_SCAN_INFO_GET_FLAGS(pap) \ - (((pap)->scan_info >> WMI_LPI_SCAN_INFO_FLAGS_S) & 0xFF) - -/* scan_info: scan_cache (bits [31:24]) */ -#define WMI_LPI_SCAN_INFO_SET_CACHE(pap, val) do { \ - (pap)->scan_info |= (((val) & 0xFF) << WMI_LPI_SCAN_INFO_CACHE_S); \ - } while (0) -#define WMI_LPI_SCAN_INFO_GET_CACHE(pap) \ - (((pap)->scan_info >> WMI_LPI_SCAN_INFO_CACHE_S) & 0xFF) - -/* ---- ESS_and_SEC_info field bit positions ---- */ -#define WMI_LPI_ESS_SEC_ESS_S 0 /* ess bits [15:0] */ -#define WMI_LPI_ESS_SEC_SEC_MODE_S 16 /* sec_mode bits [23:16] */ - -/* ESS_and_SEC_info: ess (bits [15:0]) */ -#define WMI_LPI_ESS_SEC_SET_ESS(pap, val) do { \ - (pap)->ESS_and_SEC_info |= (((val) & 0xFFFF) << WMI_LPI_ESS_SEC_ESS_S); \ - } while (0) -#define WMI_LPI_ESS_SEC_GET_ESS(pap) \ - (((pap)->ESS_and_SEC_info >> WMI_LPI_ESS_SEC_ESS_S) & 0xFFFF) - -/* ESS_and_SEC_info: sec_mode (bits [23:16]) */ -#define WMI_LPI_ESS_SEC_SET_SEC_MODE(pap, val) do { \ - (pap)->ESS_and_SEC_info |= (((val) & 0xFF) << WMI_LPI_ESS_SEC_SEC_MODE_S); \ - } while (0) -#define WMI_LPI_ESS_SEC_GET_SEC_MODE(pap) \ - (((pap)->ESS_and_SEC_info >> WMI_LPI_ESS_SEC_SEC_MODE_S) & 0xFF) - -/* ---- MCS_and_NSS_info field bit positions ---- */ -#define WMI_LPI_MCS_NSS_TX_NSS_S 0 /* tx_nss bits [7:0] */ -#define WMI_LPI_MCS_NSS_TX_MCS_S 8 /* tx_mcs bits [15:8] */ -#define WMI_LPI_MCS_NSS_RX_NSS_S 16 /* rx_nss bits [23:16] */ -#define WMI_LPI_MCS_NSS_RX_MCS_S 24 /* rx_mcs bits [31:24] */ - -/* MCS_and_NSS_info: tx_nss (bits [7:0]) */ -#define WMI_LPI_MCS_NSS_SET_TX_NSS(pap, val) do { \ - (pap)->MCS_and_NSS_info |= (((val) & 0xFF) << WMI_LPI_MCS_NSS_TX_NSS_S); \ - } while (0) -#define WMI_LPI_MCS_NSS_GET_TX_NSS(pap) \ - (((pap)->MCS_and_NSS_info >> WMI_LPI_MCS_NSS_TX_NSS_S) & 0xFF) - -/* MCS_and_NSS_info: tx_mcs (bits [15:8]) */ -#define WMI_LPI_MCS_NSS_SET_TX_MCS(pap, val) do { \ - (pap)->MCS_and_NSS_info |= (((val) & 0xFF) << WMI_LPI_MCS_NSS_TX_MCS_S); \ - } while (0) -#define WMI_LPI_MCS_NSS_GET_TX_MCS(pap) \ - (((pap)->MCS_and_NSS_info >> WMI_LPI_MCS_NSS_TX_MCS_S) & 0xFF) - -/* MCS_and_NSS_info: rx_nss (bits [23:16]) */ -#define WMI_LPI_MCS_NSS_SET_RX_NSS(pap, val) do { \ - (pap)->MCS_and_NSS_info |= (((val) & 0xFF) << WMI_LPI_MCS_NSS_RX_NSS_S); \ - } while (0) -#define WMI_LPI_MCS_NSS_GET_RX_NSS(pap) \ - (((pap)->MCS_and_NSS_info >> WMI_LPI_MCS_NSS_RX_NSS_S) & 0xFF) - -/* MCS_and_NSS_info: rx_mcs (bits [31:24]) */ -#define WMI_LPI_MCS_NSS_SET_RX_MCS(pap, val) do { \ - (pap)->MCS_and_NSS_info |= (((val) & 0xFF) << WMI_LPI_MCS_NSS_RX_MCS_S); \ - } while (0) -#define WMI_LPI_MCS_NSS_GET_RX_MCS(pap) \ - (((pap)->MCS_and_NSS_info >> WMI_LPI_MCS_NSS_RX_MCS_S) & 0xFF) - - -/* ---- venue_type_and_info field bit positions ---- */ -#define WMI_LPI_VENUE_TYPE_S 0 /* venue_type bits [7:0] */ -#define WMI_LPI_VENUE_INFO_S 8 /* venue_info bits [15:8] */ - -/* venue_type_and_info: venue_type (bits [7:0]) */ -#define WMI_LPI_VENUE_SET_TYPE(pap, val) do { \ - (pap)->venue_type_and_info |= (((val) & 0xFF) << WMI_LPI_VENUE_TYPE_S); \ - } while (0) -#define WMI_LPI_VENUE_GET_TYPE(pap) \ - (((pap)->venue_type_and_info >> WMI_LPI_VENUE_TYPE_S) & 0xFF) - -/* venue_type_and_info: venue_info (bits [15:8]) */ -#define WMI_LPI_VENUE_SET_INFO(pap, val) do { \ - (pap)->venue_type_and_info |= (((val) & 0xFF) << WMI_LPI_VENUE_INFO_S); \ - } while (0) -#define WMI_LPI_VENUE_GET_INFO(pap) \ - (((pap)->venue_type_and_info >> WMI_LPI_VENUE_INFO_S) & 0xFF) - -/* ========================================================================= - * End of WMI_LPI_SCAN_RESULT_EVENTID_V2 definitions - * ====================================================================== */ - - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stop_scan_cmd_fixed_param */ /** Scan requestor ID */ @@ -31192,18 +27896,14 @@ typedef enum { WMI_LPI_STATUS_MEDIUM_BUSY = 6, /** Extscan is the scan client whose scan complete event is triggered */ WMI_LPI_STATUS_EXTSCAN_CYCLE_AND_SCAN_REQ_COMPLETED = 7, - /** LPI scan is suspended*/ - WMI_LPI_STATUS_SCAN_SUSPENDED = 8, -} wmi_lpi_status; -/* preserve old name (with typo) as alias for corrected name */ -typedef wmi_lpi_status wmi_lpi_staus; +} wmi_lpi_staus; typedef struct { - A_UINT32 tlv_header; - A_UINT32 status; /* wmi_lpi_status */ + A_UINT32 tlv_header; + wmi_lpi_staus status; /** Scan requestor ID */ - A_UINT32 scan_req_id; + A_UINT32 scan_req_id; } wmi_lpi_status_event_fixed_param; typedef struct @@ -31708,7 +28408,6 @@ typedef enum { WMI_PEER_CFR_CAPTURE_BW_80MHZ = 2, WMI_PEER_CFR_CAPTURE_BW_160MHZ = 3, WMI_PEER_CFR_CAPTURE_BW_80_80MHZ = 4, - WMI_PEER_CFR_CAPTURE_BW_320MHZ = 5, WMI_PEER_CFR_CAPTURE_BW_MAX, } WMI_PEER_CFR_CAPTURE_BW; @@ -31761,12 +28460,6 @@ typedef enum { WMI_PEER_IND_OMI, /* operating mode indication */ } WMI_PEER_OPER_MODE_IND; - -#define WMI_EHT_PEER_PARAMS_MCS_DISABLE_GET(eht_peer_params) \ - WMI_GET_BITS(eht_peer_params, 0, 1) -#define WMI_EHT_PEER_PARAMS_MCS_DISABLE_SET(eht_peer_params, value) \ - WMI_SET_BITS(eht_peer_params, 0, 1, value) - typedef struct { /** TLV tag and len; tag equals * WMITLV_TAG_STRUC_wmi_peer_oper_mode_change */ @@ -31788,12 +28481,6 @@ typedef struct { * valid for peer_operating mode ind. OMI */ A_UINT32 new_disablemu; - /** eht_peer_params - * bit 0 - eht_mcs15_disable, refer to - * WMI_EHT_PEER_PARAMS_MCS_DISABLE_GET,SET macros - * bits 1 to 31 - reserved - */ - A_UINT32 eht_peer_params; } wmi_peer_oper_mode_change_event_fixed_param; /** FW response when tx failure count has reached threshold @@ -32445,519 +29132,6 @@ typedef struct { */ } wmi_nan_oem_data_cmd_fixed_param; -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_enable_cmd_param */ - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ -/* -* TLVs following this structure: -* wmi_nan_ctrl_config_param nan_ctrl_config[]; -* wmi_nan_disc_band_config_param nan_disc_band_config[]; -*/ -} wmi_nan_enable_cmd_fixed_param; - -typedef enum { - WMI_NAN_DISC_BAND_PRI_2GHZ = 0x01, - WMI_NAN_DISC_BAND_SEC_5GHZ = 0x02, -} WMI_NAN_DISC_BANDS; - -/* Macros for parsing nan_ctrl_flags field */ -#define WMI_NAN_CTRL_FLAGS_GET_ENABLE_RANGING(param) \ - WMI_GET_BITS(param, 0, 1) -#define WMI_NAN_CTRL_FLAGS_SET_ENABLE_RANGING(param, val) \ - WMI_SET_BITS(param, 0, 1, val) -#define WMI_NAN_CTRL_FLAGS_GET_ENABLE_EARLY_DW_TERMINATION(param) \ - WMI_GET_BITS(param, 1, 1) -#define WMI_NAN_CTRL_FLAGS_SET_ENABLE_EARLY_DW_TERMINATION(param, val) \ - WMI_SET_BITS(param, 1, 1, val) - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_enable_cmd_fixed_param */ - A_UINT32 master_pref; /* Master preference value for cluster formation */ - /* Cluster ID used for synchronization. - * The value (lower 4 bytes) is sent in network byte order (big-endian). - * If set to 0, the firmware will generate a randomized cluster ID. - */ - A_UINT32 cluster_id; - /* Service ID value for publish beacon */ - A_UINT32 service_id_bcn_val; - /* Max hop count allowed for cluster joining */ - A_UINT32 hop_count_limit_val; - /* Service ID value for subscribe beacon */ - A_UINT32 subscribe_sid_beacon_val; - A_UINT32 config_tx_rx_chains; /* TX/RX chain configuration */ - /* Bitfield for NAN control options, - * use WMI_NAN_CTRL_FLAGS_SET_* and WMI_NAN_CTRL_FLAGS_GET_* macros - * for access - */ - union { - struct { - A_UINT32 - /* Enable ranging capability */ - enable_ranging: 1, - - /* Enable early termination of Discovery Window */ - enable_early_dw_termination:1, - - reserved: 30; /* reserved for future use */ - }; - A_UINT32 nan_ctrl_flags; /* 32-bit control flags word */ - }; - A_UINT32 supp_disc_bands; /* Possible values are enum WMI_NAN_DISC_BANDS */ - /* warmup_timer_value: - * NANWarmUp timer value in seconds, to be used when starting - * a NAN cluster as part of NAN enablement. - * If warmup_timer_value == 0, target needs to use default 120 sec, - * as mentioned in spec. - */ - A_UINT32 warmup_timer_value; -/* -* TLVs following this structure: -* wmi_nan_disc_band_config_param nan_disc_band_config[]; -*/ -} wmi_nan_ctrl_config_param; - -/* Macros for parsing scan_params field */ -#define WMI_NAN_DISC_SCAN_PARAMS_GET_DWELL_MS(param) \ - WMI_GET_BITS(param, 0, 16) -#define WMI_NAN_DISC_SCAN_PARAMS_SET_DWELL_MS(param, val) \ - WMI_SET_BITS(param, 0, 16, val) - -#define WMI_NAN_DISC_SCAN_PARAMS_GET_INTERVAL_SEC(param) \ - WMI_GET_BITS(param, 16, 16) -#define WMI_NAN_DISC_SCAN_PARAMS_SET_INTERVAL_SEC(param, val) \ - WMI_SET_BITS(param, 16, 16, val) - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_band_config_param */ - /* Channel frequency (in MHz) for discovery */ - A_UINT32 chan_freq; - /* Encoded scan parameters (use WMI_NAN_DISC_SCAN_PARAMS_GET/SET macros) */ - union { - struct { - A_UINT32 - dwell_ms: 16, - interval_sec: 16; - }; - A_UINT32 scan_params_word; - }; - /* - * Committed/Awake DW interval. Valid values range: 0-5. - * 0 indicates no wakeup for DW and can't be used on 2.4GHz band, - * otherwise 2^(n-1). - */ - A_UINT32 awake_dw_intval; - /* - * RSSI threshold (in dBm) indicating close proximity; used to determine - * if a received Synchronization Beacon from a peer within the - * same NAN cluster should trigger a role change from Master to Non-Master - * Sync when the peer has a higher Master Rank. - */ - A_INT32 rssi_close_val; - /* - * RSSI threshold (in dBm) indicating medium proximity; used to evaluate - * if three or more Synchronization Beacons from peers within the - * same NAN cluster justify a role change from Master to Non-Master Sync - * when those peers have higher Master Ranks. - */ - A_INT32 rssi_middle_val; - /* - * RSSI threshold (in dBm) used to determine if a peer is within proximity - * during a match event - */ - A_INT32 rssi_proximity_val; - /* Window size for RSSI averaging (based on number of beacons received) */ - A_UINT32 rssi_avg_window_size; -} wmi_nan_disc_band_config_param; - -typedef enum { - WMI_NAN_CONF_CHANGE_MASTER_PREF = 0x00000001, - WMI_NAN_CONF_CHANGE_CLUSTER_ID = 0x00000002, - WMI_NAN_CONF_CHANGE_SERVICE_ID_BCN_VAL = 0x00000004, - WMI_NAN_CONF_CHANGE_HOP_COUNT_LIMIT_VAL = 0x00000008, - WMI_NAN_CONF_CHANGE_SUBSCRIBE_SID_BCN_VAL = 0x00000010, - WMI_NAN_CONF_CHANGE_CONFIG_TX_RX_CHAINS = 0x00000020, - WMI_NAN_CONF_CHANGE_ENABLE_RANGING = 0x00000040, - WMI_NAN_CONF_CHANGE_ENABLE_EARLY_DW_TERM = 0x00000080, - WMI_NAN_CONF_CHANGE_SUPP_DISC_BANDS = 0x00000100, -} WMI_NAN_CONFIG_CHANGE_PARAM; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_config_cmd_fixed_param */ - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ - /* Bitmap indicating which NAN configuration parameters have changed and - * need to be updated by the target firmware. Each bit corresponds to a - * specific parameter defined in WMI_NAN_CONFIG_CHANGE_PARAM. - */ - A_UINT32 nan_conf_change_bitmap; - /* nan_availability_attributes_len: - * number of valid bytes (i.e. excluding final alignment-padding) - * in the TLV nan_availability_attributes_data[] - */ - A_UINT32 nan_availability_attributes_len; -/* - * TLVs following this structure: - * wmi_nan_ctrl_config_param nan_ctrl_config[]; - * wmi_nan_disc_band_config_param nan_disc_band_config[]; - * A_UINT8 nan_availability_attributes_data[]: - * NAN availability attributes sent down (along with header) - * are sent in stream of bytes (ieee80211 protocol order). - * The host must manually byteswap these bytes within each 4-byte word - * if the host's endianness doesn't match the target's, to ensure the - * expected byte order is maintained. - */ -} wmi_nan_config_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disable_cmd_fixed_param */ - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ -} wmi_nan_disable_cmd_fixed_param; - -#define WMI_NAN_SCHED_NOT_AVAIL_SLOT 0xFF - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_channel */ - - A_UINT32 chan_freq; /* in MHz */ - A_UINT32 center_freq1; /* Center frequency 1 in MHz */ - A_UINT32 center_freq2; /* Center frequency 2 in MHz */ - /* Channel bandwidth. Possible values are wmi_channel_width */ - A_UINT32 chan_width; - A_UINT32 rx_nss; /* advertised RX NSS */ - /* chan_entry_fields: - * opaque 6-byte bytestream (with a 2-byte alignment suffix) - * The host must manually byteswap these bytes within each 4-byte word - * if the host's endianness doesn’t match the target’s, to ensure the - * network byte order is maintained. - */ - A_UINT8 chan_entry_fields[8]; -} wmi_nan_channel; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_local_schedule_cmd_fixed_param */ - - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations (NMI vdev) */ - /** schedule_chan_bitmap_len: - * number of valid bytes (i.e. excluding final alignment-padding) - * in the TLV nan_schedule_chan_bitmap[] - */ - A_UINT32 schedule_chan_bitmap_len; -/* - * TLVs following this structure: - * - * A_UINT8 nan_schedule_chan_bitmap[]; - * A mapping of time slots to channel indexes in the schedule's - * committed_channel_list. Each slot lasts 16TUs. - * An unscheduled slot will be set to WMI_NAN_SCHED_NOT_AVAIL_SLOT. - * wmi_nan_channel committed_nan_channel_list[]; - */ -} wmi_nan_local_schedule_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cmd_fixed_param */ - - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations (NMI vdev) */ - wmi_mac_addr peer_nmi_addr; - /** schedule_chan_bitmap_len: - * number of valid bytes (i.e. excluding final alignment-padding) - * in the TLV nan_schedule_chan_bitmap[] - */ - A_UINT32 schedule_chan_bitmap_len; - A_UINT32 peer_committed_dw; - A_UINT32 peer_max_chan_switch; -/* - * TLVs following this structure: - * - * A_UINT8 nan_schedule_chan_bitmap[]: - * A mapping of time slots to channel indexes in the schedule's - * committed_channel_list. Each slot lasts 16TUs. - * An unscheduled slot will be set to WMI_NAN_SCHED_NOT_AVAIL_SLOT. - * wmi_nan_channel committed_nan_channel_list[]; - */ -} wmi_nan_peer_schedule_cmd_fixed_param; - -typedef enum { - WMI_NAN_PEER_FLAG_PMF = 0x01, - WMI_NAN_PEER_FLAG_AUTHENTICATED = 0x02, - WMI_NAN_PEER_FLAG_ASSOCIATED = 0x04, - WMI_NAN_PEER_FLAG_AUTHORIZED = 0x08, -} WMI_NAN_PEER_PARAMS_FLAGS; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_peer_params_cmd_fixed_param */ - - /* Virtual device ID used for NAN operations (either NMI or NDI VDEV) */ - A_UINT32 vdev_id; - /** peer NMI MAC address */ - wmi_mac_addr peer_nmi_addr; - /** peer NDI MAC address */ - wmi_mac_addr peer_ndi_macaddr; - /** peer_flags: - * peer station flags, for indicating PMF is enabled, - * authorization is done etc.. - * Possible values are enum WMI_NAN_PEER_PARAMS_FLAGS. - */ - A_UINT32 peer_flags; - /** peer_caps_ie_len: - * number of valid bytes (i.e. excluding final alignment-padding) - * in the TLV peer_caps_ie_data[] - */ - A_UINT32 peer_caps_ie_len; -/* - * TLVs following this structure: - * - * A_UINT8 peer_caps_ie_data[]: - * HT/VHT/HE/EHT etc. capability IEs (along with header) - * are sent in stream of bytes (ieee80211 protocol order). - * The host must manually byteswap these bytes within each 4-byte word - * if the host's endianness doesn’t match the target’s, to ensure the - * expected byte order is maintained. - */ -} wmi_nan_peer_params_cmd_fixed_param; - -/* - * NAN service request type values for - * wmi_nan_disc_service_req_cmd_fixed_param.service_req_type. - * Maps to NL80211_NAN_FUNC_PUBLISH / SUBSCRIBE / FOLLOW_UP. - */ -typedef enum { - WMI_NAN_DISC_SERVICE_REQ_PUBLISH = 1, - WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE = 2, - WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP = 3, -} WMI_NAN_DISC_SERVICE_REQ_TYPE; - -/* - * Publish type values for - * wmi_nan_disc_service_req_cmd_fixed_param.publish_type. - * Valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_PUBLISH. - * Maps to NL80211_NAN_FUNC_PUBLISH_TYPE. - */ -typedef enum { - WMI_NAN_DISC_PUBLISH_UNSOLICITED = 0, - WMI_NAN_DISC_PUBLISH_SOLICITED = 1, - WMI_NAN_DISC_PUBLISH_UNSOLICITED_SOLICITED = 2, -} WMI_NAN_DISC_PUBLISH_TYPE; - -/* - * NAN discovery service request termination reason values for - * wmi_nan_disc_service_req_terminated_event_fixed_param.reason. - * Maps to nl80211_nan_func_term_reason. - */ -typedef enum { - /** - * Service request was cancelled by an explicit host request - * (WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID). - * Maps to NL80211_NAN_FUNC_TERM_REASON_USER_REQUEST = 0 - */ - WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_USER_REQUEST = 0, - /** - * Service request lifetime (TTL) elapsed; - * FW auto-expired the service request. - * Maps to NL80211_NAN_FUNC_TERM_REASON_TTL_EXPIRED = 1 - */ - WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_TTL_EXPIRED = 1, - /** - * FW encountered an internal error and could not maintain - * the service request. - * Also covers NAN_TERMINATED_REASON_COUNT_REACHED from the HAL path. - * Maps to NL80211_NAN_FUNC_TERM_REASON_ERROR = 2 - */ - WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_ERROR = 2, -} WMI_NAN_DISC_SERVICE_REQ_TERM_REASON; - -/* - * SDEA (Service Descriptor Extension Attribute) control field bit accessors. - * Maps to NL80211_ATTR_NAN_FUNC_SDEA_CTRL / cfg80211_nan_func.sdea_ctrl. - * Bit 2 : Data Path Required - * Bit 6 : Security Required - */ -#define WMI_NAN_DISC_SDEA_CTRL_GET_DATA_PATH_REQ(sdea) \ - WMI_GET_BITS(sdea, 2, 1) -#define WMI_NAN_DISC_SDEA_CTRL_SET_DATA_PATH_REQ(sdea, v) \ - WMI_SET_BITS(sdea, 2, 1, v) -#define WMI_NAN_DISC_SDEA_CTRL_GET_SECURITY_REQ(sdea) \ - WMI_GET_BITS(sdea, 6, 1) -#define WMI_NAN_DISC_SDEA_CTRL_SET_SECURITY_REQ(sdea, v) \ - WMI_SET_BITS(sdea, 6, 1, v) - -/* - * service_req_flags field bit accessors for - * wmi_nan_disc_service_req_cmd_fixed_param.service_req_flags. - * Packs all boolean cfg80211_nan_func fields into one A_UINT32. - * - * Bit 0 : close_range — match only with close-range peers - * (NL80211_ATTR_NAN_FUNC_CLOSE_RANGE) - * Bit 1 : publish_bcast — send in broadcast discovery beacons; - * valid only for Publish - * (NL80211_ATTR_NAN_FUNC_PUBLISH_BCAST) - * Bit 2 : subscribe_active — send active subscribe queries; - * valid only for Subscribe - * (NL80211_ATTR_NAN_FUNC_SUBSCRIBE_ACTIVE) - * Bit 3 : gtk_required — group temporal key required for - * multicast data - * (NL80211_ATTR_NAN_FUNC_GTK_REQUIRED) - * Bit 4 : pairing_setup — enable initial NAN3 pairing setup - * (NL80211_ATTR_NAN_FUNC_PAIRING_SETUP) - * Bit 5 : pairing_cache — enable persistent NAN3 pairing cache - * (NL80211_ATTR_NAN_FUNC_PAIRING_CACHE) - * Bit 6 : pairing_verify — enable NAN3 pairing re-verification - * (NL80211_ATTR_NAN_FUNC_PAIRING_VERIFY) - * Bit 7 : nd_pmk_valid — nd_pmk TLV is populated and valid - * (NL80211_ATTR_NAN_FUNC_ND_PMK) - * Bits 8-31 : reserved, must be set to 0 - */ -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_CLOSE_RANGE(f) \ - WMI_GET_BITS(f, 0, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_CLOSE_RANGE(f, v) \ - WMI_SET_BITS(f, 0, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_PUBLISH_BCAST(f) \ - WMI_GET_BITS(f, 1, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_PUBLISH_BCAST(f, v) \ - WMI_SET_BITS(f, 1, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_SUBSCRIBE_ACTIVE(f) \ - WMI_GET_BITS(f, 2, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_SUBSCRIBE_ACTIVE(f, v) \ - WMI_SET_BITS(f, 2, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_GTK_REQUIRED(f) \ - WMI_GET_BITS(f, 3, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_GTK_REQUIRED(f, v) \ - WMI_SET_BITS(f, 3, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_PAIRING_SETUP(f) \ - WMI_GET_BITS(f, 4, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_PAIRING_SETUP(f, v) \ - WMI_SET_BITS(f, 4, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_PAIRING_CACHE(f) \ - WMI_GET_BITS(f, 5, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_PAIRING_CACHE(f, v) \ - WMI_SET_BITS(f, 5, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_PAIRING_VERIFY(f) \ - WMI_GET_BITS(f, 6, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_PAIRING_VERIFY(f, v) \ - WMI_SET_BITS(f, 6, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_ND_PMK_VALID(f) \ - WMI_GET_BITS(f, 7, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_ND_PMK_VALID(f, v) \ - WMI_SET_BITS(f, 7, 1, v) - -/** - * WMI command to add a NAN discovery function - * (Publish / Subscribe / Follow-up). - * WMI equivalent of NL80211_CMD_ADD_NAN_FUNCTION / cfg80211_nan_func. - */ -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_service_req_cmd_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the NMI VDEV */ - A_UINT32 vdev_id; - /** - * NAN service request type: - * 1=Publish, 2=Subscribe, 3=Follow-up; - * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE - */ - A_UINT32 service_req_type; - /** - * Unique cookie assigned by cfg80211 for this function. - * Split into two A_UINT32 words for endian portability. - * Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64. - */ - A_UINT32 cookie_low32; /* lower 32 bits of 64-bit cookie value */ - A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */ - /** - * Function lifetime in Discovery Windows; - * 0 = active until explicitly deleted - */ - A_UINT32 ttl; - /** - * Publish transmission mode; - * valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_PUBLISH; - * refer to WMI_NAN_DISC_PUBLISH_TYPE - */ - A_UINT32 publish_type; - /** - * Local function instance ID to which this follow-up is associated; - * valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP - */ - A_UINT32 followup_instance_id; - /** - * Requestor instance ID from the prior match event; - * valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP - */ - A_UINT32 followup_requestor_id; - /** - * NMI MAC address of the peer to send the follow-up to; - * valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP - */ - wmi_mac_addr followup_dest; - /** - * SDEA control field bitmap; use WMI_NAN_DISC_SDEA_CTRL_GET/SET macros; - * bit2=Data Path Required, bit6=Security Required - */ - A_UINT32 sdea_ctrl; - /** - * Bitmap of supported NAN3 pairing bootstrap methods; - * bit0=Opportunistic, bit1=PIN - */ - A_UINT32 pairing_bootstrap_methods; - /** - * Bloom filter index for the SRF; - * valid only when TLV srf_bf[] is non-empty - */ - A_UINT32 srf_bf_idx; - /** - * SRF filter mode: - * 0=exclude listed entries, 1=include only listed entries - */ - A_UINT32 srf_include; - /** - * Packed boolean flags; use WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET/SET macros; - * bit0=close_range, bit1=publish_bcast, bit2=subscribe_active, - * bit3=gtk_required, bit4=pairing_setup, bit5=pairing_cache, - * bit6=pairing_verify, bit7=nd_pmk_valid, bits8-31=reserved - */ - A_UINT32 service_req_flags; - /** Actual number of bytes in TLV serv_spec_info[]; max 255 */ - A_UINT32 serv_spec_info_len; - /** Actual number of bytes in TLV srf_bf[] */ - A_UINT32 srf_bf_len; - /** Actual number of bytes in TLV rx_match_filter[] */ - A_UINT32 rx_match_filter_len; - /** Actual number of bytes in TLV tx_match_filter[] */ - A_UINT32 tx_match_filter_len; - /** extra_nan_attrs_len: - * number of valid bytes (i.e. excluding final alignment-padding) - * in the TLV extra_nan_attrs[] - */ - A_UINT32 extra_nan_attrs_len; - /** - * TLV (tag length value) parameters follow this structure: - * A_UINT8 service_id[]; 6-byte NAN Service ID, - * zero-padded to 8 bytes - * A_UINT8 serv_spec_info[]; Service Specific Info, max 255 bytes - * A_UINT8 srf_bf[]; SRF Bloom filter data - * wmi_mac_addr srf_macs[]; SRF MAC address filter list - * A_UINT8 rx_match_filter[]; RX match filter byte stream - * A_UINT8 tx_match_filter[]; TX match filter byte stream - * A_UINT32 cipher_suites[]; NAN cipher suite ID array - * A_UINT8 nd_pmk[]; NAN Data Path PMK, 32 bytes; - * present only when bit7 of - * service_req_flags is set - * A_UINT8 extra_nan_attrs[]; extra NAN attrs like Device Cap, - * Shared Key Desc, CSIA cap etc. - * are sent in stream of bytes - * (ieee80211 protocol order). - * The host must manually byteswap - * these bytes within each 4-byte word - * if the host's endianness doesn’t - * match the target’s, to ensure the - * expected byte order is maintained. - */ -} wmi_nan_disc_service_req_cmd_fixed_param; - -typedef enum { - WMI_NAN_STATUS_NO_NAN_AVAIL_DFS_CHANNEL_DETECTED = 0x1, - WMI_NAN_STATUS_NO_DFS_BEACONS_RECEIVED = 0x2, - WMI_NAN_STATUS_STA_DISCONNECTED_FROM_DFS = 0x3, -} WMI_NAN_DFS_CHANNEL_AVAILABILITY_STATUS_TYPE; - #define WMI_NAN_GET_RANGING_INITIATOR_ROLE(flag) WMI_GET_BITS(flag, 0, 1) #define WMI_NAN_SET_RANGING_INITIATOR_ROLE(flag, val) WMI_SET_BITS(flag, 0, 1, val) #define WMI_NAN_GET_RANGING_RESPONDER_ROLE(flag) WMI_GET_BITS(flag, 1, 1) @@ -33047,7 +29221,7 @@ typedef struct { A_UINT32 tlv_header; /** Unique id identifying the VDEV */ A_UINT32 vdev_id; - /** NAN Cluster ID, 4 bytes are sent in network byte order (big-endian) */ + /** NAN Cluster ID */ A_UINT32 nan_cluster_id; } wmi_nan_started_cluster_event_fixed_param_PROTOTYPE; @@ -33061,7 +29235,7 @@ typedef struct { A_UINT32 tlv_header; /** Unique id identifying the VDEV */ A_UINT32 vdev_id; - /** NAN Cluster ID, 4 bytes are sent in network byte order (big-endian) */ + /** NAN Cluster ID */ A_UINT32 nan_cluster_id; } wmi_nan_joined_cluster_event_fixed_param_PROTOTYPE; @@ -33078,354 +29252,6 @@ typedef struct { */ } wmi_nan_dmesg_event_fixed_param; -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_enable_rsp_event_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ - A_UINT32 status; /* Status code; 0 indicates NAN enable is success */ - A_UINT32 mac_id; /* MAC ID associated with NAN primary discovery channel */ -} wmi_nan_enable_rsp_event_fixed_param; - -/** - * WMI event response to WMI_NAN_DISC_SERVICE_REQ_CMDID. - * Sent by FW for each Publish / Subscribe / Follow-up function registration. - */ -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_service_rsp_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the NMI VDEV */ - A_UINT32 vdev_id; - /** - * Opaque cookie assigned by the driver; monotonically increasing per rdev. - * Host must store this and include it in every subsequent match event - * correlation. Equivalent of NL80211_ATTR_COOKIE in the CFG response. - * Split into two A_UINT32 words for endian portability. - * Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64. - */ - A_UINT32 cookie_low32; /* lower 32 bits of 64-bit cookie value */ - A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */ - /** - * FW/device-assigned service instance ID (1-255). - * Used in SDF frames and match events. - * Equivalent of NL80211_NAN_FUNC_INSTANCE_ID in the CFG response. - */ - A_UINT32 instance_id; - /** - * NAN service request type of the registered service request; - * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE: - * 1 = WMI_NAN_DISC_SERVICE_REQ_PUBLISH - * 2 = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE - * 3 = WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP - */ - A_UINT32 service_req_type; - /** Status code returned by FW: 0 = success, non-zero = failure */ - A_UINT32 status; -} wmi_nan_disc_service_rsp_event_fixed_param; - -/** - * WMI command to cancel an active NAN discovery service request. - * WMI equivalent of NL80211_CMD_DEL_NAN_FUNCTION / cfg80211 offload interface. - */ -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_cancel_service_req_cmd_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the NMI VDEV */ - A_UINT32 vdev_id; - /** - * NAN service request type being cancelled; - * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE: - * 1 = WMI_NAN_DISC_SERVICE_REQ_PUBLISH - * 2 = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE - */ - A_UINT32 service_req_type; - /** - * Instance ID of the service request to cancel (offload path); range 1-255. - * FW resolves instance_id to the internal service request object. - * Equivalent of NL80211_NAN_FUNC_INSTANCE_ID in - * NL80211_CMD_DEL_NAN_FUNCTION - */ - A_UINT32 instance_id; - /** - * Opaque cookie of the service request to cancel (standard path). - * Used when instance_id is not available; - * FW resolves cookie to service request. - * Equivalent of NL80211_ATTR_COOKIE in NL80211_CMD_DEL_NAN_FUNCTION. - * Set to 0 when instance_id is used instead. - * Split into two A_UINT32 words for endian portability. - * Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64. - */ - A_UINT32 cookie_low32; /* lower 32 bits of 64-bit cookie value */ - A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */ -} wmi_nan_disc_cancel_service_req_cmd_fixed_param; - -/** - * WMI event indicating a NAN discovery service request has been terminated. - * WMI equivalent of NL80211_CMD_DEL_NAN_FUNCTION (EVENT: terminated). - * Sent by FW when a Publish or Subscribe service request is cancelled by the - * host, expires due to TTL, or is terminated by FW due to an error. - */ -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_service_req_terminated_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the NMI VDEV */ - A_UINT32 vdev_id; - /** - * Opaque cookie of the terminated service request; assigned by FW in - * WMI_NAN_DISC_SERVICE_RSP_EVENTID. - * Equivalent of NL80211_ATTR_COOKIE in the terminated event. - * Split into two A_UINT32 words for endian portability. - * Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64. - */ - A_UINT32 cookie_low32; /* lower 32 bits of 64-bit cookie value */ - A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */ - /** - * Instance ID of the terminated service request (1-255). - * Equivalent of NL80211_NAN_FUNC_INSTANCE_ID in the terminated event - */ - A_UINT32 instance_id; - /** - * NAN service request type that was terminated; - * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE: - * 1 = WMI_NAN_DISC_SERVICE_REQ_PUBLISH - * 2 = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE - */ - A_UINT32 service_req_type; - /** - * Termination reason; refer to WMI_NAN_DISC_SERVICE_REQ_TERM_REASON enum: - * WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_USER_REQUEST (0) — - * cancelled by host - * WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_TTL_EXPIRED (1) — - * TTL elapsed - * WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_ERROR (2) — - * FW internal error - */ - A_UINT32 reason; -} wmi_nan_disc_service_req_terminated_event_fixed_param; - -/** -* WMI NAN discovery match event (NL80211_CMD_NAN_MATCH equivalent). - * Covers two match scenarios, discriminated by the type field: - * type = WMI_NAN_DISC_SERVICE_REQ_PUBLISH — - * subscriber found a matching publisher - * type = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE — - * publisher received a subscribe frame - */ -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_match_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the NMI VDEV */ - A_UINT32 vdev_id; - /** - * Cookie assigned by the driver in the - * WMI_NAN_DISC_SERVICE_RSP_EVENTID response; - * host uses this to correlate the match to the originating function. - * Split into two A_UINT32 words for endian portability. - * Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64. - */ - A_UINT32 cookie_low32; /* lower 32 bits of 64-bit cookie value */ - A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */ - /** Local function instance ID that triggered the match */ - A_UINT32 inst_id; - /** Peer's function instance ID */ - A_UINT32 peer_inst_id; - /** - * NAN service request type discriminating the match scenario; - * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE: - * 1 = WMI_NAN_DISC_SERVICE_REQ_PUBLISH (subscriber matched a publisher) - * 2 = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE (publisher received a subscribe) - */ - A_UINT32 type; - /** - * SDEA control field from peer; use WMI_NAN_DISC_SDEA_CTRL_GET macros; - * bit2=Data Path Required, bit6=Security Required - */ - A_UINT32 sdea_ctrl; - /** Peer's pairing bootstrap methods bitmap */ - A_UINT32 bootstrap_methods; - /** 1 = peer requires NDP (derived from SDEA bit 2); 0 = no NDP required */ - A_UINT32 data_path; - /** - * 1 = GTK protection required (derived from SDEA bit 10); - * 0 = not required - */ - A_UINT32 gtk_required; - /** 1 = peer supports pairing setup; 0 = not supported */ - A_UINT32 pairing_setup; - /** 1 = peer supports pairing cache; 0 = not supported */ - A_UINT32 pairing_cache; - /** 1 = peer supports pairing verify; 0 = not supported */ - A_UINT32 pairing_verify; - /** - * Received signal strength indicator (RSSI) in dBm; - * valid only when rssi_valid == 1 - */ - A_INT32 rssi; - /** 1 = rssi field is valid; 0 = rssi not populated */ - A_UINT32 rssi_valid; - /** Actual number of bytes in TLV peer_addr[] (always 6) */ - A_UINT32 peer_addr_len; - /** Actual number of bytes in TLV service_id[] (always 6) */ - A_UINT32 service_id_len; - /** Actual number of bytes in TLV serv_spec_info[] */ - A_UINT32 serv_spec_info_len; - /** Actual number of bytes in TLV scid[] */ - A_UINT32 scid_len; - /** - * Actual number of bytes in TLV extra_info[]; - * relevant when peer includes Extended SSI attribute - */ - A_UINT32 extra_info_len; - /** - * Actual number of bytes in TLV ies[]; - * raw IE blob parsed by supplicant: NPBA→bootstrap handler, - * Shared Key Descriptor→NIK exchange - */ - A_UINT32 ies_len; - /** - * TLV (tag length value) parameters follow this structure: - * wmi_mac_addr peer_addr[]; peer NMI address, 6 bytes (padded to 8) - * A_UINT8 service_id[]; local service ID, 6 bytes - * A_UINT8 serv_spec_info[]; service specific info from peer - * A_UINT32 cipher_suites[]; peer's NAN cipher suite ID array - * A_UINT8 scid[]; secure context ID; present when security_required == 1 - * A_UINT8 extra_info[]; extended SSI; present when extra_info_len > 0 - * A_UINT8 ies[]; raw IEs blob; present when ies_len > 0 - */ -} wmi_nan_disc_match_event_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_next_dw_info_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ - A_UINT32 dw_chan_freq; /* DW channel freq in MHz */ -} wmi_nan_next_dw_info_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disable_cnf_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ - A_UINT32 status; /* Status code; 0 indicates NAN enable is success */ -} wmi_nan_disable_cnf_event_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disable_ind_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ -} wmi_nan_disable_ind_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_local_schedule_cnf_event_fixed_param */ - - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations (NMI VDEV) */ - /** Status code; 0 indicates NAN local schedule got applied successfully */ - A_UINT32 status; -} wmi_nan_local_schedule_cnf_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cnf_event_fixed_param */ - - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations (NMI VDEV) */ - /** Status code; 0 indicates NAN peer schedule got applied successfully */ - A_UINT32 status; -} wmi_nan_peer_schedule_cnf_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_peer_params_cnf_event_fixed_param */ - - /** Virtual device ID used for NDP operations(either NMI or NDI VDEV) */ - A_UINT32 vdev_id; - /** peer NMI MAC address */ - wmi_mac_addr peer_nmi_addr; - /** peer NDI MAC address */ - wmi_mac_addr peer_ndi_macaddr; - /** status: - * 0 indicates NDP setup/schedule_negotiation peer params - * were applied successfully. - */ - A_UINT32 status; -} wmi_nan_peer_params_cnf_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_nan_dfs_channel_availability_ind_event_fixed_param */ - A_UINT32 vdev_id; - /** status: - * Status code; see WMI_NAN_DFS_CHANNEL_AVAILABILITY_STATUS_TYPE - */ - A_UINT32 status; -} wmi_nan_dfs_channel_availability_ind_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_channel_info_event_fixed_param */ - - A_UINT32 vdev_id; /* Virtual device ID used for NDP operations (NDI VDEV) */ - /** peer NDI MAC address */ - wmi_mac_addr peer_ndi_macaddr; - /** Number of channels on this peer */ - A_UINT32 num_ndp_channels; - /** - * TLV (tag length value) parameters follow the ndp_confirm - * structure. The TLV's are: - * wmi_channel ndp_channel_list[]; - * A_UINT32 nss_list[]; // Nss indexing should match with channel indexing, - * // since Nss is associated with the channel. - * wmi_ndp_channel_info channel_info[]; // Indexing should match with - * // channel indexing. - */ -} wmi_ndp_channel_info_event_fixed_param; - -typedef enum { - WMI_NDP_BAND_CAP_2GHZ = 0x01, - WMI_NDP_BAND_CAP_5GHZ = 0x02, - WMI_NDP_BAND_CAP_6GHZ = 0x04, -} WMI_NDP_BAND_CAP; - -/* Macros for parsing NAN device_caps fields */ -#define WMI_DEVICE_CAPS_GET_VHT_PHY_MODE(word32) \ - WMI_GET_BITS(word32, 0, 1) -#define WMI_DEVICE_CAPS_SET_VHT_PHY_MODE(word32, val) \ - WMI_SET_BITS(word32, 0, 1, val) -#define WMI_DEVICE_CAPS_GET_HE_PHY_MODE(word32) \ - WMI_GET_BITS(word32, 1, 1) -#define WMI_DEVICE_CAPS_SET_HE_PHY_MODE(word32, val) \ - WMI_SET_BITS(word32, 1, 1, val) -#define WMI_DEVICE_CAPS_GET_HE_VHT_80_80(word32) \ - WMI_GET_BITS(word32, 2, 1) -#define WMI_DEVICE_CAPS_SET_HE_VHT_80_80(word32, val) \ - WMI_SET_BITS(word32, 2, 1, val) -#define WMI_DEVICE_CAPS_GET_HE_VHT_160(word32) \ - WMI_GET_BITS(word32, 3, 1) -#define WMI_DEVICE_CAPS_SET_HE_VHT_160(word32, val) \ - WMI_SET_BITS(word32, 3, 1, val) -#define WMI_DEVICE_CAPS_GET_NUM_TX_ANT(word32) \ - WMI_GET_BITS(word32, 4, 4) -#define WMI_DEVICE_CAPS_SET_NUM_TX_ANT(word32, val) \ - WMI_SET_BITS(word32, 4, 4, val) -#define WMI_DEVICE_CAPS_GET_NUM_RX_ANT(word32) \ - WMI_GET_BITS(word32, 8, 4) -#define WMI_DEVICE_CAPS_SET_NUM_RX_ANT(word32, val) \ - WMI_SET_BITS(word32, 8, 4, val) -#define WMI_DEVICE_CAPS_GET_S3_SUPPORT(word32) \ - WMI_GET_BITS(word32, 12, 1) -#define WMI_DEVICE_CAPS_SET_S3_SUPPORT(word32, val) \ - WMI_SET_BITS(word32, 12, 1, val) -#define WMI_DEVICE_CAPS_GET_MAX_NDI_INTERFACES(word32) \ - WMI_GET_BITS(word32, 13, 3) -#define WMI_DEVICE_CAPS_SET_MAX_NDI_INTERFACES(word32, val) \ - WMI_SET_BITS(word32, 13, 3, val) -#define WMI_DEVICE_CAPS_GET_NDP_SUPPORTED_BAND(word32) \ - WMI_GET_BITS(word32, 16, 8) -#define WMI_DEVICE_CAPS_SET_NDP_SUPPORTED_BAND(word32, val) \ - WMI_SET_BITS(word32, 16, 8, val) -#define WMI_DEVICE_CAPS_GET_MAX_CHAN_SWITCH_TIME(word32) \ - WMI_GET_BITS(word32, 0, 16) -#define WMI_DEVICE_CAPS_SET_MAX_CHAN_SWITCH_TIME(word32, val) \ - WMI_SET_BITS(word32, 0, 16, val) -#define WMI_DEVICE_CAPS_GET_MAX_FAW_CHAN_PER_PEER(word32) \ - WMI_GET_BITS(word32, 16, 4) -#define WMI_DEVICE_CAPS_SET_MAX_FAW_CHAN_PER_PEER(word32, val) \ - WMI_SET_BITS(word32, 16, 4, val) - typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUCT_wmi_nan_capabilities */ A_UINT32 tlv_header; @@ -33433,35 +29259,6 @@ typedef struct { A_UINT32 max_ndp_sessions; /** Maximum number of nan pairing sessions supported by the Firmware */ A_UINT32 max_pairing_sessions; - union { - /* First 32-bit word of device capabilities */ - A_UINT32 device_caps_word0; - struct { - A_UINT32 vht_phy_mode: 1, /* Support for VHT PHY mode */ - he_phy_mode: 1, /* Support for HE PHY mode */ - he_vht_80_80: 1, /* Support for 80+80 MHz HE/VHT */ - he_vht_160: 1, /* Support for 160 MHz HE/VHT */ - num_tx_ant: 4, /* Number of TX antennas */ - num_rx_ant: 4, /* Number of RX antennas */ - s3_support: 1, /* Support for S3 power save */ - max_ndi_interfaces:3, /* Max number of NDI interfaces */ - ndp_supported_band:8, /* Supported bands for NDP - * (see WMI_NDP_BAND_CAP) */ - reserved:8; /* Reserved bits */ - }; - }; - union { - /* Second 32-bit word of device capabilities */ - A_UINT32 device_caps_word1; - struct { - A_UINT32 - /* Max channel switch time, in microseconds */ - max_chan_switch_time:16, - /* Max FAW channels to be allowed for a NDP peer */ - max_faw_chan_per_peer: 4, - reserved2: 12; /* Reserved bits */ - }; - }; } wmi_nan_capabilities; /** NAN DATA CMD's */ @@ -33682,21 +29479,6 @@ typedef struct { #define wmi_ndp_cmd_param wmi_ndp_cmd_param_PROTOTYPE -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_set_latency_tput_fixed_param */ - A_UINT32 tlv_header; - /** NDP instance id */ - A_UINT32 ndp_instance_id; - /** NDI VDEV ID */ - A_UINT32 vdev_id; - /** latency reqirement */ - A_UINT32 latency_ms; - /** throughput requirement */ - A_UINT32 tput_mbps; -} wmi_ndp_set_latency_tput_fixed_param_PROTOTYPE; - -#define wmi_ndp_set_latency_tput_fixed_param wmi_ndp_set_latency_tput_fixed_param_PROTOTYPE - /** * NDP End request */ @@ -34137,9 +29919,6 @@ enum wmi_sar_feature_state_flags { WMI_SAR_FEATURE_ON_USER_DEFINED, WMI_SAR_FEATURE_ON_SAR_V2_0, WMI_SAR_FEATURE_ON_SAR_V3, - WMI_SAR_FEATURE_ON_SAR_V3_0 = WMI_SAR_FEATURE_ON_SAR_V3, - WMI_SAR_FEATURE_ON_SAR_V4_0, - WMI_SAR_FEATURE_ON_SAR_V5_0, }; typedef struct { @@ -34291,12 +30070,6 @@ typedef struct { A_UINT8 replay_counter[GTK_REPLAY_COUNTER_BYTES]; } wmi_key_material; -#ifndef WMI_MAX_PMK_LEN -#define WMI_MAX_SMD_KDK_LEN 64 -#else -#define WMI_MAX_SMD_KDK_LEN WMI_MAX_PMK_LEN -#endif - typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_key_material_ext */ A_UINT32 tlv_header; @@ -34310,10 +30083,6 @@ typedef struct { A_UINT32 kck_len; /* length of kek in key_buffer */ A_UINT32 kek_len; - /* length of smd kdk */ - A_UINT32 smd_kdk_len; - /* smd kdk buffer */ - A_UINT8 smd_kdk_buffer[WMI_MAX_SMD_KDK_LEN]; } wmi_key_material_ext; typedef struct { @@ -34330,8 +30099,6 @@ typedef struct { * bit 7 0x1 to show bits 8-15 are valid * bits 8-15 full WMI_ROAM_TRIGGER_REASON_ID/WMI_ROAM_TRIGGER_EXT_REASON_ID * since 4 bits are not enough. - * bit 16 SMD BSS transition if it's set, see GET / SET - * ROAM_SMD_BSS_TRANSITION macros */ A_UINT32 roam_reason; /** associated AP's RSSI calculated by FW when reason code is WMI_ROAM_REASON_LOW_RSSI. not valid if roam_reason is BMISS */ @@ -34355,27 +30122,6 @@ typedef struct { A_UINT32 mac_tsf_id; /** ignore mac_tsf_id unless mac_tsf_id_valid is set */ A_UINT32 mac_tsf_id_valid; - /** - * IEEE value for auth algorithm - * Authentication algorithm number = 3: - * Simultaneous Authentication of Equals (SAE) - * Authentication algorithm number = 8: - * IEEE 802.1X authentication - * Authentication algorithm number = 9: - * EPPKE authentication - */ - A_UINT32 auth_algo; - /** smd_identifier: - * The SMD identifier of the roamed AP must not be zero in cases of - * an SMD BSS transition or a reassociation with SMD capability. - */ - wmi_mac_addr smd_identifier; - /** - * Length of KDE data which is received on EAPOL M3 frame or - * reassoc reponse frame. - * Ex: SAE PW ID KDE data - */ - A_UINT32 kde_length; /** * TLV (tag length value) parameters follows roam_synch_event * The TLV's are: @@ -34394,7 +30140,6 @@ typedef struct { * wmi_key_material_ext key_ext[]; * wmi_roam_pmk_cache_synch_tlv_param roam_pmk_cache_synch_info[]; * wmi_pdev_band_to_mac mac_freq_mapping[]; - * A_UINT8 kde_data[]; */ } wmi_roam_synch_event_fixed_param; @@ -35561,11 +31306,6 @@ typedef struct { A_UINT32 pdev_id; } wmi_pdev_resume_event_fixed_param; -/** WMI_PDEV_SUSPEND_EVENTID: generated in response to WMI_PDEV_SUSPEND_CMDID */ -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_suspend_event_fixed_param */ - A_UINT32 pdev_id; -} wmi_pdev_suspend_event_fixed_param; /** value representing all modules */ @@ -36322,7 +32062,6 @@ typedef struct { /* picks protocol type from WMI_USD_SERVICE_PROTOCOL_TYPE */ A_UINT32 protocol_type; wmi_mac_addr device_mac_addr; - wmi_mac_addr multicast_addr; } wmi_usd_service_cmd_fixed_param; typedef struct { @@ -36364,44 +32103,6 @@ typedef enum { WMI_USD_SERVICE_PROTOCOL_TYPE_CSA_MATTER = 3, } WMI_USD_SERVICE_PROTOCOL_TYPE; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_connect_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; -} wmi_vdev_unified_connect_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; -} wmi_vdev_unified_disconnect_cmd_fixed_param; - -typedef enum { - WMI_VDEV_UNIFIED_CONNECT_EVENT_SUCCESS, - WMI_VDEV_UNIFIED_CONNECT_EVENT_FAILURE, -} WMI_VDEV_UNIFIED_CONNECT_EVENT_STATUS; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_connect_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - A_UINT32 status; /* WMI_VDEV_UNIFIED_CONNECT_EVENT_STATUS */ -} wmi_vdev_unified_connect_event_fixed_param; - -typedef enum { - WMI_VDEV_UNIFIED_DISCONNECT_EVENT_SUCCESS, - WMI_VDEV_UNIFIED_DISCONNECT_EVENT_FAILURE, -} WMI_VDEV_UNIFIED_DISCONNECT_EVENT_STATUS; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - A_UINT32 status; /* WMI_VDEV_UNIFIED_DISCONNECT_EVENT_STATUS */ -} wmi_vdev_unified_disconnect_event_fixed_param; - - #define EXPIRY_TIME_IN_TSF_TIMESTAMP_OFFSET 0 #define EXPIRY_TIME_IN_TSF_TIMESTAMP_MASK 1 @@ -37535,23 +33236,6 @@ typedef struct { A_UINT32 tid_mask; /* bits 0 to 15 = QoS TIDs, bit 16 = non-qos TID */ } wmi_peer_reorder_queue_remove_cmd_fixed_param; -/** - * This command is sent from WLAN host driver to firmware for - * customizing MCS range & retry count for specific TID of specific peer - */ -typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - wmi_mac_addr peer_macaddr; /* Peer MAC address */ - A_UINT32 tid; - /* on_off: - * Rate customization enable/disable. 1 for enable and 0 for disable. - */ - A_UINT32 on_off; - A_UINT32 bw; /* Unit MHz */ - A_UINT32 retry_count; -} wmi_peer_tid_rate_custom_cmd_fixed_param; - /* DEPRECATED - use wmi_pdev_set_mac_config_response_event_fixed_param instead */ typedef struct { @@ -38203,81 +33887,6 @@ typedef struct wmi_bpf_get_vdev_work_memory_resp_evt_s { */ } wmi_bpf_get_vdev_work_memory_resp_evt_fixed_param; - -/* APF offloads supported bitmap: - * - * BIT 0: ARP OFFLOAD - * BIT 1: NS OFFLOAD - * BIT 2: IGMP OFFLOAD - * BIT 3: ICMP OFFLOAD - * BIT 4-31: reserved -*/ -#define WMI_BPF_ARP_OFFLOAD_SUPPORT_GET(param) \ - WMI_GET_BITS(param, 0, 1) -#define WMI_BPF_ARP_OFFLOAD_SUPPORT_SET(param, value) \ - WMI_SET_BITS(param, 0, 1, value) - -#define WMI_BPF_NS_OFFLOAD_SUPPORT_GET(param) \ - WMI_GET_BITS(param, 1, 1) -#define WMI_BPF_NS_OFFLOAD_SUPPORT_SET(param, value) \ - WMI_SET_BITS(param, 1, 1, value) - -#define WMI_BPF_IGMP_OFFLOAD_SUPPORT_GET(param) \ - WMI_GET_BITS(param, 2, 1) -#define WMI_BPF_IGMP_OFFLOAD_SUPPORT_SET(param, value) \ - WMI_SET_BITS(param, 2, 1, value) - -#define WMI_BPF_ICMP_OFFLOAD_SUPPORT_GET(param) \ - WMI_GET_BITS(param, 3, 1) -#define WMI_BPF_ICMP_OFFLOAD_SUPPORT_SET(param, value) \ - WMI_SET_BITS(param, 3, 1, value) - -typedef struct wmi_bpf_set_supported_offload_bitmap_cmd_s { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* ofld_bitmap: - * Host sends bitmap for APF supported offloads. - * Refer to the above WMI_BPF_ macros for the interpretation of the bits - * within the bitmap. - */ - A_UINT32 ofld_bitmap; -} wmi_bpf_set_supported_offload_bitmap_cmd_fixed_param; - -/* APF modes: */ -typedef enum { - /* Default value: 0 */ - wmi_apf_mode_default = 0, - - /* Mode 1: value 1: APF to operate only during system suspend. */ - wmi_apf_mode_system_suspend = 1, - - /* Mode 2: value 2: - * Downgrade the APF capability of the firmware to a lower version - * (from V6 to V4). - */ - wmi_apf_mode_capability_v4 = 2, - - /* Mode combination: value 3: - * Downgrade to APFv4 and enable only in system suspend. - */ - wmi_apf_mode_system_suspend_and_capability_v4 = 3, - - /* Mode 3: value 4: Turn off APF completely. */ - wmi_apf_mode_off = 4, -} wmi_apf_modes; - -typedef struct wmi_bpf_set_apf_mode_cmd_s { - A_UINT32 tlv_header; /* tag = WMITLV_TAG_STRUC_wmi_bpf_set_apf_mode_cmd_fixed_param */ - A_UINT32 vdev_id; - /* apf_mode: - * Host indicates the APF mode (or combination of modes). - * Refer to the wmi_apf_modes enum for the interpretation of the - * apf_mode value. - */ - A_UINT32 apf_mode; /* holds a wmi_apf_modes value */ -} wmi_bpf_set_apf_mode_cmd_fixed_param; - - #define AES_BLOCK_LEN 16 /* in bytes */ #define FIPS_KEY_LENGTH_128 16 /* in bytes */ #define FIPS_KEY_LENGTH_256 32 /* in bytes */ @@ -38386,29 +33995,11 @@ typedef struct { A_UINT32 rx_antenna; /* rx antenna */ A_UINT32 tx_default_antenna; /* tx default antenna */ /* - * Following this structure are the TLVs: - * - wmi_pdev_smart_ant_gpio_handle - * - * - A_UINT32 pdev_smart_ant_param[] - * bit 0 : enable separate antenna for RTS (1:enable, 0:disable) - * Refer to WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_GET/SET - * bit 1-31: reserved + * Following this structure is the TLV: + * wmi_pdev_smart_ant_gpio_handle */ } wmi_pdev_smart_ant_enable_cmd_fixed_param; -/* - * Bit field definitions for pdev_smart_ant_param A_UINT32 - * within WMI_PDEV_SMART_ANT_ENABLE_CMDID - */ -#define WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_BIT_POS 0 -#define WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_NUM_BITS 1 - -#define WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_GET(enable_field) \ - WMI_GET_BITS(enable_field, WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_BIT_POS, WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_NUM_BITS) - -#define WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_SET(enable_field, value) \ - WMI_SET_BITS(enable_field, WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_BIT_POS, WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_NUM_BITS, value) - /** GPIO pins/function values to control antennas */ typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_smart_ant_gpio_handle */ @@ -38477,35 +34068,15 @@ typedef struct { #define WMI_PER_MIN_TX_PKTS_SET(per_threshold, value) \ WMI_SET_BITS(per_threshold, WMI_PER_MIN_TX_PKTS_BIT_POS, WMI_PER_MIN_TX_PKTS_NUM_BITS, value) -#define WMI_SA_TRAIN_LATENCY_TRAFFIC_BIT_POS 25 -#define WMI_SA_TRAIN_LATENCY_TRAFFIC_NUM_BITS 1 - -#define WMI_GET_SA_TRAIN_LATENCY_TRAFFIC(per_threshold) \ - WMI_GET_BITS(per_threshold, WMI_SA_TRAIN_LATENCY_TRAFFIC_BIT_POS, WMI_SA_TRAIN_LATENCY_TRAFFIC_NUM_BITS) - -#define WMI_SET_SA_TRAIN_LATENCY_TRAFFIC(per_threshold, value) \ - WMI_SET_BITS(per_threshold, WMI_SA_TRAIN_LATENCY_TRAFFIC_BIT_POS, WMI_SA_TRAIN_LATENCY_TRAFFIC_NUM_BITS, value) - -#define WMI_SA_TRAIN_USING_QOS_NULL_BIT_POS 26 -#define WMI_SA_TRAIN_USING_QOS_NULL_NUM_BITS 1 - -#define WMI_GET_SA_TRAIN_USING_QOS_NULL(per_threshold) \ - WMI_GET_BITS(per_threshold, WMI_SA_TRAIN_USING_QOS_NULL_BIT_POS, WMI_SA_TRAIN_USING_QOS_NULL_NUM_BITS) - -#define WMI_SET_SA_TRAIN_USING_QOS_NULL(per_threshold, value) \ - WMI_SET_BITS(per_threshold, WMI_SA_TRAIN_USING_QOS_NULL_BIT_POS, WMI_SA_TRAIN_USING_QOS_NULL_NUM_BITS, value) - - #define WMI_RATE_SERIES_320_BIT_POS 0 #define WMI_RATE_SERIES_320_NUM_BITS 16 #define WMI_GET_RATE_SERIES_320(train_rate_series_ext) \ WMI_GET_BITS(train_rate_series_ext, WMI_RATE_SERIES_320_BIT_POS, WMI_RATE_SERIES_320_NUM_BITS) -#define WMI_SET_RATE_SERIES_320(train_rate_series_ext, value) \ +#define WMI_SET_RATE_SERIES_320(train_rate_series_ext) \ WMI_SET_BITS(train_rate_series_ext, WMI_RATE_SERIES_320_BIT_POS, WMI_RATE_SERIES_320_NUM_BITS, value) - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_param */ /* rate array */ @@ -38548,9 +34119,7 @@ typedef struct { * 0 | PER Threshold is valid * 1:8 | Per Threshold * 9:24 | min_tx_pkts Minimum number of pkts need to be checked - * 25 | enable_training_for_latency_traffic - * 26 | train_using_qos_null - * 27:31 | Reserved + * 25:31 | Reserved */ A_UINT32 per_threshold; /* @@ -38837,41 +34406,6 @@ typedef enum { * A_INT8 ICNIRP 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-8) (Ch117~Ch149) * A_INT8 ICNIRP 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-8) (Ch117~Ch149) * A_INT8 ICNIRP 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-8) (Ch117~Ch149) - * if version == 2 or chip is col, will have NONTAS POWER LIMIT - * ====================NONTAS POWER LIMIT VALUE====================== - * A_INT8 NONTAS 2 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) - * A_INT8 NONTAS 2 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) - * A_INT8 NONTAS 2 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) - * A_INT8 NONTAS 5 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-1, Ch32 ~ Ch48) - * A_INT8 NONTAS 5 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-1, Ch32 ~ Ch48) - * A_INT8 NONTAS 5 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-1, Ch32 ~ Ch48) - * A_INT8 NONTAS 5 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-2, Ch50 ~ Ch144) - * A_INT8 NONTAS 5 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-2, Ch50 ~ Ch144) - * A_INT8 NONTAS 5 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-2, Ch50 ~ Ch144) - * A_INT8 NONTAS 5 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-3, Ch149 ~ Ch161) - * A_INT8 NONTAS 5 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-3, Ch149 ~ Ch161) - * A_INT8 NONTAS 5 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-3, Ch149 ~ Ch161) - * A_INT8 NONTAS 5 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-4, Ch163 ~ Ch177) - * A_INT8 NONTAS 5 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-4, Ch163 ~ Ch177) - * A_INT8 NONTAS 5 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-4, Ch163 ~ Ch177) - * A_INT8 NONTAS 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-5) (Ch1, Ch2 ~ Ch41) - * A_INT8 NONTAS 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-5) (Ch1, Ch2 ~ Ch41) - * A_INT8 NONTAS 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-5) (Ch1, Ch2 ~ Ch41) - * A_INT8 NONTAS 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-5) (Ch45 ~ Ch93) - * A_INT8 NONTAS 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-5) (Ch45 ~ Ch93) - * A_INT8 NONTAS 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-5) (Ch45 ~ Ch93) - * A_INT8 NONTAS 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-6) (Ch97~ Ch113) - * A_INT8 NONTAS 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-6) (Ch97~ Ch113) - * A_INT8 NONTAS 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-6) (Ch97~ Ch113) - * A_INT8 NONTAS 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-7) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-7) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-7) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-7) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-7) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-7) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-8) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-8) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-8) (Ch117~Ch149) */ BIOS_PARAM_TYPE_BANDEDGE_CTL_POWER, @@ -39044,21 +34578,6 @@ typedef enum { * ============================================================== */ - BIOS_PARAM_TYPE_NON_SAR_COUNTRY_CONFIG, - /* - * BIOS_PARAM_TYPE_NON_SAR_COUNTRY_CONFIG structure contains 256 bytes as below - * - * A_UINT8 country_bitmap[NON_SAR_COUNTRY_BITMAP_COUNT];//NON_SAR_COUNTRY_BITMAP_COUNT = 256, 256BYTE. - * 0-255 stand for 256 country, each country has 8 bit for configuration. - * - * ==================each bit configuration=========================== - * BIT0: Skip TAS limit config - * BIT1: Skip SAR limit config - * BIT2: Use domain GEO table. 1: Use Country GEO table - * BIT3~5: index of domain/country used which group GEO offset table - * BIT6~7: reserved - * ==================================================================== - */ BIOS_PARAM_TYPE_MAX, } bios_param_type_e; @@ -39948,43 +35467,6 @@ typedef struct { A_UINT32 pdev_id; } wmi_pdev_get_chip_power_stats_cmd_fixed_param; - -typedef enum { - /* Enable the stats by default*/ - WMI_PDEV_POWER_DATAPATH_STATS_OP_DISABLE = 0, - WMI_PDEV_POWER_DATAPATH_STATS_OP_ENBLE = 1, - WMI_PDEV_POWER_DATAPATH_STATS_OP_RETRIEVE = 2, - WMI_PDEV_POWER_DATAPATH_STATS_OP_MAX, -} WMI_PDEV_POWER_DATAPATH_STATS_OPERATION; - -typedef enum { - WMI_PDEV_POWER_STATS_TYPE = 0x00000001, - WMI_PDEV_DATAPATH_STATS_TYPE = 0x00000002, - WMI_PDEV_POWER_DATAPATH_STATS_ALL = 0x00000003, - WMI_PDEV_SOC_POWER_STATS_TYPE = 0x00000004, - WMI_PDEV_SOC_POWER_DATAPATH_STATS_ALL = 0x00000005, - - - WMI_PDEV_STATS_TYPE_MAX, -} WMI_PDEV_POWER_DATAPATH_STATS_TYPE; - -/* WMI command to enable/disable or get the power/datapath stats */ -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_cmd_fixed_param */ - - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 core_index; - - /** Operation type - distinguishes between enable/disable/retrieve */ - A_UINT32 operation; /* wmi_pdev_power_datapath_stats_operation */ - - /** Stats type bitmap - specifies which stats to enable/disable/retrieve */ - A_UINT32 stats_type_bitmap; /* wmi_pdev_power_datapath_stats_type */ -} wmi_pdev_power_datapath_stats_cmd_fixed_param; - - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_bcn_recv_stats_cmd_fixed_param */ /** VDEV identifier */ @@ -40145,131 +35627,6 @@ typedef struct { */ } wmi_pdev_chip_power_stats_event_fixed_param; - -typedef enum { - WMI_PDEV_RATE_CCK_1M, - WMI_PDEV_RATE_CCK_2M, - WMI_PDEV_RATE_CCK_5M, /* CCK 5.5Mbps */ - WMI_PDEV_RATE_CCK_11M, - WMI_PDEV_RATE_OFDM_6M, - WMI_PDEV_RATE_OFDM_9M, - WMI_PDEV_RATE_OFDM_12M, - WMI_PDEV_RATE_OFDM_18M, - WMI_PDEV_RATE_OFDM_24M, - WMI_PDEV_RATE_OFDM_36M, - WMI_PDEV_RATE_OFDM_48M, - WMI_PDEV_RATE_OFDM_54M, - WMI_PDEV_RATE_MCS0, /* includes HT MCS 0 (1ss)/8 (2ss)/16 (3ss)/24 (4ss), VHT/HE MCS 0 */ - WMI_PDEV_RATE_MCS1, /* includes HT MCS 1 (1ss)/9 (2ss)/17 (3ss)/25 (4ss), VHT/HE MCS 1 */ - WMI_PDEV_RATE_MCS2, /* includes HT MCS 2 (1ss)/10 (2ss)/18 (3ss)/26 (4ss), VHT/HE MCS 2 */ - WMI_PDEV_RATE_MCS3, /* includes HT MCS 3 (1ss)/11 (2ss)/19 (3ss)/27 (4ss), VHT/HE MCS 3 */ - WMI_PDEV_RATE_MCS4, /* includes HT MCS 4 (1ss)/12 (2ss)/20 (3ss)/28 (4ss), VHT/HE MCS 4 */ - WMI_PDEV_RATE_MCS5, /* includes HT MCS 5 (1ss)/13 (2ss)/21 (3ss)/29 (4ss), VHT/HE MCS 5 */ - WMI_PDEV_RATE_MCS6, /* includes HT MCS 6 (1ss)/14 (2ss)/22 (3ss)/30 (4ss), VHT/HE MCS 6 */ - WMI_PDEV_RATE_MCS7, /* includes HT MCS 7 (1ss)/15 (2ss)/23 (3ss)/31 (4ss), VHT/HE MCS 7 */ - WMI_PDEV_RATE_MCS8, /* includes VHT/HE MCS 8 */ - WMI_PDEV_RATE_MCS9, /* includes VHT/HE MCS 9 */ - WMI_PDEV_RATE_MCS10, /* includes VHT/HE MCS 10 */ - WMI_PDEV_RATE_MCS11, /* includes VHT/HE MCS 11 */ - WMI_PDEV_RATE_MCS12, /* includes BE MCS 12 */ - WMI_PDEV_RATE_MCS13, /* includes BE MCS 13 */ - WMI_PDEV_RATE_RATE_IDX_MAX, -} WMI_PDEV_RATE_IDX; - -#define WMI_MAX_SLEEP_LEVELS 5 - -typedef struct { - A_UINT32 tlv_header;/* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_tx_rate_info */ - - /** Common element - core_index (PDEV ID) */ - A_UINT32 core_index; - - /* An index representing a specific transmit data rate */ - A_UINT32 rate_index; - - /* - * The operating band of the transmit rate. - * 0: 2.4 GHz, 1: 5 GHz, 2: 6 GHz - */ - A_UINT32 band; - - /* - * The bandwidth of the transmit rate. - * 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 MHz, 4: 320 MHz - */ - A_UINT32 bw; - - /* - * The number of spatial streams (NSS) used for this transmit rate. - * 0: NSS1, 1: NSS2, 2: NSS3, 3: NSS4, 4: NSS5 - */ - A_UINT32 nss; - - /* - * The number of times a transmit occurred with this specific - * combination of rate index, band, bandwidth, and NSS - */ - A_UINT32 count; - A_UINT32 tx_retry_count; /* accumulated over time */ -} wmi_pdev_tx_rate_info; - -/* Power stats in event payload*/ -typedef struct { - /** Power Statistics */ - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_power_stats_info */ - - /** Common element - core_index (PDEV ID) */ - A_UINT32 core_index; - - A_UINT32 radio_on_time; /* Time radio was on (ms) */ - A_UINT32 radio_off_time; /* Time radio was off (ms) */ - A_UINT32 wlan_pwr_on_time; /* WLAN power on time (ms) */ - /* tx_time: - * ms duration the radio is in a continuous transmit state - * encompassing all packet types (management, data, action frames) - */ - A_UINT32 tx_time; - /* rx_time: - * ms duration the radio is in a continuous receiving data state - * Including all Rx packets instead of only collecting for my BSS data - */ - A_UINT32 rx_time; - - /* Number of sleep levels being sent to the host */ - A_UINT32 sleep_levels_num; - A_UINT32 sleep_time_per_levels[WMI_MAX_SLEEP_LEVELS]; /* ms */ -} wmi_pdev_power_stats_info; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_event_fixed_param */ - - /** Status of the operation */ - A_UINT32 status; /* 0 = success, non-zero = error */ - - /** Stats type bitmap indicating which stats are included */ - A_UINT32 stats_type_bitmap; - - A_UINT32 wlan_soc_pwr_on_time; /* WLAN power on time (ms) */ - - /* wlan_soc_sleep_levels_num: - * Number of sleep levels supported. - * Could be less than WMI_MAX_SLEEP_LEVELS based on the chip. - */ - A_UINT32 wlan_soc_sleep_levels_num; - - /** soc sleep level. Same WMI_MAX_SLEEP_LEVELS is used for sizing */ - A_UINT32 wlan_soc_sleep_time_per_level[WMI_MAX_SLEEP_LEVELS]; /* ms */ - - /* - * Following this structure are the TLVs: - * wmi_pdev_power_stats_info[num_cores]; - * wmi_pdev_tx_rate_info[num_tx_rate_info] - * where num_cores and num_tx_rate_info are determined from the TLV array - * (i.e. array size / array element size) - */ -} wmi_pdev_power_datapath_stats_event_fixed_param; - - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_bcn_recv_stats_fixed_param */ A_UINT32 vdev_id; @@ -41050,7 +36407,7 @@ typedef enum { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_request_wlan_stats_cmd_fixed_param */ - A_UINT32 stats_id; /* wmi_wlan_stats_id */ + wmi_wlan_stats_id stats_id; } wmi_request_wlan_stats_cmd_fixed_param; typedef enum { @@ -41106,10 +36463,6 @@ typedef enum { WMI_REQUEST_CTRL_PATH_PDEV_BCN_TX_STAT = 20, WMI_REQUEST_CTRL_PATH_PDEV_CONN_STAT = 21, WMI_REQUEST_CTRL_PATH_ML_RECONFIG_STAT = 22, - WMI_REQUEST_CTRL_PATH_STA_DAR_STAT = 23, - WMI_REQUEST_ENHANCED_STAT = 24, - WMI_REQUEST_CTRL_PATH_EM_PCIE_STAT = 25, - WMI_REQUEST_CTRL_PATH_EM_DCVS_STAT = 26, } wmi_ctrl_path_stats_id; typedef enum { @@ -41129,16 +36482,6 @@ typedef enum { WMI_REQUEST_CTRL_PATH_STAT_PERIODIC_PUBLISH = 5, } wmi_ctrl_path_stats_action; -typedef enum { - /* - * The following stats actions are mutually exclusive. - * A single stats request message can only specify one action. - */ - WMI_REQUEST_CTRL_PATH_STAT_DEFAULT = 0, /* unspecified granularity */ - WMI_REQUEST_CTRL_PATH_STAT_AC_LEVEL = 1, - WMI_REQUEST_CTRL_PATH_STAT_TID_LEVEL = 2, -} wmi_ctrl_path_stats_granularity; - typedef enum { WMI_HALPHY_CTRL_PATH_SU_STATS = 0, WMI_HALPHY_CTRL_PATH_SUTXBF_STATS, @@ -41175,13 +36518,6 @@ typedef struct { */ A_UINT32 stat_periodicity; - /** stats_granularity: - * Configures AC vs. TID granularity stats reporting, - * e.g. for STA_DAR_STATs. - * Possible values are listed in the wmi_ctrl_path_stats_granularity enum. - */ - A_UINT32 stats_granularity; /* refer to wmi_ctrl_path_stats_granularity */ - /** The below TLV arrays optionally follow this fixed_param TLV structure: * 1. A_UINT32 pdev_ids[]; * If this array is present and non-zero length, stats should only @@ -41259,16 +36595,6 @@ typedef struct { A_UINT32 reset_after_request; } wmi_request_radio_chan_stats_cmd_fixed_param; -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_request_tdls_stats_cmd_fixed_param */ - A_UINT32 tlv_header; - /** VDEV identifier */ - A_UINT32 vdev_id; - /* flag to enable or disable this feature of getting TDLS stats */ - A_UINT32 enable; -} wmi_request_tdls_stats_cmd_fixed_param; - typedef struct { /** TLV tag and len; tag equals * WMITLV_TAG_STRUC_wmi_rmc_set_leader_cmd_fixed_param */ @@ -41506,9 +36832,6 @@ typedef enum wmi_hw_mode_config_type { #define WMI_SUPPORT_11BE_GET(flags) WMI_GET_BITS(flags, 6, 1) #define WMI_SUPPORT_11BE_SET(flags, value) WMI_SET_BITS(flags, 6, 1, value) -#define WMI_SUPPORT_11BN_GET(flags) WMI_GET_BITS(flags, 7, 1) -#define WMI_SUPPORT_11BN_SET(flags, value) WMI_SET_BITS(flags, 7, 1, value) - #define WMI_MAX_MUBFEE_GET(flags) WMI_GET_BITS(flags, 28, 4) #define WMI_MAX_MUBFEE_SET(flags, value) WMI_SET_BITS(flags, 28, 4, value) @@ -41688,9 +37011,8 @@ typedef struct { supports_11ac:1, supports_11ax:1, supports_11be:1, - supports_11bn:1, - unused: 20, + unused: 21, max_mubfee: 4; /* max MU beamformees supported per MAC */ }; @@ -41954,601 +37276,6 @@ typedef struct { }; } WMI_MAC_PHY_CAPABILITIES_EXT; -/* WMI Maximum Tx/Rx NSS information */ -#define WMI_MAC_PHY_CAPABILITIES_EXT2_MAX_TX_NSS_SET(param, value) \ - WMI_SET_BITS(param, 0, 4, value) -#define WMI_MAC_PHY_CAPABILITIES_EXT2_MAX_TX_NSS_GET(dword) \ - WMI_GET_BITS(dword, 0, 4) - -#define WMI_MAC_PHY_CAPABILITIES_EXT2_MAX_RX_NSS_SET(param, value) \ - WMI_SET_BITS(param, 4, 4, value) -#define WMI_MAC_PHY_CAPABILITIES_EXT2_MAX_RX_NSS_GET(dword) \ - WMI_GET_BITS(dword, 4, 4) - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES_EXT2 */ - - /* hw_mode_id: - * Identify a particular set of HW characteristics, as specified by - * the subsequent fields. - * WMI_MAC_PHY_CAPABILITIES element must be mapped to its parent - * WMI_HW_MODE_CAPABILITIES element using hw_mode_id. - * No particular ordering of WMI_MAC_PHY_CAPABILITIES elements - * should be assumed, though in practice the elements will likely - * be ordered by hw_mode_id. - */ - A_UINT32 hw_mode_id; - - /* - * pdev_id starts with 1. pdev_id 1 => phy_id 0, pdev_id 2 => phy_id 1 - * hw_link_id: Unique link id across SOCs, got as part of QMI handshake. - * For legacy chips which do not support MLO, these top bits will always - * be set to 0, so it won't impact the legacy chips which treat pdev_id - * as 32 bits. - */ - union { - struct { - A_UINT32 pdev_id:16, - hw_link_id:16; - } pdev_to_link_map; - A_UINT32 pdev_to_link_map_word32; - }; - /* phy id. Starts with 0 */ - A_UINT32 phy_id; - A_UINT32 wireless_modes_ext; /* REGDMN MODE EXT, see REGDMN_MODE_ enum */ - - /************************************************************************** - * following new params are for 802.11bn, but under development - **************************************************************************/ - /* UHR capability mac info field of 802.11bn */ - A_UINT32 uhr_cap_mac_info_2G[WMI_MAX_UHRCAP_MAC_SIZE]; - A_UINT32 uhr_cap_mac_info_5G[WMI_MAX_UHRCAP_MAC_SIZE]; - - /* UHR capability phy field of 802.11bn, WMI_UHR_CAP defines */ - A_UINT32 uhr_cap_phy_info_2G[WMI_MAX_UHRCAP_PHY_SIZE]; - A_UINT32 uhr_cap_phy_info_5G[WMI_MAX_UHRCAP_PHY_SIZE]; - - union { - struct { - A_UINT32 npca_enabled:1, /* bit 0 */ - npca_min_dur_threshold:4, /* bits 4:1 */ - npca_switch_delay:6, /* bits 10:5 */ - npca_switch_back_delay:6, /* bits 16:11 */ - npca_qsrc:2, /* bits 18:17 */ - npca_moplen:1, /* bit 19 */ - reserved: 12; - }; - A_UINT32 npca_capability; - }; - wmi_ppe_threshold uhr_ppet2G; - wmi_ppe_threshold uhr_ppet5G; - - /* nss_info: - * Bits 3:0 - Maximum suported Tx NSS - * Bits 7:4 - Maximum suported Rx NSS - * Bits 31:8 - Reserved - */ - union { - A_UINT32 nss_info; - struct { - A_UINT32 - max_tx_nss: 4, - max_rx_nss: 4, - reserved2: 24; - }; - }; - - /* - * UHR DBE Capability Parameters of 802.11bn - * (conditional on DBE Support bit) - */ - A_UINT32 uhr_cap_dbe_info_2G[WMI_MAX_UHRCAP_DBE_SIZE]; - A_UINT32 uhr_cap_dbe_info_5G[WMI_MAX_UHRCAP_DBE_SIZE]; -} WMI_MAC_PHY_CAPABILITIES_EXT2; - -#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_PDEV_ID_GET(pdev_to_link_map_word32) \ - WMI_GET_BITS(pdev_to_link_map_word32, 0, 16) -#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_PDEV_ID_SET(pdev_to_link_map_word32, val) \ - WMI_SET_BITS(pdev_to_link_map_word32, 0, 16, val) - -#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_HW_LINK_ID_GET(pdev_to_link_map_word32) \ - WMI_GET_BITS(pdev_to_link_map_word32, 16, 16) -#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_HW_LINK_ID_SET(pdev_to_link_map_word32, val) \ - WMI_SET_BITS(pdev_to_link_map_word32, 16, 16, val) - -/****** 11BN UHR PHY Capabilities Information field ******/ /* { */ - -/* Bit 0: Max Nss Rx for sounding NDP (≤ 80 MHz) */ -#define WMI_UHRCAP_PHY_MAX_NSS_RX_80_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 0, 1) -#define WMI_UHRCAP_PHY_MAX_NSS_RX_80_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 0, 1, value) - -/* Bit 1: Max Nss,total Rx for DL MU-MIMO (≤ 80 MHz) */ -#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_80_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 1, 1) -#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_80_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 1, 1, value) - -/* Bit 2: Max Nss Rx for sounding NDP (= 160 MHz) */ -#define WMI_UHRCAP_PHY_MAX_NSS_RX_160_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 2, 1) -#define WMI_UHRCAP_PHY_MAX_NSS_RX_160_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 2, 1, value) - -/* Bit 3: Max Nss,total Rx for DL MU-MIMO (= 160 MHz) */ -#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_160_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 3, 1) -#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_160_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 3, 1, value) - -/* Bit 4: Max Nss Rx for sounding NDP (= 320 MHz) */ -#define WMI_UHRCAP_PHY_MAX_NSS_RX_320_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 4, 1) -#define WMI_UHRCAP_PHY_MAX_NSS_RX_320_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 4, 1, value) - -/* Bit 5: Max Nss,total Rx for DL MU-MIMO (= 320 MHz) */ -#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_320_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 5, 1) -#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_320_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 5, 1, value) - -/* Bit 6: ELR Tx Support */ -#define WMI_UHRCAP_PHY_ELR_TX_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 6, 1) -#define WMI_UHRCAP_PHY_ELR_TX_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 6, 1, value) - -/* Bit 7: ELR Rx Support */ -#define WMI_UHRCAP_PHY_ELR_RX_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 7, 1) -#define WMI_UHRCAP_PHY_ELR_RX_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 7, 1, value) - -/* Bit 8: Partial BW DL MU-MIMO support */ -#define WMI_UHRCAP_PHY_PARTIAL_BW_DL_MU_MIMO_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 8, 1) -#define WMI_UHRCAP_PHY_PARTIAL_BW_DL_MU_MIMO_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 8, 1, value) - -/* Bit 9: Partial BW UL MU-MIMO support */ -#define WMI_UHRCAP_PHY_PARTIAL_BW_UL_MU_MIMO_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 9, 1) -#define WMI_UHRCAP_PHY_PARTIAL_BW_UL_MU_MIMO_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 9, 1, value) - -/* Bit 10: MCS 15 support */ -#define WMI_UHRCAP_PHY_MCS_15_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 10, 1) -#define WMI_UHRCAP_PHY_MCS_15_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 10, 1, value) - -/* Bit 11: 2XLDPC Tx Support */ -#define WMI_UHRCAP_PHY_2XLDPC_TX_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 11, 1) -#define WMI_UHRCAP_PHY_2XLDPC_TX_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 11, 1, value) - -/* Bit 12: 2XLDPC Rx Support */ -#define WMI_UHRCAP_PHY_2XLDPC_RX_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 12, 1) -#define WMI_UHRCAP_PHY_2XLDPC_RX_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 12, 1, value) - -/* Bits 13-14: UEQM Tx Support and Max NSS Tx */ -#define WMI_UHRCAP_PHY_UEQM_TX_MAX_NSS_TX_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 13, 2) -#define WMI_UHRCAP_PHY_UEQM_TX_MAX_NSS_TX_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 13, 2, value) - -/* Bits 15-16: UEQM Rx Support and Max NSS Rx */ -#define WMI_UHRCAP_PHY_UEQM_RX_MAX_NSS_RX_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 15, 2) -#define WMI_UHRCAP_PHY_UEQM_RX_MAX_NSS_RX_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 15, 2, value) - -/* Bit 17: Reserved */ - -/* Bit 18: Co-BF joint sounding support */ -#define WMI_UHRCAP_PHY_COBF_JOINT_SOUNDING_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 18, 1) -#define WMI_UHRCAP_PHY_COBF_JOINT_SOUNDING_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 18, 1, value) - -/* Bit 19: IM pilots tx support */ -#define WMI_UHRCAP_PHY_IM_PILOTS_TX_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 19, 1) -#define WMI_UHRCAP_PHY_IM_PILOTS_TX_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 19, 1, value) - -/* Bit 20: IM pilots rx support */ -#define WMI_UHRCAP_PHY_IM_PILOTS_RX_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 20, 1) -#define WMI_UHRCAP_PHY_IM_PILOTS_RX_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 20, 1, value) - -/* Bit 21: COSR mode 1 support */ -#define WMI_UHRCAP_PHY_COSR_MODE_1_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 21, 1) -#define WMI_UHRCAP_PHY_COSR_MODE_1_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 21, 1, value) - -/* Bit 22: COSR mode 2 support */ -#define WMI_UHRCAP_PHY_COSR_MODE_2_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 22, 1) -#define WMI_UHRCAP_PHY_COSR_MODE_2_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 22, 1, value) - -/* Bit 23: DRU DBW 20 in PBW 20 support */ -#define WMI_UHRCAP_PHY_DRU_DBW_20_PBW_20_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 23, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_20_PBW_20_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 23, 1, value) - -/* Bit 24: DRU DBW 40 in PBW 40 support */ -#define WMI_UHRCAP_PHY_DRU_DBW_40_PBW_40_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 24, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_40_PBW_40_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 24, 1, value) - -/* Bit 25: DRU DBW 80 in PBW 80 support */ -#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_80_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 25, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_80_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 25, 1, value) - -/* Bit 26: DRU DBW 80 in PBW 160 MHz support */ -#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_160_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 26, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_160_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 26, 1, value) - -/* Bit 27: DRU DBW 80 in PBW 320 MHz support */ -#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_320_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 27, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_320_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 27, 1, value) - -/* Bit 28: DRU DBW 20 in PBW >= 80 MHz support */ -#define WMI_UHRCAP_PHY_DRU_DBW_20_PBW_80_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 28, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_20_PBW_80_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 28, 1, value) - -/* Bit 29: DRU DBW 40 in PBW >= 80 MHz support */ -#define WMI_UHRCAP_PHY_DRU_DBW_40_PBW_80_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 29, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_40_PBW_80_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 29, 1, value) - -/* Bit 30: DRU DBW 60 in PBW >= 80 MHz support */ -#define WMI_UHRCAP_PHY_DRU_DBW_60_PBW_80_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 30, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_60_PBW_80_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 30, 1, value) - -/* Bit 31: DRU+RRU hybrid mode support */ -#define WMI_UHRCAP_PHY_DRU_RRU_HYBRID_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 31, 1) -#define WMI_UHRCAP_PHY_DRU_RRU_HYBRID_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 31, 1, value) - -/* Bits 32-39: Reserved */ - -/* - * ToDo: Bits 40-63 - */ - -/* - * ToDo: Bits 64-95 - */ - -/* - * ToDO: Bits 96-127 - */ - -/* - * ToDo: Bits 128-159 - */ - -/* - * ToDo: Bits 160-191 - */ - -/* - * ToDo: Bits 192-223 - */ - -/* - * ToDo: Bits 224-255 - */ - -/****** End of 11BN UHR PHY Capabilities Information field ******/ /* } */ - -/****** 11BN UHR MAC Capabilities Information field ******/ /* { */ - -/* Bit 0: DPS Support */ -#define WMI_UHRCAP_MAC_DPS_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 0, 1) -#define WMI_UHRCAP_MAC_DPS_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 0, 1, value) - -/* Bit 1: DPS Assisting support */ -#define WMI_UHRCAP_MAC_DPS_ASSIS_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 1, 1) -#define WMI_UHRCAP_MAC_DPS_ASSIS_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 1, 1, value) - -/* Bit 2: DPS AP Static HCM Support */ -#define WMI_UHRCAP_MAC_DPS_AP_HCM_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 2, 1) -#define WMI_UHRCAP_MAC_DPS_AP_HCM_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 2, 1, value) - -/* Bit 3: Reserved */ - -/* Bit 4: NPCA support */ -#define WMI_UHRCAP_MAC_NPCA_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 4, 1) -#define WMI_UHRCAP_MAC_NPCA_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 4, 1, value) - -/* Bit 5: Enhanced BSR support */ -#define WMI_UHRCAP_MAC_BSR_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 5, 1) -#define WMI_UHRCAP_MAC_BSR_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 5, 1, value) - -/* Bit 6: Additional Mapped TID Support */ -#define WMI_UHRCAP_MAC_ADDITIONAL_TID_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 6, 1) -#define WMI_UHRCAP_MAC_ADDITIONAL_TID_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 6, 1, value) - -/* Bit 7: EOTSP Support */ -#define WMI_UHRCAP_MAC_EOTSP_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 7, 1) -#define WMI_UHRCAP_MAC_EOTSP_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 7, 1, value) - -/* Bit 8: DSO Support */ -#define WMI_UHRCAP_MAC_DSO_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 8, 1) -#define WMI_UHRCAP_MAC_DSO_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 8, 1, value) - -/* Bit 9: P-EDCA Support */ -#define WMI_UHRCAP_MAC_P_EDCA_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 9, 1) -#define WMI_UHRCAP_MAC_P_EDCA_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 9, 1, value) - -/* Bit 10: DBE Support */ -#define WMI_UHRCAP_MAC_DBE_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 10, 1) -#define WMI_UHRCAP_MAC_DBE_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 10, 1, value) - -/* Bit 11: UL LLI Support */ -#define WMI_UHRCAP_MAC_UL_LLI_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 11, 1) -#define WMI_UHRCAP_MAC_UL_LLI_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 11, 1, value) - -/* Bit 12: Peer-to-Peer LLI Support */ -#define WMI_UHRCAP_MAC_PEER_LLI_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 12, 1) -#define WMI_UHRCAP_MAC_PEER_LLI_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 12, 1, value) - -/* Bit 13: PUO Support */ -#define WMI_UHRCAP_MAC_PUO_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 13, 1) -#define WMI_UHRCAP_MAC_PUO_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 13, 1, value) - -/* Bit 14: AP PUO Support */ -#define WMI_UHRCAP_MAC_AP_PUO_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 14, 1) -#define WMI_UHRCAP_MAC_AP_PUO_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 14, 1, value) - -/* Bit 15: DUO Support */ -#define WMI_UHRCAP_MAC_DUO_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 15, 1) -#define WMI_UHRCAP_MAC_DUO_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 15, 1, value) - -/* Bit 16: OM Control UL MU Data Disable RX Support */ -#define WMI_UHRCAP_MAC_OM_CTRL_UL_MU_DISABLE_RX_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 16, 1) -#define WMI_UHRCAP_MAC_OM_CTRL_UL_MU_DISABLE_RX_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 16, 1, value) - -/* Bit 17: AOM Support */ -#define WMI_UHRCAP_MAC_AOM_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 17, 1) -#define WMI_UHRCAP_MAC_AOM_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 17, 1, value) - -/* Bit 18: IFCS Location Support */ -#define WMI_UHRCAP_MAC_IFCS_LOC_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 18, 1) -#define WMI_UHRCAP_MAC_IFCS_LOC_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 18, 1, value) - -/* Bit 19: UHR TRS Support */ -#define WMI_UHRCAP_MAC_UHR_TRS_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 19, 1) -#define WMI_UHRCAP_MAC_UHR_TRS_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 19, 1, value) - -/* Bit 20: TXSPG Support */ -#define WMI_UHRCAP_MAC_TXSPG_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 20, 1) -#define WMI_UHRCAP_MAC_TXSPG_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 20, 1, value) - -/* Bit 21: TXOP Return Support in TXSPG */ -#define WMI_UHRCAP_MAC_TXOP_RETURN_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 21, 1) -#define WMI_UHRCAP_MAC_TXOP_RETURN_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 21, 1, value) - -/* Bit 22 - 25: UHR Operating Mode And Parameters Update Timeout - * - * UHR Operating Mode And Parameters Update Timeout Lookup Table - * - * +------------------+-----------------------------+ - * | Sub-field Value | Timeout Duration | - * +------------------+-----------------------------+ - * | 0 | 0 TUs | - * | 1 | 128 µs | - * | 2 | 256 µs | - * | 3 | 512 µs | - * | 4 | 1 TU | - * | 5 | 2 TUs | - * | 6 | 4 TUs | - * | 7 | 8 TUs | - * | 8 | 16 TUs | - * | 9 | 32 TUs | - * | 10 | 64 TUs | - * | 11 | 128 TUs | - * | 12 - 15 | Reserved for future use | - * +------------------+-----------------------------+ - */ -#define WMI_UHRCAP_MAC_UHR_OPMODE_TIMEOUT_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 22, 4) -#define WMI_UHRCAP_MAC_UHR_OPMODE_TIMEOUT_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 22, 4, value) - -/* Bit 26 - 28 : Parameter Update Adv Notification Interval */ -#define WMI_UHRCAP_MAC_PARAM_UPDATE_ADV_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 26, 3) -#define WMI_UHRCAP_MAC_PARAM_UPDATE_ADV_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 26, 3, value) - -/* Bit 29-33: Update Indication In TIM Interval */ -#define WMI_UHRCAP_MAC_UPDATE_IND_TIM_GET(uhr_cap_mac) \ - (WMI_GET_BITS(uhr_cap_mac[0], 29, 3) | \ - (WMI_GET_BITS(uhr_cap_mac[1], 0, 2) << 3)) -#define WMI_UHRCAP_MAC_UPDATE_IND_TIM_SET(uhr_cap_mac, value) \ - do { \ - WMI_SET_BITS(uhr_cap_mac[0], 29, 3, value & 0x7); \ - WMI_SET_BITS(uhr_cap_mac[1], 0, 2, ((value & 0x18) >> 3)); \ - } while (0) - -/* Bit 34: Bounded ESS */ -#define WMI_UHRCAP_MAC_BOUNDED_ESS_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[1], 3, 1) -#define WMI_UHRCAP_MAC_BOUNDED_ESS_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[1], 3, 1, value) - -/* Bit 35: BTM Assurance */ -#define WMI_UHRCAP_MAC_BTM_ASSURANCE_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[1], 4, 1) -#define WMI_UHRCAP_MAC_BTM_ASSURANCE_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[1], 4, 1, value) - -/* Bit 36: Co-BF Support */ -#define WMI_UHRCAP_MAC_COBF_SUPPORT_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[1], 5, 1) -#define WMI_UHRCAP_MAC_COBF_SUPPORT_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[1], 5, 1, value) - -/* Bits 37-63 --- Reserved */ - -/* - * NOTE: uhr_cap_mac[2] and uhr_cap_mac[3] (bits 64-127) are reserved. - * WMI_MAX_UHRCAP_MAC_SIZE is kept at 4 for backward compatibility. - * DBE Capability Parameters are carried in the separate uhr_cap_dbe[] - * array using WMI_UHRCAP_DBE_* macros below. - */ - -/****** End of 11BN UHR MAC Capabilities Information field ******/ /* } */ - -/****** 11BN UHR DBE Capability Parameters field ******/ /* { */ - -/* Bits B0-B2: DBE Maximum Supported Bandwidth - * - * DBE Maximum Supported Bandwidth Lookup Table - * - * +------------------+-----------------------------+ - * | Sub-field Value | DBE Bandwidth | - * +------------------+-----------------------------+ - * | 0 | Reserved | - * | 1 | 40 MHz DBE bandwidth | - * | 2 | 80 MHz DBE bandwidth | - * | 3 | 160 MHz DBE bandwidth | - * | 4 | 320 MHz DBE bandwidth | - * | 5 to 7 | Reserved | - * +------------------+-----------------------------+ - */ -#define WMI_UHRCAP_DBE_MAX_SUP_BW_GET(uhr_cap_dbe) \ - WMI_GET_BITS(uhr_cap_dbe[0], 0, 3) -#define WMI_UHRCAP_DBE_MAX_SUP_BW_SET(uhr_cap_dbe, value) \ - WMI_SET_BITS(uhr_cap_dbe[0], 0, 3, value) - -/* Bit B3: EHT-MCS Map (BW=160 MHz) Present */ -#define WMI_UHRCAP_DBE_EHT_MCS_160_PRESENT_GET(uhr_cap_dbe) \ - WMI_GET_BITS(uhr_cap_dbe[0], 3, 1) -#define WMI_UHRCAP_DBE_EHT_MCS_160_PRESENT_SET(uhr_cap_dbe, value) \ - WMI_SET_BITS(uhr_cap_dbe[0], 3, 1, value) - -/* Bit B4: EHT-MCS Map (BW=320 MHz) Present */ -#define WMI_UHRCAP_DBE_EHT_MCS_320_PRESENT_GET(uhr_cap_dbe) \ - WMI_GET_BITS(uhr_cap_dbe[0], 4, 1) -#define WMI_UHRCAP_DBE_EHT_MCS_320_PRESENT_SET(uhr_cap_dbe, value) \ - WMI_SET_BITS(uhr_cap_dbe[0], 4, 1, value) - -/* Bits B5-B7: Reserved */ - -/* Bits B8-B31: EHT-MCS Map (BW=160 MHz) — present only if B3 is set (0 or 24 bits) */ -#define WMI_UHRCAP_DBE_EHT_MCS_MAP_160_GET(uhr_cap_dbe) \ - WMI_GET_BITS(uhr_cap_dbe[0], 8, 24) -#define WMI_UHRCAP_DBE_EHT_MCS_MAP_160_SET(uhr_cap_dbe, value) \ - WMI_SET_BITS(uhr_cap_dbe[0], 8, 24, value) - -/* Bits B32-B55: EHT-MCS Map (BW=320 MHz) — present only if B4 is set (0 or 24 bits) */ -#define WMI_UHRCAP_DBE_EHT_MCS_MAP_320_GET(uhr_cap_dbe) \ - WMI_GET_BITS(uhr_cap_dbe[1], 0, 24) -#define WMI_UHRCAP_DBE_EHT_MCS_MAP_320_SET(uhr_cap_dbe, value) \ - WMI_SET_BITS(uhr_cap_dbe[1], 0, 24, value) - -/****** End of 11BN UHR DBE Capability Parameters field ******/ /* } */ - -#define WMI_CAP_EXT2_NPCA_ENABLED_GET(npca_capability) \ - WMI_GET_BITS(npca_capability, 0, 1) -#define WMI_CAP_EXT2_NPCA_ENABLED_SET(npca_capability, value) \ - WMI_SET_BITS(npca_capability, 0, 1, value) - -#define WMI_CAP_EXT2_NPCA_MIN_DUR_THRESHOLD_GET(npca_capability) \ - WMI_GET_BITS(npca_capability, 1, 4) -#define WMI_CAP_EXT2_NPCA_MIN_DUR_THRESHOLD_SET(npca_capability, value) \ - WMI_SET_BITS(npca_capability, 1, 5, value) - -#define WMI_CAP_EXT2_NPCA_SWITCH_DELAY_GET(npca_capability) \ - WMI_GET_BITS(npca_capability, 5, 6) -#define WMI_CAP_EXT2_NPCA_SWITCH_DELAY_SET(npca_capability, value) \ - WMI_SET_BITS(npca_capability, 5, 6, value) - -#define WMI_CAP_EXT2_NPCA_SWITCH_BACK_DELAY_GET(npca_capability) \ - WMI_GET_BITS(npca_capability, 11, 6) -#define WMI_CAP_EXT2_NPCA_SWITCH_BACK_DELAY_SET(npca_capability, value) \ - WMI_SET_BITS(npca_capability, 11, 6, value) - -#define WMI_CAP_EXT2_NPCA_QSRC_GET(npca_capability) \ - WMI_GET_BITS(npca_capability, 17, 2) -#define WMI_CAP_EXT2_NPCA_QSRC_SET(npca_capability, value) \ - WMI_SET_BITS(npca_capability, 17, 2, value) - -#define WMI_CAP_EXT2_NPCA_MOPLEN_GET(npca_capability) \ - WMI_GET_BITS(npca_capability, 19, 1) -#define WMI_CAP_EXT2_NPCA_MOPLEN_SET(npca_capability, value) \ - WMI_SET_BITS(npca_capability, 19, 1, value) - - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_HW_MODE_CAPABILITIES */ /* hw_mode_id - identify a particular set of HW characteristics, @@ -42766,7 +37493,6 @@ typedef struct { */ typedef enum { WMI_TWT_STA_SYNC_EVENT_CAP = 1, /* STA TWT: FW internal errors reported using sync WMI_TWT_ACK_EVENTID */ - WMI_TWT_FLEXI_SUPPORT = 2, /* Add new TWT Caps above */ WMI_TWT_MAX_CAP = 32, @@ -43254,8 +37980,6 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) /* set peer to associated state. will cary all parameters * determined during assocication time */ WMI_RETURN_STRING(WMI_PEER_ASSOC_CMDID); - /* peer assoc v2 cmd should be used for non-legacy targets */ - WMI_RETURN_STRING(WMI_PEER_ASSOC_V2_CMDID); /* add a wds (4 address ) entry. used only for testing * WDS feature on AP products */ WMI_RETURN_STRING(WMI_PEER_ADD_WDS_ENTRY_CMDID); @@ -43981,49 +38705,6 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_MLO_LINK_RECONFIG_COMPLETE_CMDID); WMI_RETURN_STRING(WMI_SAWF_EZMESH_HOP_COUNT_CMDID); WMI_RETURN_STRING(WMI_VDEV_VBSS_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_NDP_SET_LATENCY_TPUT_CMDID); - WMI_RETURN_STRING(WMI_MLO_LINK_TTLM_COMPLETE_CMDID); - WMI_RETURN_STRING(WMI_BPF_SET_SUPPORTED_OFFLOAD_BITMAP_CMDID); - WMI_RETURN_STRING(WMI_BPF_SET_APF_MODE_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_PCIE_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_PCIE_LPM_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_DCVS_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_EDPS_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_PUO_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_PEER_TID_RATE_CUSTOM_CMDID); - WMI_RETURN_STRING(WMI_VDEV_GET_TPC_IE_POWER_CMDID); - WMI_RETURN_STRING(WMI_VDEV_TRAFFIC_MONITORING_CMDID); - WMI_RETURN_STRING(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_WLAN_MODE_REQ_CMDID); - WMI_RETURN_STRING(WMI_NAN_ENABLE_CMDID); - WMI_RETURN_STRING(WMI_NAN_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_NAN_DISABLE_CMDID); - WMI_RETURN_STRING(WMI_ROAM_SMD_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_ROAM_SMD_START_STATUS_CMDID); - WMI_RETURN_STRING(WMI_VDEV_REPURPOSE_RESP_CMDID); - WMI_RETURN_STRING(WMI_IPA_RING_STATS_REQ_CMDID); - WMI_RETURN_STRING(WMI_PDEV_POWER_DATAPATH_STATS_CMDID); - WMI_RETURN_STRING(WMI_SMD_ROAM_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID); - WMI_RETURN_STRING(WMI_VDEV_UNIFIED_CONNECT_CMDID); - WMI_RETURN_STRING(WMI_VDEV_UNIFIED_DISCONNECT_CMDID); - WMI_RETURN_STRING(WMI_NAN_LOCAL_SCHEDULE_CMDID); - WMI_RETURN_STRING(WMI_NAN_PEER_SCHEDULE_CMDID); - WMI_RETURN_STRING(WMI_NAN_PEER_PARAMS_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_OEM_DATA_CMDID); - WMI_RETURN_STRING(WMI_TWT_ADD_CH_USAGE_CMDID); - WMI_RETURN_STRING(WMI_COEX_GET_POLICY_STATS_CMDID); - WMI_RETURN_STRING(WMI_PEER_UHR_OMP_CMDID); - WMI_RETURN_STRING(WMI_REQUEST_TDLS_STATS_CMDID); - WMI_RETURN_STRING(WMI_GET_CHIPSET_LOGGING_STATS_CMDID); - WMI_RETURN_STRING(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID); - WMI_RETURN_STRING(WMI_NAN_DISC_SERVICE_REQ_CMDID); - WMI_RETURN_STRING(WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID); - WMI_RETURN_STRING(WMI_SET_MODIFY_TX_PLIM_CMDID); - WMI_RETURN_STRING(WMI_GET_AVG_TX_POWER_CMDID); - WMI_RETURN_STRING(WMI_GET_TX_POWER_CALLING_CMDID); - WMI_RETURN_STRING(WMI_ATHDIAG_READ_WRITE_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -44445,10 +39126,9 @@ typedef struct { A_UINT32 num_6g_reg_rules_client_lpi[WMI_REG_CLIENT_MAX]; A_UINT32 num_6g_reg_rules_client_vlp[WMI_REG_CLIENT_MAX]; /* - * NOTE: We cannot add new parameters to the fixed param TLV though - * we have enough buffer size (WMI_SVC_MSG_SIZE) for the given WMI event. - * This is due to a crash seen in the host parsing logic of this fixed param. - * New params can be added in the same message but in other TLVs. + * NOTE: no further fields can be added into this struct, due to + * message buffer size limitations in certain targets for the + * WMI_REG_CHAN_LIST_CC_EXT_EVENT message. */ /* * This fixed_param TLV is followed by the following TLVs: @@ -44464,10 +39144,6 @@ typedef struct { * - wmi_regulatory_rule_meta_data reg_meta_data[] * struct used to fill meta information specific to new reg rules * getting added(i.e. from C2C onwards). - * - wmi_hw_blacklist_chan_fixed_param hw_blacklist_chan_fixed_param[0 or 1] - * optional TLV for reporting HW channel blacklist meta-data. - * - wmi_hw_blacklist_chan_data, hw_blacklist_chan_data[] - * optional TLV for reporting HW channel blacklist information. */ } wmi_reg_chan_list_cc_event_ext_fixed_param; @@ -44620,10 +39296,6 @@ typedef struct { * This TLV array contains zero or more TLVs of channel CFI and * EIRP power values for each of the total number of channels * per global operating class. - * 6. wmi_hw_blacklist_chan_fixed_param hw_blacklist_chan_fixed_param[] - * optional meta-data for HW channel blacklist - * 7. wmi_hw_blacklist_chan_data hw_blacklist_chan_data[] - * optional HW channel blacklist information */ } wmi_afc_event_fixed_param; @@ -44716,233 +39388,6 @@ typedef struct { A_UINT32 eirp_pwr; /* maximum permissible EIRP available for above CFI in dBm, value is stored in 0.01 dBm steps */ } wmi_afc_chan_eirp_power_info; - -typedef enum { - WMI_11BE_PUNCTURE_PATTERN_80MHZ_MINUS_20MHZ_0x1 = 0, - WMI_11BE_PUNCTURE_PATTERN_80MHZ_MINUS_20MHZ_0x2 = 1, - WMI_11BE_PUNCTURE_PATTERN_80MHZ_MINUS_20MHZ_0x4 = 2, - WMI_11BE_PUNCTURE_PATTERN_80MHZ_MINUS_20MHZ_0x8 = 3, - WMI_11BE_PUNCTURE_PATTERN_80MHZ_MAX, -} WMI_11BE_PUNCTURE_PATTERNS_80MHZ; - -typedef enum { - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x1 = 0, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x2 = 1, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x4 = 2, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x8 = 3, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x10 = 4, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x20 = 5, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x40 = 6, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x80 = 7, - - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_40MHZ_0x0C = 8, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_40MHZ_0x03 = 9, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_40MHZ_0xC0 = 10, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_40MHZ_0x30 = 11, - - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MAX, -} WMI_11BE_PUNCTURE_PATTERNS_160MHZ; - -typedef enum { - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0xC = 0, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0x3 = 1, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0xC0 = 2, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0x30 = 3, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0xC00 = 4, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0x300 = 5, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0xC000 = 6, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0x3000 = 7, - - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_80MHZ_0xF = 8, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_80MHZ_0xF0 = 9, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_80MHZ_0xF00 = 10, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_80MHZ_0xF000 = 11, - - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xF003 = 12, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xF00C = 13, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xF030 = 14, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xF0C0 = 15, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xF300 = 16, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xFC00 = 17, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0x003F = 18, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0x00CF = 19, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0x030F = 20, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0x0C0F = 21, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0x300F = 22, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xC00F = 23, - - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MAX, -} WMI_11BE_PUNCTURE_PATTERNS_320MHZ; - -typedef enum { - /* - * bits 16-19 of "blacklist_msg_info" in wmi_hw_blacklist_chan_fixed_param. - * This status code intimates host whether the TLV sent by - * Halphy is to update the master channel list or clear it. - */ - WMI_HW_BLACKLIST_CHAN_SP_UPDATE = 0, - WMI_HW_BLACKLIST_CHAN_VLP_UPDATE, - /* the below enums are added for future scope */ - WMI_HW_BLACKLIST_CHAN_SP_CLEAR, - WMI_HW_BLACKLIST_CHAN_VLP_CLEAR, - WMI_HW_BLACKLIST_CHAN_UPDATE_ALL, - WMI_HW_BLACKLIST_CHAN_CLEAR_ALL, - WMI_HW_BLACKLIST_CHAN_INVALID = 15, -} WMI_HW_BLACKLIST_CHAN_RESP_CMD_CODE; - -typedef enum { - /* - * bit 20, "blacklist_msg_info" flag in wmi_hw_blacklist_chan_fixed_param - * This bit field informs the host whether all the blacklist channel - * information has been sent, or if further messages will follow to - * deliver the remaining information. - */ - WMI_HW_BLACKLIST_CHAN_EVENT_DONE = 0, /* Indicates it is the last event */ - WMI_HW_BLACKLIST_CHAN_EVENT_MORE = 1, /* Indicates more evts will follow */ -} WMI_HW_BLACKLIST_CHAN_DATA_EVENT_FLAG; - -#define WMI_GET_BLACKLIST_MSG_INFO_WMI_EVT_SEQ_NUM(flag) \ - WMI_GET_BITS(flag, 0, 8) -#define WMI_SET_BLACKLIST_MSG_INFO_WMI_EVT_SEQ_NUM(flag, val) \ - WMI_SET_BITS(flag, 0, 8, val) - -#define WMI_GET_BLACKLIST_MSG_INFO_TOTAL_WMI_EVT_NUM(flag) \ - WMI_GET_BITS(flag, 8, 8) -#define WMI_SET_BLACKLIST_MSG_INFO_TOTAL_WMI_EVT_NUM(flag, val) \ - WMI_SET_BITS(flag, 8, 8, val) - -#define WMI_GET_BLACKLIST_MSG_INFO_RESP_CODE(flag) \ - WMI_GET_BITS(flag, 16, 4) -#define WMI_SET_BLACKLIST_MSG_INFO_RESP_CODE(flag, val) \ - WMI_SET_BITS(flag, 16, 4, val) - -#define WMI_GET_BLACKLIST_MSG_INFO_EVT_FLAG(flag) \ - WMI_GET_BITS(flag, 20, 1) -#define WMI_SET_BLACKLIST_MSG_INFO_EVT_FLAG(flag, val) \ - WMI_SET_BITS(flag, 20, 1, val) - -#define WMI_GET_BLACKLIST_CHANNELS_TOTAL_NUM_CHAN(flag) \ - WMI_GET_BITS(flag, 0, 16) -#define WMI_SET_BLACKLIST_CHANNELS_TOTAL_NUM_CHAN(flag, val) \ - WMI_SET_BITS(flag, 0, 16, val) - -#define WMI_GET_BLACKLIST_CHANNELS_CURRENT_NUM_CHAN(flag) \ - WMI_GET_BITS(flag, 16, 16) -#define WMI_SET_BLACKLIST_CHANNELS_CURRENT_NUM_CHAN(flag, val) \ - WMI_SET_BITS(flag, 16, 16, val) - -typedef struct { - /** TLV tag and len; - * tag equals WMITLV_TAG_STRUC_wmi_hw_blacklist_chan_fixed_param*/ - A_UINT32 tlv_header; - A_UINT32 phy_id; - union { - A_UINT32 blacklist_msg_info; - /* - * bit 7 - 0 -> Current WMI event sequence number - * bit 15 - 8 -> Total number of WMI events [For debugging only] - * bit 19 - 16 -> ENUM "WMI_HW_BLACKLIST_CHAN_RESP_CMD_CODE" - * bit 20 -> ENUM "WMI_HW_BLACKLIST_CHAN_DATA_EVENT_FLAG" - * bit 31 - 21 -> Reserved - */ - struct { - A_UINT32 - blacklist_wmi_seq_num: 8, - blacklist_wmi_total_num: 8, - blacklist_resp_code: 4, - blacklist_event_flag:1, - reserved: 11; - }; - }; - /* - * bit 15 - 0 -> Total number of HW blacklist channels - * bit 31 - 16 -> number of HW blacklist channels in current WMI - */ - union { - A_UINT32 num_hw_blacklist_channels; - struct { - A_UINT32 - total_num_chan: 16, - current_num_chan: 16; - }; - }; -} wmi_hw_blacklist_chan_fixed_param; - -#define WMI_GET_FREQ_INFO_PRI20_BITMAP(flag) \ - WMI_GET_BITS(flag, 0, 16) -#define WMI_SET_FREQ_INFO_PRI20_BITMAP(flag, val) \ - WMI_SET_BITS(flag, 0, 16, val) - -#define WMI_GET_FREQ_INFO_CHAN_CENTER_FREQ(flag) \ - WMI_GET_BITS(flag, 16, 16) -#define WMI_SET_FREQ_INFO_CHAN_CENTER_FREQ(flag, val) \ - WMI_SET_BITS(flag, 16, 16, val) - -#define WMI_GET_CHAN_LIST_META_DATA_POWER_MODE(flag) \ - WMI_GET_BITS(flag, 0, 4) -#define WMI_SET_CHAN_LIST_META_DATA_POWER_MODE(flag, val) \ - WMI_SET_BITS(flag, 0, 4, val) - -#define WMI_GET_CHAN_LIST_META_DATA_MAX_BW(flag) \ - WMI_GET_BITS(flag, 4, 8) -#define WMI_SET_CHAN_LIST_META_DATA_MAX_BW(flag, val) \ - WMI_SET_BITS(flag, 4, 8, val) - -#define WMI_GET_PUNCTURE_PATTERN_BITMAP(flag) \ - WMI_GET_BITS(flag, 0, 24) -#define WMI_SET_PUNCTURE_PATTERN_BITMAP(flag, val) \ - WMI_SET_BITS(flag, 0, 24, val) - -typedef struct { - /** TLV tag and len; - * tag equals WMITLV_TAG_STRUC_wmi_hw_blacklist_chan_data */ - A_UINT32 tlv_header; - /* - * bit 15 - 0 -> bitmap representing a set of 20MHz primary channels - * bit 31 - 16 -> channel center frequency in MHz for the given Max BW - * in "chan_list_meta_data" - */ - union { - A_UINT32 freq_info; - struct { - A_UINT32 - pri20_bitmap: 16, - chan_center_freq: 16; - }; - }; - /* - * bit 3 - 0 -> Power mode "WMI_6GHZ_REG_PWRMODE_TYPE" - * bit 11 - 4 -> Max BW with enum "wmi_channel_width" - * bit 31 - 12 -> reserved - */ - union { - A_UINT32 chan_list_meta_data; - struct { - A_UINT32 - power_mode: 4, - max_bw: 8, - reserved1: 20; - }; - }; - /* - * bit represents blacklisted puncture pattern based on enums - * WMI_11BE_PUNCTURE_PATTERNS_320MHZ, WMI_11BE_PUNCTURE_PATTERNS_160MHZ, - * WMI_11BE_PUNCTURE_PATTERNS_80MHZ - * bit 23 - 0 -> bitmap representing a set of puncture patterns of the - * given bandwidth. The bandwidth is represented by - * bits 8-15 of A_UINT32 chan_list_meta_data - * bit 31 - 24 -> reserved for future puncture patterns - */ - union { - A_UINT32 puncture_pattern_bitmap_info; - struct { - A_UINT32 - puncture_pattern_bitmap: 24, - reserved2: 8; - }; - }; -} wmi_hw_blacklist_chan_data; - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_11d_scan_start_cmd_fixed_param */ A_UINT32 vdev_id; @@ -45201,8 +39646,6 @@ typedef struct { * optional TLV for dbw_chan * wmi_dbw_chan_info dbw_chan_info * optional TLV used for dbw_chan_info - * wmi_uhr_ap_npca_params npca_params - * optional TLV used to update NPCA information */ } wmi_pdev_multiple_vdev_restart_request_cmd_fixed_param; @@ -45522,10 +39965,7 @@ typedef struct { #define WLM_FLAGS_ROAM_SUPPRESS 1 #define WLM_FLAGS_ALLOW_FINAL_BMISS_ROAM 2 -/* bit 8: Final bmiss roam will be triggered when all active links - * are final bmiss reported. - */ -#define WLM_FLAGS_ROAM_WHEN_ALL_LINKS_FBMISS 1 +/* bit 8: reserved for roaming */ /* bit 9-11 of flags is used for powersave operation */ /* bit 9: WLM_FLAGS_PS_DISABLE_BMPS, disable BMPS if bit is set */ @@ -45569,8 +40009,6 @@ typedef struct { #define WLM_FLAGS_TSF_LATENCY_COMPENSATE_ENABLED_SET(flag) WMI_SET_BITS(flag, 4, 1, val) #define WLM_FLAGS_ROAM_GET_POLICY(flag) WMI_GET_BITS(flag, 6, 2) #define WLM_FLAGS_ROAM_SET_POLICY(flag, val) WMI_SET_BITS(flag, 6, 2, val) -#define WLM_FLAGS_ROAM_GET_WHEN_ALL_LINKS_FBMISS(flag) WMI_GET_BITS(flag, 8, 1) -#define WLM_FLAGS_ROAM_SET_WHEN_ALL_LINKS_FBMISS(flag, val) WMI_SET_BITS(flag, 8, 1, val) #define WLM_FLAGS_PS_IS_BMPS_DISABLED(flag) WMI_GET_BITS(flag, 9, 1) #define WLM_FLAGS_PS_IS_CSS_CLPS_DISABLED(flag) WMI_GET_BITS(flag, 10, 1) #define WLM_FLAGS_PS_SET_CSS_CLPS_DISABLE(flag, val) WMI_SET_BITS(flag, 10, 1, val) @@ -45649,22 +40087,6 @@ typedef struct { A_UINT32 client_id_bitmask; } wmi_wlm_config_cmd_fixed_param; -typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - wmi_mac_addr peer_macaddr; - A_UINT32 responder_pm_mode; - A_UINT32 negotiation_type; - A_UINT32 twt_request; - A_UINT32 twt_setup_cmd; - A_UINT32 is_triggered; - A_UINT32 flow_type; - A_UINT32 wake_interval_exp; - A_UINT32 twt_protection; - A_UINT32 nominal_min_wake_duration; - A_UINT32 wake_interval_mantisa; -} wmi_ch_usage_add_dialog_cmd_fixed_param; - /* Broadcast TWT enable/disable for both REQUESTER and RESPONDER */ #define TWT_EN_DIS_FLAGS_GET_BTWT(flag) WMI_GET_BITS(flag, 0, 1) #define TWT_EN_DIS_FLAGS_SET_BTWT(flag, val) WMI_SET_BITS(flag, 0, 1, val) @@ -45756,32 +40178,11 @@ typedef struct { #define TWT_EN_DIS_FLAGS_SET_DIS_BTWT_AUTO_DELETE(flag, val) \ WMI_SET_BITS(flag, 7, 1, val) -/* - * Bit 8: indicates whether pdev_id is valid or vdev_id is valid. - * 0: pdev_id is valid (MAC-level TWT enable/disable) - * 1: vdev_id is valid (STA vdev-level TWT enable/disable) - */ -#define TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flag) WMI_GET_BITS(flag, 8, 1) -#define TWT_EN_DIS_FLAGS_SET_VDEV_SUPPORT(flag, val) WMI_SET_BITS(flag, 8, 1, val) - -/* bits 9-31: unused / reserved */ - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_enable_cmd_fixed_param */ - /** - * pdev_id or vdev_id depending on bit 8 of flags. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 0: - * pdev_id identifies the MAC. - * See macros starting with WMI_PDEV_ID_ for values. - * In non-DBDC case host should set it to 0. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 1: - * vdev_id is for STA vdev-level TWT enable. - * TWT enable applies only to that specific STA vdev. + /** pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0 */ - union { - A_UINT32 pdev_id; - A_UINT32 vdev_id; - }; + A_UINT32 pdev_id; A_UINT32 sta_cong_timer_ms; /* STA TWT congestion timer TO value in terms of ms */ A_UINT32 mbss_support; /* Reserved */ A_UINT32 default_slot_size; /* This is the default value for the TWT slot setup by AP (units = microseconds) */ @@ -45824,70 +40225,23 @@ typedef enum _WMI_ENABLE_TWT_STATUS_T { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_enable_complete_event_fixed_param */ - /** - * pdev_id or vdev_id depending on bit 8 of flags. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 0: - * pdev_id identifies the MAC. - * See macros starting with WMI_PDEV_ID_ for values. - * In non-DBDC case host should set it to 0. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 1: - * vdev_id is for STA vdev-level TWT enable. - * TWT enable applies only to that specific STA vdev. - */ - union { - A_UINT32 pdev_id; - A_UINT32 vdev_id; - }; + /** pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0 */ + A_UINT32 pdev_id; A_UINT32 status; /* WMI_ENABLE_TWT_STATUS_T */ - /* flags: - * mirrors TWT_EN_DIS_FLAGS_* from the enable command; - * bit 8 indicates pdev vs vdev - */ - A_UINT32 flags; } wmi_twt_enable_complete_event_fixed_param; typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_disable_cmd_fixed_param */ - /** - * pdev_id or vdev_id depending on bit 8 of flags. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 0: - * pdev_id identifies the MAC. - * See macros starting with WMI_PDEV_ID_ for values. - * In non-DBDC case host should set it to 0. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 1: - * vdev_id is for STA vdev-level TWT disable. - * TWT disable applies only to that specific STA vdev. - */ - union { - A_UINT32 pdev_id; /* host should never set it to WMI_PDEV_ID_SOC */ - A_UINT32 vdev_id; - }; + /** pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0 */ + A_UINT32 pdev_id; /* host should never set it to WMI_PDEV_ID_SOC */ A_UINT32 flags; /* enable/disable flags, refer to MACROs TWT_EN_DIS_FLAGS_* (TWT_EN_DIS_FLAGS_GET_BTWT etc.) */ A_UINT32 reason_code; /* refer to WMI_DISABLE_TWT_REASON_T */ } wmi_twt_disable_cmd_fixed_param; typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_disable_complete_event_fixed_param */ - /** - * pdev_id or vdev_id depending on bit 8 of flags. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 0: - * pdev_id identifies the MAC. - * See macros starting with WMI_PDEV_ID_ for values. - * In non-DBDC case host should set it to 0. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 1: - * vdev_id is for STA vdev-level TWT disable. - * TWT disable applies only to that specific STA vdev. - */ - union { - A_UINT32 pdev_id; /* host should never set it to WMI_PDEV_ID_SOC */ - A_UINT32 vdev_id; - }; + A_UINT32 pdev_id; A_UINT32 status; /* refer to WMI_DISABLE_TWT_STATUS_T enum */ - /* flags: - * mirrors TWT_EN_DIS_FLAGS_* from the enable command; - * bit 8 indicates pdev vs vdev - */ - A_UINT32 flags; } wmi_twt_disable_complete_event_fixed_param; typedef struct { @@ -46164,9 +40518,6 @@ typedef enum _WMI_DEL_TWT_STATUS_T { WMI_DEL_TWT_STATUS_CHANGE_CONGESTION_TIMEOUT, /* Congestion timeout changed */ WMI_DEL_TWT_STATUS_P2P_GO_NOA, /* P2P GO NOA */ WMI_DEL_TWT_STATUS_UNSUPPORTED_MLMR_MODE, /* Teardown due to MLMR */ - WMI_DEL_TWT_STATUS_MLO_LINK_INACTIVE, /* Teardown due to link going to inactive */ - WMI_DEL_TWT_STATUS_2G_TWT_NOT_ENABLED, /* Teardown due to 2.4 GHz TWT not enabled */ - WMI_DEL_TWT_STATUS_SCAN_STARTED, /* Teardown due to scan started */ } WMI_DEL_TWT_STATUS_T; typedef struct { @@ -46567,7 +40918,7 @@ typedef enum { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_spectral_bin_scaling_params */ A_UINT32 pdev_id; /* ID of pdev to which the scaling parameters are to be applied */ - A_UINT32 formula_id; /* WMI_SPECTRAL_SCALING_FORMULA_ID: Represents the formula to be used */ + WMI_SPECTRAL_SCALING_FORMULA_ID formula_id; /* Represets the formula to be used */ A_UINT32 low_level_offset; /* low level offset for fine tuning the scaling factor based on RSSI and AGC gain */ A_UINT32 high_level_offset; /* high level offset for fine tuning the scaling factor based on RSSI and AGC gain */ A_UINT32 rssi_thr; /* RSSI threshold to be used to adjust the inband power of the given spectral report */ @@ -46874,11 +41225,6 @@ typedef struct { A_UINT32 vdev_id; /* 1-Enable, 0-Disable */ A_UINT32 enable; - /* self_roaming_re_enable_time: - * Allow next deauth self-roaming only when time gap is more than - * self_roaming_re_enable_time w.r.t previous deauth self-roaming. - */ - A_UINT32 self_roaming_re_enable_time; /* units = seconds */ } wmi_roam_deauth_config_cmd_fixed_param; /** IDLE roam trigger parameters */ @@ -47056,24 +41402,6 @@ typedef struct { wmi_mac_addr transmit_addr; /* AKM suite type (as defined in the IEEE 802.11 spec) */ A_UINT32 akm_suite_type; - /** - * IEEE value for auth algorithm - * Authentication algorithm number = 3: - * Simultaneous Authentication of Equals (SAE) - * Authentication algorithm number = 8: - * IEEE 802.1X authentication - * Authentication algorithm number = 9: - * EPPKE authentication - */ - A_UINT32 auth_algo; - - /* IEEE value for below ciphers */ - /** unicast cipher set */ - A_UINT32 pairwise_cipher; - /** mcast/group cipher set */ - A_UINT32 group_cipher; - /** mcast/group management frames cipher set */ - A_UINT32 group_mgmt_cipher; } wmi_roam_preauth_start_event_fixed_param; typedef struct { @@ -47185,7 +41513,6 @@ typedef enum wmi_roam_invoke_status_error { WMI_ROAM_INVOKE_STATUS_INVALID_SCAN_MODE, /* Roam scan mode is invalid */ WMI_ROAM_INVOKE_STATUS_NO_CAND_AP, /* No candidate AP found to roam to */ WMI_ROAM_INVOKE_STATUS_HO_FAIL, /* handoff failed */ - WMI_ROAM_INVOKE_STATUS_SUSTAIN_CONN, /* Sustain existing connection when MLD self roaming fails */ } wmi_roam_invoke_status_error_t; typedef struct { @@ -47426,8 +41753,6 @@ typedef enum { WMI_ROAM_FAIL_REASON_CURR_AP_STILL_OK, /* Roam scan not happen due to current network condition is fine */ WMI_ROAM_FAIL_REASON_SCAN_CANCEL, /* Roam scan canceled */ WMI_ROAM_FAIL_REASON_MLD_EXTRA_SCAN_REQUIRED, /* Roaming is not triggered for current roam scan as extra scan is required to scan all MLD links */ - WMI_ROAM_FAIL_REASON_TTLM_REQUIRED, /* Roaming is not triggered as TTLM is required */ - WMI_ROAM_FAIL_REASON_LINKRECONFIG_REQUIRED, /* Roaming is not triggered as linkreconfig is required */ WMI_ROAM_FAIL_REASON_UNKNOWN = 255, } WMI_ROAM_FAIL_REASON_ID; @@ -47612,7 +41937,7 @@ typedef struct { * rssi_dbm_abs * Last known RSSI of the current BSSID at the moment when the frame * was sent and received. - * Host should ignore this field if its value is 0. + * This RSSI value is valid for deauth / disassoc frame only. * The rssi_dbm_abs value is the absolute value of the RSSI in dBm units. * For example, if the RSSI is -40 dBm, rssi_dbm_abs will be 40. */ @@ -47651,10 +41976,6 @@ typedef enum { WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_M4, WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_GTK_M1, WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_GTK_M2, - WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_ST_PREP_REQ, - WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_ST_PREP_RESP, - WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_ST_EXEC_REQ, - WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_ST_EXEC_RESP, } WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE; typedef enum { @@ -48179,18 +42500,6 @@ typedef enum { */ WMI_ROAM_PARAM_ROAM_LATENCY_OPTIMIZATION_BITMAP = 11, - /* - * Roam param to add RSSI penalty for non-6GHz Candidate AP - * during Roam Scan in case current connected AP is 6GHz and - * cand AP is non-6GHz. - * This RSSI penalty value (in dB units) for non-6GHz candidate AP - * will be configured via ini roam_rssi_delta_from_6ghz_to_non_6ghz. - * This configured RSSI penalty value will only be applicable for non-6GHz - * Candidate AP when the STA is connected to 6GHz Band AP and will - * not impact if STA is connected to non-6GHz Band AP - */ - WMI_ROAM_PARAM_ROAM_RSSI_PENALTY_FOR_NON_6GHZ_CAND_AP = 12, - /*=== END ROAM_PARAM_PROTOTYPE SECTION ===*/ } WMI_ROAM_PARAM; @@ -48230,114 +42539,6 @@ typedef enum { WLAN_CRYPTO_WPA3_SAE_ALLOW_MLO_HNP = 0x00020000, } wlan_crypto_roam_eht_config; -typedef enum { - /* - * Low-latency mode is suitable for applications with strict - * latency requirements and is also the default mode in the firmware. - * e.g VOIP, Online gaming. - */ - WMI_ROAM_LOWLATENCY_MODE = 0x0, - /* - * Packet-loss mode is suitable for applications that do not have - * strict latency requirements but have low tolerance for packet loss. - * e.g file transfer. - */ - WMI_ROAM_PACKETLOSSLESS_MODE = 0x1, - /* This mode is only used for WFA test purpose. */ - WMI_ROAM_MANUAL_MODE = 0x2, -} WMI_ROAM_SMD_MODE_PARAMS; - -/* - * useful macros defined for flags field in wmi_roam_smd_config_cmd_fixed_param - */ -#define WMI_SMD_CONFIG_FLAGS_GET_DISABLE_SMD_ASSOC(flags) \ - WMI_GET_BITS(flags, 0, 1) -#define WMI_SMD_CONFIG_FLAGS_SET_DISABLE_SMD_ASSOC(flags, val) \ - WMI_SET_BITS(flags, 0, 1, val) - -#define WMI_SMD_CONFIG_FLAGS_GET_DISABLE_SMD_TRANSITION(flags) \ - WMI_GET_BITS(flags, 1, 1) -#define WMI_SMD_CONFIG_FLAGS_SET_DISABLE_SMD_TRANSITION(flags, val) \ - WMI_SET_BITS(flags, 1, 1, val) - -/* - * useful macros defined for manual_conf field in - * wmi_roam_smd_config_cmd_fixed_param - */ -#define WMI_SMD_CONFIG_MANUAL_CONF_GET_EXECUTION_VIA_NEW_AP(conf) \ - WMI_GET_BITS(conf, 0, 1) -#define WMI_SMD_CONFIG_MANUAL_CONF_SET_EXECUTION_VIA_NEW_AP(conf, val) \ - WMI_SET_BITS(conf, 0, 1, val) - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_smd_config_cmd_fixed_param */ - A_UINT32 vdev_id; - - /* - * The mode used to control SMD transition involves a trade-off - * between low latency and packet loss. - * Depending on the upper-layer application, the choice may also vary. - * refer WMI_ROAM_SMD_MODE_PARAMS definition - */ - A_UINT32 prefer_mode; - /* flags: - * refer WMI_SMD_CONFIG_FLAGS_GET and _SET macros - * BIT 0 - Disable SMD association. - * BIT 1 - Disable SMD BSS transition, invalid when BIT 0 is set. - */ - A_UINT32 flags; - /* manual_conf: - * Valid only when prefer_mode is WMI_ROAM_MANUAL_MODE - * BIT 0 - SMD transition execution via new AP if set. - */ - A_UINT32 manual_conf; -} wmi_roam_smd_config_cmd_fixed_param; - -typedef enum { - WMI_SMD_START_STATUS_SUCCESS = 0, - - /* Failure that is not specifically defined */ - WMI_SMD_START_STATUS_UNSPECIFIC_FAILURE, - - /* Abort due to disconnection from upper layer */ - WMI_SMD_START_STATUS_ABORT_DISCONNECTION, - - /* Vdev repurpose failure */ - WMI_SMD_START_STATUS_VDEV_REPURPOSE_FAILURE, - - /* Preparation request frame no ACK */ - WMI_SMD_START_STATUS_PREP_REQ_TX_NO_ACK, - - /* No Preparation response frame received */ - WMI_SMD_START_STATUS_PREP_RESP_RX_TIMEOUT, -} WMI_SMD_START_STATUS_CODE; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_prep_resp_status_list */ - A_UINT32 ieee_link_id; - A_UINT32 status_code; /* same value defined in 'status code' in standard */ -} wmi_prep_resp_status_list; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_smd_start_status_cmd_fixed_param */ - - A_UINT32 vdev_id; - A_UINT32 status; /* Refer WMI_SMD_START_STATUS_CODE */ - /* kck_len: - * Valid when per AP-MLD ptk mode is used, KCK is used to - * calculate MIC in ST execution request frame. - */ - A_UINT32 kck_len; - - /* - * This fixed_param TLV is followed by the below TLVs: - * - * A_UINT8 smd_transition_ie[]; - * wmi_prep_resp_status_list status_list[]; - * A_UINT8 kck[]; - */ -} wmi_roam_smd_start_status_cmd_fixed_param; - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_big_data_cmd_fixed_param */ A_UINT32 vdev_id; @@ -48467,9 +42668,8 @@ typedef enum { WMI_6GHZ_REG_PWRMODE_VLP = 2, /* VLP mode for AP and client products */ WMI_6GHZ_REG_PWRMODE_SP_STA = 3, /* SP client mode for AP products */ WMI_6GHZ_REG_PWRMODE_C2C = 4, /*C2C client mode for AP and client products*/ - WMI_6GHZ_REG_PWRMODE_GVP = 5, /* GVP mode for AP and client products */ - WMI_6GHZ_REG_PWRMODE_MAX = 6 + WMI_6GHZ_REG_PWRMODE_MAX = 5 } WMI_6GHZ_REG_PWRMODE_TYPE; typedef struct { @@ -50557,81 +44757,13 @@ typedef struct { /****** End of 11BE EHT MAC Capabilities Information field ******/ -/****** 11BE EHT OPS Information field - DEPRECATED ******/ -/* DEPRECATED, replaced by - * "Bit 6 is for MCS15. If bit6 is 1 then we disable mcs15" - * OLD: Bit 0 is for MCS15. If bit0 is 1 then we enable mcs15 - */ +/****** 11BE EHT OPS Information field ******/ + +/* Bit 0 is for MCS15. If bit0 is 1 then we enable mcs15 */ #define WMI_EHT_OPS_SUPMCS15_GET(eht_ops) WMI_GET_BITS(eht_ops, 0, 1) #define WMI_EHT_OPS_SUPMCS15_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 0, 1, value) -/****** End of 11BE EHT OPS Information field - DEPRECATED ******/ -/****** 11BE EHT Operation Parameters field ******/ -/* Bit 0 EHT Operation Information Present */ -#define WMI_EHT_OPS_INFORMATION_PRESENT_GET(eht_ops) WMI_GET_BITS(eht_ops, 0, 1) -#define WMI_EHT_OPS_INFORMATION_PRESENT_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 0, 1, value) -/* Bit 1 Disabled Subchannel Bitmap Present */ -#define WMI_EHT_OPS_DISABLED_SUBCHANNEL_BITMAP_GET(eht_ops) WMI_GET_BITS(eht_ops, 1, 1) -#define WMI_EHT_OPS_DISABLED_SUBCHANNEL_BITMAP_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 1, 1, value) - -/* Bit 2 EHT default PE duration */ -#define WMI_EHT_OPS_PE_DURATION_GET(eht_ops) WMI_GET_BITS(eht_ops, 2, 1) -#define WMI_EHT_OPS_PE_DURATION_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 2, 1, value) - -/* Bit 3 Group Addressed BU indication limit*/ -#define WMI_EHT_OPS_GROUP_ADDRESSED_BU_INDICATION_LIMIT_GET(eht_ops) WMI_GET_BITS(eht_ops, 3, 1) -#define WMI_EHT_OPS_GROUP_ADDRESSED_BU_INDICATION_LIMIT_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 3, 1, value) - -/* Bit 4~5 Group Addressed BU indication Exponent */ -#define WMI_EHT_OPS_GROUP_ADDRESSED_BU_INDICATION_EXPONENT_GET(eht_ops) WMI_GET_BITS(eht_ops, 4, 2) -#define WMI_EHT_OPS_GROUP_ADDRESSED_BU_INDICATION_EXPONENT_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 4, 2, value) - -/* Bit 6 is for MCS15. If bit6 is 1 then we disable mcs15 */ -#define WMI_EHT_OPS_MCS15_DISABLE_GET(eht_ops) WMI_GET_BITS(eht_ops, 6, 1) -#define WMI_EHT_OPS_MCS15_DISABLE_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 6, 1, value) - -/* Bit 7: reserved */ -/****** End of 11BE EHT Operation Parameters field ******/ - -/****** 11BN UHR Operation Parameters field ******/ -/* Bit 0 UHR Operation Information Present */ -#define WMI_UHR_OPS_INFORMATION_PRESENT_GET(uhr_ops) \ - WMI_GET_BITS(uhr_ops, 0, 1) -#define WMI_UHR_OPS_INFORMATION_PRESENT_SET(uhr_ops, value) \ - WMI_SET_BITS(uhr_ops, 0, 1, value) - -/* Bit 1 DPS Enabled */ -#define WMI_UHR_OPS_DPS_ENABLED_GET(uhr_ops) \ - WMI_GET_BITS(uhr_ops, 1, 1) -#define WMI_UHR_OPS_DPS_ENABLED_SET(uhr_ops, value) \ - WMI_SET_BITS(uhr_ops, 1, 1, value) - -/* Bit 2 NPCA Enabled */ -#define WMI_UHR_OPS_NPCA_ENABLED_GET(uhr_ops) \ - WMI_GET_BITS(uhr_ops, 2, 1) -#define WMI_UHR_OPS_NPCA_ENABLED_SET(uhr_ops, value) \ - WMI_SET_BITS(uhr_ops, 2, 1, value) - -/* Bit 3 DBE Enabled */ -#define WMI_UHR_OPS_DBE_ENABLED_GET(uhr_ops) \ - WMI_GET_BITS(uhr_ops, 3, 1) -#define WMI_UHR_OPS_DBE_ENABLED_SET(uhr_ops, value) \ - WMI_SET_BITS(uhr_ops, 3, 1, value) - -/* Bit 4 P-EDCA Enabled */ -#define WMI_UHR_OPS_PEDCA_ENABLED_GET(uhr_ops) \ - WMI_GET_BITS(uhr_ops, 4, 1) -#define WMI_UHR_OPS_PEDCA_ENABLED_SET(uhr_ops, value) \ - WMI_SET_BITS(uhr_ops, 4, 1, value) - -/* Bit 5~7 DBE Bandwidth */ -#define WMI_UHR_OPS_DBE_BANDWIDTH_GET(uhr_ops) \ - WMI_GET_BITS(uhr_ops, 5, 3) -#define WMI_UHR_OPS_DBE_BANDWIDTH_SET(uhr_ops, value) \ - WMI_SET_BITS(uhr_ops, 5, 3, value) - -/* Bit 8~15: reserved */ -/****** End of 11BN UHR Operation Parameters field ******/ +/****** End of 11BE EHT OPS Information field ******/ typedef struct { /** TLV tag and len; tag equals @@ -50667,12 +44799,7 @@ typedef struct { A_UINT32 correlation_info_2; /* Bits 1:0: TX status (if any); values defined in enum * WMI_FRAME_TX_STATUS - * Bits 28:2: reserved (set to 0x0) - * Bit 29: frame sequence control valid flag: - * The frame_seq_ctrl word / bitfields in - * wmi_peer_cfr_capture_event_fixed_param must be ignored - * unless this flag is set. - * Bit 30: PS failed flag + * Bits 30:2: reserved (set to 0x0) * Bit 31: Status of the CFR capture of the peer * 1 (True) - Successful; 0 (False) - Not successful */ @@ -50750,41 +44877,8 @@ typedef struct { * Bits 16:31 reserved */ A_UINT32 mcs_gi_info; - - /* - * 802.11 Sequence Control field from the transmitted frame. - * Added for enhanced CFR correlation. - * - * Bits 0:3 Fragment number - * Bits 4:15 Sequence number - * Bits 16:31 Reserved (set to 0) - * - * Value is 0 if not available. - * - * NOTE: This field is appended for backward compatibility. - * Older hosts will ignore this field as they parse based on - * their known structure size. - */ - A_UINT32 frame_seq_ctrl; } wmi_peer_cfr_capture_event_fixed_param; -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX 0x00000003 -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX_S 0 - -/* bits 28:2 are reserved */ - -/* frame_seq_ctrl field is valid */ -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_FRAME_SEQ_VALID 0x20000000 -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_FRAME_SEQ_VALID_S 29 - -/* Failed to capture CFR as peer is in power save mode */ -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_PS_FAILED 0x40000000 -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_PS_FAILED_S 30 - -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK 0x80000000 -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK_S 31 - - #define WMI_CFR_MCS_GET(mcs_gi_info) \ WMI_GET_BITS(mcs_gi_info, 0, 8) @@ -50797,213 +44891,6 @@ typedef struct { #define WMI_CFR_GI_TYPE_SET(mcs_gi_info, value) \ WMI_SET_BITS(mcs_gi_info, 8, 8, value) -/* Macros to get/set fragment number from frame_seq_ctrl field */ -#define WMI_CFR_FRAME_FRAG_NUM_GET(frame_seq_ctrl) \ - WMI_GET_BITS(frame_seq_ctrl, 0, 4) -#define WMI_CFR_FRAME_FRAG_NUM_SET(frame_seq_ctrl, value) \ - WMI_SET_BITS(frame_seq_ctrl, 0, 4, value) - -/* Macros to get/set sequence number from frame_seq_ctrl field */ -#define WMI_CFR_FRAME_SEQ_NUM_GET(frame_seq_ctrl) \ - WMI_GET_BITS(frame_seq_ctrl, 4, 12) -#define WMI_CFR_FRAME_SEQ_NUM_SET(frame_seq_ctrl, value) \ - WMI_SET_BITS(frame_seq_ctrl, 4, 12, value) - -/** - * CFR capture fix agc gain status codes - * These values are sent to host in wmi_cfr_capture_filter_resp_event - */ -typedef enum { - /** Configuration successful */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_STATUS_SUCCESS = 0, - - /** RX AGC Gain index out of range */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_INDEX_OUT_OF_RANGE = 1, - - /** Fixed AGC not supported in current PHY mode */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_PHYMODE_REJECT = 2, - - /** Failed to disable Scan */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_SCAN_DISABLE_FAILED = 3, - - /** Failed to disable ANI */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_ANI_DISABLE_FAILED = 4, - - /** AGC control is already owned by another module */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_AGC_CONFLICT = 5, - - /** Another CFR/AGC session is in progress */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_SESSION_BUSY = 6, -} wmi_cfr_capture_fix_agc_gain_status_t; - -typedef struct { - /* Info of the CFR capture fix AGC gain configuration based on wmi_cfr_capture_fix_agc_gain_status_t */ - A_UINT32 tlv_header; - - /* wmi_cfr_capture_fix_agc_gain_status_t */ - A_UINT32 status; - - /* RX agc gain index for cfr capture in HW */ - A_UINT32 cfr_agc_gain_index; -} wmi_cfr_capture_fix_agc_gain_info; - -/** - * CFR capture filter command response status codes - * These values are sent to host in wmi_cfr_capture_filter_resp_event - */ -typedef enum { - /** Configuration successful */ - WMI_CFR_CAPTURE_FILTER_STATUS_SUCCESS = 0, - - /** Channel not specified for unassoc mode */ - WMI_CFR_CAPTURE_FILTER_STATUS_NO_CHANNEL = 1, - - /** Invalid MAC ID */ - WMI_CFR_CAPTURE_FILTER_STATUS_INVALID_MAC_ID = 2, - - /** OCS channel request failed */ - WMI_CFR_CAPTURE_FILTER_STATUS_OCS_FAILED = 3, - - /** vdev not found */ - WMI_CFR_CAPTURE_FILTER_STATUS_NO_VDEV = 4, - - /** Invalid param */ - WMI_CFR_CAPTURE_FILTER_STATUS_INVALID_PARAM = 5, -} wmi_cfr_capture_filter_status_t; - -typedef struct { - A_UINT32 tlv_header; - /* Status of the CFR capture filter configuration based on wmi_cfr_capture_filter_status_t */ - A_UINT32 status; /* wmi_cfr_capture_filter_status_t */ - A_UINT32 pdev_id; - /* - * Fields for peer CFR capture support - - * These fields are ONLY populated for peer capture responses. - * For filter capture responses, these remain 0. - */ - A_UINT32 vdev_id; /* VDEV ID (0 for filter capture) */ - wmi_mac_addr mac_addr; /* Peer MAC address (all zeros for filter capture) */ - A_UINT32 request; /* WMI_PEER_CFR_CAPTURE_ENABLE/DISABLE (0 for filter capture) */ -} wmi_cfr_capture_filter_resp_event_fixed_param; - - -/* max beacon bmiss bitmask array size, in 32-bit words */ -#define WMI_MAX_BCN_BMISS_HISTORY_LENGTH 8 - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_beacon_stats */ - A_UINT32 vdev_id; /* ID of the vdev these beacon stats are from */ - /* length: - * Number of A_UINT32 elements within the bmiss_bitmask array which - * contain valid data. - * Array elements beyond this limit should be ignored. - */ - A_UINT32 length; - /* bmiss_bitmask: - * Beacon miss bitmask indicating which beacons got missed from up to - * the last 255 expected beacons (32*8 bits). - * Only bmiss_bitmask[0] through bmiss_bitmask[length-1] (inclusive) - * contain valid data. - */ - A_UINT32 bmiss_bitmask[WMI_MAX_BCN_BMISS_HISTORY_LENGTH]; -} wmi_vdev_beacon_stats; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_qdata_congestion_stats */ - A_UINT32 vdev_id; /* ID of the vdev these congestion stats are from */ - /* cca_busy_time: - * Number of milliseconds during which CCA is busy, - * out of total time spent on the channel - */ - A_UINT32 cca_busy_time; - /* on_time: - * Total time in milliseconds for which we were on the channel - * and monitored - */ - A_UINT32 on_time; -} wmi_vdev_congestion_stats; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_data_stats */ - A_UINT32 vdev_id; /* ID of the vdev these data stats are from */ - /* Set of TX MCS counters for data PPDUs */ - A_UINT32 tx_mcs_data_ppdu[WMI_ENHANCE_STATS_MAX_MCS_COUNTERS]; - /* Set of TX BW counters for data PPDUs */ - A_UINT32 tx_bw_data_ppdu[WMI_STATS_EXT_EVENT_VDEV_EXT_BW_COUNTERS_MAX]; - /* Set of RX MCS counters for data PPDUs */ - A_UINT32 rx_mcs_data_ppdu[WMI_ENHANCE_STATS_MAX_MCS_COUNTERS]; - /* Set of RX BW counters for data PPDUs */ - A_UINT32 rx_bw_data_ppdu[WMI_STATS_EXT_EVENT_VDEV_EXT_BW_COUNTERS_MAX]; -} wmi_vdev_data_stats; - - -#define WMI_EM_PCIE_MAX_CHIP 4 -#define WMI_EM_PCIE_MAX_NUM_MAC 3 - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_em_pcie_stats */ - A_UINT32 is_cumac; /* set to '1' if SoC has CUMAC, else set to '0' */ - A_UINT32 enable; /* set to '1' if feature enable, else set to '0' */ - /* config_type: - * feature configuration type (holds a wmi_pcie_config_type_e value) - */ - A_UINT32 config_type; - /* mlo_partner_chip_bw: - * MLO partner chip BW information, represented as a FW-internal BW enum - * (Thus, this field is intended only for interactive debugging, and not - * for interpretation by the host SW.) - */ - A_UINT32 mlo_partner_bw[WMI_EM_PCIE_MAX_CHIP]; - /* mlo_partner_nss: MLO partner chip NSS information */ - A_UINT32 mlo_partner_nss[WMI_EM_PCIE_MAX_CHIP]; - /* pdev_bw: - * Per PDEV BW, represented as a FW-internal BW enum - * (Thus, this field is intended only for interactive debugging, and not - * for interpretation by the host SW.) - */ - A_UINT32 pdev_bw[WMI_EM_PCIE_MAX_NUM_MAC]; - A_UINT32 curr_pcie_gen; /* current PCIe generation number */ - A_UINT32 curr_pcie_lanes; /* current number of PCIe lanes */ - A_UINT32 pending_pcie_gen; /* pending PCIe generation number */ - A_UINT32 pending_pcie_lanes; /* pending number of PCIe lanes */ -} wmi_em_pcie_stats; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_em_dcvs_stats */ - A_UINT32 num_mac; /* Number of active MAC */ - /* DCVS feature config (holds a wmi_dcvs_config_e value) */ - A_UINT32 dcvs_cfg; - A_UINT32 is_cumac; /* set to '1' if SoC has CUMAC, else set to '0' */ - /* pdev_curr_bw: - * Per PDEV BW, represented as a FW-internal BW enum - * (Thus, this field is intended only for interactive debugging, and not - * for interpretation by the host SW.) - */ - A_UINT32 pdev_curr_bw[WMI_EM_PCIE_MAX_NUM_MAC]; - /* pdev_sla_status: - * SLA active status per pdev. - * set to '1' if SLA connection is active per pdev, else set to '0' - */ - A_UINT32 pdev_sla_status[WMI_EM_PCIE_MAX_NUM_MAC]; - A_UINT32 ofdma_ul_user_limit; /* OFDMA UL user limit for SVS entry */ - A_UINT32 ofdma_dl_user_limit; /* OFDMA DL user limit for SVS entry */ - /* set to '1' if OFDMA user limit is applied, else set to '0' */ - A_UINT32 is_ofdma_limit_applied; - A_UINT32 cv_corr_limit; /* CV corr limit for SVS entry */ - /* set to '1' if cv corr limit is applied, else set to '0' */ - A_UINT32 is_cv_corr_limit_applied; - /* set to '1' if mu sniffer limit is applied, else set to '0' */ - A_UINT32 is_mu_sniff_limit_applied[WMI_EM_PCIE_MAX_NUM_MAC]; - A_UINT32 pending_dcvs_vote; /* pending vote level (0-SVS, 1-NOM) */ - /* pending DCVS BW, represented as a FW-internal BW enum */ - A_UINT32 pending_dcvs_bw; - A_UINT32 pending_dcvs_level_switch; /* pending DCVS level change */ - A_UINT32 current_dcvs_vote; /* current vote level (0-SVS, 1-NOM) */ - /* current, DCVS BW, represented as a FW-internal BW enum */ - A_UINT32 current_dcvs_bw; - A_UINT32 current_dcvs_level_switch; /* current DCVS level change */ -} wmi_em_dcvs_stats; - #define WMI_UNIFIED_CHAIN_PHASE_MASK 0x0000ffff #define WMI_UNIFIED_CHAIN_PHASE_GET(tlv, chain_idx) \ @@ -51081,6 +44968,15 @@ typedef struct { A_UINT32 agc_gain_tbl_index[WMI_MAX_CHAINS/WMI_CFR_AGC_GAIN_CHAINS_PER_U32]; } wmi_peer_cfr_capture_event_phase_fixed_param; +#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK 0x80000000 +#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK_S 31 + +/* Failed to capture CFR as peer is in power save mode */ +#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_PS_FAILED 0x40000000 +#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_PS_FAILED_S 30 + +#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX 0x00000003 +#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX_S 0 /** * wmi_cold_boot_cal_data config flags @@ -51741,21 +45637,6 @@ typedef struct { A_UINT32 data_subtype_filter; } wmi_cfr_filter_group_config; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_cfr_fix_agc_gain_config */ - - /* - * 0 - disable CFR fix agc gain feature - * 1 - enable CFR fix agc gain feature - */ - A_UINT32 cfr_fix_agc_gain_enable; - - /* Forced RX agc gain index for cfr capture, which is set by user in host */ - A_UINT32 force_cfr_agc_gain_index; -} wmi_cfr_capture_fix_agc_gain_config; - - #define WMI_CFR_DIRECTED_FTM_ACK_EN_BIT_POS 0 #define WMI_CFR_ALL_FTM_ACK_EN_BIT_POS 1 #define WMI_CFR_NDPA_NDP_DIRECTED_EN_BIT_POS 2 @@ -51968,17 +45849,6 @@ typedef struct { */ A_UINT32 capture_count; - /* unassoc_capture_config: - * Bit 0: Enable unassociated capture mode - * Bits 31:1 Reserved - */ - A_UINT32 unassoc_capture_config; - - /* Target channel frequency in MHz */ - A_UINT32 unassoc_channel_mhz; - - /* Target channel phy_mode */ - A_UINT32 unassoc_phy_mode; /* WLAN_PHY_MODE */ /* * A variable-length TLV array of wmi_cfr_filter_group_config will * follow this fixed_param TLV @@ -51986,10 +45856,6 @@ typedef struct { */ } wmi_cfr_capture_filter_cmd_fixed_param; -/* CFR Capture macros to get/set the unassociated capture mode enable flag */ -#define WMI_CFR_UNASSOC_CAPTURE_EN_GET(x) WMI_GET_BITS(x, 0, 1) -#define WMI_CFR_UNASSOC_CAPTURE_EN_SET(x, value) WMI_SET_BITS(x, 0, 1, value) - enum wmi_oem_data_evt_cause { WMI_OEM_DATA_EVT_CAUSE_UNSPECIFIED = 0, WMI_OEM_DATA_EVT_CAUSE_CMD_REQ = 1, @@ -52572,17 +46438,6 @@ typedef struct { A_UINT32 force_he_trigger_to_eht_sta; } wmi_wfa_config_ofdma; -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wfa_config_ml */ - A_UINT32 tlv_header; - /* force_add_ext_mld_cap_field - * Possible values from host are: - * 0 default behavior - * 1 add ext mld cap field always when connection - */ - A_UINT32 force_add_ext_mld_cap_field; -} wmi_wfa_config_ml; - typedef struct { /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wfa_config_cmd_fixed_param */ A_UINT32 tlv_header; @@ -52594,7 +46449,6 @@ typedef struct { * wmi_wfa_config_ocv wfa_config_ocv[]; (0 or 1 elements) * wmi_wfa_config_saquery wfa_config_saquery[]; (0 or 1 elements) * wmi_wfa_config_ofdma wfa_config_ofdma[]; (0 or 1 elements) - * wmi_wfa_config_ml wmi_wfa_config_ml[]; (0 or 1 elements) */ } wmi_wfa_config_cmd_fixed_param; @@ -52849,7 +46703,6 @@ typedef enum { WMI_MLO_LINK_FORCE_REASON_TDLS = 4, /* Set force specific links because of 11BE MLO TDLS setup/teardown */ WMI_MLO_LINK_FORCE_REASON_REVERT_FAILURE = 5, /* Set force specific links for revert previous failed due to host reject */ WMI_MLO_LINK_FORCE_REASON_LINK_DELETE = 6, /* Set force specific links because link is deleted from associated link set */ - WMI_MLO_LINK_FORCE_REASON_SINGLE_LINK_EMLSR_OP = 7, /* Set force specific links because single link eMLSR operation */ } WMI_MLO_LINK_FORCE_REASON; #define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_ACTIVE(mlo_flags) \ @@ -53180,30 +47033,11 @@ typedef struct { /* MLD address of AP */ wmi_mac_addr mld_addr; /* any non-zero values of status indicate link reconfig failure. */ - A_UINT32 status; - /* reassoc_if_failure: - * Valid only when status is non-zero. - * FW will do reassociation if link reconfig failure. - */ - A_UINT32 reassoc_if_failure; + A_UINT32 status; + /* valid only when status is non-zero. fw will do reassociation if link reconfig failure */ + A_UINT32 reassoc_if_failure; } wmi_mlo_link_reconfig_complete_fixed_param; -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_ttlm_complete_fixed_param */ - A_UINT32 tlv_header; - /* unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /* MLD address of AP */ - wmi_mac_addr mld_addr; - /* any non-zero values of status indicate link TTLM failure. */ - A_UINT32 status; - /* reassoc_if_failure: - * Valid only when status is non-zero. - * FW will do reassociation if link reconfig failure. - */ - A_UINT32 reassoc_if_failure; -} wmi_mlo_link_ttlm_complete_fixed_param; - #define WMI_TID_TO_LINK_MAP_TID_NUM_GET(_var) WMI_GET_BITS(_var, 0, 5) #define WMI_TID_TO_LINK_MAP_TID_NUM_SET(_var, _val) WMI_SET_BITS(_var, 0, 5, _val) @@ -53380,8 +47214,6 @@ typedef enum { WMI_MAP_SWITCH_TIMER_EXPIRED, /* Expected Duration Expired */ WMI_EXPECTED_DUR_EXPIRED, - /* Expected Duration Near to Expiry */ - WMI_EXPECTED_DUR_NEAR_TO_EXPIRY, } WMI_MLO_TID_TO_LINK_MAP_STATUS; #define WMI_BCAST_T2LM_MAX 16 /* max number of vdevs covered by T2LM stats */ @@ -54073,11 +47905,9 @@ typedef struct { } wmi_sawf_svc_class_disable_cmd_fixed_param; /* Used to store Hop count info for SDWF-Ezmesh scenario based on topology changes */ -#define WMI_SAWF_EZMESH_HOP_COUNT_SVC_ID_GET(svc_class_params) WMI_GET_BITS(svc_class_params, 0, 8) -#define WMI_SAWF_EZMESH_HOP_COUNT_SVC_ID_SET(svc_class_params, value) WMI_SET_BITS(svc_class_params, 0, 8, value) typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sawf_ezmesh_hop_count_cmd_fixed_param */ - A_UINT32 peer_id; /* deprecated field */ + A_UINT32 peer_id; A_UINT32 hop_count; /* delay_bound: * Placeholder for future functionality where delay bound will be directly @@ -54085,15 +47915,6 @@ typedef struct { * (units = ms) */ A_UINT32 delay_bound; - wmi_mac_addr mac_address; /* Mac Address of next BSTA */ - A_UINT32 vdev_id; - union { - struct { - A_UINT32 svc_id:8, - reserved:24; - }; - A_UINT32 svc_class_params; - }; } wmi_sawf_ezmesh_hop_count_cmd_fixed_param; typedef struct { @@ -54728,7 +48549,6 @@ typedef struct { #define WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_2G_RATE_NUM_EXT 8 #define WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_5G_6G_RATE_NUM 24 -#define WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_5G_RATE_NUM_EXT 4 typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_custom_tx_power_per_mcs_cmd_fixed_param */ @@ -54754,22 +48574,22 @@ typedef struct { */ A_UINT32 bitmap_of_2GHz_band[WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_CHAIN_NUM]; - /* 5GHz band has 4 chains and each chain has 24 rates and 4 extended rates. + /* 5GHz band has 4 chains and each chain has 24 rates. * bitmap_of_5GHz_band[0] -> chain 0 bitmap: - * |bit 0|bit 1|......|bit 23| bit 24 |......| bit 27 | - * |rate 0|rate 1|......|rate 23|ext rate 0|......|ext rate 3| + * |bit 0|bit 1|......|bit 23| + * |rate 0|rate 1|......|rate 23| * * bitmap_of_5GHz_band[1] -> chain 1 bitmap: - * |bit 0|bit 1|......|bit 23| bit 24 |......| bit 27 | - * |rate 0|rate 1|......|rate 23|ext rate 0|......|ext rate 3| + * |bit 0|bit 1|......|bit 23| + * |rate 0|rate 1|......|rate 23| * * bitmap_of_5GHz_band[2] -> chain 2 bitmap: - * |bit 0|bit 1|......|bit 23| bit 24 |......| bit 27 | - * |rate 0|rate 1|......|rate 23|ext rate 0|......|ext rate 3| + * |bit 0|bit 1|......|bit 23| + * |rate 0|rate 1|......|rate 23| * * bitmap_of_5GHz_band[3] -> chain 3 bitmap: - * |bit 0|bit 1|......|bit 23| bit 24 |......| bit 27 | - * |rate 0|rate 1|......|rate 23|ext rate 0|......|ext rate 3| + * |bit 0|bit 1|......|bit 23| + * |rate 0|rate 1|......|rate 23| */ A_UINT32 bitmap_of_5GHz_band[WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_CHAIN_NUM]; @@ -55290,7 +49110,6 @@ typedef enum _WMI_VDEV_PAUSE_TYPE WMI_VDEV_PAUSE_TYPE_MLO_LINK = 1, WMI_VDEV_PAUSE_TYPE_TX = 2, WMI_VDEV_PAUSE_TYPE_TX_DATA = 3, - WMI_VDEV_PAUSE_TYPE_TX_RX = 4, } WMI_VDEV_PAUSE_TYPE; typedef struct { @@ -55890,9 +49709,7 @@ typedef struct { #define WMI_PEER_ACTIVE_TRAFFIC_TYPE_WEB_BROWSING_S 19 #define WMI_PEER_ACTIVE_TRAFFIC_TYPE_APERIODIC_BURST_TRAFFIC_1_M 0x00100000 #define WMI_PEER_ACTIVE_TRAFFIC_TYPE_APERIODIC_BURST_TRAFFIC_1_S 20 -#define WMI_PEER_ACTIVE_TRAFFIC_TYPE_LIVECAST_M 0x00200000 -#define WMI_PEER_ACTIVE_TRAFFIC_TYPE_LIVECAST_S 21 -/* bits 22-31 are reserved for new interactive traffic types */ +/* bits 21-31 are reserved for new interactive traffic types */ typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_active_traffic_map_cmd_fixed_param */ @@ -55998,10 +49815,7 @@ typedef struct { } wmi_mlo_link_del_param; typedef enum { - WMI_EVENT_POWER_BOOST_START_INFERENCING = 0, - /* alias */ - WMI_EVENT_POWER_BOOST_START_TRAINING = - WMI_EVENT_POWER_BOOST_START_INFERENCING, + WMI_EVENT_POWER_BOOST_START_TRAINING = 0, WMI_EVENT_POWER_BOOST_ABORT, WMI_EVENT_POWER_BOOST_COMPLETE, @@ -56011,13 +49825,9 @@ typedef enum { typedef enum { WMI_PDEV_POWER_BOOST_TS_FIRST_PASS = 0, WMI_PDEV_POWER_BOOST_TS_SECOND_PASS, - WMI_PDEV_POWER_BOOST_TS_THIRD_PASS, - WMI_PDEV_POWER_BOOST_TS_FOURTH_PASS, WMI_PDEV_POWER_BOOST_TS_MAX } wmi_pdev_power_boost_training_stage; -typedef wmi_pdev_power_boost_training_stage - wmi_pdev_power_boost_inferencing_stage; /* alias */ typedef struct { /* WMITLV_TAG_STRUC_wmi_pdev_power_boost_event_fixed_param */ @@ -56026,14 +49836,11 @@ typedef struct { A_UINT32 pdev_id; /* enum wmi_pdev_power_boost_event_type to update the power boost status */ A_UINT32 status; - /* inferencing_stage: - * The inferencing stage for which the I/Q samples are updated in DDR. - * This field holds a wmi_pdev_power_boost_inferencing_stage value. + /* training_stage: + * The training stage for which the I/Q samples are updated in DDR. + * This field holds a wmi_pdev_power_boost_training_stage value. */ - union { - A_UINT32 training_stage; /* deprecated name */ - A_UINT32 inferencing_stage; /* preferred name */ - }; + A_UINT32 training_stage; /* MCS value for which the current DPD training has been done */ A_UINT32 mcs; /* bandwidth: @@ -56058,16 +49865,6 @@ typedef struct { * in units of KB */ A_UINT32 size_kb; - /* tx_pwr: - * TX POWER of ANN PBT INFERENCING PKT (dBm units) - */ - A_INT32 tx_pwr; - /* tx_chain_idx: - * CHAIN INDEX where WMI is sent to HOST to start inferencing - */ - A_UINT32 tx_chain_idx; - /* req_id: to distinguish pdev_power_boost event instances */ - A_UINT32 req_id; } wmi_pdev_power_boost_event_fixed_param; typedef enum { @@ -56085,14 +49882,8 @@ typedef struct { A_UINT32 pdev_id; /* enum wmi_pdev_power_boost_cmd_type to update the power boost status */ A_UINT32 status; - /* - * wmi_pdev_power_boost_inferencing_stage value to indicate - * inferencing stage - */ - union { - A_UINT32 training_stage; /* deprecated name */ - A_UINT32 inferencing_stage; /* preferred name */ - }; + /* wmi_pdev_power_boost_training_stage value to indicate training stage */ + A_UINT32 training_stage; /* MCS value for which the Power Boost training has been done */ A_UINT32 mcs; /* Bandwidth in Mhz for which the Power Boost training has been done */ @@ -56120,8 +49911,6 @@ typedef struct { * training, in units of 1/4 (0.25dBm) steps. */ A_INT32 tx_mask_margin; - /* req_id: to distinguish pdev_power_boost cmd instances */ - A_UINT32 req_id; } wmi_pdev_power_boost_cmd_fixed_param; typedef struct { @@ -56142,35 +49931,6 @@ typedef struct { A_UINT32 tlv_header; } wmi_get_scan_cache_result_cmd_fixed_param; -typedef enum { - WMI_PLIM_DIRECTION_NONE = 0, - WMI_PLIM_DIRECTION_INCREASE, - WMI_PLIM_DIRECTION_DECREASE -} wmi_plim_direction_type; - -typedef struct { - /* WMITLV_TAG_STRUC_wmi_set_modify_tx_plim_cmd_fixed_param */ - A_UINT32 tlv_header; - /* Requested level for future enhancement, default value shall be 1 */ - A_UINT32 multiplier; - /* takes values from enum wmi_plim_direction_type */ - A_UINT32 direction; -} wmi_set_modify_tx_plim_cmd_fixed_param; - -typedef struct { - /* WMITLV_TAG_STRUC_wmi_get_avg_tx_power_cmd_fixed_param */ - A_UINT32 tlv_header; - /* Current active DSI (device state index) */ - A_UINT32 dsi_id; -} wmi_get_avg_tx_power_cmd_fixed_param; - -typedef struct { - /* WMITLV_TAG_STRUC_wmi_get_tx_power_calling_cmd_fixed_param */ - A_UINT32 tlv_header; - /* DSI index for which power limit info is to be fetched */ - A_UINT32 dsi_id; -} wmi_get_tx_power_calling_cmd_fixed_param; - /* Element ID 61 (HT Operation) is present (see HT 7.3.2) */ #define WIFI_CACHED_SCAN_RESULT_FLAGS_HT_OPS_PRESENT_GET(flags) WMI_GET_BITS(flags, 0, 1) #define WIFI_CACHED_SCAN_RESULT_FLAGS_HT_OPS_PRESENT_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) @@ -56193,7 +49953,7 @@ typedef struct { typedef struct { - A_UINT32 width; /* wmi_channel_width */ + wmi_channel_width width; A_UINT32 center_frequency0; /* Frequency value in MHz */ A_UINT32 center_frequency1; /* Frequency value in MHz */ A_UINT32 primary_frequency; /* Frequency value in MHz */ @@ -56232,66 +49992,6 @@ typedef struct { */ } wmi_scan_cache_result_fixed_param; -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_modify_tx_plim_event_fixed_param */ - - A_UINT32 status; /* 0 = success, 1 = failure */ -} wmi_modify_tx_plim_event_fixed_param; - -typedef enum { - /* Invalid Chain combination */ - WMI_POWER_REGION_INVALID = 0, - - /* Avg. tx power <= PowerLimit-backoff */ - WMI_POWER_REGION_LOW = 1, - - /* PowerLimit-backoff < Avg. tx power <= PowerLimit */ - WMI_POWER_REGION_MEDIUM = 2, - - /* PowerLimit < Avg. tx power <= PowerLimit+Boost */ - WMI_POWER_REGION_HIGH = 3, - - /* Avg. tx power > PowerLimit+Boost */ - WMI_POWER_REGION_EXTRA_HIGH = 4, - -} wmi_phyrf_tas_chain_power_region_type; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_avg_tx_power_region_per_antenna_chain */ - /* Valid chain number for which chain_power_region is filled */ - A_UINT32 chain_no; - A_UINT32 chain_operating_band; /* 0: 2GHz, 1: 5GHz, 2: 6GHz */ - /* takes values from enum wmi_phyrf_tas_chain_power_region_type */ - A_UINT32 chain_power_region; -} wmi_avg_tx_power_region_per_antenna_chain; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_avg_tx_power_event_fixed_param */ - A_UINT32 status; /* 0 = success, 1 = failure */ - /* Exposure window over which TX power is averaged */ - A_UINT32 time_window_in_sec; - /* The below TLVs follow this TLV - * struct wmi_avg_tx_power_region_per_antenna_chain[]; - */ -} wmi_avg_tx_power_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_power_per_antenna_chain */ - A_UINT32 chain_no; /* Valid chain number for which power is filled */ - A_UINT32 chain_operating_band; /* 0: 2GHz, 1: 5GHz, 2: 6GHz */ - A_INT32 power; /* Power limit in units of 0.25 dBm */ -} wmi_tx_power_per_antenna_chain; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_plimit_table_event_fixed_param */ - A_UINT32 status; /* 0 = success, 1 = failure */ - A_UINT32 dsi_id; /* DSI index for which below entries are filled */ - /* The below TLVs follow this TLV - * struct wmi_tx_power_per_antenna_chain[]; - */ -} wmi_plimit_table_event_fixed_param; - - #define WMI_POWER_BOOST_CAPABILITIES_PHY_ID_GET(word32) WMI_GET_BITS(word32, 0, 4) #define WMI_POWER_BOOST_CAPABILITIES_PHY_ID_SET(word32, value) WMI_SET_BITS(word32, 0, 4, value) #define WMI_POWER_BOOST_CAPABILITIES_POWER_BOOST_ENABLE_GET(word32) WMI_GET_BITS(word32, 4, 1) @@ -56359,9 +50059,8 @@ typedef struct { }; /* * The below TLVs follow this TLV in the WMI_VDEV_VBSS_CONFIG_CMDID msg: - * - wmi_vdev_vbss_peer_pn_info[]; * - wmi_vdev_vbss_peer_sn_info[]; - * - wmi_vdev_vbss_peer_dyn_info; + * - wmi_vdev_vbss_peer_pn_info[]; */ } wmi_vdev_vbss_config_cmd_fixed_param; @@ -56394,62 +50093,15 @@ typedef struct { ssn: 16; }; }; + /* The below TLVs follow this TLV in the WMI_VDEV_VBSS_CONFIG_EVENTID msg: + * - A_UINT32 scan_freq_list[]; + * - wmi_vdev_vbss_config_event_fixed_param[]; + */ } wmi_vdev_vbss_peer_sn_info; -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_vbss_peer_dyn_info */ - union { - A_UINT32 peer_dyn_info1_word32; - struct { - /** 15:0 omi - * 31:16 eht_omi - */ - A_UINT32 - omi: 16, - eht_omi: 16; - }; - }; - union { - A_UINT32 peer_dyn_info2_word32; - struct { - /** 0:0 pm - * 1:1 emlsr - * 17:2 padding_delay - * 26:18 transition_delay - * 30:27 transition_timeout - * 31 Reserved - */ - A_UINT32 - pm : 1, - emlsr : 1, - padding_delay_us : 16, - transition_delay_us : 9, - transition_timeout_us: 4, - rsvd1 : 1; - }; - }; - union { - A_UINT32 peer_dyn_info3_word32; - struct { - /** 13:0 link_bitmap - * 31:15 Reserved - */ - A_UINT32 - link_bitmap: 14, - rsvd2 : 18; - }; - }; -} wmi_vdev_vbss_peer_dyn_info; - typedef enum { - WMI_VBSS_UNICAST_PN_INFO = 1, - WMI_VBSS_MULTICAST_PN_INFO = 2, -} wmi_vbss_pn_ctxt_id; - -typedef enum { - WMI_VBSS_GET_PEER_CONTEXT = 1, - WMI_VBSS_SET_PEER_CONTEXT = 2, - WMI_VBSS_RX_SUSPEND_PEER_CONTEXT = 3, + WMI_VBSS_GET_PEER_CONTEXT = 0x1, + WMI_VBSS_SET_PEER_CONTEXT = 0x2, } wmi_vbss_action; #define WMI_VDEV_VBSS_GET_ACTION(action) WMI_GET_BITS(action, 0, 4) @@ -56464,30 +50116,6 @@ typedef enum { #define WMI_VDEV_VBSS_SN_INFO_GET_SSN(tid_num_ssn) WMI_GET_BITS(tid_num_ssn, 16, 16) #define WMI_VDEV_VBSS_SN_INFO_SET_SSN(action, value) WMI_SET_BITS(tid_num_ssn, 16, 16, value) -#define WMI_VDEV_VBSS_DYN_INFO_GET_OMI(peer_dyn_info1) WMI_GET_BITS(omi, 0, 16) -#define WMI_VDEV_VBSS_DYN_INFO_SET_OMI(peer_dyn_info1, value) WMI_SET_BITS(omi, 0, 16, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_EHT_OMI(peer_dyn_info1) WMI_GET_BITS(eht_omi, 16, 16) -#define WMI_VDEV_VBSS_DYN_INFO_SET_EHT_OMI(peer_dyn_info1, value) WMI_SET_BITS(eht_omi, 16, 16, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_PM(peer_dyn_info2) WMI_GET_BITS(pm, 0, 1) -#define WMI_VDEV_VBSS_DYN_INFO_SET_PM(peer_dyn_info2, value) WMI_SET_BITS(pm, 0, 1, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_EMLSR(peer_dyn_info2) WMI_GET_BITS(emlsr, 1, 1) -#define WMI_VDEV_VBSS_DYN_INFO_SET_EMLSR(peer_dyn_info2, value) WMI_SET_BITS(emlsr, 1, 1, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_PADDING_DELAY(peer_dyn_info2) WMI_GET_BITS(padding_delay, 2, 16) -#define WMI_VDEV_VBSS_DYN_INFO_SET_PADDING_DELAY(peer_dyn_info2, value) WMI_SET_BITS(padding_delay, 2, 16, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_TRANSITION_DELAY(peer_dyn_info2) WMI_GET_BITS(transition_delay, 18, 9) -#define WMI_VDEV_VBSS_DYN_INFO_SET_TRANSITION_DELAY(peer_dyn_info2, value) WMI_SET_BITS(transition_delay, 18, 9, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_TRANSITION_TIMEOUT(peer_dyn_info2) WMI_GET_BITS(transition_timeout, 27, 4) -#define WMI_VDEV_VBSS_DYN_INFO_SET_TRANSITION_TIMEOUT(peer_dyn_info2, value) WMI_SET_BITS(transition_timeout, 27, 4, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_LINK_BITMAP(peer_dyn_info3) WMI_GET_BITS(link_bitmap, 0, 14) -#define WMI_VDEV_VBSS_DYN_INFO_SET_LINK_BITMAP(peer_dyn_info3, value) WMI_SET_BITS(link_bitmap, 0, 14, value) - typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_vbss_config_event_fixed_param */ @@ -56502,1790 +50130,6 @@ typedef struct { } wmi_vdev_vbss_config_event_fixed_param; -typedef enum { - /* Channel bandwidth based semi static PCIe config */ - WMI_PCIE_CONFIG_TYPE_CHANNEL_BANDWIDTH, - /* Force a specific PCIe config */ - WMI_PCIE_CONFIG_TYPE_FORCED_STATIC, -} wmi_pcie_config_type_e; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_energy_mgmt_pcie_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /** enable or disable PCIe config */ - A_UINT32 enable; - /* PCIe config type (holds a wmi_pcie_config_type_e value) */ - A_UINT32 config_type; - /** pcie_gen: pcie generation to be used - * pcie_lane:pcie lane config (lane number) to be used - */ - A_UINT32 pcie_gen; - A_UINT32 pcie_lane; -} wmi_energy_mgmt_pcie_config_cmd_fixed_param; - -typedef enum { - WMI_PCIE_LPM_CONFIG_TYPE_UNKNOWN, - WMI_PCIE_LPM_CONFIG_TYPE_L0S, - WMI_PCIE_LPM_CONFIG_TYPE_L1, - WMI_PCIE_LPM_CONFIG_TYPE_L0S_L1, -} wmi_pcie_lpm_config_type_e; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_energy_mgmt_pcie_lpm_cmd_fixed_param */ - A_UINT32 tlv_header; - /** enable or disable PCIe LPM */ - A_UINT32 enable; - /** PCIe LPM config type */ - A_UINT32 config_type; /* holds a wmi_pcie_lpm_config_type_e value */ -} wmi_energy_mgmt_pcie_lpm_cmd_fixed_param; - -typedef enum { - WMI_DCVS_ENABLE, /* Enable clock and voltage scaling */ - WMI_DCVS_DISABLE, /* Disable clock and voltage scaling */ - WMI_DCVS_CLOCK_SCALING_ONLY, /* Enable only clock scaling */ -} wmi_dcvs_config_e; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_energy_mgmt_dcvs_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /** DCVS config - holds a wmi_dcvs_config_e value */ - A_UINT32 config; -} wmi_energy_mgmt_dcvs_config_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_energy_mgmt_dps_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /** enable or disable DPS config */ - A_UINT32 enable; - /** PDEV identifier */ - A_UINT32 pdev_id; - /** Channel to be used in DPS Low cap mode, freq must match the primary home chan freq */ - wmi_channel low_cap_channel; - /** Tx chainmask to be used in DPS Low cap mode */ - A_UINT32 low_cap_tx_chainmask; - /** Rx chainmask to be used in DPS Low cap mode */ - A_UINT32 low_cap_rx_chainmask; - /** Mbps throughput after which DPS will be exited and notified to Host */ - A_UINT32 exit_thpt_thrsld_mbps; - /** number of wakeups per second after which DPS will be exited and notified to Host */ - A_UINT32 exit_wakeup_thrsld_per_second; -} wmi_energy_mgmt_edps_config_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_energy_mgmt_puo_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /** enable or disable DPS config */ - A_UINT32 enable; - /** PDEV identifier */ - A_UINT32 pdev_id; - /** Channel to be used in PUO Low cap mode, freq must match the primary home chan freq */ - wmi_channel low_cap_channel; - /** Tx chainmask to be used in Low cap mode */ - A_UINT32 low_cap_tx_chainmask; - /** Rx chainmask to be used in Low cap mode */ - A_UINT32 low_cap_rx_chainmask; - /** minimum duration required between SP end and SP start to trigger entering to doze state */ - A_UINT32 min_doze_thrsld_in_us; -} wmi_energy_mgmt_puo_config_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_energy_mgmt_eco_mode_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /** enable or disable DPS config */ - A_UINT32 enable; - /** PDEV identifier */ - A_UINT32 pdev_id; -} wmi_energy_mgmt_eco_mode_config_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param */ - A_UINT32 pdev_id; /** pdev ID set by the command */ -} wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_ac_info */ - A_UINT32 vdev_id; - /** pending_packets_per_ac: - * number of MSDUs pending in MSDU and MPDU queues for the Access Category - * for the specific vdev - */ - A_UINT32 pending_packets_per_ac[WLAN_MAX_AC]; -} wmi_vdev_ac_info; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param */ - A_UINT32 pdev_id; /* pdev ID set by the command */ - /* The TLVs for the 4 AC follows with the vdev_id : - * wmi_vdev_ac_info vdev_ac_info[]; wmi_vdev_ac_info for BE/BK/VI/VO - */ -} wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param; - -typedef enum { - WMI_PDEV_SET_TX_CHAINMASK_SUCCESS = 0, - WMI_PDEV_SET_TX_CHAINMASK_FAIL_INVALID_CHAINMASK, -} WMI_PDEV_SET_TX_CHAINMASK_COMP_STATUS_TYPE; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_tx_chainmask_comp_event_fixed_param */ - /** pdev_id for identifying the MAC - */ - A_UINT32 pdev_id; - /* - * status type WMI_PDEV_SET_TX_CHAINMASK_COMP_STATUS_TYPE - */ - A_UINT32 status; -} wmi_pdev_set_tx_chainmask_comp_event_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - /** TX RX byte count value, in KB units */ - A_UINT32 data_threshold; - /** duration of traffic monitoring, in unit of sec */ - A_UINT32 traffic_monitoring_time; -} wmi_vdev_traffic_monitoring_cmd_fixed_param; - -typedef enum { - WMI_DPS_ASSISTING_ROLE_DISABLE, /* Disable - DPS: AP Assisting role */ - WMI_DPS_ASSISTING_ROLE_ENABLE, /* Enable - DPS: AP Assisting role */ -} wmi_dps_assisting_role_e; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - /** holds a wmi_dps_assisting_role_e value */ - A_UINT32 config; -} wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; */ - A_UINT32 tlv_header; - - /* content_type: - * This OEM-defined value specifies what kind of Energy Management - * data is present in the opaque "data" bytestream TLV. - */ - A_UINT32 content_type; - /* num bytes to distinguish data bytes from alignment-padding bytes */ - A_UINT32 num_bytes_valid; -} wmi_energy_mgmt_oem_data_fixed_param; - -typedef struct { - /** TLV tag and len; */ - A_UINT32 tlv_header; - - /* content_type: - * This OEM-defined value specifies what kind of Energy Management - * data is present in the opaque "data" bytestream TLV. - */ - A_UINT32 content_type; - /* num bytes to distinguish data bytes from alignment-padding bytes */ - A_UINT32 num_bytes_valid; -} wmi_energy_mgmt_oem_data_event_fixed_param; - - -/* WMI evt to indicate FW is ready */ -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_fw_ready_ind_event_fixed_param */ - A_UINT32 tlv_header; -} wmi_fw_ready_ind_event_fixed_param; - -typedef enum { - WMI_DRIVER_MODE_MISSION, - WMI_DRIVER_MODE_FTM, - WMI_DRIVER_MODE_OFF, -} WMI_DRIVER_MODE; - -/** WMI command to indicate the driver mode of operation */ -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_wlan_mode_req_cmd_fixed_param */ - A_UINT32 tlv_header; - /* This indicates driver mode of operation from host */ - A_UINT32 mode; /* refer to WMI_DRIVER_MODE enum */ -} wmi_wlan_mode_req_cmd_fixed_param; - -typedef enum { - WMI_DRIVER_MODE_RESP_SUCCESS, - WMI_DRIVER_MODE_RESP_FAILURE, -} WMI_WLAN_DRIVER_MODE_RESP_STATUS; - -typedef enum { - WMI_DRIVER_FAIL_REASON_UNKNOWN_MODE, - /* In FTM mode, initiate PHY error */ - WMI_DRIVER_FAIL_REASON_FTM_PHY_INIT_ERR, - /* For both MISSION and FTM mode, set power error */ - WMI_DRIVER_FAIL_REASON_POWER_INIT_ERR, - WMI_DRIVER_FAIL_REASON_MODE_OFF_ERR, -} WMI_WLAN_MODE_FAILURE_REASON; - -/* Host/Firmware can get/set the status bits using below macros */ -#define WMI_WLAN_DRIVER_MODE_RESP_STATUS_GET(status) WMI_GET_BITS(status, 0, 16) -#define WMI_WLAN_DRIVER_MODE_RESP_STATUS_SET(status, value) WMI_SET_BITS(status, 0, 16, value) - -#define WMI_WLAN_DRIVER_MODE_RESP_FAILURE_GET(mode) WMI_GET_BITS(mode, 16, 16) -#define WMI_WLAN_DRIVER_MODE_RESP_FAILURE_SET(mode, value) WMI_GET_BITS(mode, 16, 16, value) - -/* WMI evt to acknowledge the driver mode sent by host */ -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_wlan_mode_resp_event_fixed_param */ - A_UINT32 tlv_header; - /* The status word contains the following bitfields: - * bits 15:0 - Indicates whether the FW has accepted - * (WMI_DRIVER_MODE_RESP_SUCCESS) or rejected - * (WMI_DRIVER_MODE_RESP_FAILURE) the driver mode - * specified by the host. - * bits 31:16 - Indicates the reason if the FW has rejected - * the driver mode. - * This field is only relevant if the status is - * WMI_DRIVER_MODE_RESP_FAILURE. - */ - A_UINT32 status; -} wmi_wlan_mode_resp_event_fixed_param; - -/* Optional version for future expansion */ -typedef enum { - WMI_IPA_RING_STATS_EVENT_VERSION1 = 1, - -} WMI_IPA_RING_STATS_EVENT_VERSIONS; - -typedef struct { - A_UINT32 tlv_header; - /* version: - * For future extensions; currently 1 (WMI_IPA_RING_STATS_EVENT_VERSION1) - * Refer to WMI_IPA_RING_STATS_EVENT_VERSIONS. - */ - A_UINT32 version; - A_UINT32 ring_id; -} wmi_ipa_ring_stats_req_cmd_fixed_param; - -/* Per-ring sample (indices and sizes in entries to keep host parsing simple) */ -typedef struct { - A_UINT32 tlv_header; - A_UINT32 ring_id; /* e.g., HAL ring_id or your own enum */ - A_UINT32 hp_idx; /* head pointer index (entry index) */ - A_UINT32 tp_idx; /* tail pointer index (entry index) */ - A_UINT32 free_entries; /* how many entries free */ - A_UINT32 ring_entries; /* total entries */ -} wmi_ipa_ring_stat_entry; - -/* Event fixed params (TLV-safe layout) */ -typedef struct { - A_UINT32 tlv_header; - A_UINT32 version; /* Refer to WMI_RING_STATS_EVENT_VERSIONS */ -} wmi_ipa_ring_stats_conf_event_fixed_param; - - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_dps_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether DPS for this VAP is enabled or disabled - * Bit1 : Mode Update - * This should be set when any of the DPS params needs an update - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* Add the required fields below*/ -} wmi_uhr_ap_dps_params; - -#define WMI_DPS_MODE_TUPLE_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_DPS_MODE_TUPLE_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_DPS_MODE_TUPLE_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_DPS_MODE_TUPLE_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_npca_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether NPCA for this VAP is enabled or disabled - * Bit1 : Mode Update - * This should be set when any of the NPCA params needs an update - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* npca_chan: - * WMI Non-Primary Channel Access channel - * Specifically, this is the "other primary" channel used if the - * "main primary" is occupied by low-bandwidth OBSS traffic. - */ - wmi_channel npca_chan; - /* NPCA punctured bitmap */ - A_UINT32 puncture_20mhz_bitmap; - /* - * Bit0-7 : NPCA Primary Channel - * WMI_NPCA_PRIM_CHAN_GET / WMI_NPCA_PRIM_CHAN_SET - * - * Bit8-11 : NPCA Minium Threshold - * The NPCA minimum duration threshold T, in units of 128 - * us, is T = 512 + NMDT x 128, where NMDT is the field - * value, which yields a minimum of 512 us and a maximum of - * 2432 us. The minimum is chosen to cover at least the - * transmission time of NPCA ICF and ICR exchange plus a - * typical Data and Ack/BA exchange using non-HT or non- - * HT duplicate PPDU format with 6 Mb/s data rate - * WMI_NPCA_AP_CAP_MIN_THRES_GET / _SET - * - * Bit12-17: NPCA Switch Delay - * The time needed by an NPCA STA to switch from the - * BSS primary channel to the NPCA primary channel, - * in units of 4 us. - * WMI_NPCA_AP_CAP_SWITCH_DELAY_GET / _SET - * - * Bit18:23: NPCA Switch Back Delay - * The time needed by an NPCA STA to switch from the - * NPCA primary channel to the BSS primary channel, - * in units of 4 us. - * WMI_NPCA_AP_CAP_SWITCH_BACK_DELAY_GET / _SET - * - * Bit24:25: The Initial NPCA QSRC field indicates the value - * that is used to initialize the EDCAF QSRC[AC] variables - * when an NPCA STA in the BSS switches to NPCA operation. - * WMI_NPCA_AP_CAP_MIN_THRES_GET / _SET - * - * Bit26 : The MOPLEN NPCA field indicates which conditions can be used - * to initiate an NPCA operation. A value of 1 in this field - * indicates that both PHYLEN NPCA operation and MOPLEN NPCA - * operations are permitted in the BSS. - * A value of 0 in this field indicates that only PHYLEN NPCA - * operation is allowed in the BSS. - * WMI_NPCA_AP_CAP_MOPLEN_GET / _SET - * - * Bit27 : The NPCA Disabled Subchannel Bitmap Present field indicates - * whether the NPCA Disabled Subchannel Bitmap field is present. - * This field indicates that the NPCA Disabled Subchannel Bitmap - * field is present. - * WMI_NPCA_AP_CAP_DISABLED_SB_PRESENT_GET / _SET - * - * Bit28-31: Reserved - */ - A_UINT32 npca_cap1; - - /* - * Bit0-15 : The NPCA Disabled Subchannel Bitmap field is a bitmap where - * the lowest numbered bit corresponds to the 20 MHz subchannel - * that lies within the BSS bandwidth and is the lowest in - * frequency of the set of all 20MHz subchannels within the BSS - * bandwidth. Each successive bit in the bitmap corresponds to - * the next higher frequency 20 MHz subchannel. A bit in the - * bitmap that lies within the BSS bandwidth is set to 1 to - * indicate that the corresponding 20MHz subchannel is - * punctured and is set to 0 to indicate that the corresponding - * 20 MHz subchannel is not punctured. A bit in the bitmap that - * falls outside of the BSS bandwidth is reserved. - * This field is present when the value of the NPCA Disabled - * Subchannel Bitmap Field Present field is equal to 1, and - * not present, otherwise. - * WMI_NPCA_AP_CAP_DISABLED_SB_GET / _SET - * - * Bit16-31: Reserved - */ - A_UINT32 npca_cap2; -} wmi_uhr_ap_npca_params; - -#define WMI_NPCA_MODE_TUPLE_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_NPCA_MODE_TUPLE_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_NPCA_MODE_TUPLE_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_NPCA_MODE_TUPLE_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - -#define WMI_NPCA_PRIM_CHAN_GET(_var) WMI_GET_BITS(_var, 0, 8) -#define WMI_NPCA_PRIM_CHAN_SET(_var, _val) WMI_SET_BITS(_var, 0, 8, _val) - -#define WMI_NPCA_AP_CAP_MIN_THRESH_GET(_var) WMI_GET_BITS(_var, 8, 4) -#define WMI_NPCA_AP_CAP_MIN_THRESH_SET(_var, _val) WMI_SET_BITS(_var, 8, 4, _val) - -#define WMI_NPCA_AP_CAP_SWITCH_DELAY_GET(_var) WMI_GET_BITS(_var, 12, 6) -#define WMI_NPCA_AP_CAP_SWITCH_DELAY_SET(_var, _val) WMI_SET_BITS(_var, 12, 6, _val) - -#define WMI_NPCA_AP_CAP_SWITCH_BACK_DELAY_GET(_var) WMI_GET_BITS(_var, 18, 6) -#define WMI_NPCA_AP_CAP_SWITCH_BACK_DELAY_SET(_var, _val) WMI_SET_BITS(_var, 18, 6, _val) - -#define WMI_NPCA_AP_CAP_QSRC_GET(_var) WMI_GET_BITS(_var, 24, 2) -#define WMI_NPCA_AP_CAP_QSRC_SET(_var, _val) WMI_SET_BITS(_var, 24, 2, _val) - -#define WMI_NPCA_AP_CAP_MOPLEN_GET(_var) WMI_GET_BITS(_var, 26, 1) -#define WMI_NPCA_AP_CAP_MOPLEN_SET(_var, _val) WMI_SET_BITS(_var, 26, 1, _val) - -#define WMI_NPCA_AP_CAP_DISABLED_SB_PRESENT_GET(_var) WMI_GET_BITS(_var, 27, 1) -#define WMI_NPCA_AP_CAP_DISABLED_SB_PRESENT_SET(_var, _val) WMI_SET_BITS(_var, 27, 1, _val) - -#define WMI_NPCA_AP_CAP_DISABLED_SB_GET(_var) WMI_GET_BITS(_var, 0, 16) -#define WMI_NPCA_AP_CAP_DISABLED_SB_SET(_var, _val) WMI_SET_BITS(_var, 0, 16, _val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_duo_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether NPCA for this VAP is enabled or disabled - * Bit1 : Mode Update - * This should be set when any of the NPCA params needs an update - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* Add any new required fields below */ -} wmi_uhr_ap_duo_params; - -#define WMI_UHR_AP_DUO_PARAMS_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_UHR_AP_DUO_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_UHR_AP_DUO_PARAMS_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_UHR_AP_DUO_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_pedca_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether NPCA for this VAP is enabled or disabled - * - * Bit1 : Mode Update - * This should be set when any of the NPCA params needs an update - * - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* Add any new required fields below */ -} wmi_uhr_ap_pedca_params; - -#define WMI_UHR_AP_PEDCA_PARAMS_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_UHR_AP_PEDCA_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_UHR_AP_PEDCA_PARAMS_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_UHR_AP_PEDCA_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_dbe_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether NPCA for this VAP is enabled or disabled - * Bit1 : Mode Update - * This should be set when any of the NPCA params needs an update - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* Add any new required fields below */ -} wmi_uhr_ap_dbe_params; - -#define WMI_UHR_AP_DBE_PARAMS_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_UHR_AP_DBE_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_UHR_AP_DBE_PARAMS_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_UHR_AP_DBE_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_puo_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether NPCA for this VAP is enabled or disabled - * Bit1 : Mode Update - * This should be set when any of the NPCA params needs an update - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* Add any new required fields below */ -} wmi_uhr_ap_puo_params; - -#define WMI_UHR_AP_PUO_PARAMS_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_UHR_AP_PUO_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_UHR_AP_PUO_PARAMS_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_UHR_AP_PUO_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_elr_reception_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether NPCA for this VAP is enabled or disabled - * Bit1 : Mode Update - * This should be set when any of the NPCA params needs an update - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* Add any new required fields below */ -} wmi_uhr_ap_elr_reception_params; - -#define WMI_UHR_AP_ELR_RECEPTION_PARAMS_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_UHR_AP_ELR_RECEPTION_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_UHR_AP_ELR_RECEPTION_PARAMS_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_UHR_AP_ELR_RECEPTION_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - - -/* ---------------- Mode bit positions ---------------- */ -typedef enum { - WMI_UHR_AP_MODE_TUP_DPS = 0, - WMI_UHR_AP_MODE_TUP_NPCA = 1, - WMI_UHR_AP_MODE_TUP_DUO = 2, - WMI_UHR_AP_MODE_TUP_PEDCA = 3, - WMI_UHR_AP_MODE_TUP_DBE = 4, - WMI_UHR_AP_MODE_TUP_PUO = 5, - WMI_UHR_AP_MODE_TUP_ELR = 6, - /* Future modes -> 6..23 */ - WMI_UHR_MAX_MODES = 24 -} WMI_UHR_AP_MODE_TUP; - -typedef enum{ - WMI_UHR_AP_MODE_TUP_STATE_DISABLE = 0, - WMI_UHR_AP_MODE_TUP_STATE_ENABLE = 1, - WMI_UHR_AP_MODE_TUP_STATE_UPDATE = 2, - WMI_UHR_AP_MODE_TUP_STATE_RESERVED = 3, - WMI_UHR_AP_MODE_TUP_STATE_MAX = 4 -} WMI_UHR_AP_MODE_TUP_STATE; - -#define WMI_UHR_AP_VDEV_ID_GET(var) WMI_GET_BITS(var, 0, 8) -#define WMI_UHR_AP_VDEV_ID_SET(var, val) WMI_SET_BITS(var, 0, 8, val) - - -#define WMI_UHR_AP_MODE_TUP_DPS_GET(var) WMI_GET_BITS(var, 8, 2) -#define WMI_UHR_AP_MODE_TUP_DPS_SET(var, val) WMI_SET_BITS(var, 8, 2, val) - -#define WMI_UHR_AP_MODE_TUP_NPCA_GET(var) WMI_GET_BITS(var, 10, 2) -#define WMI_UHR_AP_MODE_TUP_NPCA_SET(var, val) WMI_SET_BITS(var, 10, 2, val) - -#define WMI_UHR_AP_MODE_TUP_DUO_GET(var) WMI_GET_BITS(var, 12, 2) -#define WMI_UHR_AP_MODE_TUP_DUO_SET(var, val) WMI_SET_BITS(var, 12, 2, val) - -#define WMI_UHR_AP_MODE_TUP_PEDCA_GET(var) WMI_GET_BITS(var, 14, 2) -#define WMI_UHR_AP_MODE_TUP_PEDCA_SET(var, val) WMI_SET_BITS(var, 14, 2, val) - -#define WMI_UHR_AP_MODE_TUP_DBE_GET(var) WMI_GET_BITS(var, 16, 2) -#define WMI_UHR_AP_MODE_TUP_DBE_SET(var, val) WMI_SET_BITS(var, 16, 2, val) - -#define WMI_UHR_AP_MODE_TUP_PUO_GET(var) WMI_GET_BITS(var, 18, 2) -#define WMI_UHR_AP_MODE_TUP_PUO_SET(var, val) WMI_SET_BITS(var, 18, 2, val) - -#define WMI_UHR_AP_MODE_TUP_ELR_GET(var) WMI_GET_BITS(var, 20, 2) -#define WMI_UHR_AP_MODE_TUP_ELR_SET(var, val) WMI_SET_BITS(var, 20, 2, val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_mode_tuple_enable_disable_update_params */ - A_UINT32 tlv_header; - /* - * WMI_UHR_AP_MODE_TUP_DPS_GET/_NPCA/DBE/DUO/PUO/ELR/PEDCA - * Modes are defined in WMI_UHR_AP_MODE_TUP - * WMI_UHR_AP_MODE_TUP_DPS_SET/ - * similarly for DBE/DPS/DUO/PUO/ELR/PEDCA - */ - union{ - /* - * Bits 0:7 - vdev_id (8 bits) - * Bits 8:31 - mode enable/disable/update bitmap - * (24 bits, using 2 bits for each mode) - * WMI_UHR_AP_MODE_TUP_STATE - * WMI_UHR_MAX_MODES - * Bits 8:9 DPS - * Bits 10:11 NPCA - * Bits 12:13 DUO - * Bits 14:15 PEDCA - * Bits 16:17 DBE - * Bits 18:19 PUO - * Bits 20:21 ELR - * Bits 22:31 reserved - */ - A_UINT32 vdev_id_mode_tuple_enable_disable_update_bits; - struct{ - A_UINT32 vdev_id:8, - mode_tup_dps_enable_disable_update_bits: 2, - mode_tup_npca_enable_disable_update_bits: 2, - mode_tup_duo_enable_disable_update_bits: 2, - mode_tup_pedca_enable_disable_update_bits: 2, - mode_tup_dbe_enable_disable_update_bits: 2, - mode_tup_puo_enable_disable_update_bits: 2, - mode_tup_elr_enable_disable_update_bits: 2, - reserved:10; - }; - }; - /* Add any new required fields below */ -} wmi_uhr_ap_mode_tuple_enable_disable_update_params; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_cmd_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* This fixed param TLV will be followed by the below TLVs - * - wmi_uhr_ap_dps_params - * - wmi_uhr_ap_npca_params - * - wmi_uhr_ap_duo_params - * - wmi_uhr_ap_pedca_params - * - wmi_uhr_ap_dbe_params - * - wmi_uhr_ap_ap_puo_params - * - wmi_uhr_ap_elr_reception_params - * - wmi_uhr_ap_mode_tuple_enable_disable_update_params[] - */ -} wmi_vdev_uhr_cu_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_cmd_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 pdev_id; - /* This fixed param TLV will be followed by the below TLVs - * - wmi_uhr_ap_dps_params[] - * - wmi_uhr_ap_npca_params[] - * - wmi_uhr_ap_duo_params[] - * - wmi_uhr_ap_pedca_params[] - * - wmi_uhr_ap_dbe_params[] - * - wmi_uhr_ap_ap_puo_params[] - * - wmi_uhr_ap_elr_reception_params[] - * - wmi_uhr_ap_mode_tuple_enable_disable_update_params[] - */ -} wmi_pdev_uhr_cu_cmd_fixed_param; - -typedef enum { - WMI_VDEV_UHR_CU_IN_PROGRESS, - WMI_VDEV_UHR_CU_ESTABLISHED, - WMI_VDEV_UHR_CU_SESSION_END, -} wmi_vdev_uhr_cu_state; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_status */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* Refer wmi_vdev_uhr_cu_state*/ - A_UINT32 status; -} wmi_vdev_uhr_cu_status; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_event_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 pdev_id; - - /* This fixed param TLV will be followed by the below TLVs - * - wmi_vdev_uhr_cu_status[] - */ -} wmi_pdev_uhr_cu_event_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_vdev_channel_hopping_schedule_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* index of next channel in the channel_list tlvs to visit */ - A_UINT32 next_channel_index; - /* dwell time in TUs to stay on each channel. 1 TU = 1024 usec */ - A_UINT32 dwell_time_tu; - /* Target tsf at which this schedule should start */ - A_UINT32 target_switch_time_tsf; - - /* This fixed param TLV will be followed by the below TLVs - * - A_UINT32 channel_list[num_chan]; // in MHz - * // DEPRECATED - POPULATE WITH ZERO ELEMS. - * // Use channel_param_list instead. - * - wmi_channel_hopping_channel_params channel_param_list[num_chan]; - */ -} wmi_vdev_channel_hopping_schedule_fixed_param; - -typedef enum { - /* Channel is designated for PASSTHRU VDEV */ - WMI_CHANNEL_HOPPING_ROLE_PASSTHRU = 0, - /* Channel is designated for any other interfaces besides PASSTHRU VDEV */ - WMI_CHANNEL_HOPPING_ROLE_NON_PASSTHRU, -} wmi_channel_hopping_role; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_channel_hopping_channel_params */ - A_UINT32 tlv_header; - A_UINT32 chan_mhz; /* in MHz. Valid only when role is PASSTHRU */ - /* bandwidth: - * Holds a wmi_channel_width enum value. - * Valid only when role is PASSTHRU. - */ - A_UINT32 bandwidth; - A_UINT32 role; /* holds wmi_channel_hopping_role enum value */ -} wmi_channel_hopping_channel_params; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_chan_hop_status_report_cmd_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; -} wmi_vdev_get_chan_hop_status_report_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_chan_hop_slot_status */ - A_UINT32 tlv_header; - A_UINT32 role; /* holds wmi_channel_hopping_role enum value */ - A_UINT32 chan_mhz; - /* - * TSF of the most recent actual frequency transition leading into - * slot. Carried forward for consecutive same-frequency slots. - */ - A_UINT32 channel_switch_tsf; - A_UINT32 channel_start_tsf; /* TSF when this slot's active period began. */ - A_UINT32 channel_end_tsf; /* TSF when this slot's active period ended. */ - /** - * tx_traffic_index = (tx_duration_us / channel_spent_us) * 100 - * Range: 0 - 100 - */ - A_UINT32 tx_traffic_index; - /** - * rx_traffic_index = (rx_duration_us / channel_spent_us) * 100 - * Range: 0 - 100 - */ - A_UINT32 rx_traffic_index; -} wmi_vdev_chan_hop_slot_status; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_chan_hop_status_report_event_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /** TSF timestamp of the current channel hopping request */ - A_UINT32 hopping_request_tsf; - /* Index of the current channel in the channel hopping list */ - A_UINT32 current_channel_index; -} wmi_vdev_chan_hop_status_report_event_fixed_param; - -typedef enum { - WMI_SMD_ROAM_CONFIG_ROLE_SERVING_AP = 1, - WMI_SMD_ROAM_CONFIG_ROLE_TARGET_AP, - WMI_SMD_ROAM_CONFIG_ROLE_STA, -} wmi_smd_roam_config_role; - -typedef enum { - WMI_SMD_ROAM_CONFIG_CMD_PREP_REQ = 1, - WMI_SMD_ROAM_CONFIG_CMD_PREP_RESP, - WMI_SMD_ROAM_CONFIG_CMD_EXEC_REQ, - WMI_SMD_ROAM_CONFIG_CMD_EXEC_RESP, - WMI_SMD_ROAM_CONFIG_CMD_DYNAMIC_CONTEXT, - WMI_SMD_ROAM_CONFIG_CMD_TERMINATION, -} wmi_smd_roam_config_cmd_type; - -#define WMI_SMD_ROAM_FLAG_DL_SN_NOT_TRANSFFERED 0x01 -#define WMI_SMD_ROAM_FLAG_UL_SN_NOT_TRANSFFERED 0x02 -#define WMI_SMD_ROAM_FLAG_DISABLE_LINK 0x04 - -#define WMI_SMD_ROAM_PEER_GET_MLSN(dword) \ - WMI_GET_BITS(dword, 0, 16) -#define WMI_SMD_ROAM_PEER_SET_MLSN(dword, value) \ - WMI_SET_BITS(dword, 0, 16, value) - -#define WMI_SMD_ROAM_PEER_GET_OFFSET(dword) \ - WMI_GET_BITS(dword, 16, 16) -#define WMI_SMD_ROAM_PEER_SET_OFFSET(dword, value) \ - WMI_SET_BITS(dword, 16, 16, value) - -typedef struct { - A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_smd_roam_peer_tid_info */ - A_UINT32 tid_num; - union { - A_UINT32 mlsn__offset__word32; - struct { - A_UINT32 mlsn: 16, - offset: 16; - }; - }; - A_UINT32 tx_buffer_size; /* tx block ack window size */ - A_UINT32 rx_buffer_size; /* rx block ack window size */ -} wmi_smd_roam_peer_tid_info; - -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_GET_ROLE(cmd_flags) WMI_GET_BITS(mlo_flags, 0, 4) -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_SET_ROLE(cmd_flags, value) WMI_SET_BITS(mlo_flags, 0, 4, value) - -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_GET_CMD_TYPE(cmd_flags) WMI_GET_BITS(mlo_flags, 4, 8) -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_SET_CMD_TYPE(cmd_flags, value) WMI_SET_BITS(mlo_flags, 4, 8, value) - -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_GET_STATUS(cmd_flags) WMI_GET_BITS(mlo_flags, 12, 8) -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_SET_STATUS(cmd_flags, value) WMI_SET_BITS(mlo_flags, 12, 8, value) - -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_GET_ROAM_FLAGS(cmd_flags) WMI_GET_BITS(mlo_flags, 20, 8) -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_SET_ROAM_FLAGS(cmd_flags, value) WMI_SET_BITS(mlo_flags, 20, 8, value) - -typedef enum { - WMI_SMD_ROAM_CONFIG_CMD_SUCCESS = 0, - WMI_SMD_ROAM_CONFIG_CMD_FAILURE, -} wmi_smd_roam_config_cmd_status; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_smd_roam_config_cmd_fixed_param */ - /** global unique ID identifying vdev */ - A_UINT32 vdev_id; - /** PEER MAC address */ - wmi_mac_addr peer_mac_addr; - union { - A_UINT32 cmd_flags; - struct { - A_UINT32 role :4, /* wmi_smd_config_role */ - cmd_type :8, /* wmi_smd_config_cmd_type */ - status :8, /* wmi_smd_roam_config_cmd_status */ - roam_flags :8, /* WMI_SMD_ROAM_FLAG_* */ - reserved :4; - }; - }; - A_UINT32 dl_drain_time; /* units = milliseconds */ - /* - * Followed by per tid tlv wmi_smd_roam_peer_tid_info[]. - * Present when dynamic context is set. - */ -} wmi_smd_roam_config_cmd_fixed_param; - -#define WMI_SMD_ROAM_CONFIG_EVENT_FLAGS_GET_ROLE(event_flags) WMI_GET_BITS(mlo_flags, 0, 4) -#define WMI_SMD_ROAM_CONFIG_EVENT_FLAGS_SET_ROLE(event_flags, value) WMI_SET_BITS(mlo_flags, 0, 4, value) - -#define WMI_SMD_ROAM_CONFIG_EVENT_FLAGS_GET_CMD_TYPE(event_flags) WMI_GET_BITS(mlo_flags, 4, 8) -#define WMI_SMD_ROAM_CONFIG_EVENT_FLAGS_SET_CMD_TYPE(event_flags, value) WMI_SET_BITS(mlo_flags, 4, 8, value) - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; */ - /** global unique ID identifying vdev */ - A_UINT32 vdev_id; - /** PEER MAC address */ - wmi_mac_addr peer_mac_address; - /* maximum ST Transitory Duration */ - A_UINT32 dl_drain_time; /* units = milliseconds */ - union { - A_UINT32 event_flags; - struct { - A_UINT32 role:4, - cmd_type:8, - unused:20; - }; - }; -} wmi_smd_roam_config_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_cmd_fixed_param */ - - /** global unique ID identifying peer */ - A_UINT32 peer_id; - /* - * Following this struct are the TLV's: - * wmi_smd_roam_peer_tid_info smd_roam_peer_tid_info[]; <- TLV per TID - * wmi_peer_create_cmd_fixed_param peer_create_fixed_param; - * wmi_peer_create_mlo_params peer_create_mlo_params[]; - * wmi_peer_assoc_complete_cmd_fixed_param peer_assoc_fixed_param; - * A_UINT8 peer_assoc_peer_legacy_rates[]; - * A_UINT8 peer_assoc_peer_ht_rates[]; - * wmi_vht_rate_set peer_assoc_peer_vht_rates; - * wmi_he_rate_set peer_assoc_peer_he_rates[]; - * wmi_peer_assoc_mlo_params peer_assoc_mlo_params[]; - * wmi_eht_rate_set peer_assoc_peer_eht_rates[]; - * wmi_peer_assoc_mlo_partner_link_params - * peer_assoc_partner_link_params[]; - * wmi_peer_assoc_tid_to_link_map peer_assoc_peer_tid_to_link_map[]; - * wmi_peer_assoc_operating_mode_params - * peer_assoc_operating_mode_params[]; - * wmi_peer_assoc_mgmt_mpduq_params peer_assoc_mgmt_mpduq_params[]; - * wmi_peer_assoc_mgmt_msduq_params peer_assoc_mgmt_msduq_params[]; - * wmi_peer_assoc_hol_msduq_params peer_assoc_hol_mdsuq_params[]; - * wmi_peer_assoc_complete_cmd_fixed_param peer_assoc_v2_fixed_param; - * A_UINT8 peer_assoc_v2_peer_legacy_rates[]; - * A_UINT8 peer_assoc_v2_peer_ht_rates[]; - * wmi_vht_rate_set peer_assoc_v2_peer_vht_rates; - * wmi_he_rate_set peer_assoc_v2_peer_he_rates[]; - * wmi_peer_assoc_mlo_params peer_assoc_v2_mlo_params[]; - * wmi_eht_rate_set peer_assoc_v2_peer_eht_rates[]; - * wmi_peer_assoc_mlo_partner_link_params - * peer_assoc_v2_partner_link_params[]; - * wmi_peer_assoc_tid_to_link_map peer_assoc_v2_peer_tid_to_link_map[]; - * wmi_peer_assoc_operating_mode_params - * peer_assoc_v2_operating_mode_params[]; - * wmi_peer_assoc_mgmt_mpduq_params peer_assoc_v2_mgmt_mpduq_params[]; - * wmi_peer_assoc_mgmt_msduq_params peer_assoc_v2_mgmt_msduq_params[]; - * wmi_peer_assoc_hol_msduq_params peer_assoc_v2_hol_mdsuq_params[]; - * wmi_peer_uhr_npca_cap_params peer_assoc_v2_peer_npca_cap_params[]; - * wmi_peer_create_mlo_params peer_assoc_v2_create_mlo_params[]; - * wmi_peer_assoc_cfp_params peer_assoc_v2_cfp_params; - * wmi_peer_assoc_smd_params peer_assoc_v2_smd_params; - * wmi_vdev_install_key_cmd_fixed_param key_install_fixed_param; - * A_UINT8 key_data[]; - * wmi_uhr_rate_set peer_uhr_rates[]; - * wmi_peer_uhr_npca_op_params npca_op_params[0,1] - */ -} wmi_smd_roam_peer_unified_setup_cmd_fixed_param; - -typedef enum { - WMI_SMD_PEER_SETUP_SUCCESS = 0, - WMI_SMD_PEER_SETUP_FAILURE, -} wmi_smd_peer_setup_status_type; - -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_complete_event_fixed_param */ - A_UINT32 tlv_header; - /** global unique ID identifying peer */ - A_UINT32 peer_id; - A_UINT32 status; /** wmi_smd_peer_setup_status_type */ -} wmi_smd_roam_peer_unified_setup_complete_event_fixed_param; - -/* ================================================================ */ -/* WMI_PEER_SET_MAPC_PARAMS_CMDID structures */ -/* ================================================================ */ - -/* Scheme enable bitmap — indicates which scheme TLVs are present */ -#define WMI_MAPC_SCHEME_COBF (1 << 0) /* Co-BF */ -#define WMI_MAPC_SCHEME_COSR (1 << 1) /* Co-SR */ -#define WMI_MAPC_SCHEME_COTDMA (1 << 2) /* Co-TDMA */ -#define WMI_MAPC_SCHEME_CORTWT (1 << 3) /* Co-rTWT */ -#define WMI_MAPC_SCHEME_COCR (1 << 4) /* Co-CR */ - -/* - * wmi_peer_set_mapc_params_cmd_fixed_param: - * Identity + routing hint for WMI_PEER_SET_MAPC_PARAMS_CMDID. - * mapc_scheme_enable_bitmap indicates which scheme TLVs follow. - * Sent after WMI_PEER_CREATE_CMDID (peer_type=WMI_PEER_TYPE_MAPC) - * and after each MAPC Negotiation Agreement Establishment/Update. - */ -typedef struct { - A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_peer_set_mapc_params_cmd_fixed_param */ - A_UINT32 vdev_id; - wmi_mac_addr peer_macaddr; - A_UINT32 mapc_scheme_enable_bitmap; /* WMI_MAPC_SCHEME_* bitmask */ -} wmi_peer_set_mapc_params_cmd_fixed_param; - -/* - * wmi_mapc_cmn_params: - * Common MAPC params shared across all schemes. - */ -typedef struct { - A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_mapc_cmn_params */ - - /* peer's advertised MAPC capability bitmap */ - A_UINT32 mapc_capability_bitmap; - - /* APID assigned by local AP to remote C-AP */ - A_UINT32 apid_to_neighbor_peer; - - /* APID assigned by remote C-AP to local AP */ - A_UINT32 apid_from_neighbor_peer; - - /* Vendor Q2Q APID assigned to remote peer */ - A_UINT32 q2q_apid_to_neighbor_peer; - - /* Vendor Q2Q APID assigned by remote peer */ - A_UINT32 q2q_apid_from_neighbor_peer; -} wmi_mapc_cmn_params; - -/* - * wmi_mapc_cotdma_params: mapc_ctdma_profile + mapc_txop_sharing_policy - * Co-TDMA per-peer policy parameters. - */ -typedef struct { - A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_mapc_cotdma_params */ - - /* Channel info — mapc_ctdma_profile */ - A_UINT32 channel_width; /* operating channel width (MHz) */ - A_UINT32 ccfs; /* center channel frequency segment index */ - A_UINT32 bss_color; /* 802.11ax/be BSS color */ - - /* 1 = peer supports RX-driven TXOP return */ - A_UINT32 rx_txop_return_support; - - A_UINT32 disable_subchannel_bitmap; /* subchannels to disable */ - - /* TXOP sharing policy — mapc_txop_sharing_policy */ - A_UINT32 primary_ac; /* primary AC: VO=0 VI=1 BE=2 BK=3 */ - A_UINT32 nbr_ap_prio; /* Cotroller set nbr shared ap prio */ - A_UINT32 latency_sensitive_threshold_us; - A_UINT32 service_start_time; /* TSF-relative service window start (us) */ - A_UINT32 service_interval; /* periodicity (us); 0 = always available */ - A_UINT32 service_end_time; /* TSF-relative service window end (us) */ - A_UINT32 critical_traffic_dur_thresh_us; - A_UINT32 max_shared_txop_dur_us; /* per-AC max shared TXOP */ - A_UINT32 min_shared_txop_dur_us; /* per-AC min TXOP to trigger C-TDMA */ -} wmi_mapc_cotdma_params; - -/* - * Stub structures for future MAPC coordination schemes. - * Included now to reserve TLV slots in WMI_PEER_SET_MAPC_PARAMS_CMDID so that - * the TLV layout remains stable when these schemes are implemented. Host must - * send 0 array entries for each stub; FW ignores them until the feature lands. - */ - -/* Co-SR (Coordinated Spatial Reuse, 802.11bn): allows coordinated BSS-color / - * OBSS_PD threshold negotiation between C-APs to improve spatial reuse. */ -typedef struct { A_UINT32 tlv_header; } wmi_mapc_cosr_params; - -/* Co-BF (Coordinated Beamforming, 802.11bn): enables joint beamforming vector - * coordination between C-APs to suppress inter-BSS interference. */ -typedef struct { A_UINT32 tlv_header; } wmi_mapc_cobf_params; - -/* Co-rTWT (Coordinated restricted-TWT, 802.11bn): allows C-APs to align their - * restricted-TWT service periods to avoid overlapping transmissions. */ -typedef struct { A_UINT32 tlv_header; } wmi_mapc_cortwt_params; - - -typedef enum { - WMI_PDEV_SET_CUMAC_CHIP_ID_SUCCESS = 0, - WMI_PDEV_SET_CUMAC_CHIP_ID_FAILURE, -} wmi_pdev_set_cumac_chip_id_status_type; - -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_set_cumac_chip_id_cmd_fixed_param */ - A_UINT32 tlv_header; - /** global unique ID identifying pdev */ - A_UINT32 pdev_id; - /** global unique ID identifying chip id of selected CUMAC chip */ - A_UINT32 cumac_chip_id; -} wmi_pdev_set_cumac_chip_id_cmd_fixed_param; - -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param */ - A_UINT32 tlv_header; - /** global unique ID identifying pdev */ - A_UINT32 pdev_id; - A_UINT32 status; /** wmi_pdev_set_cumac_chip_id_status_type */ -} wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param; - - -/* vdev operating param flags */ -#define WMI_VDEV_OPERATING_PARAM_SET_UPDATED_BW 0x1 -#define WMI_VDEV_OPERATING_PARAM_SET_UPDATED_NSS 0x2 -#define WMI_VDEV_OPERATING_PARAM_SET_UPDATED_CHAINS 0x4 - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_current_operating_param_event_fixed_param */ - /* operating_param_flags: holds WMI_VDEV_OPERATING_PARAM_ values */ - A_UINT32 operating_param_flags; - A_UINT32 vdev_id; /* ID of the vdev these data stats are from */ - /* bw: current operating bandwidth (a wmi_channel_width enum value) */ - A_UINT32 bw; - /* Current operating Tx and Rx NSS */ - A_UINT32 tx_nss; - A_UINT32 rx_nss; - /* Current Tx and RX Chains of HW intersected with connection capability */ - A_UINT32 tx_chains; - A_UINT32 rx_chains; -} wmi_vdev_current_operating_param_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_cmd_fixed_param */ - /** unique id identifying the request */ - A_UINT32 request_id; -} wmi_get_chipset_logging_stats_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_event_fixed_param */ - /** unique id identifying the request */ - A_UINT32 request_id; - /** length in bytes of the chipset log stats data */ - A_UINT32 data_len; - /** - * Following this structure is the TLV: - * A_UINT8 data[]; <-- chipset log stats data, length given by data_len - */ -} wmi_get_chipset_logging_stats_event_fixed_param; - -/* ----------------------------------------------------------------------- - * TLV #1 — Message-level header - * ----------------------------------------------------------------------- */ -typedef struct { - A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_anomaly_report_hdr */ - A_UINT32 pdev_id; /* PDEV ID (common for all entries in batch) */ -} wmi_anomaly_report_hdr; - -/* ----------------------------------------------------------------------- - * Per-Anomaly Context Sub-Structures (all fields A_UINT32 per WMI convention) - * ----------------------------------------------------------------------- */ - -/* - * Context for WMI_ANOMALY_ID_VDEV_DELETE_REQUESTED_BEFORE_STOP - * (ID 0000–0999) - */ -typedef struct { - A_UINT32 vdev_state; /* Internal VDEV state at time of fault */ - A_UINT32 vdev_type; /* VDEV type (AP/STA/IBSS/etc.) */ -} wmi_anomaly_vdev_ctx_t; - -/* - * Context for WMI_ANOMALY_ID_DELETE_VDEV_BEFORE_DELETING_ALL_PEERS - * (ID 1000–1999) - */ -typedef struct { - A_UINT32 peer_count; /* Number of peers still associated */ - /* MAC address of first offending peer (lower 32 bits) */ - A_UINT32 peer_mac_addr_lo; - /* MAC address of first offending peer (upper 16 bits) */ - A_UINT32 peer_mac_addr_hi; - A_UINT32 peer_state; /* Internal peer state at time of fault */ -} wmi_anomaly_peer_ctx_t; - -/* - * Context for WMI_ANOMALY_ID_BEACON_TEMPLATE_SANITY_FAILED - * (ID 2000–2999) - */ -typedef struct { - A_UINT32 bcn_buf_len; /* Beacon buffer length that was received */ - A_UINT32 max_allowed_len; /* Maximum allowed beacon buffer length */ - A_UINT32 ie_offset; /* IE offset at which sanity failed */ - A_UINT32 fail_reason; /* Internal reason code for the failure */ -} wmi_anomaly_beacon_ctx_t; - -/* - * Context for halPhy bucket groups - * (ID 5000–9999) - */ -typedef struct { - A_UINT32 phy_err_code; /* Hardware PHY error code at fault time */ - A_UINT32 chain_mask; /* Active RX/TX chain mask at fault time */ - A_UINT32 cal_step; /* Calibration step index; 0 if not applicable */ - A_UINT32 hw_status; /* Raw hardware status register snapshot */ -} wmi_anomaly_halphy_ctx_t; - -/* - * Context for uCode bucket groups - * (ID 10000–14999) - */ -typedef struct { - A_UINT32 ucode_pc; /* uCode program counter at fault time */ - A_UINT32 sched_state; /* Scheduler state machine value at fault time */ - A_UINT32 txrx_status; /* TX/RX pipeline status register snapshot */ - A_UINT32 watchdog_count; /* Watchdog expiry count since last reset */ -} wmi_anomaly_ucode_ctx_t; - -/* ----------------------------------------------------------------------- - * TLV #2 — Per-Anomaly Entry (ARRAY_STRUC element) - * anomaly_id is the discriminant — tells host which union member is valid. - * ----------------------------------------------------------------------- */ -typedef struct { - A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_anomaly_entry_t */ - A_UINT32 anomaly_id; /* [31:1]=WMI_ANOMALY_ID [0]=type(0=A/1=E) */ - A_UINT32 vdev_id; /* Virtual Device ID (0xFFFFFFFF if N/A) */ - A_UINT32 priority; /* WMI_ANOMALY_PRIORITY */ - A_UINT32 related_cmd_id; /* WMI_CMD_ID (0 if N/A) */ - A_UINT32 reserved[2]; /* for future use when needed */ - union { - wmi_anomaly_vdev_ctx_t vdev; /* ID 0000–0999 */ - wmi_anomaly_peer_ctx_t peer; /* ID 1000–1999 */ - wmi_anomaly_beacon_ctx_t beacon; /* ID 2000–2999 */ - wmi_anomaly_halphy_ctx_t halphy; /* ID 5000–9999 */ - wmi_anomaly_ucode_ctx_t ucode; /* ID 10000–14999 */ - } ctx; - /* NOTE: - * No new fields can be added here - this restriction allows new fields - * to be added to the end of the wmi_anomaly_xxx_ctx_t structs instead. - */ -} wmi_anomaly_entry_t; - - -/* RTT Peer Measurement (Proximity Detection/Ranging) capabilities */ - -/* - * macros to set/get bitfields within - * wmi_rtt_peer_meas_capabilities - */ - -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_REPORT_AP_TSF_GET(flags) WMI_GET_BITS(flags, 0, 1) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_REPORT_AP_TSF_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_RANDOMIZE_MAC_GET(flags) WMI_GET_BITS(flags, 1, 1) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_RANDOMIZE_MAC_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_SUPPORT_GET(flags) WMI_GET_BITS(flags, 2, 1) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_CONCURRENT_GET(flags) WMI_GET_BITS(flags, 3, 1) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_CONCURRENT_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_RANDOM_MAC_CONNECTED_GET(flags) WMI_GET_BITS(flags, 4, 1) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_RANDOM_MAC_CONNECTED_SET(flags, value) WMI_SET_BITS(flags, 4, 1, value) - -#define WMI_RTT_PEER_MEAS_CAPS_PD_MAX_PEERS_ISTA_ROLE_GET(flags) WMI_GET_BITS(flags, 0, 16) -#define WMI_RTT_PEER_MEAS_CAPS_PD_MAX_PEERS_ISTA_ROLE_SET(flags, value) WMI_SET_BITS(flags, 0, 16, value) -#define WMI_RTT_PEER_MEAS_CAPS_PD_MAX_PEERS_RSTA_ROLE_GET(flags) WMI_GET_BITS(flags, 16, 16) -#define WMI_RTT_PEER_MEAS_CAPS_PD_MAX_PEERS_RSTA_ROLE_SET(flags, value) WMI_SET_BITS(flags, 16, 16, value) - -#define WMI_RTT_PEER_MEAS_CAPS_FTM_SUPPORT_GET(flags) WMI_GET_BITS(flags, 0, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_ASAP_SUPPORT_GET(flags) WMI_GET_BITS(flags, 1, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_ASAP_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_NON_ASAP_SUPPORT_GET(flags) WMI_GET_BITS(flags, 2, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_NON_ASAP_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_REQ_LCI_SUPPORT_GET(flags) WMI_GET_BITS(flags, 3, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_REQ_LCI_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_REQ_CIVICLOC_SUPPORT_GET(flags) WMI_GET_BITS(flags, 4, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_REQ_CIVICLOC_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 4, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_TB_RANGING_SUPPORT_GET(flags) WMI_GET_BITS(flags, 5, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_TB_RANGING_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 5, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_NTB_RANGING_SUPPORT_GET(flags) WMI_GET_BITS(flags, 6, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_NTB_RANGING_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 6, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_6GHZ_SUPPORT_GET(flags) WMI_GET_BITS(flags, 7, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_6GHZ_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 7, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_RSTA_ROLE_SUPPORT_GET(flags) WMI_GET_BITS(flags, 8, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_RSTA_ROLE_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 8, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_EDCA_RESPONDER_SUPPORT_GET(flags) WMI_GET_BITS(flags, 9, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_EDCA_RESPONDER_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 9, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_RANGE_REPORT_SUPPORT_GET(flags) WMI_GET_BITS(flags, 10, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_RANGE_REPORT_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 10, 1, value) - -#define WMI_RTT_PEER_MEAS_CAPS_MAX_BURST_EXPONENTS_GET(caps) WMI_GET_BITS(caps, 0, 8) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_BURST_EXPONENTS_SET(caps, value) WMI_SET_BITS(caps, 0, 8, value) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_FTM_PER_BURST_GET(caps) WMI_GET_BITS(caps, 8, 8) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_FTM_PER_BURST_SET(caps, value) WMI_SET_BITS(caps, 8, 8, value) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_TX_ANTENNAS_GET(caps) WMI_GET_BITS(caps, 16, 8) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_TX_ANTENNAS_SET(caps, value) WMI_SET_BITS(caps, 16, 8, value) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_RX_ANTENNAS_GET(caps) WMI_GET_BITS(caps, 24, 8) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_RX_ANTENNAS_SET(caps, value) WMI_SET_BITS(caps, 24, 8, value) - -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_LTF_REP_GET(params) WMI_GET_BITS(params, 0, 3) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_LTF_REP_SET(params, value) WMI_SET_BITS(params, 0, 3, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_LTF_REP_GET(params) WMI_GET_BITS(params, 3, 3) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_LTF_REP_SET(params, value) WMI_SET_BITS(params, 3, 3, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_LTF_TOTAL_GET(params) WMI_GET_BITS(params, 6, 2) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_LTF_TOTAL_SET(params, value) WMI_SET_BITS(params, 6, 2, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_LTF_TOTAL_GET(params) WMI_GET_BITS(params, 8, 2) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_LTF_TOTAL_SET(params, value) WMI_SET_BITS(params, 8, 2, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_STS_LE80_GET(params) WMI_GET_BITS(params, 10, 3) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_STS_LE80_SET(params, value) WMI_SET_BITS(params, 10, 3, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_STS_GT80_GET(params) WMI_GET_BITS(params, 13, 3) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_STS_GT80_SET(params, value) WMI_SET_BITS(params, 13, 3, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_STS_LE80_GET(params) WMI_GET_BITS(params, 16, 3) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_STS_LE80_SET(params, value) WMI_SET_BITS(params, 16, 3, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_STS_GT80_GET(params) WMI_GET_BITS(params, 19, 3) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_STS_GT80_SET(params, value) WMI_SET_BITS(params, 19, 3, value) - - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_capabilities */ - A_UINT32 tlv_header; - /** - * Support flag - * Bit 0 : report AP tsf - * Bit 1 : randomize mac address - * Bit 2 : Proximity Detection (PD) support i.e. USD ranging - * Bit 3 : PD concurrent ISTA and RSTA support - * Bit 4 : PD randomize mac address connected state - * Bits 31-5 : Reserved - */ - A_UINT32 support_flag; - A_UINT32 max_peers; - /** - * pd max peers - * Bits 15-0 : pd_max_peers ISTA role - * Bits 31-16 : pd_max_peers RSTA role - */ - A_UINT32 pd_max_peers; - /** - * FTM support flag - * Bit 0 : ftm supported - * Bit 1 : asap mode is supported - * Bit 2 : non-asap mode is supported - * Bit 3 : request lci - * Bit 4 : request civicloc - * Bit 5 : trigger based supported (TB ranging) - * Bit 6 : non-trigger based supported (NTB ranging) - * Bit 7 : 6 Ghz supported - * Bit 8 : Support Rsta role - * Bit 9 : Support edca responder - * Bit 10 : Support range report - * Bits 31-11 : Reserved - */ - A_UINT32 ftm_support_flag; - /** Bitmap of BW supported per wmi_channel_width enum */ - A_UINT32 supported_bw_bitmap; - /** Bitmap of Preambles supported per WMI_RATE_PREAMBLE */ - A_UINT32 supported_preamble_bitmap; - /** - * capabilities - * Bits 7-0 : Max burst exponents - * Bits 15-8 : Max FTM per burst - * Bits 23-16 : Max Tx antennas - * Bits 31-24 : Max Rx antennas - */ - A_UINT32 capabilities; - /** - * ranging 11az parameters - * Bits 2-0 : Max Tx LTF repetition - * Bits 5-3 : Max Rx LTF repetition - * Bits 7-6 : Max Rx LTF total - * Bits 9-8 : Max Tx LTF total - * Bits 12-10 : Max Rx STS LE 80 - * Bits 15-13 : Max Rx STS GT 80 - * Bits 18-16 : Max Tx STS LE 80 - * Bits 21-19 : Max Tx STS GT 80 - * Bits 31-22 : Reserved - */ - A_UINT32 ranging_11az_parameters; - /* Min allowed ranging interval supported by target in EDCA-based ranging, in ms */ - A_UINT32 min_interval_edca_ms; - /* Min allowed ranging interval supported by target in NTB (Non-Trigger Based) ranging, in ms */ - A_UINT32 min_interval_ntb_ms; -} wmi_rtt_peer_meas_capabilities; - -/* - * macros to set/get bitfields within - * wmi_rtt_peer_meas_req_peer_info - */ - -#define WMI_RTT_PEER_MEAS_REQ_FLAG_REPORT_AP_TSF_GET(flags) WMI_GET_BITS(flags, 0, 1) -#define WMI_RTT_PEER_MEAS_REQ_FLAG_REPORT_AP_TSF_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_FLAG_PD_REQUEST_GET(flags) WMI_GET_BITS(flags, 1, 1) -#define WMI_RTT_PEER_MEAS_REQ_FLAG_PD_REQUEST_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value) - -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_FTM_REQUESTED_GET(flags) WMI_GET_BITS(flags, 0, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_FTM_REQUESTED_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_ASAP_MODE_GET(flags) WMI_GET_BITS(flags, 1, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_ASAP_MODE_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_LCI_REQ_GET(flags) WMI_GET_BITS(flags, 2, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_LCI_REQ_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_LOC_CIVIC_REQ_GET(flags) WMI_GET_BITS(flags, 3, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_LOC_CIVIC_REQ_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_TB_RANGING_GET(flags) WMI_GET_BITS(flags, 4, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_TB_RANGING_SET(flags, value) WMI_SET_BITS(flags, 4, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_NTB_RANGING_GET(flags) WMI_GET_BITS(flags, 5, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_NTB_RANGING_SET(flags, value) WMI_SET_BITS(flags, 5, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_I2R_LMR_FEEDBACK_GET(flags) WMI_GET_BITS(flags, 6, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_I2R_LMR_FEEDBACK_SET(flags, value) WMI_SET_BITS(flags, 6, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_RSTA_ROLE_GET(flags) WMI_GET_BITS(flags, 7, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_RSTA_ROLE_SET(flags, value) WMI_SET_BITS(flags, 7, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_RANGE_REPORT_GET(flags) WMI_GET_BITS(flags, 8, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_RANGE_REPORT_SET(flags, value) WMI_SET_BITS(flags, 8, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_SUPPRESS_PD_RESULT_GET(flags) WMI_GET_BITS(flags, 9, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_SUPPRESS_PD_RESULT_SET(flags, value) WMI_SET_BITS(flags, 9, 1, value) - -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_NUM_BURST_EXP_GET(info) WMI_GET_BITS(info, 0, 8) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_NUM_BURST_EXP_SET(info, value) WMI_SET_BITS(info, 0, 8, value) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_BURST_DURATION_GET(info) WMI_GET_BITS(info, 8, 8) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_BURST_DURATION_SET(info, value) WMI_SET_BITS(info, 8, 8, value) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_FTMS_PER_BURST_GET(info) WMI_GET_BITS(info, 16, 8) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_FTMS_PER_BURST_SET(info, value) WMI_SET_BITS(info, 16, 8, value) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_FTMR_RETRIES_GET(info) WMI_GET_BITS(info, 24, 8) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_FTMR_RETRIES_SET(info, value) WMI_SET_BITS(info, 24, 8, value) - -#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_NOMINAL_TIME_GET(elem) WMI_GET_BITS(elem, 0, 16) -#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_NOMINAL_TIME_SET(elem, value) WMI_SET_BITS(elem, 0, 16, value) -#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_MEAS_PER_AW_GET(elem) WMI_GET_BITS(elem, 16, 8) -#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_MEAS_PER_AW_SET(elem, value) WMI_SET_BITS(elem, 16, 8, value) -#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_AW_DURATION_GET(elem) WMI_GET_BITS(elem, 24, 8) -#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_AW_DURATION_SET(elem, value) WMI_SET_BITS(elem, 24, 8, value) - - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_peer_info */ - A_UINT32 tlv_header; - /** Destination mac address for measurement */ - wmi_mac_addr dest_mac; - /** Channel for ranging */ - wmi_channel channel; - /** - * request_flag - * Bit 0 : Report AP TSF - * Bit 1 : PD request - indicates a peer-to-peer Proximity Detection request - * Bits 31-2 : Reserved - */ - A_UINT32 request_flag; - A_UINT32 preamble; /** see WMI_RATE_PREAMBLE for possible values */ - /** - * Control flag - * Bit 0 : FTM requested - * Bit 1 : Asap mode - * Bit 2 : LCI Req = True/False - * Bit 3 : Location Civic Req = True/False - * Bit 4 : Trigger based (TB ranging) - * Bit 5 : Non-trigger based (NTB ranging) - * Bit 6 : I2R LMR Feedback - * Bit 7 : RSTA (Operate as the RSTA in the measurement) - * Bit 8 : Range Report - * Bit 9 : Suppress PD result - * Bits 31-10 : Reserved - */ - A_UINT32 control_flag; - A_UINT32 burst_period; /* units = 100 ms */ - /** - * Burst Information - * Bits 7-0 : num_burst_exponent - * Bits 15-8 : burst_duration - * units = IEEE 802.11 FTM burst dur encoding (250 us * 2^n) - * Bits 23-16 : ftms_per_burst - * Bits 31-24 : ftmr_retries - */ - A_UINT32 burst_info; - A_UINT32 min_time_between_measurements; /** In units of 100 us */ - A_UINT32 max_time_between_measurements; /** In units of 10 ms. */ - /** - * Availability window sub elements - * Bits 15-0 : nominal_time (in unit of 1 ms) - * Bits 23-16 : meas_per_aw - * Bits 31-24 : aw_duration (in unit of 1 ms) - */ - A_UINT32 availibility_sub_elem; -} wmi_rtt_peer_meas_req_peer_info; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_cmd_fixed_param */ - A_UINT32 tlv_header; - /** Unique request ID */ - A_UINT32 req_id; - A_UINT32 vdev_id; - /** Timeout (in ms) for the whole operation, if zero it means there's no timeout */ - A_UINT32 timeout; - /** Randomized mac address if randomization is enabled */ - wmi_mac_addr random_mac_addr; - /** - * This fixed param TLV will be followed by the below TLVs - * - wmi_rtt_peer_meas_req_peer_info rtt_peer_info[] - */ -} wmi_rtt_peer_meas_req_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_cmd_fixed_param */ - A_UINT32 tlv_header; - /** Cancel all the requests associated with this req_id */ - A_UINT32 req_id; -} wmi_rtt_peer_meas_cancel_meas_cmd_fix_param; - -typedef enum { - WMI_RTT_PEER_MEAS_STATUS_SUCCESS, /* measurement completed successfully */ - WMI_RTT_PEER_MEAS_STATUS_REFUSED, /* measurement was locally refused */ - WMI_RTT_PEER_MEAS_STATUS_TIMEOUT, /* measurement timed out */ - WMI_RTT_PEER_MEAS_STATUS_FAILURE, /* measurement failed */ -} WMI_RTT_PEER_MEAS_STATUS; - -typedef enum { - WMI_RTT_PEER_MEAS_FTM_FAILURE_UNSPECIFIED, /* unspecified failure, not used */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_NO_RESPONSE, /* no response from the FTM responder */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_REJECTED, /* FTM responder rejected measurement */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_WRONG_CHANNEL, /* peer is on a different channel */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_PEER_NOT_CAPABLE, /* peer can't actually do FTM */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_INVALID_TIMESTAMP, /* invalid T1/T4 timestamps received */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_PEER_BUSY, /* peer reports busy, may retry later */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_BAD_CHANGED_PARAMS, /* peer changed params no longer supported */ -} WMI_RTT_PEER_MEAS_FAILURE; - -typedef enum { - WMI_PEER_MEAS_TYPE_INVALID, - WMI_PEER_MEAS_TYPE_FTM, /* Fine Timing Measurement (IEEE 802.11mc / 802.11az) */ - WMI_PEER_MEAS_TYPES, - WMI_PEER_MEAS_MAX = WMI_PEER_MEAS_TYPES - 1, -} WMI_RTT_PEER_MEAS_TYPES; - -typedef enum { - WMI_RTT_GI_UNKNOWN = 0, /* default / not available */ - WMI_RTT_GI_08_US = 1, /* 0.8 µs GI */ - WMI_RTT_GI_16_US = 2, /* 1.6 µs GI (11az ranging common) */ - WMI_RTT_GI_32_US = 3, /* 3.2 µs GI */ - WMI_RTT_GI_ZERO_POWER = 4, /* "zero power GI" (secure LTF behavior) */ -} WMI_RTT_GI_TYPE; - -typedef enum { - WMI_PEER_AUTHORIZE_CLEAR = 0, - WMI_PEER_AUTHORIZE_SECURED_MODE = 1, - WMI_PEER_AUTHORIZE_OPEN_MODE = 2, - WMI_PEER_AUTHORIZE_SW_ENCRYPTION_MODE = 3, -} WMI_PEER_AUTHORIZE_TYPE; - -/* - * macros to set/get bitfields within - * wmi_rtt_peer_meas_report_peer_meas_result_info - */ -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_FINAL_GET(flags) WMI_GET_BITS(flags, 0, 1) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_FINAL_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_TB_RANGING_GET(flags) WMI_GET_BITS(flags, 1, 1) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_TB_RANGING_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_NTB_RANGING_GET(flags) WMI_GET_BITS(flags, 2, 1) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_NTB_RANGING_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_AP_TSF_VALID_GET(flags) WMI_GET_BITS(flags, 3, 1) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_AP_TSF_VALID_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_IS_DELAYED_LMR_GET(flags) WMI_GET_BITS(flags, 4, 1) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_IS_DELAYED_LMR_SET(flags, value) WMI_SET_BITS(flags, 4, 1, value) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_MEAS_TYPE_GET(flags) WMI_GET_BITS(flags, 5, 1) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_MEAS_TYPE_SET(flags, value) WMI_SET_BITS(flags, 5, 1, value) - -#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_BURST_INDEX_GET(info) WMI_GET_BITS(info, 0, 16) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_BURST_INDEX_SET(info, value) WMI_SET_BITS(info, 0, 16, value) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_NUM_BURSTS_EXP_GET(info) WMI_GET_BITS(info, 16, 8) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_NUM_BURSTS_EXP_SET(info, value) WMI_SET_BITS(info, 16, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_BUSY_RETRY_TIME_GET(info) WMI_GET_BITS(info, 24, 8) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_BUSY_RETRY_TIME_SET(info, value) WMI_SET_BITS(info, 24, 8, value) - -#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_BURST_PERIOD_GET(params) WMI_GET_BITS(params, 0, 16) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_BURST_PERIOD_SET(params, value) WMI_SET_BITS(params, 0, 16, value) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_BURST_DURATION_GET(params) WMI_GET_BITS(params, 16, 8) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_BURST_DURATION_SET(params, value) WMI_SET_BITS(params, 16, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_FTMS_PER_BURST_GET(params) WMI_GET_BITS(params, 24, 8) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_FTMS_PER_BURST_SET(params, value) WMI_SET_BITS(params, 24, 8, value) - -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_I2R_REP_GET(params) WMI_GET_BITS(params, 0, 8) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_I2R_REP_SET(params, value) WMI_SET_BITS(params, 0, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_R2I_REP_GET(params) WMI_GET_BITS(params, 8, 8) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_R2I_REP_SET(params, value) WMI_SET_BITS(params, 8, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_I2R_STS_GET(params) WMI_GET_BITS(params, 16, 8) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_I2R_STS_SET(params, value) WMI_SET_BITS(params, 16, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_R2I_STS_GET(params) WMI_GET_BITS(params, 24, 8) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_R2I_STS_SET(params, value) WMI_SET_BITS(params, 24, 8, value) - -#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_NOMINAL_TIME_MS_GET(params) WMI_GET_BITS(params, 0, 16) -#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_NOMINAL_TIME_MS_SET(params, value) WMI_SET_BITS(params, 0, 16, value) -#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_MEAS_PER_AW_GET(params) WMI_GET_BITS(params, 16, 8) -#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_MEAS_PER_AW_SET(params, value) WMI_SET_BITS(params, 16, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_AW_DURATION_GET(params) WMI_GET_BITS(params, 24, 8) -#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_AW_DURATION_SET(params, value) WMI_SET_BITS(params, 24, 8, value) - -#define WMI_RTT_PEER_MEAS_REPORT_CHAN_CODE_BW_GET(code) WMI_GET_BITS(code, 0, 8) -#define WMI_RTT_PEER_MEAS_REPORT_CHAN_CODE_BW_SET(code, value) WMI_SET_BITS(code, 0, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_CHAN_CODE_PREAMBLE_GET(code) WMI_GET_BITS(code, 8, 8) -#define WMI_RTT_PEER_MEAS_REPORT_CHAN_CODE_PREAMBLE_SET(code, value) WMI_SET_BITS(code, 8, 8, value) - -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_MCS_IDX_GET(info) WMI_GET_BITS(info, 0, 8) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_MCS_IDX_SET(info, value) WMI_SET_BITS(info, 0, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_NSS_GET(info) WMI_GET_BITS(info, 8, 4) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_NSS_SET(info, value) WMI_SET_BITS(info, 8, 4, value) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_BW_GET(info) WMI_GET_BITS(info, 12, 4) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_BW_SET(info, value) WMI_SET_BITS(info, 12, 4, value) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_GI_GET(info) WMI_GET_BITS(info, 16, 8) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_GI_SET(info, value) WMI_SET_BITS(info, 16, 8, value) - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_peer_meas_result_info */ - A_UINT32 tlv_header; - /** Destination mac address for measurement */ - wmi_mac_addr dest_mac; - /** Measurement status and reason */ - A_UINT32 status; /** refer WMI_RTT_PEER_MEAS_STATUS */ - A_UINT32 ftm_failure_reason; /** refer WMI_RTT_PEER_MEAS_STATUS */ - /** - * Result flag - * Bit 0 : final : 1 => this is last response for this peer/session - * Bit 1 : tb_ranging : 1 => if this is TB ranging - * Bit 2 : ntb_ranging : 1 => if this is NTB ranging - * Bit 3 : ap_tsf_valid : 1 => ap_tsf field is valid - * Bit 4 : is_delayed_lmr : 1 => reported LMR belongs to previous burst - * Bit 5 : meas_type : WMI_PEER_MEAS_TYPES (e.g. FTM) - * Bits 31-6 : Reserved - */ - A_UINT32 result_flag; - /** FTM Burst Counts */ - A_UINT32 num_ftmr_attempts; /** Number of FTM request frames transmitted */ - A_UINT32 num_ftmr_successes; /** Number of FTM request frames ACKed */ - /** - * Burst Info - * Bits 15-0 : burst_index [0..num_bursts-1] - * Bits 23-16 : num_bursts_exp (Negotiated num bursts exponent) - * Bits 31-24 : busy_retry_time (In seconds, if peer was busy) - */ - A_UINT32 burst_info; - /** - * Negotiated/Actual Burst Parameters - * Bits 15-0 : burst_period (In units of 100ms) - * Bits 23-16 : burst_duration (Actual burst duration negotiated) - * Bits 31-24 : ftms_per_burst (Actual FTMs per burst negotiated) - */ - A_UINT32 burst_params; - - /** AP TSF at measurement time (valid if ap_tsf_valid=1) */ - struct { - A_UINT32 ap_tsf_l32; - A_UINT32 ap_tsf_h32; - } ap_tsf; - - /** optional legacy 32-bit TSF when measurement started */ - A_UINT32 meas_start_tsf; - - /** RSSI Information */ - struct { - A_INT32 rssi_avg_dbm; - A_INT32 rssi_spread_db; - } rssi; - - /** RTT statistics (units: picoseconds) */ - struct { - union { - A_INT64 value; /* for use by target only */ - struct { - A_UINT32 value_l32; - A_UINT32 value_h32; - } part; - } rtt_avg_ps; - union { - A_INT64 value; /* for use by target only */ - struct { - A_UINT32 value_l32; - A_UINT32 value_h32; - } part; - } rtt_variance_ps; - union { - A_INT64 value; /* for use by target only */ - struct { - A_UINT32 value_l32; - A_UINT32 value_h32; - } part; - } rtt_spread_ps; - } rtt; - - /** Distance statistics (units: millimeters) */ - struct { - union { - A_INT64 value; /* for use by target only */ - struct { - A_UINT32 value_l32; - A_UINT32 value_h32; - } part; - } dist_avg_mm; - union { - A_INT64 value; /* for use by target only */ - struct { - A_UINT32 value_l32; - A_UINT32 value_h32; - } part; - } dist_variance_mm; - union { - A_INT64 value; /* for use by target only */ - struct { - A_UINT32 value_l32; - A_UINT32 value_h32; - } part; - } dist_spread_mm; - } dist; - - /** - * Negotiated/Actual 11az params - * Bits 7-0 : max_i2r_repetition - * Bits 15-8 : max_r2i_repetition - * Bits 23-16 : max_i2r_sts - * Bits 31-24 : max_r2i_sts - */ - A_UINT32 ftm_11az_params; - A_UINT32 min_time_between_measurements; /** In units of 100 us */ - A_UINT32 max_time_between_measurements; /** In units of 10 ms */ - - /** - * Negotiated/Actual avail windows params - * Bits 15-0 : nominal_time_ms (In units of 1 ms) - * Bits 23-16 : measurements_per_aw - * Bits 31-24 : aw_duration (In units of 1 ms) - */ - A_UINT32 avail_window_params; - - /** - * Negotiated/Actual FTM IE channel code - * Bits 7-0 : chan_bw (refer wmi_channel_width) - * Bits 15-8 : preamble (refer WMI_RATE_PREAMBLE) - * Bits 31-16 : reserved - */ - A_UINT32 ftm_ie_channel_code; - - /** - * Tx/Rx Rate Info - * Bits 7-0 : rateMcsIdx - OFDM/CCK rate code would be as per IEEE standard in the units of 0.5mbps - * - HT/VHT/HE it would be mcs index - * Bits 11-8 : Nss (1*1, 2*2, 3*3, 4*4) - * Bits 15-12 : Rx packet BW (0-20 Mhz, 1 - 40 Mhz, 2 - 80 Mhz, 3 - 160 Mhz, 4 - 320 Mhz) - * Bits 23-16 : gi (refer WMI_RTT_GI_TYPE) - * Bits 31-24 : Reserved - */ - A_UINT32 tx_rate_info_1; - A_UINT32 rx_rate_info_1; - - /** bits 31:0: TX/RX Bit rate in 100kbps */ - A_UINT32 tx_rate_info_2; - A_UINT32 rx_rate_info_2; -} wmi_rtt_peer_meas_report_peer_meas_result_info; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_event_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 req_id; /** Unique Identifier */ - A_UINT32 vdev_id; - /** - * This fixed param TLV will be followed by the below TLVs - * - wmi_rtt_peer_meas_report_peer_meas_result_info peer_meas_info[] - */ -} wmi_rtt_peer_meas_report_event_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_athdiag_read_write_cmd_fixed_param */ - A_UINT32 tlv_header; - /* register offset to read or write using ath diag */ - A_UINT32 offset; - /** - * Number of bytes to read from or write to 'offset'. - * - * For a read: FW returns exactly 'data_length' bytes in the event. - * For a write: Host sends exactly 'data_length' bytes in the data TLV. - */ - A_UINT32 data_length; - /** - * mem_type: - * Indicates the type of memory being accessed. - */ - A_UINT32 mem_type; - /** - * is_write: - * Distinguishes between a read and a write operation. - * - * 0 = READ FW reads 'data_length' bytes from 'offset'. - * No data TLV is appended to this command. - * - * 1 = WRITE FW writes 'data_length' bytes to 'offset'. - * A WMITLV_TAG_ARRAY_BYTE TLV with the write payload - * is appended to this command. - */ - A_UINT32 is_write; -} wmi_athdiag_read_write_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_athdiag_read_write_event_fixed_param */ - A_UINT32 tlv_header; - /** - * Number of bytes to read from or write to 'offset'. - * - * For a read: FW returns exactly 'data_length' bytes in the event. - * For a write: Host sends exactly 'data_length' bytes in the data TLV. - */ - A_UINT32 data_length; - /** - * status: - * Result of the read or write operation performed by FW. - * - * 0 = Success operation completed without error. - * non-zero = Failure FW-defined error codes. - */ - A_UINT32 status; - /** - * is_write: - * Echoed back from the corresponding WMI_ATHDIAG_READ_WRITE_CMDID. - * - * 0 = READ response data TLV with 'data_length' bytes follows - * (only when status == 0) - * 1 = WRITE response no data TLV appended; check 'status' only - */ - A_UINT32 is_write; - /* - * This fixed_param TLV is followed by the following TLVs: - * - A_UINT8 data[] (WMITLV_TAG_ARRAY_BYTE) - * For READ response (is_write == 0): read data, data_length bytes. - * Present only when status == 0. - * For WRITE response (is_write == 1): not present. - */ -} wmi_athdiag_read_write_event_fixed_param; - - /* ADD NEW DEFS HERE */ diff --git a/drivers/staging/fw-api/fw/wmi_version.h b/drivers/staging/fw-api/fw/wmi_version.h index 4efa48281edb..145e8fcc2aa4 100644 --- a/drivers/staging/fw-api/fw/wmi_version.h +++ b/drivers/staging/fw-api/fw/wmi_version.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1781 +#define __WMI_REVISION_ 1575 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work diff --git a/drivers/staging/fw-api/hw/fig/v1/HALcomdef.h b/drivers/staging/fw-api/hw/fig/v1/HALcomdef.h deleted file mode 100644 index fd5cc2f41dcb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/HALcomdef.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef HAL_COMDEF_H -#define HAL_COMDEF_H - -#ifndef _ARM_ASM_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "com_dtypes.h" - -#ifndef _BOOL32_DEFINED -typedef unsigned long int bool32; -#define _BOOL32_DEFINED -#endif - -#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF - - #define inp(port) (*((volatile byte *) (port))) - #define inpw(port) (*((volatile word *) (port))) - #define inpdw(port) (*((volatile dword *)(port))) - - #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) - #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) - #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) - -#ifdef __cplusplus -} -#endif - -#endif - -#endif - diff --git a/drivers/staging/fw-api/hw/fig/v1/HALhwio.h b/drivers/staging/fw-api/hw/fig/v1/HALhwio.h deleted file mode 100644 index 53f7d7ef21e5..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/HALhwio.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef HAL_HWIO_H -#define HAL_HWIO_H - -#include "HALcomdef.h" - -#define HWIO_BASE_PTR(base) base##_BASE_PTR - -#ifdef __ARMCC_VERSION - #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) -#else - #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) -#endif - -#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) -#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) -#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) -#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) - -#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) -#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) -#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) -#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) -#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) -#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) -#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) - -#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) -#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) -#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) -#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) -#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) -#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) -#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) - -#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) -#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) -#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) -#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) - -#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) -#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) -#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) -#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) - -#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) - -#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) -#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) -#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) -#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) -#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) -#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) -#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) - -#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) - -#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) -#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) -#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) -#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) - -#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) -#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) -#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) -#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) - -#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) - -#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) - -#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) -#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) -#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) -#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) - -#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) -#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) -#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) -#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) -#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) -#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) -#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) - -#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) -#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) -#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) - -#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) - -#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) - -#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) -#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) -#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) -#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) -#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) -#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) -#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) -#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) - -#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) -#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) - -#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN -#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) -#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) -#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) -#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) -#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) -#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) -#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) -#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) -#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) -#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) -#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) -#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) -#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) -#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) -#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) -#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR -#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) -#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) -#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) -#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS -#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) -#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) -#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) -#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS -#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) -#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) -#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) -#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK -#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) -#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK -#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT -#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT -#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow -#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) -#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL - -#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) -#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) -#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) -#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) -#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) -#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) -#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) -#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) -#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) -#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) -#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) -#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) -#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) -#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ - HWIO_##hwiosym##_OUTM(base, mask1, val1); \ - HWIO_##hwiosym##_OUTM(base, mask2, val2); \ - } -#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ - HWIO_##hwiosym##_OUTM(base, mask1, val1); \ - HWIO_##hwiosym##_OUTM(base, mask2, val2); \ - HWIO_##hwiosym##_OUTM(base, mask3, val3); \ - } -#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ - HWIO_##hwiosym##_OUTM(base, mask1, val1); \ - HWIO_##hwiosym##_OUTM(base, mask2, val2); \ - HWIO_##hwiosym##_OUTM(base, mask3, val3); \ - HWIO_##hwiosym##_OUTM(base, mask4, val4); \ - } - -#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) -#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) -#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) -#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) -#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) -#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) -#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) -#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) -#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) -#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) -#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) - -#define HWIO_INTLOCK() -#define HWIO_INTFREE() - -#define __inp(port) (*((volatile uint8 *) (port))) -#define __inpw(port) (*((volatile uint16 *) (port))) -#define __inpdw(port) (*((volatile uint32 *) (port))) -#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) -#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) -#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) - -#ifdef HAL_HWIO_EXTERNAL - -#undef __inp -#undef __inpw -#undef __inpdw -#undef __outp -#undef __outpw -#undef __outpdw - -#define __inp(port) __inp_extern(port) -#define __inpw(port) __inpw_extern(port) -#define __inpdw(port) __inpdw_extern(port) -#define __outp(port, val) __outp_extern(port, val) -#define __outpw(port, val) __outpw_extern(port, val) -#define __outpdw(port, val) __outpdw_extern(port, val) - -extern uint8 __inp_extern ( uint32 nAddr ); -extern uint16 __inpw_extern ( uint32 nAddr ); -extern uint32 __inpdw_extern ( uint32 nAddr ); -extern void __outp_extern ( uint32 nAddr, uint8 nData ); -extern void __outpw_extern ( uint32 nAddr, uint16 nData ); -extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); - -#endif - -#define in_byte(addr) (__inp(addr)) -#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) -#define out_byte(addr, val) __outp(addr,val) -#define out_byte_masked(io, mask, val, shadow) \ - HWIO_INTLOCK(); \ - out_byte( io, shadow); \ - shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ - HWIO_INTFREE() -#define out_byte_masked_ns(io, mask, val, current_reg_content) \ - out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ - ((uint16)((val) & (mask)))) ) - -#define in_word(addr) (__inpw(addr)) -#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) -#define out_word(addr, val) __outpw(addr,val) -#define out_word_masked(io, mask, val, shadow) \ - HWIO_INTLOCK( ); \ - shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ - out_word( io, shadow); \ - HWIO_INTFREE( ) -#define out_word_masked_ns(io, mask, val, current_reg_content) \ - out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ - ((uint16)((val) & (mask)))) ) - -#define in_dword(addr) (__inpdw(addr)) -#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) -#define out_dword(addr, val) __outpdw(addr,val) -#define out_dword_masked(io, mask, val, shadow) \ - HWIO_INTLOCK(); \ - shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ - out_dword( io, shadow); \ - HWIO_INTFREE() -#define out_dword_masked_ns(io, mask, val, current_reg_content) \ - out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ - ((uint32)((val) & (mask)))) ) - -#endif - diff --git a/drivers/staging/fw-api/hw/fig/v1/ack_report.h b/drivers/staging/fw-api/hw/fig/v1/ack_report.h deleted file mode 100644 index e78921b308fd..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/ack_report.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _ACK_REPORT_H_ -#define _ACK_REPORT_H_ - -#define NUM_OF_DWORDS_ACK_REPORT 1 - -struct ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t selfgen_response_reason : 4, - ax_trigger_type : 4, - sr_ppdu : 1, - reserved : 7, - frame_control : 16; -#else - uint32_t frame_control : 16, - reserved : 7, - sr_ppdu : 1, - ax_trigger_type : 4, - selfgen_response_reason : 4; -#endif -}; - -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f - -#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 -#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 -#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 -#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 - -#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 -#define ACK_REPORT_SR_PPDU_LSB 8 -#define ACK_REPORT_SR_PPDU_MSB 8 -#define ACK_REPORT_SR_PPDU_MASK 0x00000100 - -#define ACK_REPORT_RESERVED_OFFSET 0x00000000 -#define ACK_REPORT_RESERVED_LSB 9 -#define ACK_REPORT_RESERVED_MSB 15 -#define ACK_REPORT_RESERVED_MASK 0x0000fe00 - -#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 -#define ACK_REPORT_FRAME_CONTROL_LSB 16 -#define ACK_REPORT_FRAME_CONTROL_MSB 31 -#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/boron_top_reg.h b/drivers/staging/fw-api/hw/fig/v1/boron_top_reg.h deleted file mode 100644 index 306398284fe3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/boron_top_reg.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef BORON_TOP_REG_H -#define BORON_TOP_REG_H - -#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C) -#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050) - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/buffer_addr_info.h b/drivers/staging/fw-api/hw/fig/v1/buffer_addr_info.h deleted file mode 100644 index d65375b54715..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/buffer_addr_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _BUFFER_ADDR_INFO_H_ -#define _BUFFER_ADDR_INFO_H_ - -#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 - -struct buffer_addr_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_addr_31_0 : 32; - uint32_t buffer_addr_39_32 : 8, - return_buffer_manager : 4, - sw_buffer_cookie : 20; -#else - uint32_t buffer_addr_31_0 : 32; - uint32_t sw_buffer_cookie : 20, - return_buffer_manager : 4, - buffer_addr_39_32 : 8; -#endif -}; - -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/ce_src_desc.h b/drivers/staging/fw-api/hw/fig/v1/ce_src_desc.h deleted file mode 100644 index 4ecaedcab2a7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/ce_src_desc.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _CE_SRC_DESC_H_ -#define _CE_SRC_DESC_H_ - -#define NUM_OF_DWORDS_CE_SRC_DESC 4 - -struct ce_src_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t src_buffer_low : 32; - uint32_t src_buffer_high : 8, - toeplitz_en : 1, - src_swap : 1, - dest_swap : 1, - gather : 1, - ce_res_0 : 1, - barrier_read : 1, - ce_res_1 : 2, - length : 16; - uint32_t fw_metadata : 16, - ce_res_2 : 16; - uint32_t ce_res_3 : 20, - ring_id : 8, - looping_count : 4; -#else - uint32_t src_buffer_low : 32; - uint32_t length : 16, - ce_res_1 : 2, - barrier_read : 1, - ce_res_0 : 1, - gather : 1, - dest_swap : 1, - src_swap : 1, - toeplitz_en : 1, - src_buffer_high : 8; - uint32_t ce_res_2 : 16, - fw_metadata : 16; - uint32_t looping_count : 4, - ring_id : 8, - ce_res_3 : 20; -#endif -}; - -#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000 -#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0 -#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31 -#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff - -#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff - -#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004 -#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8 -#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8 -#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100 - -#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004 -#define CE_SRC_DESC_SRC_SWAP_LSB 9 -#define CE_SRC_DESC_SRC_SWAP_MSB 9 -#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200 - -#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004 -#define CE_SRC_DESC_DEST_SWAP_LSB 10 -#define CE_SRC_DESC_DEST_SWAP_MSB 10 -#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400 - -#define CE_SRC_DESC_GATHER_OFFSET 0x00000004 -#define CE_SRC_DESC_GATHER_LSB 11 -#define CE_SRC_DESC_GATHER_MSB 11 -#define CE_SRC_DESC_GATHER_MASK 0x00000800 - -#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004 -#define CE_SRC_DESC_CE_RES_0_LSB 12 -#define CE_SRC_DESC_CE_RES_0_MSB 12 -#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000 - -#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004 -#define CE_SRC_DESC_BARRIER_READ_LSB 13 -#define CE_SRC_DESC_BARRIER_READ_MSB 13 -#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000 - -#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004 -#define CE_SRC_DESC_CE_RES_1_LSB 14 -#define CE_SRC_DESC_CE_RES_1_MSB 15 -#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000 - -#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004 -#define CE_SRC_DESC_LENGTH_LSB 16 -#define CE_SRC_DESC_LENGTH_MSB 31 -#define CE_SRC_DESC_LENGTH_MASK 0xffff0000 - -#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008 -#define CE_SRC_DESC_FW_METADATA_LSB 0 -#define CE_SRC_DESC_FW_METADATA_MSB 15 -#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff - -#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008 -#define CE_SRC_DESC_CE_RES_2_LSB 16 -#define CE_SRC_DESC_CE_RES_2_MSB 31 -#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000 - -#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c -#define CE_SRC_DESC_CE_RES_3_LSB 0 -#define CE_SRC_DESC_CE_RES_3_MSB 19 -#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff - -#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c -#define CE_SRC_DESC_RING_ID_LSB 20 -#define CE_SRC_DESC_RING_ID_MSB 27 -#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000 - -#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c -#define CE_SRC_DESC_LOOPING_COUNT_LSB 28 -#define CE_SRC_DESC_LOOPING_COUNT_MSB 31 -#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/ce_stat_desc.h b/drivers/staging/fw-api/hw/fig/v1/ce_stat_desc.h deleted file mode 100644 index 0b9f9a221215..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/ce_stat_desc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _CE_STAT_DESC_H_ -#define _CE_STAT_DESC_H_ - -#define NUM_OF_DWORDS_CE_STAT_DESC 4 - -struct ce_stat_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ce_res_5 : 8, - toeplitz_en : 1, - src_swap : 1, - dest_swap : 1, - gather : 1, - barrier_read : 1, - ce_res_6 : 3, - length : 16; - uint32_t toeplitz_hash_0 : 32; - uint32_t toeplitz_hash_1 : 32; - uint32_t fw_metadata : 16, - ce_res_7 : 4, - ring_id : 8, - looping_count : 4; -#else - uint32_t length : 16, - ce_res_6 : 3, - barrier_read : 1, - gather : 1, - dest_swap : 1, - src_swap : 1, - toeplitz_en : 1, - ce_res_5 : 8; - uint32_t toeplitz_hash_0 : 32; - uint32_t toeplitz_hash_1 : 32; - uint32_t looping_count : 4, - ring_id : 8, - ce_res_7 : 4, - fw_metadata : 16; -#endif -}; - -#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000 -#define CE_STAT_DESC_CE_RES_5_LSB 0 -#define CE_STAT_DESC_CE_RES_5_MSB 7 -#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff - -#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000 -#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8 -#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8 -#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100 - -#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000 -#define CE_STAT_DESC_SRC_SWAP_LSB 9 -#define CE_STAT_DESC_SRC_SWAP_MSB 9 -#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200 - -#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000 -#define CE_STAT_DESC_DEST_SWAP_LSB 10 -#define CE_STAT_DESC_DEST_SWAP_MSB 10 -#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400 - -#define CE_STAT_DESC_GATHER_OFFSET 0x00000000 -#define CE_STAT_DESC_GATHER_LSB 11 -#define CE_STAT_DESC_GATHER_MSB 11 -#define CE_STAT_DESC_GATHER_MASK 0x00000800 - -#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000 -#define CE_STAT_DESC_BARRIER_READ_LSB 12 -#define CE_STAT_DESC_BARRIER_READ_MSB 12 -#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000 - -#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000 -#define CE_STAT_DESC_CE_RES_6_LSB 13 -#define CE_STAT_DESC_CE_RES_6_MSB 15 -#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000 - -#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000 -#define CE_STAT_DESC_LENGTH_LSB 16 -#define CE_STAT_DESC_LENGTH_MSB 31 -#define CE_STAT_DESC_LENGTH_MASK 0xffff0000 - -#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff - -#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff - -#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c -#define CE_STAT_DESC_FW_METADATA_LSB 0 -#define CE_STAT_DESC_FW_METADATA_MSB 15 -#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff - -#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c -#define CE_STAT_DESC_CE_RES_7_LSB 16 -#define CE_STAT_DESC_CE_RES_7_MSB 19 -#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000 - -#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c -#define CE_STAT_DESC_RING_ID_LSB 20 -#define CE_STAT_DESC_RING_ID_MSB 27 -#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000 - -#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c -#define CE_STAT_DESC_LOOPING_COUNT_LSB 28 -#define CE_STAT_DESC_LOOPING_COUNT_MSB 31 -#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/coex_rx_status.h b/drivers/staging/fw-api/hw/fig/v1/coex_rx_status.h deleted file mode 100644 index 7d9c6b4d2057..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/coex_rx_status.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_RX_STATUS_H_ -#define _COEX_RX_STATUS_H_ - -#define NUM_OF_DWORDS_COEX_RX_STATUS 2 - -#define NUM_OF_QWORDS_COEX_RX_STATUS 1 - -struct coex_rx_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_mac_frame_status : 2, - rx_with_tx_response : 1, - rx_rate : 5, - rx_bw : 3, - single_mpdu : 1, - filter_status : 1, - ampdu : 1, - directed : 1, - reserved_0 : 1, - rx_nss : 3, - rx_rssi : 8, - rx_type : 3, - retry_bit_setting : 1, - more_data_bit_setting : 1; - uint32_t remain_rx_packet_time : 16, - rx_remaining_fes_time : 16; -#else - uint32_t more_data_bit_setting : 1, - retry_bit_setting : 1, - rx_type : 3, - rx_rssi : 8, - rx_nss : 3, - reserved_0 : 1, - directed : 1, - ampdu : 1, - filter_status : 1, - single_mpdu : 1, - rx_bw : 3, - rx_rate : 5, - rx_with_tx_response : 1, - rx_mac_frame_status : 2; - uint32_t rx_remaining_fes_time : 16, - remain_rx_packet_time : 16; -#endif -}; - -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 - -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 - -#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_RATE_LSB 3 -#define COEX_RX_STATUS_RX_RATE_MSB 7 -#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 - -#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_BW_LSB 8 -#define COEX_RX_STATUS_RX_BW_MSB 10 -#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 - -#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 -#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 -#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 - -#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 -#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 -#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 - -#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_AMPDU_LSB 13 -#define COEX_RX_STATUS_AMPDU_MSB 13 -#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 - -#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_DIRECTED_LSB 14 -#define COEX_RX_STATUS_DIRECTED_MSB 14 -#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 - -#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RESERVED_0_LSB 15 -#define COEX_RX_STATUS_RESERVED_0_MSB 15 -#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 - -#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_NSS_LSB 16 -#define COEX_RX_STATUS_RX_NSS_MSB 18 -#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 - -#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_RSSI_LSB 19 -#define COEX_RX_STATUS_RX_RSSI_MSB 26 -#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 - -#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_TYPE_LSB 27 -#define COEX_RX_STATUS_RX_TYPE_MSB 29 -#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 - -#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 - -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 - -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 - -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/coex_tx_req.h b/drivers/staging/fw-api/hw/fig/v1/coex_tx_req.h deleted file mode 100644 index ed5b4c57bfd8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/coex_tx_req.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_TX_REQ_H_ -#define _COEX_TX_REQ_H_ - -#define NUM_OF_DWORDS_COEX_TX_REQ 6 - -#define NUM_OF_QWORDS_COEX_TX_REQ 3 - -struct coex_tx_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_pwr : 8, - min_tx_pwr : 8, - nss : 3, - tx_chain_mask : 8, - bw : 3, - reserved_0 : 2; - uint32_t alt_tx_pwr : 8, - alt_min_tx_pwr : 8, - alt_nss : 3, - alt_tx_chain_mask : 8, - alt_bw : 3, - reserved_1 : 2; - uint32_t tx_pwr_1 : 8, - alt_tx_pwr_1 : 8, - wlan_request_duration : 16; - uint32_t wlan_pkt_type : 4, - coex_tx_reason : 2, - response_frame_type : 5, - wlan_low_priority_slicing_allowed : 1, - wlan_high_priority_slicing_allowed : 1, - sch_tx_burst_ongoing : 1, - coex_tx_priority : 4, - blackout_details_en : 1, - blackout_peek_duration : 8, - reserved_3a : 5; - uint32_t frequency_channel_bonding_mask : 16, - num_blackout_windows : 8, - reserved_4a : 8; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0 : 2, - bw : 3, - tx_chain_mask : 8, - nss : 3, - min_tx_pwr : 8, - tx_pwr : 8; - uint32_t reserved_1 : 2, - alt_bw : 3, - alt_tx_chain_mask : 8, - alt_nss : 3, - alt_min_tx_pwr : 8, - alt_tx_pwr : 8; - uint32_t wlan_request_duration : 16, - alt_tx_pwr_1 : 8, - tx_pwr_1 : 8; - uint32_t reserved_3a : 5, - blackout_peek_duration : 8, - blackout_details_en : 1, - coex_tx_priority : 4, - sch_tx_burst_ongoing : 1, - wlan_high_priority_slicing_allowed : 1, - wlan_low_priority_slicing_allowed : 1, - response_frame_type : 5, - coex_tx_reason : 2, - wlan_pkt_type : 4; - uint32_t reserved_4a : 8, - num_blackout_windows : 8, - frequency_channel_bonding_mask : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_TX_PWR_LSB 0 -#define COEX_TX_REQ_TX_PWR_MSB 7 -#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff - -#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 -#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 -#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_NSS_LSB 16 -#define COEX_TX_REQ_NSS_MSB 18 -#define COEX_TX_REQ_NSS_MASK 0x0000000000070000 - -#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 -#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 -#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_BW_LSB 27 -#define COEX_TX_REQ_BW_MSB 29 -#define COEX_TX_REQ_BW_MASK 0x0000000038000000 - -#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_RESERVED_0_LSB 30 -#define COEX_TX_REQ_RESERVED_0_MSB 31 -#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000 - -#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_TX_PWR_LSB 32 -#define COEX_TX_REQ_ALT_TX_PWR_MSB 39 -#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_NSS_LSB 48 -#define COEX_TX_REQ_ALT_NSS_MSB 50 -#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000 - -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_BW_LSB 59 -#define COEX_TX_REQ_ALT_BW_MSB 61 -#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000 - -#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_RESERVED_1_LSB 62 -#define COEX_TX_REQ_RESERVED_1_MSB 63 -#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000 - -#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_TX_PWR_1_LSB 0 -#define COEX_TX_REQ_TX_PWR_1_MSB 7 -#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff - -#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 -#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 -#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00 - -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000 - -#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32 -#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35 -#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000 - -#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_COEX_TX_REASON_LSB 36 -#define COEX_TX_REQ_COEX_TX_REASON_MSB 37 -#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000 - -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000 - -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000 - -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000 - -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000 - -#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46 -#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49 -#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000 - -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_LSB 50 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MSB 50 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MASK 0x0004000000000000 - -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_LSB 51 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MSB 58 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MASK 0x07f8000000000000 - -#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_RESERVED_3A_LSB 59 -#define COEX_TX_REQ_RESERVED_3A_MSB 63 -#define COEX_TX_REQ_RESERVED_3A_MASK 0xf800000000000000 - -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_LSB 0 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MSB 15 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MASK 0x000000000000ffff - -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_LSB 16 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MSB 23 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MASK 0x0000000000ff0000 - -#define COEX_TX_REQ_RESERVED_4A_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_RESERVED_4A_LSB 24 -#define COEX_TX_REQ_RESERVED_4A_MSB 31 -#define COEX_TX_REQ_RESERVED_4A_MASK 0x00000000ff000000 - -#define COEX_TX_REQ_TLV64_PADDING_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_TLV64_PADDING_LSB 32 -#define COEX_TX_REQ_TLV64_PADDING_MSB 63 -#define COEX_TX_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/coex_tx_status.h b/drivers/staging/fw-api/hw/fig/v1/coex_tx_status.h deleted file mode 100644 index c47c29c2a5ba..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/coex_tx_status.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_TX_STATUS_H_ -#define _COEX_TX_STATUS_H_ - -#define NUM_OF_DWORDS_COEX_TX_STATUS 4 - -#define NUM_OF_QWORDS_COEX_TX_STATUS 2 - -struct coex_tx_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 7, - tx_bw : 3, - tx_status_reason : 3, - tx_wait_ack : 1, - fes_tx_is_gen_frame : 1, - sch_tx_burst_ongoing : 1, - current_tx_duration : 16; - uint32_t next_rx_active_time : 16, - remaining_fes_time : 16; - uint32_t tx_antenna_mask : 8, - shared_ant_tx_pwr : 8, - other_ant_tx_pwr : 8, - reserved_2 : 8; - uint32_t tlv64_padding : 32; -#else - uint32_t current_tx_duration : 16, - sch_tx_burst_ongoing : 1, - fes_tx_is_gen_frame : 1, - tx_wait_ack : 1, - tx_status_reason : 3, - tx_bw : 3, - reserved_0a : 7; - uint32_t remaining_fes_time : 16, - next_rx_active_time : 16; - uint32_t reserved_2 : 8, - other_ant_tx_pwr : 8, - shared_ant_tx_pwr : 8, - tx_antenna_mask : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_RESERVED_0A_LSB 0 -#define COEX_TX_STATUS_RESERVED_0A_MSB 6 -#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f - -#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_BW_LSB 7 -#define COEX_TX_STATUS_TX_BW_MSB 9 -#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 - -#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 -#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 -#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 - -#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 -#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 -#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 - -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 - -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 - -#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 - -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 - -#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 -#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 -#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 - -#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff - -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 - -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 - -#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_RESERVED_2_LSB 24 -#define COEX_TX_STATUS_RESERVED_2_MSB 31 -#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 - -#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_TLV64_PADDING_LSB 32 -#define COEX_TX_STATUS_TLV64_PADDING_MSB 63 -#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/com_dtypes.h b/drivers/staging/fw-api/hw/fig/v1/com_dtypes.h deleted file mode 100644 index a122ca419081..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/com_dtypes.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef COM_DTYPES_H -#define COM_DTYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef T_WINNT - #ifndef WIN32 - #define WIN32 - #endif - #include -#endif - -#ifdef TRUE -#undef TRUE -#endif - -#ifdef FALSE -#undef FALSE -#endif - -#define TRUE 1 -#define FALSE 0 - -#define ON 1 -#define OFF 0 - -#ifndef NULL - #define NULL 0 -#endif - -#ifndef _ARM_ASM_ -#ifndef _BOOLEAN_DEFINED - -typedef unsigned char boolean; -#define _BOOLEAN_DEFINED -#endif - -#if defined(DALSTDDEF_H) -#define _BOOLEAN_DEFINED -#define _UINT32_DEFINED -#define _UINT16_DEFINED -#define _UINT8_DEFINED -#define _INT32_DEFINED -#define _INT16_DEFINED -#define _INT8_DEFINED -#define _UINT64_DEFINED -#define _INT64_DEFINED -#define _BYTE_DEFINED -#endif - -#ifndef _UINT32_DEFINED - -typedef unsigned int uint32; -#define _UINT32_DEFINED -#endif - -#ifndef _UINT16_DEFINED - -typedef unsigned short uint16; -#define _UINT16_DEFINED -#endif - -#ifndef _UINT8_DEFINED - -typedef unsigned char uint8; -#define _UINT8_DEFINED -#endif - -#ifndef _INT32_DEFINED - -typedef signed int int32; -#define _INT32_DEFINED -#endif - -#ifndef _INT16_DEFINED - -typedef signed short int16; -#define _INT16_DEFINED -#endif - -#ifndef _INT8_DEFINED - -typedef signed char int8; -#define _INT8_DEFINED -#endif - -#ifndef _BYTE_DEFINED - -typedef unsigned char byte; -#define _BYTE_DEFINED -#endif - -typedef unsigned short word; - -typedef unsigned long dword; - -typedef unsigned char uint1; - -typedef unsigned short uint2; - -typedef unsigned long uint4; - -typedef signed char int1; - -typedef signed short int2; - -typedef long int int4; - -typedef signed long sint31; - -typedef signed short sint15; - -typedef signed char sint7; - -typedef uint16 UWord16 ; -typedef uint32 UWord32 ; -typedef int32 Word32 ; -typedef int16 Word16 ; -typedef uint8 UWord8 ; -typedef int8 Word8 ; -typedef int32 Vect32 ; - -#if (! defined T_WINNT) && (! defined __GNUC__) - - #ifndef _INT64_DEFINED - - typedef long long int64; - #define _INT64_DEFINED - #endif - #ifndef _UINT64_DEFINED - - typedef unsigned long long uint64; - #define _UINT64_DEFINED - #endif -#else - - #if (defined __GNUC__) - #ifndef _INT64_DEFINED - typedef long long int64; - #define _INT64_DEFINED - #endif - #ifndef _UINT64_DEFINED - typedef unsigned long long uint64; - #define _UINT64_DEFINED - #endif - #else - typedef __int64 int64; - #ifndef _UINT64_DEFINED - typedef unsigned __int64 uint64; - #define _UINT64_DEFINED - #endif - #endif -#endif - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_mu_mimo_info.h deleted file mode 100644 index c9e20d75e648..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_mu_mimo_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ -#define _EHT_SIG_USR_MU_MIMO_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 - -struct eht_sig_usr_mu_mimo_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - sta_coding : 1, - sta_spatial_config : 6, - reserved_0a : 1, - rx_integrity_check_passed : 1, - subband80_cc_mask : 8; - uint32_t user_order_subband80_0 : 8, - user_order_subband80_1 : 8, - user_order_subband80_2 : 8, - user_order_subband80_3 : 8; -#else - uint32_t subband80_cc_mask : 8, - rx_integrity_check_passed : 1, - reserved_0a : 1, - sta_spatial_config : 6, - sta_coding : 1, - sta_mcs : 4, - sta_id : 11; - uint32_t user_order_subband80_3 : 8, - user_order_subband80_2 : 8, - user_order_subband80_1 : 8, - user_order_subband80_0 : 8; -#endif -}; - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 - -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 - -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 - -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_ofdma_info.h deleted file mode 100644 index f2520cccfde9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_ofdma_info.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ -#define _EHT_SIG_USR_OFDMA_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 - -struct eht_sig_usr_ofdma_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - validate_0a : 1, - nss : 4, - txbf : 1, - sta_coding : 1, - reserved_0b : 1, - rx_integrity_check_passed : 1, - subband80_cc_mask : 8; - uint32_t user_order_subband80_0 : 8, - user_order_subband80_1 : 8, - user_order_subband80_2 : 8, - user_order_subband80_3 : 8; -#else - uint32_t subband80_cc_mask : 8, - rx_integrity_check_passed : 1, - reserved_0b : 1, - sta_coding : 1, - txbf : 1, - nss : 4, - validate_0a : 1, - sta_mcs : 4, - sta_id : 11; - uint32_t user_order_subband80_3 : 8, - user_order_subband80_2 : 8, - user_order_subband80_1 : 8, - user_order_subband80_0 : 8; -#endif -}; - -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 - -#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 -#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 -#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 - -#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 - -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 - -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 - -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 - -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_su_info.h deleted file mode 100644 index 208cb4de0539..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_su_info.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_SU_INFO_H_ -#define _EHT_SIG_USR_SU_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 - -struct eht_sig_usr_su_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - validate_0a : 1, - nss : 4, - txbf : 1, - sta_coding : 1, - reserved_0b : 9, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0b : 9, - sta_coding : 1, - txbf : 1, - nss : 4, - validate_0a : 1, - sta_mcs : 4, - sta_id : 11; -#endif -}; - -#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 - -#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 -#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 -#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 - -#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 -#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 -#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 - -#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 -#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 -#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 - -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 - -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/expected_response.h b/drivers/staging/fw-api/hw/fig/v1/expected_response.h deleted file mode 100644 index b3ec83ceccf8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/expected_response.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EXPECTED_RESPONSE_H_ -#define _EXPECTED_RESPONSE_H_ - -#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 - -#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 - -struct expected_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_ad2_31_0 : 32; - uint32_t tx_ad2_47_32 : 16, - expected_response_type : 5, - response_to_response : 3, - su_ba_user_number : 1, - response_info_part2_required : 1, - transmitted_bssid_check_en : 1, - eht___reserved_g_0022_ndp_expected : 1, - reserved_1 : 4; - uint32_t ndp_sta_partial_aid_2_8_0 : 11, - reserved_2 : 10, - ndp_sta_partial_aid1_8_0 : 11; - uint32_t ast_index : 16, - capture_ack_ba_sounding : 1, - capture_sounding_1str_20mhz : 1, - capture_sounding_1str_40mhz : 1, - capture_sounding_1str_80mhz : 1, - capture_sounding_1str_160mhz : 1, - capture_sounding_1str_240mhz : 1, - capture_sounding_1str_320mhz : 1, - reserved_3a : 9; - uint32_t fcs : 9, - expect_rx_with_blackout_details : 1, - crc : 4, - scrambler_seed : 7, - reserved_4b : 11; - uint32_t tlv64_padding : 32; -#else - uint32_t tx_ad2_31_0 : 32; - uint32_t reserved_1 : 4, - eht___reserved_g_0022_ndp_expected : 1, - transmitted_bssid_check_en : 1, - response_info_part2_required : 1, - su_ba_user_number : 1, - response_to_response : 3, - expected_response_type : 5, - tx_ad2_47_32 : 16; - uint32_t ndp_sta_partial_aid1_8_0 : 11, - reserved_2 : 10, - ndp_sta_partial_aid_2_8_0 : 11; - uint32_t reserved_3a : 9, - capture_sounding_1str_320mhz : 1, - capture_sounding_1str_240mhz : 1, - capture_sounding_1str_160mhz : 1, - capture_sounding_1str_80mhz : 1, - capture_sounding_1str_40mhz : 1, - capture_sounding_1str_20mhz : 1, - capture_ack_ba_sounding : 1, - ast_index : 16; - uint32_t reserved_4b : 11, - scrambler_seed : 7, - crc : 4, - expect_rx_with_blackout_details : 1, - fcs : 9; - uint32_t tlv64_padding : 32; -#endif -}; - -#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 -#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 -#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff - -#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 -#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 -#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 - -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 - -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 - -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 - -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 - -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 - -#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESERVED_1_LSB 60 -#define EXPECTED_RESPONSE_RESERVED_1_MSB 63 -#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf000000000000000 - -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff - -#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 -#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 -#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 - -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 - -#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_AST_INDEX_LSB 32 -#define EXPECTED_RESPONSE_AST_INDEX_MSB 47 -#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 - -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 - -#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 -#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 -#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 - -#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_FCS_LSB 0 -#define EXPECTED_RESPONSE_FCS_MSB 8 -#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff - -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB 9 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB 9 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK 0x0000000000000200 - -#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_CRC_LSB 10 -#define EXPECTED_RESPONSE_CRC_MSB 13 -#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 - -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 - -#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 -#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 -#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 - -#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 -#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 -#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_dl_info.h deleted file mode 100644 index 84571eb65d3b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_dl_info.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_MU_DL_INFO_H_ -#define _HE_SIG_A_MU_DL_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 - -struct he_sig_a_mu_dl_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dl_ul_flag : 1, - mcs_of_sig_b : 3, - dcm_of_sig_b : 1, - bss_color_id : 6, - spatial_reuse : 4, - transmit_bw : 3, - num_sig_b_symbols : 4, - comp_mode_sig_b : 1, - cp_ltf_size : 2, - doppler_indication : 1, - reserved_0a : 6; - uint32_t txop_duration : 7, - reserved_1a : 1, - num_ltf_symbols : 3, - ldpc_extra_symbol : 1, - stbc : 1, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - crc : 4, - tail : 6, - reserved_1b : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0a : 6, - doppler_indication : 1, - cp_ltf_size : 2, - comp_mode_sig_b : 1, - num_sig_b_symbols : 4, - transmit_bw : 3, - spatial_reuse : 4, - bss_color_id : 6, - dcm_of_sig_b : 1, - mcs_of_sig_b : 3, - dl_ul_flag : 1; - uint32_t rx_integrity_check_passed : 1, - reserved_1b : 5, - tail : 6, - crc : 4, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - stbc : 1, - ldpc_extra_symbol : 1, - num_ltf_symbols : 3, - reserved_1a : 1, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 - -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e - -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 - -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 - -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 - -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 - -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 - -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 - -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 - -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 - -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 - -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 - -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 - -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 - -#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 -#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 -#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 - -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 - -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 - -#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 -#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 -#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 -#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 -#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 - -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_ul_info.h deleted file mode 100644 index e2d0ad73a66c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_ul_info.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_MU_UL_INFO_H_ -#define _HE_SIG_A_MU_UL_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 - -struct he_sig_a_mu_ul_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t format_indication : 1, - bss_color_id : 6, - spatial_reuse : 16, - reserved_0a : 1, - transmit_bw : 2, - reserved_0b : 6; - uint32_t txop_duration : 7, - reserved_1a : 9, - crc : 4, - tail : 6, - reserved_1b : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0b : 6, - transmit_bw : 2, - reserved_0a : 1, - spatial_reuse : 16, - bss_color_id : 6, - format_indication : 1; - uint32_t rx_integrity_check_passed : 1, - reserved_1b : 5, - tail : 6, - crc : 4, - reserved_1a : 9, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 - -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e - -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 - -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 - -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 - -#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 -#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 -#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 -#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 -#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 - -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_a_su_info.h deleted file mode 100644 index e4be3671016e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/he_sig_a_su_info.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_SU_INFO_H_ -#define _HE_SIG_A_SU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 - -struct he_sig_a_su_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t format_indication : 1, - beam_change : 1, - dl_ul_flag : 1, - transmit_mcs : 4, - dcm : 1, - bss_color_id : 6, - reserved_0a : 1, - spatial_reuse : 4, - transmit_bw : 2, - cp_ltf_size : 2, - nsts : 3, - reserved_0b : 6; - uint32_t txop_duration : 7, - coding : 1, - ldpc_extra_symbol : 1, - stbc : 1, - txbf : 1, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - reserved_1a : 1, - doppler_indication : 1, - crc : 4, - tail : 6, - dot11ax_su_extended : 1, - dot11ax_ext_ru_size : 3, - rx_ndp : 1, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0b : 6, - nsts : 3, - cp_ltf_size : 2, - transmit_bw : 2, - spatial_reuse : 4, - reserved_0a : 1, - bss_color_id : 6, - dcm : 1, - transmit_mcs : 4, - dl_ul_flag : 1, - beam_change : 1, - format_indication : 1; - uint32_t rx_integrity_check_passed : 1, - rx_ndp : 1, - dot11ax_ext_ru_size : 3, - dot11ax_su_extended : 1, - tail : 6, - crc : 4, - doppler_indication : 1, - reserved_1a : 1, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - txbf : 1, - stbc : 1, - ldpc_extra_symbol : 1, - coding : 1, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001 - -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002 - -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004 - -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078 - -#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_DCM_LSB 7 -#define HE_SIG_A_SU_INFO_DCM_MSB 7 -#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080 - -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00 - -#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000 - -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000 - -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000 - -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000 - -#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_NSTS_LSB 23 -#define HE_SIG_A_SU_INFO_NSTS_MSB 25 -#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000 - -#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26 -#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31 -#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000 - -#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_CODING_LSB 7 -#define HE_SIG_A_SU_INFO_CODING_MSB 7 -#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080 - -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100 - -#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_STBC_LSB 9 -#define HE_SIG_A_SU_INFO_STBC_MSB 9 -#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200 - -#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TXBF_LSB 10 -#define HE_SIG_A_SU_INFO_TXBF_MSB 10 -#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400 - -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 - -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 - -#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000 - -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000 - -#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_CRC_LSB 16 -#define HE_SIG_A_SU_INFO_CRC_MSB 19 -#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TAIL_LSB 20 -#define HE_SIG_A_SU_INFO_TAIL_MSB 25 -#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 - -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 - -#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30 -#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30 -#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000 - -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_b1_mu_info.h deleted file mode 100644 index a248c3dc67b3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/he_sig_b1_mu_info.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B1_MU_INFO_H_ -#define _HE_SIG_B1_MU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 - -struct he_sig_b1_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_allocation : 8, - reserved_0 : 23, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0 : 23, - ru_allocation : 8; -#endif -}; - -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff - -#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 -#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 -#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 - -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_mu_info.h deleted file mode 100644 index 83d6f3bc843f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_mu_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B2_MU_INFO_H_ -#define _HE_SIG_B2_MU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2 - -struct he_sig_b2_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_spatial_config : 4, - sta_mcs : 4, - reserved_set_to_1 : 1, - sta_coding : 1, - reserved_0a : 7, - nsts : 3, - rx_integrity_check_passed : 1; - uint32_t user_order : 8, - cc_mask : 8, - reserved_1a : 16; -#else - uint32_t rx_integrity_check_passed : 1, - nsts : 3, - reserved_0a : 7, - sta_coding : 1, - reserved_set_to_1 : 1, - sta_mcs : 4, - sta_spatial_config : 4, - sta_id : 11; - uint32_t reserved_1a : 16, - cc_mask : 8, - user_order : 8; -#endif -}; - -#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0 -#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10 -#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff - -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800 - -#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15 -#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18 -#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000 - -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000 - -#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20 -#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20 -#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000 - -#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000 - -#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_NSTS_LSB 28 -#define HE_SIG_B2_MU_INFO_NSTS_MSB 30 -#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000 - -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0 -#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7 -#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff - -#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8 -#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15 -#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00 - -#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_ofdma_info.h deleted file mode 100644 index 6357d216eb3a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_ofdma_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B2_OFDMA_INFO_H_ -#define _HE_SIG_B2_OFDMA_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 - -struct he_sig_b2_ofdma_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - nsts : 3, - txbf : 1, - sta_mcs : 4, - sta_dcm : 1, - sta_coding : 1, - reserved_0 : 10, - rx_integrity_check_passed : 1; - uint32_t user_order : 8, - cc_mask : 8, - reserved_1a : 16; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0 : 10, - sta_coding : 1, - sta_dcm : 1, - sta_mcs : 4, - txbf : 1, - nsts : 3, - sta_id : 11; - uint32_t reserved_1a : 16, - cc_mask : 8, - user_order : 8; -#endif -}; - -#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff - -#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 -#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 -#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 - -#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 -#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 -#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 - -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 - -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 - -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 - -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 - -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff - -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 - -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/ht_sig_info.h b/drivers/staging/fw-api/hw/fig/v1/ht_sig_info.h deleted file mode 100644 index d6a4a719e6e2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/ht_sig_info.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HT_SIG_INFO_H_ -#define _HT_SIG_INFO_H_ - -#define NUM_OF_DWORDS_HT_SIG_INFO 2 - -struct ht_sig_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mcs : 7, - cbw : 1, - length : 16, - reserved_0 : 8; - uint32_t smoothing : 1, - not_sounding : 1, - ht_reserved : 1, - aggregation : 1, - stbc : 2, - fec_coding : 1, - short_gi : 1, - num_ext_sp_str : 2, - crc : 8, - signal_tail : 6, - reserved_1 : 7, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0 : 8, - length : 16, - cbw : 1, - mcs : 7; - uint32_t rx_integrity_check_passed : 1, - reserved_1 : 7, - signal_tail : 6, - crc : 8, - num_ext_sp_str : 2, - short_gi : 1, - fec_coding : 1, - stbc : 2, - aggregation : 1, - ht_reserved : 1, - not_sounding : 1, - smoothing : 1; -#endif -}; - -#define HT_SIG_INFO_MCS_OFFSET 0x00000000 -#define HT_SIG_INFO_MCS_LSB 0 -#define HT_SIG_INFO_MCS_MSB 6 -#define HT_SIG_INFO_MCS_MASK 0x0000007f - -#define HT_SIG_INFO_CBW_OFFSET 0x00000000 -#define HT_SIG_INFO_CBW_LSB 7 -#define HT_SIG_INFO_CBW_MSB 7 -#define HT_SIG_INFO_CBW_MASK 0x00000080 - -#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000 -#define HT_SIG_INFO_LENGTH_LSB 8 -#define HT_SIG_INFO_LENGTH_MSB 23 -#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00 - -#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000 -#define HT_SIG_INFO_RESERVED_0_LSB 24 -#define HT_SIG_INFO_RESERVED_0_MSB 31 -#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000 - -#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004 -#define HT_SIG_INFO_SMOOTHING_LSB 0 -#define HT_SIG_INFO_SMOOTHING_MSB 0 -#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001 - -#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004 -#define HT_SIG_INFO_NOT_SOUNDING_LSB 1 -#define HT_SIG_INFO_NOT_SOUNDING_MSB 1 -#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002 - -#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004 -#define HT_SIG_INFO_HT_RESERVED_LSB 2 -#define HT_SIG_INFO_HT_RESERVED_MSB 2 -#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004 - -#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004 -#define HT_SIG_INFO_AGGREGATION_LSB 3 -#define HT_SIG_INFO_AGGREGATION_MSB 3 -#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008 - -#define HT_SIG_INFO_STBC_OFFSET 0x00000004 -#define HT_SIG_INFO_STBC_LSB 4 -#define HT_SIG_INFO_STBC_MSB 5 -#define HT_SIG_INFO_STBC_MASK 0x00000030 - -#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004 -#define HT_SIG_INFO_FEC_CODING_LSB 6 -#define HT_SIG_INFO_FEC_CODING_MSB 6 -#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040 - -#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004 -#define HT_SIG_INFO_SHORT_GI_LSB 7 -#define HT_SIG_INFO_SHORT_GI_MSB 7 -#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080 - -#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004 -#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8 -#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9 -#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300 - -#define HT_SIG_INFO_CRC_OFFSET 0x00000004 -#define HT_SIG_INFO_CRC_LSB 10 -#define HT_SIG_INFO_CRC_MSB 17 -#define HT_SIG_INFO_CRC_MASK 0x0003fc00 - -#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004 -#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18 -#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23 -#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000 - -#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004 -#define HT_SIG_INFO_RESERVED_1_LSB 24 -#define HT_SIG_INFO_RESERVED_1_MSB 30 -#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000 - -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/l_sig_a_info.h b/drivers/staging/fw-api/hw/fig/v1/l_sig_a_info.h deleted file mode 100644 index 6da0725dfee7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/l_sig_a_info.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _L_SIG_A_INFO_H_ -#define _L_SIG_A_INFO_H_ - -#define NUM_OF_DWORDS_L_SIG_A_INFO 1 - -struct l_sig_a_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rate : 4, - lsig_reserved : 1, - length : 12, - parity : 1, - tail : 6, - pkt_type : 4, - captured_implicit_sounding : 1, - reserved : 2, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved : 2, - captured_implicit_sounding : 1, - pkt_type : 4, - tail : 6, - parity : 1, - length : 12, - lsig_reserved : 1, - rate : 4; -#endif -}; - -#define L_SIG_A_INFO_RATE_OFFSET 0x00000000 -#define L_SIG_A_INFO_RATE_LSB 0 -#define L_SIG_A_INFO_RATE_MSB 3 -#define L_SIG_A_INFO_RATE_MASK 0x0000000f - -#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000 -#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4 -#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4 -#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010 - -#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000 -#define L_SIG_A_INFO_LENGTH_LSB 5 -#define L_SIG_A_INFO_LENGTH_MSB 16 -#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0 - -#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000 -#define L_SIG_A_INFO_PARITY_LSB 17 -#define L_SIG_A_INFO_PARITY_MSB 17 -#define L_SIG_A_INFO_PARITY_MASK 0x00020000 - -#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000 -#define L_SIG_A_INFO_TAIL_LSB 18 -#define L_SIG_A_INFO_TAIL_MSB 23 -#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000 - -#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000 -#define L_SIG_A_INFO_PKT_TYPE_LSB 24 -#define L_SIG_A_INFO_PKT_TYPE_MSB 27 -#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000 - -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 - -#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000 -#define L_SIG_A_INFO_RESERVED_LSB 29 -#define L_SIG_A_INFO_RESERVED_MSB 30 -#define L_SIG_A_INFO_RESERVED_MASK 0x60000000 - -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/l_sig_b_info.h b/drivers/staging/fw-api/hw/fig/v1/l_sig_b_info.h deleted file mode 100644 index f2052702e2de..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/l_sig_b_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _L_SIG_B_INFO_H_ -#define _L_SIG_B_INFO_H_ - -#define NUM_OF_DWORDS_L_SIG_B_INFO 1 - -struct l_sig_b_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rate : 4, - length : 12, - reserved : 15, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved : 15, - length : 12, - rate : 4; -#endif -}; - -#define L_SIG_B_INFO_RATE_OFFSET 0x00000000 -#define L_SIG_B_INFO_RATE_LSB 0 -#define L_SIG_B_INFO_RATE_MSB 3 -#define L_SIG_B_INFO_RATE_MASK 0x0000000f - -#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000 -#define L_SIG_B_INFO_LENGTH_LSB 4 -#define L_SIG_B_INFO_LENGTH_MSB 15 -#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0 - -#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000 -#define L_SIG_B_INFO_RESERVED_LSB 16 -#define L_SIG_B_INFO_RESERVED_MSB 30 -#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000 - -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v1/macrx_abort_request_info.h deleted file mode 100644 index 038f4038fa59..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/macrx_abort_request_info.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACRX_ABORT_REQUEST_INFO_H_ -#define _MACRX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 - -struct macrx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t macrx_abort_reason : 8, - reserved_0 : 8; -#else - uint16_t reserved_0 : 8, - macrx_abort_reason : 8; -#endif -}; - -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff - -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h deleted file mode 100644 index f29ca356a223..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ -#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ - -#include "eht_sig_usr_mu_mimo_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 - -struct mactx_eht_sig_usr_mu_mimo { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; -#else - struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; -#endif -}; - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_ofdma.h deleted file mode 100644 index 24bf6691978d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_ofdma.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ -#define _MACTX_EHT_SIG_USR_OFDMA_H_ - -#include "eht_sig_usr_ofdma_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1 - -struct mactx_eht_sig_usr_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; -#else - struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; -#endif -}; - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_su.h deleted file mode 100644 index 1fb82723c1ff..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_su.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_SU_H_ -#define _MACTX_EHT_SIG_USR_SU_H_ - -#include "eht_sig_usr_su_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1 - -struct mactx_eht_sig_usr_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; - uint32_t tlv64_padding : 32; -#else - struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_dl.h deleted file mode 100644 index 438f3af6f9e7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_dl.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_MU_DL_H_ -#define _MACTX_HE_SIG_A_MU_DL_H_ - -#include "he_sig_a_mu_dl_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1 - -struct mactx_he_sig_a_mu_dl { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; -#else - struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_ul.h deleted file mode 100644 index 96d2b912665a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_ul.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_MU_UL_H_ -#define _MACTX_HE_SIG_A_MU_UL_H_ - -#include "he_sig_a_mu_ul_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1 - -struct mactx_he_sig_a_mu_ul { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; -#else - struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_su.h deleted file mode 100644 index e51241d26559..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_su.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_SU_H_ -#define _MACTX_HE_SIG_A_SU_H_ - -#include "he_sig_a_su_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1 - -struct mactx_he_sig_a_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_su_info mactx_he_sig_a_su_info_details; -#else - struct he_sig_a_su_info mactx_he_sig_a_su_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b1_mu.h deleted file mode 100644 index 700528af2048..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b1_mu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B1_MU_H_ -#define _MACTX_HE_SIG_B1_MU_H_ - -#include "he_sig_b1_mu_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 - -struct mactx_he_sig_b1_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#else - struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_mu.h deleted file mode 100644 index ccc1c593fed6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_mu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B2_MU_H_ -#define _MACTX_HE_SIG_B2_MU_H_ - -#include "he_sig_b2_mu_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1 - -struct mactx_he_sig_b2_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; -#else - struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; -#endif -}; - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_ofdma.h deleted file mode 100644 index afc3c4b22841..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_ofdma.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ -#define _MACTX_HE_SIG_B2_OFDMA_H_ - -#include "he_sig_b2_ofdma_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1 - -struct mactx_he_sig_b2_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; -#else - struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; -#endif -}; - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_ht_sig.h b/drivers/staging/fw-api/hw/fig/v1/mactx_ht_sig.h deleted file mode 100644 index ec28824c590f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_ht_sig.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HT_SIG_H_ -#define _MACTX_HT_SIG_H_ - -#include "ht_sig_info.h" -#define NUM_OF_DWORDS_MACTX_HT_SIG 2 - -#define NUM_OF_QWORDS_MACTX_HT_SIG 1 - -struct mactx_ht_sig { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ht_sig_info mactx_ht_sig_info_details; -#else - struct ht_sig_info mactx_ht_sig_info_details; -#endif -}; - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_a.h deleted file mode 100644 index 061e46e28a2c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_a.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_L_SIG_A_H_ -#define _MACTX_L_SIG_A_H_ - -#include "l_sig_a_info.h" -#define NUM_OF_DWORDS_MACTX_L_SIG_A 2 - -#define NUM_OF_QWORDS_MACTX_L_SIG_A 1 - -struct mactx_l_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_a_info mactx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_a_info mactx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32 -#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63 -#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_b.h deleted file mode 100644 index 6d533acef675..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_b.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_L_SIG_B_H_ -#define _MACTX_L_SIG_B_H_ - -#include "l_sig_b_info.h" -#define NUM_OF_DWORDS_MACTX_L_SIG_B 2 - -#define NUM_OF_QWORDS_MACTX_L_SIG_B 1 - -struct mactx_l_sig_b { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_b_info mactx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_b_info mactx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32 -#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63 -#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_phy_desc.h b/drivers/staging/fw-api/hw/fig/v1/mactx_phy_desc.h deleted file mode 100644 index ee4ccdf65c28..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_phy_desc.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_PHY_DESC_H_ -#define _MACTX_PHY_DESC_H_ - -#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 - -#define NUM_OF_QWORDS_MACTX_PHY_DESC 2 - -struct mactx_phy_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 16, - bf_type : 2, - wait_sifs : 2, - dot11b_preamble_type : 1, - pkt_type : 4, - su_or_mu : 2, - mu_type : 1, - bandwidth : 3, - channel_capture : 1; - uint32_t mcs : 5, - global_ofdma_mimo_enable : 1, - stbc : 1, - dot11ax_su_extended : 1, - dot11ax_trigger_frame_embedded : 1, - tx_pwr_shared : 8, - tx_pwr_unshared : 8, - measure_power : 1, - tpc_glut_self_cal : 1, - back_to_back_transmission_expected : 1, - heavy_clip_nss : 3, - txbf_per_packet_no_csd_no_walsh : 1; - uint32_t ndp : 3, - ul_flag : 1, - triggered : 1, - ap_pkt_bw : 3, - ru_position_start : 8, - pcu_ppdu_setup_start_reason : 3, - tlv_source : 1, - reserved_2a : 1, - nss : 3, - stream_offset : 3, - reserved_2b : 2, - clpc_enable : 1, - mu_ndp : 1, - response_expected : 1; - uint32_t rx_chain_mask : 8, - rx_chain_mask_valid : 1, - ant_sel_valid : 1, - ant_sel : 1, - cp_setting : 2, - he_ppdu_subtype : 2, - active_channel : 3, - generate_phyrx_tx_start_timing : 1, - ltf_size : 2, - ru_size_updated_v2 : 4, - reserved_3c : 1, - u_sig_puncture_pattern_encoding : 6; -#else - uint32_t channel_capture : 1, - bandwidth : 3, - mu_type : 1, - su_or_mu : 2, - pkt_type : 4, - dot11b_preamble_type : 1, - wait_sifs : 2, - bf_type : 2, - reserved_0a : 16; - uint32_t txbf_per_packet_no_csd_no_walsh : 1, - heavy_clip_nss : 3, - back_to_back_transmission_expected : 1, - tpc_glut_self_cal : 1, - measure_power : 1, - tx_pwr_unshared : 8, - tx_pwr_shared : 8, - dot11ax_trigger_frame_embedded : 1, - dot11ax_su_extended : 1, - stbc : 1, - global_ofdma_mimo_enable : 1, - mcs : 5; - uint32_t response_expected : 1, - mu_ndp : 1, - clpc_enable : 1, - reserved_2b : 2, - stream_offset : 3, - nss : 3, - reserved_2a : 1, - tlv_source : 1, - pcu_ppdu_setup_start_reason : 3, - ru_position_start : 8, - ap_pkt_bw : 3, - triggered : 1, - ul_flag : 1, - ndp : 3; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_3c : 1, - ru_size_updated_v2 : 4, - ltf_size : 2, - generate_phyrx_tx_start_timing : 1, - active_channel : 3, - he_ppdu_subtype : 2, - cp_setting : 2, - ant_sel : 1, - ant_sel_valid : 1, - rx_chain_mask_valid : 1, - rx_chain_mask : 8; -#endif -}; - -#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 -#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 -#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff - -#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BF_TYPE_LSB 16 -#define MACTX_PHY_DESC_BF_TYPE_MSB 17 -#define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 - -#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 -#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 -#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 - -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 - -#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 -#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 -#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 - -#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 -#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 -#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 - -#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MU_TYPE_LSB 27 -#define MACTX_PHY_DESC_MU_TYPE_MSB 27 -#define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 - -#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 -#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 -#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 - -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 - -#define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MCS_LSB 32 -#define MACTX_PHY_DESC_MCS_MSB 36 -#define MACTX_PHY_DESC_MCS_MASK 0x0000001f00000000 - -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 37 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 37 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000002000000000 - -#define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_STBC_LSB 38 -#define MACTX_PHY_DESC_STBC_MSB 38 -#define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 - -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 - -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 - -#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 -#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 -#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 - -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 - -#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 -#define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 -#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 - -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 - -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 - -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 - -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 - -#define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_NDP_LSB 0 -#define MACTX_PHY_DESC_NDP_MSB 2 -#define MACTX_PHY_DESC_NDP_MASK 0x0000000000000007 - -#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_UL_FLAG_LSB 3 -#define MACTX_PHY_DESC_UL_FLAG_MSB 3 -#define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000008 - -#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_TRIGGERED_LSB 4 -#define MACTX_PHY_DESC_TRIGGERED_MSB 4 -#define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000010 - -#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_AP_PKT_BW_LSB 5 -#define MACTX_PHY_DESC_AP_PKT_BW_MSB 7 -#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000000000000e0 - -#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RU_POSITION_START_LSB 8 -#define MACTX_PHY_DESC_RU_POSITION_START_MSB 15 -#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x000000000000ff00 - -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 16 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 18 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000070000 - -#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_TLV_SOURCE_LSB 19 -#define MACTX_PHY_DESC_TLV_SOURCE_MSB 19 -#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000080000 - -#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_2A_LSB 20 -#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 -#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000100000 - -#define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_NSS_LSB 21 -#define MACTX_PHY_DESC_NSS_MSB 23 -#define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 - -#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 -#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 -#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 - -#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 -#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 -#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 - -#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 -#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 -#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 - -#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_MU_NDP_LSB 30 -#define MACTX_PHY_DESC_MU_NDP_MSB 30 -#define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 - -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 - -#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 - -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 - -#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 -#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 -#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 - -#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ANT_SEL_LSB 42 -#define MACTX_PHY_DESC_ANT_SEL_MSB 42 -#define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 - -#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_CP_SETTING_LSB 43 -#define MACTX_PHY_DESC_CP_SETTING_MSB 44 -#define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 - -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 - -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 - -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 - -#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_LTF_SIZE_LSB 51 -#define MACTX_PHY_DESC_LTF_SIZE_MSB 52 -#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 - -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 - -#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_3C_LSB 57 -#define MACTX_PHY_DESC_RESERVED_3C_MSB 57 -#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 - -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_su_mu.h deleted file mode 100644 index f46583e4c7ee..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_su_mu.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ -#define _MACTX_U_SIG_EHT_SU_MU_H_ - -#include "u_sig_eht_su_mu_info.h" -#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 - -#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1 - -struct mactx_u_sig_eht_su_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; -#else - struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; -#endif -}; - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_tb.h deleted file mode 100644 index 5e57312a9da2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_tb.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_U_SIG_EHT_TB_H_ -#define _MACTX_U_SIG_EHT_TB_H_ - -#include "u_sig_eht_tb_info.h" -#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 - -#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1 - -struct mactx_u_sig_eht_tb { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; -#else - struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; -#endif -}; - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_common.h deleted file mode 100644 index 04124271bbc9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_common.h +++ /dev/null @@ -1,482 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_USER_DESC_COMMON_H_ -#define _MACTX_USER_DESC_COMMON_H_ - -#include "unallocated_ru_160_info.h" -#include "ru_allocation_160_info.h" -#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 - -#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 - -struct mactx_user_desc_common { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t num_users : 6, - reserved_0b : 5, - ltf_size : 2, - reserved_0c : 3, - he_stf_long : 1, - reserved_0d : 7, - num_users_he_sigb_band0 : 8; - uint32_t num_ltf_symbols : 3, - reserved_1a : 5, - num_users_he_sigb_band1 : 8, - reserved_1b : 16; - uint32_t packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - packet_extension : 3, - reserved : 2, - he_sigb_dcm : 1, - reserved_2b : 7, - he_sigb_compression : 1, - reserved_2c : 15; - uint32_t he_sigb_0_mcs : 3, - reserved_3a : 13, - num_he_sigb_sym : 5, - center_ru_0 : 1, - center_ru_1 : 1, - reserved_3b : 1, - ftm_en : 1, - pe_nss : 3, - pe_ltf_size : 2, - pe_content : 1, - pe_chain_csd_en : 1; - struct ru_allocation_160_info ru_allocation_0123_details; - struct ru_allocation_160_info ru_allocation_4567_details; - struct unallocated_ru_160_info ru_allocation_160_0_details; - struct unallocated_ru_160_info ru_allocation_160_1_details; - uint32_t num_data_symbols : 16, - ndp_ru_tone_set_index : 7, - ndp_feedback_status : 1, - doppler_indication : 1, - reserved_14a : 7; - uint32_t spatial_reuse : 16, - distributed_ru : 1, - dru_spreading_bw : 2, - reserved_15a : 13; -#else - uint32_t num_users_he_sigb_band0 : 8, - reserved_0d : 7, - he_stf_long : 1, - reserved_0c : 3, - ltf_size : 2, - reserved_0b : 5, - num_users : 6; - uint32_t reserved_1b : 16, - num_users_he_sigb_band1 : 8, - reserved_1a : 5, - num_ltf_symbols : 3; - uint32_t reserved_2c : 15, - he_sigb_compression : 1, - reserved_2b : 7, - he_sigb_dcm : 1, - reserved : 2, - packet_extension : 3, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2; - uint32_t pe_chain_csd_en : 1, - pe_content : 1, - pe_ltf_size : 2, - pe_nss : 3, - ftm_en : 1, - reserved_3b : 1, - center_ru_1 : 1, - center_ru_0 : 1, - num_he_sigb_sym : 5, - reserved_3a : 13, - he_sigb_0_mcs : 3; - struct ru_allocation_160_info ru_allocation_0123_details; - struct ru_allocation_160_info ru_allocation_4567_details; - struct unallocated_ru_160_info ru_allocation_160_0_details; - struct unallocated_ru_160_info ru_allocation_160_1_details; - uint32_t reserved_14a : 7, - doppler_indication : 1, - ndp_feedback_status : 1, - ndp_ru_tone_set_index : 7, - num_data_symbols : 16; - uint32_t reserved_15a : 13, - dru_spreading_bw : 2, - distributed_ru : 1, - spatial_reuse : 16; -#endif -}; - -#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 -#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 -#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f - -#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 - -#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 - -#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 - -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 - -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 - -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 - -#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 -#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 -#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 - -#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 - -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 - -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 - -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 - -#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 -#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 -#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 - -#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 -#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 -#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 - -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 - -#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 - -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 - -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff - -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 - -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 - -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 - -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_LSB 48 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MSB 48 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MASK 0x0001000000000000 - -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_LSB 49 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MSB 50 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MASK 0x0006000000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 51 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xfff8000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_per_user.h deleted file mode 100644 index a68b50d9d639..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_per_user.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_USER_DESC_PER_USER_H_ -#define _MACTX_USER_DESC_PER_USER_H_ - -#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 6 - -#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 3 - -struct mactx_user_desc_per_user { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t psdu_length : 24, - reserved_0a : 8; - uint32_t ru_start_index : 8, - ru_size : 4, - reserved_1b : 4, - ofdma_mu_mimo_enabled : 1, - nss : 3, - stream_offset : 3, - reserved_1c : 1, - mcs : 5, - dcm : 1, - reserved_1d : 2; - uint32_t fec_type : 1, - reserved_2a : 1, - qam_diff1 : 2, - qam_diff2 : 2, - qam_diff3 : 2, - user_bf_type : 2, - a_factor_ldpc2x : 2, - extra_sym_ldpc2x : 1, - cw_len_2x : 2, - reserved_2b : 1, - drop_user_cbf : 1, - a_factor_ldpc1x : 2, - extra_sym_ldpc1x : 1, - cw_len_1x : 2, - ldpc1x_used : 1, - ldpc2x_used : 1, - ldpc_extra_symbol : 1, - force_extra_symbol : 1, - ldpc_2x_codeword : 1, - reserved_2d : 5; - uint32_t sw_peer_id : 16, - per_user_subband_mask : 16; - uint32_t ldpc_num_avbits : 27, - reserved_4a : 5; - uint32_t num_cw_1x : 16, - num_cw_2x : 16; -#else - uint32_t reserved_0a : 8, - psdu_length : 24; - uint32_t reserved_1d : 2, - dcm : 1, - mcs : 5, - reserved_1c : 1, - stream_offset : 3, - nss : 3, - ofdma_mu_mimo_enabled : 1, - reserved_1b : 4, - ru_size : 4, - ru_start_index : 8; - uint32_t reserved_2d : 5, - ldpc_2x_codeword : 1, - force_extra_symbol : 1, - ldpc_extra_symbol : 1, - ldpc2x_used : 1, - ldpc1x_used : 1, - cw_len_1x : 2, - extra_sym_ldpc1x : 1, - a_factor_ldpc1x : 2, - drop_user_cbf : 1, - reserved_2b : 1, - cw_len_2x : 2, - extra_sym_ldpc2x : 1, - a_factor_ldpc2x : 2, - user_bf_type : 2, - qam_diff3 : 2, - qam_diff2 : 2, - qam_diff1 : 2, - reserved_2a : 1, - fec_type : 1; - uint32_t per_user_subband_mask : 16, - sw_peer_id : 16; - uint32_t reserved_4a : 5, - ldpc_num_avbits : 27; - uint32_t num_cw_2x : 16, - num_cw_1x : 16; -#endif -}; - -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff - -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000 - -#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000 - -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000 - -#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_NSS_LSB 49 -#define MACTX_USER_DESC_PER_USER_NSS_MSB 51 -#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000 - -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000 - -#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_MCS_LSB 56 -#define MACTX_USER_DESC_PER_USER_MCS_MSB 60 -#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x1f00000000000000 - -#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_DCM_LSB 61 -#define MACTX_USER_DESC_PER_USER_DCM_MSB 61 -#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x2000000000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 62 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xc000000000000000 - -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 1 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x0000000000000002 - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_LSB 2 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MSB 3 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MASK 0x000000000000000c - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_LSB 4 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MSB 5 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MASK 0x0000000000000030 - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_LSB 6 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MSB 7 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MASK 0x00000000000000c0 - -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300 - -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_LSB 10 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MSB 11 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MASK 0x0000000000000c00 - -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_LSB 12 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MSB 12 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MASK 0x0000000000001000 - -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_LSB 13 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MSB 14 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MASK 0x0000000000006000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 15 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x0000000000008000 - -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_LSB 17 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MSB 18 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MASK 0x0000000000060000 - -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_LSB 19 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MSB 19 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MASK 0x0000000000080000 - -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_LSB 20 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MSB 21 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MASK 0x0000000000300000 - -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_LSB 22 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MSB 22 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MASK 0x0000000000400000 - -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_LSB 23 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MSB 23 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MASK 0x0000000000800000 - -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000 - -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000 - -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_LSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MASK 0x0000000004000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 27 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000f8000000 - -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000 - -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_LSB 0 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MASK 0x0000000007ffffff - -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_LSB 27 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MASK 0x00000000f8000000 - -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_LSB 32 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MSB 47 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_LSB 48 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MSB 63 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_a.h deleted file mode 100644 index 6dec145785d6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_a.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_A_H_ -#define _MACTX_VHT_SIG_A_H_ - -#include "vht_sig_a_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1 - -struct mactx_vht_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_a_info mactx_vht_sig_a_info_details; -#else - struct vht_sig_a_info mactx_vht_sig_a_info_details; -#endif -}; - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu160.h deleted file mode 100644 index b66278da930b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu160.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU160_H_ -#define _MACTX_VHT_SIG_B_MU160_H_ - -#include "vht_sig_b_mu160_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4 - -struct mactx_vht_sig_b_mu160 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; -#else - struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu20.h deleted file mode 100644 index 95feca30eaa3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu20.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU20_H_ -#define _MACTX_VHT_SIG_B_MU20_H_ - -#include "vht_sig_b_mu20_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1 - -struct mactx_vht_sig_b_mu20 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; - uint32_t tlv64_padding : 32; -#else - struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu40.h deleted file mode 100644 index c770db089203..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu40.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU40_H_ -#define _MACTX_VHT_SIG_B_MU40_H_ - -#include "vht_sig_b_mu40_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1 - -struct mactx_vht_sig_b_mu40 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; -#else - struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu80.h deleted file mode 100644 index 9e39d240b618..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu80.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU80_H_ -#define _MACTX_VHT_SIG_B_MU80_H_ - -#include "vht_sig_b_mu80_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2 - -struct mactx_vht_sig_b_mu80 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; -#else - struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su160.h deleted file mode 100644 index 01bc54e5ab89..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su160.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU160_H_ -#define _MACTX_VHT_SIG_B_SU160_H_ - -#include "vht_sig_b_su160_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4 - -struct mactx_vht_sig_b_su160 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; -#else - struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su20.h deleted file mode 100644 index c297cc0785e3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su20.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU20_H_ -#define _MACTX_VHT_SIG_B_SU20_H_ - -#include "vht_sig_b_su20_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1 - -struct mactx_vht_sig_b_su20 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; - uint32_t tlv64_padding : 32; -#else - struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su40.h deleted file mode 100644 index 002d72c430ca..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su40.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU40_H_ -#define _MACTX_VHT_SIG_B_SU40_H_ - -#include "vht_sig_b_su40_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1 - -struct mactx_vht_sig_b_su40 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; -#else - struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su80.h deleted file mode 100644 index b15646f03f4a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su80.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU80_H_ -#define _MACTX_VHT_SIG_B_SU80_H_ - -#include "vht_sig_b_su80_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2 - -struct mactx_vht_sig_b_su80 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; -#else - struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/fig/v1/mlo_sta_id_details.h deleted file mode 100644 index 952056890206..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mlo_sta_id_details.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MLO_STA_ID_DETAILS_H_ -#define _MLO_STA_ID_DETAILS_H_ - -#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 - -struct mlo_sta_id_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t nstr_mlo_sta_id : 10, - block_self_ml_sync : 1, - block_partner_ml_sync : 1, - nstr_mlo_sta_id_valid : 1, - reserved_0a : 3; -#else - uint16_t reserved_0a : 3, - nstr_mlo_sta_id_valid : 1, - block_partner_ml_sync : 1, - block_self_ml_sync : 1, - nstr_mlo_sta_id : 10; -#endif -}; - -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff - -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 - -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 - -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 - -#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 -#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 -#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mon_buffer_addr.h b/drivers/staging/fw-api/hw/fig/v1/mon_buffer_addr.h deleted file mode 100644 index 8cb6f5fd57b9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mon_buffer_addr.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_BUFFER_ADDR_H_ -#define _MON_BUFFER_ADDR_H_ - -#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 - -#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 - -struct mon_buffer_addr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t dma_length : 12, - reserved_2a : 4, - msdu_continuation : 1, - truncated : 1, - reserved_2b : 14; - uint32_t tlv64_padding : 32; -#else - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t reserved_2b : 14, - truncated : 1, - msdu_continuation : 1, - reserved_2a : 4, - dma_length : 12; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff - -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 - -#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 -#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 -#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff - -#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 -#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 -#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 - -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 - -#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 -#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 -#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 - -#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 -#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 -#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 - -#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 -#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 -#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mon_destination_ring.h b/drivers/staging/fw-api/hw/fig/v1/mon_destination_ring.h deleted file mode 100644 index 1f373b585fd5..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mon_destination_ring.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_DESTINATION_RING_H_ -#define _MON_DESTINATION_RING_H_ - -#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 - -struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t stat_buf_virt_addr_31_0 : 32; - uint32_t stat_buf_virt_addr_63_32 : 32; - uint32_t ppdu_id : 32; - uint32_t end_offset : 12, - reserved_3a : 2, - link_info : 2, - end_reason : 2, - initiator : 1, - empty_descriptor : 1, - pkt_buffer_cnt : 8, - looping_count : 4; -#else - uint32_t stat_buf_virt_addr_31_0 : 32; - uint32_t stat_buf_virt_addr_63_32 : 32; - uint32_t ppdu_id : 32; - uint32_t looping_count : 4, - pkt_buffer_cnt : 8, - empty_descriptor : 1, - initiator : 1, - end_reason : 2, - link_info : 2, - reserved_3a : 2, - end_offset : 12; -#endif -}; - -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff - -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff - -#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 -#define MON_DESTINATION_RING_PPDU_ID_LSB 0 -#define MON_DESTINATION_RING_PPDU_ID_MSB 31 -#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff - -#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c -#define MON_DESTINATION_RING_END_OFFSET_LSB 0 -#define MON_DESTINATION_RING_END_OFFSET_MSB 11 -#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff - -#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c -#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 -#define MON_DESTINATION_RING_RESERVED_3A_MSB 13 -#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x00003000 - -#define MON_DESTINATION_RING_LINK_INFO_OFFSET 0x0000000c -#define MON_DESTINATION_RING_LINK_INFO_LSB 14 -#define MON_DESTINATION_RING_LINK_INFO_MSB 15 -#define MON_DESTINATION_RING_LINK_INFO_MASK 0x0000c000 - -#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c -#define MON_DESTINATION_RING_END_REASON_LSB 16 -#define MON_DESTINATION_RING_END_REASON_MSB 17 -#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 - -#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c -#define MON_DESTINATION_RING_INITIATOR_LSB 18 -#define MON_DESTINATION_RING_INITIATOR_MSB 18 -#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 - -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 - -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_OFFSET 0x0000000c -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_LSB 20 -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MSB 27 -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MASK 0x0ff00000 - -#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c -#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 -#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 -#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mon_drop.h b/drivers/staging/fw-api/hw/fig/v1/mon_drop.h deleted file mode 100644 index d1135ecd0dc2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mon_drop.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_DROP_H_ -#define _MON_DROP_H_ - -#define NUM_OF_DWORDS_MON_DROP 2 - -#define NUM_OF_QWORDS_MON_DROP 1 - -struct mon_drop { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ppdu_id : 32; - uint32_t ppdu_drop_cnt : 10, - mpdu_drop_cnt : 10, - tlv_drop_cnt : 10, - end_of_ppdu_seen : 1, - reserved_1a : 1; -#else - uint32_t ppdu_id : 32; - uint32_t reserved_1a : 1, - end_of_ppdu_seen : 1, - tlv_drop_cnt : 10, - mpdu_drop_cnt : 10, - ppdu_drop_cnt : 10; -#endif -}; - -#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000 -#define MON_DROP_PPDU_ID_LSB 0 -#define MON_DROP_PPDU_ID_MSB 31 -#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff - -#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_PPDU_DROP_CNT_LSB 32 -#define MON_DROP_PPDU_DROP_CNT_MSB 41 -#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000 - -#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_MPDU_DROP_CNT_LSB 42 -#define MON_DROP_MPDU_DROP_CNT_MSB 51 -#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000 - -#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_TLV_DROP_CNT_LSB 52 -#define MON_DROP_TLV_DROP_CNT_MSB 61 -#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000 - -#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000 -#define MON_DROP_END_OF_PPDU_SEEN_LSB 62 -#define MON_DROP_END_OF_PPDU_SEEN_MSB 62 -#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000 - -#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000 -#define MON_DROP_RESERVED_1A_LSB 63 -#define MON_DROP_RESERVED_1A_MSB 63 -#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mon_ingress_ring.h b/drivers/staging/fw-api/hw/fig/v1/mon_ingress_ring.h deleted file mode 100644 index 76f4e80417e0..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mon_ingress_ring.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_INGRESS_RING_H_ -#define _MON_INGRESS_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_MON_INGRESS_RING 4 - -struct mon_ingress_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buffer_addr_info_details; - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; -#else - struct buffer_addr_info buffer_addr_info_details; - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; -#endif -}; - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff - -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/msmhwiobase.h b/drivers/staging/fw-api/hw/fig/v1/msmhwiobase.h deleted file mode 100644 index f7620cef5599..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/msmhwiobase.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef __MSMHWIOBASE_H__ -#define __MSMHWIOBASE_H__ - -#define SOC_WFSS_CE_REG_BASE 0x01b80000 -#define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 -#define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/msmhwioreg.h b/drivers/staging/fw-api/hw/fig/v1/msmhwioreg.h deleted file mode 100644 index 881c73e30f58..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/msmhwioreg.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef __MSMHWIOREG_H__ -#define __MSMHWIOREG_H__ - -#include "msmhwiobase.h" - -#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400) -#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058) - - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/no_ack_report.h b/drivers/staging/fw-api/hw/fig/v1/no_ack_report.h deleted file mode 100644 index 5f9660801de6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/no_ack_report.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _NO_ACK_REPORT_H_ -#define _NO_ACK_REPORT_H_ - -#define NUM_OF_DWORDS_NO_ACK_REPORT 4 - -struct no_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t no_ack_transmit_reason : 4, - macrx_abort_reason : 4, - phyrx_abort_reason : 8, - frame_control : 16; - uint32_t rx_ppdu_duration : 24, - sr_ppdu_during_obss : 1, - selfgen_response_reason_to_sr_ppdu : 4, - reserved_1 : 3; - uint32_t pre_bt_broadcast_status_details : 12, - first_bt_broadcast_status_details : 12, - reserved_2 : 8; - uint32_t second_bt_broadcast_status_details : 12, - reserved_3 : 20; -#else - uint32_t frame_control : 16, - phyrx_abort_reason : 8, - macrx_abort_reason : 4, - no_ack_transmit_reason : 4; - uint32_t reserved_1 : 3, - selfgen_response_reason_to_sr_ppdu : 4, - sr_ppdu_during_obss : 1, - rx_ppdu_duration : 24; - uint32_t reserved_2 : 8, - first_bt_broadcast_status_details : 12, - pre_bt_broadcast_status_details : 12; - uint32_t reserved_3 : 20, - second_bt_broadcast_status_details : 12; -#endif -}; - -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f - -#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 - -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 - -#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 -#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 -#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 -#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 - -#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 -#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 -#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 -#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff - -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 - -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 - -#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 -#define NO_ACK_REPORT_RESERVED_1_LSB 29 -#define NO_ACK_REPORT_RESERVED_1_MSB 31 -#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 - -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff - -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 - -#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 -#define NO_ACK_REPORT_RESERVED_2_LSB 24 -#define NO_ACK_REPORT_RESERVED_2_MSB 31 -#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 - -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff - -#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c -#define NO_ACK_REPORT_RESERVED_3_LSB 12 -#define NO_ACK_REPORT_RESERVED_3_MSB 31 -#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/fig/v1/ofdma_trigger_details.h deleted file mode 100644 index 604b52e0d464..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/ofdma_trigger_details.h +++ /dev/null @@ -1,928 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _OFDMA_TRIGGER_DETAILS_H_ -#define _OFDMA_TRIGGER_DETAILS_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 26 - -#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 13 - -struct ofdma_trigger_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ax_trigger_source : 1, - rx_trigger_frame_user_source : 2, - received_bandwidth : 3, - txop_duration_all_ones : 1, - eht_trigger_response : 1, - pre_rssi_comb : 8, - rssi_comb : 8, - rxpcu_pcie_l0_req_duration : 8; - uint32_t he_trigger_ul_ppdu_length : 5, - he_trigger_ru_allocation : 8, - he_trigger_dl_tx_power : 5, - he_trigger_ul_target_rssi : 5, - he_trigger_ul_mcs : 2, - he_trigger_reserved : 1, - bss_color : 6; - uint32_t trigger_type : 4, - lsig_response_length : 12, - cascade_indication : 1, - carrier_sense : 1, - bandwidth : 2, - cp_ltf_size : 2, - mu_mimo_ltf_mode : 1, - number_of_ltfs : 3, - stbc : 1, - ldpc_extra_symbol : 1, - ap_tx_power_lsb_part : 4; - uint32_t ap_tx_power_msb_part : 2, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - spatial_reuse : 16, - doppler : 1, - he_siga_reserved : 9, - reserved_3b : 1; - uint32_t aid12 : 12, - ru_allocation : 9, - mcs : 4, - dcm : 1, - start_spatial_stream : 3, - number_of_spatial_stream : 3; - uint32_t target_rssi : 7, - coding_type : 1, - mpdu_mu_spacing_factor : 2, - tid_aggregation_limit : 3, - reserved_5b : 1, - prefered_ac : 2, - bar_control_ack_policy : 1, - bar_control_multi_tid : 1, - bar_control_compressed_bitmap : 1, - bar_control_reserved : 9, - bar_control_tid_info : 4; - uint32_t nr0_per_tid_info_reserved : 12, - nr0_per_tid_info_tid_value : 4, - nr0_start_seq_ctrl_frag_number : 4, - nr0_start_seq_ctrl_start_seq_number : 12; - uint32_t nr1_per_tid_info_reserved : 12, - nr1_per_tid_info_tid_value : 4, - nr1_start_seq_ctrl_frag_number : 4, - nr1_start_seq_ctrl_start_seq_number : 12; - uint32_t nr2_per_tid_info_reserved : 12, - nr2_per_tid_info_tid_value : 4, - nr2_start_seq_ctrl_frag_number : 4, - nr2_start_seq_ctrl_start_seq_number : 12; - uint32_t nr3_per_tid_info_reserved : 12, - nr3_per_tid_info_tid_value : 4, - nr3_start_seq_ctrl_frag_number : 4, - nr3_start_seq_ctrl_start_seq_number : 12; - uint32_t nr4_per_tid_info_reserved : 12, - nr4_per_tid_info_tid_value : 4, - nr4_start_seq_ctrl_frag_number : 4, - nr4_start_seq_ctrl_start_seq_number : 12; - uint32_t nr5_per_tid_info_reserved : 12, - nr5_per_tid_info_tid_value : 4, - nr5_start_seq_ctrl_frag_number : 4, - nr5_start_seq_ctrl_start_seq_number : 12; - uint32_t nr6_per_tid_info_reserved : 12, - nr6_per_tid_info_tid_value : 4, - nr6_start_seq_ctrl_frag_number : 4, - nr6_start_seq_ctrl_start_seq_number : 12; - uint32_t nr7_per_tid_info_reserved : 12, - nr7_per_tid_info_tid_value : 4, - nr7_start_seq_ctrl_frag_number : 4, - nr7_start_seq_ctrl_start_seq_number : 12; - uint32_t fb_segment_retransmission_bitmap : 8, - reserved_14a : 2, - u_sig_puncture_pattern_encoding : 6, - dot11be_puncture_bitmap : 16; - uint32_t rx_chain_mask : 8, - rx_duration_field : 16, - scrambler_seed : 7, - rx_chain_mask_type : 1; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t normalized_pre_rssi_comb : 8, - normalized_rssi_comb : 8; - uint32_t sw_peer_id : 16, - response_tx_duration : 16; - uint32_t __reserved_g_0022_trigger_subtype : 4, - tbr_trigger_common_info_79_68 : 12, - tbr_trigger_sound_reserved_20_12 : 9, - i2r_rep : 3, - tbr_trigger_sound_reserved_25_24 : 2, - reserved_18a : 1, - qos_null_only_response_tx : 1; - uint32_t tbr_trigger_sound_sac : 16, - reserved_19a : 8, - u_sig_reserved2 : 5, - reserved_19b : 3; - uint32_t eht_special_aid12 : 12, - phy_version : 3, - bandwidth_ext : 2, - eht_spatial_reuse : 8, - u_sig_reserved1 : 7; - uint32_t eht_trigger_special_user_info_71_40 : 32; - uint32_t __reserved_g_0035 : 1, - __reserved_g_0035_trigger_subtype : 4, - blackout_details_en : 1, - uhr_trig_response : 1, - mcs_ext : 1, - dso_primary20_index_select : 4, - dso_icf_reception : 1, - dru_spreading_bw : 2, - dru_indication_per_80mhz : 4, - coding_type_ext : 1, - pad_duration : 5, - ects_as_tb_ppdu : 1, - reserved_22a : 6; - uint32_t dso_cca_puncture_pattern : 16, - dso_freq_subband_channel_bonding_mask : 16; - uint32_t reserved_24a : 32; - uint32_t reserved_25a : 32; -#else - uint32_t rxpcu_pcie_l0_req_duration : 8, - rssi_comb : 8, - pre_rssi_comb : 8, - eht_trigger_response : 1, - txop_duration_all_ones : 1, - received_bandwidth : 3, - rx_trigger_frame_user_source : 2, - ax_trigger_source : 1; - uint32_t bss_color : 6, - he_trigger_reserved : 1, - he_trigger_ul_mcs : 2, - he_trigger_ul_target_rssi : 5, - he_trigger_dl_tx_power : 5, - he_trigger_ru_allocation : 8, - he_trigger_ul_ppdu_length : 5; - uint32_t ap_tx_power_lsb_part : 4, - ldpc_extra_symbol : 1, - stbc : 1, - number_of_ltfs : 3, - mu_mimo_ltf_mode : 1, - cp_ltf_size : 2, - bandwidth : 2, - carrier_sense : 1, - cascade_indication : 1, - lsig_response_length : 12, - trigger_type : 4; - uint32_t reserved_3b : 1, - he_siga_reserved : 9, - doppler : 1, - spatial_reuse : 16, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - ap_tx_power_msb_part : 2; - uint32_t number_of_spatial_stream : 3, - start_spatial_stream : 3, - dcm : 1, - mcs : 4, - ru_allocation : 9, - aid12 : 12; - uint32_t bar_control_tid_info : 4, - bar_control_reserved : 9, - bar_control_compressed_bitmap : 1, - bar_control_multi_tid : 1, - bar_control_ack_policy : 1, - prefered_ac : 2, - reserved_5b : 1, - tid_aggregation_limit : 3, - mpdu_mu_spacing_factor : 2, - coding_type : 1, - target_rssi : 7; - uint32_t nr0_start_seq_ctrl_start_seq_number : 12, - nr0_start_seq_ctrl_frag_number : 4, - nr0_per_tid_info_tid_value : 4, - nr0_per_tid_info_reserved : 12; - uint32_t nr1_start_seq_ctrl_start_seq_number : 12, - nr1_start_seq_ctrl_frag_number : 4, - nr1_per_tid_info_tid_value : 4, - nr1_per_tid_info_reserved : 12; - uint32_t nr2_start_seq_ctrl_start_seq_number : 12, - nr2_start_seq_ctrl_frag_number : 4, - nr2_per_tid_info_tid_value : 4, - nr2_per_tid_info_reserved : 12; - uint32_t nr3_start_seq_ctrl_start_seq_number : 12, - nr3_start_seq_ctrl_frag_number : 4, - nr3_per_tid_info_tid_value : 4, - nr3_per_tid_info_reserved : 12; - uint32_t nr4_start_seq_ctrl_start_seq_number : 12, - nr4_start_seq_ctrl_frag_number : 4, - nr4_per_tid_info_tid_value : 4, - nr4_per_tid_info_reserved : 12; - uint32_t nr5_start_seq_ctrl_start_seq_number : 12, - nr5_start_seq_ctrl_frag_number : 4, - nr5_per_tid_info_tid_value : 4, - nr5_per_tid_info_reserved : 12; - uint32_t nr6_start_seq_ctrl_start_seq_number : 12, - nr6_start_seq_ctrl_frag_number : 4, - nr6_per_tid_info_tid_value : 4, - nr6_per_tid_info_reserved : 12; - uint32_t nr7_start_seq_ctrl_start_seq_number : 12, - nr7_start_seq_ctrl_frag_number : 4, - nr7_per_tid_info_tid_value : 4, - nr7_per_tid_info_reserved : 12; - uint32_t dot11be_puncture_bitmap : 16, - u_sig_puncture_pattern_encoding : 6, - reserved_14a : 2, - fb_segment_retransmission_bitmap : 8; - uint32_t rx_chain_mask_type : 1, - scrambler_seed : 7, - rx_duration_field : 16, - rx_chain_mask : 8; - uint32_t normalized_rssi_comb : 8, - normalized_pre_rssi_comb : 8; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint32_t response_tx_duration : 16, - sw_peer_id : 16; - uint32_t qos_null_only_response_tx : 1, - reserved_18a : 1, - tbr_trigger_sound_reserved_25_24 : 2, - i2r_rep : 3, - tbr_trigger_sound_reserved_20_12 : 9, - tbr_trigger_common_info_79_68 : 12, - __reserved_g_0022_trigger_subtype : 4; - uint32_t reserved_19b : 3, - u_sig_reserved2 : 5, - reserved_19a : 8, - tbr_trigger_sound_sac : 16; - uint32_t u_sig_reserved1 : 7, - eht_spatial_reuse : 8, - bandwidth_ext : 2, - phy_version : 3, - eht_special_aid12 : 12; - uint32_t eht_trigger_special_user_info_71_40 : 32; - uint32_t reserved_22a : 6, - ects_as_tb_ppdu : 1, - pad_duration : 5, - coding_type_ext : 1, - dru_indication_per_80mhz : 4, - dru_spreading_bw : 2, - dso_icf_reception : 1, - dso_primary20_index_select : 4, - mcs_ext : 1, - uhr_trig_response : 1, - blackout_details_en : 1, - __reserved_g_0035_trigger_subtype : 4, - __reserved_g_0035 : 1; - uint32_t dso_freq_subband_channel_bonding_mask : 16, - dso_cca_puncture_pattern : 16; - uint32_t reserved_24a : 32; - uint32_t reserved_25a : 32; -#endif -}; - -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001 - -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006 - -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038 - -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040 - -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080 - -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00 - -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000 - -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000 - -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000 - -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f - -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0 - -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000 - -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000 - -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000 - -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000 - -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000 - -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000 - -#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 -#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 -#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000 - -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000 - -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000 - -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000 - -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000 - -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000 - -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000 - -#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000 - -#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 -#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 -#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000 - -#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 -#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 -#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000 - -#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 -#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 -#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000 - -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000 - -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000 - -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000 - -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000 - -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000 - -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000 - -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff - -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00 - -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000 - -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000 - -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000 - -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000 - -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 - -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 - -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000 - -#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000 - -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000 - -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000 - -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000 - -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000 - -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000 - -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_LSB 5 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MSB 5 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MASK 0x0000000000000020 - -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_LSB 6 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MSB 6 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MASK 0x0000000000000040 - -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_LSB 7 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MSB 7 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MASK 0x0000000000000080 - -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_LSB 8 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MSB 11 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MASK 0x0000000000000f00 - -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MSB 12 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MASK 0x0000000000001000 - -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_LSB 13 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MSB 14 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MASK 0x0000000000006000 - -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_LSB 15 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MSB 18 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MASK 0x0000000000078000 - -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_LSB 19 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MSB 19 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MASK 0x0000000000080000 - -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_LSB 20 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MSB 24 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MASK 0x0000000001f00000 - -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 25 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 25 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x0000000002000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_LSB 26 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MASK 0x00000000fc000000 - -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_LSB 32 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MSB 47 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 48 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 63 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0xffff000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_LSB 0 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MASK 0x00000000ffffffff - -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_LSB 32 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/fig/v1/pcu_ppdu_setup_init.h deleted file mode 100644 index 621b649df965..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/pcu_ppdu_setup_init.h +++ /dev/null @@ -1,2309 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PCU_PPDU_SETUP_INIT_H_ -#define _PCU_PPDU_SETUP_INIT_H_ - -#include "pdg_response_rate_setting.h" -#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 - -#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29 - -struct pcu_ppdu_setup_init { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t medium_prot_type : 3, - response_type : 5, - response_info_part2_required : 1, - response_to_response : 3, - mba_user_order : 2, - expected_mba_size : 11, - required_ul_mu_resp_user_count : 6, - transmitted_bssid_check_en : 1; - uint32_t mprot_required_bw1 : 1, - mprot_required_bw20 : 1, - mprot_required_bw40 : 1, - mprot_required_bw80 : 1, - mprot_required_bw160 : 1, - mprot_required_bw240 : 1, - mprot_required_bw320 : 1, - ppdu_allowed_bw1 : 1, - ppdu_allowed_bw20 : 1, - ppdu_allowed_bw40 : 1, - ppdu_allowed_bw80 : 1, - ppdu_allowed_bw160 : 1, - ppdu_allowed_bw240 : 1, - ppdu_allowed_bw320 : 1, - set_fc_pwr_mgt : 1, - use_cts_duration_for_data_tx : 1, - update_timestamp_64 : 1, - update_timestamp_32_lower : 1, - update_timestamp_32_upper : 1, - reserved_1a : 13; - uint32_t insert_timestamp_offset_0 : 16, - insert_timestamp_offset_1 : 16; - uint32_t max_bw40_try_count : 4, - max_bw80_try_count : 4, - max_bw160_try_count : 4, - max_bw240_try_count : 4, - max_bw320_try_count : 4, - insert_wur_timestamp_offset : 6, - update_wur_timestamp : 1, - wur_embedded_bssid_present : 1, - insert_wur_fcs : 1, - reserved_3b : 3; - struct pdg_response_rate_setting response_to_response_rate_info_bw20; - struct pdg_response_rate_setting response_to_response_rate_info_bw40; - struct pdg_response_rate_setting response_to_response_rate_info_bw80; - struct pdg_response_rate_setting response_to_response_rate_info_bw160; - struct pdg_response_rate_setting response_to_response_rate_info_bw240; - struct pdg_response_rate_setting response_to_response_rate_info_bw320; - uint32_t r2r_hw_response_tx_duration : 16, - r2r_rx_duration_field : 16; - uint32_t r2r_group_id : 6, - r2r_response_frame_type : 4, - r2r_sta_partial_aid : 11, - use_address_fields_for_protection : 1, - r2r_set_required_response_time : 1, - reserved_29a : 3, - r2r_bw20_active_channel : 3, - r2r_bw40_active_channel : 3; - uint32_t r2r_bw80_active_channel : 3, - r2r_bw160_active_channel : 3, - r2r_bw240_active_channel : 3, - r2r_bw320_active_channel : 3, - r2r_bw20 : 3, - r2r_bw40 : 3, - r2r_bw80 : 3, - r2r_bw160 : 3, - r2r_bw240 : 3, - r2r_bw320 : 3, - tx_with_blackout_details : 1, - expect_rx_with_blackout_details : 1; - uint32_t mu_response_expected_bitmap_31_0 : 32; - uint32_t mu_response_expected_bitmap_36_32 : 5, - mu_expected_response_cbf_count : 6, - mu_expected_response_sta_count : 6, - transmit_includes_multidestination : 1, - insert_prev_tx_start_timing_info : 1, - insert_current_tx_start_timing_info : 1, - tx_start_transmit_time_byte_offset : 12; - uint32_t protection_frame_ad1_31_0 : 32; - uint32_t protection_frame_ad1_47_32 : 16, - protection_frame_ad2_15_0 : 16; - uint32_t protection_frame_ad2_47_16 : 32; - uint32_t dynamic_medium_prot_threshold : 24, - dynamic_medium_prot_type : 1, - reserved_54a : 7; - uint32_t protection_frame_ad3_31_0 : 32; - uint32_t protection_frame_ad3_47_32 : 16, - protection_frame_ad4_15_0 : 16; - uint32_t protection_frame_ad4_47_16 : 32; -#else - uint32_t transmitted_bssid_check_en : 1, - required_ul_mu_resp_user_count : 6, - expected_mba_size : 11, - mba_user_order : 2, - response_to_response : 3, - response_info_part2_required : 1, - response_type : 5, - medium_prot_type : 3; - uint32_t reserved_1a : 13, - update_timestamp_32_upper : 1, - update_timestamp_32_lower : 1, - update_timestamp_64 : 1, - use_cts_duration_for_data_tx : 1, - set_fc_pwr_mgt : 1, - ppdu_allowed_bw320 : 1, - ppdu_allowed_bw240 : 1, - ppdu_allowed_bw160 : 1, - ppdu_allowed_bw80 : 1, - ppdu_allowed_bw40 : 1, - ppdu_allowed_bw20 : 1, - ppdu_allowed_bw1 : 1, - mprot_required_bw320 : 1, - mprot_required_bw240 : 1, - mprot_required_bw160 : 1, - mprot_required_bw80 : 1, - mprot_required_bw40 : 1, - mprot_required_bw20 : 1, - mprot_required_bw1 : 1; - uint32_t insert_timestamp_offset_1 : 16, - insert_timestamp_offset_0 : 16; - uint32_t reserved_3b : 3, - insert_wur_fcs : 1, - wur_embedded_bssid_present : 1, - update_wur_timestamp : 1, - insert_wur_timestamp_offset : 6, - max_bw320_try_count : 4, - max_bw240_try_count : 4, - max_bw160_try_count : 4, - max_bw80_try_count : 4, - max_bw40_try_count : 4; - struct pdg_response_rate_setting response_to_response_rate_info_bw20; - struct pdg_response_rate_setting response_to_response_rate_info_bw40; - struct pdg_response_rate_setting response_to_response_rate_info_bw80; - struct pdg_response_rate_setting response_to_response_rate_info_bw160; - struct pdg_response_rate_setting response_to_response_rate_info_bw240; - struct pdg_response_rate_setting response_to_response_rate_info_bw320; - uint32_t r2r_rx_duration_field : 16, - r2r_hw_response_tx_duration : 16; - uint32_t r2r_bw40_active_channel : 3, - r2r_bw20_active_channel : 3, - reserved_29a : 3, - r2r_set_required_response_time : 1, - use_address_fields_for_protection : 1, - r2r_sta_partial_aid : 11, - r2r_response_frame_type : 4, - r2r_group_id : 6; - uint32_t expect_rx_with_blackout_details : 1, - tx_with_blackout_details : 1, - r2r_bw320 : 3, - r2r_bw240 : 3, - r2r_bw160 : 3, - r2r_bw80 : 3, - r2r_bw40 : 3, - r2r_bw20 : 3, - r2r_bw320_active_channel : 3, - r2r_bw240_active_channel : 3, - r2r_bw160_active_channel : 3, - r2r_bw80_active_channel : 3; - uint32_t mu_response_expected_bitmap_31_0 : 32; - uint32_t tx_start_transmit_time_byte_offset : 12, - insert_current_tx_start_timing_info : 1, - insert_prev_tx_start_timing_info : 1, - transmit_includes_multidestination : 1, - mu_expected_response_sta_count : 6, - mu_expected_response_cbf_count : 6, - mu_response_expected_bitmap_36_32 : 5; - uint32_t protection_frame_ad1_31_0 : 32; - uint32_t protection_frame_ad2_15_0 : 16, - protection_frame_ad1_47_32 : 16; - uint32_t protection_frame_ad2_47_16 : 32; - uint32_t reserved_54a : 7, - dynamic_medium_prot_type : 1, - dynamic_medium_prot_threshold : 24; - uint32_t protection_frame_ad3_31_0 : 32; - uint32_t protection_frame_ad4_15_0 : 16, - protection_frame_ad3_47_32 : 16; - uint32_t protection_frame_ad4_47_16 : 32; -#endif -}; - -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x0000000000000007 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x00000000000000f8 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0000000000000100 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x0000000000000e00 - -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x0000000000003000 - -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x0000000001ffc000 - -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x000000007e000000 - -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 32 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 32 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 33 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 33 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x0000000200000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 34 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 34 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x0000000400000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 35 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 35 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x0000000800000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 36 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 36 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x0000001000000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 37 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 37 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x0000002000000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 38 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 38 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x0000004000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 39 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 39 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 40 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 40 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x0000010000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 41 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 41 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x0000020000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 42 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 42 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 43 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 43 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 44 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 44 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 45 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 45 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 46 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 46 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 47 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 47 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 48 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 48 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x0001000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 49 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 49 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x0002000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 50 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 50 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x0004000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff8000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 32 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 35 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 36 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 39 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 40 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 43 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f0000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 44 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 47 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f00000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 48 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 51 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 52 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 57 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 58 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 58 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 59 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 59 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x0800000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 60 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 60 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x1000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xe000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 37 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f00000000 - -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 38 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 41 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 42 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 52 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc0000000000 - -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 53 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 53 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 54 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 54 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x0040000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 55 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x0380000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 58 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 60 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c00000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 61 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 63 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe000000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x0000000000000007 - -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x0000000000000038 - -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x00000000000001c0 - -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x0000000000000e00 - -#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x0000000000007000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x0000000000038000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x0000000000e00000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x0000000007000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_LSB 30 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MSB 30 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB 31 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB 31 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x00000000000007e0 - -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x000000000001f800 - -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x0000000000020000 - -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x0000000000040000 - -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0x00000000fff00000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x0000000000ffffff - -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0x00000000fe000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/pdg_response.h b/drivers/staging/fw-api/hw/fig/v1/pdg_response.h deleted file mode 100644 index a730a445ed10..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/pdg_response.h +++ /dev/null @@ -1,503 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_RESPONSE_H_ -#define _PDG_RESPONSE_H_ - -#include "pdg_response_rate_setting.h" -#define NUM_OF_DWORDS_PDG_RESPONSE 14 - -#define NUM_OF_QWORDS_PDG_RESPONSE 7 - -struct pdg_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct pdg_response_rate_setting hw_response_rate_info; - uint32_t hw_response_tx_duration : 16, - rx_duration_field : 16; - uint32_t punctured_response_transmission : 1, - cca_subband_channel_bonding_mask : 16, - scrambler_seed_override : 2, - response_density_valid : 1, - response_density : 5, - more_data : 1, - duration_indication : 1, - blackout_details_en : 1, - reserved_8a : 1, - bandwidth : 3; - uint32_t ack_id : 16, - block_ack_bitmap : 16; - uint32_t response_frame_type : 4, - ack_id_ext : 10, - ftm_en : 1, - group_id : 6, - sta_partial_aid : 11; - uint32_t ndp_ba_start_seq_ctrl : 12, - active_channel : 3, - txop_duration_all_ones : 1, - frame_length : 16; - uint32_t dso_primary20_index_select : 4, - dso_freq_subband_channel_bonding_mask : 16, - pad_duration : 5, - reserved_12a : 7; - uint32_t tlv64_padding : 32; -#else - struct pdg_response_rate_setting hw_response_rate_info; - uint32_t rx_duration_field : 16, - hw_response_tx_duration : 16; - uint32_t bandwidth : 3, - reserved_8a : 1, - blackout_details_en : 1, - duration_indication : 1, - more_data : 1, - response_density : 5, - response_density_valid : 1, - scrambler_seed_override : 2, - cca_subband_channel_bonding_mask : 16, - punctured_response_transmission : 1; - uint32_t block_ack_bitmap : 16, - ack_id : 16; - uint32_t sta_partial_aid : 11, - group_id : 6, - ftm_en : 1, - ack_id_ext : 10, - response_frame_type : 4; - uint32_t frame_length : 16, - txop_duration_all_ones : 1, - active_channel : 3, - ndp_ba_start_seq_ctrl : 12; - uint32_t reserved_12a : 7, - pad_duration : 5, - dso_freq_subband_channel_bonding_mask : 16, - dso_primary20_index_select : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MSB 3 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MASK 0x000000000000000f - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 36 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 37 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000e000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 46 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00007c0000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_LSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000 - -#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48 -#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63 -#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000 - -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001 - -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe - -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000 - -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000 - -#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 -#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 -#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000 - -#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_MORE_DATA_LSB 25 -#define PDG_RESPONSE_MORE_DATA_MSB 25 -#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000 - -#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 -#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 -#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000 - -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_LSB 27 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MSB 27 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MASK 0x0000000008000000 - -#define PDG_RESPONSE_RESERVED_8A_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESERVED_8A_LSB 28 -#define PDG_RESPONSE_RESERVED_8A_MSB 28 -#define PDG_RESPONSE_RESERVED_8A_MASK 0x0000000010000000 - -#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BANDWIDTH_LSB 29 -#define PDG_RESPONSE_BANDWIDTH_MSB 31 -#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000 - -#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_ACK_ID_LSB 32 -#define PDG_RESPONSE_ACK_ID_MSB 47 -#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000 - -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000 - -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f - -#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 -#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 -#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0 - -#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_FTM_EN_LSB 14 -#define PDG_RESPONSE_FTM_EN_MSB 14 -#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000 - -#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_GROUP_ID_LSB 15 -#define PDG_RESPONSE_GROUP_ID_MSB 20 -#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000 - -#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 -#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 -#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000 - -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000 - -#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44 -#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46 -#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000 - -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000 - -#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_FRAME_LENGTH_LSB 48 -#define PDG_RESPONSE_FRAME_LENGTH_MSB 63 -#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000 - -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_LSB 0 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MSB 3 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MASK 0x000000000000000f - -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 4 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 19 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x00000000000ffff0 - -#define PDG_RESPONSE_PAD_DURATION_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_PAD_DURATION_LSB 20 -#define PDG_RESPONSE_PAD_DURATION_MSB 24 -#define PDG_RESPONSE_PAD_DURATION_MASK 0x0000000001f00000 - -#define PDG_RESPONSE_RESERVED_12A_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_RESERVED_12A_LSB 25 -#define PDG_RESPONSE_RESERVED_12A_MSB 31 -#define PDG_RESPONSE_RESERVED_12A_MASK 0x00000000fe000000 - -#define PDG_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_TLV64_PADDING_LSB 32 -#define PDG_RESPONSE_TLV64_PADDING_MSB 63 -#define PDG_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/pdg_response_rate_setting.h b/drivers/staging/fw-api/hw/fig/v1/pdg_response_rate_setting.h deleted file mode 100644 index eb123386f2bf..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/pdg_response_rate_setting.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_RESPONSE_RATE_SETTING_H_ -#define _PDG_RESPONSE_RATE_SETTING_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 - -struct pdg_response_rate_setting { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 1, - tx_antenna_sector_ctrl : 24, - pkt_type : 4, - smoothing : 1, - ldpc : 1, - stbc : 1; - uint32_t alt_tx_pwr : 8, - alt_min_tx_pwr : 8, - alt_nss : 3, - alt_tx_chain_mask : 8, - alt_bw : 3, - stf_ltf_3db_boost : 1, - force_extra_symbol : 1; - uint32_t reserved_2a : 4, - nss : 3, - dpd_enable : 1, - tx_pwr : 8, - min_tx_pwr : 8, - tx_chain_mask : 8; - uint32_t alt_rate_mcs : 5, - reserved_3a : 3, - sgi : 2, - rate_mcs : 5, - ldpc_2x_codeword : 1, - tx_pwr_1 : 8, - alt_tx_pwr_1 : 8; - uint32_t aggregation : 1, - dot11ax_bss_color_id : 6, - dot11ax_spatial_reuse : 4, - dot11ax_cp_ltf_size : 2, - dot11ax_dcm : 1, - dot11ax_doppler_indication : 1, - dot11ax_su_extended : 1, - dot11ax_min_packet_extension : 2, - dot11ax_pe_nss : 3, - dot11ax_pe_content : 1, - dot11ax_pe_ltf_size : 2, - dot11ax_chain_csd_en : 1, - dot11ax_pe_chain_csd_en : 1, - dot11ax_dl_ul_flag : 1, - reserved_4a : 5; - uint32_t dot11ax_ext_ru_start_index : 4, - dot11ax_ext_ru_size : 4, - eht_duplicate_mode : 2, - he_sigb_dcm : 1, - he_sigb_0_mcs : 3, - num_he_sigb_sym : 5, - required_response_time_source : 1, - reserved_5a : 6, - u_sig_puncture_pattern_encoding : 6; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t required_response_time : 12, - dot11be_params_placeholder : 4; -#else - uint32_t stbc : 1, - ldpc : 1, - smoothing : 1, - pkt_type : 4, - tx_antenna_sector_ctrl : 24, - reserved_0a : 1; - uint32_t force_extra_symbol : 1, - stf_ltf_3db_boost : 1, - alt_bw : 3, - alt_tx_chain_mask : 8, - alt_nss : 3, - alt_min_tx_pwr : 8, - alt_tx_pwr : 8; - uint32_t tx_chain_mask : 8, - min_tx_pwr : 8, - tx_pwr : 8, - dpd_enable : 1, - nss : 3, - reserved_2a : 4; - uint32_t alt_tx_pwr_1 : 8, - tx_pwr_1 : 8, - ldpc_2x_codeword : 1, - rate_mcs : 5, - sgi : 2, - reserved_3a : 3, - alt_rate_mcs : 5; - uint32_t reserved_4a : 5, - dot11ax_dl_ul_flag : 1, - dot11ax_pe_chain_csd_en : 1, - dot11ax_chain_csd_en : 1, - dot11ax_pe_ltf_size : 2, - dot11ax_pe_content : 1, - dot11ax_pe_nss : 3, - dot11ax_min_packet_extension : 2, - dot11ax_su_extended : 1, - dot11ax_doppler_indication : 1, - dot11ax_dcm : 1, - dot11ax_cp_ltf_size : 2, - dot11ax_spatial_reuse : 4, - dot11ax_bss_color_id : 6, - aggregation : 1; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_5a : 6, - required_response_time_source : 1, - num_he_sigb_sym : 5, - he_sigb_0_mcs : 3, - he_sigb_dcm : 1, - eht_duplicate_mode : 2, - dot11ax_ext_ru_size : 4, - dot11ax_ext_ru_start_index : 4; - uint32_t dot11be_params_placeholder : 4, - required_response_time : 12; - struct mlo_sta_id_details mlo_sta_id_details_rx; -#endif -}; - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 - -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe - -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 - -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 - -#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 -#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 -#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 - -#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 -#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff - -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 - -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 - -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 - -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MSB 3 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MASK 0x0000000f - -#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 -#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 -#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 - -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 - -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 - -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 - -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 4 -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000001f - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 5 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000e0 - -#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 - -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 14 -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00007c00 - -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_LSB 15 -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MASK 0x00008000 - -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 - -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 - -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 - -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 - -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 - -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 - -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 - -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 - -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/pdg_tx_req.h b/drivers/staging/fw-api/hw/fig/v1/pdg_tx_req.h deleted file mode 100644 index 6baf640807da..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/pdg_tx_req.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_TX_REQ_H_ -#define _PDG_TX_REQ_H_ - -#define NUM_OF_DWORDS_PDG_TX_REQ 2 - -#define NUM_OF_QWORDS_PDG_TX_REQ 1 - -struct pdg_tx_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_reason : 2, - use_puncture_pattern : 2, - req_bw : 3, - puncture_pattern_number : 6, - reserved_0b : 1, - req_paprd : 1, - duration_field_boundary_valid : 1, - duration_field_boundary : 16; - uint32_t puncture_subband_mask : 16, - reserved_0c : 16; -#else - uint32_t duration_field_boundary : 16, - duration_field_boundary_valid : 1, - req_paprd : 1, - reserved_0b : 1, - puncture_pattern_number : 6, - req_bw : 3, - use_puncture_pattern : 2, - tx_reason : 2; - uint32_t reserved_0c : 16, - puncture_subband_mask : 16; -#endif -}; - -#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_TX_REASON_LSB 0 -#define PDG_TX_REQ_TX_REASON_MSB 1 -#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003 - -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c - -#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_REQ_BW_LSB 4 -#define PDG_TX_REQ_REQ_BW_MSB 6 -#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070 - -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80 - -#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_RESERVED_0B_LSB 13 -#define PDG_TX_REQ_RESERVED_0B_MSB 13 -#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000 - -#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_REQ_PAPRD_LSB 14 -#define PDG_TX_REQ_REQ_PAPRD_MSB 14 -#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000 - -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000 - -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000 - -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000 - -#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_RESERVED_0C_LSB 48 -#define PDG_TX_REQ_RESERVED_0C_MSB 63 -#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_abort_request_info.h deleted file mode 100644 index 1f3bf4b817b9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_abort_request_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ -#define _PHYRX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 - -struct phyrx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phyrx_abort_reason : 8, - phy_enters_nap_state : 1, - phy_enters_defer_state : 1, - gain_change_by_main : 1, - gain_change_by_bt : 1, - main_tx_indication : 1, - bt_tx_indication : 1, - concurrent_mode : 1, - reserved_0 : 1, - receive_duration : 16; -#else - uint32_t receive_duration : 16, - reserved_0 : 1, - concurrent_mode : 1, - bt_tx_indication : 1, - main_tx_indication : 1, - gain_change_by_bt : 1, - gain_change_by_main : 1, - phy_enters_defer_state : 1, - phy_enters_nap_state : 1, - phyrx_abort_reason : 8; -#endif -}; - -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff - -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 - -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 - -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB 10 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB 10 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK 0x00000400 - -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB 11 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB 11 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK 0x00000800 - -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB 12 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB 12 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK 0x00001000 - -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB 13 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB 13 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK 0x00002000 - -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB 14 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB 14 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK 0x00004000 - -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 15 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x00008000 - -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_common_user_info.h deleted file mode 100644 index 1aac5bf9fd32..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_common_user_info.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_COMMON_USER_INFO_H_ -#define _PHYRX_COMMON_USER_INFO_H_ - -#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4 - -#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2 - -struct phyrx_common_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t receive_duration : 16, - reserved_0a : 16; - uint32_t u_sig_puncture_pattern_encoding : 6, - eht___reserved_g_0022_ndp : 1, - reserved_1a : 8, - obss_nav_update_enable : 1, - obss_nav_value : 16; - uint32_t eht_or_uhr_ppdu_type : 2, - bss_color_id : 6, - dl_ul_flag : 1, - txop_duration : 7, - cp_setting : 2, - ltf_size : 2, - spatial_reuse : 4, - rx_ndp : 1, - dot11bn_su_elr : 1, - reserved_2a : 6; - uint32_t eht_duplicate : 2, - eht_or_uhr_sig_cmn_field_type : 2, - doppler_indication : 1, - sta_id : 11, - puncture_bitmap : 16; -#else - uint32_t reserved_0a : 16, - receive_duration : 16; - uint32_t obss_nav_value : 16, - obss_nav_update_enable : 1, - reserved_1a : 8, - eht___reserved_g_0022_ndp : 1, - u_sig_puncture_pattern_encoding : 6; - uint32_t reserved_2a : 6, - dot11bn_su_elr : 1, - rx_ndp : 1, - spatial_reuse : 4, - ltf_size : 2, - cp_setting : 2, - txop_duration : 7, - dl_ul_flag : 1, - bss_color_id : 6, - eht_or_uhr_ppdu_type : 2; - uint32_t puncture_bitmap : 16, - sta_id : 11, - doppler_indication : 1, - eht_or_uhr_sig_cmn_field_type : 2, - eht_duplicate : 2; -#endif -}; - -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x000000000000ffff - -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0x00000000ffff0000 - -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 32 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 37 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f00000000 - -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 39 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 46 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0x00007f8000000000 - -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB 47 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB 47 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK 0x0000800000000000 - -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB 48 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB 63 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK 0xffff000000000000 - -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_LSB 0 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MSB 1 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MASK 0x0000000000000003 - -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x00000000000000fc - -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x0000000000000100 - -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x000000000000fe00 - -#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x0000000000030000 - -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x00000000000c0000 - -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x0000000000f00000 - -#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24 -#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24 -#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x0000000001000000 - -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_LSB 25 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MSB 25 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MASK 0x0000000002000000 - -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26 -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31 -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0x00000000fc000000 - -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 32 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 33 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x0000000300000000 - -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_LSB 34 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MSB 35 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MASK 0x0000000c00000000 - -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 36 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 36 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x0000001000000000 - -#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 37 -#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 47 -#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe000000000 - -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 48 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 63 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_dl.h deleted file mode 100644 index da4f1691b9f7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_dl.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ -#define _PHYRX_HE_SIG_A_MU_DL_H_ - -#include "he_sig_a_mu_dl_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1 - -struct phyrx_he_sig_a_mu_dl { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; -#else - struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_ul.h deleted file mode 100644 index ff9cf72a7237..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_ul.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ -#define _PHYRX_HE_SIG_A_MU_UL_H_ - -#include "he_sig_a_mu_ul_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1 - -struct phyrx_he_sig_a_mu_ul { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; -#else - struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_su.h deleted file mode 100644 index abca58673a90..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_su.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_SU_H_ -#define _PHYRX_HE_SIG_A_SU_H_ - -#include "he_sig_a_su_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1 - -struct phyrx_he_sig_a_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; -#else - struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b1_mu.h deleted file mode 100644 index ae784469331b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b1_mu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B1_MU_H_ -#define _PHYRX_HE_SIG_B1_MU_H_ - -#include "he_sig_b1_mu_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1 - -struct phyrx_he_sig_b1_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#else - struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_mu.h deleted file mode 100644 index 6035ecffde5d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_mu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B2_MU_H_ -#define _PHYRX_HE_SIG_B2_MU_H_ - -#include "he_sig_b2_mu_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1 - -struct phyrx_he_sig_b2_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; -#else - struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; -#endif -}; - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_ofdma.h deleted file mode 100644 index 126a9559e155..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_ofdma.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ -#define _PHYRX_HE_SIG_B2_OFDMA_H_ - -#include "he_sig_b2_ofdma_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1 - -struct phyrx_he_sig_b2_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; -#else - struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; -#endif -}; - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_ht_sig.h deleted file mode 100644 index 4dd90653d431..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_ht_sig.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HT_SIG_H_ -#define _PHYRX_HT_SIG_H_ - -#include "ht_sig_info.h" -#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 - -#define NUM_OF_QWORDS_PHYRX_HT_SIG 1 - -struct phyrx_ht_sig { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ht_sig_info phyrx_ht_sig_info_details; -#else - struct ht_sig_info phyrx_ht_sig_info_details; -#endif -}; - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_a.h deleted file mode 100644 index 2e70822f5d06..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_a.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_L_SIG_A_H_ -#define _PHYRX_L_SIG_A_H_ - -#include "l_sig_a_info.h" -#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2 - -#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1 - -struct phyrx_l_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_a_info phyrx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_a_info phyrx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32 -#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63 -#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_b.h deleted file mode 100644 index 461edd24dd4e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_b.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_L_SIG_B_H_ -#define _PHYRX_L_SIG_B_H_ - -#include "l_sig_b_info.h" -#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2 - -#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1 - -struct phyrx_l_sig_b { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_b_info phyrx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_b_info phyrx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32 -#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63 -#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_location.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_location.h deleted file mode 100644 index 15a8413e304a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_location.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_LOCATION_H_ -#define _PHYRX_LOCATION_H_ - -#include "rx_location_info.h" -#define NUM_OF_DWORDS_PHYRX_LOCATION 28 - -#define NUM_OF_QWORDS_PHYRX_LOCATION 14 - -struct phyrx_location { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_location_info rx_location_info_details; -#else - struct rx_location_info rx_location_info_details; -#endif -}; - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_other_receive_info_ru_details.h deleted file mode 100644 index a6090f721e1d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_other_receive_info_ru_details.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ -#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ - -#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4 - -#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2 - -struct phyrx_other_receive_info_ru_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_details_channel_0 : 32; - uint32_t ru_details_channel_1 : 32; - uint32_t spare : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t ru_details_channel_0 : 32; - uint32_t ru_details_channel_1 : 32; - uint32_t spare : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000 - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end.h deleted file mode 100644 index 1d1675edc0e1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end.h +++ /dev/null @@ -1,427 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_PKT_END_H_ -#define _PHYRX_PKT_END_H_ - -#include "phyrx_pkt_end_info.h" -#define NUM_OF_DWORDS_PHYRX_PKT_END 24 - -#define NUM_OF_QWORDS_PHYRX_PKT_END 12 - -struct phyrx_pkt_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct phyrx_pkt_end_info rx_pkt_end_details; -#else - struct phyrx_pkt_end_info rx_pkt_end_details; -#endif -}; - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 44 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 53 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff00000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB 54 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc0000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end_info.h deleted file mode 100644 index a21edc94d24e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end_info.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_PKT_END_INFO_H_ -#define _PHYRX_PKT_END_INFO_H_ - -#include "receive_rssi_info.h" -#include "rx_timing_info.h" -#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 - -struct phyrx_pkt_end_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0001 : 1, - location_info_valid : 1, - timing_info_valid : 1, - rssi_info_valid : 1, - reserved_0a : 1, - frameless_frame_received : 1, - reserved_0b : 2, - rssi_comb : 8, - reserved_0c : 16; - struct rx_timing_info rx_timing_info_details; - struct receive_rssi_info post_rssi_info_details; - uint32_t phy_sw_status_31_0 : 32; - uint32_t phy_sw_status_63_32 : 32; -#else - uint32_t reserved_0c : 16, - rssi_comb : 8, - reserved_0b : 2, - frameless_frame_received : 1, - reserved_0a : 1, - rssi_info_valid : 1, - timing_info_valid : 1, - location_info_valid : 1, - __reserved_g_0001 : 1; - struct rx_timing_info rx_timing_info_details; - struct receive_rssi_info post_rssi_info_details; - uint32_t phy_sw_status_31_0 : 32; - uint32_t phy_sw_status_63_32 : 32; -#endif -}; - -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 - -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 - -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 - -#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 -#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 -#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 - -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 - -#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 -#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 -#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 - -#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 -#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 -#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 -#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 -#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 12 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 21 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff000 - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB 22 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc00000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_rssi_legacy.h deleted file mode 100644 index 820ced6212ca..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_rssi_legacy.h +++ /dev/null @@ -1,806 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_RSSI_LEGACY_H_ -#define _PHYRX_RSSI_LEGACY_H_ - -#include "receive_rssi_info.h" -#include "receive_pkt_start_info.h" -#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 - -#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21 - -struct phyrx_rssi_legacy { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_pkt_start_info rx_pkt_start_details; - uint32_t sw_phy_meta_data : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 32; - struct receive_rssi_info pre_rssi_info_details; - struct receive_rssi_info preamble_rssi_info_details; - uint32_t pre_rssi_comb : 8, - rssi_comb : 8, - normalized_pre_rssi_comb : 8, - normalized_rssi_comb : 8; - uint32_t rssi_comb_ppdu : 8, - rssi_db_to_dbm_offset : 8, - rssi_for_spatial_reuse : 8, - rssi_for_trigger_resp : 8; -#else - struct receive_pkt_start_info rx_pkt_start_details; - uint32_t sw_phy_meta_data : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 32; - struct receive_rssi_info pre_rssi_info_details; - struct receive_rssi_info preamble_rssi_info_details; - uint32_t normalized_rssi_comb : 8, - normalized_pre_rssi_comb : 8, - rssi_comb : 8, - pre_rssi_comb : 8; - uint32_t rssi_for_trigger_resp : 8, - rssi_for_spatial_reuse : 8, - rssi_db_to_dbm_offset : 8, - rssi_comb_ppdu : 8; -#endif -}; - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB 3 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK 0x000000000000000f - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x0000000000000010 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB 5 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB 7 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00000000000000e0 - -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB 8 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB 15 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB 16 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB 32 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB 63 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB 32 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB 39 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB 40 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB 40 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK 0x0000010000000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB 41 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB 63 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK 0xfffffe0000000000 - -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x0000000000000010 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 31 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x0000000000000010 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 32 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 63 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x0000000000000018 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000000000000018 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 32 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 63 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 32 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 39 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 40 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 47 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 48 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 55 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 56 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 63 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_user_info.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_user_info.h deleted file mode 100644 index d3dc8b6b2414..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_user_info.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_USER_INFO_H_ -#define _PHYRX_USER_INFO_H_ - -#include "receive_user_info.h" -#define NUM_OF_DWORDS_PHYRX_USER_INFO 8 - -#define NUM_OF_QWORDS_PHYRX_USER_INFO 4 - -struct phyrx_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_user_info receive_user_info_details; -#else - struct receive_user_info receive_user_info_details; -#endif -}; - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 36 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000001f00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 37 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 38 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000006000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 1 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x0000000000000002 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB 2 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB 3 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK 0x000000000000000c - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB 4 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB 5 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK 0x0000000000000030 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB 6 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB 7 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK 0x00000000000000c0 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_vht_sig_a.h deleted file mode 100644 index e47f0e35adeb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_vht_sig_a.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_VHT_SIG_A_H_ -#define _PHYRX_VHT_SIG_A_H_ - -#include "vht_sig_a_info.h" -#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 - -#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1 - -struct phyrx_vht_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_a_info phyrx_vht_sig_a_info_details; -#else - struct vht_sig_a_info phyrx_vht_sig_a_info_details; -#endif -}; - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phytx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v1/phytx_abort_request_info.h deleted file mode 100644 index e4800f6a2d97..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phytx_abort_request_info.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ -#define _PHYTX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 - -struct phytx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t phytx_abort_reason : 8, - user_number : 6, - reserved : 2; -#else - uint16_t reserved : 2, - user_number : 6, - phytx_abort_reason : 8; -#endif -}; - -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff - -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 - -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phytx_pkt_end.h b/drivers/staging/fw-api/hw/fig/v1/phytx_pkt_end.h deleted file mode 100644 index 55911ea9edb3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phytx_pkt_end.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_PKT_END_H_ -#define _PHYTX_PKT_END_H_ - -#define NUM_OF_WORDS_PHYTX_PKT_END 28 - -#define NUM_OF_DWORDS_PHYTX_PKT_END 14 - -struct phytx_pkt_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t start_of_frame_timestamp_15_0 : 16; - uint16_t start_of_frame_timestamp_31_16 : 16; - uint16_t end_of_frame_timestamp_15_0 : 16; - uint16_t end_of_frame_timestamp_31_16 : 16; - uint16_t tx_group_delay : 12, - timing_status : 2, - phyrx_entered_nap_state : 1, - dpdtrain_done : 1; - uint16_t transmit_delay : 16; - uint16_t tpc_dbg_info_cmn_15_0 : 16; - uint16_t tpc_dbg_info_cmn_31_16 : 16; - uint16_t tpc_dbg_info_cmn_47_32 : 16; - uint16_t tpc_dbg_info_chn1_15_0 : 16; - uint16_t tpc_dbg_info_chn1_31_16 : 16; - uint16_t tpc_dbg_info_chn1_47_32 : 16; - uint16_t tpc_dbg_info_chn1_63_48 : 16; - uint16_t tpc_dbg_info_chn1_79_64 : 16; - uint16_t tpc_dbg_info_chn2_15_0 : 16; - uint16_t tpc_dbg_info_chn2_31_16 : 16; - uint16_t tpc_dbg_info_chn2_47_32 : 16; - uint16_t tpc_dbg_info_chn2_63_48 : 16; - uint16_t tpc_dbg_info_chn2_79_64 : 16; - uint16_t phytx_tx_end_sw_info_15_0 : 16; - uint16_t phytx_tx_end_sw_info_31_16 : 16; - uint16_t phytx_tx_end_sw_info_47_32 : 16; - uint16_t phytx_tx_end_sw_info_63_48 : 16; - uint16_t beamform_masked_user_bitmap_15_0 : 16; - uint16_t beamform_masked_user_bitmap_31_16 : 16; - uint16_t beamform_masked_user_bitmap_36_32 : 5, - reserved_23 : 11; - uint16_t reserved_26 : 16; - uint16_t reserved_27 : 16; -#else - uint16_t start_of_frame_timestamp_15_0 : 16; - uint16_t start_of_frame_timestamp_31_16 : 16; - uint16_t end_of_frame_timestamp_15_0 : 16; - uint16_t end_of_frame_timestamp_31_16 : 16; - uint16_t dpdtrain_done : 1, - phyrx_entered_nap_state : 1, - timing_status : 2, - tx_group_delay : 12; - uint16_t transmit_delay : 16; - uint16_t tpc_dbg_info_cmn_15_0 : 16; - uint16_t tpc_dbg_info_cmn_31_16 : 16; - uint16_t tpc_dbg_info_cmn_47_32 : 16; - uint16_t tpc_dbg_info_chn1_15_0 : 16; - uint16_t tpc_dbg_info_chn1_31_16 : 16; - uint16_t tpc_dbg_info_chn1_47_32 : 16; - uint16_t tpc_dbg_info_chn1_63_48 : 16; - uint16_t tpc_dbg_info_chn1_79_64 : 16; - uint16_t tpc_dbg_info_chn2_15_0 : 16; - uint16_t tpc_dbg_info_chn2_31_16 : 16; - uint16_t tpc_dbg_info_chn2_47_32 : 16; - uint16_t tpc_dbg_info_chn2_63_48 : 16; - uint16_t tpc_dbg_info_chn2_79_64 : 16; - uint16_t phytx_tx_end_sw_info_15_0 : 16; - uint16_t phytx_tx_end_sw_info_31_16 : 16; - uint16_t phytx_tx_end_sw_info_47_32 : 16; - uint16_t phytx_tx_end_sw_info_63_48 : 16; - uint16_t beamform_masked_user_bitmap_15_0 : 16; - uint16_t beamform_masked_user_bitmap_31_16 : 16; - uint16_t reserved_23 : 11, - beamform_masked_user_bitmap_36_32 : 5; - uint16_t reserved_26 : 16; - uint16_t reserved_27 : 16; -#endif -}; - -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000000 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000002 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 0 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 15 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000004 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000006 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 0 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 15 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET 0x00000008 -#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB 0 -#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB 11 -#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK 0x00000fff - -#define PHYTX_PKT_END_TIMING_STATUS_OFFSET 0x00000008 -#define PHYTX_PKT_END_TIMING_STATUS_LSB 12 -#define PHYTX_PKT_END_TIMING_STATUS_MSB 13 -#define PHYTX_PKT_END_TIMING_STATUS_MASK 0x00003000 - -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET 0x00000008 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB 14 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB 14 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK 0x00004000 - -#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET 0x00000008 -#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB 15 -#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB 15 -#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK 0x00008000 - -#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET 0x0000000a -#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB 0 -#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB 15 -#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000c -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000e -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET 0x00000010 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x00000012 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x00000014 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x00000016 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x00000018 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000001a -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000001c -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000001e -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x00000020 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x00000022 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x00000024 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x00000026 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x00000028 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000002a -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000002c -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000002e -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x00000030 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 15 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000032 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 4 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x0000001f - -#define PHYTX_PKT_END_RESERVED_23_OFFSET 0x00000032 -#define PHYTX_PKT_END_RESERVED_23_LSB 5 -#define PHYTX_PKT_END_RESERVED_23_MSB 15 -#define PHYTX_PKT_END_RESERVED_23_MASK 0x0000ffe0 - -#define PHYTX_PKT_END_RESERVED_26_OFFSET 0x00000034 -#define PHYTX_PKT_END_RESERVED_26_LSB 0 -#define PHYTX_PKT_END_RESERVED_26_MSB 15 -#define PHYTX_PKT_END_RESERVED_26_MASK 0x0000ffff - -#define PHYTX_PKT_END_RESERVED_27_OFFSET 0x00000036 -#define PHYTX_PKT_END_RESERVED_27_LSB 0 -#define PHYTX_PKT_END_RESERVED_27_MSB 15 -#define PHYTX_PKT_END_RESERVED_27_MASK 0x0000ffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phytx_ppdu_header_info_request.h b/drivers/staging/fw-api/hw/fig/v1/phytx_ppdu_header_info_request.h deleted file mode 100644 index 7fbecae41236..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phytx_ppdu_header_info_request.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ -#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ - -#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 - -#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 - -struct phytx_ppdu_header_info_request { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t request_type : 5, - reserved : 11; - uint16_t tlv32_padding : 16; -#else - uint16_t reserved : 11, - request_type : 5; - uint16_t tlv32_padding : 16; -#endif -}; - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/receive_pkt_start_info.h b/drivers/staging/fw-api/hw/fig/v1/receive_pkt_start_info.h deleted file mode 100644 index 7f7c81449a15..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/receive_pkt_start_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_PKT_START_INFO_H_ -#define _RECEIVE_PKT_START_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4 - -struct receive_pkt_start_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reception_type : 4, - rx_chain_mask_type : 1, - receive_bandwidth : 3, - rx_chain_mask : 8, - phy_ppdu_id : 16; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t preamble_time_to_rxframe : 8, - standalone_sniffer_mode : 1, - reserved_3a : 23; -#else - uint32_t phy_ppdu_id : 16, - rx_chain_mask : 8, - receive_bandwidth : 3, - rx_chain_mask_type : 1, - reception_type : 4; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t reserved_3a : 23, - standalone_sniffer_mode : 1, - preamble_time_to_rxframe : 8; -#endif -}; - -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB 0 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB 3 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK 0x0000000f - -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB 4 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB 4 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK 0x00000010 - -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB 5 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB 7 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK 0x000000e0 - -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB 8 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB 15 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK 0x0000ff00 - -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB 16 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB 31 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK 0xffff0000 - -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff - -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff - -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB 0 -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB 7 -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff - -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB 8 -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB 8 -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK 0x00000100 - -#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB 9 -#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB 31 -#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK 0xfffffe00 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/receive_rssi_info.h b/drivers/staging/fw-api/hw/fig/v1/receive_rssi_info.h deleted file mode 100644 index 9aaa98217d99..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/receive_rssi_info.h +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_RSSI_INFO_H_ -#define _RECEIVE_RSSI_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 - -struct receive_rssi_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rssi_pri20_chain0 : 8, - rssi_ext20_chain0 : 8, - rssi_ext40_low20_chain0 : 8, - rssi_ext40_high20_chain0 : 8; - uint32_t rssi_ext80_low20_chain0 : 8, - rssi_ext80_low_high20_chain0 : 8, - rssi_ext80_high_low20_chain0 : 8, - rssi_ext80_high20_chain0 : 8; - uint32_t rssi_ext160_0_chain0 : 8, - rssi_ext160_1_chain0 : 8, - rssi_ext160_2_chain0 : 8, - rssi_ext160_3_chain0 : 8; - uint32_t rssi_ext160_4_chain0 : 8, - rssi_ext160_5_chain0 : 8, - rssi_ext160_6_chain0 : 8, - rssi_ext160_7_chain0 : 8; - uint32_t rssi_pri20_chain1 : 8, - rssi_ext20_chain1 : 8, - rssi_ext40_low20_chain1 : 8, - rssi_ext40_high20_chain1 : 8; - uint32_t rssi_ext80_low20_chain1 : 8, - rssi_ext80_low_high20_chain1 : 8, - rssi_ext80_high_low20_chain1 : 8, - rssi_ext80_high20_chain1 : 8; - uint32_t rssi_ext160_0_chain1 : 8, - rssi_ext160_1_chain1 : 8, - rssi_ext160_2_chain1 : 8, - rssi_ext160_3_chain1 : 8; - uint32_t rssi_ext160_4_chain1 : 8, - rssi_ext160_5_chain1 : 8, - rssi_ext160_6_chain1 : 8, - rssi_ext160_7_chain1 : 8; - uint32_t rssi_pri20_chain2 : 8, - rssi_ext20_chain2 : 8, - rssi_ext40_low20_chain2 : 8, - rssi_ext40_high20_chain2 : 8; - uint32_t rssi_ext80_low20_chain2 : 8, - rssi_ext80_low_high20_chain2 : 8, - rssi_ext80_high_low20_chain2 : 8, - rssi_ext80_high20_chain2 : 8; - uint32_t rssi_ext160_0_chain2 : 8, - rssi_ext160_1_chain2 : 8, - rssi_ext160_2_chain2 : 8, - rssi_ext160_3_chain2 : 8; - uint32_t rssi_ext160_4_chain2 : 8, - rssi_ext160_5_chain2 : 8, - rssi_ext160_6_chain2 : 8, - rssi_ext160_7_chain2 : 8; - uint32_t rssi_pri20_chain3 : 8, - rssi_ext20_chain3 : 8, - rssi_ext40_low20_chain3 : 8, - rssi_ext40_high20_chain3 : 8; - uint32_t rssi_ext80_low20_chain3 : 8, - rssi_ext80_low_high20_chain3 : 8, - rssi_ext80_high_low20_chain3 : 8, - rssi_ext80_high20_chain3 : 8; - uint32_t rssi_ext160_0_chain3 : 8, - rssi_ext160_1_chain3 : 8, - rssi_ext160_2_chain3 : 8, - rssi_ext160_3_chain3 : 8; - uint32_t rssi_ext160_4_chain3 : 8, - rssi_ext160_5_chain3 : 8, - rssi_ext160_6_chain3 : 8, - rssi_ext160_7_chain3 : 8; -#else - uint32_t rssi_ext40_high20_chain0 : 8, - rssi_ext40_low20_chain0 : 8, - rssi_ext20_chain0 : 8, - rssi_pri20_chain0 : 8; - uint32_t rssi_ext80_high20_chain0 : 8, - rssi_ext80_high_low20_chain0 : 8, - rssi_ext80_low_high20_chain0 : 8, - rssi_ext80_low20_chain0 : 8; - uint32_t rssi_ext160_3_chain0 : 8, - rssi_ext160_2_chain0 : 8, - rssi_ext160_1_chain0 : 8, - rssi_ext160_0_chain0 : 8; - uint32_t rssi_ext160_7_chain0 : 8, - rssi_ext160_6_chain0 : 8, - rssi_ext160_5_chain0 : 8, - rssi_ext160_4_chain0 : 8; - uint32_t rssi_ext40_high20_chain1 : 8, - rssi_ext40_low20_chain1 : 8, - rssi_ext20_chain1 : 8, - rssi_pri20_chain1 : 8; - uint32_t rssi_ext80_high20_chain1 : 8, - rssi_ext80_high_low20_chain1 : 8, - rssi_ext80_low_high20_chain1 : 8, - rssi_ext80_low20_chain1 : 8; - uint32_t rssi_ext160_3_chain1 : 8, - rssi_ext160_2_chain1 : 8, - rssi_ext160_1_chain1 : 8, - rssi_ext160_0_chain1 : 8; - uint32_t rssi_ext160_7_chain1 : 8, - rssi_ext160_6_chain1 : 8, - rssi_ext160_5_chain1 : 8, - rssi_ext160_4_chain1 : 8; - uint32_t rssi_ext40_high20_chain2 : 8, - rssi_ext40_low20_chain2 : 8, - rssi_ext20_chain2 : 8, - rssi_pri20_chain2 : 8; - uint32_t rssi_ext80_high20_chain2 : 8, - rssi_ext80_high_low20_chain2 : 8, - rssi_ext80_low_high20_chain2 : 8, - rssi_ext80_low20_chain2 : 8; - uint32_t rssi_ext160_3_chain2 : 8, - rssi_ext160_2_chain2 : 8, - rssi_ext160_1_chain2 : 8, - rssi_ext160_0_chain2 : 8; - uint32_t rssi_ext160_7_chain2 : 8, - rssi_ext160_6_chain2 : 8, - rssi_ext160_5_chain2 : 8, - rssi_ext160_4_chain2 : 8; - uint32_t rssi_ext40_high20_chain3 : 8, - rssi_ext40_low20_chain3 : 8, - rssi_ext20_chain3 : 8, - rssi_pri20_chain3 : 8; - uint32_t rssi_ext80_high20_chain3 : 8, - rssi_ext80_high_low20_chain3 : 8, - rssi_ext80_low_high20_chain3 : 8, - rssi_ext80_low20_chain3 : 8; - uint32_t rssi_ext160_3_chain3 : 8, - rssi_ext160_2_chain3 : 8, - rssi_ext160_1_chain3 : 8, - rssi_ext160_0_chain3 : 8; - uint32_t rssi_ext160_7_chain3 : 8, - rssi_ext160_6_chain3 : 8, - rssi_ext160_5_chain3 : 8, - rssi_ext160_4_chain3 : 8; -#endif -}; - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/receive_user_info.h b/drivers/staging/fw-api/hw/fig/v1/receive_user_info.h deleted file mode 100644 index 23daabab5dc8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/receive_user_info.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_USER_INFO_H_ -#define _RECEIVE_USER_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8 - -struct receive_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - user_rssi : 8, - pkt_type : 4, - stbc : 1, - reception_type : 3; - uint32_t rate_mcs : 5, - sgi : 2, - __reserved_g_0004 : 1, - mimo_ss_bitmap : 8, - receive_bandwidth : 3, - reserved_1b : 5, - dl_ofdma_user_index : 8; - uint32_t dl_ofdma_content_channel : 1, - reserved_2a : 1, - qam_diff1 : 2, - qam_diff2 : 2, - qam_diff3 : 2, - nss : 3, - stream_offset : 3, - sta_dcm : 1, - ldpc : 1, - ru_type_80_0 : 4, - ru_type_80_1 : 4, - ru_type_80_2 : 4, - ru_type_80_3 : 4; - uint32_t ru_start_index_80_0 : 6, - reserved_3a : 2, - ru_start_index_80_1 : 6, - reserved_3b : 2, - ru_start_index_80_2 : 6, - reserved_3c : 2, - ru_start_index_80_3 : 6, - reserved_3d : 2; - uint32_t user_fd_rssi_seg0 : 32; - uint32_t user_fd_rssi_seg1 : 32; - uint32_t user_fd_rssi_seg2 : 32; - uint32_t user_fd_rssi_seg3 : 32; -#else - uint32_t reception_type : 3, - stbc : 1, - pkt_type : 4, - user_rssi : 8, - phy_ppdu_id : 16; - uint32_t dl_ofdma_user_index : 8, - reserved_1b : 5, - receive_bandwidth : 3, - mimo_ss_bitmap : 8, - __reserved_g_0004 : 1, - sgi : 2, - rate_mcs : 5; - uint32_t ru_type_80_3 : 4, - ru_type_80_2 : 4, - ru_type_80_1 : 4, - ru_type_80_0 : 4, - ldpc : 1, - sta_dcm : 1, - stream_offset : 3, - nss : 3, - qam_diff3 : 2, - qam_diff2 : 2, - qam_diff1 : 2, - reserved_2a : 1, - dl_ofdma_content_channel : 1; - uint32_t reserved_3d : 2, - ru_start_index_80_3 : 6, - reserved_3c : 2, - ru_start_index_80_2 : 6, - reserved_3b : 2, - ru_start_index_80_1 : 6, - reserved_3a : 2, - ru_start_index_80_0 : 6; - uint32_t user_fd_rssi_seg0 : 32; - uint32_t user_fd_rssi_seg1 : 32; - uint32_t user_fd_rssi_seg2 : 32; - uint32_t user_fd_rssi_seg3 : 32; -#endif -}; - -#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff - -#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_USER_RSSI_LSB 16 -#define RECEIVE_USER_INFO_USER_RSSI_MSB 23 -#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 - -#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 -#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 -#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 - -#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_STBC_LSB 28 -#define RECEIVE_USER_INFO_STBC_MSB 28 -#define RECEIVE_USER_INFO_STBC_MASK 0x10000000 - -#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 - -#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RATE_MCS_LSB 0 -#define RECEIVE_USER_INFO_RATE_MCS_MSB 4 -#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000001f - -#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_SGI_LSB 5 -#define RECEIVE_USER_INFO_SGI_MSB 6 -#define RECEIVE_USER_INFO_SGI_MASK 0x00000060 - -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 - -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 - -#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 -#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 -#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 - -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 - -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 - -#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 -#define RECEIVE_USER_INFO_RESERVED_2A_MSB 1 -#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x00000002 - -#define RECEIVE_USER_INFO_QAM_DIFF1_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF1_LSB 2 -#define RECEIVE_USER_INFO_QAM_DIFF1_MSB 3 -#define RECEIVE_USER_INFO_QAM_DIFF1_MASK 0x0000000c - -#define RECEIVE_USER_INFO_QAM_DIFF2_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF2_LSB 4 -#define RECEIVE_USER_INFO_QAM_DIFF2_MSB 5 -#define RECEIVE_USER_INFO_QAM_DIFF2_MASK 0x00000030 - -#define RECEIVE_USER_INFO_QAM_DIFF3_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF3_LSB 6 -#define RECEIVE_USER_INFO_QAM_DIFF3_MSB 7 -#define RECEIVE_USER_INFO_QAM_DIFF3_MASK 0x000000c0 - -#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_NSS_LSB 8 -#define RECEIVE_USER_INFO_NSS_MSB 10 -#define RECEIVE_USER_INFO_NSS_MASK 0x00000700 - -#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 -#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 -#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 - -#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_STA_DCM_LSB 14 -#define RECEIVE_USER_INFO_STA_DCM_MSB 14 -#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 - -#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_LDPC_LSB 15 -#define RECEIVE_USER_INFO_LDPC_MSB 15 -#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f - -#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 -#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 -#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 - -#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 -#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 -#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 - -#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 -#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 -#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 - -#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30 -#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 -#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000 - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_response_user_15_8.h b/drivers/staging/fw-api/hw/fig/v1/received_response_user_15_8.h deleted file mode 100644 index 6cf8117ff02f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_response_user_15_8.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ -#define _RECEIVED_RESPONSE_USER_15_8_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32 - -struct received_response_user_15_8 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user8; - struct received_response_user_info received_response_details_user9; - struct received_response_user_info received_response_details_user10; - struct received_response_user_info received_response_details_user11; - struct received_response_user_info received_response_details_user12; - struct received_response_user_info received_response_details_user13; - struct received_response_user_info received_response_details_user14; - struct received_response_user_info received_response_details_user15; -#else - struct received_response_user_info received_response_details_user8; - struct received_response_user_info received_response_details_user9; - struct received_response_user_info received_response_details_user10; - struct received_response_user_info received_response_details_user11; - struct received_response_user_info received_response_details_user12; - struct received_response_user_info received_response_details_user13; - struct received_response_user_info received_response_details_user14; - struct received_response_user_info received_response_details_user15; -#endif -}; - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_response_user_23_16.h b/drivers/staging/fw-api/hw/fig/v1/received_response_user_23_16.h deleted file mode 100644 index ff56f4d96472..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_response_user_23_16.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ -#define _RECEIVED_RESPONSE_USER_23_16_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32 - -struct received_response_user_23_16 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user16; - struct received_response_user_info received_response_details_user17; - struct received_response_user_info received_response_details_user18; - struct received_response_user_info received_response_details_user19; - struct received_response_user_info received_response_details_user20; - struct received_response_user_info received_response_details_user21; - struct received_response_user_info received_response_details_user22; - struct received_response_user_info received_response_details_user23; -#else - struct received_response_user_info received_response_details_user16; - struct received_response_user_info received_response_details_user17; - struct received_response_user_info received_response_details_user18; - struct received_response_user_info received_response_details_user19; - struct received_response_user_info received_response_details_user20; - struct received_response_user_info received_response_details_user21; - struct received_response_user_info received_response_details_user22; - struct received_response_user_info received_response_details_user23; -#endif -}; - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_response_user_31_24.h b/drivers/staging/fw-api/hw/fig/v1/received_response_user_31_24.h deleted file mode 100644 index aaa90838daa9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_response_user_31_24.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ -#define _RECEIVED_RESPONSE_USER_31_24_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32 - -struct received_response_user_31_24 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user24; - struct received_response_user_info received_response_details_user25; - struct received_response_user_info received_response_details_user26; - struct received_response_user_info received_response_details_user27; - struct received_response_user_info received_response_details_user28; - struct received_response_user_info received_response_details_user29; - struct received_response_user_info received_response_details_user30; - struct received_response_user_info received_response_details_user31; -#else - struct received_response_user_info received_response_details_user24; - struct received_response_user_info received_response_details_user25; - struct received_response_user_info received_response_details_user26; - struct received_response_user_info received_response_details_user27; - struct received_response_user_info received_response_details_user28; - struct received_response_user_info received_response_details_user29; - struct received_response_user_info received_response_details_user30; - struct received_response_user_info received_response_details_user31; -#endif -}; - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_response_user_36_32.h b/drivers/staging/fw-api/hw/fig/v1/received_response_user_36_32.h deleted file mode 100644 index 3f33fdab635e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_response_user_36_32.h +++ /dev/null @@ -1,705 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ -#define _RECEIVED_RESPONSE_USER_36_32_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20 - -struct received_response_user_36_32 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user32; - struct received_response_user_info received_response_details_user33; - struct received_response_user_info received_response_details_user34; - struct received_response_user_info received_response_details_user35; - struct received_response_user_info received_response_details_user36; -#else - struct received_response_user_info received_response_details_user32; - struct received_response_user_info received_response_details_user33; - struct received_response_user_info received_response_details_user34; - struct received_response_user_info received_response_details_user35; - struct received_response_user_info received_response_details_user36; -#endif -}; - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_response_user_7_0.h b/drivers/staging/fw-api/hw/fig/v1/received_response_user_7_0.h deleted file mode 100644 index f785aca46840..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_response_user_7_0.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ -#define _RECEIVED_RESPONSE_USER_7_0_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32 - -struct received_response_user_7_0 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user0; - struct received_response_user_info received_response_details_user1; - struct received_response_user_info received_response_details_user2; - struct received_response_user_info received_response_details_user3; - struct received_response_user_info received_response_details_user4; - struct received_response_user_info received_response_details_user5; - struct received_response_user_info received_response_details_user6; - struct received_response_user_info received_response_details_user7; -#else - struct received_response_user_info received_response_details_user0; - struct received_response_user_info received_response_details_user1; - struct received_response_user_info received_response_details_user2; - struct received_response_user_info received_response_details_user3; - struct received_response_user_info received_response_details_user4; - struct received_response_user_info received_response_details_user5; - struct received_response_user_info received_response_details_user6; - struct received_response_user_info received_response_details_user7; -#endif -}; - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_response_user_info.h b/drivers/staging/fw-api/hw/fig/v1/received_response_user_info.h deleted file mode 100644 index 3c3faf119635..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_response_user_info.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ -#define _RECEIVED_RESPONSE_USER_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 - -struct received_response_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mpdu_fcs_pass_count : 12, - mpdu_fcs_fail_count : 12, - qosnull_frame_count : 4, - reserved_0a : 3, - user_info_valid : 1; - uint32_t null_delimiter_count : 22, - reserved_1a : 9, - ht_control_valid : 1; - uint32_t ht_control : 32; - uint32_t qos_control_valid : 16, - eosp : 16; - uint32_t qos_control_15_8_tid_0 : 8, - qos_control_15_8_tid_1 : 8, - qos_control_15_8_tid_2 : 8, - qos_control_15_8_tid_3 : 8; - uint32_t qos_control_15_8_tid_4 : 8, - qos_control_15_8_tid_5 : 8, - qos_control_15_8_tid_6 : 8, - qos_control_15_8_tid_7 : 8; - uint32_t qos_control_15_8_tid_8 : 8, - qos_control_15_8_tid_9 : 8, - qos_control_15_8_tid_10 : 8, - qos_control_15_8_tid_11 : 8; - uint32_t qos_control_15_8_tid_12 : 8, - qos_control_15_8_tid_13 : 8, - qos_control_15_8_tid_14 : 8, - qos_control_15_8_tid_15 : 8; -#else - uint32_t user_info_valid : 1, - reserved_0a : 3, - qosnull_frame_count : 4, - mpdu_fcs_fail_count : 12, - mpdu_fcs_pass_count : 12; - uint32_t ht_control_valid : 1, - reserved_1a : 9, - null_delimiter_count : 22; - uint32_t ht_control : 32; - uint32_t eosp : 16, - qos_control_valid : 16; - uint32_t qos_control_15_8_tid_3 : 8, - qos_control_15_8_tid_2 : 8, - qos_control_15_8_tid_1 : 8, - qos_control_15_8_tid_0 : 8; - uint32_t qos_control_15_8_tid_7 : 8, - qos_control_15_8_tid_6 : 8, - qos_control_15_8_tid_5 : 8, - qos_control_15_8_tid_4 : 8; - uint32_t qos_control_15_8_tid_11 : 8, - qos_control_15_8_tid_10 : 8, - qos_control_15_8_tid_9 : 8, - qos_control_15_8_tid_8 : 8; - uint32_t qos_control_15_8_tid_15 : 8, - qos_control_15_8_tid_14 : 8, - qos_control_15_8_tid_13 : 8, - qos_control_15_8_tid_12 : 8; -#endif -}; - -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff - -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 - -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 - -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 - -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 - -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff - -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 - -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 - -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff - -#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c -#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_trigger_info.h b/drivers/staging/fw-api/hw/fig/v1/received_trigger_info.h deleted file mode 100644 index 16d10249d075..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_trigger_info.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_TRIGGER_INFO_H_ -#define _RECEIVED_TRIGGER_INFO_H_ - -#include "received_trigger_info_details.h" -#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6 - -#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3 - -struct received_trigger_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_trigger_info_details received_trigger_details; -#else - struct received_trigger_info_details received_trigger_details; -#endif -}; - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB 29 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB 30 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK 0x0000000060000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x0000000080000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_LSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MASK 0x2000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x4000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0x8000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 48 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 56 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xe000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x0000000100000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 33 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 36 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 37 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 39 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_LSB 40 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MASK 0xffffff0000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_trigger_info_details.h b/drivers/staging/fw-api/hw/fig/v1/received_trigger_info_details.h deleted file mode 100644 index ebffe439b3b2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_trigger_info_details.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ -#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ - -#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 6 - -struct received_trigger_info_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t trigger_type : 4, - ax_trigger_source : 1, - ax_trigger_type : 4, - trigger_source_sta_full_aid : 13, - frame_control_valid : 1, - qos_control_valid : 1, - he_control_info_valid : 1, - __reserved_g_0022_trigger_subtype : 4, - txop_sharing_mode : 2, - tid_aggregation_limit_is_zero : 1; - uint32_t phy_ppdu_id : 16, - lsig_response_length : 12, - __reserved_g_0035 : 1, - scsid_valid : 1, - ects_as_tb_ppdu : 1, - reserved_1a : 1; - uint32_t frame_control : 16, - qos_control : 16; - uint32_t sw_peer_id : 16, - txop_sharing_allocation_duration : 9, - __reserved_g_0035_trigger_subtype : 4, - reserved_3a : 3; - uint32_t he_control : 32; - uint32_t txop_sharing_duration_from_durid : 1, - frame_durationid_lower_4 : 4, - frame_durationid_upper_3 : 3, - reserved_5a : 24; -#else - uint32_t tid_aggregation_limit_is_zero : 1, - txop_sharing_mode : 2, - __reserved_g_0022_trigger_subtype : 4, - he_control_info_valid : 1, - qos_control_valid : 1, - frame_control_valid : 1, - trigger_source_sta_full_aid : 13, - ax_trigger_type : 4, - ax_trigger_source : 1, - trigger_type : 4; - uint32_t reserved_1a : 1, - ects_as_tb_ppdu : 1, - scsid_valid : 1, - __reserved_g_0035 : 1, - lsig_response_length : 12, - phy_ppdu_id : 16; - uint32_t qos_control : 16, - frame_control : 16; - uint32_t reserved_3a : 3, - __reserved_g_0035_trigger_subtype : 4, - txop_sharing_allocation_duration : 9, - sw_peer_id : 16; - uint32_t he_control : 32; - uint32_t reserved_5a : 24, - frame_durationid_upper_3 : 3, - frame_durationid_lower_4 : 4, - txop_sharing_duration_from_durid : 1; -#endif -}; - -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f - -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 - -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MASK 0x20000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_LSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MASK 0x40000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0x80000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xe0000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x00000001 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 1 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 5 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 7 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e0 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_LSB 8 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MASK 0xffffff00 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/reo_destination_ring.h b/drivers/staging/fw-api/hw/fig/v1/reo_destination_ring.h deleted file mode 100644 index 5147635121c1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/reo_destination_ring.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_DESTINATION_RING_H_ -#define _REO_DESTINATION_RING_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_mpdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_REO_DESTINATION_RING 8 - -struct reo_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t release_source_module : 3, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_delink_error : 1, - sw_buffer_cookie : 20; - uint32_t msdu_link_desc_index : 4, - reserved_6a : 28; - uint32_t reo_dest_buffer_type : 1, - reo_push_reason : 2, - reo_error_code : 5, - captured_msdu_data_size : 4, - sw_exception : 1, - src_link_id : 3, - reo_destination_struct_signature : 4, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t sw_buffer_cookie : 20, - reo_delink_error : 1, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - release_source_module : 3; - uint32_t reserved_6a : 28, - msdu_link_desc_index : 4; - uint32_t looping_count : 4, - ring_id : 8, - reo_destination_struct_signature : 4, - src_link_id : 3, - sw_exception : 1, - captured_msdu_data_size : 4, - reo_error_code : 5, - reo_push_reason : 2, - reo_dest_buffer_type : 1; -#endif -}; - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_LSB 3 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MSB 3 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MASK 0x00000008 - -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_LSB 4 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MSB 5 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MASK 0x00000030 - -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_LSB 6 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MSB 10 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MASK 0x000007c0 - -#define REO_DESTINATION_RING_REO_DELINK_ERROR_OFFSET 0x00000014 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_LSB 11 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_MSB 11 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_MASK 0x00000800 - -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_LSB 0 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MSB 3 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MASK 0x0000000f - -#define REO_DESTINATION_RING_RESERVED_6A_OFFSET 0x00000018 -#define REO_DESTINATION_RING_RESERVED_6A_LSB 4 -#define REO_DESTINATION_RING_RESERVED_6A_MSB 31 -#define REO_DESTINATION_RING_RESERVED_6A_MASK 0xfffffff0 - -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 - -#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 -#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 -#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 - -#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 -#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 -#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 - -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 - -#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c -#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 -#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 -#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 - -#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 -#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 -#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 - -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 - -#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_RING_ID_LSB 20 -#define REO_DESTINATION_RING_RING_ID_MSB 27 -#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 - -#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 -#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 -#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/reo_destination_ring_with_pn.h b/drivers/staging/fw-api/hw/fig/v1/reo_destination_ring_with_pn.h deleted file mode 100644 index b486a8658388..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/reo_destination_ring_with_pn.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_DESTINATION_RING_WITH_PN_H_ -#define _REO_DESTINATION_RING_WITH_PN_H_ - -#include "rx_msdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8 - -struct reo_destination_ring_with_pn { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - uint32_t msdu_count : 8, - prev_pn_23_0 : 24; - uint32_t prev_pn_47_24 : 24, - prev_pn_127_48_info : 2, - reserved_3a : 6; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t release_source_module : 3, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_delink_error : 1, - sw_buffer_cookie : 20; - uint32_t msdu_link_desc_index : 4, - reserved_6a : 28; - uint32_t reo_dest_buffer_type : 1, - reo_push_reason : 2, - reo_error_code : 5, - captured_msdu_data_size : 4, - sw_exception : 1, - src_link_id : 3, - reo_destination_struct_signature : 4, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - uint32_t prev_pn_23_0 : 24, - msdu_count : 8; - uint32_t reserved_3a : 6, - prev_pn_127_48_info : 2, - prev_pn_47_24 : 24; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t sw_buffer_cookie : 20, - reo_delink_error : 1, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - release_source_module : 3; - uint32_t reserved_6a : 28, - msdu_link_desc_index : 4; - uint32_t looping_count : 4, - ring_id : 8, - reo_destination_struct_signature : 4, - src_link_id : 3, - sw_exception : 1, - captured_msdu_data_size : 4, - reo_error_code : 5, - reo_push_reason : 2, - reo_dest_buffer_type : 1; -#endif -}; - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00 - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MSB 23 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MASK 0x00ffffff - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_LSB 24 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MSB 25 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MASK 0x03000000 - -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_LSB 26 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MASK 0xfc000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MSB 3 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MASK 0x00000008 - -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_LSB 4 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MSB 5 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MASK 0x00000030 - -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_LSB 6 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MSB 10 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MASK 0x000007c0 - -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_LSB 11 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MASK 0x00000800 - -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MSB 3 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MASK 0x0000000f - -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_OFFSET 0x00000018 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_LSB 4 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MASK 0xfffffff0 - -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0 -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001 - -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1 -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006 - -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8 - -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 - -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000 - -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13 -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15 -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000 - -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 - -#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20 -#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27 -#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000 - -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28 -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/reo_entrance_ring.h b/drivers/staging/fw-api/hw/fig/v1/reo_entrance_ring.h deleted file mode 100644 index 800244f712be..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/reo_entrance_ring.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_ENTRANCE_RING_H_ -#define _REO_ENTRANCE_RING_H_ - -#include "rx_mpdu_details.h" -#define NUM_OF_DWORDS_REO_ENTRANCE_RING 16 - -struct reo_entrance_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_mpdu_details reo_level_mpdu_frame_info; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t rx_reo_queue_desc_addr_39_32 : 8, - rounded_mpdu_byte_count : 14, - reo_destination_indication : 5, - frameless_bar : 1, - reserved_7a : 4; - uint32_t rxdma_push_reason : 2, - rxdma_error_code : 5, - mpdu_fragment_number : 4, - sw_exception : 1, - sw_exception_mpdu_delink : 1, - sw_exception_destination_ring_valid : 1, - sw_exception_destination_ring : 5, - mpdu_sequence_number : 12, - no_ack : 1; - uint32_t phy_ppdu_id : 16, - src_link_id : 3, - reserved_9a : 13; - uint32_t receive_queue_number : 16, - fw_reorder_push_reason : 2, - fw_reorder_error_code : 5, - reserved_10a : 9; - uint32_t reserved_11a : 32; - uint32_t reserved_12a : 32; - uint32_t reserved_13a : 32; - uint32_t reserved_14a : 32; - uint32_t reserved_15a : 20, - ring_id : 8, - looping_count : 4; -#else - struct rx_mpdu_details reo_level_mpdu_frame_info; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t reserved_7a : 4, - frameless_bar : 1, - reo_destination_indication : 5, - rounded_mpdu_byte_count : 14, - rx_reo_queue_desc_addr_39_32 : 8; - uint32_t no_ack : 1, - mpdu_sequence_number : 12, - sw_exception_destination_ring : 5, - sw_exception_destination_ring_valid : 1, - sw_exception_mpdu_delink : 1, - sw_exception : 1, - mpdu_fragment_number : 4, - rxdma_error_code : 5, - rxdma_push_reason : 2; - uint32_t reserved_9a : 13, - src_link_id : 3, - phy_ppdu_id : 16; - uint32_t reserved_10a : 9, - fw_reorder_error_code : 5, - fw_reorder_push_reason : 2, - receive_queue_number : 16; - uint32_t reserved_11a : 32; - uint32_t reserved_12a : 32; - uint32_t reserved_13a : 32; - uint32_t reserved_14a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_15a : 20; -#endif -}; - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000 - -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff - -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 - -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 - -#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 -#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 -#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 - -#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_RESERVED_7A_LSB 28 -#define REO_ENTRANCE_RING_RESERVED_7A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0xf0000000 - -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 - -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c - -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 - -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 - -#define REO_ENTRANCE_RING_NO_ACK_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_NO_ACK_LSB 31 -#define REO_ENTRANCE_RING_NO_ACK_MSB 31 -#define REO_ENTRANCE_RING_NO_ACK_MASK 0x80000000 - -#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 -#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 -#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 - -#define REO_ENTRANCE_RING_RESERVED_9A_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_RESERVED_9A_LSB 19 -#define REO_ENTRANCE_RING_RESERVED_9A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_9A_MASK 0xfff80000 - -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_LSB 0 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MSB 15 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_LSB 16 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MSB 17 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MASK 0x00030000 - -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_LSB 18 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MSB 22 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MASK 0x007c0000 - -#define REO_ENTRANCE_RING_RESERVED_10A_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_RESERVED_10A_LSB 23 -#define REO_ENTRANCE_RING_RESERVED_10A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_10A_MASK 0xff800000 - -#define REO_ENTRANCE_RING_RESERVED_11A_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_RESERVED_11A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_11A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_11A_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RESERVED_12A_OFFSET 0x00000030 -#define REO_ENTRANCE_RING_RESERVED_12A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_12A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_12A_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RESERVED_13A_OFFSET 0x00000034 -#define REO_ENTRANCE_RING_RESERVED_13A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_13A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_13A_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RESERVED_14A_OFFSET 0x00000038 -#define REO_ENTRANCE_RING_RESERVED_14A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_14A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_14A_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RESERVED_15A_OFFSET 0x0000003c -#define REO_ENTRANCE_RING_RESERVED_15A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_15A_MSB 19 -#define REO_ENTRANCE_RING_RESERVED_15A_MASK 0x000fffff - -#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000003c -#define REO_ENTRANCE_RING_RING_ID_LSB 20 -#define REO_ENTRANCE_RING_RING_ID_MSB 27 -#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 - -#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000003c -#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 -#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 -#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/response_end_status.h b/drivers/staging/fw-api/hw/fig/v1/response_end_status.h deleted file mode 100644 index 30c6c65e043a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/response_end_status.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RESPONSE_END_STATUS_H_ -#define _RESPONSE_END_STATUS_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10 - -#define NUM_OF_QWORDS_RESPONSE_END_STATUS 5 - -struct response_end_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0046 : 1, - __reserved_g_0043 : 1, - __reserved_g_0041 : 1, - global_data_underflow_warning : 1, - response_transmit_status : 4, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - generated_response : 3, - mba_user_count : 7, - mba_fake_bitmap_count : 7, - coex_based_tx_bw : 3, - trig_response_related : 1, - __reserved_g_0035 : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t cbf_segment_request_mask : 8, - cbf_segment_sent_mask : 8; - uint32_t underflow_mpdu_count : 9, - data_underflow_warning : 2, - reserved_2b : 10, - only_null_delim_sent : 1, - brp_info_valid : 1, - __reserved_g_0068 : 1, - __reserved_g_0056 : 1, - __reserved_g_0039 : 1, - __reserved_g_0040 : 1, - __reserved_g_0063 : 1, - __reserved_g_0061 : 1, - __reserved_g_0059 : 1, - __reserved_g_0057 : 1, - __reserved_g_0042 : 1; - uint32_t mu_response_bitmap_31_0 : 32; - uint32_t mu_response_bitmap_36_32 : 5, - reserved_4a : 27; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t addr3_47_32 : 16, - __reserved_g_0022 : 1, - secure : 1, - __reserved_g_0022_ftm_frame_sent : 1, - reserved_20a : 13; -#else - uint32_t __reserved_g_0035 : 1, - trig_response_related : 1, - coex_based_tx_bw : 3, - mba_fake_bitmap_count : 7, - mba_user_count : 7, - generated_response : 3, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - response_transmit_status : 4, - global_data_underflow_warning : 1, - __reserved_g_0041 : 1, - __reserved_g_0043 : 1, - __reserved_g_0046 : 1; - uint32_t cbf_segment_sent_mask : 8, - cbf_segment_request_mask : 8; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t __reserved_g_0042 : 1, - __reserved_g_0057 : 1, - __reserved_g_0059 : 1, - __reserved_g_0061 : 1, - __reserved_g_0063 : 1, - __reserved_g_0040 : 1, - __reserved_g_0039 : 1, - __reserved_g_0056 : 1, - __reserved_g_0068 : 1, - brp_info_valid : 1, - only_null_delim_sent : 1, - reserved_2b : 10, - data_underflow_warning : 2, - underflow_mpdu_count : 9; - uint32_t mu_response_bitmap_31_0 : 32; - uint32_t reserved_4a : 27, - mu_response_bitmap_36_32 : 5; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t reserved_20a : 13, - __reserved_g_0022_ftm_frame_sent : 1, - secure : 1, - __reserved_g_0022 : 1, - addr3_47_32 : 16; -#endif -}; - -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 - -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 - -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 - -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 - -#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 - -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 - -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 - -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 - -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 - -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff - -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 - -#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_RESERVED_2B_LSB 11 -#define RESPONSE_END_STATUS_RESERVED_2B_MSB 20 -#define RESPONSE_END_STATUS_RESERVED_2B_MASK 0x00000000001ff800 - -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 - -#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 - -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f - -#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 -#define RESPONSE_END_STATUS_RESERVED_4A_MSB 31 -#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x00000000ffffffe0 - -#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 32 -#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 63 -#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 0 -#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 15 -#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x000000000000ffff - -#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 16 -#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 31 -#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0x00000000ffff0000 - -#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 32 -#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 63 -#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 0 -#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 31 -#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0x00000000ffffffff - -#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 32 -#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 47 -#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x0000ffff00000000 - -#define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_SECURE_LSB 49 -#define RESPONSE_END_STATUS_SECURE_MSB 49 -#define RESPONSE_END_STATUS_SECURE_MASK 0x0002000000000000 - -#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_RESERVED_20A_LSB 51 -#define RESPONSE_END_STATUS_RESERVED_20A_MSB 63 -#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0xfff8000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/response_start_status.h b/drivers/staging/fw-api/hw/fig/v1/response_start_status.h deleted file mode 100644 index b8b96e8d9f3d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/response_start_status.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RESPONSE_START_STATUS_H_ -#define _RESPONSE_START_STATUS_H_ - -#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 - -#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 - -struct response_start_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t generated_response : 3, - __reserved_g_0012 : 2, - trig_response_related : 1, - response_sta_count : 7, - reserved : 19; - uint32_t phy_ppdu_id : 16, - sw_peer_id : 16; -#else - uint32_t reserved : 19, - response_sta_count : 7, - trig_response_related : 1, - __reserved_g_0012 : 2, - generated_response : 3; - uint32_t sw_peer_id : 16, - phy_ppdu_id : 16; -#endif -}; - -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 - -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 - -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 - -#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_RESERVED_LSB 13 -#define RESPONSE_START_STATUS_RESERVED_MSB 31 -#define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffffe000 - -#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 - -#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 -#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 -#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/ru_allocation_160_info.h b/drivers/staging/fw-api/hw/fig/v1/ru_allocation_160_info.h deleted file mode 100644 index 57d51dc44f8a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/ru_allocation_160_info.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RU_ALLOCATION_160_INFO_H_ -#define _RU_ALLOCATION_160_INFO_H_ - -#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 - -struct ru_allocation_160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_allocation_band0_0 : 9, - ru_allocation_band0_1 : 9, - reserved_0a : 6, - ru_allocations_01_subband80_mask : 4, - ru_allocations_23_subband80_mask : 4; - uint32_t ru_allocation_band0_2 : 9, - ru_allocation_band0_3 : 9, - reserved_1a : 14; - uint32_t ru_allocation_band1_0 : 9, - ru_allocation_band1_1 : 9, - reserved_2a : 14; - uint32_t ru_allocation_band1_2 : 9, - ru_allocation_band1_3 : 9, - reserved_3a : 14; -#else - uint32_t ru_allocations_23_subband80_mask : 4, - ru_allocations_01_subband80_mask : 4, - reserved_0a : 6, - ru_allocation_band0_1 : 9, - ru_allocation_band0_0 : 9; - uint32_t reserved_1a : 14, - ru_allocation_band0_3 : 9, - ru_allocation_band0_2 : 9; - uint32_t reserved_2a : 14, - ru_allocation_band1_1 : 9, - ru_allocation_band1_0 : 9; - uint32_t reserved_3a : 14, - ru_allocation_band1_3 : 9, - ru_allocation_band1_2 : 9; -#endif -}; - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_attention.h b/drivers/staging/fw-api/hw/fig/v1/rx_attention.h deleted file mode 100644 index cac7c2fb52c3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_attention.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_ATTENTION_H_ -#define _RX_ATTENTION_H_ - -#define NUM_OF_DWORDS_RX_ATTENTION 4 - -#define NUM_OF_QWORDS_RX_ATTENTION 2 - -struct rx_attention { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t first_mpdu : 1, - reserved_1a : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - a_msdu_error : 1, - fragment_flag : 1, - order : 1, - cce_match : 1, - overflow_err : 1, - msdu_length_err : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - sa_idx_invalid : 1, - da_idx_invalid : 1, - reserved_1b : 1, - rx_in_tx_decrypt_byp : 1, - encrypt_required : 1, - directed : 1, - buffer_fragment : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - fcs_err : 1; - uint32_t flow_idx_timeout : 1, - flow_idx_invalid : 1, - wifi_parser_error : 1, - amsdu_parser_error : 1, - sa_idx_timeout : 1, - da_idx_timeout : 1, - msdu_limit_error : 1, - da_is_valid : 1, - da_is_mcbc : 1, - sa_is_valid : 1, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - reserved_2 : 17, - msdu_done : 1; - uint32_t tlv64_padding : 32; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t fcs_err : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - buffer_fragment : 1, - directed : 1, - encrypt_required : 1, - rx_in_tx_decrypt_byp : 1, - reserved_1b : 1, - da_idx_invalid : 1, - sa_idx_invalid : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - msdu_length_err : 1, - overflow_err : 1, - cce_match : 1, - order : 1, - fragment_flag : 1, - a_msdu_error : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - reserved_1a : 1, - first_mpdu : 1; - uint32_t msdu_done : 1, - reserved_2 : 17, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - sa_is_valid : 1, - da_is_mcbc : 1, - da_is_valid : 1, - msdu_limit_error : 1, - da_idx_timeout : 1, - sa_idx_timeout : 1, - amsdu_parser_error : 1, - wifi_parser_error : 1, - flow_idx_invalid : 1, - flow_idx_timeout : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_0_LSB 9 -#define RX_ATTENTION_RESERVED_0_MSB 15 -#define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_PHY_PPDU_ID_LSB 16 -#define RX_ATTENTION_PHY_PPDU_ID_MSB 31 -#define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FIRST_MPDU_LSB 32 -#define RX_ATTENTION_FIRST_MPDU_MSB 32 -#define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 - -#define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_1A_LSB 33 -#define RX_ATTENTION_RESERVED_1A_MSB 33 -#define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 - -#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MCAST_BCAST_LSB 34 -#define RX_ATTENTION_MCAST_BCAST_MSB 34 -#define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 - -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 - -#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 - -#define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_POWER_MGMT_LSB 37 -#define RX_ATTENTION_POWER_MGMT_MSB 37 -#define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 - -#define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 -#define RX_ATTENTION_NON_QOS_LSB 38 -#define RX_ATTENTION_NON_QOS_MSB 38 -#define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 - -#define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 -#define RX_ATTENTION_NULL_DATA_LSB 39 -#define RX_ATTENTION_NULL_DATA_MSB 39 -#define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 - -#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MGMT_TYPE_LSB 40 -#define RX_ATTENTION_MGMT_TYPE_MSB 40 -#define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 - -#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 -#define RX_ATTENTION_CTRL_TYPE_LSB 41 -#define RX_ATTENTION_CTRL_TYPE_MSB 41 -#define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 - -#define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MORE_DATA_LSB 42 -#define RX_ATTENTION_MORE_DATA_MSB 42 -#define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 - -#define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 -#define RX_ATTENTION_EOSP_LSB 43 -#define RX_ATTENTION_EOSP_MSB 43 -#define RX_ATTENTION_EOSP_MASK 0x0000080000000000 - -#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_A_MSDU_ERROR_LSB 44 -#define RX_ATTENTION_A_MSDU_ERROR_MSB 44 -#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 - -#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 -#define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 -#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 - -#define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 -#define RX_ATTENTION_ORDER_LSB 46 -#define RX_ATTENTION_ORDER_MSB 46 -#define RX_ATTENTION_ORDER_MASK 0x0000400000000000 - -#define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 -#define RX_ATTENTION_CCE_MATCH_LSB 47 -#define RX_ATTENTION_CCE_MATCH_MSB 47 -#define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 - -#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_OVERFLOW_ERR_LSB 48 -#define RX_ATTENTION_OVERFLOW_ERR_MSB 48 -#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 - -#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 -#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 -#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 - -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 - -#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 -#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 -#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 -#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 - -#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_SA_IDX_INVALID_LSB 52 -#define RX_ATTENTION_SA_IDX_INVALID_MSB 52 -#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 - -#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DA_IDX_INVALID_LSB 53 -#define RX_ATTENTION_DA_IDX_INVALID_MSB 53 -#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 - -#define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_1B_LSB 54 -#define RX_ATTENTION_RESERVED_1B_MSB 54 -#define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 - -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 - -#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 -#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 -#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 -#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 - -#define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DIRECTED_LSB 57 -#define RX_ATTENTION_DIRECTED_MSB 57 -#define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 - -#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 -#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 -#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 - -#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 -#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 -#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 - -#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 -#define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 -#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 - -#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DECRYPT_ERR_LSB 61 -#define RX_ATTENTION_DECRYPT_ERR_MSB 61 -#define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 - -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 - -#define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FCS_ERR_LSB 63 -#define RX_ATTENTION_FCS_ERR_MSB 63 -#define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 - -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 - -#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 -#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 -#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 - -#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 -#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 -#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 - -#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 - -#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 -#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 -#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 - -#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 -#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 -#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 - -#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 - -#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IS_VALID_LSB 7 -#define RX_ATTENTION_DA_IS_VALID_MSB 7 -#define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 - -#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IS_MCBC_LSB 8 -#define RX_ATTENTION_DA_IS_MCBC_MSB 8 -#define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 - -#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_SA_IS_VALID_LSB 9 -#define RX_ATTENTION_SA_IS_VALID_MSB 9 -#define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 - -#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 - -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 - -#define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 -#define RX_ATTENTION_RESERVED_2_LSB 14 -#define RX_ATTENTION_RESERVED_2_MSB 30 -#define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 - -#define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 -#define RX_ATTENTION_MSDU_DONE_LSB 31 -#define RX_ATTENTION_MSDU_DONE_MSB 31 -#define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 - -#define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 -#define RX_ATTENTION_TLV64_PADDING_LSB 32 -#define RX_ATTENTION_TLV64_PADDING_MSB 63 -#define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/fig/v1/rx_flow_search_entry.h deleted file mode 100644 index 25f1f81c439f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_flow_search_entry.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FLOW_SEARCH_ENTRY_H_ -#define _RX_FLOW_SEARCH_ENTRY_H_ - -#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 - -struct rx_flow_search_entry { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t src_ip_127_96 : 32; - uint32_t src_ip_95_64 : 32; - uint32_t src_ip_63_32 : 32; - uint32_t src_ip_31_0 : 32; - uint32_t dest_ip_127_96 : 32; - uint32_t dest_ip_95_64 : 32; - uint32_t dest_ip_63_32 : 32; - uint32_t dest_ip_31_0 : 32; - uint32_t src_port : 16, - dest_port : 16; - uint32_t l4_protocol : 8, - valid : 1, - reserved_9 : 4, - service_code : 9, - priority_valid : 1, - use_ppe : 1, - reo_destination_indication : 5, - msdu_drop : 1, - reo_destination_handler : 2; - uint32_t metadata : 32; - uint32_t aggregation_count : 7, - lro_eligible : 1, - msdu_count : 24; - uint32_t msdu_byte_count : 32; - uint32_t timestamp : 32; - uint32_t cumulative_ip_length_pmac1 : 16, - cumulative_ip_length : 16; - uint32_t tcp_sequence_number : 32; -#else - uint32_t src_ip_127_96 : 32; - uint32_t src_ip_95_64 : 32; - uint32_t src_ip_63_32 : 32; - uint32_t src_ip_31_0 : 32; - uint32_t dest_ip_127_96 : 32; - uint32_t dest_ip_95_64 : 32; - uint32_t dest_ip_63_32 : 32; - uint32_t dest_ip_31_0 : 32; - uint32_t dest_port : 16, - src_port : 16; - uint32_t reo_destination_handler : 2, - msdu_drop : 1, - reo_destination_indication : 5, - use_ppe : 1, - priority_valid : 1, - service_code : 9, - reserved_9 : 4, - valid : 1, - l4_protocol : 8; - uint32_t metadata : 32; - uint32_t msdu_count : 24, - lro_eligible : 1, - aggregation_count : 7; - uint32_t msdu_byte_count : 32; - uint32_t timestamp : 32; - uint32_t cumulative_ip_length : 16, - cumulative_ip_length_pmac1 : 16; - uint32_t tcp_sequence_number : 32; -#endif -}; - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 - -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff - -#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 -#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 -#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 - -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 - -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 - -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 - -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 - -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 - -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 - -#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 -#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f - -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff - -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 - -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_frame_1k_bitmap_ack.h b/drivers/staging/fw-api/hw/fig/v1/rx_frame_1k_bitmap_ack.h deleted file mode 100644 index a43548b14a07..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_frame_1k_bitmap_ack.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ -#define _RX_FRAME_1K_BITMAP_ACK_H_ - -#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 - -#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 - -struct rx_frame_1k_bitmap_ack { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 5, - ba_bitmap_size : 2, - gen_mlo_notification : 1, - reserved_0b : 2, - ba_tid : 4, - sta_full_aid : 13, - reserved_0c : 5; - uint32_t mlo_sta_id : 10, - ba_size_1024_allowed : 1, - ba_size_512_allowed : 1, - reserved_1a : 20; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_ctrl : 16, - ba_ts_seq : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; - uint32_t ba_ts_bitmap_287_256 : 32; - uint32_t ba_ts_bitmap_319_288 : 32; - uint32_t ba_ts_bitmap_351_320 : 32; - uint32_t ba_ts_bitmap_383_352 : 32; - uint32_t ba_ts_bitmap_415_384 : 32; - uint32_t ba_ts_bitmap_447_416 : 32; - uint32_t ba_ts_bitmap_479_448 : 32; - uint32_t ba_ts_bitmap_511_480 : 32; - uint32_t ba_ts_bitmap_543_512 : 32; - uint32_t ba_ts_bitmap_575_544 : 32; - uint32_t ba_ts_bitmap_607_576 : 32; - uint32_t ba_ts_bitmap_639_608 : 32; - uint32_t ba_ts_bitmap_671_640 : 32; - uint32_t ba_ts_bitmap_703_672 : 32; - uint32_t ba_ts_bitmap_735_704 : 32; - uint32_t ba_ts_bitmap_767_736 : 32; - uint32_t ba_ts_bitmap_799_768 : 32; - uint32_t ba_ts_bitmap_831_800 : 32; - uint32_t ba_ts_bitmap_863_832 : 32; - uint32_t ba_ts_bitmap_895_864 : 32; - uint32_t ba_ts_bitmap_927_896 : 32; - uint32_t ba_ts_bitmap_959_928 : 32; - uint32_t ba_ts_bitmap_991_960 : 32; - uint32_t ba_ts_bitmap_1023_992 : 32; -#else - uint32_t reserved_0c : 5, - sta_full_aid : 13, - ba_tid : 4, - reserved_0b : 2, - gen_mlo_notification : 1, - ba_bitmap_size : 2, - reserved_0a : 5; - uint32_t reserved_1a : 20, - ba_size_512_allowed : 1, - ba_size_1024_allowed : 1, - mlo_sta_id : 10; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_seq : 16, - ba_ts_ctrl : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; - uint32_t ba_ts_bitmap_287_256 : 32; - uint32_t ba_ts_bitmap_319_288 : 32; - uint32_t ba_ts_bitmap_351_320 : 32; - uint32_t ba_ts_bitmap_383_352 : 32; - uint32_t ba_ts_bitmap_415_384 : 32; - uint32_t ba_ts_bitmap_447_416 : 32; - uint32_t ba_ts_bitmap_479_448 : 32; - uint32_t ba_ts_bitmap_511_480 : 32; - uint32_t ba_ts_bitmap_543_512 : 32; - uint32_t ba_ts_bitmap_575_544 : 32; - uint32_t ba_ts_bitmap_607_576 : 32; - uint32_t ba_ts_bitmap_639_608 : 32; - uint32_t ba_ts_bitmap_671_640 : 32; - uint32_t ba_ts_bitmap_703_672 : 32; - uint32_t ba_ts_bitmap_735_704 : 32; - uint32_t ba_ts_bitmap_767_736 : 32; - uint32_t ba_ts_bitmap_799_768 : 32; - uint32_t ba_ts_bitmap_831_800 : 32; - uint32_t ba_ts_bitmap_863_832 : 32; - uint32_t ba_ts_bitmap_895_864 : 32; - uint32_t ba_ts_bitmap_927_896 : 32; - uint32_t ba_ts_bitmap_959_928 : 32; - uint32_t ba_ts_bitmap_991_960 : 32; - uint32_t ba_ts_bitmap_1023_992 : 32; -#endif -}; - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f - -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 - -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB 7 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB 7 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK 0x0000000000000080 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 8 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000300 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 - -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 - -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MSB 41 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MASK 0x000003ff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB 42 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB 42 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK 0x0000040000000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB 43 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB 43 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK 0x0000080000000000 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_LSB 44 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MASK 0xfffff00000000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 47 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 48 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 47 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 48 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff000000000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000020 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000028 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000030 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000038 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000040 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000048 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000050 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000058 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000060 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000068 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000070 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000078 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000080 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000088 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000090 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_frame_bitmap_ack.h b/drivers/staging/fw-api/hw/fig/v1/rx_frame_bitmap_ack.h deleted file mode 100644 index 0b68486b038e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_frame_bitmap_ack.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_BITMAP_ACK_H_ -#define _RX_FRAME_BITMAP_ACK_H_ - -#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 - -#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 - -struct rx_frame_bitmap_ack { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t no_bitmap_available : 1, - explicit_ack : 1, - explict_ack_type : 3, - ba_bitmap_size : 2, - gen_mlo_notification : 1, - reserved_0a : 2, - ba_tid : 4, - sta_full_aid : 13, - reserved_0b : 5; - uint32_t mlo_sta_id : 10, - ba_size_1024_allowed : 1, - ba_size_512_allowed : 1, - ba_size_256_allowed : 1, - ba_size_128_allowed : 1, - ba_size_64_allowed : 1, - ba_size_32_allowed : 1, - reserved_1a : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_ctrl : 16, - ba_ts_seq : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; -#else - uint32_t reserved_0b : 5, - sta_full_aid : 13, - ba_tid : 4, - reserved_0a : 2, - gen_mlo_notification : 1, - ba_bitmap_size : 2, - explict_ack_type : 3, - explicit_ack : 1, - no_bitmap_available : 1; - uint32_t reserved_1a : 16, - ba_size_32_allowed : 1, - ba_size_64_allowed : 1, - ba_size_128_allowed : 1, - ba_size_256_allowed : 1, - ba_size_512_allowed : 1, - ba_size_1024_allowed : 1, - mlo_sta_id : 10; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_seq : 16, - ba_ts_ctrl : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; -#endif -}; - -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 - -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 - -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c - -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 - -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB 7 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB 7 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK 0x0000000000000080 - -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 8 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000300 - -#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 -#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 -#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 - -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 - -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 - -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_LSB 32 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MSB 41 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MASK 0x000003ff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB 42 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB 42 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK 0x0000040000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB 43 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB 43 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK 0x0000080000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_LSB 44 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MSB 44 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MASK 0x0000100000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_LSB 45 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MSB 45 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MASK 0x0000200000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_LSB 46 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MSB 46 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MASK 0x0000400000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_LSB 47 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MSB 47 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MASK 0x0000800000000000 - -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_LSB 48 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MSB 63 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 0 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 31 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 32 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 47 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 48 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 63 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 0 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 31 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 47 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 48 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000020 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000028 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000030 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_frame_bitmap_req.h b/drivers/staging/fw-api/hw/fig/v1/rx_frame_bitmap_req.h deleted file mode 100644 index 24f8ddd1c57c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_frame_bitmap_req.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_BITMAP_REQ_H_ -#define _RX_FRAME_BITMAP_REQ_H_ - -#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2 - -#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1 - -struct rx_frame_bitmap_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t explicit_user_request : 1, - user_request_type : 1, - user_number : 6, - sw_peer_id : 16, - tid_specific_request : 1, - requested_tid : 4, - reserved_0 : 3; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0 : 3, - requested_tid : 4, - tid_specific_request : 1, - sw_peer_id : 16, - user_number : 6, - user_request_type : 1, - explicit_user_request : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x0000000000000001 - -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x0000000000000002 - -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x00000000000000fc - -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x0000000000ffff00 - -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x0000000001000000 - -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x000000001e000000 - -#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0x00000000e0000000 - -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB 32 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB 63 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_location_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_location_info.h deleted file mode 100644 index ee000f6d4cda..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_location_info.h +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_LOCATION_INFO_H_ -#define _RX_LOCATION_INFO_H_ - -#define NUM_OF_DWORDS_RX_LOCATION_INFO 28 - -struct rx_location_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_location_info_valid : 1, - rtt_hw_ifft_mode : 1, - rtt___reserved_g_0020_mode : 2, - reserved_0 : 4, - rtt_num_fac : 8, - rtt_rx_chain_mask : 8, - rtt_num_streams : 8; - uint32_t rtt_first_selected_chain : 8, - rtt_second_selected_chain : 8, - rtt_cfr_status : 8, - rtt_cir_status : 8; - uint32_t rtt_che_buffer_pointer_low32 : 32; - uint32_t rtt_che_buffer_pointer_high8 : 8, - reserved_3 : 8, - rtt_pkt_bw_vht : 4, - rtt_pkt_bw_leg : 4, - rtt_mcs_rate : 8; - uint32_t rtt_cfo_measurement : 16, - rtt_preamble_type : 8, - rtt_gi_type : 8; - uint32_t rx_start_ts : 32; - uint32_t rx_start_ts_upper : 32; - uint32_t rx_end_ts : 32; - uint32_t gain_chain0 : 16, - gain_chain1 : 16; - uint32_t gain_chain2 : 16, - gain_chain3 : 16; - uint32_t gain_report_status : 8, - rtt_timing_backoff_sel : 8, - rtt_fac_combined : 16; - uint32_t rtt_fac_0 : 16, - rtt_fac_1 : 16; - uint32_t rtt_fac_2 : 16, - rtt_fac_3 : 16; - uint32_t rtt_fac_4 : 16, - rtt_fac_5 : 16; - uint32_t rtt_fac_6 : 16, - rtt_fac_7 : 16; - uint32_t rtt_fac_8 : 16, - rtt_fac_9 : 16; - uint32_t rtt_fac_10 : 16, - rtt_fac_11 : 16; - uint32_t rtt_fac_12 : 16, - rtt_fac_13 : 16; - uint32_t rtt_fac_14 : 16, - rtt_fac_15 : 16; - uint32_t rtt_fac_16 : 16, - rtt_fac_17 : 16; - uint32_t rtt_fac_18 : 16, - rtt_fac_19 : 16; - uint32_t rtt_fac_20 : 16, - rtt_fac_21 : 16; - uint32_t rtt_fac_22 : 16, - rtt_fac_23 : 16; - uint32_t rtt_fac_24 : 16, - rtt_fac_25 : 16; - uint32_t rtt_fac_26 : 16, - rtt_fac_27 : 16; - uint32_t rtt_fac_28 : 16, - rtt_fac_29 : 16; - uint32_t rtt_fac_30 : 16, - rtt_fac_31 : 16; - uint32_t reserved_27a : 32; -#else - uint32_t rtt_num_streams : 8, - rtt_rx_chain_mask : 8, - rtt_num_fac : 8, - reserved_0 : 4, - rtt___reserved_g_0020_mode : 2, - rtt_hw_ifft_mode : 1, - rx_location_info_valid : 1; - uint32_t rtt_cir_status : 8, - rtt_cfr_status : 8, - rtt_second_selected_chain : 8, - rtt_first_selected_chain : 8; - uint32_t rtt_che_buffer_pointer_low32 : 32; - uint32_t rtt_mcs_rate : 8, - rtt_pkt_bw_leg : 4, - rtt_pkt_bw_vht : 4, - reserved_3 : 8, - rtt_che_buffer_pointer_high8 : 8; - uint32_t rtt_gi_type : 8, - rtt_preamble_type : 8, - rtt_cfo_measurement : 16; - uint32_t rx_start_ts : 32; - uint32_t rx_start_ts_upper : 32; - uint32_t rx_end_ts : 32; - uint32_t gain_chain1 : 16, - gain_chain0 : 16; - uint32_t gain_chain3 : 16, - gain_chain2 : 16; - uint32_t rtt_fac_combined : 16, - rtt_timing_backoff_sel : 8, - gain_report_status : 8; - uint32_t rtt_fac_1 : 16, - rtt_fac_0 : 16; - uint32_t rtt_fac_3 : 16, - rtt_fac_2 : 16; - uint32_t rtt_fac_5 : 16, - rtt_fac_4 : 16; - uint32_t rtt_fac_7 : 16, - rtt_fac_6 : 16; - uint32_t rtt_fac_9 : 16, - rtt_fac_8 : 16; - uint32_t rtt_fac_11 : 16, - rtt_fac_10 : 16; - uint32_t rtt_fac_13 : 16, - rtt_fac_12 : 16; - uint32_t rtt_fac_15 : 16, - rtt_fac_14 : 16; - uint32_t rtt_fac_17 : 16, - rtt_fac_16 : 16; - uint32_t rtt_fac_19 : 16, - rtt_fac_18 : 16; - uint32_t rtt_fac_21 : 16, - rtt_fac_20 : 16; - uint32_t rtt_fac_23 : 16, - rtt_fac_22 : 16; - uint32_t rtt_fac_25 : 16, - rtt_fac_24 : 16; - uint32_t rtt_fac_27 : 16, - rtt_fac_26 : 16; - uint32_t rtt_fac_29 : 16, - rtt_fac_28 : 16; - uint32_t rtt_fac_31 : 16, - rtt_fac_30 : 16; - uint32_t reserved_27a : 32; -#endif -}; - -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001 - -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002 - -#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RESERVED_0_LSB 4 -#define RX_LOCATION_INFO_RESERVED_0_MSB 7 -#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0 - -#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8 -#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15 -#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff - -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff - -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff - -#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RESERVED_3_LSB 8 -#define RX_LOCATION_INFO_RESERVED_3_MSB 15 -#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16 -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19 -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000 - -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20 -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23 -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000 - -#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24 -#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31 -#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24 -#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31 -#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000 - -#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014 -#define RX_LOCATION_INFO_RX_START_TS_LSB 0 -#define RX_LOCATION_INFO_RX_START_TS_MSB 31 -#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff - -#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff - -#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c -#define RX_LOCATION_INFO_RX_END_TS_LSB 0 -#define RX_LOCATION_INFO_RX_END_TS_MSB 31 -#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff - -#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020 -#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0 -#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15 -#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff - -#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020 -#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16 -#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31 -#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000 - -#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024 -#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0 -#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15 -#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff - -#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024 -#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16 -#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31 -#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000 - -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff - -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c -#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c -#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030 -#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030 -#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034 -#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034 -#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038 -#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038 -#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c -#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c -#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040 -#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040 -#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044 -#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044 -#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048 -#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048 -#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c -#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c -#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050 -#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050 -#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054 -#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054 -#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058 -#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058 -#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c -#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c -#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060 -#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060 -#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064 -#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064 -#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068 -#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068 -#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c -#define RX_LOCATION_INFO_RESERVED_27A_LSB 0 -#define RX_LOCATION_INFO_RESERVED_27A_MSB 31 -#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_desc_info.h deleted file mode 100644 index 30f538fb1228..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_desc_info.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_DESC_INFO_H_ -#define _RX_MPDU_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 - -struct rx_mpdu_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t msdu_count : 8, - fragment_flag : 1, - mpdu_retry_bit : 1, - ampdu_flag : 1, - bar_frame : 1, - pn_fields_contain_valid_info : 1, - raw_mpdu : 1, - more_fragment_flag : 1, - src_info : 12, - mpdu_qos_control_valid : 1, - tid : 4; - uint32_t peer_meta_data : 32; -#else - uint32_t tid : 4, - mpdu_qos_control_valid : 1, - src_info : 12, - more_fragment_flag : 1, - raw_mpdu : 1, - pn_fields_contain_valid_info : 1, - bar_frame : 1, - ampdu_flag : 1, - mpdu_retry_bit : 1, - fragment_flag : 1, - msdu_count : 8; - uint32_t peer_meta_data : 32; -#endif -}; - -#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff - -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 - -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 - -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 - -#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 -#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 -#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 - -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 -#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 -#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 - -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 -#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 -#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 - -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_TID_LSB 28 -#define RX_MPDU_DESC_INFO_TID_MSB 31 -#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 - -#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_details.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_details.h deleted file mode 100644 index d2d96a0a9996..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_details.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_DETAILS_H_ -#define _RX_MPDU_DETAILS_H_ - -#include "rx_mpdu_ext_desc_info.h" -#include "rx_mpdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MPDU_DETAILS 6 - -struct rx_mpdu_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info msdu_link_desc_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_mpdu_ext_desc_info rx_mpdu_ext_desc_info_details; -#else - struct buffer_addr_info msdu_link_desc_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_mpdu_ext_desc_info rx_mpdu_ext_desc_info_details; -#endif -}; - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000 - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_end.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_end.h deleted file mode 100644 index b811f3622720..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_end.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_END_H_ -#define _RX_MPDU_END_H_ - -#define NUM_OF_DWORDS_RX_MPDU_END 4 - -#define NUM_OF_QWORDS_RX_MPDU_END 2 - -struct rx_mpdu_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t reserved_1a : 11, - unsup_ktype_short_frame : 1, - rx_in_tx_decrypt_byp : 1, - overflow_err : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - pn_fields_contain_valid_info : 1, - fcs_err : 1, - msdu_length_err : 1, - reserved1c : 6, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - reserved_1b : 1; - uint32_t reserved_2a : 15, - rxpcu_mgmt_sequence_nr_valid : 1, - rxpcu_mgmt_sequence_nr : 16; - uint32_t __reserved_g_0002 : 32; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_1b : 1, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - reserved1c : 6, - msdu_length_err : 1, - fcs_err : 1, - pn_fields_contain_valid_info : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - overflow_err : 1, - rx_in_tx_decrypt_byp : 1, - unsup_ktype_short_frame : 1, - reserved_1a : 11; - uint32_t rxpcu_mgmt_sequence_nr : 16, - rxpcu_mgmt_sequence_nr_valid : 1, - reserved_2a : 15; - uint32_t __reserved_g_0002 : 32; -#endif -}; - -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_0_LSB 9 -#define RX_MPDU_END_RESERVED_0_MSB 15 -#define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MPDU_END_PHY_PPDU_ID_LSB 16 -#define RX_MPDU_END_PHY_PPDU_ID_MSB 31 -#define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_1A_LSB 32 -#define RX_MPDU_END_RESERVED_1A_MSB 42 -#define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000 - -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 - -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 - -#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_OVERFLOW_ERR_LSB 45 -#define RX_MPDU_END_OVERFLOW_ERR_MSB 45 -#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 - -#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 -#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 -#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 - -#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 -#define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 -#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 - -#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_DECRYPT_ERR_LSB 48 -#define RX_MPDU_END_DECRYPT_ERR_MSB 48 -#define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 - -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 - -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 - -#define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_FCS_ERR_LSB 51 -#define RX_MPDU_END_FCS_ERR_MSB 51 -#define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 - -#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 -#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 -#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 - -#define RX_MPDU_END_RESERVED1C_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED1C_LSB 53 -#define RX_MPDU_END_RESERVED1C_MSB 58 -#define RX_MPDU_END_RESERVED1C_MASK 0x07e0000000000000 - -#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 - -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 - -#define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_1B_LSB 63 -#define RX_MPDU_END_RESERVED_1B_MSB 63 -#define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000 - -#define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RESERVED_2A_LSB 0 -#define RX_MPDU_END_RESERVED_2A_MSB 14 -#define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff - -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 - -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_ext_desc_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_ext_desc_info.h deleted file mode 100644 index 83f4df333c88..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_ext_desc_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_EXT_DESC_INFO_H_ -#define _RX_MPDU_EXT_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MPDU_EXT_DESC_INFO 2 - -struct rx_mpdu_ext_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pn_31_0 : 32; - uint32_t pn_47_32 : 16, - pn_127_48_info : 2, - msdu_link_desc_index : 4, - reserved_1a : 10; -#else - uint32_t pn_31_0 : 32; - uint32_t reserved_1a : 10, - msdu_link_desc_index : 4, - pn_127_48_info : 2, - pn_47_32 : 16; -#endif -}; - -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_OFFSET 0x00000000 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_LSB 0 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MSB 31 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_LSB 0 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MSB 15 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MASK 0x0000ffff - -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_LSB 16 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MSB 17 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MASK 0x00030000 - -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_LSB 18 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MSB 21 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_LSB 22 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MSB 31 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_info.h deleted file mode 100644 index b742b6ce733b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_info.h +++ /dev/null @@ -1,958 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_INFO_H_ -#define _RX_MPDU_INFO_H_ - -#include "rxpt_classify_info.h" -#define NUM_OF_DWORDS_RX_MPDU_INFO 30 - -struct rx_mpdu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rxpt_classify_info rxpt_classify_info_details; - uint32_t epd_en : 1, - all_frames_shall_be_encrypted : 1, - encrypt_type : 4, - wep_key_width_for_variable_key : 2, - __reserved_g_0003 : 2, - bssid_hit : 1, - bssid_number : 4, - tid : 4, - reserved_7a : 13; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t rx_reo_queue_desc_addr_39_32 : 8, - receive_queue_number : 16, - pre_delim_err_warning : 1, - first_delim_err : 1, - reserved_2a : 6; - uint32_t pn_31_0 : 32; - uint32_t pn_63_32 : 32; - uint32_t pn_95_64 : 32; - uint32_t pn_127_96 : 32; - uint32_t mpdu_frame_control_valid : 1, - mpdu_duration_valid : 1, - mac_addr_ad1_valid : 1, - mac_addr_ad2_valid : 1, - mac_addr_ad3_valid : 1, - mac_addr_ad4_valid : 1, - mpdu_sequence_control_valid : 1, - mpdu_qos_control_valid : 1, - mpdu_ht_control_valid : 1, - frame_encryption_info_valid : 1, - mpdu_fragment_number : 4, - more_fragment_flag : 1, - reserved_11a : 1, - fr_ds : 1, - to_ds : 1, - encrypted : 1, - mpdu_retry : 1, - mpdu_sequence_number : 12; - uint32_t peer_meta_data : 32; - uint32_t ast_index : 16, - sw_peer_id : 16; - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - ndp_frame : 1, - phy_err : 1, - phy_err_during_mpdu_header : 1, - protocol_version_err : 1, - ast_based_lookup_valid : 1, - __reserved_g_0022 : 1, - __reserved_g_0035 : 1, - phy_ppdu_id : 16; - uint32_t key_id_octet : 8, - new_peer_entry : 1, - decrypt_needed : 1, - decap_type : 2, - rx_insert_vlan_c_tag_padding : 1, - rx_insert_vlan_s_tag_padding : 1, - strip_vlan_c_tag_decap : 1, - strip_vlan_s_tag_decap : 1, - pre_delim_count : 12, - ampdu_flag : 1, - bar_frame : 1, - raw_mpdu : 1, - reserved_12 : 1; - uint32_t mpdu_length : 14, - first_mpdu : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - fragment_flag : 1, - order : 1, - u_apsd_trigger : 1, - encrypt_required : 1, - directed : 1, - amsdu_present : 1, - reserved_13 : 1; - uint32_t mpdu_frame_control_field : 16, - mpdu_duration_field : 16; - uint32_t mac_addr_ad1_31_0 : 32; - uint32_t mac_addr_ad1_47_32 : 16, - mac_addr_ad2_15_0 : 16; - uint32_t mac_addr_ad2_47_16 : 32; - uint32_t mac_addr_ad3_31_0 : 32; - uint32_t mac_addr_ad3_47_32 : 16, - mpdu_sequence_control_field : 16; - uint32_t mac_addr_ad4_31_0 : 32; - uint32_t mac_addr_ad4_47_32 : 16, - mpdu_qos_control_field : 16; - uint32_t mpdu_ht_control_field : 32; - uint32_t vdev_id : 8, - service_code : 9, - priority_valid : 1, - src_info : 12, - reserved_23a : 1, - __reserved_g_0006 : 1; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0008 : 16, - __reserved_g_0009 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t authorized_to_send_wds : 1, - disallow_mcbc_da_in_unicast_mpdu : 1, - fromtods_00_fnf_check_dis : 1, - fromtods_01_fnf_check_dis : 1, - fromtods_10_fnf_check_dis : 1, - fromtods_11_fnf_check_dis : 1, - rx_misc_config : 3, - a_msdu_fromtods_10_ad3 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_11_ad4 : 2, - multi_link_addr_fromtods_00_raw_en : 1, - multi_link_addr_fromtods_non00_raw_en : 1, - multi_link_addr_ad3_valid : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_ad1_trans_dis : 1, - data_fromtods_00_ad3 : 2, - mgmt_fromtods_00_ad3 : 2, - multi_link_addr_mgmt_en : 1, - multi_link_addr_ctrl_en : 1, - reserved_27a : 5; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t multi_link_addr_ad3_47_32 : 16, - reserved_29a : 16; -#else - struct rxpt_classify_info rxpt_classify_info_details; - uint32_t reserved_7a : 13, - tid : 4, - bssid_number : 4, - bssid_hit : 1, - __reserved_g_0003 : 2, - wep_key_width_for_variable_key : 2, - encrypt_type : 4, - all_frames_shall_be_encrypted : 1, - epd_en : 1; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t reserved_2a : 6, - first_delim_err : 1, - pre_delim_err_warning : 1, - receive_queue_number : 16, - rx_reo_queue_desc_addr_39_32 : 8; - uint32_t pn_31_0 : 32; - uint32_t pn_63_32 : 32; - uint32_t pn_95_64 : 32; - uint32_t pn_127_96 : 32; - uint32_t mpdu_sequence_number : 12, - mpdu_retry : 1, - encrypted : 1, - to_ds : 1, - fr_ds : 1, - reserved_11a : 1, - more_fragment_flag : 1, - mpdu_fragment_number : 4, - frame_encryption_info_valid : 1, - mpdu_ht_control_valid : 1, - mpdu_qos_control_valid : 1, - mpdu_sequence_control_valid : 1, - mac_addr_ad4_valid : 1, - mac_addr_ad3_valid : 1, - mac_addr_ad2_valid : 1, - mac_addr_ad1_valid : 1, - mpdu_duration_valid : 1, - mpdu_frame_control_valid : 1; - uint32_t peer_meta_data : 32; - uint32_t sw_peer_id : 16, - ast_index : 16; - uint32_t phy_ppdu_id : 16, - __reserved_g_0035 : 1, - __reserved_g_0022 : 1, - ast_based_lookup_valid : 1, - protocol_version_err : 1, - phy_err_during_mpdu_header : 1, - phy_err : 1, - ndp_frame : 1, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_12 : 1, - raw_mpdu : 1, - bar_frame : 1, - ampdu_flag : 1, - pre_delim_count : 12, - strip_vlan_s_tag_decap : 1, - strip_vlan_c_tag_decap : 1, - rx_insert_vlan_s_tag_padding : 1, - rx_insert_vlan_c_tag_padding : 1, - decap_type : 2, - decrypt_needed : 1, - new_peer_entry : 1, - key_id_octet : 8; - uint32_t reserved_13 : 1, - amsdu_present : 1, - directed : 1, - encrypt_required : 1, - u_apsd_trigger : 1, - order : 1, - fragment_flag : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - first_mpdu : 1, - mpdu_length : 14; - uint32_t mpdu_duration_field : 16, - mpdu_frame_control_field : 16; - uint32_t mac_addr_ad1_31_0 : 32; - uint32_t mac_addr_ad2_15_0 : 16, - mac_addr_ad1_47_32 : 16; - uint32_t mac_addr_ad2_47_16 : 32; - uint32_t mac_addr_ad3_31_0 : 32; - uint32_t mpdu_sequence_control_field : 16, - mac_addr_ad3_47_32 : 16; - uint32_t mac_addr_ad4_31_0 : 32; - uint32_t mpdu_qos_control_field : 16, - mac_addr_ad4_47_32 : 16; - uint32_t mpdu_ht_control_field : 32; - uint32_t __reserved_g_0006 : 1, - reserved_23a : 1, - src_info : 12, - priority_valid : 1, - service_code : 9, - vdev_id : 8; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0009 : 16, - __reserved_g_0008 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t reserved_27a : 5, - multi_link_addr_ctrl_en : 1, - multi_link_addr_mgmt_en : 1, - mgmt_fromtods_00_ad3 : 2, - data_fromtods_00_ad3 : 2, - multi_link_addr_ad1_trans_dis : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_ad3_valid : 1, - multi_link_addr_fromtods_non00_raw_en : 1, - multi_link_addr_fromtods_00_raw_en : 1, - a_msdu_fromtods_11_ad4 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_10_ad3 : 2, - rx_misc_config : 3, - fromtods_11_fnf_check_dis : 1, - fromtods_10_fnf_check_dis : 1, - fromtods_01_fnf_check_dis : 1, - fromtods_00_fnf_check_dis : 1, - disallow_mcbc_da_in_unicast_mpdu : 1, - authorized_to_send_wds : 1; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t reserved_29a : 16, - multi_link_addr_ad3_47_32 : 16; -#endif -}; - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000 - -#define RX_MPDU_INFO_EPD_EN_OFFSET 0x00000004 -#define RX_MPDU_INFO_EPD_EN_LSB 0 -#define RX_MPDU_INFO_EPD_EN_MSB 0 -#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 - -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 - -#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x00000004 -#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 -#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 -#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c - -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 - -#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x00000004 -#define RX_MPDU_INFO_BSSID_HIT_LSB 10 -#define RX_MPDU_INFO_BSSID_HIT_MSB 10 -#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 - -#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x00000004 -#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 -#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 -#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 - -#define RX_MPDU_INFO_TID_OFFSET 0x00000004 -#define RX_MPDU_INFO_TID_LSB 15 -#define RX_MPDU_INFO_TID_MSB 18 -#define RX_MPDU_INFO_TID_MASK 0x00078000 - -#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x00000004 -#define RX_MPDU_INFO_RESERVED_7A_LSB 19 -#define RX_MPDU_INFO_RESERVED_7A_MSB 31 -#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 - -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 - -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 - -#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x0000000c -#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 -#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 -#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 - -#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x0000000c -#define RX_MPDU_INFO_RESERVED_2A_LSB 26 -#define RX_MPDU_INFO_RESERVED_2A_MSB 31 -#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 - -#define RX_MPDU_INFO_PN_31_0_OFFSET 0x00000010 -#define RX_MPDU_INFO_PN_31_0_LSB 0 -#define RX_MPDU_INFO_PN_31_0_MSB 31 -#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000014 -#define RX_MPDU_INFO_PN_63_32_LSB 0 -#define RX_MPDU_INFO_PN_63_32_MSB 31 -#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000018 -#define RX_MPDU_INFO_PN_95_64_LSB 0 -#define RX_MPDU_INFO_PN_95_64_MSB 31 -#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_127_96_OFFSET 0x0000001c -#define RX_MPDU_INFO_PN_127_96_LSB 0 -#define RX_MPDU_INFO_PN_127_96_MSB 31 -#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff - -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 - -#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 - -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 - -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 - -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 - -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 - -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 - -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 - -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 - -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 - -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 - -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000020 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x00000020 -#define RX_MPDU_INFO_RESERVED_11A_LSB 15 -#define RX_MPDU_INFO_RESERVED_11A_MSB 15 -#define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 - -#define RX_MPDU_INFO_FR_DS_OFFSET 0x00000020 -#define RX_MPDU_INFO_FR_DS_LSB 16 -#define RX_MPDU_INFO_FR_DS_MSB 16 -#define RX_MPDU_INFO_FR_DS_MASK 0x00010000 - -#define RX_MPDU_INFO_TO_DS_OFFSET 0x00000020 -#define RX_MPDU_INFO_TO_DS_LSB 17 -#define RX_MPDU_INFO_TO_DS_MSB 17 -#define RX_MPDU_INFO_TO_DS_MASK 0x00020000 - -#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x00000020 -#define RX_MPDU_INFO_ENCRYPTED_LSB 18 -#define RX_MPDU_INFO_ENCRYPTED_MSB 18 -#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 - -#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_RETRY_LSB 19 -#define RX_MPDU_INFO_MPDU_RETRY_MSB 19 -#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 - -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 - -#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000024 -#define RX_MPDU_INFO_PEER_META_DATA_LSB 0 -#define RX_MPDU_INFO_PEER_META_DATA_MSB 31 -#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff - -#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 -#define RX_MPDU_INFO_AST_INDEX_LSB 0 -#define RX_MPDU_INFO_AST_INDEX_MSB 15 -#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff - -#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 -#define RX_MPDU_INFO_SW_PEER_ID_LSB 16 -#define RX_MPDU_INFO_SW_PEER_ID_MSB 31 -#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 - -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 - -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x0000002c -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc - -#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x0000002c -#define RX_MPDU_INFO_NDP_FRAME_LSB 9 -#define RX_MPDU_INFO_NDP_FRAME_MSB 9 -#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 - -#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_ERR_LSB 10 -#define RX_MPDU_INFO_PHY_ERR_MSB 10 -#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 - -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 - -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 - -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 - -#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 -#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 -#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 - -#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 -#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 -#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 -#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff - -#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 - -#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 -#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 -#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 -#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 - -#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 -#define RX_MPDU_INFO_DECAP_TYPE_LSB 10 -#define RX_MPDU_INFO_DECAP_TYPE_MSB 11 -#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 - -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 - -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 - -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 - -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 - -#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 - -#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 -#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 -#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 -#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 - -#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 -#define RX_MPDU_INFO_BAR_FRAME_LSB 29 -#define RX_MPDU_INFO_BAR_FRAME_MSB 29 -#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 - -#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 -#define RX_MPDU_INFO_RAW_MPDU_LSB 30 -#define RX_MPDU_INFO_RAW_MPDU_MSB 30 -#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 - -#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 -#define RX_MPDU_INFO_RESERVED_12_LSB 31 -#define RX_MPDU_INFO_RESERVED_12_MSB 31 -#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 - -#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 -#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 -#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 -#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff - -#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 -#define RX_MPDU_INFO_FIRST_MPDU_LSB 14 -#define RX_MPDU_INFO_FIRST_MPDU_MSB 14 -#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 - -#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 -#define RX_MPDU_INFO_MCAST_BCAST_LSB 15 -#define RX_MPDU_INFO_MCAST_BCAST_MSB 15 -#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 - -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 - -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 - -#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 -#define RX_MPDU_INFO_POWER_MGMT_LSB 18 -#define RX_MPDU_INFO_POWER_MGMT_MSB 18 -#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 - -#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 -#define RX_MPDU_INFO_NON_QOS_LSB 19 -#define RX_MPDU_INFO_NON_QOS_MSB 19 -#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 - -#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 -#define RX_MPDU_INFO_NULL_DATA_LSB 20 -#define RX_MPDU_INFO_NULL_DATA_MSB 20 -#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 - -#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 -#define RX_MPDU_INFO_MGMT_TYPE_LSB 21 -#define RX_MPDU_INFO_MGMT_TYPE_MSB 21 -#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 - -#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 -#define RX_MPDU_INFO_CTRL_TYPE_LSB 22 -#define RX_MPDU_INFO_CTRL_TYPE_MSB 22 -#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 - -#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 -#define RX_MPDU_INFO_MORE_DATA_LSB 23 -#define RX_MPDU_INFO_MORE_DATA_MSB 23 -#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 - -#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 -#define RX_MPDU_INFO_EOSP_LSB 24 -#define RX_MPDU_INFO_EOSP_MSB 24 -#define RX_MPDU_INFO_EOSP_MASK 0x01000000 - -#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 -#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 -#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 -#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 - -#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 -#define RX_MPDU_INFO_ORDER_LSB 26 -#define RX_MPDU_INFO_ORDER_MSB 26 -#define RX_MPDU_INFO_ORDER_MASK 0x04000000 - -#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 -#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 -#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 -#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 - -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 - -#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 -#define RX_MPDU_INFO_DIRECTED_LSB 29 -#define RX_MPDU_INFO_DIRECTED_MSB 29 -#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 - -#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 -#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 -#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 -#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 - -#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 -#define RX_MPDU_INFO_RESERVED_13_LSB 31 -#define RX_MPDU_INFO_RESERVED_13_MSB 31 -#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 - -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff - -#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c -#define RX_MPDU_INFO_VDEV_ID_LSB 0 -#define RX_MPDU_INFO_VDEV_ID_MSB 7 -#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff - -#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c -#define RX_MPDU_INFO_SERVICE_CODE_LSB 8 -#define RX_MPDU_INFO_SERVICE_CODE_MSB 16 -#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 - -#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c -#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 -#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 -#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 - -#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c -#define RX_MPDU_INFO_SRC_INFO_LSB 18 -#define RX_MPDU_INFO_SRC_INFO_MSB 29 -#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 - -#define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c -#define RX_MPDU_INFO_RESERVED_23A_LSB 30 -#define RX_MPDU_INFO_RESERVED_23A_MSB 30 -#define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 - -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 - -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET 0x0000006c -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB 1 -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB 1 -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK 0x00000002 - -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_LSB 2 -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MSB 2 -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MASK 0x00000004 - -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_LSB 3 -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MSB 3 -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MASK 0x00000008 - -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_LSB 4 -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MSB 4 -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MASK 0x00000010 - -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_LSB 5 -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MSB 5 -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MASK 0x00000020 - -#define RX_MPDU_INFO_RX_MISC_CONFIG_OFFSET 0x0000006c -#define RX_MPDU_INFO_RX_MISC_CONFIG_LSB 6 -#define RX_MPDU_INFO_RX_MISC_CONFIG_MSB 8 -#define RX_MPDU_INFO_RX_MISC_CONFIG_MASK 0x000001c0 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_LSB 9 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MSB 10 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MASK 0x00000600 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_LSB 11 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MSB 12 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MASK 0x00001800 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_LSB 13 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MSB 14 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MASK 0x00006000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_LSB 15 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_MSB 15 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_MASK 0x00008000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_LSB 16 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_MSB 16 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x00010000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_VALID_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_VALID_LSB 17 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_VALID_MSB 17 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_VALID_MASK 0x00020000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 18 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 18 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x00040000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 19 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 19 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x00080000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 20 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 20 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x00100000 - -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_LSB 21 -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MSB 22 -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MASK 0x00600000 - -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_LSB 23 -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MSB 24 -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MASK 0x01800000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_EN_LSB 25 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_EN_MSB 25 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_EN_MASK 0x02000000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_CTRL_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_CTRL_EN_LSB 26 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_CTRL_EN_MSB 26 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_CTRL_EN_MASK 0x04000000 - -#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c -#define RX_MPDU_INFO_RESERVED_27A_LSB 27 -#define RX_MPDU_INFO_RESERVED_27A_MSB 31 -#define RX_MPDU_INFO_RESERVED_27A_MASK 0xf8000000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_31_0_OFFSET 0x00000070 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_47_32_OFFSET 0x00000074 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_47_32_LSB 0 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_47_32_MSB 15 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 -#define RX_MPDU_INFO_RESERVED_29A_LSB 16 -#define RX_MPDU_INFO_RESERVED_29A_MSB 31 -#define RX_MPDU_INFO_RESERVED_29A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_link_ptr.h deleted file mode 100644 index e9d7e83a92cc..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_link_ptr.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_LINK_PTR_H_ -#define _RX_MPDU_LINK_PTR_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 - -struct rx_mpdu_link_ptr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info mpdu_link_desc_addr_info; -#else - struct buffer_addr_info mpdu_link_desc_addr_info; -#endif -}; - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_start.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_start.h deleted file mode 100644 index 3f98c5b7377d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_start.h +++ /dev/null @@ -1,702 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_START_H_ -#define _RX_MPDU_START_H_ - -#include "rx_mpdu_info.h" -#define NUM_OF_DWORDS_RX_MPDU_START 30 - -#define NUM_OF_QWORDS_RX_MPDU_START 15 - -struct rx_mpdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_mpdu_info rx_mpdu_info_details; -#else - struct rx_mpdu_info rx_mpdu_info_details; -#endif -}; - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x0000000000100000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x0000000000400000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ff800000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x0000000100000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x0000000200000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 38 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x0000040000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x0000780000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x0007800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff8000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff0000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x0100000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc00000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000000000010 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x0000000000000010 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x0000000000000018 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000000000000018 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x0000000000000001 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 1 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x0000000000000002 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 2 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x0000000000000004 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 3 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x0000000000000008 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x0000000000000010 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x0000000000000020 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x0000000000000040 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x0000000000000080 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x0000000000003c00 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x0000000000004000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x0000000000008000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x0000000000010000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x0000000000020000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x0000000000040000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x0000000000080000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x00000000fff00000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000300000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x0000020000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x0000040000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x0000080000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x0000100000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x0000200000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x00000000000000ff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x0000000000000c00 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x0000000000001000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x0000000000002000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x0000000000004000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x0000000000008000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x000000000fff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x0000000010000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x0000000020000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x0000000040000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x0000000080000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x0000400000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x0000800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x0004000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x0008000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x0010000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x0020000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x0040000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x0080000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x0100000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x0400000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x0800000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 60 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 60 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x1000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x2000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x4000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x8000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff0000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK 0x4000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x0000000100000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK 0x0000000200000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MASK 0x0000000400000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_LSB 35 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MSB 35 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MASK 0x0000000800000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_LSB 36 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MSB 36 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MASK 0x0000001000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_LSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MASK 0x0000002000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_LSB 38 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MASK 0x000001c000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_LSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MASK 0x0000060000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MASK 0x0000180000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_LSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MASK 0x0000600000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_MASK 0x0000800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_VALID_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_VALID_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_VALID_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_VALID_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0004000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x0008000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x0010000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_LSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MASK 0x0060000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_LSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MASK 0x0180000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_EN_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_EN_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_EN_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_CTRL_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_CTRL_EN_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_CTRL_EN_MSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_CTRL_EN_MASK 0x0400000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xf800000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_31_0_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_47_32_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_msdu_desc_info.h deleted file mode 100644 index 88569b653b64..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_desc_info.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_DESC_INFO_H_ -#define _RX_MSDU_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 - -struct rx_msdu_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t first_msdu_in_mpdu_flag : 1, - last_msdu_in_mpdu_flag : 1, - msdu_continuation : 1, - msdu_length : 14, - msdu_drop : 1, - sa_is_valid : 1, - da_is_valid : 1, - da_is_mcbc : 1, - l3_header_padding_msb : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - fr_ds : 1, - to_ds : 1, - intra_bss : 1, - dest_chip_id : 2, - decap_format : 2, - __reserved_g_0015 : 1; -#else - uint32_t __reserved_g_0015 : 1, - decap_format : 2, - dest_chip_id : 2, - intra_bss : 1, - to_ds : 1, - fr_ds : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - l3_header_padding_msb : 1, - da_is_mcbc : 1, - da_is_valid : 1, - sa_is_valid : 1, - msdu_drop : 1, - msdu_length : 14, - msdu_continuation : 1, - last_msdu_in_mpdu_flag : 1, - first_msdu_in_mpdu_flag : 1; -#endif -}; - -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 -#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 -#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_FR_DS_LSB 24 -#define RX_MSDU_DESC_INFO_FR_DS_MSB 24 -#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 - -#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_TO_DS_LSB 25 -#define RX_MSDU_DESC_INFO_TO_DS_MSB 25 -#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 - -#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 -#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 -#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_details.h b/drivers/staging/fw-api/hw/fig/v1/rx_msdu_details.h deleted file mode 100644 index 0b763a473ce6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_details.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_DETAILS_H_ -#define _RX_MSDU_DETAILS_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_msdu_ext_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 - -struct rx_msdu_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buffer_addr_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; -#else - struct buffer_addr_info buffer_addr_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; -#endif -}; - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xe0000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_end.h b/drivers/staging/fw-api/hw/fig/v1/rx_msdu_end.h deleted file mode 100644 index 34753b47edc7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_end.h +++ /dev/null @@ -1,1087 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_END_H_ -#define _RX_MSDU_END_H_ - -#define NUM_OF_DWORDS_RX_MSDU_END 32 - -#define NUM_OF_QWORDS_RX_MSDU_END 16 - -struct rx_msdu_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t ip_hdr_chksum : 16, - reported_mpdu_length : 14, - reserved_1a : 2; - uint32_t reserved_2a : 8, - cce_super_rule : 6, - cce_classify_not_done_truncate : 1, - cce_classify_not_done_cce_dis : 1, - cumulative_l3_checksum : 16; - uint32_t rule_indication_31_0 : 32; - uint32_t ipv6_options_crc : 32; - uint32_t da_offset : 6, - sa_offset : 6, - da_offset_valid : 1, - sa_offset_valid : 1, - reserved_5a : 2, - l3_type : 16; - uint32_t rule_indication_63_32 : 32; - uint32_t tcp_seq_number : 32; - uint32_t tcp_ack_number : 32; - uint32_t tcp_flag : 9, - lro_eligible : 1, - reserved_9a : 6, - window_size : 16; - uint32_t sa_sw_peer_id : 16, - sa_idx_timeout : 1, - da_idx_timeout : 1, - to_ds : 1, - tid : 4, - sa_is_valid : 1, - da_is_valid : 1, - da_is_mcbc : 1, - l3_header_padding : 2, - first_msdu : 1, - last_msdu : 1, - fr_ds : 1, - ip_chksum_fail_copy : 1; - uint32_t sa_idx : 16, - da_idx_or_sw_peer_id : 16; - uint32_t msdu_drop : 1, - reo_destination_indication : 5, - flow_idx : 20, - use_ppe : 1, - __reserved_g_0003 : 2, - vlan_ctag_stripped : 1, - vlan_stag_stripped : 1, - fragment_flag : 1; - uint32_t fse_metadata : 32; - uint32_t cce_metadata : 16, - tcp_udp_chksum : 16; - uint32_t aggregation_count : 8, - flow_aggregation_continuation : 1, - fisa_timeout : 1, - tcp_udp_chksum_fail_copy : 1, - msdu_limit_error : 1, - flow_idx_timeout : 1, - flow_idx_invalid : 1, - cce_match : 1, - amsdu_parser_error : 1, - cumulative_ip_length : 16; - uint32_t key_id_octet : 8, - reserved_16a : 24; - uint32_t reserved_17a : 6, - service_code : 9, - priority_valid : 1, - intra_bss : 1, - dest_chip_id : 2, - multicast_echo : 1, - wds_learning_event : 1, - wds_roaming_event : 1, - wds_keep_alive_event : 1, - __reserved_g_0015 : 1, - reserved_17b : 8; - uint32_t msdu_length : 14, - stbc : 1, - ipsec_esp : 1, - l3_offset : 7, - ipsec_ah : 1, - l4_offset : 8; - uint32_t msdu_number : 8, - decap_format : 2, - ipv4_proto : 1, - ipv6_proto : 1, - tcp_proto : 1, - udp_proto : 1, - ip_frag : 1, - tcp_only_ack : 1, - da_is_bcast_mcast : 1, - toeplitz_hash_sel : 2, - ip_fixed_header_valid : 1, - ip_extn_header_valid : 1, - tcp_udp_header_valid : 1, - mesh_control_present : 1, - ldpc : 1, - ip4_protocol_ip6_next_header : 8; - uint32_t vlan_ctag_ci : 16, - vlan_stag_ci : 16; - uint32_t peer_meta_data : 32; - uint32_t user_rssi : 8, - pkt_type : 4, - sgi : 2, - rate_mcs : 5, - receive_bandwidth : 3, - reception_type : 3, - mimo_ss_bitmap : 6, - msdu_done_copy : 1; - uint32_t flow_id_toeplitz : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t reserved_28a : 16, - sa_15_0 : 16; - uint32_t sa_47_16 : 32; - uint32_t first_mpdu : 1, - reserved_30a : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - a_msdu_error : 1, - reserved_30b : 1, - order : 1, - wifi_parser_error : 1, - overflow_err : 1, - msdu_length_err : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - sa_idx_invalid : 1, - da_idx_invalid : 1, - amsdu_addr_mismatch : 1, - rx_in_tx_decrypt_byp : 1, - encrypt_required : 1, - directed : 1, - buffer_fragment : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - fcs_err : 1; - uint32_t reserved_31a : 10, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - reserved_31b : 17, - msdu_done : 1; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_1a : 2, - reported_mpdu_length : 14, - ip_hdr_chksum : 16; - uint32_t cumulative_l3_checksum : 16, - cce_classify_not_done_cce_dis : 1, - cce_classify_not_done_truncate : 1, - cce_super_rule : 6, - reserved_2a : 8; - uint32_t rule_indication_31_0 : 32; - uint32_t ipv6_options_crc : 32; - uint32_t l3_type : 16, - reserved_5a : 2, - sa_offset_valid : 1, - da_offset_valid : 1, - sa_offset : 6, - da_offset : 6; - uint32_t rule_indication_63_32 : 32; - uint32_t tcp_seq_number : 32; - uint32_t tcp_ack_number : 32; - uint32_t window_size : 16, - reserved_9a : 6, - lro_eligible : 1, - tcp_flag : 9; - uint32_t ip_chksum_fail_copy : 1, - fr_ds : 1, - last_msdu : 1, - first_msdu : 1, - l3_header_padding : 2, - da_is_mcbc : 1, - da_is_valid : 1, - sa_is_valid : 1, - tid : 4, - to_ds : 1, - da_idx_timeout : 1, - sa_idx_timeout : 1, - sa_sw_peer_id : 16; - uint32_t da_idx_or_sw_peer_id : 16, - sa_idx : 16; - uint32_t fragment_flag : 1, - vlan_stag_stripped : 1, - vlan_ctag_stripped : 1, - __reserved_g_0003 : 2, - use_ppe : 1, - flow_idx : 20, - reo_destination_indication : 5, - msdu_drop : 1; - uint32_t fse_metadata : 32; - uint32_t tcp_udp_chksum : 16, - cce_metadata : 16; - uint32_t cumulative_ip_length : 16, - amsdu_parser_error : 1, - cce_match : 1, - flow_idx_invalid : 1, - flow_idx_timeout : 1, - msdu_limit_error : 1, - tcp_udp_chksum_fail_copy : 1, - fisa_timeout : 1, - flow_aggregation_continuation : 1, - aggregation_count : 8; - uint32_t reserved_16a : 24, - key_id_octet : 8; - uint32_t reserved_17b : 8, - __reserved_g_0015 : 1, - wds_keep_alive_event : 1, - wds_roaming_event : 1, - wds_learning_event : 1, - multicast_echo : 1, - dest_chip_id : 2, - intra_bss : 1, - priority_valid : 1, - service_code : 9, - reserved_17a : 6; - uint32_t l4_offset : 8, - ipsec_ah : 1, - l3_offset : 7, - ipsec_esp : 1, - stbc : 1, - msdu_length : 14; - uint32_t ip4_protocol_ip6_next_header : 8, - ldpc : 1, - mesh_control_present : 1, - tcp_udp_header_valid : 1, - ip_extn_header_valid : 1, - ip_fixed_header_valid : 1, - toeplitz_hash_sel : 2, - da_is_bcast_mcast : 1, - tcp_only_ack : 1, - ip_frag : 1, - udp_proto : 1, - tcp_proto : 1, - ipv6_proto : 1, - ipv4_proto : 1, - decap_format : 2, - msdu_number : 8; - uint32_t vlan_stag_ci : 16, - vlan_ctag_ci : 16; - uint32_t peer_meta_data : 32; - uint32_t msdu_done_copy : 1, - mimo_ss_bitmap : 6, - reception_type : 3, - receive_bandwidth : 3, - rate_mcs : 5, - sgi : 2, - pkt_type : 4, - user_rssi : 8; - uint32_t flow_id_toeplitz : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t sa_15_0 : 16, - reserved_28a : 16; - uint32_t sa_47_16 : 32; - uint32_t fcs_err : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - buffer_fragment : 1, - directed : 1, - encrypt_required : 1, - rx_in_tx_decrypt_byp : 1, - amsdu_addr_mismatch : 1, - da_idx_invalid : 1, - sa_idx_invalid : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - msdu_length_err : 1, - overflow_err : 1, - wifi_parser_error : 1, - order : 1, - reserved_30b : 1, - a_msdu_error : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - reserved_30a : 1, - first_mpdu : 1; - uint32_t msdu_done : 1, - reserved_31b : 17, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - reserved_31a : 10; -#endif -}; - -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RESERVED_0_LSB 9 -#define RX_MSDU_END_RESERVED_0_MSB 15 -#define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_END_PHY_PPDU_ID_LSB 16 -#define RX_MSDU_END_PHY_PPDU_ID_MSB 31 -#define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 -#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 -#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 -#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 - -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 - -#define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RESERVED_1A_LSB 62 -#define RX_MSDU_END_RESERVED_1A_MSB 63 -#define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 - -#define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MSDU_END_RESERVED_2A_LSB 0 -#define RX_MSDU_END_RESERVED_2A_MSB 7 -#define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff - -#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 -#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 -#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 - -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 - -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 - -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 -#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 -#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 -#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 - -#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff - -#define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 -#define RX_MSDU_END_DA_OFFSET_LSB 32 -#define RX_MSDU_END_DA_OFFSET_MSB 37 -#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 - -#define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 -#define RX_MSDU_END_SA_OFFSET_LSB 38 -#define RX_MSDU_END_SA_OFFSET_MSB 43 -#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 - -#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 -#define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 -#define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 -#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 - -#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 -#define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 -#define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 -#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 - -#define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 -#define RX_MSDU_END_RESERVED_5A_LSB 46 -#define RX_MSDU_END_RESERVED_5A_MSB 47 -#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 - -#define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_END_L3_TYPE_LSB 48 -#define RX_MSDU_END_L3_TYPE_MSB 63 -#define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 - -#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 -#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 -#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 -#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 -#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 -#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 - -#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 -#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 -#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 -#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 -#define RX_MSDU_END_TCP_FLAG_LSB 32 -#define RX_MSDU_END_TCP_FLAG_MSB 40 -#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 - -#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 -#define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 -#define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 -#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 - -#define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 -#define RX_MSDU_END_RESERVED_9A_LSB 42 -#define RX_MSDU_END_RESERVED_9A_MSB 47 -#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 - -#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 -#define RX_MSDU_END_WINDOW_SIZE_LSB 48 -#define RX_MSDU_END_WINDOW_SIZE_MSB 63 -#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 - -#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 -#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 -#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff - -#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 -#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 -#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 - -#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 -#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 -#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 - -#define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 -#define RX_MSDU_END_TO_DS_LSB 18 -#define RX_MSDU_END_TO_DS_MSB 18 -#define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 - -#define RX_MSDU_END_TID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_TID_LSB 19 -#define RX_MSDU_END_TID_MSB 22 -#define RX_MSDU_END_TID_MASK 0x0000000000780000 - -#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IS_VALID_LSB 23 -#define RX_MSDU_END_SA_IS_VALID_MSB 23 -#define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 - -#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IS_VALID_LSB 24 -#define RX_MSDU_END_DA_IS_VALID_MSB 24 -#define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 - -#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IS_MCBC_LSB 25 -#define RX_MSDU_END_DA_IS_MCBC_MSB 25 -#define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 - -#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 -#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 -#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 -#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 - -#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 -#define RX_MSDU_END_FIRST_MSDU_LSB 28 -#define RX_MSDU_END_FIRST_MSDU_MSB 28 -#define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 - -#define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 -#define RX_MSDU_END_LAST_MSDU_LSB 29 -#define RX_MSDU_END_LAST_MSDU_MSB 29 -#define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 - -#define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 -#define RX_MSDU_END_FR_DS_LSB 30 -#define RX_MSDU_END_FR_DS_MSB 30 -#define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 - -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 - -#define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IDX_LSB 32 -#define RX_MSDU_END_SA_IDX_MSB 47 -#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 - -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 - -#define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 -#define RX_MSDU_END_MSDU_DROP_LSB 0 -#define RX_MSDU_END_MSDU_DROP_MSB 0 -#define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 - -#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e - -#define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FLOW_IDX_LSB 6 -#define RX_MSDU_END_FLOW_IDX_MSB 25 -#define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 - -#define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 -#define RX_MSDU_END_USE_PPE_LSB 26 -#define RX_MSDU_END_USE_PPE_MSB 26 -#define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 - -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 - -#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 - -#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 -#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 -#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 - -#define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FSE_METADATA_LSB 32 -#define RX_MSDU_END_FSE_METADATA_MSB 63 -#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CCE_METADATA_LSB 0 -#define RX_MSDU_END_CCE_METADATA_MSB 15 -#define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff - -#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 -#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 -#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 -#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 -#define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 -#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 - -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 - -#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FISA_TIMEOUT_LSB 41 -#define RX_MSDU_END_FISA_TIMEOUT_MSB 41 -#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 - -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 - -#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 - -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 - -#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 -#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 -#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 - -#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CCE_MATCH_LSB 46 -#define RX_MSDU_END_CCE_MATCH_MSB 46 -#define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 - -#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 - -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 - -#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 -#define RX_MSDU_END_KEY_ID_OCTET_LSB 0 -#define RX_MSDU_END_KEY_ID_OCTET_MSB 7 -#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff - -#define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_16A_LSB 8 -#define RX_MSDU_END_RESERVED_16A_MSB 31 -#define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 - -#define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_17A_LSB 32 -#define RX_MSDU_END_RESERVED_17A_MSB 37 -#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 - -#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 -#define RX_MSDU_END_SERVICE_CODE_LSB 38 -#define RX_MSDU_END_SERVICE_CODE_MSB 46 -#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 - -#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 -#define RX_MSDU_END_PRIORITY_VALID_LSB 47 -#define RX_MSDU_END_PRIORITY_VALID_MSB 47 -#define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 - -#define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 -#define RX_MSDU_END_INTRA_BSS_LSB 48 -#define RX_MSDU_END_INTRA_BSS_MSB 48 -#define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 - -#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 -#define RX_MSDU_END_DEST_CHIP_ID_LSB 49 -#define RX_MSDU_END_DEST_CHIP_ID_MSB 50 -#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 - -#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 -#define RX_MSDU_END_MULTICAST_ECHO_LSB 51 -#define RX_MSDU_END_MULTICAST_ECHO_MSB 51 -#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 - -#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 -#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 -#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 - -#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 -#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 -#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 - -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 - -#define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_17B_LSB 56 -#define RX_MSDU_END_RESERVED_17B_MSB 63 -#define RX_MSDU_END_RESERVED_17B_MASK 0xff00000000000000 - -#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MSDU_LENGTH_LSB 0 -#define RX_MSDU_END_MSDU_LENGTH_MSB 13 -#define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff - -#define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 -#define RX_MSDU_END_STBC_LSB 14 -#define RX_MSDU_END_STBC_MSB 14 -#define RX_MSDU_END_STBC_MASK 0x0000000000004000 - -#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPSEC_ESP_LSB 15 -#define RX_MSDU_END_IPSEC_ESP_MSB 15 -#define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 - -#define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 -#define RX_MSDU_END_L3_OFFSET_LSB 16 -#define RX_MSDU_END_L3_OFFSET_MSB 22 -#define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 - -#define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPSEC_AH_LSB 23 -#define RX_MSDU_END_IPSEC_AH_MSB 23 -#define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 - -#define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 -#define RX_MSDU_END_L4_OFFSET_LSB 24 -#define RX_MSDU_END_L4_OFFSET_MSB 31 -#define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 - -#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MSDU_NUMBER_LSB 32 -#define RX_MSDU_END_MSDU_NUMBER_MSB 39 -#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 - -#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 -#define RX_MSDU_END_DECAP_FORMAT_LSB 40 -#define RX_MSDU_END_DECAP_FORMAT_MSB 41 -#define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 - -#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPV4_PROTO_LSB 42 -#define RX_MSDU_END_IPV4_PROTO_MSB 42 -#define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 - -#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPV6_PROTO_LSB 43 -#define RX_MSDU_END_IPV6_PROTO_MSB 43 -#define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 - -#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_PROTO_LSB 44 -#define RX_MSDU_END_TCP_PROTO_MSB 44 -#define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 - -#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_UDP_PROTO_LSB 45 -#define RX_MSDU_END_UDP_PROTO_MSB 45 -#define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 - -#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_FRAG_LSB 46 -#define RX_MSDU_END_IP_FRAG_MSB 46 -#define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 - -#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 -#define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 -#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 - -#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 - -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 - -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 - -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 - -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 - -#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 - -#define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 -#define RX_MSDU_END_LDPC_LSB 55 -#define RX_MSDU_END_LDPC_MSB 55 -#define RX_MSDU_END_LDPC_MASK 0x0080000000000000 - -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 - -#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 -#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 -#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 -#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff - -#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 -#define RX_MSDU_END_VLAN_STAG_CI_LSB 16 -#define RX_MSDU_END_VLAN_STAG_CI_MSB 31 -#define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 -#define RX_MSDU_END_PEER_META_DATA_LSB 32 -#define RX_MSDU_END_PEER_META_DATA_MSB 63 -#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 -#define RX_MSDU_END_USER_RSSI_LSB 0 -#define RX_MSDU_END_USER_RSSI_MSB 7 -#define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff - -#define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 -#define RX_MSDU_END_PKT_TYPE_LSB 8 -#define RX_MSDU_END_PKT_TYPE_MSB 11 -#define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 - -#define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 -#define RX_MSDU_END_SGI_LSB 12 -#define RX_MSDU_END_SGI_MSB 13 -#define RX_MSDU_END_SGI_MASK 0x0000000000003000 - -#define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RATE_MCS_LSB 14 -#define RX_MSDU_END_RATE_MCS_MSB 18 -#define RX_MSDU_END_RATE_MCS_MASK 0x000000000007c000 - -#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 19 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 21 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x0000000000380000 - -#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RECEPTION_TYPE_LSB 22 -#define RX_MSDU_END_RECEPTION_TYPE_MSB 24 -#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000001c00000 - -#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 -#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 25 -#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 -#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007e000000 - -#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 -#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 -#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 -#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 - -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 - -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff - -#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 -#define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 -#define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 -#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 - -#define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 -#define RX_MSDU_END_RESERVED_28A_LSB 0 -#define RX_MSDU_END_RESERVED_28A_MSB 15 -#define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff - -#define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 -#define RX_MSDU_END_SA_15_0_LSB 16 -#define RX_MSDU_END_SA_15_0_MSB 31 -#define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 -#define RX_MSDU_END_SA_47_16_LSB 32 -#define RX_MSDU_END_SA_47_16_MSB 63 -#define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 - -#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 -#define RX_MSDU_END_FIRST_MPDU_LSB 0 -#define RX_MSDU_END_FIRST_MPDU_MSB 0 -#define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 - -#define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_30A_LSB 1 -#define RX_MSDU_END_RESERVED_30A_MSB 1 -#define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 - -#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MCAST_BCAST_LSB 2 -#define RX_MSDU_END_MCAST_BCAST_MSB 2 -#define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 - -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 - -#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 - -#define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_POWER_MGMT_LSB 5 -#define RX_MSDU_END_POWER_MGMT_MSB 5 -#define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 - -#define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 -#define RX_MSDU_END_NON_QOS_LSB 6 -#define RX_MSDU_END_NON_QOS_MSB 6 -#define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 - -#define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 -#define RX_MSDU_END_NULL_DATA_LSB 7 -#define RX_MSDU_END_NULL_DATA_MSB 7 -#define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 - -#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MGMT_TYPE_LSB 8 -#define RX_MSDU_END_MGMT_TYPE_MSB 8 -#define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 - -#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_CTRL_TYPE_LSB 9 -#define RX_MSDU_END_CTRL_TYPE_MSB 9 -#define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 - -#define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MORE_DATA_LSB 10 -#define RX_MSDU_END_MORE_DATA_MSB 10 -#define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 - -#define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 -#define RX_MSDU_END_EOSP_LSB 11 -#define RX_MSDU_END_EOSP_MSB 11 -#define RX_MSDU_END_EOSP_MASK 0x0000000000000800 - -#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_A_MSDU_ERROR_LSB 12 -#define RX_MSDU_END_A_MSDU_ERROR_MSB 12 -#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 - -#define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_30B_LSB 13 -#define RX_MSDU_END_RESERVED_30B_MSB 13 -#define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 - -#define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 -#define RX_MSDU_END_ORDER_LSB 14 -#define RX_MSDU_END_ORDER_MSB 14 -#define RX_MSDU_END_ORDER_MASK 0x0000000000004000 - -#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 -#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 -#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 - -#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_OVERFLOW_ERR_LSB 16 -#define RX_MSDU_END_OVERFLOW_ERR_MSB 16 -#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 - -#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 -#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 -#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 - -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 - -#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 -#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 -#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 -#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 - -#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 -#define RX_MSDU_END_SA_IDX_INVALID_LSB 20 -#define RX_MSDU_END_SA_IDX_INVALID_MSB 20 -#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 - -#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DA_IDX_INVALID_LSB 21 -#define RX_MSDU_END_DA_IDX_INVALID_MSB 21 -#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 - -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 - -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 - -#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 -#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 -#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 - -#define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DIRECTED_LSB 25 -#define RX_MSDU_END_DIRECTED_MSB 25 -#define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 - -#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 -#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 -#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 - -#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 -#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 -#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 - -#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 -#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 -#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 - -#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DECRYPT_ERR_LSB 29 -#define RX_MSDU_END_DECRYPT_ERR_MSB 29 -#define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 - -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 - -#define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_FCS_ERR_LSB 31 -#define RX_MSDU_END_FCS_ERR_MSB 31 -#define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 - -#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_31A_LSB 32 -#define RX_MSDU_END_RESERVED_31A_MSB 41 -#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 - -#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 - -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 - -#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_31B_LSB 46 -#define RX_MSDU_END_RESERVED_31B_MSB 62 -#define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000 - -#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MSDU_DONE_LSB 63 -#define RX_MSDU_END_MSDU_DONE_MSB 63 -#define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_ext_desc_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_msdu_ext_desc_info.h deleted file mode 100644 index 70bda69ddfec..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_ext_desc_info.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_EXT_DESC_INFO_H_ -#define _RX_MSDU_EXT_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 - -struct rx_msdu_ext_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reo_destination_indication : 5, - service_code : 9, - priority_valid : 1, - data_offset : 12, - src_link_id : 3, - reserved_0a : 2; -#else - uint32_t reserved_0a : 2, - src_link_id : 3, - data_offset : 12, - priority_valid : 1, - service_code : 9, - reo_destination_indication : 5; -#endif -}; - -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_link.h b/drivers/staging/fw-api/hw/fig/v1/rx_msdu_link.h deleted file mode 100644 index c54357dae2ef..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_link.h +++ /dev/null @@ -1,2051 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_LINK_H_ -#define _RX_MSDU_LINK_H_ - -#include "uniform_descriptor_header.h" -#include "buffer_addr_info.h" -#include "rx_msdu_details.h" -#define NUM_OF_DWORDS_RX_MSDU_LINK 64 - -struct rx_msdu_link { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct uniform_descriptor_header descriptor_header; - struct buffer_addr_info next_msdu_link_desc_addr_info; - uint32_t reserved_3a : 32; - struct rx_msdu_details msdu_0; - struct rx_msdu_details msdu_1; - struct rx_msdu_details msdu_2; - struct rx_msdu_details msdu_3; - struct rx_msdu_details msdu_4; - struct rx_msdu_details msdu_5; - struct rx_msdu_details msdu_6; - struct rx_msdu_details msdu_7; - struct rx_msdu_details msdu_8; - struct rx_msdu_details msdu_9; - struct rx_msdu_details msdu_10; - struct rx_msdu_details msdu_11; - struct rx_msdu_details msdu_12; - struct rx_msdu_details msdu_13; - struct rx_msdu_details msdu_14; -#else - struct uniform_descriptor_header descriptor_header; - struct buffer_addr_info next_msdu_link_desc_addr_info; - uint32_t reserved_3a : 32; - struct rx_msdu_details msdu_0; - struct rx_msdu_details msdu_1; - struct rx_msdu_details msdu_2; - struct rx_msdu_details msdu_3; - struct rx_msdu_details msdu_4; - struct rx_msdu_details msdu_5; - struct rx_msdu_details msdu_6; - struct rx_msdu_details msdu_7; - struct rx_msdu_details msdu_8; - struct rx_msdu_details msdu_9; - struct rx_msdu_details msdu_10; - struct rx_msdu_details msdu_11; - struct rx_msdu_details msdu_12; - struct rx_msdu_details msdu_13; - struct rx_msdu_details msdu_14; -#endif -}; - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c -#define RX_MSDU_LINK_RESERVED_3A_LSB 0 -#define RX_MSDU_LINK_RESERVED_3A_MSB 31 -#define RX_MSDU_LINK_RESERVED_3A_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000010 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000080 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000090 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000a0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000b0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000c0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000d0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000e0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000f0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_start.h b/drivers/staging/fw-api/hw/fig/v1/rx_msdu_start.h deleted file mode 100644 index e1e99c027c85..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_start.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_START_H_ -#define _RX_MSDU_START_H_ - -#define NUM_OF_DWORDS_RX_MSDU_START 10 - -#define NUM_OF_QWORDS_RX_MSDU_START 5 - -struct rx_msdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - rate_mcs : 5, - reserved_0 : 2, - phy_ppdu_id : 16; - uint32_t msdu_length : 14, - stbc : 1, - ipsec_esp : 1, - l3_offset : 7, - ipsec_ah : 1, - l4_offset : 8; - uint32_t msdu_number : 8, - decap_format : 2, - ipv4_proto : 1, - ipv6_proto : 1, - tcp_proto : 1, - udp_proto : 1, - ip_frag : 1, - tcp_only_ack : 1, - da_is_bcast_mcast : 1, - toeplitz_hash_sel : 2, - ip_fixed_header_valid : 1, - ip_extn_header_valid : 1, - tcp_udp_header_valid : 1, - mesh_control_present : 1, - ldpc : 1, - ip4_protocol_ip6_next_header : 8; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t flow_id_toeplitz : 32; - uint32_t user_rssi : 8, - pkt_type : 4, - sgi : 2, - reserved_5a : 4, - receive_bandwidth : 3, - reception_type : 3, - mimo_ss_bitmap : 8; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t vlan_ctag_ci : 16, - vlan_stag_ci : 16; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 2, - rate_mcs : 5, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t l4_offset : 8, - ipsec_ah : 1, - l3_offset : 7, - ipsec_esp : 1, - stbc : 1, - msdu_length : 14; - uint32_t ip4_protocol_ip6_next_header : 8, - ldpc : 1, - mesh_control_present : 1, - tcp_udp_header_valid : 1, - ip_extn_header_valid : 1, - ip_fixed_header_valid : 1, - toeplitz_hash_sel : 2, - da_is_bcast_mcast : 1, - tcp_only_ack : 1, - ip_frag : 1, - udp_proto : 1, - tcp_proto : 1, - ipv6_proto : 1, - ipv4_proto : 1, - decap_format : 2, - msdu_number : 8; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t flow_id_toeplitz : 32; - uint32_t mimo_ss_bitmap : 8, - reception_type : 3, - receive_bandwidth : 3, - reserved_5a : 4, - sgi : 2, - pkt_type : 4, - user_rssi : 8; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t vlan_stag_ci : 16, - vlan_ctag_ci : 16; -#endif -}; - -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MSDU_START_RATE_MCS_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RATE_MCS_LSB 9 -#define RX_MSDU_START_RATE_MCS_MSB 13 -#define RX_MSDU_START_RATE_MCS_MASK 0x0000000000003e00 - -#define RX_MSDU_START_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RESERVED_0_LSB 14 -#define RX_MSDU_START_RESERVED_0_MSB 15 -#define RX_MSDU_START_RESERVED_0_MASK 0x000000000000c000 - -#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_START_PHY_PPDU_ID_LSB 16 -#define RX_MSDU_START_PHY_PPDU_ID_MSB 31 -#define RX_MSDU_START_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x0000000000000000 -#define RX_MSDU_START_MSDU_LENGTH_LSB 32 -#define RX_MSDU_START_MSDU_LENGTH_MSB 45 -#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff00000000 - -#define RX_MSDU_START_STBC_OFFSET 0x0000000000000000 -#define RX_MSDU_START_STBC_LSB 46 -#define RX_MSDU_START_STBC_MSB 46 -#define RX_MSDU_START_STBC_MASK 0x0000400000000000 - -#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x0000000000000000 -#define RX_MSDU_START_IPSEC_ESP_LSB 47 -#define RX_MSDU_START_IPSEC_ESP_MSB 47 -#define RX_MSDU_START_IPSEC_ESP_MASK 0x0000800000000000 - -#define RX_MSDU_START_L3_OFFSET_OFFSET 0x0000000000000000 -#define RX_MSDU_START_L3_OFFSET_LSB 48 -#define RX_MSDU_START_L3_OFFSET_MSB 54 -#define RX_MSDU_START_L3_OFFSET_MASK 0x007f000000000000 - -#define RX_MSDU_START_IPSEC_AH_OFFSET 0x0000000000000000 -#define RX_MSDU_START_IPSEC_AH_LSB 55 -#define RX_MSDU_START_IPSEC_AH_MSB 55 -#define RX_MSDU_START_IPSEC_AH_MASK 0x0080000000000000 - -#define RX_MSDU_START_L4_OFFSET_OFFSET 0x0000000000000000 -#define RX_MSDU_START_L4_OFFSET_LSB 56 -#define RX_MSDU_START_L4_OFFSET_MSB 63 -#define RX_MSDU_START_L4_OFFSET_MASK 0xff00000000000000 - -#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x0000000000000008 -#define RX_MSDU_START_MSDU_NUMBER_LSB 0 -#define RX_MSDU_START_MSDU_NUMBER_MSB 7 -#define RX_MSDU_START_MSDU_NUMBER_MASK 0x00000000000000ff - -#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x0000000000000008 -#define RX_MSDU_START_DECAP_FORMAT_LSB 8 -#define RX_MSDU_START_DECAP_FORMAT_MSB 9 -#define RX_MSDU_START_DECAP_FORMAT_MASK 0x0000000000000300 - -#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IPV4_PROTO_LSB 10 -#define RX_MSDU_START_IPV4_PROTO_MSB 10 -#define RX_MSDU_START_IPV4_PROTO_MASK 0x0000000000000400 - -#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IPV6_PROTO_LSB 11 -#define RX_MSDU_START_IPV6_PROTO_MSB 11 -#define RX_MSDU_START_IPV6_PROTO_MASK 0x0000000000000800 - -#define RX_MSDU_START_TCP_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_PROTO_LSB 12 -#define RX_MSDU_START_TCP_PROTO_MSB 12 -#define RX_MSDU_START_TCP_PROTO_MASK 0x0000000000001000 - -#define RX_MSDU_START_UDP_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_UDP_PROTO_LSB 13 -#define RX_MSDU_START_UDP_PROTO_MSB 13 -#define RX_MSDU_START_UDP_PROTO_MASK 0x0000000000002000 - -#define RX_MSDU_START_IP_FRAG_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_FRAG_LSB 14 -#define RX_MSDU_START_IP_FRAG_MSB 14 -#define RX_MSDU_START_IP_FRAG_MASK 0x0000000000004000 - -#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 -#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 -#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x0000000000008000 - -#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000008 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x0000000000010000 - -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x0000000000060000 - -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x0000000000080000 - -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x0000000000100000 - -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x0000000000200000 - -#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000008 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x0000000000400000 - -#define RX_MSDU_START_LDPC_OFFSET 0x0000000000000008 -#define RX_MSDU_START_LDPC_LSB 23 -#define RX_MSDU_START_LDPC_MSB 23 -#define RX_MSDU_START_LDPC_MASK 0x0000000000800000 - -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00000000ff000000 - -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 32 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 63 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 - -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000010 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0x00000000ffffffff - -#define RX_MSDU_START_USER_RSSI_OFFSET 0x0000000000000010 -#define RX_MSDU_START_USER_RSSI_LSB 32 -#define RX_MSDU_START_USER_RSSI_MSB 39 -#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff00000000 - -#define RX_MSDU_START_PKT_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_START_PKT_TYPE_LSB 40 -#define RX_MSDU_START_PKT_TYPE_MSB 43 -#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f0000000000 - -#define RX_MSDU_START_SGI_OFFSET 0x0000000000000010 -#define RX_MSDU_START_SGI_LSB 44 -#define RX_MSDU_START_SGI_MSB 45 -#define RX_MSDU_START_SGI_MASK 0x0000300000000000 - -#define RX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RESERVED_5A_LSB 46 -#define RX_MSDU_START_RESERVED_5A_MSB 49 -#define RX_MSDU_START_RESERVED_5A_MASK 0x0003c00000000000 - -#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 50 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 52 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c000000000000 - -#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RECEPTION_TYPE_LSB 53 -#define RX_MSDU_START_RECEPTION_TYPE_MSB 55 -#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e0000000000000 - -#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x0000000000000010 -#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 56 -#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 63 -#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff00000000000000 - -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000018 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000018 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 - -#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000020 -#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 -#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 -#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0x00000000ffffffff - -#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x0000000000000020 -#define RX_MSDU_START_VLAN_CTAG_CI_LSB 32 -#define RX_MSDU_START_VLAN_CTAG_CI_MSB 47 -#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff00000000 - -#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x0000000000000020 -#define RX_MSDU_START_VLAN_STAG_CI_LSB 48 -#define RX_MSDU_START_VLAN_STAG_CI_MSB 63 -#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_ack_report.h b/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_ack_report.h deleted file mode 100644 index 345b14ea4255..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_ack_report.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_ACK_REPORT_H_ -#define _RX_PPDU_ACK_REPORT_H_ - -#include "ack_report.h" -#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2 - -#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1 - -struct rx_ppdu_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ack_report ack_report_details; - uint32_t tlv64_padding : 32; -#else - struct ack_report ack_report_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x000000000000000f - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000000f0 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x0000000000000100 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x000000000000fe00 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 - -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB 32 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB 63 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_end_user_stats.h deleted file mode 100644 index 51db8f35a6ab..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_end_user_stats.h +++ /dev/null @@ -1,679 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_END_USER_STATS_H_ -#define _RX_PPDU_END_USER_STATS_H_ - -#include "rx_rxpcu_classification_overview.h" -#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 - -#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15 - -struct rx_ppdu_end_user_stats { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t sta_full_aid : 13, - mcs : 5, - nss : 3, - expected_response_ack_or_ba : 1, - reserved_1a : 10; - uint32_t sw_peer_id : 16, - mpdu_cnt_fcs_err : 11, - sw2rxdma0_buf_source_used : 1, - fw2rxdma0_buf_source_used : 1, - sw2rxdma1_buf_source_used : 1, - sw2rxdma2_buf_source_used : 1, - fw2rxdma1_buf_source_used : 1; - uint32_t mpdu_cnt_fcs_ok : 11, - frame_control_info_valid : 1, - qos_control_info_valid : 1, - ht_control_info_valid : 1, - data_sequence_control_info_valid : 1, - ht_control_info_null_valid : 1, - rxdma2fw0_ring_used : 1, - rxdma2fw1_ring_used : 1, - rxdma2fwreo_0_ring_used : 1, - rxdma2fwreo_1_ring_used : 1, - reserved_3a : 1, - ht_control_field_pkt_type : 4, - reserved_3b : 7; - uint32_t ast_index : 16, - frame_control_field : 16; - uint32_t first_data_seq_ctrl : 16, - qos_control_field : 16; - uint32_t ht_control_field : 32; - uint32_t fcs_ok_bitmap_31_0 : 32; - uint32_t fcs_ok_bitmap_63_32 : 32; - uint32_t udp_msdu_count : 16, - tcp_msdu_count : 16; - uint32_t other_msdu_count : 16, - tcp_ack_msdu_count : 16; - uint32_t sw_response_reference_ptr : 32; - uint32_t received_qos_data_tid_bitmap : 16, - received_qos_data_tid_eosp_bitmap : 16; - uint32_t qosctrl_15_8_tid0 : 8, - qosctrl_15_8_tid1 : 8, - qosctrl_15_8_tid2 : 8, - qosctrl_15_8_tid3 : 8; - uint32_t qosctrl_15_8_tid4 : 8, - qosctrl_15_8_tid5 : 8, - qosctrl_15_8_tid6 : 8, - qosctrl_15_8_tid7 : 8; - uint32_t qosctrl_15_8_tid8 : 8, - qosctrl_15_8_tid9 : 8, - qosctrl_15_8_tid10 : 8, - qosctrl_15_8_tid11 : 8; - uint32_t qosctrl_15_8_tid12 : 8, - qosctrl_15_8_tid13 : 8, - qosctrl_15_8_tid14 : 8, - qosctrl_15_8_tid15 : 8; - uint32_t mpdu_ok_byte_count : 25, - ampdu_delim_ok_count_6_0 : 7; - uint32_t ampdu_delim_err_count : 25, - ampdu_delim_ok_count_13_7 : 7; - uint32_t mpdu_err_byte_count : 25, - ampdu_delim_ok_count_20_14 : 7; - uint32_t non_consecutive_delimiter_err : 16, - retried_msdu_count : 16; - uint32_t ht_control_null_field : 32; - uint32_t sw_response_reference_ptr_ext : 32; - uint32_t corrupted_due_to_fifo_delay : 1, - frame_control_info_null_valid : 1, - frame_control_field_null : 16, - retried_mpdu_count : 11, - reserved_23a : 3; - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_24a : 4, - frame_control_info_mgmt_ctrl_valid : 1, - mac_addr_ad2_valid : 1, - mcast_bcast : 1, - frame_control_field_mgmt_ctrl : 16; - uint32_t user_ppdu_len : 24, - reserved_25a : 8; - uint32_t mac_addr_ad2_31_0 : 32; - uint32_t mac_addr_ad2_47_32 : 16, - amsdu_msdu_count : 16; - uint32_t non_amsdu_msdu_count : 16, - ucast_msdu_count : 16; - uint32_t bcast_msdu_count : 16, - mcast_bcast_msdu_count : 16; -#else - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t reserved_1a : 10, - expected_response_ack_or_ba : 1, - nss : 3, - mcs : 5, - sta_full_aid : 13; - uint32_t fw2rxdma1_buf_source_used : 1, - sw2rxdma2_buf_source_used : 1, - sw2rxdma1_buf_source_used : 1, - fw2rxdma0_buf_source_used : 1, - sw2rxdma0_buf_source_used : 1, - mpdu_cnt_fcs_err : 11, - sw_peer_id : 16; - uint32_t reserved_3b : 7, - ht_control_field_pkt_type : 4, - reserved_3a : 1, - rxdma2fwreo_1_ring_used : 1, - rxdma2fwreo_0_ring_used : 1, - rxdma2fw1_ring_used : 1, - rxdma2fw0_ring_used : 1, - ht_control_info_null_valid : 1, - data_sequence_control_info_valid : 1, - ht_control_info_valid : 1, - qos_control_info_valid : 1, - frame_control_info_valid : 1, - mpdu_cnt_fcs_ok : 11; - uint32_t frame_control_field : 16, - ast_index : 16; - uint32_t qos_control_field : 16, - first_data_seq_ctrl : 16; - uint32_t ht_control_field : 32; - uint32_t fcs_ok_bitmap_31_0 : 32; - uint32_t fcs_ok_bitmap_63_32 : 32; - uint32_t tcp_msdu_count : 16, - udp_msdu_count : 16; - uint32_t tcp_ack_msdu_count : 16, - other_msdu_count : 16; - uint32_t sw_response_reference_ptr : 32; - uint32_t received_qos_data_tid_eosp_bitmap : 16, - received_qos_data_tid_bitmap : 16; - uint32_t qosctrl_15_8_tid3 : 8, - qosctrl_15_8_tid2 : 8, - qosctrl_15_8_tid1 : 8, - qosctrl_15_8_tid0 : 8; - uint32_t qosctrl_15_8_tid7 : 8, - qosctrl_15_8_tid6 : 8, - qosctrl_15_8_tid5 : 8, - qosctrl_15_8_tid4 : 8; - uint32_t qosctrl_15_8_tid11 : 8, - qosctrl_15_8_tid10 : 8, - qosctrl_15_8_tid9 : 8, - qosctrl_15_8_tid8 : 8; - uint32_t qosctrl_15_8_tid15 : 8, - qosctrl_15_8_tid14 : 8, - qosctrl_15_8_tid13 : 8, - qosctrl_15_8_tid12 : 8; - uint32_t ampdu_delim_ok_count_6_0 : 7, - mpdu_ok_byte_count : 25; - uint32_t ampdu_delim_ok_count_13_7 : 7, - ampdu_delim_err_count : 25; - uint32_t ampdu_delim_ok_count_20_14 : 7, - mpdu_err_byte_count : 25; - uint32_t retried_msdu_count : 16, - non_consecutive_delimiter_err : 16; - uint32_t ht_control_null_field : 32; - uint32_t sw_response_reference_ptr_ext : 32; - uint32_t reserved_23a : 3, - retried_mpdu_count : 11, - frame_control_field_null : 16, - frame_control_info_null_valid : 1, - corrupted_due_to_fifo_delay : 1; - uint32_t frame_control_field_mgmt_ctrl : 16, - mcast_bcast : 1, - mac_addr_ad2_valid : 1, - frame_control_info_mgmt_ctrl_valid : 1, - reserved_24a : 4, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_25a : 8, - user_ppdu_len : 24; - uint32_t mac_addr_ad2_31_0 : 32; - uint32_t amsdu_msdu_count : 16, - mac_addr_ad2_47_32 : 16; - uint32_t ucast_msdu_count : 16, - non_amsdu_msdu_count : 16; - uint32_t mcast_bcast_msdu_count : 16, - bcast_msdu_count : 16; -#endif -}; - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 - -#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_MCS_LSB 45 -#define RX_PPDU_END_USER_STATS_MCS_MSB 49 -#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0003e00000000000 - -#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_NSS_LSB 50 -#define RX_PPDU_END_USER_STATS_NSS_MSB 52 -#define RX_PPDU_END_USER_STATS_NSS_MASK 0x001c000000000000 - -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 53 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 53 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0020000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 54 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffc0000000000000 - -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 - -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_LSB 28 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MSB 28 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000010000000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_LSB 30 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MSB 30 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MASK 0x0000000040000000 - -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_LSB 31 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MSB 31 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000080000000 - -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 - -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 - -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_LSB 48 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MSB 48 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MASK 0x0001000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_LSB 49 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MSB 49 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MASK 0x0002000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_LSB 50 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MSB 50 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MASK 0x0004000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_LSB 51 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MSB 51 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MASK 0x0008000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_LSB 52 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_MSB 52 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_MASK 0x0010000000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 57 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 -#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 -#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 - -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 - -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 - -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 - -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x0000000000001e00 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x0000000000002000 - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x0000000000004000 - -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x0000000000008000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 32 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 55 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff00000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 56 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 32 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 47 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 47 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_end_user_stats_ext.h deleted file mode 100644 index 0a11202db481..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_end_user_stats_ext.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ -#define _RX_PPDU_END_USER_STATS_EXT_H_ - -#include "rx_rxpcu_classification_overview.h" -#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 - -#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4 - -struct rx_ppdu_end_user_stats_ext { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t fcs_ok_bitmap_95_64 : 32; - uint32_t fcs_ok_bitmap_127_96 : 32; - uint32_t fcs_ok_bitmap_159_128 : 32; - uint32_t fcs_ok_bitmap_191_160 : 32; - uint32_t fcs_ok_bitmap_223_192 : 32; - uint32_t fcs_ok_bitmap_255_224 : 32; - uint32_t corrupted_due_to_fifo_delay : 1, - reserved_7a : 31; -#else - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t fcs_ok_bitmap_95_64 : 32; - uint32_t fcs_ok_bitmap_127_96 : 32; - uint32_t fcs_ok_bitmap_159_128 : 32; - uint32_t fcs_ok_bitmap_191_160 : 32; - uint32_t fcs_ok_bitmap_223_192 : 32; - uint32_t fcs_ok_bitmap_255_224 : 32; - uint32_t reserved_7a : 31, - corrupted_due_to_fifo_delay : 1; -#endif -}; - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 - -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 33 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_no_ack_report.h b/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_no_ack_report.h deleted file mode 100644 index d9c54c04df32..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_no_ack_report.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_NO_ACK_REPORT_H_ -#define _RX_PPDU_NO_ACK_REPORT_H_ - -#include "no_ack_report.h" -#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 - -#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2 - -struct rx_ppdu_no_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct no_ack_report no_ack_report_details; -#else - struct no_ack_report no_ack_report_details; -#endif -}; - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x000000000000000f - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000f0 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000000000ff00 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 32 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 55 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff00000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 56 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 56 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x0100000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 61 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 63 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0x00000000ff000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 44 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 63 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff00000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_start.h b/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_start.h deleted file mode 100644 index 19765eb4409b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_start.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_START_H_ -#define _RX_PPDU_START_H_ - -#define NUM_OF_DWORDS_RX_PPDU_START 6 - -#define NUM_OF_QWORDS_RX_PPDU_START 3 - -struct rx_ppdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - preamble_time_to_rxframe : 8, - reserved_0a : 8; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t rxframe_assert_timestamp : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 8, - preamble_time_to_rxframe : 8, - phy_ppdu_id : 16; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t rxframe_assert_timestamp : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_START_PHY_PPDU_ID_LSB 0 -#define RX_PPDU_START_PHY_PPDU_ID_MSB 15 -#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 - -#define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_PPDU_START_RESERVED_0A_LSB 24 -#define RX_PPDU_START_RESERVED_0A_MSB 31 -#define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 - -#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 -#define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 -#define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 -#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 - -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 - -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff - -#define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 -#define RX_PPDU_START_TLV64_PADDING_LSB 32 -#define RX_PPDU_START_TLV64_PADDING_MSB 63 -#define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_start_user_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_start_user_info.h deleted file mode 100644 index e0caf9b2ac24..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_start_user_info.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_START_USER_INFO_H_ -#define _RX_PPDU_START_USER_INFO_H_ - -#include "receive_user_info.h" -#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8 - -#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 4 - -struct rx_ppdu_start_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_user_info receive_user_info_details; -#else - struct receive_user_info receive_user_info_details; -#endif -}; - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 36 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000001f00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 37 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 38 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000006000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 1 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x0000000000000002 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB 2 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB 3 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK 0x000000000000000c - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB 4 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB 5 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK 0x0000000000000030 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB 6 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB 7 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK 0x00000000000000c0 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_preamble.h b/drivers/staging/fw-api/hw/fig/v1/rx_preamble.h deleted file mode 100644 index 807463753865..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_preamble.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PREAMBLE_H_ -#define _RX_PREAMBLE_H_ - -#define NUM_OF_DWORDS_RX_PREAMBLE 2 - -#define NUM_OF_QWORDS_RX_PREAMBLE 1 - -struct rx_preamble { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t num_users : 6, - pkt_type : 4, - direction : 1, - reserved_0a : 21; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 21, - direction : 1, - pkt_type : 4, - num_users : 6; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PREAMBLE_NUM_USERS_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_NUM_USERS_LSB 0 -#define RX_PREAMBLE_NUM_USERS_MSB 5 -#define RX_PREAMBLE_NUM_USERS_MASK 0x000000000000003f - -#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_PKT_TYPE_LSB 6 -#define RX_PREAMBLE_PKT_TYPE_MSB 9 -#define RX_PREAMBLE_PKT_TYPE_MASK 0x00000000000003c0 - -#define RX_PREAMBLE_DIRECTION_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_DIRECTION_LSB 10 -#define RX_PREAMBLE_DIRECTION_MSB 10 -#define RX_PREAMBLE_DIRECTION_MASK 0x0000000000000400 - -#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_RESERVED_0A_LSB 11 -#define RX_PREAMBLE_RESERVED_0A_MSB 31 -#define RX_PREAMBLE_RESERVED_0A_MASK 0x00000000fffff800 - -#define RX_PREAMBLE_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_TLV64_PADDING_LSB 32 -#define RX_PREAMBLE_TLV64_PADDING_MSB 63 -#define RX_PREAMBLE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_response_required_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_response_required_info.h deleted file mode 100644 index 9d5364537a1c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_response_required_info.h +++ /dev/null @@ -1,750 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ -#define _RX_RESPONSE_REQUIRED_INFO_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 - -#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 - -struct rx_response_required_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - su_or_uplink_mu_reception : 1, - trigger_frame_received : 1, - __reserved_g_0012 : 2, - tb___reserved_g_0022_response_required : 2, - mac_security : 1, - filter_pass_monitor_ovrd : 1, - ast_search_incomplete : 1, - r2r_end_status_to_follow : 1, - __reserved_g_0016_listen_cca_check_at_phy_desc : 1, - __reserved_g_0016_listen_indication : 1, - three_or_more_type_subtypes : 1, - wait_sifs_config_valid : 1, - wait_sifs : 2; - uint32_t general_frame_control : 16, - second_frame_control : 16; - uint32_t duration : 16, - pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5, - sgi : 2, - stbc : 1, - ldpc : 1, - ampdu : 1, - rts_ta_grp_bit : 1; - uint32_t ctrl_frame_soliciting_resp : 1, - ast_fail_for_dot11ax_su_ext : 1, - service_dynamic : 1, - m_pkt : 1, - sta_partial_aid : 12, - group_id : 6, - ctrl_resp_pwr_mgmt : 1, - response_indication : 2, - ndp_indication : 1, - ndp_frame_type : 3, - second_frame_control_valid : 1, - ack_ba_resp_more_data : 1, - vht_ack : 1; - uint32_t sta_aid : 11, - interference : 1, - ects_as_tb_ppdu : 1, - reserved_4a : 3, - ack_id_ext : 10, - agc_cbw : 3, - service_cbw : 3; - uint32_t response_sta_count : 7, - __reserved_g_0035 : 1, - blackout_details_en : 1, - reserved : 2, - ht_vht_sig_cbw : 3, - cts_cbw : 3, - response_ack_count : 7, - response_assoc_ack_count : 7, - txop_duration_all_ones : 1; - uint32_t response_ba32_count : 7, - response_ba64_count : 7, - response_ba128_count : 7, - response_ba256_count : 7, - multi_tid : 1, - sw_response_tlv_from_crypto : 1, - dot11ax_dl_ul_flag : 1, - emlsr_main_tlv_if : 1; - uint32_t sw_response_frame_length : 16, - response_ba512_count : 7, - response_ba1024_count : 7, - reserved_7a : 2; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t dot11ax_received_format_indication : 1, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_bss_color_id : 6, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_cp_size : 2, - dot11ax_received_ltf_size : 2, - dot11ax_received_coding : 1, - dot11ax_received_dcm : 1, - dot11ax_received_doppler_indication : 1, - dot11ax_received_ext_ru_size : 4, - ftm_fields_valid : 1, - ftm_pe_nss : 3, - ftm_pe_ltf_size : 2, - ftm_pe_content : 1, - ftm_chain_csd_en : 1, - ftm_pe_chain_csd_en : 1; - uint32_t dot11ax_response_rate_source : 8, - dot11ax_ext_response_rate_source : 8, - sw_peer_id : 16; - uint32_t dot11be_puncture_bitmap : 16, - dot11be_response : 1, - punctured_response : 1, - eht_duplicate_mode : 2, - force_extra_symbol : 1, - ctrl_pkt_protect : 1, - mac_hdr_protect : 1, - reserved_13a : 3, - u_sig_puncture_pattern_encoding : 6; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t he_a_control_response_time : 12, - reserved_after_struct16 : 4; - uint32_t dso_primary20_index_select : 4, - dso_freq_subband_channel_bonding_mask : 16, - pad_duration : 5, - reserved_15a : 7; -#else - uint32_t wait_sifs : 2, - wait_sifs_config_valid : 1, - three_or_more_type_subtypes : 1, - __reserved_g_0016_listen_indication : 1, - __reserved_g_0016_listen_cca_check_at_phy_desc : 1, - r2r_end_status_to_follow : 1, - ast_search_incomplete : 1, - filter_pass_monitor_ovrd : 1, - mac_security : 1, - tb___reserved_g_0022_response_required : 2, - __reserved_g_0012 : 2, - trigger_frame_received : 1, - su_or_uplink_mu_reception : 1, - phy_ppdu_id : 16; - uint32_t second_frame_control : 16, - general_frame_control : 16; - uint32_t rts_ta_grp_bit : 1, - ampdu : 1, - ldpc : 1, - stbc : 1, - sgi : 2, - rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4, - duration : 16; - uint32_t vht_ack : 1, - ack_ba_resp_more_data : 1, - second_frame_control_valid : 1, - ndp_frame_type : 3, - ndp_indication : 1, - response_indication : 2, - ctrl_resp_pwr_mgmt : 1, - group_id : 6, - sta_partial_aid : 12, - m_pkt : 1, - service_dynamic : 1, - ast_fail_for_dot11ax_su_ext : 1, - ctrl_frame_soliciting_resp : 1; - uint32_t service_cbw : 3, - agc_cbw : 3, - ack_id_ext : 10, - reserved_4a : 3, - ects_as_tb_ppdu : 1, - interference : 1, - sta_aid : 11; - uint32_t txop_duration_all_ones : 1, - response_assoc_ack_count : 7, - response_ack_count : 7, - cts_cbw : 3, - ht_vht_sig_cbw : 3, - reserved : 2, - blackout_details_en : 1, - __reserved_g_0035 : 1, - response_sta_count : 7; - uint32_t emlsr_main_tlv_if : 1, - dot11ax_dl_ul_flag : 1, - sw_response_tlv_from_crypto : 1, - multi_tid : 1, - response_ba256_count : 7, - response_ba128_count : 7, - response_ba64_count : 7, - response_ba32_count : 7; - uint32_t reserved_7a : 2, - response_ba1024_count : 7, - response_ba512_count : 7, - sw_response_frame_length : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ftm_pe_chain_csd_en : 1, - ftm_chain_csd_en : 1, - ftm_pe_content : 1, - ftm_pe_ltf_size : 2, - ftm_pe_nss : 3, - ftm_fields_valid : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_received_doppler_indication : 1, - dot11ax_received_dcm : 1, - dot11ax_received_coding : 1, - dot11ax_received_ltf_size : 2, - dot11ax_received_cp_size : 2, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_bss_color_id : 6, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_format_indication : 1; - uint32_t sw_peer_id : 16, - dot11ax_ext_response_rate_source : 8, - dot11ax_response_rate_source : 8; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_13a : 3, - mac_hdr_protect : 1, - ctrl_pkt_protect : 1, - force_extra_symbol : 1, - eht_duplicate_mode : 2, - punctured_response : 1, - dot11be_response : 1, - dot11be_puncture_bitmap : 16; - uint32_t reserved_after_struct16 : 4, - he_a_control_response_time : 12; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint32_t reserved_15a : 7, - pad_duration : 5, - dso_freq_subband_channel_bonding_mask : 16, - dso_primary20_index_select : 4; -#endif -}; - -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 - -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 - -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 - -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 - -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 - -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 - -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 - -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff - -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 - -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000003e00000 - -#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 26 -#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x000000000c000000 - -#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 30 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000040000000 - -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 - -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 - -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 - -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 - -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 - -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK 0x4000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MSB 10 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MASK 0x00000000000007ff - -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_LSB 11 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MSB 11 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MASK 0x0000000000000800 - -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_LSB 12 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MSB 12 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MASK 0x0000000000001000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_LSB 13 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MASK 0x000000000000e000 - -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 - -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 - -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 - -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_LSB 40 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MSB 40 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MASK 0x0000010000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 41 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000060000000000 - -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 - -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 - -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB 31 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK 0x0000000080000000 - -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 - -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_LSB 53 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MSB 53 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MASK 0x0020000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_LSB 54 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MASK 0x0040000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x0380000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 - -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MSB 35 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MASK 0x0000000f00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 36 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 51 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000ffff000000000 - -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_LSB 52 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MSB 56 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MASK 0x01f0000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_LSB 57 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MASK 0xfe00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/fig/v1/rx_rxpcu_classification_overview.h deleted file mode 100644 index 92489a5f5b2d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_rxpcu_classification_overview.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ -#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ - -#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 - -struct rx_rxpcu_classification_overview { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t filter_pass_mpdus : 1, - filter_pass_mpdus_fcs_ok : 1, - monitor_direct_mpdus : 1, - monitor_direct_mpdus_fcs_ok : 1, - monitor_other_mpdus : 1, - monitor_other_mpdus_fcs_ok : 1, - phyrx_abort_received : 1, - filter_pass_monitor_ovrd_mpdus : 1, - filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, - reserved_0 : 7, - phy_ppdu_id : 16; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, - filter_pass_monitor_ovrd_mpdus : 1, - phyrx_abort_received : 1, - monitor_other_mpdus_fcs_ok : 1, - monitor_other_mpdus : 1, - monitor_direct_mpdus_fcs_ok : 1, - monitor_direct_mpdus : 1, - filter_pass_mpdus_fcs_ok : 1, - filter_pass_mpdus : 1; -#endif -}; - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_start_param.h b/drivers/staging/fw-api/hw/fig/v1/rx_start_param.h deleted file mode 100644 index bb2b87e3cc97..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_start_param.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_START_PARAM_H_ -#define _RX_START_PARAM_H_ - -#define NUM_OF_DWORDS_RX_START_PARAM 2 - -#define NUM_OF_QWORDS_RX_START_PARAM 1 - -struct rx_start_param { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pkt_type : 4, - reserved_0a : 12, - remaining_rx_time : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t remaining_rx_time : 16, - reserved_0a : 12, - pkt_type : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_START_PARAM_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_START_PARAM_PKT_TYPE_LSB 0 -#define RX_START_PARAM_PKT_TYPE_MSB 3 -#define RX_START_PARAM_PKT_TYPE_MASK 0x000000000000000f - -#define RX_START_PARAM_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_START_PARAM_RESERVED_0A_LSB 4 -#define RX_START_PARAM_RESERVED_0A_MSB 15 -#define RX_START_PARAM_RESERVED_0A_MASK 0x000000000000fff0 - -#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x0000000000000000 -#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 -#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 -#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0x00000000ffff0000 - -#define RX_START_PARAM_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_START_PARAM_TLV64_PADDING_LSB 32 -#define RX_START_PARAM_TLV64_PADDING_MSB 63 -#define RX_START_PARAM_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_timing_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_timing_info.h deleted file mode 100644 index ea6780e25c55..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_timing_info.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_TIMING_INFO_H_ -#define _RX_TIMING_INFO_H_ - -#define NUM_OF_DWORDS_RX_TIMING_INFO 5 - -struct rx_timing_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_timestamp_1_lower_32 : 32; - uint32_t phy_timestamp_1_upper_32 : 32; - uint32_t phy_timestamp_2_lower_32 : 32; - uint32_t phy_timestamp_2_upper_32 : 32; - uint32_t residual_phase_offset : 12, - sub_usec_ts_rx_end : 10, - reserved : 10; -#else - uint32_t phy_timestamp_1_lower_32 : 32; - uint32_t phy_timestamp_1_upper_32 : 32; - uint32_t phy_timestamp_2_lower_32 : 32; - uint32_t phy_timestamp_2_upper_32 : 32; - uint32_t reserved : 10, - sub_usec_ts_rx_end : 10, - residual_phase_offset : 12; -#endif -}; - -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000000 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000004 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x00000008 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000c -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000010 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB 0 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB 11 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff - -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_OFFSET 0x00000010 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_LSB 12 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MSB 21 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MASK 0x003ff000 - -#define RX_TIMING_INFO_RESERVED_OFFSET 0x00000010 -#define RX_TIMING_INFO_RESERVED_LSB 22 -#define RX_TIMING_INFO_RESERVED_MSB 31 -#define RX_TIMING_INFO_RESERVED_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_trig_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_trig_info.h deleted file mode 100644 index b6b074118bea..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_trig_info.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_TRIG_INFO_H_ -#define _RX_TRIG_INFO_H_ - -#define NUM_OF_DWORDS_RX_TRIG_INFO 2 - -#define NUM_OF_QWORDS_RX_TRIG_INFO 1 - -struct rx_trig_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_trigger_frame_type : 2, - trigger_resp_type : 3, - reserved_0 : 27; - uint32_t ppdu_duration : 16, - unique_destination_id : 16; -#else - uint32_t reserved_0 : 27, - trigger_resp_type : 3, - rx_trigger_frame_type : 2; - uint32_t unique_destination_id : 16, - ppdu_duration : 16; -#endif -}; - -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003 - -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c - -#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_RESERVED_0_LSB 5 -#define RX_TRIG_INFO_RESERVED_0_MSB 31 -#define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0 - -#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_PPDU_DURATION_LSB 32 -#define RX_TRIG_INFO_PPDU_DURATION_MSB 47 -#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000 - -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rxpcu_early_rx_indication.h b/drivers/staging/fw-api/hw/fig/v1/rxpcu_early_rx_indication.h deleted file mode 100644 index d2dc464cf1cf..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rxpcu_early_rx_indication.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_EARLY_RX_INDICATION_H_ -#define _RXPCU_EARLY_RX_INDICATION_H_ - -#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2 - -#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1 - -struct rxpcu_early_rx_indication { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5, - dot11ax_received_ext_ru_size : 4, - reserved_0a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 18, - dot11ax_received_ext_ru_size : 4, - rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x000000000000000f - -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x0000000000000010 - -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 9 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x00000000000003e0 - -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 10 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 13 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0000000000003c00 - -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 14 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0x00000000ffffc000 - -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB 32 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB 63 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/fig/v1/rxpcu_ppdu_end_info.h deleted file mode 100644 index 2d53435fb817..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rxpcu_ppdu_end_info.h +++ /dev/null @@ -1,925 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_PPDU_END_INFO_H_ -#define _RXPCU_PPDU_END_INFO_H_ - -#include "phyrx_abort_request_info.h" -#include "macrx_abort_request_info.h" -#include "rxpcu_ppdu_end_layout_info.h" -#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 32 - -#define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 16 - -struct rxpcu_ppdu_end_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t wb_timestamp_lower_32 : 32; - uint32_t wb_timestamp_upper_32 : 32; - uint32_t rx_antenna : 24, - tx_ht_vht_ack : 1, - unsupported_mu_nc : 1, - otp_txbf_disable : 1, - previous_tlv_corrupted : 1, - phyrx_abort_request_info_valid : 1, - macrx_abort_request_info_valid : 1, - coex_wan_tx_from_start_of_rx_ratid1 : 1, - coex_wan_tx_after_start_of_rx_ratid1 : 1; - uint32_t coex_bt_tx_from_start_of_rx : 1, - coex_bt_tx_after_start_of_rx : 1, - coex_wan_tx_from_start_of_rx : 1, - coex_wan_tx_after_start_of_rx : 1, - coex_wlan_tx_from_start_of_rx : 1, - coex_wlan_tx_after_start_of_rx : 1, - mpdu_delimiter_errors_seen : 1, - __reserved_g_0012 : 2, - dialog_token : 8, - follow_up_dialog_token : 8, - bb_captured_channel : 1, - bb_captured_reason : 3, - bb_captured_timeout : 1, - __reserved_g_0066 : 1, - __reserved_g_0067 : 1; - uint32_t before_mpdu_count_passing_fcs : 10, - before_mpdu_count_failing_fcs : 10, - after_mpdu_count_passing_fcs : 10, - reserved_4 : 2; - uint32_t after_mpdu_count_failing_fcs : 10, - reserved_5 : 22; - uint32_t phy_timestamp_tx_lower_32 : 32; - uint32_t phy_timestamp_tx_upper_32 : 32; - uint32_t bb_length : 16, - bb_data : 1, - reserved_8 : 3, - first_bt_broadcast_status_details : 12; - uint32_t rx_ppdu_duration : 24, - reserved_9 : 8; - uint32_t ast_index : 16, - ast_index_valid : 1, - reserved_10 : 3, - second_bt_broadcast_status_details : 12; - struct phyrx_abort_request_info phyrx_abort_request_info_details; - struct macrx_abort_request_info macrx_abort_request_info_details; - uint16_t pre_bt_broadcast_status_details : 12, - reserved_12a : 4; - uint32_t non_qos_sn_info_valid : 1, - rts_or_trig_protected_ppdu : 1, - rts_or_trig_prot_type : 2, - reserved_13a : 2, - non_qos_sn_highest : 12, - non_qos_sn_highest_retry_setting : 1, - non_qos_sn_lowest : 12, - non_qos_sn_lowest_retry_setting : 1; - uint32_t qos_sn_1_info_valid : 1, - reserved_14a : 1, - qos_sn_1_tid : 4, - qos_sn_1_highest : 12, - qos_sn_1_highest_retry_setting : 1, - qos_sn_1_lowest : 12, - qos_sn_1_lowest_retry_setting : 1; - uint32_t qos_sn_2_info_valid : 1, - reserved_15a : 1, - qos_sn_2_tid : 4, - qos_sn_2_highest : 12, - qos_sn_2_highest_retry_setting : 1, - qos_sn_2_lowest : 12, - qos_sn_2_lowest_retry_setting : 1; - struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; - uint32_t corrupted_due_to_fifo_delay : 1, - qos_sn_1_more_frag_state : 1, - qos_sn_1_frag_num_state : 4, - qos_sn_2_more_frag_state : 1, - qos_sn_2_frag_num_state : 4, - rts_or_trig_prot_non_11a : 1, - rts_or_trig_prot_rate_mcs : 4, - rts_or_trig_prot_peer_addr_15_0 : 16; - uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; - uint32_t rts_or_trig_rx_count : 32; - uint32_t cts_or_null_tx_count : 32; - uint32_t coex_tracker2_tx_from_start_of_rx : 1, - coex_tracker2_tx_after_start_of_rx : 1, - coex_tracker3_tx_from_start_of_rx : 1, - coex_tracker3_tx_after_start_of_rx : 1, - coex_tracker4_tx_from_start_of_rx : 1, - coex_tracker4_tx_after_start_of_rx : 1, - coex_tracker5_tx_from_start_of_rx : 1, - coex_tracker5_tx_after_start_of_rx : 1, - coex_tracker6_tx_from_start_of_rx : 1, - coex_tracker6_tx_after_start_of_rx : 1, - reserved_30a : 22; - uint32_t rx_ppdu_end_marker : 32; -#else - uint32_t wb_timestamp_lower_32 : 32; - uint32_t wb_timestamp_upper_32 : 32; - uint32_t coex_wan_tx_after_start_of_rx_ratid1 : 1, - coex_wan_tx_from_start_of_rx_ratid1 : 1, - macrx_abort_request_info_valid : 1, - phyrx_abort_request_info_valid : 1, - previous_tlv_corrupted : 1, - otp_txbf_disable : 1, - unsupported_mu_nc : 1, - tx_ht_vht_ack : 1, - rx_antenna : 24; - uint32_t __reserved_g_0067 : 1, - __reserved_g_0066 : 1, - bb_captured_timeout : 1, - bb_captured_reason : 3, - bb_captured_channel : 1, - follow_up_dialog_token : 8, - dialog_token : 8, - __reserved_g_0012 : 2, - mpdu_delimiter_errors_seen : 1, - coex_wlan_tx_after_start_of_rx : 1, - coex_wlan_tx_from_start_of_rx : 1, - coex_wan_tx_after_start_of_rx : 1, - coex_wan_tx_from_start_of_rx : 1, - coex_bt_tx_after_start_of_rx : 1, - coex_bt_tx_from_start_of_rx : 1; - uint32_t reserved_4 : 2, - after_mpdu_count_passing_fcs : 10, - before_mpdu_count_failing_fcs : 10, - before_mpdu_count_passing_fcs : 10; - uint32_t reserved_5 : 22, - after_mpdu_count_failing_fcs : 10; - uint32_t phy_timestamp_tx_lower_32 : 32; - uint32_t phy_timestamp_tx_upper_32 : 32; - uint32_t first_bt_broadcast_status_details : 12, - reserved_8 : 3, - bb_data : 1, - bb_length : 16; - uint32_t reserved_9 : 8, - rx_ppdu_duration : 24; - uint32_t second_bt_broadcast_status_details : 12, - reserved_10 : 3, - ast_index_valid : 1, - ast_index : 16; - struct phyrx_abort_request_info phyrx_abort_request_info_details; - uint32_t reserved_12a : 4, - pre_bt_broadcast_status_details : 12; - struct macrx_abort_request_info macrx_abort_request_info_details; - uint32_t non_qos_sn_lowest_retry_setting : 1, - non_qos_sn_lowest : 12, - non_qos_sn_highest_retry_setting : 1, - non_qos_sn_highest : 12, - reserved_13a : 2, - rts_or_trig_prot_type : 2, - rts_or_trig_protected_ppdu : 1, - non_qos_sn_info_valid : 1; - uint32_t qos_sn_1_lowest_retry_setting : 1, - qos_sn_1_lowest : 12, - qos_sn_1_highest_retry_setting : 1, - qos_sn_1_highest : 12, - qos_sn_1_tid : 4, - reserved_14a : 1, - qos_sn_1_info_valid : 1; - uint32_t qos_sn_2_lowest_retry_setting : 1, - qos_sn_2_lowest : 12, - qos_sn_2_highest_retry_setting : 1, - qos_sn_2_highest : 12, - qos_sn_2_tid : 4, - reserved_15a : 1, - qos_sn_2_info_valid : 1; - struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; - uint32_t rts_or_trig_prot_peer_addr_15_0 : 16, - rts_or_trig_prot_rate_mcs : 4, - rts_or_trig_prot_non_11a : 1, - qos_sn_2_frag_num_state : 4, - qos_sn_2_more_frag_state : 1, - qos_sn_1_frag_num_state : 4, - qos_sn_1_more_frag_state : 1, - corrupted_due_to_fifo_delay : 1; - uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; - uint32_t rts_or_trig_rx_count : 32; - uint32_t cts_or_null_tx_count : 32; - uint32_t reserved_30a : 22, - coex_tracker6_tx_after_start_of_rx : 1, - coex_tracker6_tx_from_start_of_rx : 1, - coex_tracker5_tx_after_start_of_rx : 1, - coex_tracker5_tx_from_start_of_rx : 1, - coex_tracker4_tx_after_start_of_rx : 1, - coex_tracker4_tx_from_start_of_rx : 1, - coex_tracker3_tx_after_start_of_rx : 1, - coex_tracker3_tx_from_start_of_rx : 1, - coex_tracker2_tx_after_start_of_rx : 1, - coex_tracker2_tx_from_start_of_rx : 1; - uint32_t rx_ppdu_end_marker : 32; -#endif -}; - -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff - -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 - -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 - -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 - -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_LSB 30 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MSB 30 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MASK 0x0000000040000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_LSB 31 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MSB 31 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MASK 0x0000000080000000 - -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 - -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 - -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 - -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 - -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 - -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 - -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff - -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 - -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 - -#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 -#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 - -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 -#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 -#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 - -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff - -#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 -#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 -#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 - -#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 -#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 -#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 - -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 - -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 -#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 -#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 - -#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 -#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 -#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff - -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 - -#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 -#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 -#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 - -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 42 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 42 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x0000040000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB 43 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB 43 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x0000080000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 44 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 44 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x0000100000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB 45 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB 45 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK 0x0000200000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB 46 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB 46 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK 0x0000400000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 47 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000800000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 - -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 - -#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB 33 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB 33 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB 34 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB 35 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK 0x0000000c00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 36 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB 11 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB 11 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK 0x0000000000000800 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB 12 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB 15 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK 0x000000000000f000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB 16 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB 31 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK 0x00000000ffff0000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB 32 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB 63 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET 0x0000000000000070 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB 0 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB 31 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET 0x0000000000000070 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB 32 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB 63 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_LSB 0 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MSB 0 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_LSB 1 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MSB 1 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_LSB 2 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MSB 2 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MASK 0x0000000000000004 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_LSB 3 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MSB 3 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MASK 0x0000000000000008 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_LSB 4 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MSB 4 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MASK 0x0000000000000010 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_LSB 5 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MSB 5 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MASK 0x0000000000000020 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_LSB 6 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MSB 6 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MASK 0x0000000000000040 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_LSB 7 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MSB 7 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MASK 0x0000000000000080 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_LSB 8 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MSB 8 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MASK 0x0000000000000100 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_LSB 9 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MSB 9 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MASK 0x0000000000000200 - -#define RXPCU_PPDU_END_INFO_RESERVED_30A_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_LSB 10 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_MASK 0x00000000fffffc00 - -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rxpcu_ppdu_end_layout_info.h b/drivers/staging/fw-api/hw/fig/v1/rxpcu_ppdu_end_layout_info.h deleted file mode 100644 index 9d54e91522ec..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rxpcu_ppdu_end_layout_info.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ -#define _RXPCU_PPDU_END_LAYOUT_INFO_H_ - -#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 - -struct rxpcu_ppdu_end_layout_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rssi_legacy_offset : 2, - l_sig_a_offset : 6, - l_sig_b_offset : 6, - ht_sig_offset : 6, - vht_sig_a_offset : 6, - repeat_l_sig_a_offset : 6; - uint32_t he_sig_a_su_offset : 6, - he_sig_a_mu_dl_offset : 6, - he_sig_a_mu_ul_offset : 6, - generic_u_sig_offset : 6, - rssi_ht_offset : 7, - reserved_1a : 1; - uint32_t vht_sig_b_su20_offset : 7, - vht_sig_b_su40_offset : 7, - vht_sig_b_su80_offset : 7, - vht_sig_b_su160_offset : 7, - reserved_2a : 4; - uint32_t vht_sig_b_mu20_offset : 7, - vht_sig_b_mu40_offset : 7, - vht_sig_b_mu80_offset : 7, - vht_sig_b_mu160_offset : 7, - reserved_3a : 4; - uint32_t he_sig_b1_mu_offset : 7, - he_sig_b2_mu_offset : 7, - he_sig_b2_ofdma_offset : 7, - first_generic_eht_sig_offset : 7, - multiple_generic_eht_sig_included : 1, - reserved_4a : 3; - uint32_t common_user_info_offset : 7, - first_debug_info_offset : 8, - multiple_debug_info_included : 1, - first_other_receive_info_offset : 8, - multiple_other_receive_info_included : 1, - reserved_5a : 7; - uint32_t data_done_offset : 8, - generated_cbf_details_offset : 8, - pkt_end_part1_offset : 8, - location_offset : 8; - uint32_t __reserved_g_0011 : 8, - pkt_end_offset : 8, - abort_request_ack_offset : 8, - reserved_7a : 8; - uint32_t reserved_8a : 32; - uint32_t reserved_9a : 32; -#else - uint32_t repeat_l_sig_a_offset : 6, - vht_sig_a_offset : 6, - ht_sig_offset : 6, - l_sig_b_offset : 6, - l_sig_a_offset : 6, - rssi_legacy_offset : 2; - uint32_t reserved_1a : 1, - rssi_ht_offset : 7, - generic_u_sig_offset : 6, - he_sig_a_mu_ul_offset : 6, - he_sig_a_mu_dl_offset : 6, - he_sig_a_su_offset : 6; - uint32_t reserved_2a : 4, - vht_sig_b_su160_offset : 7, - vht_sig_b_su80_offset : 7, - vht_sig_b_su40_offset : 7, - vht_sig_b_su20_offset : 7; - uint32_t reserved_3a : 4, - vht_sig_b_mu160_offset : 7, - vht_sig_b_mu80_offset : 7, - vht_sig_b_mu40_offset : 7, - vht_sig_b_mu20_offset : 7; - uint32_t reserved_4a : 3, - multiple_generic_eht_sig_included : 1, - first_generic_eht_sig_offset : 7, - he_sig_b2_ofdma_offset : 7, - he_sig_b2_mu_offset : 7, - he_sig_b1_mu_offset : 7; - uint32_t reserved_5a : 7, - multiple_other_receive_info_included : 1, - first_other_receive_info_offset : 8, - multiple_debug_info_included : 1, - first_debug_info_offset : 8, - common_user_info_offset : 7; - uint32_t location_offset : 8, - pkt_end_part1_offset : 8, - generated_cbf_details_offset : 8, - data_done_offset : 8; - uint32_t reserved_7a : 8, - abort_request_ack_offset : 8, - pkt_end_offset : 8, - __reserved_g_0011 : 8; - uint32_t reserved_8a : 32; - uint32_t reserved_9a : 32; -#endif -}; - -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 - -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc - -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff - -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rxpt_classify_info.h b/drivers/staging/fw-api/hw/fig/v1/rxpt_classify_info.h deleted file mode 100644 index 7fc572ae2474..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rxpt_classify_info.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPT_CLASSIFY_INFO_H_ -#define _RXPT_CLASSIFY_INFO_H_ - -#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 - -struct rxpt_classify_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reo_destination_indication : 5, - lmac_peer_id_msb : 2, - use_flow_id_toeplitz_clfy : 1, - pkt_selection_fp_ucast_data : 1, - pkt_selection_fp_mcast_data : 1, - pkt_selection_fp_1000 : 1, - rxdma0_source_ring_selection : 3, - rxdma0_destination_ring_selection : 3, - mcast_echo_drop_enable : 1, - wds_learning_detect_en : 1, - intrabss_check_en : 1, - use_ppe : 1, - ppe_routing_enable : 1, - cce_source_sel_en : 1, - reserved_0b : 9; -#else - uint32_t reserved_0b : 9, - cce_source_sel_en : 1, - ppe_routing_enable : 1, - use_ppe : 1, - intrabss_check_en : 1, - wds_learning_detect_en : 1, - mcast_echo_drop_enable : 1, - rxdma0_destination_ring_selection : 3, - rxdma0_source_ring_selection : 3, - pkt_selection_fp_1000 : 1, - pkt_selection_fp_mcast_data : 1, - pkt_selection_fp_ucast_data : 1, - use_flow_id_toeplitz_clfy : 1, - lmac_peer_id_msb : 2, - reo_destination_indication : 5; -#endif -}; - -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060 - -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400 - -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 - -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 - -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 - -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000 - -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000 - -#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20 -#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20 -#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000 - -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000 - -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB 22 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB 22 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK 0x00400000 - -#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 23 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xff800000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/seq_hwio.h b/drivers/staging/fw-api/hw/fig/v1/seq_hwio.h deleted file mode 100644 index 69111d08d535..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/seq_hwio.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef __SEQ_H__ -#define __SEQ_H__ - -#include "HALhwio.h" - -#define SEQ_INH(base, regtype, reg) \ - SEQ_##regtype##_INH(base, reg) - -#define SEQ_INMH(base, regtype, reg, mask) \ - SEQ_##regtype##_INMH(base, reg, mask) - -#define SEQ_INFH(base, regtype, reg, fld) \ - (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) - -#define SEQ_OUTH(base, regtype, reg, val) \ - SEQ_##regtype##_OUTH(base, reg, val) - -#define SEQ_OUTMH(base, regtype, reg, mask, val) \ - SEQ_##regtype##_OUTMH(base, reg, mask, val) - -#define SEQ_OUTFH(base, regtype, reg, fld, val) \ - SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) - -typedef enum { - SEC, - MS, - US, - NS -} SEQ_TimeUnit; - -extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); - -extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); - -#endif - diff --git a/drivers/staging/fw-api/hw/fig/v1/tcl_assist_cmd.h b/drivers/staging/fw-api/hw/fig/v1/tcl_assist_cmd.h deleted file mode 100644 index f7a5bd5287cb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tcl_assist_cmd.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TCL_ASSIST_CMD_H_ -#define _TCL_ASSIST_CMD_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_TCL_ASSIST_CMD 16 - -struct tcl_assist_cmd { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_addr_info; - uint32_t buf_or_ext_desc_type : 1, - bank_id : 6, - vdev_id : 8, - data_length : 14, - to_fw_tqm : 2, - reserved_2a : 1; - uint32_t reserved_3a : 25, - metadata_length : 7; - uint32_t txpt_classify_info_index : 8, - txpt_classify_info_sel : 5, - txpt_classify_info_override : 1, - flow_override_enable : 1, - flow_select : 1, - hlos_tid : 4, - hlos_tid_overwrite : 1, - tos_tc_value : 8, - reserved_4a : 3; - uint32_t reserved_5a : 16, - l3_type : 16; - uint32_t l4_protocol : 8, - l4_port : 16, - l4_port_type : 1, - da_is_bcast_mcast : 1, - da_is_bcast : 1, - reserved_6a : 5; - uint32_t ip_address_31_0 : 32; - uint32_t ip_address_63_32 : 32; - uint32_t ip_address_95_64 : 32; - uint32_t ip_address_127_96 : 32; - uint32_t ip_da_or_sa : 1, - encap_length_change : 6, - encap_length_decrease : 1, - encap_length_override : 1, - type_or_length : 1, - snap_oui_zero_or_f8 : 1, - snap_oui_not_zero_and_not_f8 : 1, - msdu_color : 2, - tx_notify_frame : 3, - tqm_no_drop : 1, - reserved_11a : 12, - l3_checksum_enable : 1, - l4_checksum_enable : 1; - uint32_t buffer_timestamp : 19, - buffer_timestamp_valid : 1, - s_vlan_tag_present : 1, - c_vlan_tag_present : 1, - wmac_hdr_len : 7, - reserved_12a : 3; - uint32_t tcl_cmd_number : 32; - uint32_t reserved_14a : 32; - uint32_t reserved_15a : 20, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_addr_info; - uint32_t reserved_2a : 1, - to_fw_tqm : 2, - data_length : 14, - vdev_id : 8, - bank_id : 6, - buf_or_ext_desc_type : 1; - uint32_t metadata_length : 7, - reserved_3a : 25; - uint32_t reserved_4a : 3, - tos_tc_value : 8, - hlos_tid_overwrite : 1, - hlos_tid : 4, - flow_select : 1, - flow_override_enable : 1, - txpt_classify_info_override : 1, - txpt_classify_info_sel : 5, - txpt_classify_info_index : 8; - uint32_t l3_type : 16, - reserved_5a : 16; - uint32_t reserved_6a : 5, - da_is_bcast : 1, - da_is_bcast_mcast : 1, - l4_port_type : 1, - l4_port : 16, - l4_protocol : 8; - uint32_t ip_address_31_0 : 32; - uint32_t ip_address_63_32 : 32; - uint32_t ip_address_95_64 : 32; - uint32_t ip_address_127_96 : 32; - uint32_t l4_checksum_enable : 1, - l3_checksum_enable : 1, - reserved_11a : 12, - tqm_no_drop : 1, - tx_notify_frame : 3, - msdu_color : 2, - snap_oui_not_zero_and_not_f8 : 1, - snap_oui_zero_or_f8 : 1, - type_or_length : 1, - encap_length_override : 1, - encap_length_decrease : 1, - encap_length_change : 6, - ip_da_or_sa : 1; - uint32_t reserved_12a : 3, - wmac_hdr_len : 7, - c_vlan_tag_present : 1, - s_vlan_tag_present : 1, - buffer_timestamp_valid : 1, - buffer_timestamp : 19; - uint32_t tcl_cmd_number : 32; - uint32_t reserved_14a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_15a : 20; -#endif -}; - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_LSB 0 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MSB 0 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001 - -#define TCL_ASSIST_CMD_BANK_ID_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_BANK_ID_LSB 1 -#define TCL_ASSIST_CMD_BANK_ID_MSB 6 -#define TCL_ASSIST_CMD_BANK_ID_MASK 0x0000007e - -#define TCL_ASSIST_CMD_VDEV_ID_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_VDEV_ID_LSB 7 -#define TCL_ASSIST_CMD_VDEV_ID_MSB 14 -#define TCL_ASSIST_CMD_VDEV_ID_MASK 0x00007f80 - -#define TCL_ASSIST_CMD_DATA_LENGTH_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_DATA_LENGTH_LSB 15 -#define TCL_ASSIST_CMD_DATA_LENGTH_MSB 28 -#define TCL_ASSIST_CMD_DATA_LENGTH_MASK 0x1fff8000 - -#define TCL_ASSIST_CMD_TO_FW_TQM_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_TO_FW_TQM_LSB 29 -#define TCL_ASSIST_CMD_TO_FW_TQM_MSB 30 -#define TCL_ASSIST_CMD_TO_FW_TQM_MASK 0x60000000 - -#define TCL_ASSIST_CMD_RESERVED_2A_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_RESERVED_2A_LSB 31 -#define TCL_ASSIST_CMD_RESERVED_2A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_2A_MASK 0x80000000 - -#define TCL_ASSIST_CMD_RESERVED_3A_OFFSET 0x0000000c -#define TCL_ASSIST_CMD_RESERVED_3A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_3A_MSB 24 -#define TCL_ASSIST_CMD_RESERVED_3A_MASK 0x01ffffff - -#define TCL_ASSIST_CMD_METADATA_LENGTH_OFFSET 0x0000000c -#define TCL_ASSIST_CMD_METADATA_LENGTH_LSB 25 -#define TCL_ASSIST_CMD_METADATA_LENGTH_MSB 31 -#define TCL_ASSIST_CMD_METADATA_LENGTH_MASK 0xfe000000 - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_LSB 0 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MSB 7 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MASK 0x000000ff - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_LSB 8 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MSB 12 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MASK 0x00001f00 - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_LSB 13 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MSB 13 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MASK 0x00002000 - -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_LSB 14 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MSB 14 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00004000 - -#define TCL_ASSIST_CMD_FLOW_SELECT_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_FLOW_SELECT_LSB 15 -#define TCL_ASSIST_CMD_FLOW_SELECT_MSB 15 -#define TCL_ASSIST_CMD_FLOW_SELECT_MASK 0x00008000 - -#define TCL_ASSIST_CMD_HLOS_TID_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_HLOS_TID_LSB 16 -#define TCL_ASSIST_CMD_HLOS_TID_MSB 19 -#define TCL_ASSIST_CMD_HLOS_TID_MASK 0x000f0000 - -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_LSB 20 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MSB 20 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MASK 0x00100000 - -#define TCL_ASSIST_CMD_TOS_TC_VALUE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_LSB 21 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_MSB 28 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_MASK 0x1fe00000 - -#define TCL_ASSIST_CMD_RESERVED_4A_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_RESERVED_4A_LSB 29 -#define TCL_ASSIST_CMD_RESERVED_4A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_4A_MASK 0xe0000000 - -#define TCL_ASSIST_CMD_RESERVED_5A_OFFSET 0x00000014 -#define TCL_ASSIST_CMD_RESERVED_5A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_5A_MSB 15 -#define TCL_ASSIST_CMD_RESERVED_5A_MASK 0x0000ffff - -#define TCL_ASSIST_CMD_L3_TYPE_OFFSET 0x00000014 -#define TCL_ASSIST_CMD_L3_TYPE_LSB 16 -#define TCL_ASSIST_CMD_L3_TYPE_MSB 31 -#define TCL_ASSIST_CMD_L3_TYPE_MASK 0xffff0000 - -#define TCL_ASSIST_CMD_L4_PROTOCOL_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PROTOCOL_LSB 0 -#define TCL_ASSIST_CMD_L4_PROTOCOL_MSB 7 -#define TCL_ASSIST_CMD_L4_PROTOCOL_MASK 0x000000ff - -#define TCL_ASSIST_CMD_L4_PORT_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PORT_LSB 8 -#define TCL_ASSIST_CMD_L4_PORT_MSB 23 -#define TCL_ASSIST_CMD_L4_PORT_MASK 0x00ffff00 - -#define TCL_ASSIST_CMD_L4_PORT_TYPE_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_LSB 24 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_MSB 24 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_MASK 0x01000000 - -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_LSB 25 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MSB 25 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MASK 0x02000000 - -#define TCL_ASSIST_CMD_DA_IS_BCAST_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_DA_IS_BCAST_LSB 26 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MSB 26 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MASK 0x04000000 - -#define TCL_ASSIST_CMD_RESERVED_6A_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_RESERVED_6A_LSB 27 -#define TCL_ASSIST_CMD_RESERVED_6A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_6A_MASK 0xf8000000 - -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_OFFSET 0x0000001c -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_OFFSET 0x00000020 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_OFFSET 0x00000024 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_OFFSET 0x00000028 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_DA_OR_SA_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_IP_DA_OR_SA_LSB 0 -#define TCL_ASSIST_CMD_IP_DA_OR_SA_MSB 0 -#define TCL_ASSIST_CMD_IP_DA_OR_SA_MASK 0x00000001 - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_LSB 1 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MSB 6 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MASK 0x0000007e - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_LSB 7 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MSB 7 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MASK 0x00000080 - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_LSB 8 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MSB 8 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MASK 0x00000100 - -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_LSB 9 -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MSB 9 -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MASK 0x00000200 - -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_LSB 10 -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MSB 10 -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MASK 0x00000400 - -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_LSB 11 -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MSB 11 -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MASK 0x00000800 - -#define TCL_ASSIST_CMD_MSDU_COLOR_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_MSDU_COLOR_LSB 12 -#define TCL_ASSIST_CMD_MSDU_COLOR_MSB 13 -#define TCL_ASSIST_CMD_MSDU_COLOR_MASK 0x00003000 - -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_LSB 14 -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MSB 16 -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MASK 0x0001c000 - -#define TCL_ASSIST_CMD_TQM_NO_DROP_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TQM_NO_DROP_LSB 17 -#define TCL_ASSIST_CMD_TQM_NO_DROP_MSB 17 -#define TCL_ASSIST_CMD_TQM_NO_DROP_MASK 0x00020000 - -#define TCL_ASSIST_CMD_RESERVED_11A_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_RESERVED_11A_LSB 18 -#define TCL_ASSIST_CMD_RESERVED_11A_MSB 29 -#define TCL_ASSIST_CMD_RESERVED_11A_MASK 0x3ffc0000 - -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_LSB 30 -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MSB 30 -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MASK 0x40000000 - -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_LSB 31 -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MSB 31 -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MASK 0x80000000 - -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_LSB 0 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MSB 18 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MASK 0x0007ffff - -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_LSB 19 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MSB 19 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x00080000 - -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_LSB 20 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MSB 20 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MASK 0x00100000 - -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_LSB 21 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MSB 21 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MASK 0x00200000 - -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_LSB 22 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MSB 28 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MASK 0x1fc00000 - -#define TCL_ASSIST_CMD_RESERVED_12A_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_RESERVED_12A_LSB 29 -#define TCL_ASSIST_CMD_RESERVED_12A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_12A_MASK 0xe0000000 - -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_OFFSET 0x00000034 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_LSB 0 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MSB 31 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MASK 0xffffffff - -#define TCL_ASSIST_CMD_RESERVED_14A_OFFSET 0x00000038 -#define TCL_ASSIST_CMD_RESERVED_14A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_14A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_14A_MASK 0xffffffff - -#define TCL_ASSIST_CMD_RESERVED_15A_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_RESERVED_15A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_15A_MSB 19 -#define TCL_ASSIST_CMD_RESERVED_15A_MASK 0x000fffff - -#define TCL_ASSIST_CMD_RING_ID_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_RING_ID_LSB 20 -#define TCL_ASSIST_CMD_RING_ID_MSB 27 -#define TCL_ASSIST_CMD_RING_ID_MASK 0x0ff00000 - -#define TCL_ASSIST_CMD_LOOPING_COUNT_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_LOOPING_COUNT_LSB 28 -#define TCL_ASSIST_CMD_LOOPING_COUNT_MSB 31 -#define TCL_ASSIST_CMD_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tcl_status_ring.h b/drivers/staging/fw-api/hw/fig/v1/tcl_status_ring.h deleted file mode 100644 index 5a24217c95d5..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tcl_status_ring.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TCL_STATUS_RING_H_ -#define _TCL_STATUS_RING_H_ - -#define NUM_OF_DWORDS_TCL_STATUS_RING 8 - -struct tcl_status_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t gse_ctrl : 4, - ase_fse_sel : 1, - cache_op_res : 2, - index_search_en : 1, - msdu_cnt_n : 24; - uint32_t msdu_byte_cnt_n : 32; - uint32_t msdu_timestmp_n : 32; - uint32_t cmd_meta_data_31_0 : 32; - uint32_t cmd_meta_data_63_32 : 32; - uint32_t hash_indx_val : 20, - cache_set_num : 4, - reserved_5a : 8; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 20, - ring_id : 8, - looping_count : 4; -#else - uint32_t msdu_cnt_n : 24, - index_search_en : 1, - cache_op_res : 2, - ase_fse_sel : 1, - gse_ctrl : 4; - uint32_t msdu_byte_cnt_n : 32; - uint32_t msdu_timestmp_n : 32; - uint32_t cmd_meta_data_31_0 : 32; - uint32_t cmd_meta_data_63_32 : 32; - uint32_t reserved_5a : 8, - cache_set_num : 4, - hash_indx_val : 20; - uint32_t reserved_6a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_7a : 20; -#endif -}; - -#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 -#define TCL_STATUS_RING_GSE_CTRL_LSB 0 -#define TCL_STATUS_RING_GSE_CTRL_MSB 3 -#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f - -#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 -#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 -#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 -#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 - -#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 -#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 -#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 -#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 - -#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 - -#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 -#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 -#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 -#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 - -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff - -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff - -#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c -#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 -#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 -#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff - -#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff - -#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 -#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 -#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 -#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff - -#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 -#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 -#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 -#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 - -#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 -#define TCL_STATUS_RING_RESERVED_5A_LSB 24 -#define TCL_STATUS_RING_RESERVED_5A_MSB 31 -#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 - -#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 -#define TCL_STATUS_RING_RESERVED_6A_LSB 0 -#define TCL_STATUS_RING_RESERVED_6A_MSB 31 -#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff - -#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c -#define TCL_STATUS_RING_RESERVED_7A_LSB 0 -#define TCL_STATUS_RING_RESERVED_7A_MSB 19 -#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff - -#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c -#define TCL_STATUS_RING_RING_ID_LSB 20 -#define TCL_STATUS_RING_RING_ID_MSB 27 -#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 - -#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 -#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 -#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tlv_hdr.h b/drivers/staging/fw-api/hw/fig/v1/tlv_hdr.h deleted file mode 100644 index a2defe7be508..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tlv_hdr.h +++ /dev/null @@ -1,634 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TLV_HDR_H_ -#define _TLV_HDR_H_ - -#define _TLV_USERID_WIDTH_ 6 - -#define _TLV_MRV_EN_LEN_WIDTH_ 9 -#define _TLV_MRV_DIS_LEN_WIDTH_ 12 - -#define _TLV_DATA_WIDTH_ 32 -#define _TLV_64_DATA_WIDTH_ 64 -#define _TLV_CDATA_WIDTH_ 32 -#define _TLV_77_DATA_WIDTH_ 77 -#define _TLV_CDATA_77_WIDTH_ 64 - -#define _TLV_TAG_WIDTH_ 10 -#define _TLV_CTAG_WIDTH_ 6 - -struct tlv_mlo_usr_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mlo_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_32_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_32_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : 6; -#else - uint32_t tlv_reserved : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_64_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_64_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_c_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata_lower_52 : 52; - uint64_t tlv_cdata_upper_12 : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - tlv_cdata_upper_12 : 12; - uint64_t tlv_cdata_lower_52 : 52, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_; -#endif -}; - -struct tlv_mlo_usr_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mlo_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_reserved : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mac_usr_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mac_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_reserved : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_usr_c_77_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata_lower_20 : 20; - uint32_t tlv_cdata_middle_32 : 32; - uint32_t tlv_cdata_upper_12 : 12, - tlv_compression : 1, - pad_77to96_bit : 19; - uint32_t pad_96to128_bit : 32; -#else - uint32_t tlv_cdata_lower_20 : 20, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_; - uint32_t tlv_cdata_middle_32 : 32; - uint32_t pad_77to96_bit : 20, - tlv_compression : 1, - tlv_cdata_upper_12 : 12; - uint32_t pad_96to128_bit : 32; -#endif -}; - -struct tlv_usr_32_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_reserved : 32; -#else - uint64_t tlv_reserved : 32, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_32_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : 6, - pad_32to64_bit : 32; -#else - uint64_t pad_32to64_bit : 32, - tlv_reserved : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_77_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint32_t pad_64to75_bit : 12, - tlv_compression : 1, - pad_77to95_bit : 19; -#else - uint32_t pad_77to95_bit : 19, - tlv_compression : 1, - pad_64to75_bit : 12; - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_77_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint32_t pad_64to75_bit : 12, - tlv_compression : 1, - pad_77to96_bit : 19; -#else - uint32_t pad_77to96_bit : 19, - tlv_compression : 1, - pad_64to75_bit : 12; - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_c_44_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata : _TLV_CDATA_WIDTH_, - pad_44to64_bit : 20; -#else - uint64_t tlv_cdata_lower_20 : 20, - pad_44to64_bit : 20, - tlv_cdata_upper_12 : 12; - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_, -#endif -}; - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tlv_tag_def.h b/drivers/staging/fw-api/hw/fig/v1/tlv_tag_def.h deleted file mode 100644 index 8189c6ec5601..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tlv_tag_def.h +++ /dev/null @@ -1,1976 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TLV_TAG_DEF_ -#define _TLV_TAG_DEF_ - -typedef enum tlv_tag_def { - WIFIMACTX_CBF_START_E = 0 , - WIFIPHYRX_DATA_E = 1 , - WIFIPHYRX_CBF_DATA_RESP_E = 2 , - WIFIPHYRX_ABORT_REQUEST_E = 3 , - WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , - WIFIMACTX_DATA_RESP_E = 5 , - WIFIMACTX_CBF_DATA_E = 6 , - WIFIMACTX_CBF_DONE_E = 7 , - WIFIPHYRX_LMR_DATA_RESP_E = 8 , - WIFIRXPCU_TO_UCODE_START_E = 9 , - WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , - WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , - WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 , - WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , - WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , - WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , - WIFIRXPCU_TO_UCODE_END_E = 16 , - WIFIPHYRX_RSSI_LEGACY_20MHZ_E = 17 , - WIFIPHYRX_NC_ABORT_REQUEST_E = 18 , - WIFIPHYRX_PKT_END_20MHZ_E = 19 , - WIFIPHYRX_NC_DATA_E = 20 , - WIFIMACRX_CBF_READ_REQUEST_E = 64 , - WIFIMACRX_CBF_DATA_REQUEST_E = 65 , - WIFIMACRX_EXPECT_NDP_RECEPTION_E = 66 , - WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 67 , - WIFIMACRX_NDP_TIMEOUT_E = 68 , - WIFIMACRX_ABORT_ACK_E = 69 , - WIFIMACRX_REQ_IMPLICIT_FB_E = 70 , - WIFIMACRX_CHAIN_MASK_E = 71 , - WIFIMACRX_NAP_USER_E = 72 , - WIFIMACRX_ABORT_REQUEST_E = 73 , - WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 74 , - WIFIPHYTX_ABORT_ACK_E = 75 , - WIFIPHYTX_ABORT_REQUEST_E = 76 , - WIFIPHYTX_PKT_END_E = 77 , - WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 78 , - WIFIPHYTX_REQUEST_CTRL_INFO_E = 79 , - WIFIPHYTX_DATA_REQUEST_E = 80 , - WIFIPHYTX_BF_CV_LOADING_DONE_E = 81 , - WIFIPHYTX_NAP_ACK_E = 82 , - WIFIPHYTX_NAP_DONE_E = 83 , - WIFIPHYTX_OFF_ACK_E = 84 , - WIFIPHYTX_ON_ACK_E = 85 , - WIFIPHYTX_SYNTH_OFF_ACK_E = 86 , - WIFIPHYTX_DEBUG16_E = 87 , - WIFIMACTX_ABORT_REQUEST_E = 88 , - WIFIMACTX_ABORT_ACK_E = 89 , - WIFIMACTX_PKT_END_E = 90 , - WIFIMACTX_PRE_PHY_DESC_E = 91 , - WIFIMACTX_BF_PARAMS_COMMON_E = 92 , - WIFIMACTX_BF_PARAMS_PER_USER_E = 93 , - WIFIMACTX_PREFETCH_CV_E = 94 , - WIFIMACTX_USER_DESC_COMMON_E = 95 , - WIFIMACTX_USER_DESC_PER_USER_E = 96 , - WIFIEXAMPLE_USER_TLV_16_E = 97 , - WIFIEXAMPLE_TLV_16_E = 98 , - WIFIMACTX_PHY_OFF_E = 99 , - WIFIMACTX_PHY_ON_E = 100 , - WIFIMACTX_SYNTH_OFF_E = 101 , - WIFIMACTX_EXPECT_CBF_COMMON_E = 102 , - WIFIMACTX_EXPECT_CBF_PER_USER_E = 103 , - WIFIMACTX_PHY_DESC_E = 104 , - WIFIMACTX_L_SIG_A_E = 105 , - WIFIMACTX_L_SIG_B_E = 106 , - WIFIMACTX_HT_SIG_E = 107 , - WIFIMACTX_VHT_SIG_A_E = 108 , - WIFIMACTX_VHT_SIG_B_SU20_E = 109 , - WIFIMACTX_VHT_SIG_B_SU40_E = 110 , - WIFIMACTX_VHT_SIG_B_SU80_E = 111 , - WIFIMACTX_VHT_SIG_B_SU160_E = 112 , - WIFIMACTX_VHT_SIG_B_MU20_E = 113 , - WIFIMACTX_VHT_SIG_B_MU40_E = 114 , - WIFIMACTX_VHT_SIG_B_MU80_E = 115 , - WIFIMACTX_VHT_SIG_B_MU160_E = 116 , - WIFIMACTX_SERVICE_E = 117 , - WIFIMACTX_HE_SIG_A_SU_E = 118 , - WIFIMACTX_HE_SIG_A_MU_DL_E = 119 , - WIFIMACTX_HE_SIG_A_MU_UL_E = 120 , - WIFIMACTX_HE_SIG_B1_MU_E = 121 , - WIFIMACTX_HE_SIG_B2_MU_E = 122 , - WIFIMACTX_HE_SIG_B2_OFDMA_E = 123 , - WIFIMACTX_DELETE_CV_E = 124 , - WIFIMACTX_MU_UPLINK_COMMON_E = 125 , - WIFIMACTX_MU_UPLINK_USER_SETUP_E = 126 , - WIFIMACTX_OTHER_TRANSMIT_INFO_E = 127 , - WIFIMACTX_PHY_NAP_E = 128 , - WIFIMACTX_DEBUG_E = 129 , - WIFIPHYRX_ABORT_ACK_E = 130 , - WIFIPHYRX_GENERATED_CBF_DETAILS_E = 131 , - WIFIPHYRX_RSSI_LEGACY_E = 132 , - WIFIPHYRX_RSSI_HT_E = 133 , - WIFIPHYRX_USER_INFO_E = 134 , - WIFIPHYRX_PKT_END_E = 135 , - WIFIPHYRX_DEBUG_E = 136 , - WIFIPHYRX_CBF_TRANSFER_DONE_E = 137 , - WIFIPHYRX_CBF_TRANSFER_ABORT_E = 138 , - WIFIPHYRX_L_SIG_A_E = 139 , - WIFIPHYRX_L_SIG_B_E = 140 , - WIFIPHYRX_HT_SIG_E = 141 , - WIFIPHYRX_VHT_SIG_A_E = 142 , - WIFIPHYRX_VHT_SIG_B_SU20_E = 143 , - WIFIPHYRX_VHT_SIG_B_SU40_E = 144 , - WIFIPHYRX_VHT_SIG_B_SU80_E = 145 , - WIFIPHYRX_VHT_SIG_B_SU160_E = 146 , - WIFIPHYRX_VHT_SIG_B_MU20_E = 147 , - WIFIPHYRX_VHT_SIG_B_MU40_E = 148 , - WIFIPHYRX_VHT_SIG_B_MU80_E = 149 , - WIFIPHYRX_VHT_SIG_B_MU160_E = 150 , - WIFIPHYRX_HE_SIG_A_SU_E = 151 , - WIFIPHYRX_HE_SIG_A_MU_DL_E = 152 , - WIFIPHYRX_HE_SIG_A_MU_UL_E = 153 , - WIFIPHYRX_HE_SIG_B1_MU_E = 154 , - WIFIPHYRX_HE_SIG_B2_MU_E = 155 , - WIFIPHYRX_HE_SIG_B2_OFDMA_E = 156 , - WIFIPHYRX_OTHER_RECEIVE_INFO_E = 157 , - WIFIPHYRX_COMMON_USER_INFO_E = 158 , - WIFIPHYRX_DATA_DONE_E = 159 , - WIFICOEX_TX_REQ_E = 160 , - WIFIDUMMY_E = 161 , - WIFIEXAMPLE_TLV_32_NAME_E = 162 , - WIFIMPDU_LIMIT_E = 163 , - WIFINA_LENGTH_END_E = 164 , - WIFIOLE_BUF_STATUS_E = 165 , - WIFIPCU_PPDU_SETUP_DONE_E = 166 , - WIFIPCU_PPDU_SETUP_END_E = 167 , - WIFIPCU_PPDU_SETUP_INIT_E = 168 , - WIFIPCU_PPDU_SETUP_START_E = 169 , - WIFIPDG_FES_SETUP_E = 170 , - WIFIPDG_RESPONSE_E = 171 , - WIFIPDG_TX_REQ_E = 172 , - WIFISCH_WAIT_INSTR_E = 173 , - WIFIMACTX_SWITCH_TO_MAIN_E = 174 , - WIFIPHYTX_LINK_STATE_E = 175 , - WIFIAUX_PPDU_END_E = 176 , - WIFITQM_GEN_MPDU_LENGTH_LIST_E = 177 , - WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 178 , - WIFITQM_GEN_MPDUS_E = 179 , - WIFITQM_GEN_MPDUS_STATUS_E = 180 , - WIFITQM_REMOVE_MPDU_E = 181 , - WIFITQM_REMOVE_MPDU_STATUS_E = 182 , - WIFITQM_REMOVE_MSDU_E = 183 , - WIFITQM_REMOVE_MSDU_STATUS_E = 184 , - WIFITQM_UPDATE_TX_MPDU_COUNT_E = 185 , - WIFITQM_WRITE_CMD_E = 186 , - WIFIOFDMA_TRIGGER_DETAILS_E = 187 , - WIFITX_DATA_E = 188 , - WIFITX_FES_SETUP_E = 189 , - WIFIRX_PACKET_E = 190 , - WIFIEXPECTED_RESPONSE_E = 191 , - WIFITX_MPDU_END_E = 192 , - WIFITX_MPDU_START_E = 193 , - WIFITX_MSDU_END_E = 194 , - WIFITX_MSDU_START_E = 195 , - WIFITX_SW_MODE_SETUP_E = 196 , - WIFITXPCU_BUFFER_STATUS_E = 197 , - WIFITXPCU_USER_BUFFER_STATUS_E = 198 , - WIFIDATA_TO_TIME_CONFIG_E = 199 , - WIFIEXAMPLE_USER_TLV_32_E = 200 , - WIFIMPDU_INFO_E = 201 , - WIFIPDG_USER_SETUP_E = 202 , - WIFITX_11AH_SETUP_E = 203 , - WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 204 , - WIFITX_PEER_ENTRY_E = 205 , - WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 206 , - WIFIEXAMPLE_USER_TLV_44_E = 207 , - WIFITX_FLUSH_E = 208 , - WIFITX_FLUSH_REQ_E = 209 , - WIFITQM_WRITE_CMD_STATUS_E = 210 , - WIFITQM_GET_MPDU_QUEUE_STATS_E = 211 , - WIFITQM_GET_MSDU_FLOW_STATS_E = 212 , - WIFIEXAMPLE_USER_CTLV_44_E = 213 , - WIFITX_FES_STATUS_START_E = 214 , - WIFITX_FES_STATUS_USER_PPDU_E = 215 , - WIFITX_FES_STATUS_USER_RESPONSE_E = 216 , - WIFITX_FES_STATUS_END_E = 217 , - WIFIRX_TRIG_INFO_E = 218 , - WIFIRXPCU_TX_SETUP_CLEAR_E = 219 , - WIFIRX_FRAME_BITMAP_REQ_E = 220 , - WIFIRX_FRAME_BITMAP_ACK_E = 221 , - WIFICOEX_RX_STATUS_E = 222 , - WIFIRX_START_PARAM_E = 223 , - WIFIRX_PPDU_START_E = 224 , - WIFIRX_PPDU_END_E = 225 , - WIFIRX_MPDU_START_E = 226 , - WIFIRX_MPDU_END_E = 227 , - WIFIRX_MSDU_START_E = 228 , - WIFIRX_MSDU_END_E = 229 , - WIFIRX_ATTENTION_E = 230 , - WIFIRECEIVED_RESPONSE_INFO_E = 231 , - WIFIRX_PHY_SLEEP_E = 232 , - WIFIRX_HEADER_E = 233 , - WIFIRX_PEER_ENTRY_E = 234 , - WIFIRX_FLUSH_E = 235 , - WIFIRX_RESPONSE_REQUIRED_INFO_E = 236 , - WIFIRX_FRAMELESS_BAR_DETAILS_E = 237 , - WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 238 , - WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 239 , - WIFITX_CBF_INFO_E = 240 , - WIFIPCU_PPDU_SETUP_USER_E = 241 , - WIFIRX_MPDU_PCU_START_E = 242 , - WIFIRX_PM_INFO_E = 243 , - WIFIRX_USER_PPDU_END_E = 244 , - WIFIRX_PRE_PPDU_START_E = 245 , - WIFIRX_PREAMBLE_E = 246 , - WIFITX_FES_SETUP_COMPLETE_E = 247 , - WIFITX_LAST_MPDU_FETCHED_E = 248 , - WIFITXDMA_STOP_REQUEST_E = 249 , - WIFIRXPCU_SETUP_E = 250 , - WIFIRXPCU_USER_SETUP_E = 251 , - WIFITX_FES_STATUS_ACK_OR_BA_E = 252 , - WIFITQM_ACKED_MPDU_E = 253 , - WIFICOEX_TX_RESP_E = 254 , - WIFICOEX_TX_STATUS_E = 255 , - WIFIMACTX_COEX_PHY_CTRL_E = 256 , - WIFICOEX_STATUS_BROADCAST_E = 257 , - WIFIRESPONSE_START_STATUS_E = 258 , - WIFIRESPONSE_END_STATUS_E = 259 , - WIFICRYPTO_STATUS_E = 260 , - WIFIRECEIVED_TRIGGER_INFO_E = 261 , - WIFICOEX_TX_STOP_CTRL_E = 262 , - WIFIRX_PPDU_ACK_REPORT_E = 263 , - WIFIRX_PPDU_NO_ACK_REPORT_E = 264 , - WIFISCH_COEX_STATUS_E = 265 , - WIFISCHEDULER_COMMAND_STATUS_E = 266 , - WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 267 , - WIFITX_FES_STATUS_PROT_E = 268 , - WIFITX_FES_STATUS_START_PPDU_E = 269 , - WIFITX_FES_STATUS_START_PROT_E = 270 , - WIFITXPCU_PHYTX_DEBUG32_E = 271 , - WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 272 , - WIFITX_MPDU_COUNT_TRANSFER_END_E = 273 , - WIFIWHO_ANCHOR_OFFSET_E = 274 , - WIFIWHO_ANCHOR_VALUE_E = 275 , - WIFIWHO_CCE_INFO_E = 276 , - WIFIWHO_COMMIT_E = 277 , - WIFIWHO_COMMIT_DONE_E = 278 , - WIFIWHO_FLUSH_E = 279 , - WIFIWHO_L2_LLC_E = 280 , - WIFIWHO_L2_PAYLOAD_E = 281 , - WIFIWHO_L3_CHECKSUM_E = 282 , - WIFIWHO_L3_INFO_E = 283 , - WIFIWHO_L4_CHECKSUM_E = 284 , - WIFIWHO_L4_INFO_E = 285 , - WIFIWHO_MSDU_E = 286 , - WIFIWHO_MSDU_MISC_E = 287 , - WIFIWHO_PACKET_DATA_E = 288 , - WIFIWHO_PACKET_HDR_E = 289 , - WIFIWHO_PPDU_END_E = 290 , - WIFIWHO_PPDU_START_E = 291 , - WIFIWHO_TSO_E = 292 , - WIFIWHO_WMAC_HEADER_PV0_E = 293 , - WIFIWHO_WMAC_HEADER_PV1_E = 294 , - WIFIWHO_WMAC_IV_E = 295 , - WIFIMPDU_INFO_END_E = 296 , - WIFIMPDU_INFO_BITMAP_E = 297 , - WIFITX_QUEUE_EXTENSION_E = 298 , - WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 299 , - WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 300 , - WIFITQM_ACKED_MPDU_STATUS_E = 301 , - WIFITQM_ADD_MSDU_STATUS_E = 302 , - WIFITQM_LIST_GEN_DONE_E = 303 , - WIFIWHO_TERMINATE_E = 304 , - WIFITX_LAST_MPDU_END_E = 305 , - WIFITX_CV_DATA_E = 306 , - WIFIPPDU_TX_END_E = 307 , - WIFIPROT_TX_END_E = 308 , - WIFIMPDU_INFO_GLOBAL_END_E = 309 , - WIFITQM_SCH_INSTR_GLOBAL_END_E = 310 , - WIFIRX_PPDU_END_USER_STATS_E = 311 , - WIFIRX_PPDU_END_USER_STATS_EXT_E = 312 , - WIFIREO_GET_QUEUE_STATS_E = 313 , - WIFIREO_FLUSH_QUEUE_E = 314 , - WIFIREO_FLUSH_CACHE_E = 315 , - WIFIREO_UNBLOCK_CACHE_E = 316 , - WIFIREO_GET_QUEUE_STATS_STATUS_E = 317 , - WIFIREO_FLUSH_QUEUE_STATUS_E = 318 , - WIFIREO_FLUSH_CACHE_STATUS_E = 319 , - WIFIREO_UNBLOCK_CACHE_STATUS_E = 320 , - WIFITQM_FLUSH_CACHE_E = 321 , - WIFITQM_UNBLOCK_CACHE_E = 322 , - WIFITQM_FLUSH_CACHE_STATUS_E = 323 , - WIFITQM_UNBLOCK_CACHE_STATUS_E = 324 , - WIFIRX_PPDU_END_STATUS_DONE_E = 325 , - WIFIRX_STATUS_BUFFER_DONE_E = 326 , - WIFISCHEDULER_MLO_SW_MSG_STATUS_E = 327 , - WIFISCHEDULER_TXOP_DURATION_TRIGGER_E = 328 , - WIFITX_DATA_SYNC_E = 329 , - WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 330 , - WIFITQM_GET_MPDU_HEAD_INFO_E = 331 , - WIFITQM_SYNC_CMD_E = 332 , - WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 333 , - WIFITQM_SYNC_CMD_STATUS_E = 334 , - WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 335 , - WIFITCC_TQM_WRAPPER_CMD_E = 336 , - WIFIREO_FLUSH_TIMEOUT_LIST_E = 337 , - WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 338 , - WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 339 , - WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 340 , - WIFIEXAMPLE_USER_TLV_32_NAME_E = 341 , - WIFIRX_PPDU_START_USER_INFO_E = 342 , - WIFIRX_RING_MASK_E = 343 , - WIFICOEX_MAC_NAP_E = 344 , - WIFIRXPCU_PPDU_END_INFO_E = 345 , - WIFIWHO_MESH_CONTROL_E = 346 , - WIFIPDG_SW_MODE_BW_START_E = 347 , - WIFIPDG_SW_MODE_BW_END_E = 348 , - WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 349 , - WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 350 , - WIFISCHEDULER_END_E = 351 , - WIFIRX_PPDU_START_DROPPED_E = 352 , - WIFIRX_PPDU_END_DROPPED_E = 353 , - WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 354 , - WIFIRX_MPDU_START_DROPPED_E = 355 , - WIFIRX_MSDU_START_DROPPED_E = 356 , - WIFIRX_MSDU_END_DROPPED_E = 357 , - WIFIRX_MPDU_END_DROPPED_E = 358 , - WIFIRX_ATTENTION_DROPPED_E = 359 , - WIFITXPCU_USER_SETUP_E = 360 , - WIFIRXPCU_USER_SETUP_EXT_E = 361 , - WIFICMD_PART_0_END_E = 362 , - WIFIMACTX_SYNTH_ON_E = 363 , - WIFISCH_CRITICAL_TLV_REFERENCE_E = 364 , - WIFITQM_MPDU_GLOBAL_START_E = 365 , - WIFIEXAMPLE_TLV_32_E = 366 , - WIFITQM_UPDATE_TX_MSDU_FLOW_E = 367 , - WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 368 , - WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 369 , - WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 370 , - WIFIREO_UPDATE_RX_REO_QUEUE_E = 371 , - WIFITQM_2_SCH_MPDU_AVAILABLE_E = 372 , - WIFIPDG_TRIG_RESPONSE_E = 373 , - WIFITRIGGER_RESPONSE_TX_DONE_E = 374 , - WIFIABORT_FROM_PHYRX_DETAILS_E = 375 , - WIFISCH_TQM_CMD_WRAPPER_E = 376 , - WIFIMPDUS_AVAILABLE_E = 377 , - WIFIRECEIVED_RESPONSE_INFO_PART2_E = 378 , - WIFIPHYRX_TX_START_TIMING_E = 379 , - WIFITXPCU_PREAMBLE_DONE_E = 380 , - WIFINDP_PREAMBLE_DONE_E = 381 , - WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 382 , - WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 383 , - WIFIMACTX_CLEAR_PREV_TX_INFO_E = 384 , - WIFITX_PUNCTURE_SETUP_E = 385 , - WIFIR2R_STATUS_END_E = 386 , - WIFIMACTX_PREFETCH_CV_COMMON_E = 387 , - WIFIEND_OF_FLUSH_MARKER_E = 388 , - WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 389 , - WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 390 , - WIFIRECEIVED_RESPONSE_USER_7_0_E = 391 , - WIFIRECEIVED_RESPONSE_USER_15_8_E = 392 , - WIFIRECEIVED_RESPONSE_USER_23_16_E = 393 , - WIFIRECEIVED_RESPONSE_USER_31_24_E = 394 , - WIFIRECEIVED_RESPONSE_USER_36_32_E = 395 , - WIFITX_LOOPBACK_SETUP_E = 396 , - WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 397 , - WIFISCH_WAIT_INSTR_TX_PATH_E = 398 , - WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 399 , - WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 400 , - WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 401 , - WIFITX_WUR_DATA_E = 402 , - WIFIRX_PPDU_END_START_E = 403 , - WIFIRX_PPDU_END_MIDDLE_E = 404 , - WIFIRX_PPDU_END_LAST_E = 405 , - WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 406 , - WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 407 , - WIFISRP_INFO_E = 408 , - WIFIOBSS_SR_INFO_E = 409 , - WIFISCHEDULER_SW_MSG_STATUS_E = 410 , - WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 411 , - WIFIRXPCU_SETUP_COMPLETE_E = 412 , - WIFIMACTX_MCC_SWITCH_E = 413 , - WIFIMACTX_MCC_SWITCH_BACK_E = 414 , - WIFIPHYTX_MCC_SWITCH_ACK_E = 415 , - WIFIPHYTX_MCC_SWITCH_BACK_ACK_E = 416 , - WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E = 417 , - WIFILMR_TX_END_E = 418 , - WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 419 , - WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 420 , - WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 421 , - WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 422 , - WIFISCH_TLV_WRAPPER_E = 423 , - WIFISCHEDULER_STATUS_WRAPPER_E = 424 , - WIFIMPDU_INFO_6X_E = 425 , - WIFIMACTX___RESERVED_G_0013 = 426 , - WIFIMACTX_U_SIG_EHT_SU_MU_E = 427 , - WIFIMACTX_U_SIG_EHT_TB_E = 428 , - WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E = 429 , - WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E = 430 , - WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E = 431 , - WIFIPHYRX_U_SIG_EHT_SU_MU_E = 432 , - WIFIPHYRX_U_SIG_EHT_TB_E = 433 , - WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E = 434 , - WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 435 , - WIFITX_PUNCTURE_6PATTERNS_SETUP_E = 436 , - WIFIMACRX_LMR_READ_REQUEST_E = 437 , - WIFIMACRX_LMR_DATA_REQUEST_E = 438 , - WIFIPHYRX_LMR_TRANSFER_DONE_E = 439 , - WIFIPHYRX_LMR_TRANSFER_ABORT_E = 440 , - WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 441 , - WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 442 , - WIFIPHYRX_USER_INFO_MU_UL_E = 443 , - WIFIMPDU_QUEUE_OVERVIEW_E = 444 , - WIFISCHEDULER_NAV_INFO_E = 445 , - WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 446 , - WIFILMR_PEER_ENTRY_E = 447 , - WIFILMR_MPDU_START_E = 448 , - WIFILMR_DATA_E = 449 , - WIFILMR_MPDU_END_E = 450 , - WIFIREO_GET_QUEUE_1K_STATS_STATUS_E = 451 , - WIFIRX_FRAME_1K_BITMAP_ACK_E = 452 , - WIFITX_FES_STATUS_1K_BA_E = 453 , - WIFITQM_ACKED_1K_MPDU_E = 454 , - WIFIMACRX_INBSS_OBSS_IND_E = 455 , - WIFIPHYRX_LOCATION_E = 456 , - WIFIMLO_TX_NOTIFICATION_SU_E = 457 , - WIFIMLO_TX_NOTIFICATION_MU_E = 458 , - WIFIMLO_TX_REQ_SU_E = 459 , - WIFIMLO_TX_REQ_MU_E = 460 , - WIFIMLO_TX_RESP_E = 461 , - WIFIMLO_RX_NOTIFICATION_E = 462 , - WIFIMLO_BKOFF_TRUNC_REQ_E = 463 , - WIFIMLO_TBTT_NOTIFICATION_E = 464 , - WIFIMLO_MESSAGE_E = 465 , - WIFIMLO_TS_SYNC_MSG_E = 466 , - WIFIMLO_FES_SETUP_E = 467 , - WIFIMLO_PDG_FES_SETUP_SU_E = 468 , - WIFIMLO_PDG_FES_SETUP_MU_E = 469 , - WIFIMPDU_INFO_1K_BITMAP_E = 470 , - WIFIMON_BUFFER_ADDR_E = 471 , - WIFITX_FRAG_STATE_E = 472 , - WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 473 , - WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 474 , - WIFIMACTX_EHT_SIG_USR_OFDMA_E = 475 , - WIFIMACTX_U_SIG_UHR_SU_MU_E = 476 , - WIFIMACTX_U_SIG_UHR_TB_E = 477 , - WIFITX_MPDU_COMPRESSED_DETAILS_TLV_E = 478 , - WIFITX_MSDU_COMPRESSED_DETAILS_TLV_E = 479 , - WIFITX_MSDU_COMPONENT_DETAILS_TLV_E = 480 , - WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 481 , - WIFISCHEDULER_IU_TEMPLATE_ID_E = 482 , - WIFIPHYRX_PKT_END_PART1_E = 483 , - WIFIMACTX_EXPECT_NDP_RECEPTION_E = 484 , - WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 485 , - WIFITX_MPDU_LENGTH_AND_RESTRICTIONS_E = 486 , - WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 487 , - WIFIPHYRX___RESERVED_G_0014 = 488 , - WIFIPHYTX_LOCATION_E = 489 , - WIFIPHYTX___RESERVED_G_0014 = 490 , - WIFIMPDU_LENGTH_STRUCTS_START_E = 491 , - WIFIMACTX_EHT_SIG_USR_SU_E = 492 , - WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 493 , - WIFIPHYRX_EHT_SIG_USR_SU_E = 494 , - WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 495 , - WIFIPHYRX_GENERIC_U_SIG_E = 496 , - WIFIPHYRX_GENERIC_EHT_OR_UHR_SIG_E = 497 , - WIFIOVERWRITE_RESP_START_E = 498 , - WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 499 , - WIFIOVERWRITE_RESP_FRAME_INFO_E = 500 , - WIFIOVERWRITE_RESP_END_E = 501 , - WIFIRXPCU_EARLY_RX_INDICATION_E = 502 , - WIFIMON_DROP_E = 503 , - WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 504 , - WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 505 , - WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 506 , - WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 507 , - WIFIMACTX_PREFETCH_CV_DMA_E = 508 , - WIFIMACTX_PREFETCH_CV_PER_USER_E = 509 , - WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 510 , - WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 511 , - WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 512 , - WIFIRANGING_USER_DETAILS_E = 513 , - WIFIPHYTX_CV_CORR_STATUS_E = 514 , - WIFIPHYTX_CV_CORR_COMMON_E = 515 , - WIFIPHYTX_CV_CORR_USER_E = 516 , - WIFIMACTX_CV_CORR_COMMON_E = 517 , - WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 518 , - WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 519 , - WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 520 , - WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 521 , - WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 522 , - WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 523 , - WIFIRX_PPDU_END_USER_STATS_EXT2_E = 524 , - WIFIFW2SW_MON_E = 525 , - WIFIWSI_DIRECT_MESSAGE_E = 526 , - WIFIMACTX_EMLSR_PRE_SWITCH_E = 527 , - WIFIMACTX_EMLSR_SWITCH_E = 528 , - WIFIMACTX_EMLSR_SWITCH_BACK_E = 529 , - WIFIPHYTX_EMLSR_SWITCH_ACK_E = 530 , - WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 531 , - WIFIEAD_COMMAND_E = 532 , - WIFIEAD_LEGACY_STATUS_CONTROL_E = 533 , - WIFIEAD_LEGACY_INTERRUPT_CONTROL_E = 534 , - WIFITPI_TX_INITIALIZATION_CONFIG_E = 535 , - WIFITPI_ENABLE_RESPONSE_TIMEOUT_E = 536 , - WIFITPI_LEGACY_STATUS_CONTROL_E = 537 , - WIFITPI_LEGACY_INTERRUPT_CONTROL_E = 538 , - WIFITPI_MPDU_START_E = 539 , - WIFITPI_MPDU_CONTINUATION_E = 540 , - WIFITPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E = 541 , - WIFITPI_SEND_TLV_TO_PHYTX_E = 542 , - WIFITPI_TX_START_TIME_ARRIVED_E = 543 , - WIFITPI_STATUS_E = 544 , - WIFITPI_ERROR_STATUS_E = 545 , - WIFITPI_TIMESTAMP_STATUS_E = 546 , - WIFIRPI_SEND_TLV_TO_PHYRX_E = 547 , - WIFIRPI_LEGACY_STATUS_CONTROL_E = 548 , - WIFIRPI_LEGACY_INTERRUPT_CONTROL_E = 549 , - WIFIRPI_STATUS_E = 550 , - WIFIRPI_ERROR_STATUS_E = 551 , - WIFIRPI_TIMESTAMP_STATUS_E = 552 , - WIFIRPI_RX_FRAME_UPDATE_STATUS_E = 553 , - WIFITCC_PUSH_TRANSMIT_COMMAND_E = 554 , - WIFITCC_TLV_FETCH_E = 555 , - WIFITCC_LEGACY_STATUS_CONTROL_E = 556 , - WIFITCC_LEGACY_INTERRUPT_CONTROL_E = 557 , - WIFITCC_STATUS_E = 558 , - WIFITCC_ERROR_STATUS_E = 559 , - WIFITCC_TIMESTAMP_STATUS_E = 560 , - WIFITCC_PRE_BACKOFF_CMD_AVAILABLE_E = 561 , - WIFITCC_SCHEDULER_CMD_E = 562 , - WIFITCC_BURST_CMD_AVAILABLE_E = 563 , - WIFIRPI_NON_DATA_CTLV_44_FROM_PHYRX_E = 564 , - WIFIEAD_RING_AIR_TIME_REFERENCE_E = 565 , - WIFIRPI_FETCH_INFO_FROM_EXT_MEM_E = 566 , - WIFIRPI_WRITE_INFO_TO_EXT_MEM_E = 567 , - WIFIRPI_INIT_CBF_DATA_RESP_ADDR_E = 568 , - WIFIRPI_INIT_LMR_DATA_RESP_ADDR_E = 569 , - WIFITPI_SEND_CBF_DATA_TO_PHYTX_E = 570 , - WIFITPI_SEND_CTLV_44_TO_PHYTX_E = 571 , - WIFITCC_FES_END_MESSAGE_E = 572 , - WIFITPI_TX_FRAME_UPDATE_STATUS_E = 573 , - WIFITPI_DISABLE_RESPONSE_TIMEOUT_E = 574 , - WIFIEAD_MPDU_DATA_FETCH_CONTINUATION_E = 575 , - WIFIEAD_MSDU_STATUS_START_E = 576 , - WIFIEAD_MSDU_STATUS_DETAILS_E = 577 , - WIFIMACTX_UHR_SIG_USR_SU_E = 578 , - WIFIMACTX_UHR_SIG_USR_MU_MIMO_E = 579 , - WIFIMACTX_UHR_SIG_USR_OFDMA_E = 580 , - WIFIMACTX_ELR_SIG_UHR_SU_E = 581 , - WIFICOEX_BLACKOUT_DETAILS_E = 582 , - WIFIPEER_BLACKOUT_DETAILS_E = 583 , - WIFIMACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E = 584 , - WIFIHDR_CTRL_PROT_PEER_ENTRY_E = 585 , - WIFIHDR_CTRL_PROT_MPDU_START_E = 586 , - WIFIHDR_CTRL_PROT_DATA_E = 587 , - WIFIHDR_CTRL_PROT_MPDU_END_E = 588 , - WIFIHDR_CTRL_PROT_MIC_STATUS_E = 589 , - WIFIHDR_CTRL_PROT_PEER_INFO_E = 590 , - WIFIHDR_CTRL_PROT_PEER_ENTRY_DONE_E = 591 , - WIFIMACTX_U_SIG_UHR_ELR_SU_E = 592 , - WIFIMACTX_U_SIG_UHR_COBF_E = 593 , - WIFIMACTX_UHR_SIG_USR_COBF_E = 594 , - WIFISPARE_REUSE_TAG_0_E = 595 , - WIFISPARE_REUSE_TAG_1_E = 596 , - WIFISPARE_REUSE_TAG_2_E = 597 , - WIFISPARE_REUSE_TAG_3_E = 598 , - WIFISPARE_REUSE_TAG_4_E = 599 , - WIFISPARE_REUSE_TAG_5_E = 600 , - WIFISPARE_REUSE_TAG_6_E = 601 , - WIFISPARE_REUSE_TAG_7_E = 602 , - WIFISPARE_REUSE_TAG_8_E = 603 , - WIFISPARE_REUSE_TAG_9_E = 604 , - WIFISPARE_REUSE_TAG_10_E = 605 , - WIFISPARE_REUSE_TAG_11_E = 606 , - WIFISPARE_REUSE_TAG_12_E = 607 , - WIFISPARE_REUSE_TAG_13_E = 608 , - WIFISPARE_REUSE_TAG_14_E = 609 , - WIFISPARE_REUSE_TAG_15_E = 610 , - WIFISPARE_REUSE_TAG_16_E = 611 , - WIFISPARE_REUSE_TAG_17_E = 612 , - WIFISPARE_REUSE_TAG_18_E = 613 , - WIFISPARE_REUSE_TAG_19_E = 614 , - WIFISPARE_REUSE_TAG_20_E = 615 , - WIFISPARE_REUSE_TAG_21_E = 616 , - WIFISPARE_REUSE_TAG_22_E = 617 , - WIFISPARE_REUSE_TAG_23_E = 618 , - WIFISPARE_REUSE_TAG_24_E = 619 , - WIFISPARE_REUSE_TAG_25_E = 620 , - WIFISPARE_REUSE_TAG_26_E = 621 , - WIFISPARE_REUSE_TAG_27_E = 622 , - WIFISPARE_REUSE_TAG_28_E = 623 , - WIFISPARE_REUSE_TAG_29_E = 624 , - WIFISPARE_REUSE_TAG_30_E = 625 , - WIFISPARE_REUSE_TAG_31_E = 626 , - WIFISPARE_REUSE_TAG_32_E = 627 , - WIFISPARE_REUSE_TAG_33_E = 628 , - WIFISPARE_REUSE_TAG_34_E = 629 , - WIFISPARE_REUSE_TAG_35_E = 630 , - WIFISPARE_REUSE_TAG_36_E = 631 , - WIFISPARE_REUSE_TAG_37_E = 632 , - WIFISPARE_REUSE_TAG_38_E = 633 , - WIFISPARE_REUSE_TAG_39_E = 634 , - WIFISPARE_REUSE_TAG_40_E = 635 , - WIFISPARE_REUSE_TAG_41_E = 636 , - WIFISPARE_REUSE_TAG_42_E = 637 , - WIFISPARE_REUSE_TAG_43_E = 638 , - WIFISPARE_REUSE_TAG_44_E = 639 , - WIFISPARE_REUSE_TAG_45_E = 640 , - WIFISPARE_REUSE_TAG_46_E = 641 , - WIFISPARE_REUSE_TAG_47_E = 642 , - WIFISPARE_REUSE_TAG_48_E = 643 , - WIFISPARE_REUSE_TAG_49_E = 644 , - WIFISPARE_REUSE_TAG_50_E = 645 , - WIFISPARE_REUSE_TAG_51_E = 646 , - WIFISPARE_REUSE_TAG_52_E = 647 , - WIFISPARE_REUSE_TAG_53_E = 648 , - WIFISPARE_REUSE_TAG_54_E = 649 , - WIFISPARE_REUSE_TAG_55_E = 650 , - WIFISPARE_REUSE_TAG_56_E = 651 , - WIFISPARE_REUSE_TAG_57_E = 652 , - WIFISPARE_REUSE_TAG_58_E = 653 , - WIFISPARE_REUSE_TAG_59_E = 654 , - WIFISPARE_REUSE_TAG_60_E = 655 , - WIFISPARE_REUSE_TAG_61_E = 656 , - WIFISPARE_REUSE_TAG_62_E = 657 , - WIFISPARE_REUSE_TAG_63_E = 658 , - WIFISPARE_REUSE_TAG_64_E = 659 , - WIFISPARE_REUSE_TAG_65_E = 660 , - WIFISPARE_REUSE_TAG_66_E = 661 , - WIFISPARE_REUSE_TAG_67_E = 662 , - WIFISPARE_REUSE_TAG_68_E = 663 , - WIFISPARE_REUSE_TAG_69_E = 664 , - WIFISPARE_REUSE_TAG_70_E = 665 , - WIFISPARE_REUSE_TAG_71_E = 666 , - WIFISPARE_REUSE_TAG_72_E = 667 , - WIFISPARE_REUSE_TAG_73_E = 668 , - WIFISPARE_REUSE_TAG_74_E = 669 , - WIFISPARE_REUSE_TAG_75_E = 670 , - WIFISPARE_REUSE_TAG_76_E = 671 , - WIFISPARE_REUSE_TAG_77_E = 672 , - WIFISPARE_REUSE_TAG_78_E = 673 , - WIFISPARE_REUSE_TAG_79_E = 674 , - WIFISPARE_REUSE_TAG_80_E = 675 , - WIFISPARE_REUSE_TAG_81_E = 676 , - WIFISPARE_REUSE_TAG_82_E = 677 , - WIFISPARE_REUSE_TAG_83_E = 678 , - WIFISPARE_REUSE_TAG_84_E = 679 , - WIFISPARE_REUSE_TAG_85_E = 680 , - WIFISPARE_REUSE_TAG_86_E = 681 , - WIFISPARE_REUSE_TAG_87_E = 682 , - WIFISPARE_REUSE_TAG_88_E = 683 , - WIFISPARE_REUSE_TAG_89_E = 684 , - WIFISPARE_REUSE_TAG_90_E = 685 , - WIFISPARE_REUSE_TAG_91_E = 686 , - WIFISPARE_REUSE_TAG_92_E = 687 , - WIFISPARE_REUSE_TAG_93_E = 688 , - WIFISPARE_REUSE_TAG_94_E = 689 , - WIFISPARE_REUSE_TAG_95_E = 690 , - WIFISPARE_REUSE_TAG_96_E = 691 , - WIFISPARE_REUSE_TAG_97_E = 692 , - WIFISPARE_REUSE_TAG_98_E = 693 , - WIFISPARE_REUSE_TAG_99_E = 694 , - WIFISPARE_REUSE_TAG_100_E = 695 , - WIFISPARE_REUSE_TAG_101_E = 696 , - WIFISPARE_REUSE_TAG_102_E = 697 , - WIFISPARE_REUSE_TAG_103_E = 698 , - WIFISPARE_REUSE_TAG_104_E = 699 , - WIFISPARE_REUSE_TAG_105_E = 700 , - WIFISPARE_REUSE_TAG_106_E = 701 , - WIFISPARE_REUSE_TAG_107_E = 702 , - WIFISPARE_REUSE_TAG_108_E = 703 , - WIFISPARE_REUSE_TAG_109_E = 704 , - WIFISPARE_REUSE_TAG_110_E = 705 , - WIFISPARE_REUSE_TAG_111_E = 706 , - WIFISPARE_REUSE_TAG_112_E = 707 , - WIFISPARE_REUSE_TAG_113_E = 708 , - WIFISPARE_REUSE_TAG_114_E = 709 , - WIFISPARE_REUSE_TAG_115_E = 710 , - WIFISPARE_REUSE_TAG_116_E = 711 , - WIFISPARE_REUSE_TAG_117_E = 712 , - WIFISPARE_REUSE_TAG_118_E = 713 , - WIFISPARE_REUSE_TAG_119_E = 714 , - WIFISPARE_REUSE_TAG_120_E = 715 , - WIFISPARE_REUSE_TAG_121_E = 716 , - WIFISPARE_REUSE_TAG_122_E = 717 , - WIFISPARE_REUSE_TAG_123_E = 718 , - WIFISPARE_REUSE_TAG_124_E = 719 , - WIFISPARE_REUSE_TAG_125_E = 720 , - WIFISPARE_REUSE_TAG_126_E = 721 , - WIFISPARE_REUSE_TAG_127_E = 722 , - WIFISPARE_REUSE_TAG_128_E = 723 , - WIFISPARE_REUSE_TAG_129_E = 724 , - WIFISPARE_REUSE_TAG_130_E = 725 , - WIFISPARE_REUSE_TAG_131_E = 726 , - WIFISPARE_REUSE_TAG_132_E = 727 , - WIFISPARE_REUSE_TAG_133_E = 728 , - WIFISPARE_REUSE_TAG_134_E = 729 , - WIFISPARE_REUSE_TAG_135_E = 730 , - WIFISPARE_REUSE_TAG_136_E = 731 , - WIFISPARE_REUSE_TAG_137_E = 732 , - WIFISPARE_REUSE_TAG_138_E = 733 , - WIFISPARE_REUSE_TAG_139_E = 734 , - WIFISPARE_REUSE_TAG_140_E = 735 , - WIFISPARE_REUSE_TAG_141_E = 736 , - WIFISPARE_REUSE_TAG_142_E = 737 , - WIFISPARE_REUSE_TAG_143_E = 738 , - WIFISPARE_REUSE_TAG_144_E = 739 , - WIFISPARE_REUSE_TAG_145_E = 740 , - WIFISPARE_REUSE_TAG_146_E = 741 , - WIFISPARE_REUSE_TAG_147_E = 742 , - WIFISPARE_REUSE_TAG_148_E = 743 , - WIFISPARE_REUSE_TAG_149_E = 744 , - WIFISPARE_REUSE_TAG_150_E = 745 , - WIFISPARE_REUSE_TAG_151_E = 746 , - WIFISPARE_REUSE_TAG_152_E = 747 , - WIFISPARE_REUSE_TAG_153_E = 748 , - WIFISPARE_REUSE_TAG_154_E = 749 , - WIFISPARE_REUSE_TAG_155_E = 750 , - WIFISPARE_REUSE_TAG_156_E = 751 , - WIFISPARE_REUSE_TAG_157_E = 752 , - WIFISPARE_REUSE_TAG_158_E = 753 , - WIFISPARE_REUSE_TAG_159_E = 754 , - WIFISPARE_REUSE_TAG_160_E = 755 , - WIFISPARE_REUSE_TAG_161_E = 756 , - WIFISPARE_REUSE_TAG_162_E = 757 , - WIFISPARE_REUSE_TAG_163_E = 758 , - WIFISPARE_REUSE_TAG_164_E = 759 , - WIFISPARE_REUSE_TAG_165_E = 760 , - WIFISPARE_REUSE_TAG_166_E = 761 , - WIFISPARE_REUSE_TAG_167_E = 762 , - WIFISPARE_REUSE_TAG_168_E = 763 , - WIFISPARE_REUSE_TAG_169_E = 764 , - WIFISPARE_REUSE_TAG_170_E = 765 , - WIFISPARE_REUSE_TAG_171_E = 766 , - WIFISPARE_REUSE_TAG_172_E = 767 , - WIFISPARE_REUSE_TAG_173_E = 768 , - WIFISPARE_REUSE_TAG_174_E = 769 , - WIFISPARE_REUSE_TAG_175_E = 770 , - WIFISPARE_REUSE_TAG_176_E = 771 , - WIFISPARE_REUSE_TAG_177_E = 772 , - WIFISPARE_REUSE_TAG_178_E = 773 , - WIFISPARE_REUSE_TAG_179_E = 774 , - WIFISPARE_REUSE_TAG_180_E = 775 , - WIFISPARE_REUSE_TAG_181_E = 776 , - WIFISPARE_REUSE_TAG_182_E = 777 , - WIFISPARE_REUSE_TAG_183_E = 778 , - WIFISPARE_REUSE_TAG_184_E = 779 , - WIFISPARE_REUSE_TAG_185_E = 780 , - WIFISPARE_REUSE_TAG_186_E = 781 , - WIFISPARE_REUSE_TAG_187_E = 782 , - WIFISPARE_REUSE_TAG_188_E = 783 , - WIFISPARE_REUSE_TAG_189_E = 784 , - WIFISPARE_REUSE_TAG_190_E = 785 , - WIFISPARE_REUSE_TAG_191_E = 786 , - WIFISPARE_REUSE_TAG_192_E = 787 , - WIFISPARE_REUSE_TAG_193_E = 788 , - WIFISPARE_REUSE_TAG_194_E = 789 , - WIFISPARE_REUSE_TAG_195_E = 790 , - WIFISPARE_REUSE_TAG_196_E = 791 , - WIFISPARE_REUSE_TAG_197_E = 792 , - WIFISPARE_REUSE_TAG_198_E = 793 , - WIFISPARE_REUSE_TAG_199_E = 794 , - WIFISPARE_REUSE_TAG_200_E = 795 , - WIFISPARE_REUSE_TAG_201_E = 796 , - WIFISPARE_REUSE_TAG_202_E = 797 , - WIFISPARE_REUSE_TAG_203_E = 798 , - WIFISPARE_REUSE_TAG_204_E = 799 , - WIFISPARE_REUSE_TAG_205_E = 800 , - WIFISPARE_REUSE_TAG_206_E = 801 , - WIFISPARE_REUSE_TAG_207_E = 802 , - WIFISPARE_REUSE_TAG_208_E = 803 , - WIFISPARE_REUSE_TAG_209_E = 804 , - WIFISPARE_REUSE_TAG_210_E = 805 , - WIFISPARE_REUSE_TAG_211_E = 806 , - WIFISPARE_REUSE_TAG_212_E = 807 , - WIFISPARE_REUSE_TAG_213_E = 808 , - WIFISPARE_REUSE_TAG_214_E = 809 , - WIFISPARE_REUSE_TAG_215_E = 810 , - WIFISPARE_REUSE_TAG_216_E = 811 , - WIFISPARE_REUSE_TAG_217_E = 812 , - WIFISPARE_REUSE_TAG_218_E = 813 , - WIFISPARE_REUSE_TAG_219_E = 814 , - WIFISPARE_REUSE_TAG_220_E = 815 , - WIFISPARE_REUSE_TAG_221_E = 816 , - WIFISPARE_REUSE_TAG_222_E = 817 , - WIFISPARE_REUSE_TAG_223_E = 818 , - WIFISPARE_REUSE_TAG_224_E = 819 , - WIFISPARE_REUSE_TAG_225_E = 820 , - WIFISPARE_REUSE_TAG_226_E = 821 , - WIFISPARE_REUSE_TAG_227_E = 822 , - WIFISPARE_REUSE_TAG_228_E = 823 , - WIFISPARE_REUSE_TAG_229_E = 824 , - WIFISPARE_REUSE_TAG_230_E = 825 , - WIFISPARE_REUSE_TAG_231_E = 826 , - WIFISPARE_REUSE_TAG_232_E = 827 , - WIFISPARE_REUSE_TAG_233_E = 828 , - WIFISPARE_REUSE_TAG_234_E = 829 , - WIFISPARE_REUSE_TAG_235_E = 830 , - WIFISPARE_REUSE_TAG_236_E = 831 , - WIFISPARE_REUSE_TAG_237_E = 832 , - WIFISPARE_REUSE_TAG_238_E = 833 , - WIFISPARE_REUSE_TAG_239_E = 834 , - WIFISPARE_REUSE_TAG_240_E = 835 , - WIFISPARE_REUSE_TAG_241_E = 836 , - WIFISPARE_REUSE_TAG_242_E = 837 , - WIFISPARE_REUSE_TAG_243_E = 838 , - WIFISPARE_REUSE_TAG_244_E = 839 , - WIFISPARE_REUSE_TAG_245_E = 840 , - WIFISPARE_REUSE_TAG_246_E = 841 , - WIFISPARE_REUSE_TAG_247_E = 842 , - WIFISPARE_REUSE_TAG_248_E = 843 , - WIFISPARE_REUSE_TAG_249_E = 844 , - WIFISPARE_REUSE_TAG_250_E = 845 , - WIFISPARE_REUSE_TAG_251_E = 846 , - WIFISPARE_REUSE_TAG_252_E = 847 , - WIFISPARE_REUSE_TAG_253_E = 848 , - WIFISPARE_REUSE_TAG_254_E = 849 , - WIFISPARE_REUSE_TAG_255_E = 850 , - WIFISPARE_REUSE_TAG_256_E = 851 , - WIFISPARE_REUSE_TAG_257_E = 852 , - WIFISPARE_REUSE_TAG_258_E = 853 , - WIFISPARE_REUSE_TAG_259_E = 854 , - WIFISPARE_REUSE_TAG_260_E = 855 , - WIFISPARE_REUSE_TAG_261_E = 856 , - WIFISPARE_REUSE_TAG_262_E = 857 , - WIFISPARE_REUSE_TAG_263_E = 858 , - WIFISPARE_REUSE_TAG_264_E = 859 , - WIFISPARE_REUSE_TAG_265_E = 860 , - WIFISPARE_REUSE_TAG_266_E = 861 , - WIFISPARE_REUSE_TAG_267_E = 862 , - WIFISPARE_REUSE_TAG_268_E = 863 , - WIFISPARE_REUSE_TAG_269_E = 864 , - WIFISPARE_REUSE_TAG_270_E = 865 , - WIFISPARE_REUSE_TAG_271_E = 866 , - WIFISPARE_REUSE_TAG_272_E = 867 , - WIFISPARE_REUSE_TAG_273_E = 868 , - WIFISPARE_REUSE_TAG_274_E = 869 , - WIFISPARE_REUSE_TAG_275_E = 870 , - WIFISPARE_REUSE_TAG_276_E = 871 , - WIFISPARE_REUSE_TAG_277_E = 872 , - WIFISPARE_REUSE_TAG_278_E = 873 , - WIFISPARE_REUSE_TAG_279_E = 874 , - WIFISPARE_REUSE_TAG_280_E = 875 , - WIFISPARE_REUSE_TAG_281_E = 876 , - WIFISPARE_REUSE_TAG_282_E = 877 , - WIFISPARE_REUSE_TAG_283_E = 878 , - WIFISPARE_REUSE_TAG_284_E = 879 , - WIFISPARE_REUSE_TAG_285_E = 880 , - WIFISPARE_REUSE_TAG_286_E = 881 , - WIFISPARE_REUSE_TAG_287_E = 882 , - WIFISPARE_REUSE_TAG_288_E = 883 , - WIFISPARE_REUSE_TAG_289_E = 884 , - WIFISPARE_REUSE_TAG_290_E = 885 , - WIFISPARE_REUSE_TAG_291_E = 886 , - WIFISPARE_REUSE_TAG_292_E = 887 , - WIFISPARE_REUSE_TAG_293_E = 888 , - WIFISPARE_REUSE_TAG_294_E = 889 , - WIFISPARE_REUSE_TAG_295_E = 890 , - WIFISPARE_REUSE_TAG_296_E = 891 , - WIFISPARE_REUSE_TAG_297_E = 892 , - WIFISPARE_REUSE_TAG_298_E = 893 , - WIFISPARE_REUSE_TAG_299_E = 894 , - WIFISPARE_REUSE_TAG_300_E = 895 , - WIFISPARE_REUSE_TAG_301_E = 896 , - WIFISPARE_REUSE_TAG_302_E = 897 , - WIFISPARE_REUSE_TAG_303_E = 898 , - WIFISPARE_REUSE_TAG_304_E = 899 , - WIFISPARE_REUSE_TAG_305_E = 900 , - WIFISPARE_REUSE_TAG_306_E = 901 , - WIFISPARE_REUSE_TAG_307_E = 902 , - WIFISPARE_REUSE_TAG_308_E = 903 , - WIFISPARE_REUSE_TAG_309_E = 904 , - WIFISPARE_REUSE_TAG_310_E = 905 , - WIFISPARE_REUSE_TAG_311_E = 906 , - WIFISPARE_REUSE_TAG_312_E = 907 , - WIFISPARE_REUSE_TAG_313_E = 908 , - WIFISPARE_REUSE_TAG_314_E = 909 , - WIFISPARE_REUSE_TAG_315_E = 910 , - WIFISPARE_REUSE_TAG_316_E = 911 , - WIFISPARE_REUSE_TAG_317_E = 912 , - WIFISPARE_REUSE_TAG_318_E = 913 , - WIFISPARE_REUSE_TAG_319_E = 914 , - WIFISPARE_REUSE_TAG_320_E = 915 , - WIFISPARE_REUSE_TAG_321_E = 916 , - WIFISPARE_REUSE_TAG_322_E = 917 , - WIFISPARE_REUSE_TAG_323_E = 918 , - WIFISPARE_REUSE_TAG_324_E = 919 , - WIFISPARE_REUSE_TAG_325_E = 920 , - WIFISPARE_REUSE_TAG_326_E = 921 , - WIFISPARE_REUSE_TAG_327_E = 922 , - WIFISPARE_REUSE_TAG_328_E = 923 , - WIFISPARE_REUSE_TAG_329_E = 924 , - WIFISPARE_REUSE_TAG_330_E = 925 , - WIFISPARE_REUSE_TAG_331_E = 926 , - WIFISPARE_REUSE_TAG_332_E = 927 , - WIFISPARE_REUSE_TAG_333_E = 928 , - WIFISPARE_REUSE_TAG_334_E = 929 , - WIFISPARE_REUSE_TAG_335_E = 930 , - WIFISPARE_REUSE_TAG_336_E = 931 , - WIFISPARE_REUSE_TAG_337_E = 932 , - WIFISPARE_REUSE_TAG_338_E = 933 , - WIFISPARE_REUSE_TAG_339_E = 934 , - WIFISPARE_REUSE_TAG_340_E = 935 , - WIFISPARE_REUSE_TAG_341_E = 936 , - WIFISPARE_REUSE_TAG_342_E = 937 , - WIFISPARE_REUSE_TAG_343_E = 938 , - WIFISPARE_REUSE_TAG_344_E = 939 , - WIFISPARE_REUSE_TAG_345_E = 940 , - WIFISPARE_REUSE_TAG_346_E = 941 , - WIFISPARE_REUSE_TAG_347_E = 942 , - WIFISPARE_REUSE_TAG_348_E = 943 , - WIFISPARE_REUSE_TAG_349_E = 944 , - WIFISPARE_REUSE_TAG_350_E = 945 , - WIFISPARE_REUSE_TAG_351_E = 946 , - WIFISPARE_REUSE_TAG_352_E = 947 , - WIFISPARE_REUSE_TAG_353_E = 948 , - WIFISPARE_REUSE_TAG_354_E = 949 , - WIFISPARE_REUSE_TAG_355_E = 950 , - WIFISPARE_REUSE_TAG_356_E = 951 , - WIFISPARE_REUSE_TAG_357_E = 952 , - WIFISPARE_REUSE_TAG_358_E = 953 , - WIFISPARE_REUSE_TAG_359_E = 954 , - WIFISPARE_REUSE_TAG_360_E = 955 , - WIFISPARE_REUSE_TAG_361_E = 956 , - WIFISPARE_REUSE_TAG_362_E = 957 , - WIFISPARE_REUSE_TAG_363_E = 958 , - WIFISPARE_REUSE_TAG_364_E = 959 , - WIFISPARE_REUSE_TAG_365_E = 960 , - WIFISPARE_REUSE_TAG_366_E = 961 , - WIFISPARE_REUSE_TAG_367_E = 962 , - WIFISPARE_REUSE_TAG_368_E = 963 , - WIFISPARE_REUSE_TAG_369_E = 964 , - WIFISPARE_REUSE_TAG_370_E = 965 , - WIFISPARE_REUSE_TAG_371_E = 966 , - WIFISPARE_REUSE_TAG_372_E = 967 , - WIFISPARE_REUSE_TAG_373_E = 968 , - WIFISPARE_REUSE_TAG_374_E = 969 , - WIFISPARE_REUSE_TAG_375_E = 970 , - WIFISPARE_REUSE_TAG_376_E = 971 , - WIFISPARE_REUSE_TAG_377_E = 972 , - WIFISPARE_REUSE_TAG_378_E = 973 , - WIFISPARE_REUSE_TAG_379_E = 974 , - WIFISPARE_REUSE_TAG_380_E = 975 , - WIFISPARE_REUSE_TAG_381_E = 976 , - WIFISPARE_REUSE_TAG_382_E = 977 , - WIFISPARE_REUSE_TAG_383_E = 978 , - WIFISPARE_REUSE_TAG_384_E = 979 , - WIFISPARE_REUSE_TAG_385_E = 980 , - WIFISPARE_REUSE_TAG_386_E = 981 , - WIFISPARE_REUSE_TAG_387_E = 982 , - WIFISPARE_REUSE_TAG_388_E = 983 , - WIFISPARE_REUSE_TAG_389_E = 984 , - WIFISPARE_REUSE_TAG_390_E = 985 , - WIFISPARE_REUSE_TAG_391_E = 986 , - WIFISPARE_REUSE_TAG_392_E = 987 , - WIFISPARE_REUSE_TAG_393_E = 988 , - WIFISPARE_REUSE_TAG_394_E = 989 , - WIFISPARE_REUSE_TAG_395_E = 990 , - WIFISPARE_REUSE_TAG_396_E = 991 , - WIFISPARE_REUSE_TAG_397_E = 992 , - WIFISPARE_REUSE_TAG_398_E = 993 , - WIFISPARE_REUSE_TAG_399_E = 994 , - WIFISPARE_REUSE_TAG_400_E = 995 , - WIFISPARE_REUSE_TAG_401_E = 996 , - WIFISPARE_REUSE_TAG_402_E = 997 , - WIFISPARE_REUSE_TAG_403_E = 998 , - WIFISPARE_REUSE_TAG_404_E = 999 , - WIFISPARE_REUSE_TAG_405_E = 1000 , - WIFISPARE_REUSE_TAG_406_E = 1001 , - WIFISPARE_REUSE_TAG_407_E = 1002 , - WIFISPARE_REUSE_TAG_408_E = 1003 , - WIFISPARE_REUSE_TAG_409_E = 1004 , - WIFISPARE_REUSE_TAG_410_E = 1005 , - WIFISPARE_REUSE_TAG_411_E = 1006 , - WIFISPARE_REUSE_TAG_412_E = 1007 , - WIFISPARE_REUSE_TAG_413_E = 1008 , - WIFISPARE_REUSE_TAG_414_E = 1009 , - WIFISPARE_REUSE_TAG_415_E = 1010 , - WIFISPARE_REUSE_TAG_416_E = 1011 , - WIFISPARE_REUSE_TAG_417_E = 1012 , - WIFISPARE_REUSE_TAG_418_E = 1013 , - WIFISPARE_REUSE_TAG_419_E = 1014 , - WIFISPARE_REUSE_TAG_420_E = 1015 , - WIFISPARE_REUSE_TAG_421_E = 1016 , - WIFISPARE_REUSE_TAG_422_E = 1017 , - WIFISPARE_REUSE_TAG_423_E = 1018 , - WIFISPARE_REUSE_TAG_424_E = 1019 , - WIFISPARE_REUSE_TAG_425_E = 1020 , - WIFISPARE_REUSE_TAG_426_E = 1021 -} tlv_tag_def__e; - -typedef enum { - WIFI_EXT_PHYRX_DATA_E = 1 , - WIFI_EXT_PHYRX_ABORT_REQUEST_E = 3 , - WIFI_EXT_MACTX_DATA_RESP_E = 5 , - WIFI_EXT_MACTX_CBF_DONE_E = 7 , - WIFI_EXT_RXPCU_TO_UCODE_START_E = 9 , - WIFI_EXT_RXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , - WIFI_EXT_RXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , - WIFI_EXT_RXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , - WIFI_EXT_PHYRX_RSSI_LEGACY_20MHZ_E = 17 , - WIFI_EXT_PHYRX_PKT_END_20MHZ_E = 19 , - WIFI_EXT_MACRX_CBF_DATA_REQUEST_E = 65 , - WIFI_EXT_MACRX_FREEZE_CAPTURE_CHANNEL_E = 67 , - WIFI_EXT_MACRX_ABORT_ACK_E = 69 , - WIFI_EXT_MACRX_CHAIN_MASK_E = 71 , - WIFI_EXT_MACRX_ABORT_REQUEST_E = 73 , - WIFI_EXT_PHYTX_ABORT_ACK_E = 75 , - WIFI_EXT_PHYTX_PKT_END_E = 77 , - WIFI_EXT_PHYTX_REQUEST_CTRL_INFO_E = 79 , - WIFI_EXT_PHYTX_BF_CV_LOADING_DONE_E = 81 , - WIFI_EXT_PHYTX_NAP_DONE_E = 83 , - WIFI_EXT_PHYTX_ON_ACK_E = 85 , - WIFI_EXT_PHYTX_DEBUG16_E = 87 , - WIFI_EXT_MACTX_ABORT_ACK_E = 89 , - WIFI_EXT_MACTX_PRE_PHY_DESC_E = 91 , - WIFI_EXT_MACTX_BF_PARAMS_PER_USER_E = 93 , - WIFI_EXT_MACTX_USER_DESC_COMMON_E = 95 , - WIFI_EXT_EXAMPLE_USER_TLV_16_E = 97 , - WIFI_EXT_MACTX_PHY_OFF_E = 99 , - WIFI_EXT_MACTX_SYNTH_OFF_E = 101 , - WIFI_EXT_MACTX_EXPECT_CBF_PER_USER_E = 103 , - WIFI_EXT_MACTX_L_SIG_A_E = 105 , - WIFI_EXT_MACTX_HT_SIG_E = 107 , - WIFI_EXT_MACTX_VHT_SIG_B_SU20_E = 109 , - WIFI_EXT_MACTX_VHT_SIG_B_SU80_E = 111 , - WIFI_EXT_MACTX_VHT_SIG_B_MU20_E = 113 , - WIFI_EXT_MACTX_VHT_SIG_B_MU80_E = 115 , - WIFI_EXT_MACTX_SERVICE_E = 117 , - WIFI_EXT_MACTX_HE_SIG_A_MU_DL_E = 119 , - WIFI_EXT_MACTX_HE_SIG_B1_MU_E = 121 , - WIFI_EXT_MACTX_HE_SIG_B2_OFDMA_E = 123 , - WIFI_EXT_MACTX_MU_UPLINK_COMMON_E = 125 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_E = 127 , - WIFI_EXT_MACTX_DEBUG_E = 129 , - WIFI_EXT_PHYRX_GENERATED_CBF_DETAILS_E = 131 , - WIFI_EXT_PHYRX_RSSI_HT_E = 133 , - WIFI_EXT_PHYRX_PKT_END_E = 135 , - WIFI_EXT_PHYRX_CBF_TRANSFER_DONE_E = 137 , - WIFI_EXT_PHYRX_L_SIG_A_E = 139 , - WIFI_EXT_PHYRX_HT_SIG_E = 141 , - WIFI_EXT_PHYRX_VHT_SIG_B_SU20_E = 143 , - WIFI_EXT_PHYRX_VHT_SIG_B_SU80_E = 145 , - WIFI_EXT_PHYRX_VHT_SIG_B_MU20_E = 147 , - WIFI_EXT_PHYRX_VHT_SIG_B_MU80_E = 149 , - WIFI_EXT_PHYRX_HE_SIG_A_SU_E = 151 , - WIFI_EXT_PHYRX_HE_SIG_A_MU_UL_E = 153 , - WIFI_EXT_PHYRX_HE_SIG_B2_MU_E = 155 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_E = 157 , - WIFI_EXT_PHYRX_DATA_DONE_E = 159 , - WIFI_EXT_DUMMY_E = 161 , - WIFI_EXT_MPDU_LIMIT_E = 163 , - WIFI_EXT_OLE_BUF_STATUS_E = 165 , - WIFI_EXT_PCU_PPDU_SETUP_END_E = 167 , - WIFI_EXT_PCU_PPDU_SETUP_START_E = 169 , - WIFI_EXT_PDG_RESPONSE_E = 171 , - WIFI_EXT_SCH_WAIT_INSTR_E = 173 , - WIFI_EXT_PHYTX_LINK_STATE_E = 175 , - WIFI_EXT_TQM_GEN_MPDU_LENGTH_LIST_E = 177 , - WIFI_EXT_TQM_GEN_MPDUS_E = 179 , - WIFI_EXT_TQM_REMOVE_MPDU_E = 181 , - WIFI_EXT_TQM_REMOVE_MSDU_E = 183 , - WIFI_EXT_TQM_UPDATE_TX_MPDU_COUNT_E = 185 , - WIFI_EXT_OFDMA_TRIGGER_DETAILS_E = 187 , - WIFI_EXT_TX_FES_SETUP_E = 189 , - WIFI_EXT_EXPECTED_RESPONSE_E = 191 , - WIFI_EXT_TX_MPDU_START_E = 193 , - WIFI_EXT_TX_MSDU_START_E = 195 , - WIFI_EXT_TXPCU_BUFFER_STATUS_E = 197 , - WIFI_EXT_DATA_TO_TIME_CONFIG_E = 199 , - WIFI_EXT_MPDU_INFO_E = 201 , - WIFI_EXT_TX_11AH_SETUP_E = 203 , - WIFI_EXT_TX_PEER_ENTRY_E = 205 , - WIFI_EXT_EXAMPLE_USER_TLV_44_E = 207 , - WIFI_EXT_TX_FLUSH_REQ_E = 209 , - WIFI_EXT_TQM_GET_MPDU_QUEUE_STATS_E = 211 , - WIFI_EXT_EXAMPLE_USER_CTLV_44_E = 213 , - WIFI_EXT_TX_FES_STATUS_USER_PPDU_E = 215 , - WIFI_EXT_TX_FES_STATUS_END_E = 217 , - WIFI_EXT_RXPCU_TX_SETUP_CLEAR_E = 219 , - WIFI_EXT_RX_FRAME_BITMAP_ACK_E = 221 , - WIFI_EXT_RX_START_PARAM_E = 223 , - WIFI_EXT_RX_PPDU_END_E = 225 , - WIFI_EXT_RX_MPDU_END_E = 227 , - WIFI_EXT_RX_MSDU_END_E = 229 , - WIFI_EXT_RECEIVED_RESPONSE_INFO_E = 231 , - WIFI_EXT_RX_HEADER_E = 233 , - WIFI_EXT_RX_FLUSH_E = 235 , - WIFI_EXT_RX_FRAMELESS_BAR_DETAILS_E = 237 , - WIFI_EXT_TQM_GET_MSDU_FLOW_STATS_STATUS_E = 239 , - WIFI_EXT_PCU_PPDU_SETUP_USER_E = 241 , - WIFI_EXT_RX_PM_INFO_E = 243 , - WIFI_EXT_RX_PRE_PPDU_START_E = 245 , - WIFI_EXT_TX_FES_SETUP_COMPLETE_E = 247 , - WIFI_EXT_TXDMA_STOP_REQUEST_E = 249 , - WIFI_EXT_RXPCU_USER_SETUP_E = 251 , - WIFI_EXT_TQM_ACKED_MPDU_E = 253 , - WIFI_EXT_COEX_TX_STATUS_E = 255 , - WIFI_EXT_COEX_STATUS_BROADCAST_E = 257 , - WIFI_EXT_RESPONSE_END_STATUS_E = 259 , - WIFI_EXT_RECEIVED_TRIGGER_INFO_E = 261 , - WIFI_EXT_RX_PPDU_ACK_REPORT_E = 263 , - WIFI_EXT_SCH_COEX_STATUS_E = 265 , - WIFI_EXT_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 267 , - WIFI_EXT_TX_FES_STATUS_START_PPDU_E = 269 , - WIFI_EXT_TXPCU_PHYTX_DEBUG32_E = 271 , - WIFI_EXT_TX_MPDU_COUNT_TRANSFER_END_E = 273 , - WIFI_EXT_WHO_ANCHOR_VALUE_E = 275 , - WIFI_EXT_WHO_COMMIT_E = 277 , - WIFI_EXT_WHO_FLUSH_E = 279 , - WIFI_EXT_WHO_L2_PAYLOAD_E = 281 , - WIFI_EXT_WHO_L3_INFO_E = 283 , - WIFI_EXT_WHO_L4_INFO_E = 285 , - WIFI_EXT_WHO_MSDU_MISC_E = 287 , - WIFI_EXT_WHO_PACKET_HDR_E = 289 , - WIFI_EXT_WHO_PPDU_START_E = 291 , - WIFI_EXT_WHO_WMAC_HEADER_PV0_E = 293 , - WIFI_EXT_WHO_WMAC_IV_E = 295 , - WIFI_EXT_MPDU_INFO_BITMAP_E = 297 , - WIFI_EXT_SCHEDULER_SELFGEN_RESPONSE_STATUS_E = 299 , - WIFI_EXT_TQM_ACKED_MPDU_STATUS_E = 301 , - WIFI_EXT_TQM_LIST_GEN_DONE_E = 303 , - WIFI_EXT_TX_LAST_MPDU_END_E = 305 , - WIFI_EXT_PPDU_TX_END_E = 307 , - WIFI_EXT_MPDU_INFO_GLOBAL_END_E = 309 , - WIFI_EXT_RX_PPDU_END_USER_STATS_E = 311 , - WIFI_EXT_REO_GET_QUEUE_STATS_E = 313 , - WIFI_EXT_REO_FLUSH_CACHE_E = 315 , - WIFI_EXT_REO_GET_QUEUE_STATS_STATUS_E = 317 , - WIFI_EXT_REO_FLUSH_CACHE_STATUS_E = 319 , - WIFI_EXT_TQM_FLUSH_CACHE_E = 321 , - WIFI_EXT_TQM_FLUSH_CACHE_STATUS_E = 323 , - WIFI_EXT_RX_PPDU_END_STATUS_DONE_E = 325 , - WIFI_EXT_SCHEDULER_MLO_SW_MSG_STATUS_E = 327 , - WIFI_EXT_TX_DATA_SYNC_E = 329 , - WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_E = 331 , - WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_STATUS_E = 333 , - WIFI_EXT_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 335 , - WIFI_EXT_REO_FLUSH_TIMEOUT_LIST_E = 337 , - WIFI_EXT_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 339 , - WIFI_EXT_EXAMPLE_USER_TLV_32_NAME_E = 341 , - WIFI_EXT_RX_RING_MASK_E = 343 , - WIFI_EXT_RXPCU_PPDU_END_INFO_E = 345 , - WIFI_EXT_PDG_SW_MODE_BW_START_E = 347 , - WIFI_EXT_PDG_WAIT_FOR_MAC_REQUEST_E = 349 , - WIFI_EXT_SCHEDULER_END_E = 351 , - WIFI_EXT_RX_PPDU_END_DROPPED_E = 353 , - WIFI_EXT_RX_MPDU_START_DROPPED_E = 355 , - WIFI_EXT_RX_MSDU_END_DROPPED_E = 357 , - WIFI_EXT_RX_ATTENTION_DROPPED_E = 359 , - WIFI_EXT_RXPCU_USER_SETUP_EXT_E = 361 , - WIFI_EXT_MACTX_SYNTH_ON_E = 363 , - WIFI_EXT_TQM_MPDU_GLOBAL_START_E = 365 , - WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_E = 367 , - WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 369 , - WIFI_EXT_REO_UPDATE_RX_REO_QUEUE_E = 371 , - WIFI_EXT_PDG_TRIG_RESPONSE_E = 373 , - WIFI_EXT_ABORT_FROM_PHYRX_DETAILS_E = 375 , - WIFI_EXT_MPDUS_AVAILABLE_E = 377 , - WIFI_EXT_PHYRX_TX_START_TIMING_E = 379 , - WIFI_EXT_NDP_PREAMBLE_DONE_E = 381 , - WIFI_EXT_SCH_TQM_CMD_WRAPPER_CONT_DROP_E = 383 , - WIFI_EXT_TX_PUNCTURE_SETUP_E = 385 , - WIFI_EXT_MACTX_PREFETCH_CV_COMMON_E = 387 , - WIFI_EXT_MACTX_MU_UPLINK_COMMON_PUNC_E = 389 , - WIFI_EXT_RECEIVED_RESPONSE_USER_7_0_E = 391 , - WIFI_EXT_RECEIVED_RESPONSE_USER_23_16_E = 393 , - WIFI_EXT_RECEIVED_RESPONSE_USER_36_32_E = 395 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 397 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 399 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 401 , - WIFI_EXT_RX_PPDU_END_START_E = 403 , - WIFI_EXT_RX_PPDU_END_LAST_E = 405 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 407 , - WIFI_EXT_OBSS_SR_INFO_E = 409 , - WIFI_EXT_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 411 , - WIFI_EXT_MACTX_MCC_SWITCH_E = 413 , - WIFI_EXT_PHYTX_MCC_SWITCH_ACK_E = 415 , - WIFI_EXT_PHYTX_EMLSR_PRE_SWITCH_ACK_E = 417 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 419 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 421 , - WIFI_EXT_SCH_TLV_WRAPPER_E = 423 , - WIFI_EXT_MPDU_INFO_6X_E = 425 , - WIFI_EXT_MACTX_U_SIG_EHT_SU_MU_E = 427 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG0_CFG_E = 429 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG2_CFG_E = 431 , - WIFI_EXT_PHYRX_U_SIG_EHT_TB_E = 433 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 435 , - WIFI_EXT_MACRX_LMR_READ_REQUEST_E = 437 , - WIFI_EXT_PHYRX_LMR_TRANSFER_DONE_E = 439 , - WIFI_EXT_PHYRX_LMR_READ_REQUEST_ACK_E = 441 , - WIFI_EXT_PHYRX_USER_INFO_MU_UL_E = 443 , - WIFI_EXT_SCHEDULER_NAV_INFO_E = 445 , - WIFI_EXT_LMR_PEER_ENTRY_E = 447 , - WIFI_EXT_LMR_DATA_E = 449 , - WIFI_EXT_REO_GET_QUEUE_1K_STATS_STATUS_E = 451 , - WIFI_EXT_TX_FES_STATUS_1K_BA_E = 453 , - WIFI_EXT_MACRX_INBSS_OBSS_IND_E = 455 , - WIFI_EXT_MLO_TX_NOTIFICATION_SU_E = 457 , - WIFI_EXT_MLO_TX_REQ_SU_E = 459 , - WIFI_EXT_MLO_TX_RESP_E = 461 , - WIFI_EXT_MLO_BKOFF_TRUNC_REQ_E = 463 , - WIFI_EXT_MLO_MESSAGE_E = 465 , - WIFI_EXT_MLO_FES_SETUP_E = 467 , - WIFI_EXT_MLO_PDG_FES_SETUP_MU_E = 469 , - WIFI_EXT_MON_BUFFER_ADDR_E = 471 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 473 , - WIFI_EXT_MACTX_EHT_SIG_USR_OFDMA_E = 475 , - WIFI_EXT_MACTX_U_SIG_UHR_TB_E = 477 , - WIFI_EXT_TX_MSDU_COMPRESSED_DETAILS_TLV_E = 479 , - WIFI_EXT_PHYRX_EHT_SIG_USR_OFDMA_E = 481 , - WIFI_EXT_PHYRX_PKT_END_PART1_E = 483 , - WIFI_EXT_MACTX_SECURE_LTF_SEQ_PTR_E = 485 , - WIFI_EXT_MLO_PDG_BKOFF_TRUNC_NOTIFY_E = 487 , - WIFI_EXT_PHYTX_LOCATION_E = 489 , - WIFI_EXT_MPDU_LENGTH_STRUCTS_START_E = 491 , - WIFI_EXT_MACTX_EHT_SIG_USR_MU_MIMO_E = 493 , - WIFI_EXT_PHYRX_EHT_SIG_USR_MU_MIMO_E = 495 , - WIFI_EXT_PHYRX_GENERIC_EHT_OR_UHR_SIG_E = 497 , - WIFI_EXT_OVERWRITE_RESP_PREAMBLE_INFO_E = 499 , - WIFI_EXT_OVERWRITE_RESP_END_E = 501 , - WIFI_EXT_MON_DROP_E = 503 , - WIFI_EXT_MACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 505 , - WIFI_EXT_MACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 507 , - WIFI_EXT_MACTX_PREFETCH_CV_PER_USER_E = 509 , - WIFI_EXT_MACTX_BF_PARAMS_UPDATE_COMMON_E = 511 , - WIFI_EXT_RANGING_USER_DETAILS_E = 513 , - WIFI_EXT_PHYTX_CV_CORR_COMMON_E = 515 , - WIFI_EXT_MACTX_CV_CORR_COMMON_E = 517 , - WIFI_EXT_BW_PUNCTURE_EVAL_WRAPPER_E = 519 , - WIFI_EXT_MACTX_TX_NOTIFICATION_FOR_PHY_E = 521 , - WIFI_EXT_MACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 523 , - WIFI_EXT_FW2SW_MON_E = 525 , - WIFI_EXT_MACTX_EMLSR_PRE_SWITCH_E = 527 , - WIFI_EXT_MACTX_EMLSR_SWITCH_BACK_E = 529 , - WIFI_EXT_PHYTX_EMLSR_SWITCH_BACK_ACK_E = 531 , - WIFI_EXT_EAD_LEGACY_STATUS_CONTROL_E = 533 , - WIFI_EXT_TPI_TX_INITIALIZATION_CONFIG_E = 535 , - WIFI_EXT_TPI_LEGACY_STATUS_CONTROL_E = 537 , - WIFI_EXT_TPI_MPDU_START_E = 539 , - WIFI_EXT_TPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E = 541 , - WIFI_EXT_TPI_TX_START_TIME_ARRIVED_E = 543 , - WIFI_EXT_TPI_ERROR_STATUS_E = 545 , - WIFI_EXT_RPI_SEND_TLV_TO_PHYRX_E = 547 , - WIFI_EXT_RPI_LEGACY_INTERRUPT_CONTROL_E = 549 , - WIFI_EXT_RPI_ERROR_STATUS_E = 551 , - WIFI_EXT_RPI_RX_FRAME_UPDATE_STATUS_E = 553 , - WIFI_EXT_TCC_TLV_FETCH_E = 555 , - WIFI_EXT_TCC_LEGACY_INTERRUPT_CONTROL_E = 557 , - WIFI_EXT_TCC_ERROR_STATUS_E = 559 , - WIFI_EXT_TCC_PRE_BACKOFF_CMD_AVAILABLE_E = 561 , - WIFI_EXT_TCC_BURST_CMD_AVAILABLE_E = 563 , - WIFI_EXT_EAD_RING_AIR_TIME_REFERENCE_E = 565 , - WIFI_EXT_RPI_WRITE_INFO_TO_EXT_MEM_E = 567 , - WIFI_EXT_RPI_INIT_LMR_DATA_RESP_ADDR_E = 569 , - WIFI_EXT_TPI_SEND_CTLV_44_TO_PHYTX_E = 571 , - WIFI_EXT_TPI_TX_FRAME_UPDATE_STATUS_E = 573 , - WIFI_EXT_EAD_MPDU_DATA_FETCH_CONTINUATION_E = 575 , - WIFI_EXT_EAD_MSDU_STATUS_DETAILS_E = 577 , - WIFI_EXT_MACTX_UHR_SIG_USR_MU_MIMO_E = 579 , - WIFI_EXT_MACTX_ELR_SIG_UHR_SU_E = 581 , - WIFI_EXT_PEER_BLACKOUT_DETAILS_E = 583 , - WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_E = 585 , - WIFI_EXT_HDR_CTRL_PROT_DATA_E = 587 , - WIFI_EXT_HDR_CTRL_PROT_MIC_STATUS_E = 589 , - WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_DONE_E = 591 , - WIFI_EXT_MACTX_U_SIG_UHR_COBF_E = 593 , - WIFI_EXT_SPARE_REUSE_TAG_0_E = 595 , - WIFI_EXT_SPARE_REUSE_TAG_2_E = 597 , - WIFI_EXT_SPARE_REUSE_TAG_4_E = 599 , - WIFI_EXT_SPARE_REUSE_TAG_6_E = 601 , - WIFI_EXT_SPARE_REUSE_TAG_8_E = 603 , - WIFI_EXT_SPARE_REUSE_TAG_10_E = 605 , - WIFI_EXT_SPARE_REUSE_TAG_12_E = 607 , - WIFI_EXT_SPARE_REUSE_TAG_14_E = 609 , - WIFI_EXT_SPARE_REUSE_TAG_16_E = 611 , - WIFI_EXT_SPARE_REUSE_TAG_18_E = 613 , - WIFI_EXT_SPARE_REUSE_TAG_20_E = 615 , - WIFI_EXT_SPARE_REUSE_TAG_22_E = 617 , - WIFI_EXT_SPARE_REUSE_TAG_24_E = 619 , - WIFI_EXT_SPARE_REUSE_TAG_26_E = 621 , - WIFI_EXT_SPARE_REUSE_TAG_28_E = 623 , - WIFI_EXT_SPARE_REUSE_TAG_30_E = 625 , - WIFI_EXT_SPARE_REUSE_TAG_32_E = 627 , - WIFI_EXT_SPARE_REUSE_TAG_34_E = 629 , - WIFI_EXT_SPARE_REUSE_TAG_36_E = 631 , - WIFI_EXT_SPARE_REUSE_TAG_38_E = 633 , - WIFI_EXT_SPARE_REUSE_TAG_40_E = 635 , - WIFI_EXT_SPARE_REUSE_TAG_42_E = 637 , - WIFI_EXT_SPARE_REUSE_TAG_44_E = 639 , - WIFI_EXT_SPARE_REUSE_TAG_46_E = 641 , - WIFI_EXT_SPARE_REUSE_TAG_48_E = 643 , - WIFI_EXT_SPARE_REUSE_TAG_50_E = 645 , - WIFI_EXT_SPARE_REUSE_TAG_52_E = 647 , - WIFI_EXT_SPARE_REUSE_TAG_54_E = 649 , - WIFI_EXT_SPARE_REUSE_TAG_56_E = 651 , - WIFI_EXT_SPARE_REUSE_TAG_58_E = 653 , - WIFI_EXT_SPARE_REUSE_TAG_60_E = 655 , - WIFI_EXT_SPARE_REUSE_TAG_62_E = 657 , - WIFI_EXT_SPARE_REUSE_TAG_64_E = 659 , - WIFI_EXT_SPARE_REUSE_TAG_66_E = 661 , - WIFI_EXT_SPARE_REUSE_TAG_68_E = 663 , - WIFI_EXT_SPARE_REUSE_TAG_70_E = 665 , - WIFI_EXT_SPARE_REUSE_TAG_72_E = 667 , - WIFI_EXT_SPARE_REUSE_TAG_74_E = 669 , - WIFI_EXT_SPARE_REUSE_TAG_76_E = 671 , - WIFI_EXT_SPARE_REUSE_TAG_78_E = 673 , - WIFI_EXT_SPARE_REUSE_TAG_80_E = 675 , - WIFI_EXT_SPARE_REUSE_TAG_82_E = 677 , - WIFI_EXT_SPARE_REUSE_TAG_84_E = 679 , - WIFI_EXT_SPARE_REUSE_TAG_86_E = 681 , - WIFI_EXT_SPARE_REUSE_TAG_88_E = 683 , - WIFI_EXT_SPARE_REUSE_TAG_90_E = 685 , - WIFI_EXT_SPARE_REUSE_TAG_92_E = 687 , - WIFI_EXT_SPARE_REUSE_TAG_94_E = 689 , - WIFI_EXT_SPARE_REUSE_TAG_96_E = 691 , - WIFI_EXT_SPARE_REUSE_TAG_98_E = 693 , - WIFI_EXT_SPARE_REUSE_TAG_100_E = 695 , - WIFI_EXT_SPARE_REUSE_TAG_102_E = 697 , - WIFI_EXT_SPARE_REUSE_TAG_104_E = 699 , - WIFI_EXT_SPARE_REUSE_TAG_106_E = 701 , - WIFI_EXT_SPARE_REUSE_TAG_108_E = 703 , - WIFI_EXT_SPARE_REUSE_TAG_110_E = 705 , - WIFI_EXT_SPARE_REUSE_TAG_112_E = 707 , - WIFI_EXT_SPARE_REUSE_TAG_114_E = 709 , - WIFI_EXT_SPARE_REUSE_TAG_116_E = 711 , - WIFI_EXT_SPARE_REUSE_TAG_118_E = 713 , - WIFI_EXT_SPARE_REUSE_TAG_120_E = 715 , - WIFI_EXT_SPARE_REUSE_TAG_122_E = 717 , - WIFI_EXT_SPARE_REUSE_TAG_124_E = 719 , - WIFI_EXT_SPARE_REUSE_TAG_126_E = 721 , - WIFI_EXT_SPARE_REUSE_TAG_128_E = 723 , - WIFI_EXT_SPARE_REUSE_TAG_130_E = 725 , - WIFI_EXT_SPARE_REUSE_TAG_132_E = 727 , - WIFI_EXT_SPARE_REUSE_TAG_134_E = 729 , - WIFI_EXT_SPARE_REUSE_TAG_136_E = 731 , - WIFI_EXT_SPARE_REUSE_TAG_138_E = 733 , - WIFI_EXT_SPARE_REUSE_TAG_140_E = 735 , - WIFI_EXT_SPARE_REUSE_TAG_142_E = 737 , - WIFI_EXT_SPARE_REUSE_TAG_144_E = 739 , - WIFI_EXT_SPARE_REUSE_TAG_146_E = 741 , - WIFI_EXT_SPARE_REUSE_TAG_148_E = 743 , - WIFI_EXT_SPARE_REUSE_TAG_150_E = 745 , - WIFI_EXT_SPARE_REUSE_TAG_152_E = 747 , - WIFI_EXT_SPARE_REUSE_TAG_154_E = 749 , - WIFI_EXT_SPARE_REUSE_TAG_156_E = 751 , - WIFI_EXT_SPARE_REUSE_TAG_158_E = 753 , - WIFI_EXT_SPARE_REUSE_TAG_160_E = 755 , - WIFI_EXT_SPARE_REUSE_TAG_162_E = 757 , - WIFI_EXT_SPARE_REUSE_TAG_164_E = 759 , - WIFI_EXT_SPARE_REUSE_TAG_166_E = 761 , - WIFI_EXT_SPARE_REUSE_TAG_168_E = 763 , - WIFI_EXT_SPARE_REUSE_TAG_170_E = 765 , - WIFI_EXT_SPARE_REUSE_TAG_172_E = 767 , - WIFI_EXT_SPARE_REUSE_TAG_174_E = 769 , - WIFI_EXT_SPARE_REUSE_TAG_176_E = 771 , - WIFI_EXT_SPARE_REUSE_TAG_178_E = 773 , - WIFI_EXT_SPARE_REUSE_TAG_180_E = 775 , - WIFI_EXT_SPARE_REUSE_TAG_182_E = 777 , - WIFI_EXT_SPARE_REUSE_TAG_184_E = 779 , - WIFI_EXT_SPARE_REUSE_TAG_186_E = 781 , - WIFI_EXT_SPARE_REUSE_TAG_188_E = 783 , - WIFI_EXT_SPARE_REUSE_TAG_190_E = 785 , - WIFI_EXT_SPARE_REUSE_TAG_192_E = 787 , - WIFI_EXT_SPARE_REUSE_TAG_194_E = 789 , - WIFI_EXT_SPARE_REUSE_TAG_196_E = 791 , - WIFI_EXT_SPARE_REUSE_TAG_198_E = 793 , - WIFI_EXT_SPARE_REUSE_TAG_200_E = 795 , - WIFI_EXT_SPARE_REUSE_TAG_202_E = 797 , - WIFI_EXT_SPARE_REUSE_TAG_204_E = 799 , - WIFI_EXT_SPARE_REUSE_TAG_206_E = 801 , - WIFI_EXT_SPARE_REUSE_TAG_208_E = 803 , - WIFI_EXT_SPARE_REUSE_TAG_210_E = 805 , - WIFI_EXT_SPARE_REUSE_TAG_212_E = 807 , - WIFI_EXT_SPARE_REUSE_TAG_214_E = 809 , - WIFI_EXT_SPARE_REUSE_TAG_216_E = 811 , - WIFI_EXT_SPARE_REUSE_TAG_218_E = 813 , - WIFI_EXT_SPARE_REUSE_TAG_220_E = 815 , - WIFI_EXT_SPARE_REUSE_TAG_222_E = 817 , - WIFI_EXT_SPARE_REUSE_TAG_224_E = 819 , - WIFI_EXT_SPARE_REUSE_TAG_226_E = 821 , - WIFI_EXT_SPARE_REUSE_TAG_228_E = 823 , - WIFI_EXT_SPARE_REUSE_TAG_230_E = 825 , - WIFI_EXT_SPARE_REUSE_TAG_232_E = 827 , - WIFI_EXT_SPARE_REUSE_TAG_234_E = 829 , - WIFI_EXT_SPARE_REUSE_TAG_236_E = 831 , - WIFI_EXT_SPARE_REUSE_TAG_238_E = 833 , - WIFI_EXT_SPARE_REUSE_TAG_240_E = 835 , - WIFI_EXT_SPARE_REUSE_TAG_242_E = 837 , - WIFI_EXT_SPARE_REUSE_TAG_244_E = 839 , - WIFI_EXT_SPARE_REUSE_TAG_246_E = 841 , - WIFI_EXT_SPARE_REUSE_TAG_248_E = 843 , - WIFI_EXT_SPARE_REUSE_TAG_250_E = 845 , - WIFI_EXT_SPARE_REUSE_TAG_252_E = 847 , - WIFI_EXT_SPARE_REUSE_TAG_254_E = 849 , - WIFI_EXT_SPARE_REUSE_TAG_256_E = 851 , - WIFI_EXT_SPARE_REUSE_TAG_258_E = 853 , - WIFI_EXT_SPARE_REUSE_TAG_260_E = 855 , - WIFI_EXT_SPARE_REUSE_TAG_262_E = 857 , - WIFI_EXT_SPARE_REUSE_TAG_264_E = 859 , - WIFI_EXT_SPARE_REUSE_TAG_266_E = 861 , - WIFI_EXT_SPARE_REUSE_TAG_268_E = 863 , - WIFI_EXT_SPARE_REUSE_TAG_270_E = 865 , - WIFI_EXT_SPARE_REUSE_TAG_272_E = 867 , - WIFI_EXT_SPARE_REUSE_TAG_274_E = 869 , - WIFI_EXT_SPARE_REUSE_TAG_276_E = 871 , - WIFI_EXT_SPARE_REUSE_TAG_278_E = 873 , - WIFI_EXT_SPARE_REUSE_TAG_280_E = 875 , - WIFI_EXT_SPARE_REUSE_TAG_282_E = 877 , - WIFI_EXT_SPARE_REUSE_TAG_284_E = 879 , - WIFI_EXT_SPARE_REUSE_TAG_286_E = 881 , - WIFI_EXT_SPARE_REUSE_TAG_288_E = 883 , - WIFI_EXT_SPARE_REUSE_TAG_290_E = 885 , - WIFI_EXT_SPARE_REUSE_TAG_292_E = 887 , - WIFI_EXT_SPARE_REUSE_TAG_294_E = 889 , - WIFI_EXT_SPARE_REUSE_TAG_296_E = 891 , - WIFI_EXT_SPARE_REUSE_TAG_298_E = 893 , - WIFI_EXT_SPARE_REUSE_TAG_300_E = 895 , - WIFI_EXT_SPARE_REUSE_TAG_302_E = 897 , - WIFI_EXT_SPARE_REUSE_TAG_304_E = 899 , - WIFI_EXT_SPARE_REUSE_TAG_306_E = 901 , - WIFI_EXT_SPARE_REUSE_TAG_308_E = 903 , - WIFI_EXT_SPARE_REUSE_TAG_310_E = 905 , - WIFI_EXT_SPARE_REUSE_TAG_312_E = 907 , - WIFI_EXT_SPARE_REUSE_TAG_314_E = 909 , - WIFI_EXT_SPARE_REUSE_TAG_316_E = 911 , - WIFI_EXT_SPARE_REUSE_TAG_318_E = 913 , - WIFI_EXT_SPARE_REUSE_TAG_320_E = 915 , - WIFI_EXT_SPARE_REUSE_TAG_322_E = 917 , - WIFI_EXT_SPARE_REUSE_TAG_324_E = 919 , - WIFI_EXT_SPARE_REUSE_TAG_326_E = 921 , - WIFI_EXT_SPARE_REUSE_TAG_328_E = 923 , - WIFI_EXT_SPARE_REUSE_TAG_330_E = 925 , - WIFI_EXT_SPARE_REUSE_TAG_332_E = 927 , - WIFI_EXT_SPARE_REUSE_TAG_334_E = 929 , - WIFI_EXT_SPARE_REUSE_TAG_336_E = 931 , - WIFI_EXT_SPARE_REUSE_TAG_338_E = 933 , - WIFI_EXT_SPARE_REUSE_TAG_340_E = 935 , - WIFI_EXT_SPARE_REUSE_TAG_342_E = 937 , - WIFI_EXT_SPARE_REUSE_TAG_344_E = 939 , - WIFI_EXT_SPARE_REUSE_TAG_346_E = 941 , - WIFI_EXT_SPARE_REUSE_TAG_348_E = 943 , - WIFI_EXT_SPARE_REUSE_TAG_350_E = 945 , - WIFI_EXT_SPARE_REUSE_TAG_352_E = 947 , - WIFI_EXT_SPARE_REUSE_TAG_354_E = 949 , - WIFI_EXT_SPARE_REUSE_TAG_356_E = 951 , - WIFI_EXT_SPARE_REUSE_TAG_358_E = 953 , - WIFI_EXT_SPARE_REUSE_TAG_360_E = 955 , - WIFI_EXT_SPARE_REUSE_TAG_362_E = 957 , - WIFI_EXT_SPARE_REUSE_TAG_364_E = 959 , - WIFI_EXT_SPARE_REUSE_TAG_366_E = 961 , - WIFI_EXT_SPARE_REUSE_TAG_368_E = 963 , - WIFI_EXT_SPARE_REUSE_TAG_370_E = 965 , - WIFI_EXT_SPARE_REUSE_TAG_372_E = 967 , - WIFI_EXT_SPARE_REUSE_TAG_374_E = 969 , - WIFI_EXT_SPARE_REUSE_TAG_376_E = 971 , - WIFI_EXT_SPARE_REUSE_TAG_378_E = 973 , - WIFI_EXT_SPARE_REUSE_TAG_380_E = 975 , - WIFI_EXT_SPARE_REUSE_TAG_382_E = 977 , - WIFI_EXT_SPARE_REUSE_TAG_384_E = 979 , - WIFI_EXT_SPARE_REUSE_TAG_386_E = 981 , - WIFI_EXT_SPARE_REUSE_TAG_388_E = 983 , - WIFI_EXT_SPARE_REUSE_TAG_390_E = 985 , - WIFI_EXT_SPARE_REUSE_TAG_392_E = 987 , - WIFI_EXT_SPARE_REUSE_TAG_394_E = 989 , - WIFI_EXT_SPARE_REUSE_TAG_396_E = 991 , - WIFI_EXT_SPARE_REUSE_TAG_398_E = 993 , - WIFI_EXT_SPARE_REUSE_TAG_400_E = 995 , - WIFI_EXT_SPARE_REUSE_TAG_402_E = 997 , - WIFI_EXT_SPARE_REUSE_TAG_404_E = 999 , - WIFI_EXT_SPARE_REUSE_TAG_406_E = 1001 , - WIFI_EXT_SPARE_REUSE_TAG_408_E = 1003 , - WIFI_EXT_SPARE_REUSE_TAG_410_E = 1005 , - WIFI_EXT_SPARE_REUSE_TAG_412_E = 1007 , - WIFI_EXT_SPARE_REUSE_TAG_414_E = 1009 , - WIFI_EXT_SPARE_REUSE_TAG_416_E = 1011 , - WIFI_EXT_SPARE_REUSE_TAG_418_E = 1013 , - WIFI_EXT_SPARE_REUSE_TAG_420_E = 1015 , - WIFI_EXT_SPARE_REUSE_TAG_422_E = 1017 , - WIFI_EXT_SPARE_REUSE_TAG_424_E = 1019 , - WIFI_EXT_SPARE_REUSE_TAG_426_E = 1021 -} ext_tlv_tag_def__e; - -typedef enum { - WIFI_N_EXT_MACTX_CBF_START_E = 0 , - WIFI_N_EXT_PHYRX_CBF_DATA_RESP_E = 2 , - WIFI_N_EXT_PHYRX_USER_ABORT_NOTIFICATION_E = 4 , - WIFI_N_EXT_MACTX_CBF_DATA_E = 6 , - WIFI_N_EXT_PHYRX_LMR_DATA_RESP_E = 8 , - WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , - WIFI_N_EXT_RXPCU_TO_UCODE_FCS_STATUS_E = 12 , - WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , - WIFI_N_EXT_RXPCU_TO_UCODE_END_E = 16 , - WIFI_N_EXT_PHYRX_NC_ABORT_REQUEST_E = 18 , - WIFI_N_EXT_PHYRX_NC_DATA_E = 20 , - WIFI_N_EXT_MACRX_CBF_READ_REQUEST_E = 64 , - WIFI_N_EXT_MACRX_EXPECT_NDP_RECEPTION_E = 66 , - WIFI_N_EXT_MACRX_NDP_TIMEOUT_E = 68 , - WIFI_N_EXT_MACRX_REQ_IMPLICIT_FB_E = 70 , - WIFI_N_EXT_MACRX_NAP_USER_E = 72 , - WIFI_N_EXT_PHYTX_OTHER_TRANSMIT_INFO16_E = 74 , - WIFI_N_EXT_PHYTX_ABORT_REQUEST_E = 76 , - WIFI_N_EXT_PHYTX_PPDU_HEADER_INFO_REQUEST_E = 78 , - WIFI_N_EXT_PHYTX_DATA_REQUEST_E = 80 , - WIFI_N_EXT_PHYTX_NAP_ACK_E = 82 , - WIFI_N_EXT_PHYTX_OFF_ACK_E = 84 , - WIFI_N_EXT_PHYTX_SYNTH_OFF_ACK_E = 86 , - WIFI_N_EXT_MACTX_ABORT_REQUEST_E = 88 , - WIFI_N_EXT_MACTX_PKT_END_E = 90 , - WIFI_N_EXT_MACTX_BF_PARAMS_COMMON_E = 92 , - WIFI_N_EXT_MACTX_PREFETCH_CV_E = 94 , - WIFI_N_EXT_MACTX_USER_DESC_PER_USER_E = 96 , - WIFI_N_EXT_EXAMPLE_TLV_16_E = 98 , - WIFI_N_EXT_MACTX_PHY_ON_E = 100 , - WIFI_N_EXT_MACTX_EXPECT_CBF_COMMON_E = 102 , - WIFI_N_EXT_MACTX_PHY_DESC_E = 104 , - WIFI_N_EXT_MACTX_L_SIG_B_E = 106 , - WIFI_N_EXT_MACTX_VHT_SIG_A_E = 108 , - WIFI_N_EXT_MACTX_VHT_SIG_B_SU40_E = 110 , - WIFI_N_EXT_MACTX_VHT_SIG_B_SU160_E = 112 , - WIFI_N_EXT_MACTX_VHT_SIG_B_MU40_E = 114 , - WIFI_N_EXT_MACTX_VHT_SIG_B_MU160_E = 116 , - WIFI_N_EXT_MACTX_HE_SIG_A_SU_E = 118 , - WIFI_N_EXT_MACTX_HE_SIG_A_MU_UL_E = 120 , - WIFI_N_EXT_MACTX_HE_SIG_B2_MU_E = 122 , - WIFI_N_EXT_MACTX_DELETE_CV_E = 124 , - WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_E = 126 , - WIFI_N_EXT_MACTX_PHY_NAP_E = 128 , - WIFI_N_EXT_PHYRX_ABORT_ACK_E = 130 , - WIFI_N_EXT_PHYRX_RSSI_LEGACY_E = 132 , - WIFI_N_EXT_PHYRX_USER_INFO_E = 134 , - WIFI_N_EXT_PHYRX_DEBUG_E = 136 , - WIFI_N_EXT_PHYRX_CBF_TRANSFER_ABORT_E = 138 , - WIFI_N_EXT_PHYRX_L_SIG_B_E = 140 , - WIFI_N_EXT_PHYRX_VHT_SIG_A_E = 142 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_SU40_E = 144 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_SU160_E = 146 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_MU40_E = 148 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_MU160_E = 150 , - WIFI_N_EXT_PHYRX_HE_SIG_A_MU_DL_E = 152 , - WIFI_N_EXT_PHYRX_HE_SIG_B1_MU_E = 154 , - WIFI_N_EXT_PHYRX_HE_SIG_B2_OFDMA_E = 156 , - WIFI_N_EXT_PHYRX_COMMON_USER_INFO_E = 158 , - WIFI_N_EXT_COEX_TX_REQ_E = 160 , - WIFI_N_EXT_EXAMPLE_TLV_32_NAME_E = 162 , - WIFI_N_EXT_NA_LENGTH_END_E = 164 , - WIFI_N_EXT_PCU_PPDU_SETUP_DONE_E = 166 , - WIFI_N_EXT_PCU_PPDU_SETUP_INIT_E = 168 , - WIFI_N_EXT_PDG_FES_SETUP_E = 170 , - WIFI_N_EXT_PDG_TX_REQ_E = 172 , - WIFI_N_EXT_MACTX_SWITCH_TO_MAIN_E = 174 , - WIFI_N_EXT_AUX_PPDU_END_E = 176 , - WIFI_N_EXT_TQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 178 , - WIFI_N_EXT_TQM_GEN_MPDUS_STATUS_E = 180 , - WIFI_N_EXT_TQM_REMOVE_MPDU_STATUS_E = 182 , - WIFI_N_EXT_TQM_REMOVE_MSDU_STATUS_E = 184 , - WIFI_N_EXT_TQM_WRITE_CMD_E = 186 , - WIFI_N_EXT_TX_DATA_E = 188 , - WIFI_N_EXT_RX_PACKET_E = 190 , - WIFI_N_EXT_TX_MPDU_END_E = 192 , - WIFI_N_EXT_TX_MSDU_END_E = 194 , - WIFI_N_EXT_TX_SW_MODE_SETUP_E = 196 , - WIFI_N_EXT_TXPCU_USER_BUFFER_STATUS_E = 198 , - WIFI_N_EXT_EXAMPLE_USER_TLV_32_E = 200 , - WIFI_N_EXT_PDG_USER_SETUP_E = 202 , - WIFI_N_EXT_REO_UPDATE_RX_REO_QUEUE_STATUS_E = 204 , - WIFI_N_EXT_TX_RAW_OR_NATIVE_FRAME_SETUP_E = 206 , - WIFI_N_EXT_TX_FLUSH_E = 208 , - WIFI_N_EXT_TQM_WRITE_CMD_STATUS_E = 210 , - WIFI_N_EXT_TQM_GET_MSDU_FLOW_STATS_E = 212 , - WIFI_N_EXT_TX_FES_STATUS_START_E = 214 , - WIFI_N_EXT_TX_FES_STATUS_USER_RESPONSE_E = 216 , - WIFI_N_EXT_RX_TRIG_INFO_E = 218 , - WIFI_N_EXT_RX_FRAME_BITMAP_REQ_E = 220 , - WIFI_N_EXT_COEX_RX_STATUS_E = 222 , - WIFI_N_EXT_RX_PPDU_START_E = 224 , - WIFI_N_EXT_RX_MPDU_START_E = 226 , - WIFI_N_EXT_RX_MSDU_START_E = 228 , - WIFI_N_EXT_RX_ATTENTION_E = 230 , - WIFI_N_EXT_RX_PHY_SLEEP_E = 232 , - WIFI_N_EXT_RX_PEER_ENTRY_E = 234 , - WIFI_N_EXT_RX_RESPONSE_REQUIRED_INFO_E = 236 , - WIFI_N_EXT_TQM_GET_MPDU_QUEUE_STATS_STATUS_E = 238 , - WIFI_N_EXT_TX_CBF_INFO_E = 240 , - WIFI_N_EXT_RX_MPDU_PCU_START_E = 242 , - WIFI_N_EXT_RX_USER_PPDU_END_E = 244 , - WIFI_N_EXT_RX_PREAMBLE_E = 246 , - WIFI_N_EXT_TX_LAST_MPDU_FETCHED_E = 248 , - WIFI_N_EXT_RXPCU_SETUP_E = 250 , - WIFI_N_EXT_TX_FES_STATUS_ACK_OR_BA_E = 252 , - WIFI_N_EXT_COEX_TX_RESP_E = 254 , - WIFI_N_EXT_MACTX_COEX_PHY_CTRL_E = 256 , - WIFI_N_EXT_RESPONSE_START_STATUS_E = 258 , - WIFI_N_EXT_CRYPTO_STATUS_E = 260 , - WIFI_N_EXT_COEX_TX_STOP_CTRL_E = 262 , - WIFI_N_EXT_RX_PPDU_NO_ACK_REPORT_E = 264 , - WIFI_N_EXT_SCHEDULER_COMMAND_STATUS_E = 266 , - WIFI_N_EXT_TX_FES_STATUS_PROT_E = 268 , - WIFI_N_EXT_TX_FES_STATUS_START_PROT_E = 270 , - WIFI_N_EXT_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 272 , - WIFI_N_EXT_WHO_ANCHOR_OFFSET_E = 274 , - WIFI_N_EXT_WHO_CCE_INFO_E = 276 , - WIFI_N_EXT_WHO_COMMIT_DONE_E = 278 , - WIFI_N_EXT_WHO_L2_LLC_E = 280 , - WIFI_N_EXT_WHO_L3_CHECKSUM_E = 282 , - WIFI_N_EXT_WHO_L4_CHECKSUM_E = 284 , - WIFI_N_EXT_WHO_MSDU_E = 286 , - WIFI_N_EXT_WHO_PACKET_DATA_E = 288 , - WIFI_N_EXT_WHO_PPDU_END_E = 290 , - WIFI_N_EXT_WHO_TSO_E = 292 , - WIFI_N_EXT_WHO_WMAC_HEADER_PV1_E = 294 , - WIFI_N_EXT_MPDU_INFO_END_E = 296 , - WIFI_N_EXT_TX_QUEUE_EXTENSION_E = 298 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 300 , - WIFI_N_EXT_TQM_ADD_MSDU_STATUS_E = 302 , - WIFI_N_EXT_WHO_TERMINATE_E = 304 , - WIFI_N_EXT_TX_CV_DATA_E = 306 , - WIFI_N_EXT_PROT_TX_END_E = 308 , - WIFI_N_EXT_TQM_SCH_INSTR_GLOBAL_END_E = 310 , - WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT_E = 312 , - WIFI_N_EXT_REO_FLUSH_QUEUE_E = 314 , - WIFI_N_EXT_REO_UNBLOCK_CACHE_E = 316 , - WIFI_N_EXT_REO_FLUSH_QUEUE_STATUS_E = 318 , - WIFI_N_EXT_REO_UNBLOCK_CACHE_STATUS_E = 320 , - WIFI_N_EXT_TQM_UNBLOCK_CACHE_E = 322 , - WIFI_N_EXT_TQM_UNBLOCK_CACHE_STATUS_E = 324 , - WIFI_N_EXT_RX_STATUS_BUFFER_DONE_E = 326 , - WIFI_N_EXT_SCHEDULER_TXOP_DURATION_TRIGGER_E = 328 , - WIFI_N_EXT_PHYRX_CBF_READ_REQUEST_ACK_E = 330 , - WIFI_N_EXT_TQM_SYNC_CMD_E = 332 , - WIFI_N_EXT_TQM_SYNC_CMD_STATUS_E = 334 , - WIFI_N_EXT_TCC_TQM_WRAPPER_CMD_E = 336 , - WIFI_N_EXT_REO_FLUSH_TIMEOUT_LIST_STATUS_E = 338 , - WIFI_N_EXT_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 340 , - WIFI_N_EXT_RX_PPDU_START_USER_INFO_E = 342 , - WIFI_N_EXT_COEX_MAC_NAP_E = 344 , - WIFI_N_EXT_WHO_MESH_CONTROL_E = 346 , - WIFI_N_EXT_PDG_SW_MODE_BW_END_E = 348 , - WIFI_N_EXT_PDG_WAIT_FOR_PHY_REQUEST_E = 350 , - WIFI_N_EXT_RX_PPDU_START_DROPPED_E = 352 , - WIFI_N_EXT_RX_PPDU_END_STATUS_DONE_DROPPED_E = 354 , - WIFI_N_EXT_RX_MSDU_START_DROPPED_E = 356 , - WIFI_N_EXT_RX_MPDU_END_DROPPED_E = 358 , - WIFI_N_EXT_TXPCU_USER_SETUP_E = 360 , - WIFI_N_EXT_CMD_PART_0_END_E = 362 , - WIFI_N_EXT_SCH_CRITICAL_TLV_REFERENCE_E = 364 , - WIFI_N_EXT_EXAMPLE_TLV_32_E = 366 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 368 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 370 , - WIFI_N_EXT_TQM_2_SCH_MPDU_AVAILABLE_E = 372 , - WIFI_N_EXT_TRIGGER_RESPONSE_TX_DONE_E = 374 , - WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_E = 376 , - WIFI_N_EXT_RECEIVED_RESPONSE_INFO_PART2_E = 378 , - WIFI_N_EXT_TXPCU_PREAMBLE_DONE_E = 380 , - WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_RBO_DROP_E = 382 , - WIFI_N_EXT_MACTX_CLEAR_PREV_TX_INFO_E = 384 , - WIFI_N_EXT_R2R_STATUS_END_E = 386 , - WIFI_N_EXT_END_OF_FLUSH_MARKER_E = 388 , - WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_PUNC_E = 390 , - WIFI_N_EXT_RECEIVED_RESPONSE_USER_15_8_E = 392 , - WIFI_N_EXT_RECEIVED_RESPONSE_USER_31_24_E = 394 , - WIFI_N_EXT_TX_LOOPBACK_SETUP_E = 396 , - WIFI_N_EXT_SCH_WAIT_INSTR_TX_PATH_E = 398 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 400 , - WIFI_N_EXT_TX_WUR_DATA_E = 402 , - WIFI_N_EXT_RX_PPDU_END_MIDDLE_E = 404 , - WIFI_N_EXT_MACTX_BACKOFF_BASED_TRANSMISSION_E = 406 , - WIFI_N_EXT_SRP_INFO_E = 408 , - WIFI_N_EXT_SCHEDULER_SW_MSG_STATUS_E = 410 , - WIFI_N_EXT_RXPCU_SETUP_COMPLETE_E = 412 , - WIFI_N_EXT_MACTX_MCC_SWITCH_BACK_E = 414 , - WIFI_N_EXT_PHYTX_MCC_SWITCH_BACK_ACK_E = 416 , - WIFI_N_EXT_LMR_TX_END_E = 418 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 420 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 422 , - WIFI_N_EXT_SCHEDULER_STATUS_WRAPPER_E = 424 , - WIFI_N_EXT_MACTX___RESERVED_G_0013 = 426 , - WIFI_N_EXT_MACTX_U_SIG_EHT_TB_E = 428 , - WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG1_CFG_E = 430 , - WIFI_N_EXT_PHYRX_U_SIG_EHT_SU_MU_E = 432 , - WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG3_CFG_E = 434 , - WIFI_N_EXT_TX_PUNCTURE_6PATTERNS_SETUP_E = 436 , - WIFI_N_EXT_MACRX_LMR_DATA_REQUEST_E = 438 , - WIFI_N_EXT_PHYRX_LMR_TRANSFER_ABORT_E = 440 , - WIFI_N_EXT_MACRX_SECURE_LTF_SEQ_PTR_E = 442 , - WIFI_N_EXT_MPDU_QUEUE_OVERVIEW_E = 444 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 446 , - WIFI_N_EXT_LMR_MPDU_START_E = 448 , - WIFI_N_EXT_LMR_MPDU_END_E = 450 , - WIFI_N_EXT_RX_FRAME_1K_BITMAP_ACK_E = 452 , - WIFI_N_EXT_TQM_ACKED_1K_MPDU_E = 454 , - WIFI_N_EXT_PHYRX_LOCATION_E = 456 , - WIFI_N_EXT_MLO_TX_NOTIFICATION_MU_E = 458 , - WIFI_N_EXT_MLO_TX_REQ_MU_E = 460 , - WIFI_N_EXT_MLO_RX_NOTIFICATION_E = 462 , - WIFI_N_EXT_MLO_TBTT_NOTIFICATION_E = 464 , - WIFI_N_EXT_MLO_TS_SYNC_MSG_E = 466 , - WIFI_N_EXT_MLO_PDG_FES_SETUP_SU_E = 468 , - WIFI_N_EXT_MPDU_INFO_1K_BITMAP_E = 470 , - WIFI_N_EXT_TX_FRAG_STATE_E = 472 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 474 , - WIFI_N_EXT_MACTX_U_SIG_UHR_SU_MU_E = 476 , - WIFI_N_EXT_TX_MPDU_COMPRESSED_DETAILS_TLV_E = 478 , - WIFI_N_EXT_TX_MSDU_COMPONENT_DETAILS_TLV_E = 480 , - WIFI_N_EXT_SCHEDULER_IU_TEMPLATE_ID_E = 482 , - WIFI_N_EXT_MACTX_EXPECT_NDP_RECEPTION_E = 484 , - WIFI_N_EXT_TX_MPDU_LENGTH_AND_RESTRICTIONS_E = 486 , - WIFI_N_EXT_PHYRX___RESERVED_G_0014 = 488 , - WIFI_N_EXT_PHYTX___RESERVED_G_0014 = 490 , - WIFI_N_EXT_MACTX_EHT_SIG_USR_SU_E = 492 , - WIFI_N_EXT_PHYRX_EHT_SIG_USR_SU_E = 494 , - WIFI_N_EXT_PHYRX_GENERIC_U_SIG_E = 496 , - WIFI_N_EXT_OVERWRITE_RESP_START_E = 498 , - WIFI_N_EXT_OVERWRITE_RESP_FRAME_INFO_E = 500 , - WIFI_N_EXT_RXPCU_EARLY_RX_INDICATION_E = 502 , - WIFI_N_EXT_MACRX_MU_UPLINK_COMMON_SNIFF_E = 504 , - WIFI_N_EXT_MACRX_MU_UPLINK_USER_SEL_SNIFF_E = 506 , - WIFI_N_EXT_MACTX_PREFETCH_CV_DMA_E = 508 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 510 , - WIFI_N_EXT_MACTX_BF_PARAMS_UPDATE_PER_USER_E = 512 , - WIFI_N_EXT_PHYTX_CV_CORR_STATUS_E = 514 , - WIFI_N_EXT_PHYTX_CV_CORR_USER_E = 516 , - WIFI_N_EXT_MACTX_CV_CORR_MAC_INFO_GROUP_E = 518 , - WIFI_N_EXT_MACTX_RX_NOTIFICATION_FOR_PHY_E = 520 , - WIFI_N_EXT_MACTX_MU_UPLINK_COMMON_PER_BW_E = 522 , - WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT2_E = 524 , - WIFI_N_EXT_WSI_DIRECT_MESSAGE_E = 526 , - WIFI_N_EXT_MACTX_EMLSR_SWITCH_E = 528 , - WIFI_N_EXT_PHYTX_EMLSR_SWITCH_ACK_E = 530 , - WIFI_N_EXT_EAD_COMMAND_E = 532 , - WIFI_N_EXT_EAD_LEGACY_INTERRUPT_CONTROL_E = 534 , - WIFI_N_EXT_TPI_ENABLE_RESPONSE_TIMEOUT_E = 536 , - WIFI_N_EXT_TPI_LEGACY_INTERRUPT_CONTROL_E = 538 , - WIFI_N_EXT_TPI_MPDU_CONTINUATION_E = 540 , - WIFI_N_EXT_TPI_SEND_TLV_TO_PHYTX_E = 542 , - WIFI_N_EXT_TPI_STATUS_E = 544 , - WIFI_N_EXT_TPI_TIMESTAMP_STATUS_E = 546 , - WIFI_N_EXT_RPI_LEGACY_STATUS_CONTROL_E = 548 , - WIFI_N_EXT_RPI_STATUS_E = 550 , - WIFI_N_EXT_RPI_TIMESTAMP_STATUS_E = 552 , - WIFI_N_EXT_TCC_PUSH_TRANSMIT_COMMAND_E = 554 , - WIFI_N_EXT_TCC_LEGACY_STATUS_CONTROL_E = 556 , - WIFI_N_EXT_TCC_STATUS_E = 558 , - WIFI_N_EXT_TCC_TIMESTAMP_STATUS_E = 560 , - WIFI_N_EXT_TCC_SCHEDULER_CMD_E = 562 , - WIFI_N_EXT_RPI_NON_DATA_CTLV_44_FROM_PHYRX_E = 564 , - WIFI_N_EXT_RPI_FETCH_INFO_FROM_EXT_MEM_E = 566 , - WIFI_N_EXT_RPI_INIT_CBF_DATA_RESP_ADDR_E = 568 , - WIFI_N_EXT_TPI_SEND_CBF_DATA_TO_PHYTX_E = 570 , - WIFI_N_EXT_TCC_FES_END_MESSAGE_E = 572 , - WIFI_N_EXT_TPI_DISABLE_RESPONSE_TIMEOUT_E = 574 , - WIFI_N_EXT_EAD_MSDU_STATUS_START_E = 576 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_SU_E = 578 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_OFDMA_E = 580 , - WIFI_N_EXT_COEX_BLACKOUT_DETAILS_E = 582 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E = 584 , - WIFI_N_EXT_HDR_CTRL_PROT_MPDU_START_E = 586 , - WIFI_N_EXT_HDR_CTRL_PROT_MPDU_END_E = 588 , - WIFI_N_EXT_HDR_CTRL_PROT_PEER_INFO_E = 590 , - WIFI_N_EXT_MACTX_U_SIG_UHR_ELR_SU_E = 592 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_COBF_E = 594 , - WIFI_N_EXT_SPARE_REUSE_TAG_1_E = 596 , - WIFI_N_EXT_SPARE_REUSE_TAG_3_E = 598 , - WIFI_N_EXT_SPARE_REUSE_TAG_5_E = 600 , - WIFI_N_EXT_SPARE_REUSE_TAG_7_E = 602 , - WIFI_N_EXT_SPARE_REUSE_TAG_9_E = 604 , - WIFI_N_EXT_SPARE_REUSE_TAG_11_E = 606 , - WIFI_N_EXT_SPARE_REUSE_TAG_13_E = 608 , - WIFI_N_EXT_SPARE_REUSE_TAG_15_E = 610 , - WIFI_N_EXT_SPARE_REUSE_TAG_17_E = 612 , - WIFI_N_EXT_SPARE_REUSE_TAG_19_E = 614 , - WIFI_N_EXT_SPARE_REUSE_TAG_21_E = 616 , - WIFI_N_EXT_SPARE_REUSE_TAG_23_E = 618 , - WIFI_N_EXT_SPARE_REUSE_TAG_25_E = 620 , - WIFI_N_EXT_SPARE_REUSE_TAG_27_E = 622 , - WIFI_N_EXT_SPARE_REUSE_TAG_29_E = 624 , - WIFI_N_EXT_SPARE_REUSE_TAG_31_E = 626 , - WIFI_N_EXT_SPARE_REUSE_TAG_33_E = 628 , - WIFI_N_EXT_SPARE_REUSE_TAG_35_E = 630 , - WIFI_N_EXT_SPARE_REUSE_TAG_37_E = 632 , - WIFI_N_EXT_SPARE_REUSE_TAG_39_E = 634 , - WIFI_N_EXT_SPARE_REUSE_TAG_41_E = 636 , - WIFI_N_EXT_SPARE_REUSE_TAG_43_E = 638 , - WIFI_N_EXT_SPARE_REUSE_TAG_45_E = 640 , - WIFI_N_EXT_SPARE_REUSE_TAG_47_E = 642 , - WIFI_N_EXT_SPARE_REUSE_TAG_49_E = 644 , - WIFI_N_EXT_SPARE_REUSE_TAG_51_E = 646 , - WIFI_N_EXT_SPARE_REUSE_TAG_53_E = 648 , - WIFI_N_EXT_SPARE_REUSE_TAG_55_E = 650 , - WIFI_N_EXT_SPARE_REUSE_TAG_57_E = 652 , - WIFI_N_EXT_SPARE_REUSE_TAG_59_E = 654 , - WIFI_N_EXT_SPARE_REUSE_TAG_61_E = 656 , - WIFI_N_EXT_SPARE_REUSE_TAG_63_E = 658 , - WIFI_N_EXT_SPARE_REUSE_TAG_65_E = 660 , - WIFI_N_EXT_SPARE_REUSE_TAG_67_E = 662 , - WIFI_N_EXT_SPARE_REUSE_TAG_69_E = 664 , - WIFI_N_EXT_SPARE_REUSE_TAG_71_E = 666 , - WIFI_N_EXT_SPARE_REUSE_TAG_73_E = 668 , - WIFI_N_EXT_SPARE_REUSE_TAG_75_E = 670 , - WIFI_N_EXT_SPARE_REUSE_TAG_77_E = 672 , - WIFI_N_EXT_SPARE_REUSE_TAG_79_E = 674 , - WIFI_N_EXT_SPARE_REUSE_TAG_81_E = 676 , - WIFI_N_EXT_SPARE_REUSE_TAG_83_E = 678 , - WIFI_N_EXT_SPARE_REUSE_TAG_85_E = 680 , - WIFI_N_EXT_SPARE_REUSE_TAG_87_E = 682 , - WIFI_N_EXT_SPARE_REUSE_TAG_89_E = 684 , - WIFI_N_EXT_SPARE_REUSE_TAG_91_E = 686 , - WIFI_N_EXT_SPARE_REUSE_TAG_93_E = 688 , - WIFI_N_EXT_SPARE_REUSE_TAG_95_E = 690 , - WIFI_N_EXT_SPARE_REUSE_TAG_97_E = 692 , - WIFI_N_EXT_SPARE_REUSE_TAG_99_E = 694 , - WIFI_N_EXT_SPARE_REUSE_TAG_101_E = 696 , - WIFI_N_EXT_SPARE_REUSE_TAG_103_E = 698 , - WIFI_N_EXT_SPARE_REUSE_TAG_105_E = 700 , - WIFI_N_EXT_SPARE_REUSE_TAG_107_E = 702 , - WIFI_N_EXT_SPARE_REUSE_TAG_109_E = 704 , - WIFI_N_EXT_SPARE_REUSE_TAG_111_E = 706 , - WIFI_N_EXT_SPARE_REUSE_TAG_113_E = 708 , - WIFI_N_EXT_SPARE_REUSE_TAG_115_E = 710 , - WIFI_N_EXT_SPARE_REUSE_TAG_117_E = 712 , - WIFI_N_EXT_SPARE_REUSE_TAG_119_E = 714 , - WIFI_N_EXT_SPARE_REUSE_TAG_121_E = 716 , - WIFI_N_EXT_SPARE_REUSE_TAG_123_E = 718 , - WIFI_N_EXT_SPARE_REUSE_TAG_125_E = 720 , - WIFI_N_EXT_SPARE_REUSE_TAG_127_E = 722 , - WIFI_N_EXT_SPARE_REUSE_TAG_129_E = 724 , - WIFI_N_EXT_SPARE_REUSE_TAG_131_E = 726 , - WIFI_N_EXT_SPARE_REUSE_TAG_133_E = 728 , - WIFI_N_EXT_SPARE_REUSE_TAG_135_E = 730 , - WIFI_N_EXT_SPARE_REUSE_TAG_137_E = 732 , - WIFI_N_EXT_SPARE_REUSE_TAG_139_E = 734 , - WIFI_N_EXT_SPARE_REUSE_TAG_141_E = 736 , - WIFI_N_EXT_SPARE_REUSE_TAG_143_E = 738 , - WIFI_N_EXT_SPARE_REUSE_TAG_145_E = 740 , - WIFI_N_EXT_SPARE_REUSE_TAG_147_E = 742 , - WIFI_N_EXT_SPARE_REUSE_TAG_149_E = 744 , - WIFI_N_EXT_SPARE_REUSE_TAG_151_E = 746 , - WIFI_N_EXT_SPARE_REUSE_TAG_153_E = 748 , - WIFI_N_EXT_SPARE_REUSE_TAG_155_E = 750 , - WIFI_N_EXT_SPARE_REUSE_TAG_157_E = 752 , - WIFI_N_EXT_SPARE_REUSE_TAG_159_E = 754 , - WIFI_N_EXT_SPARE_REUSE_TAG_161_E = 756 , - WIFI_N_EXT_SPARE_REUSE_TAG_163_E = 758 , - WIFI_N_EXT_SPARE_REUSE_TAG_165_E = 760 , - WIFI_N_EXT_SPARE_REUSE_TAG_167_E = 762 , - WIFI_N_EXT_SPARE_REUSE_TAG_169_E = 764 , - WIFI_N_EXT_SPARE_REUSE_TAG_171_E = 766 , - WIFI_N_EXT_SPARE_REUSE_TAG_173_E = 768 , - WIFI_N_EXT_SPARE_REUSE_TAG_175_E = 770 , - WIFI_N_EXT_SPARE_REUSE_TAG_177_E = 772 , - WIFI_N_EXT_SPARE_REUSE_TAG_179_E = 774 , - WIFI_N_EXT_SPARE_REUSE_TAG_181_E = 776 , - WIFI_N_EXT_SPARE_REUSE_TAG_183_E = 778 , - WIFI_N_EXT_SPARE_REUSE_TAG_185_E = 780 , - WIFI_N_EXT_SPARE_REUSE_TAG_187_E = 782 , - WIFI_N_EXT_SPARE_REUSE_TAG_189_E = 784 , - WIFI_N_EXT_SPARE_REUSE_TAG_191_E = 786 , - WIFI_N_EXT_SPARE_REUSE_TAG_193_E = 788 , - WIFI_N_EXT_SPARE_REUSE_TAG_195_E = 790 , - WIFI_N_EXT_SPARE_REUSE_TAG_197_E = 792 , - WIFI_N_EXT_SPARE_REUSE_TAG_199_E = 794 , - WIFI_N_EXT_SPARE_REUSE_TAG_201_E = 796 , - WIFI_N_EXT_SPARE_REUSE_TAG_203_E = 798 , - WIFI_N_EXT_SPARE_REUSE_TAG_205_E = 800 , - WIFI_N_EXT_SPARE_REUSE_TAG_207_E = 802 , - WIFI_N_EXT_SPARE_REUSE_TAG_209_E = 804 , - WIFI_N_EXT_SPARE_REUSE_TAG_211_E = 806 , - WIFI_N_EXT_SPARE_REUSE_TAG_213_E = 808 , - WIFI_N_EXT_SPARE_REUSE_TAG_215_E = 810 , - WIFI_N_EXT_SPARE_REUSE_TAG_217_E = 812 , - WIFI_N_EXT_SPARE_REUSE_TAG_219_E = 814 , - WIFI_N_EXT_SPARE_REUSE_TAG_221_E = 816 , - WIFI_N_EXT_SPARE_REUSE_TAG_223_E = 818 , - WIFI_N_EXT_SPARE_REUSE_TAG_225_E = 820 , - WIFI_N_EXT_SPARE_REUSE_TAG_227_E = 822 , - WIFI_N_EXT_SPARE_REUSE_TAG_229_E = 824 , - WIFI_N_EXT_SPARE_REUSE_TAG_231_E = 826 , - WIFI_N_EXT_SPARE_REUSE_TAG_233_E = 828 , - WIFI_N_EXT_SPARE_REUSE_TAG_235_E = 830 , - WIFI_N_EXT_SPARE_REUSE_TAG_237_E = 832 , - WIFI_N_EXT_SPARE_REUSE_TAG_239_E = 834 , - WIFI_N_EXT_SPARE_REUSE_TAG_241_E = 836 , - WIFI_N_EXT_SPARE_REUSE_TAG_243_E = 838 , - WIFI_N_EXT_SPARE_REUSE_TAG_245_E = 840 , - WIFI_N_EXT_SPARE_REUSE_TAG_247_E = 842 , - WIFI_N_EXT_SPARE_REUSE_TAG_249_E = 844 , - WIFI_N_EXT_SPARE_REUSE_TAG_251_E = 846 , - WIFI_N_EXT_SPARE_REUSE_TAG_253_E = 848 , - WIFI_N_EXT_SPARE_REUSE_TAG_255_E = 850 , - WIFI_N_EXT_SPARE_REUSE_TAG_257_E = 852 , - WIFI_N_EXT_SPARE_REUSE_TAG_259_E = 854 , - WIFI_N_EXT_SPARE_REUSE_TAG_261_E = 856 , - WIFI_N_EXT_SPARE_REUSE_TAG_263_E = 858 , - WIFI_N_EXT_SPARE_REUSE_TAG_265_E = 860 , - WIFI_N_EXT_SPARE_REUSE_TAG_267_E = 862 , - WIFI_N_EXT_SPARE_REUSE_TAG_269_E = 864 , - WIFI_N_EXT_SPARE_REUSE_TAG_271_E = 866 , - WIFI_N_EXT_SPARE_REUSE_TAG_273_E = 868 , - WIFI_N_EXT_SPARE_REUSE_TAG_275_E = 870 , - WIFI_N_EXT_SPARE_REUSE_TAG_277_E = 872 , - WIFI_N_EXT_SPARE_REUSE_TAG_279_E = 874 , - WIFI_N_EXT_SPARE_REUSE_TAG_281_E = 876 , - WIFI_N_EXT_SPARE_REUSE_TAG_283_E = 878 , - WIFI_N_EXT_SPARE_REUSE_TAG_285_E = 880 , - WIFI_N_EXT_SPARE_REUSE_TAG_287_E = 882 , - WIFI_N_EXT_SPARE_REUSE_TAG_289_E = 884 , - WIFI_N_EXT_SPARE_REUSE_TAG_291_E = 886 , - WIFI_N_EXT_SPARE_REUSE_TAG_293_E = 888 , - WIFI_N_EXT_SPARE_REUSE_TAG_295_E = 890 , - WIFI_N_EXT_SPARE_REUSE_TAG_297_E = 892 , - WIFI_N_EXT_SPARE_REUSE_TAG_299_E = 894 , - WIFI_N_EXT_SPARE_REUSE_TAG_301_E = 896 , - WIFI_N_EXT_SPARE_REUSE_TAG_303_E = 898 , - WIFI_N_EXT_SPARE_REUSE_TAG_305_E = 900 , - WIFI_N_EXT_SPARE_REUSE_TAG_307_E = 902 , - WIFI_N_EXT_SPARE_REUSE_TAG_309_E = 904 , - WIFI_N_EXT_SPARE_REUSE_TAG_311_E = 906 , - WIFI_N_EXT_SPARE_REUSE_TAG_313_E = 908 , - WIFI_N_EXT_SPARE_REUSE_TAG_315_E = 910 , - WIFI_N_EXT_SPARE_REUSE_TAG_317_E = 912 , - WIFI_N_EXT_SPARE_REUSE_TAG_319_E = 914 , - WIFI_N_EXT_SPARE_REUSE_TAG_321_E = 916 , - WIFI_N_EXT_SPARE_REUSE_TAG_323_E = 918 , - WIFI_N_EXT_SPARE_REUSE_TAG_325_E = 920 , - WIFI_N_EXT_SPARE_REUSE_TAG_327_E = 922 , - WIFI_N_EXT_SPARE_REUSE_TAG_329_E = 924 , - WIFI_N_EXT_SPARE_REUSE_TAG_331_E = 926 , - WIFI_N_EXT_SPARE_REUSE_TAG_333_E = 928 , - WIFI_N_EXT_SPARE_REUSE_TAG_335_E = 930 , - WIFI_N_EXT_SPARE_REUSE_TAG_337_E = 932 , - WIFI_N_EXT_SPARE_REUSE_TAG_339_E = 934 , - WIFI_N_EXT_SPARE_REUSE_TAG_341_E = 936 , - WIFI_N_EXT_SPARE_REUSE_TAG_343_E = 938 , - WIFI_N_EXT_SPARE_REUSE_TAG_345_E = 940 , - WIFI_N_EXT_SPARE_REUSE_TAG_347_E = 942 , - WIFI_N_EXT_SPARE_REUSE_TAG_349_E = 944 , - WIFI_N_EXT_SPARE_REUSE_TAG_351_E = 946 , - WIFI_N_EXT_SPARE_REUSE_TAG_353_E = 948 , - WIFI_N_EXT_SPARE_REUSE_TAG_355_E = 950 , - WIFI_N_EXT_SPARE_REUSE_TAG_357_E = 952 , - WIFI_N_EXT_SPARE_REUSE_TAG_359_E = 954 , - WIFI_N_EXT_SPARE_REUSE_TAG_361_E = 956 , - WIFI_N_EXT_SPARE_REUSE_TAG_363_E = 958 , - WIFI_N_EXT_SPARE_REUSE_TAG_365_E = 960 , - WIFI_N_EXT_SPARE_REUSE_TAG_367_E = 962 , - WIFI_N_EXT_SPARE_REUSE_TAG_369_E = 964 , - WIFI_N_EXT_SPARE_REUSE_TAG_371_E = 966 , - WIFI_N_EXT_SPARE_REUSE_TAG_373_E = 968 , - WIFI_N_EXT_SPARE_REUSE_TAG_375_E = 970 , - WIFI_N_EXT_SPARE_REUSE_TAG_377_E = 972 , - WIFI_N_EXT_SPARE_REUSE_TAG_379_E = 974 , - WIFI_N_EXT_SPARE_REUSE_TAG_381_E = 976 , - WIFI_N_EXT_SPARE_REUSE_TAG_383_E = 978 , - WIFI_N_EXT_SPARE_REUSE_TAG_385_E = 980 , - WIFI_N_EXT_SPARE_REUSE_TAG_387_E = 982 , - WIFI_N_EXT_SPARE_REUSE_TAG_389_E = 984 , - WIFI_N_EXT_SPARE_REUSE_TAG_391_E = 986 , - WIFI_N_EXT_SPARE_REUSE_TAG_393_E = 988 , - WIFI_N_EXT_SPARE_REUSE_TAG_395_E = 990 , - WIFI_N_EXT_SPARE_REUSE_TAG_397_E = 992 , - WIFI_N_EXT_SPARE_REUSE_TAG_399_E = 994 , - WIFI_N_EXT_SPARE_REUSE_TAG_401_E = 996 , - WIFI_N_EXT_SPARE_REUSE_TAG_403_E = 998 , - WIFI_N_EXT_SPARE_REUSE_TAG_405_E = 1000 , - WIFI_N_EXT_SPARE_REUSE_TAG_407_E = 1002 , - WIFI_N_EXT_SPARE_REUSE_TAG_409_E = 1004 , - WIFI_N_EXT_SPARE_REUSE_TAG_411_E = 1006 , - WIFI_N_EXT_SPARE_REUSE_TAG_413_E = 1008 , - WIFI_N_EXT_SPARE_REUSE_TAG_415_E = 1010 , - WIFI_N_EXT_SPARE_REUSE_TAG_417_E = 1012 , - WIFI_N_EXT_SPARE_REUSE_TAG_419_E = 1014 , - WIFI_N_EXT_SPARE_REUSE_TAG_421_E = 1016 , - WIFI_N_EXT_SPARE_REUSE_TAG_423_E = 1018 , - WIFI_N_EXT_SPARE_REUSE_TAG_425_E = 1020 -} non_ext_tlv_tag_def__e; - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tqm2sw_completion_ring.h b/drivers/staging/fw-api/hw/fig/v1/tqm2sw_completion_ring.h deleted file mode 100644 index f67deea1f6a1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tqm2sw_completion_ring.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TQM2SW_COMPLETION_RING_H_ -#define _TQM2SW_COMPLETION_RING_H_ - -#include "tx_rate_stats_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_TQM2SW_COMPLETION_RING 8 - -struct tqm2sw_completion_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_desc_virt_addr_or_addr_info; - uint32_t release_source_module : 3, - cache_id : 1, - reserved_2a : 2, - buffer_or_desc_type : 3, - return_buffer_manager : 4, - tqm_release_reason : 4, - rbm_override_valid : 1, - sw_buffer_cookie_11_0 : 12, - cookie_conversion_status : 1, - tqm_completion_error : 1; - uint32_t tqm_status_number : 24, - transmit_count : 7, - sw_release_details_valid : 1; - uint32_t ack_frame_rssi : 8, - first_msdu : 1, - last_msdu : 1, - fw_tx_notify_frame : 3, - buffer_timestamp : 19; - struct tx_rate_stats_info tx_rate_stats; - uint32_t sw_peer_id : 16, - tid : 4, - sw_buffer_cookie_19_12 : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_desc_virt_addr_or_addr_info; - uint32_t tqm_completion_error : 1, - cookie_conversion_status : 1, - sw_buffer_cookie_11_0 : 12, - rbm_override_valid : 1, - tqm_release_reason : 4, - return_buffer_manager : 4, - buffer_or_desc_type : 3, - reserved_2a : 2, - cache_id : 1, - release_source_module : 3; - uint32_t sw_release_details_valid : 1, - transmit_count : 7, - tqm_status_number : 24; - uint32_t buffer_timestamp : 19, - fw_tx_notify_frame : 3, - last_msdu : 1, - first_msdu : 1, - ack_frame_rssi : 8; - struct tx_rate_stats_info tx_rate_stats; - uint32_t looping_count : 4, - sw_buffer_cookie_19_12 : 8, - tid : 4, - sw_peer_id : 16; -#endif -}; - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define TQM2SW_COMPLETION_RING_CACHE_ID_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_CACHE_ID_LSB 3 -#define TQM2SW_COMPLETION_RING_CACHE_ID_MSB 3 -#define TQM2SW_COMPLETION_RING_CACHE_ID_MASK 0x00000008 - -#define TQM2SW_COMPLETION_RING_RESERVED_2A_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_LSB 4 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_MSB 5 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_MASK 0x00000030 - -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_LSB 6 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MSB 8 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_LSB 9 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MSB 12 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MASK 0x00001e00 - -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_LSB 13 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MSB 16 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MASK 0x0001e000 - -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_LSB 17 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MSB 17 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MASK 0x00020000 - -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_LSB 18 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MSB 29 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 - -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_LSB 30 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MSB 30 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MASK 0x40000000 - -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_LSB 31 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MSB 31 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MASK 0x80000000 - -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_LSB 0 -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MSB 23 -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MASK 0x00ffffff - -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_LSB 24 -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MSB 30 -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MASK 0x7f000000 - -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_LSB 31 -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MSB 31 -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 - -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_LSB 0 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MSB 7 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MASK 0x000000ff - -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_LSB 8 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MSB 8 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MASK 0x00000100 - -#define TQM2SW_COMPLETION_RING_LAST_MSDU_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_LSB 9 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_MSB 9 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_MASK 0x00000200 - -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_LSB 10 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MSB 12 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 - -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_LSB 13 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MSB 31 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MASK 0xffffe000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_LSB 1 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MSB 3 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MSB 16 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0001f000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_LSB 17 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MSB 19 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MASK 0x000e0000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 20 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 20 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00100000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_LSB 21 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MSB 24 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MASK 0x01e00000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_LSB 25 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MSB 28 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MASK 0x1e000000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff - -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_LSB 0 -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MSB 15 -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MASK 0x0000ffff - -#define TQM2SW_COMPLETION_RING_TID_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_TID_LSB 16 -#define TQM2SW_COMPLETION_RING_TID_MSB 19 -#define TQM2SW_COMPLETION_RING_TID_MASK 0x000f0000 - -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_LSB 20 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MSB 27 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 - -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_LSB 28 -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MSB 31 -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_cbf_info.h b/drivers/staging/fw-api/hw/fig/v1/tx_cbf_info.h deleted file mode 100644 index fed064ce95a8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_cbf_info.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_CBF_INFO_H_ -#define _TX_CBF_INFO_H_ - -#define NUM_OF_DWORDS_TX_CBF_INFO 16 - -#define NUM_OF_QWORDS_TX_CBF_INFO 8 - -struct tx_cbf_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sw_peer_id : 16, - pre_cbf_duration : 16; - uint32_t brpoll_info_valid : 1, - trigger_brpoll_info_valid : 1, - npda_info_11ac_valid : 1, - npda_info_11ax_valid : 1, - dot11ax_su_extended : 1, - bandwidth : 3, - brpoll_info : 8, - cbf_response_table_base_index : 8, - peer_index : 3, - pkt_type : 4, - txop_duration_all_ones : 1; - uint32_t trigger_brpoll_common_info_15_0 : 16, - trigger_brpoll_common_info_31_16 : 16; - uint32_t trigger_brpoll_user_info_15_0 : 16, - trigger_brpoll_user_info_31_16 : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t addr3_47_32 : 16, - sta_partial_aid : 11, - __reserved_g_0035 : 1, - reserved_8a : 3, - cbf_resp_pwr_mgmt : 1; - uint32_t group_id : 6, - rssi_comb : 8, - reserved_9a : 2, - vht_ndpa_sta_info : 16; - uint32_t he_eht_sta_info_15_0 : 16, - he_eht_sta_info_31_16 : 16; - uint32_t dot11ax_received_format_indication : 1, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_bss_color_id : 6, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_cp_size : 2, - dot11ax_received_ltf_size : 2, - dot11ax_received_coding : 1, - dot11ax_received_dcm : 1, - dot11ax_received_doppler_indication : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_dl_ul_flag : 1, - reserved_11a : 8; - uint32_t sw_response_frame_length : 16, - sw_response_tlv_from_crypto : 1, - wait_sifs_config_valid : 1, - wait_sifs : 2, - __reserved_g_0022 : 1, - secure : 1, - tb___reserved_g_0022_response_required : 2, - emlsr_main_tlv_if : 1, - reserved_12a : 1, - u_sig_puncture_pattern_encoding : 6; - uint32_t dot11be_puncture_bitmap : 16, - dot11be_response : 1, - punctured_response : 1, - npda_info_11be_valid : 1, - eht_duplicate_mode : 2, - reserved_13a : 11; - uint32_t eht_sta_info_39_32 : 8, - unassociated___reserved_g_0022_peer : 1, - reserved_14a : 23; - uint32_t tlv64_padding : 32; -#else - uint32_t pre_cbf_duration : 16, - sw_peer_id : 16; - uint32_t txop_duration_all_ones : 1, - pkt_type : 4, - peer_index : 3, - cbf_response_table_base_index : 8, - brpoll_info : 8, - bandwidth : 3, - dot11ax_su_extended : 1, - npda_info_11ax_valid : 1, - npda_info_11ac_valid : 1, - trigger_brpoll_info_valid : 1, - brpoll_info_valid : 1; - uint32_t trigger_brpoll_common_info_31_16 : 16, - trigger_brpoll_common_info_15_0 : 16; - uint32_t trigger_brpoll_user_info_31_16 : 16, - trigger_brpoll_user_info_15_0 : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t cbf_resp_pwr_mgmt : 1, - reserved_8a : 3, - __reserved_g_0035 : 1, - sta_partial_aid : 11, - addr3_47_32 : 16; - uint32_t vht_ndpa_sta_info : 16, - reserved_9a : 2, - rssi_comb : 8, - group_id : 6; - uint32_t he_eht_sta_info_31_16 : 16, - he_eht_sta_info_15_0 : 16; - uint32_t reserved_11a : 8, - dot11ax_dl_ul_flag : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_received_doppler_indication : 1, - dot11ax_received_dcm : 1, - dot11ax_received_coding : 1, - dot11ax_received_ltf_size : 2, - dot11ax_received_cp_size : 2, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_bss_color_id : 6, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_format_indication : 1; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_12a : 1, - emlsr_main_tlv_if : 1, - tb___reserved_g_0022_response_required : 2, - secure : 1, - __reserved_g_0022 : 1, - wait_sifs : 2, - wait_sifs_config_valid : 1, - sw_response_tlv_from_crypto : 1, - sw_response_frame_length : 16; - uint32_t reserved_13a : 11, - eht_duplicate_mode : 2, - npda_info_11be_valid : 1, - punctured_response : 1, - dot11be_response : 1, - dot11be_puncture_bitmap : 16; - uint32_t reserved_14a : 23, - unassociated___reserved_g_0022_peer : 1, - eht_sta_info_39_32 : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_SW_PEER_ID_LSB 0 -#define TX_CBF_INFO_SW_PEER_ID_MSB 15 -#define TX_CBF_INFO_SW_PEER_ID_MASK 0x000000000000ffff - -#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 -#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 -#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 32 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 32 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x0000000100000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 33 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 33 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x0000000200000000 - -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 34 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 34 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x0000000400000000 - -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 35 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 35 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x0000000800000000 - -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 36 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 36 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000001000000000 - -#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BANDWIDTH_LSB 37 -#define TX_CBF_INFO_BANDWIDTH_MSB 39 -#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e000000000 - -#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BRPOLL_INFO_LSB 40 -#define TX_CBF_INFO_BRPOLL_INFO_MSB 47 -#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff0000000000 - -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 48 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 55 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff000000000000 - -#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PEER_INDEX_LSB 56 -#define TX_CBF_INFO_PEER_INDEX_MSB 58 -#define TX_CBF_INFO_PEER_INDEX_MASK 0x0700000000000000 - -#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PKT_TYPE_LSB 59 -#define TX_CBF_INFO_PKT_TYPE_MSB 62 -#define TX_CBF_INFO_PKT_TYPE_MASK 0x7800000000000000 - -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 63 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 63 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x000000000000ffff - -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 32 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 47 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 48 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 63 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff000000000000 - -#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR1_31_0_LSB 0 -#define TX_CBF_INFO_ADDR1_31_0_MSB 31 -#define TX_CBF_INFO_ADDR1_31_0_MASK 0x00000000ffffffff - -#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR1_47_32_LSB 32 -#define TX_CBF_INFO_ADDR1_47_32_MSB 47 -#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR2_15_0_LSB 48 -#define TX_CBF_INFO_ADDR2_15_0_MSB 63 -#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff000000000000 - -#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x0000000000000018 -#define TX_CBF_INFO_ADDR2_47_16_LSB 0 -#define TX_CBF_INFO_ADDR2_47_16_MSB 31 -#define TX_CBF_INFO_ADDR2_47_16_MASK 0x00000000ffffffff - -#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000000000000018 -#define TX_CBF_INFO_ADDR3_31_0_LSB 32 -#define TX_CBF_INFO_ADDR3_31_0_MSB 63 -#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff00000000 - -#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_ADDR3_47_32_LSB 0 -#define TX_CBF_INFO_ADDR3_47_32_MSB 15 -#define TX_CBF_INFO_ADDR3_47_32_MASK 0x000000000000ffff - -#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 -#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 -#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x0000000007ff0000 - -#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RESERVED_8A_LSB 28 -#define TX_CBF_INFO_RESERVED_8A_MSB 30 -#define TX_CBF_INFO_RESERVED_8A_MASK 0x0000000070000000 - -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x0000000080000000 - -#define TX_CBF_INFO_GROUP_ID_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_GROUP_ID_LSB 32 -#define TX_CBF_INFO_GROUP_ID_MSB 37 -#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f00000000 - -#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RSSI_COMB_LSB 38 -#define TX_CBF_INFO_RSSI_COMB_MSB 45 -#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc000000000 - -#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RESERVED_9A_LSB 46 -#define TX_CBF_INFO_RESERVED_9A_MSB 47 -#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c00000000000 - -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 48 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 63 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff000000000000 - -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x000000000000ffff - -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 48 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 48 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 49 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 49 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 - -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 55 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 55 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0080000000000000 - -#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_RESERVED_11A_LSB 56 -#define TX_CBF_INFO_RESERVED_11A_MSB 63 -#define TX_CBF_INFO_RESERVED_11A_MASK 0xff00000000000000 - -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x000000000000ffff - -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000000010000 - -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000000020000 - -#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_WAIT_SIFS_LSB 18 -#define TX_CBF_INFO_WAIT_SIFS_MSB 19 -#define TX_CBF_INFO_WAIT_SIFS_MASK 0x00000000000c0000 - -#define TX_CBF_INFO_SECURE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SECURE_LSB 21 -#define TX_CBF_INFO_SECURE_MSB 21 -#define TX_CBF_INFO_SECURE_MASK 0x0000000000200000 - -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB 24 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB 24 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK 0x0000000001000000 - -#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_RESERVED_12A_LSB 25 -#define TX_CBF_INFO_RESERVED_12A_MSB 25 -#define TX_CBF_INFO_RESERVED_12A_MASK 0x0000000002000000 - -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 48 -#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 48 -#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 - -#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 49 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 49 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 - -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 50 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 50 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x0004000000000000 - -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 51 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 52 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x0018000000000000 - -#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_RESERVED_13A_LSB 53 -#define TX_CBF_INFO_RESERVED_13A_MSB 63 -#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe0000000000000 - -#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x00000000000000ff - -#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_RESERVED_14A_LSB 9 -#define TX_CBF_INFO_RESERVED_14A_MSB 31 -#define TX_CBF_INFO_RESERVED_14A_MASK 0x00000000fffffe00 - -#define TX_CBF_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_TLV64_PADDING_LSB 32 -#define TX_CBF_INFO_TLV64_PADDING_MSB 63 -#define TX_CBF_INFO_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_setup.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_setup.h deleted file mode 100644 index 24151f70fecd..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_setup.h +++ /dev/null @@ -1,550 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_SETUP_H_ -#define _TX_FES_SETUP_H_ - -#define NUM_OF_DWORDS_TX_FES_SETUP 10 - -#define NUM_OF_QWORDS_TX_FES_SETUP 5 - -struct tx_fes_setup { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t schedule_id : 32; - uint32_t fes_in_11ax_trigger_response_config : 1, - bo_based_tid_aggregation_limit : 4, - __reserved_g_0022 : 1, - expect_i2r_lmr : 1, - transmit_start_reason : 3, - use_alt_power_sr : 1, - static_2_pwr_mode_status : 1, - obss_srg_opport_transmit_status : 1, - srp_based_transmit_status : 1, - obss_pd_based_transmit_status : 1, - puncture_from_all_allowed_modes : 1, - schedule_cmd_ring_id : 5, - fes_control_mode : 2, - number_of_users : 6, - mu_type : 1, - ofdma_triggered_response : 1, - response_to_response_cmd : 1; - uint32_t schedule_try : 4, - reserved_2a : 1, - subband_antenna_selection_en : 1, - txbf : 1, - allow_txop_exceed_in_1st_pkt : 1, - ignore_bw_available : 1, - ignore_tbtt : 1, - static_bandwidth : 3, - set_txop_duration_all_ones : 1, - transmission_contains_mu_rts : 1, - bw_restricted_frames_embedded : 1, - ast_index : 16; - uint32_t cv_id : 8, - trigger_resp_txpdu_ppdu_boundary : 2, - rxpcu_setup_complete_present : 1, - rbo_must_have_data_user_limit : 4, - mu_ndp : 1, - bf_type : 2, - cbf_nc_index_mask : 1, - cbf_nc_index : 3, - cbf_nr_index_mask : 1, - cbf_nr_index : 3, - secure___reserved_g_0022_ista : 1, - ndpa : 1, - wait_sifs : 2, - cbf_feedback_type_mask : 1, - cbf_feedback_type : 1; - uint32_t cbf_sounding_token : 6, - cbf_sounding_token_mask : 1, - cbf_bw_mask : 1, - cbf_bw : 3, - use_static_bw : 1, - coex_nack_count : 5, - sch_tx_burst_ongoing : 1, - gen_tqm_update_mpdu_count_tlv : 1, - rts_tx_over___reserved_g_0016 : 1, - ndp_frame : 3, - optimal_bw_retry_count : 4, - fes_continuation_ratio_threshold : 5; - uint32_t transmit_cca_bitmap : 32; - uint32_t tb___reserved_g_0022 : 1, - __reserved_g_0022_trigger_subtype : 4, - min_cts2self_count : 4, - max_cts2self_count : 4, - wifi_radar_enable : 1, - reserved_6a : 1, - wait_for_chksum_done : 1, - txrx_self_test_enable : 1, - rtt_self_cal_enable : 1, - secure___reserved_g_0022_rsta : 1, - hip_edca_prot_enable : 1, - hip_edca_prot_required : 1, - hip_edca_mini_contention_gap : 8, - last_command_in_burst : 1, - retain_peer_blackout_details : 1, - enable_hw_qos_null : 1; - uint32_t monitor_override_sta_31_0 : 32; - uint32_t monitor_override_sta_36_32 : 5, - enable_qos_null_switch_for_eosp : 1, - __reserved_g_0035 : 1, - secure___reserved_g_0035_smr : 1, - __reserved_g_0035_type : 2, - __reserved_g_0035_trigger_subtype : 4, - reserved_8a : 18; - uint32_t fw2sw_info : 32; -#else - uint32_t schedule_id : 32; - uint32_t response_to_response_cmd : 1, - ofdma_triggered_response : 1, - mu_type : 1, - number_of_users : 6, - fes_control_mode : 2, - schedule_cmd_ring_id : 5, - puncture_from_all_allowed_modes : 1, - obss_pd_based_transmit_status : 1, - srp_based_transmit_status : 1, - obss_srg_opport_transmit_status : 1, - static_2_pwr_mode_status : 1, - use_alt_power_sr : 1, - transmit_start_reason : 3, - expect_i2r_lmr : 1, - __reserved_g_0022 : 1, - bo_based_tid_aggregation_limit : 4, - fes_in_11ax_trigger_response_config : 1; - uint32_t ast_index : 16, - bw_restricted_frames_embedded : 1, - transmission_contains_mu_rts : 1, - set_txop_duration_all_ones : 1, - static_bandwidth : 3, - ignore_tbtt : 1, - ignore_bw_available : 1, - allow_txop_exceed_in_1st_pkt : 1, - txbf : 1, - subband_antenna_selection_en : 1, - reserved_2a : 1, - schedule_try : 4; - uint32_t cbf_feedback_type : 1, - cbf_feedback_type_mask : 1, - wait_sifs : 2, - ndpa : 1, - secure___reserved_g_0022_ista : 1, - cbf_nr_index : 3, - cbf_nr_index_mask : 1, - cbf_nc_index : 3, - cbf_nc_index_mask : 1, - bf_type : 2, - mu_ndp : 1, - rbo_must_have_data_user_limit : 4, - rxpcu_setup_complete_present : 1, - trigger_resp_txpdu_ppdu_boundary : 2, - cv_id : 8; - uint32_t fes_continuation_ratio_threshold : 5, - optimal_bw_retry_count : 4, - ndp_frame : 3, - rts_tx_over___reserved_g_0016 : 1, - gen_tqm_update_mpdu_count_tlv : 1, - sch_tx_burst_ongoing : 1, - coex_nack_count : 5, - use_static_bw : 1, - cbf_bw : 3, - cbf_bw_mask : 1, - cbf_sounding_token_mask : 1, - cbf_sounding_token : 6; - uint32_t transmit_cca_bitmap : 32; - uint32_t enable_hw_qos_null : 1, - retain_peer_blackout_details : 1, - last_command_in_burst : 1, - hip_edca_mini_contention_gap : 8, - hip_edca_prot_required : 1, - hip_edca_prot_enable : 1, - secure___reserved_g_0022_rsta : 1, - rtt_self_cal_enable : 1, - txrx_self_test_enable : 1, - wait_for_chksum_done : 1, - reserved_6a : 1, - wifi_radar_enable : 1, - max_cts2self_count : 4, - min_cts2self_count : 4, - __reserved_g_0022_trigger_subtype : 4, - tb___reserved_g_0022 : 1; - uint32_t monitor_override_sta_31_0 : 32; - uint32_t reserved_8a : 18, - __reserved_g_0035_trigger_subtype : 4, - __reserved_g_0035_type : 2, - secure___reserved_g_0035_smr : 1, - __reserved_g_0035 : 1, - enable_qos_null_switch_for_eosp : 1, - monitor_override_sta_36_32 : 5; - uint32_t fw2sw_info : 32; -#endif -}; - -#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 -#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 -#define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff - -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 - -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 - -#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 -#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 -#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 - -#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 -#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 -#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 - -#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 -#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 -#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 - -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 - -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 - -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 - -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 - -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 - -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 - -#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 -#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 -#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 - -#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 -#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 -#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 - -#define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_MU_TYPE_LSB 61 -#define TX_FES_SETUP_MU_TYPE_MSB 61 -#define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 - -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 - -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 - -#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 -#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 -#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f - -#define TX_FES_SETUP_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RESERVED_2A_LSB 4 -#define TX_FES_SETUP_RESERVED_2A_MSB 4 -#define TX_FES_SETUP_RESERVED_2A_MASK 0x0000000000000010 - -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_LSB 5 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MSB 5 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MASK 0x0000000000000020 - -#define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TXBF_LSB 6 -#define TX_FES_SETUP_TXBF_MSB 6 -#define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 - -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 - -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 - -#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 -#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 -#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 - -#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 -#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 -#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 - -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 - -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 - -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 - -#define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_AST_INDEX_LSB 16 -#define TX_FES_SETUP_AST_INDEX_MSB 31 -#define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 - -#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CV_ID_LSB 32 -#define TX_FES_SETUP_CV_ID_MSB 39 -#define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 - -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 - -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 - -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 - -#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_MU_NDP_LSB 47 -#define TX_FES_SETUP_MU_NDP_MSB 47 -#define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 - -#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_BF_TYPE_LSB 48 -#define TX_FES_SETUP_BF_TYPE_MSB 49 -#define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 - -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 - -#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 -#define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 - -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 - -#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 -#define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 - -#define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_NDPA_LSB 59 -#define TX_FES_SETUP_NDPA_MSB 59 -#define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 - -#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_WAIT_SIFS_LSB 60 -#define TX_FES_SETUP_WAIT_SIFS_MSB 61 -#define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 - -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 - -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 - -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f - -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 - -#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 -#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 -#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 - -#define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_BW_LSB 8 -#define TX_FES_SETUP_CBF_BW_MSB 10 -#define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 - -#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 -#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 -#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 - -#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 -#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 -#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 - -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 - -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 - -#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_NDP_FRAME_LSB 20 -#define TX_FES_SETUP_NDP_FRAME_MSB 22 -#define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000700000 - -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 - -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 - -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 - -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 - -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 - -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 - -#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RESERVED_6A_LSB 14 -#define TX_FES_SETUP_RESERVED_6A_MSB 14 -#define TX_FES_SETUP_RESERVED_6A_MASK 0x0000000000004000 - -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB 15 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB 15 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK 0x0000000000008000 - -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_LSB 16 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MSB 16 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MASK 0x0000000000010000 - -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_LSB 17 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MSB 17 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MASK 0x0000000000020000 - -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_LSB 19 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MSB 19 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MASK 0x0000000000080000 - -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_LSB 20 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MSB 20 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MASK 0x0000000000100000 - -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_LSB 21 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MSB 28 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MASK 0x000000001fe00000 - -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_LSB 29 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MSB 29 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MASK 0x0000000020000000 - -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_LSB 30 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MSB 30 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MASK 0x0000000040000000 - -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB 31 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB 31 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK 0x0000000080000000 - -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 - -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f - -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB 5 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB 5 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK 0x0000000000000020 - -#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_RESERVED_8A_LSB 14 -#define TX_FES_SETUP_RESERVED_8A_MSB 31 -#define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000ffffc000 - -#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_FW2SW_INFO_LSB 32 -#define TX_FES_SETUP_FW2SW_INFO_MSB 63 -#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_1k_ba.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_1k_ba.h deleted file mode 100644 index 4409dc03ac03..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_1k_ba.h +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_1K_BA_H_ -#define _TX_FES_STATUS_1K_BA_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 - -#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 - -struct tx_fes_status_1k_ba { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ack_ba_status_type : 1, - ba_type : 1, - ba_tid : 4, - unexpected_ack_or_ba : 1, - response_timeout : 1, - ack_frame_rssi : 8, - ssn : 12, - reserved_0b : 4; - uint32_t sw_peer_id : 16, - reserved_1a : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; - uint32_t ba_bitmap_287_256 : 32; - uint32_t ba_bitmap_319_288 : 32; - uint32_t ba_bitmap_351_320 : 32; - uint32_t ba_bitmap_383_352 : 32; - uint32_t ba_bitmap_415_384 : 32; - uint32_t ba_bitmap_447_416 : 32; - uint32_t ba_bitmap_479_448 : 32; - uint32_t ba_bitmap_511_480 : 32; - uint32_t ba_bitmap_543_512 : 32; - uint32_t ba_bitmap_575_544 : 32; - uint32_t ba_bitmap_607_576 : 32; - uint32_t ba_bitmap_639_608 : 32; - uint32_t ba_bitmap_671_640 : 32; - uint32_t ba_bitmap_703_672 : 32; - uint32_t ba_bitmap_735_704 : 32; - uint32_t ba_bitmap_767_736 : 32; - uint32_t ba_bitmap_799_768 : 32; - uint32_t ba_bitmap_831_800 : 32; - uint32_t ba_bitmap_863_832 : 32; - uint32_t ba_bitmap_895_864 : 32; - uint32_t ba_bitmap_927_896 : 32; - uint32_t ba_bitmap_959_928 : 32; - uint32_t ba_bitmap_991_960 : 32; - uint32_t ba_bitmap_1023_992 : 32; -#else - uint32_t reserved_0b : 4, - ssn : 12, - ack_frame_rssi : 8, - response_timeout : 1, - unexpected_ack_or_ba : 1, - ba_tid : 4, - ba_type : 1, - ack_ba_status_type : 1; - uint32_t reserved_1a : 16, - sw_peer_id : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; - uint32_t ba_bitmap_287_256 : 32; - uint32_t ba_bitmap_319_288 : 32; - uint32_t ba_bitmap_351_320 : 32; - uint32_t ba_bitmap_383_352 : 32; - uint32_t ba_bitmap_415_384 : 32; - uint32_t ba_bitmap_447_416 : 32; - uint32_t ba_bitmap_479_448 : 32; - uint32_t ba_bitmap_511_480 : 32; - uint32_t ba_bitmap_543_512 : 32; - uint32_t ba_bitmap_575_544 : 32; - uint32_t ba_bitmap_607_576 : 32; - uint32_t ba_bitmap_639_608 : 32; - uint32_t ba_bitmap_671_640 : 32; - uint32_t ba_bitmap_703_672 : 32; - uint32_t ba_bitmap_735_704 : 32; - uint32_t ba_bitmap_767_736 : 32; - uint32_t ba_bitmap_799_768 : 32; - uint32_t ba_bitmap_831_800 : 32; - uint32_t ba_bitmap_863_832 : 32; - uint32_t ba_bitmap_895_864 : 32; - uint32_t ba_bitmap_927_896 : 32; - uint32_t ba_bitmap_959_928 : 32; - uint32_t ba_bitmap_991_960 : 32; - uint32_t ba_bitmap_1023_992 : 32; -#endif -}; - -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 - -#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 -#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 -#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 - -#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 -#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 -#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c - -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 - -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 - -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_SSN_LSB 16 -#define TX_FES_STATUS_1K_BA_SSN_MSB 27 -#define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 - -#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 - -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_ack_or_ba.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_ack_or_ba.h deleted file mode 100644 index 678c639141ba..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_ack_or_ba.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ -#define _TX_FES_STATUS_ACK_OR_BA_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 - -#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5 - -struct tx_fes_status_ack_or_ba { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ack_ba_status_type : 1, - ba_type : 1, - ba_tid : 4, - unexpected_ack_or_ba : 1, - response_timeout : 1, - ack_frame_rssi : 8, - ssn : 12, - reserved_0b : 4; - uint32_t sw_peer_id : 16, - reserved_1a : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; -#else - uint32_t reserved_0b : 4, - ssn : 12, - ack_frame_rssi : 8, - response_timeout : 1, - unexpected_ack_or_ba : 1, - ba_tid : 4, - ba_type : 1, - ack_ba_status_type : 1; - uint32_t reserved_1a : 16, - sw_peer_id : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; -#endif -}; - -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 - -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x0000000000000002 - -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x000000000000003c - -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 - -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 - -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 -#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 -#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x000000000fff0000 - -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0x00000000f0000000 - -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 47 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 48 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff000000000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_end.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_end.h deleted file mode 100644 index b1cccb06c7e1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_end.h +++ /dev/null @@ -1,581 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_END_H_ -#define _TX_FES_STATUS_END_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_END 12 - -#define NUM_OF_QWORDS_TX_FES_STATUS_END 6 - -struct tx_fes_status_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t prot___reserved_g_0046 : 1, - prot___reserved_g_0086 : 1, - prot___reserved_g_0043 : 1, - prot___reserved_g_0053 : 1, - prot___reserved_g_0041 : 1, - __reserved_g_0082 : 1, - __reserved_g_0046 : 1, - __reserved_g_0086 : 1, - __reserved_g_0043 : 1, - __reserved_g_0053 : 1, - __reserved_g_0041 : 1, - __reserved_g_0083 : 1, - global_data_underflow_warning : 1, - global_fes_transmit_result : 4, - cbf_bw_received_valid : 1, - cbf_bw_received : 3, - actual_received_ack_type : 4, - sta_response_count : 6, - more_data_received : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t reserved_after_struct16 : 4, - brp_info_valid : 1, - qos_null_switch_done_for_eosp : 1, - reserved_1a : 5, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - fes_in_11ax_trigger_response_config : 1, - null_delim_inserted_before_mpdus : 1, - only_null_delim_sent : 1; - uint32_t terminate___reserved_g_0022_sequence : 1, - reserved_2b : 5, - response_type : 5, - r2r_end_status_to_follow : 1, - reserved_5a : 3, - __reserved_g_0055 : 1, - __reserved_g_0084 : 1, - prot___reserved_g_0042 : 1, - prot___reserved_g_0052 : 1, - __reserved_g_0042 : 1, - __reserved_g_0052 : 1, - reserved_2c : 11; - uint32_t beamform_masked_user_bitmap_15_0 : 16, - beamform_masked_user_bitmap_31_16 : 16; - uint32_t cbf_segment_request_mask : 8, - cbf_segment_sent_mask : 8, - highest_achieved_data_null_ratio : 5, - use_alt_power_sr : 1, - static_2_pwr_mode_status : 1, - obss_srg_opport_transmit_status : 1, - srp_based_transmit_status : 1, - obss_pd_based_transmit_status : 1, - beamform_masked_user_bitmap_36_32 : 5, - pdg_mpdu_ready : 1; - uint32_t pdg_mpdu_count : 16, - pdg_est_mpdu_tx_count : 16; - uint32_t pdg_overview_length : 24, - txop_duration : 7, - pdg_dropped_mpdu_warning : 1; - uint32_t packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - packet_extension : 3, - fec_type : 1, - stbc : 1, - num_data_symbols : 16, - ru_size : 4, - reserved_17a : 4; - uint32_t num_ltf_symbols : 3, - ltf_size : 2, - cp_setting : 2, - reserved_18a : 5, - dcm : 1, - ldpc_extra_symbol : 1, - force_extra_symbol : 1, - reserved_18b : 1, - tx_pwr_shared : 8, - tx_pwr_unshared : 8; - uint32_t __reserved_g_0022_active_user_map : 16, - __reserved_g_0022_sent_dummy_tx : 1, - __reserved_g_0022_ftm_frame_sent : 1, - __reserved_g_0068 : 1, - __reserved_g_0069 : 1, - prot___reserved_g_0068 : 1, - prot___reserved_g_0069 : 1, - __reserved_g_0056 : 1, - __reserved_g_0085 : 1, - cv_corr_status : 8; - uint32_t current_tx_duration : 16, - reserved_21a : 4, - hw_qos_null_bitmap : 8, - hw_qos_null_setup_missing : 1, - reserved_21b : 3; - uint32_t reserved_22b : 4, - prot___reserved_g_0040 : 1, - prot___reserved_g_0080 : 1, - __reserved_g_0040 : 1, - __reserved_g_0080 : 1, - prot___reserved_g_0063 : 1, - prot___reserved_g_0078 : 1, - __reserved_g_0063 : 1, - __reserved_g_0078 : 1, - prot___reserved_g_0061 : 1, - prot___reserved_g_0076 : 1, - __reserved_g_0061 : 1, - __reserved_g_0076 : 1, - prot___reserved_g_0059 : 1, - prot___reserved_g_0074 : 1, - __reserved_g_0059 : 1, - __reserved_g_0074 : 1, - prot___reserved_g_0057 : 1, - prot___reserved_g_0072 : 1, - __reserved_g_0057 : 1, - __reserved_g_0072 : 1, - coex_signaling_status : 8; -#else - uint32_t more_data_received : 1, - sta_response_count : 6, - actual_received_ack_type : 4, - cbf_bw_received : 3, - cbf_bw_received_valid : 1, - global_fes_transmit_result : 4, - global_data_underflow_warning : 1, - __reserved_g_0083 : 1, - __reserved_g_0041 : 1, - __reserved_g_0053 : 1, - __reserved_g_0043 : 1, - __reserved_g_0086 : 1, - __reserved_g_0046 : 1, - __reserved_g_0082 : 1, - prot___reserved_g_0041 : 1, - prot___reserved_g_0053 : 1, - prot___reserved_g_0043 : 1, - prot___reserved_g_0086 : 1, - prot___reserved_g_0046 : 1; - uint32_t only_null_delim_sent : 1, - null_delim_inserted_before_mpdus : 1, - fes_in_11ax_trigger_response_config : 1, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - reserved_1a : 5, - qos_null_switch_done_for_eosp : 1, - brp_info_valid : 1, - reserved_after_struct16 : 4; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t reserved_2c : 11, - __reserved_g_0052 : 1, - __reserved_g_0042 : 1, - prot___reserved_g_0052 : 1, - prot___reserved_g_0042 : 1, - __reserved_g_0084 : 1, - __reserved_g_0055 : 1, - reserved_5a : 3, - r2r_end_status_to_follow : 1, - response_type : 5, - reserved_2b : 5, - terminate___reserved_g_0022_sequence : 1; - uint32_t beamform_masked_user_bitmap_31_16 : 16, - beamform_masked_user_bitmap_15_0 : 16; - uint32_t pdg_mpdu_ready : 1, - beamform_masked_user_bitmap_36_32 : 5, - obss_pd_based_transmit_status : 1, - srp_based_transmit_status : 1, - obss_srg_opport_transmit_status : 1, - static_2_pwr_mode_status : 1, - use_alt_power_sr : 1, - highest_achieved_data_null_ratio : 5, - cbf_segment_sent_mask : 8, - cbf_segment_request_mask : 8; - uint32_t pdg_est_mpdu_tx_count : 16, - pdg_mpdu_count : 16; - uint32_t pdg_dropped_mpdu_warning : 1, - txop_duration : 7, - pdg_overview_length : 24; - uint32_t reserved_17a : 4, - ru_size : 4, - num_data_symbols : 16, - stbc : 1, - fec_type : 1, - packet_extension : 3, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2; - uint32_t tx_pwr_unshared : 8, - tx_pwr_shared : 8, - reserved_18b : 1, - force_extra_symbol : 1, - ldpc_extra_symbol : 1, - dcm : 1, - reserved_18a : 5, - cp_setting : 2, - ltf_size : 2, - num_ltf_symbols : 3; - uint32_t cv_corr_status : 8, - __reserved_g_0085 : 1, - __reserved_g_0056 : 1, - prot___reserved_g_0069 : 1, - prot___reserved_g_0068 : 1, - __reserved_g_0069 : 1, - __reserved_g_0068 : 1, - __reserved_g_0022_ftm_frame_sent : 1, - __reserved_g_0022_sent_dummy_tx : 1, - __reserved_g_0022_active_user_map : 16; - uint32_t reserved_21b : 3, - hw_qos_null_setup_missing : 1, - hw_qos_null_bitmap : 8, - reserved_21a : 4, - current_tx_duration : 16; - uint32_t coex_signaling_status : 8, - __reserved_g_0072 : 1, - __reserved_g_0057 : 1, - prot___reserved_g_0072 : 1, - prot___reserved_g_0057 : 1, - __reserved_g_0074 : 1, - __reserved_g_0059 : 1, - prot___reserved_g_0074 : 1, - prot___reserved_g_0059 : 1, - __reserved_g_0076 : 1, - __reserved_g_0061 : 1, - prot___reserved_g_0076 : 1, - prot___reserved_g_0061 : 1, - __reserved_g_0078 : 1, - __reserved_g_0063 : 1, - prot___reserved_g_0078 : 1, - prot___reserved_g_0063 : 1, - __reserved_g_0080 : 1, - __reserved_g_0040 : 1, - prot___reserved_g_0080 : 1, - prot___reserved_g_0040 : 1, - reserved_22b : 4; -#endif -}; - -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 - -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 - -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 - -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 - -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 - -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 - -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB 31 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB 31 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 - -#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 -#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 -#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 - -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB 53 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB 53 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK 0x0020000000000000 - -#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_RESERVED_1A_LSB 54 -#define TX_FES_STATUS_END_RESERVED_1A_MSB 58 -#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07c0000000000000 - -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 - -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 - -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 - -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 - -#define TX_FES_STATUS_END_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESERVED_2B_LSB 1 -#define TX_FES_STATUS_END_RESERVED_2B_MSB 5 -#define TX_FES_STATUS_END_RESERVED_2B_MASK 0x000000000000003e - -#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 6 -#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 10 -#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x00000000000007c0 - -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 11 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 11 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000000800 - -#define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESERVED_5A_LSB 12 -#define TX_FES_STATUS_END_RESERVED_5A_MSB 14 -#define TX_FES_STATUS_END_RESERVED_5A_MASK 0x0000000000007000 - -#define TX_FES_STATUS_END_RESERVED_2C_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESERVED_2C_LSB 21 -#define TX_FES_STATUS_END_RESERVED_2C_MSB 31 -#define TX_FES_STATUS_END_RESERVED_2C_MASK 0x00000000ffe00000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 32 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 47 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 48 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 63 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0xffff000000000000 - -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 0 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 7 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x00000000000000ff - -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 8 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 15 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 16 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 20 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x00000000001f0000 - -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 21 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 21 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0000000000200000 - -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 22 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 22 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0000000000400000 - -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 23 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 23 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000000000800000 - -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 24 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 24 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000000001000000 - -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 25 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 25 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000000002000000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 26 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 30 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x000000007c000000 - -#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 31 -#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 31 -#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 32 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 47 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 48 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 63 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0xffff000000000000 - -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 0 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 23 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x0000000000ffffff - -#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_TXOP_DURATION_LSB 24 -#define TX_FES_STATUS_END_TXOP_DURATION_MSB 30 -#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x000000007f000000 - -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 31 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 31 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 32 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 33 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000300000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 34 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 34 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000400000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 35 -#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 37 -#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000003800000000 - -#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_FEC_TYPE_LSB 38 -#define TX_FES_STATUS_END_FEC_TYPE_MSB 38 -#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000004000000000 - -#define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_STBC_LSB 39 -#define TX_FES_STATUS_END_STBC_MSB 39 -#define TX_FES_STATUS_END_STBC_MASK 0x0000008000000000 - -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 40 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 55 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x00ffff0000000000 - -#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_RU_SIZE_LSB 56 -#define TX_FES_STATUS_END_RU_SIZE_MSB 59 -#define TX_FES_STATUS_END_RU_SIZE_MASK 0x0f00000000000000 - -#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_RESERVED_17A_LSB 60 -#define TX_FES_STATUS_END_RESERVED_17A_MSB 63 -#define TX_FES_STATUS_END_RESERVED_17A_MASK 0xf000000000000000 - -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 0 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 2 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000000000007 - -#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_LTF_SIZE_LSB 3 -#define TX_FES_STATUS_END_LTF_SIZE_MSB 4 -#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000000000000018 - -#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_CP_SETTING_LSB 5 -#define TX_FES_STATUS_END_CP_SETTING_MSB 6 -#define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000000000000060 - -#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_RESERVED_18A_LSB 7 -#define TX_FES_STATUS_END_RESERVED_18A_MSB 11 -#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x0000000000000f80 - -#define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_DCM_LSB 12 -#define TX_FES_STATUS_END_DCM_MSB 12 -#define TX_FES_STATUS_END_DCM_MASK 0x0000000000001000 - -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 13 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 13 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000000000002000 - -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 14 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 14 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000000000004000 - -#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_RESERVED_18B_LSB 15 -#define TX_FES_STATUS_END_RESERVED_18B_MSB 15 -#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000000000008000 - -#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 16 -#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 23 -#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x0000000000ff0000 - -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 24 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 31 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0x00000000ff000000 - -#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 56 -#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 63 -#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0xff00000000000000 - -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 0 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 15 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x000000000000ffff - -#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_21A_LSB 16 -#define TX_FES_STATUS_END_RESERVED_21A_MSB 19 -#define TX_FES_STATUS_END_RESERVED_21A_MASK 0x00000000000f0000 - -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB 20 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB 27 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK 0x000000000ff00000 - -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB 28 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB 28 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK 0x0000000010000000 - -#define TX_FES_STATUS_END_RESERVED_21B_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_21B_LSB 29 -#define TX_FES_STATUS_END_RESERVED_21B_MSB 31 -#define TX_FES_STATUS_END_RESERVED_21B_MASK 0x00000000e0000000 - -#define TX_FES_STATUS_END_RESERVED_22B_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_22B_LSB 32 -#define TX_FES_STATUS_END_RESERVED_22B_MSB 35 -#define TX_FES_STATUS_END_RESERVED_22B_MASK 0x0000000f00000000 - -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_LSB 56 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MSB 63 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_prot.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_prot.h deleted file mode 100644 index 702cc1add940..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_prot.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_PROT_H_ -#define _TX_FES_STATUS_PROT_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 4 - -#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 2 - -struct tx_fes_status_prot { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t success : 1, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - reserved_0 : 19, - pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5; - uint32_t frame_type : 2, - frame_subtype : 4, - rx_pwr_mgmt : 1, - status : 1, - duration_field : 16, - reserved_1a : 2, - agc_cbw : 3, - service_cbw : 3; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t reserved_2a : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4, - reserved_0 : 19, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - success : 1; - uint32_t service_cbw : 3, - agc_cbw : 3, - reserved_1a : 2, - duration_field : 16, - status : 1, - rx_pwr_mgmt : 1, - frame_subtype : 4, - frame_type : 2; - uint32_t reserved_2a : 16; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 -#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 -#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 - -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 - -#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 -#define TX_FES_STATUS_PROT_RESERVED_0_MSB 21 -#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000003ffff8 - -#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 22 -#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 25 -#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000003c00000 - -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 26 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 26 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000004000000 - -#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RATE_MCS_LSB 27 -#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 -#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f8000000 - -#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 -#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 -#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 - -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 - -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 - -#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_STATUS_LSB 39 -#define TX_FES_STATUS_PROT_STATUS_MSB 39 -#define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 - -#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 -#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 -#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 - -#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 -#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 -#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 - -#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 -#define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 -#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 - -#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 -#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 -#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00000000000000ff - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x0000000000003f00 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x000000000000c000 - -#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_RESERVED_2A_LSB 16 -#define TX_FES_STATUS_PROT_RESERVED_2A_MSB 31 -#define TX_FES_STATUS_PROT_RESERVED_2A_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_PROT_TLV64_PADDING_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_PROT_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_PROT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start.h deleted file mode 100644 index bc8e06ec59fb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_H_ -#define _TX_FES_STATUS_START_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START 2 - -struct tx_fes_status_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t schedule_id : 32; - uint32_t reserved_1a : 8, - transmit_start_reason : 3, - disabled_user_bitmap_36_32 : 5, - schedule_cmd_ring_id : 5, - fes_control_mode : 2, - schedule_try : 4, - medium_prot_type : 3, - reserved_1b : 2; - uint32_t optimal_bw_try_count : 4, - number_of_users : 7, - coex_nack_count : 5, - cca_ed0 : 16; - uint32_t disabled_user_bitmap_31_0 : 32; -#else - uint32_t schedule_id : 32; - uint32_t reserved_1b : 2, - medium_prot_type : 3, - schedule_try : 4, - fes_control_mode : 2, - schedule_cmd_ring_id : 5, - disabled_user_bitmap_36_32 : 5, - transmit_start_reason : 3, - reserved_1a : 8; - uint32_t cca_ed0 : 16, - coex_nack_count : 5, - number_of_users : 7, - optimal_bw_try_count : 4; - uint32_t disabled_user_bitmap_31_0 : 32; -#endif -}; - -#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 -#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 -#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_RESERVED_1A_LSB 32 -#define TX_FES_STATUS_START_RESERVED_1A_MSB 39 -#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 40 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 42 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x0000070000000000 - -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 43 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 47 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f80000000000 - -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 48 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 52 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 - -#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 53 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 54 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x0060000000000000 - -#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 55 -#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 58 -#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x0780000000000000 - -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 59 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 61 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x3800000000000000 - -#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_RESERVED_1B_LSB 62 -#define TX_FES_STATUS_START_RESERVED_1B_MSB 63 -#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc000000000000000 - -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x000000000000000f - -#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x00000000000007f0 - -#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x000000000000f800 - -#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_CCA_ED0_LSB 16 -#define TX_FES_STATUS_START_CCA_ED0_MSB 31 -#define TX_FES_STATUS_START_CCA_ED0_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 32 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 63 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start_ppdu.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start_ppdu.h deleted file mode 100644 index a87b3b0a0ccc..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start_ppdu.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_PPDU_H_ -#define _TX_FES_STATUS_START_PPDU_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 3 - -struct tx_fes_status_start_ppdu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ppdu_timestamp_lower_32 : 32; - uint32_t ppdu_timestamp_upper_32 : 32; - uint32_t subband_mask : 16, - ndp_frame : 3, - reserved_2b : 1, - coex_based_tx_bw : 3, - coex_based_ant_mask : 8, - reserved_2c : 1; - uint32_t coex_based_tx_pwr_shared_ant : 8, - coex_based_tx_pwr_ant : 8, - concurrent_bt_tx : 1, - concurrent_wlan_tx : 1, - concurrent_wan_tx : 1, - concurrent_wan_rx : 1, - coex_pwr_reduction_bt : 1, - coex_pwr_reduction_wlan : 1, - coex_pwr_reduction_wan : 1, - coex_result_alt_based : 1, - request_packet_bw : 3, - response_type : 5; - uint32_t concurrent_rx_activity_tracker1 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - coex_pwr_reduction_wan_ratid1 : 1, - reserved_4a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t ppdu_timestamp_lower_32 : 32; - uint32_t ppdu_timestamp_upper_32 : 32; - uint32_t reserved_2c : 1, - coex_based_ant_mask : 8, - coex_based_tx_bw : 3, - reserved_2b : 1, - ndp_frame : 3, - subband_mask : 16; - uint32_t response_type : 5, - request_packet_bw : 3, - coex_result_alt_based : 1, - coex_pwr_reduction_wan : 1, - coex_pwr_reduction_wlan : 1, - coex_pwr_reduction_bt : 1, - concurrent_wan_rx : 1, - concurrent_wan_tx : 1, - concurrent_wlan_tx : 1, - concurrent_bt_tx : 1, - coex_based_tx_pwr_ant : 8, - coex_based_tx_pwr_shared_ant : 8; - uint32_t reserved_4a : 18, - coex_pwr_reduction_wan_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker1 : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 32 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 63 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x000000000000ffff - -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 18 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x0000000000070000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 19 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x0000000000080000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x0000000000700000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x0000000080000000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 32 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 39 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 40 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 47 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff0000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 48 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 48 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x0001000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 49 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 49 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 50 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 50 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x0004000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 51 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 51 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x0008000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 52 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 52 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 53 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 53 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 54 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 54 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 55 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 55 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x0080000000000000 - -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 56 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 58 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x0700000000000000 - -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 59 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 63 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf800000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB 0 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB 0 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK 0x0000000000000001 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB 1 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB 1 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK 0x0000000000000002 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB 2 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB 2 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK 0x0000000000000004 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB 3 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB 3 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK 0x0000000000000008 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB 4 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB 4 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK 0x0000000000000010 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB 5 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB 5 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK 0x0000000000000020 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB 6 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB 6 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK 0x0000000000000040 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB 7 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB 7 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK 0x0000000000000080 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB 8 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB 8 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK 0x0000000000000100 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB 9 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB 9 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK 0x0000000000000200 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB 10 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB 10 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK 0x0000000000000400 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_LSB 11 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MSB 11 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MASK 0x0000000000000800 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_LSB 12 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MSB 12 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MASK 0x0000000000001000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_LSB 13 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MSB 13 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MASK 0x0000000000002000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_LSB 14 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MASK 0x00000000ffffc000 - -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start_prot.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start_prot.h deleted file mode 100644 index aca9ac5eb28b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start_prot.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_PROT_H_ -#define _TX_FES_STATUS_START_PROT_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 3 - -struct tx_fes_status_start_prot { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t prot_timestamp_lower_32 : 32; - uint32_t prot_timestamp_upper_32 : 32; - uint32_t subband_mask : 16, - reserved_2b : 4, - prot_coex_based_tx_bw : 3, - prot_coex_based_ant_mask : 8, - prot_coex_result_alt_based : 1; - uint32_t prot_coex_tx_pwr_shared_ant : 8, - prot_coex_tx_pwr_ant : 8, - prot_concurrent_bt_tx : 1, - prot_concurrent_wlan_tx : 1, - prot_concurrent_wan_tx : 1, - prot_concurrent_wan_rx : 1, - prot_coex_pwr_reduction_bt : 1, - prot_coex_pwr_reduction_wlan : 1, - prot_coex_pwr_reduction_wan : 1, - prot_request_packet_bw : 3, - response_type : 5, - reserved_3a : 1; - uint32_t concurrent_rx_activity_tracker1 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - coex_pwr_reduction_wan_ratid1 : 1, - reserved_4a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t prot_timestamp_lower_32 : 32; - uint32_t prot_timestamp_upper_32 : 32; - uint32_t prot_coex_result_alt_based : 1, - prot_coex_based_ant_mask : 8, - prot_coex_based_tx_bw : 3, - reserved_2b : 4, - subband_mask : 16; - uint32_t reserved_3a : 1, - response_type : 5, - prot_request_packet_bw : 3, - prot_coex_pwr_reduction_wan : 1, - prot_coex_pwr_reduction_wlan : 1, - prot_coex_pwr_reduction_bt : 1, - prot_concurrent_wan_rx : 1, - prot_concurrent_wan_tx : 1, - prot_concurrent_wlan_tx : 1, - prot_concurrent_bt_tx : 1, - prot_coex_tx_pwr_ant : 8, - prot_coex_tx_pwr_shared_ant : 8; - uint32_t reserved_4a : 18, - coex_pwr_reduction_wan_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker1 : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 32 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 63 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x000000000000ffff - -#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x00000000000f0000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x0000000000700000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x0000000080000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 32 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 39 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 40 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 47 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff0000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 48 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 48 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x0001000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 49 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 49 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 50 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 50 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x0004000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 51 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 51 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x0008000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 52 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 52 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 53 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 53 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 54 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 54 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 55 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 57 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x0380000000000000 - -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 58 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 62 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c00000000000000 - -#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 63 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 63 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x8000000000000000 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB 0 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB 0 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK 0x0000000000000001 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB 1 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB 1 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK 0x0000000000000002 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB 2 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB 2 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK 0x0000000000000004 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB 3 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB 3 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK 0x0000000000000008 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB 4 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB 4 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK 0x0000000000000010 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB 5 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB 5 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK 0x0000000000000020 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB 6 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB 6 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK 0x0000000000000040 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB 7 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB 7 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK 0x0000000000000080 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB 8 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB 8 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK 0x0000000000000100 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB 9 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB 9 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK 0x0000000000000200 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB 10 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB 10 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK 0x0000000000000400 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_LSB 11 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MSB 11 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MASK 0x0000000000000800 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_LSB 12 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MSB 12 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MASK 0x0000000000001000 - -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_LSB 13 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MSB 13 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MASK 0x0000000000002000 - -#define TX_FES_STATUS_START_PROT_RESERVED_4A_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_LSB 14 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_MSB 31 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_MASK 0x00000000ffffc000 - -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_ppdu.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_ppdu.h deleted file mode 100644 index dad9a040ff46..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_ppdu.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_USER_PPDU_H_ -#define _TX_FES_STATUS_USER_PPDU_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 - -struct tx_fes_status_user_ppdu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t underflow_mpdu_count : 9, - data_underflow_warning : 2, - bw_drop_underflow_warning : 1, - qc_eosp_setting : 1, - mpdu_tx_count : 11, - user_blocked : 1, - pre_trig_response_delim_count : 7; - uint32_t underflow_byte_count : 16, - coex_abort_mpdu_count_valid : 1, - coex_abort_mpdu_count : 9, - transmitted_tid : 4, - txdma_dropped_mpdu_warning : 1, - cv_corr_user_valid_in_phy : 1; - uint32_t duration : 16, - num_eof_delim_added : 16; - uint32_t psdu_octet : 24, - qos_buf_state : 8; - uint32_t num_null_delim_added : 22, - fc_more_data_setting : 1, - fc_pwr_mgt_setting : 1, - nss : 3, - mcs : 5; - uint32_t ht_control : 32; -#else - uint32_t pre_trig_response_delim_count : 7, - user_blocked : 1, - mpdu_tx_count : 11, - qc_eosp_setting : 1, - bw_drop_underflow_warning : 1, - data_underflow_warning : 2, - underflow_mpdu_count : 9; - uint32_t cv_corr_user_valid_in_phy : 1, - txdma_dropped_mpdu_warning : 1, - transmitted_tid : 4, - coex_abort_mpdu_count : 9, - coex_abort_mpdu_count_valid : 1, - underflow_byte_count : 16; - uint32_t num_eof_delim_added : 16, - duration : 16; - uint32_t qos_buf_state : 8, - psdu_octet : 24; - uint32_t mcs : 5, - nss : 3, - fc_pwr_mgt_setting : 1, - fc_more_data_setting : 1, - num_null_delim_added : 22; - uint32_t ht_control : 32; -#endif -}; - -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff - -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 - -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 - -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 - -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 13 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ffe000 - -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 - -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 - -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 - -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 - -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 - -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 - -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 63 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 63 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x8000000000000000 - -#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 -#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 -#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff - -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 - -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 - -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff - -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 22 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 22 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000400000 - -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 23 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 23 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000800000 - -#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_NSS_LSB 24 -#define TX_FES_STATUS_USER_PPDU_NSS_MSB 26 -#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x0000000007000000 - -#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_MCS_LSB 27 -#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 -#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f8000000 - -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_response.h deleted file mode 100644 index a4562d64a9ec..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_response.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ -#define _TX_FES_STATUS_USER_RESPONSE_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 - -#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1 - -struct tx_fes_status_user_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t fes_transmit_result : 4, - reserved_0 : 28; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t pre_padding_fcs_overwritten : 1, - reserved_after_struct16 : 15; -#else - uint32_t reserved_0 : 28, - fes_transmit_result : 4; - uint32_t reserved_after_struct16 : 15, - pre_padding_fcs_overwritten : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; -#endif -}; - -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x000000000000000f - -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 31 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0x00000000fffffff0 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_LSB 48 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MSB 48 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MASK 0x0001000000000000 - -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 49 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 63 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xfffe000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_flush_req.h b/drivers/staging/fw-api/hw/fig/v1/tx_flush_req.h deleted file mode 100644 index af502ec619eb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_flush_req.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FLUSH_REQ_H_ -#define _TX_FLUSH_REQ_H_ - -#define NUM_OF_DWORDS_TX_FLUSH_REQ 2 - -#define NUM_OF_QWORDS_TX_FLUSH_REQ 1 - -struct tx_flush_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t flush_req_reason : 8, - phytx_abort_reason : 8, - flush_req_user_number_or_link_id : 6, - mlo_abort_reason : 5, - reserved_0a : 5; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 5, - mlo_abort_reason : 5, - flush_req_user_number_or_link_id : 6, - phytx_abort_reason : 8, - flush_req_reason : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff - -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00 - -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000 - -#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000 - -#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 -#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 -#define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000 - -#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_TLV64_PADDING_LSB 32 -#define TX_FLUSH_REQ_TLV64_PADDING_MSB 63 -#define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_mpdu_start.h b/drivers/staging/fw-api/hw/fig/v1/tx_mpdu_start.h deleted file mode 100644 index a68fab7a4f2a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_mpdu_start.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MPDU_START_H_ -#define _TX_MPDU_START_H_ - -#define NUM_OF_DWORDS_TX_MPDU_START 10 - -#define NUM_OF_QWORDS_TX_MPDU_START 5 - -struct tx_mpdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mpdu_length : 14, - frame_not_from_tqm : 1, - vht_control_present : 1, - mpdu_header_length : 8, - retry_count : 7, - wds : 1; - uint32_t pn_31_0 : 32; - uint32_t pn_47_32 : 16, - mpdu_sequence_number : 12, - raw_already_encrypted : 1, - frame_type : 2, - txdma_dropped_mpdu_warning : 1; - uint32_t iv_byte_0 : 8, - iv_byte_1 : 8, - iv_byte_2 : 8, - iv_byte_3 : 8; - uint32_t iv_byte_4 : 8, - iv_byte_5 : 8, - iv_byte_6 : 8, - iv_byte_7 : 8; - uint32_t iv_byte_8 : 8, - iv_byte_9 : 8, - iv_byte_10 : 8, - iv_byte_11 : 8; - uint32_t iv_byte_12 : 8, - iv_byte_13 : 8, - iv_byte_14 : 8, - iv_byte_15 : 8; - uint32_t iv_byte_16 : 8, - iv_byte_17 : 8, - iv_len : 5, - icv_len : 5, - vht_control_offset : 6; - uint32_t mpdu_type : 1, - transmit_bw_restriction : 1, - allowed_transmit_bw : 4, - tx_notify_frame : 3, - reserved_8a : 23; - uint32_t tlv64_padding : 32; -#else - uint32_t wds : 1, - retry_count : 7, - mpdu_header_length : 8, - vht_control_present : 1, - frame_not_from_tqm : 1, - mpdu_length : 14; - uint32_t pn_31_0 : 32; - uint32_t txdma_dropped_mpdu_warning : 1, - frame_type : 2, - raw_already_encrypted : 1, - mpdu_sequence_number : 12, - pn_47_32 : 16; - uint32_t iv_byte_3 : 8, - iv_byte_2 : 8, - iv_byte_1 : 8, - iv_byte_0 : 8; - uint32_t iv_byte_7 : 8, - iv_byte_6 : 8, - iv_byte_5 : 8, - iv_byte_4 : 8; - uint32_t iv_byte_11 : 8, - iv_byte_10 : 8, - iv_byte_9 : 8, - iv_byte_8 : 8; - uint32_t iv_byte_15 : 8, - iv_byte_14 : 8, - iv_byte_13 : 8, - iv_byte_12 : 8; - uint32_t vht_control_offset : 6, - icv_len : 5, - iv_len : 5, - iv_byte_17 : 8, - iv_byte_16 : 8; - uint32_t reserved_8a : 23, - tx_notify_frame : 3, - allowed_transmit_bw : 4, - transmit_bw_restriction : 1, - mpdu_type : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 -#define TX_MPDU_START_MPDU_LENGTH_LSB 0 -#define TX_MPDU_START_MPDU_LENGTH_MSB 13 -#define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff - -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 - -#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 - -#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 -#define TX_MPDU_START_RETRY_COUNT_LSB 24 -#define TX_MPDU_START_RETRY_COUNT_MSB 30 -#define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 - -#define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 -#define TX_MPDU_START_WDS_LSB 31 -#define TX_MPDU_START_WDS_MSB 31 -#define TX_MPDU_START_WDS_MASK 0x0000000080000000 - -#define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 -#define TX_MPDU_START_PN_31_0_LSB 32 -#define TX_MPDU_START_PN_31_0_MSB 63 -#define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 - -#define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 -#define TX_MPDU_START_PN_47_32_LSB 0 -#define TX_MPDU_START_PN_47_32_MSB 15 -#define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff - -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 - -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 - -#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 -#define TX_MPDU_START_FRAME_TYPE_LSB 29 -#define TX_MPDU_START_FRAME_TYPE_MSB 30 -#define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 - -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 - -#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_0_LSB 32 -#define TX_MPDU_START_IV_BYTE_0_MSB 39 -#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_1_LSB 40 -#define TX_MPDU_START_IV_BYTE_1_MSB 47 -#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_2_LSB 48 -#define TX_MPDU_START_IV_BYTE_2_MSB 55 -#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 - -#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_3_LSB 56 -#define TX_MPDU_START_IV_BYTE_3_MSB 63 -#define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 - -#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_4_LSB 0 -#define TX_MPDU_START_IV_BYTE_4_MSB 7 -#define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff - -#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_5_LSB 8 -#define TX_MPDU_START_IV_BYTE_5_MSB 15 -#define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 - -#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_6_LSB 16 -#define TX_MPDU_START_IV_BYTE_6_MSB 23 -#define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_7_LSB 24 -#define TX_MPDU_START_IV_BYTE_7_MSB 31 -#define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 - -#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_8_LSB 32 -#define TX_MPDU_START_IV_BYTE_8_MSB 39 -#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_9_LSB 40 -#define TX_MPDU_START_IV_BYTE_9_MSB 47 -#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_10_LSB 48 -#define TX_MPDU_START_IV_BYTE_10_MSB 55 -#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 - -#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_11_LSB 56 -#define TX_MPDU_START_IV_BYTE_11_MSB 63 -#define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 - -#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_12_LSB 0 -#define TX_MPDU_START_IV_BYTE_12_MSB 7 -#define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff - -#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_13_LSB 8 -#define TX_MPDU_START_IV_BYTE_13_MSB 15 -#define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 - -#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_14_LSB 16 -#define TX_MPDU_START_IV_BYTE_14_MSB 23 -#define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_15_LSB 24 -#define TX_MPDU_START_IV_BYTE_15_MSB 31 -#define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 - -#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_16_LSB 32 -#define TX_MPDU_START_IV_BYTE_16_MSB 39 -#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_17_LSB 40 -#define TX_MPDU_START_IV_BYTE_17_MSB 47 -#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_LEN_LSB 48 -#define TX_MPDU_START_IV_LEN_MSB 52 -#define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 - -#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 -#define TX_MPDU_START_ICV_LEN_LSB 53 -#define TX_MPDU_START_ICV_LEN_MSB 57 -#define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 - -#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 - -#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 -#define TX_MPDU_START_MPDU_TYPE_LSB 0 -#define TX_MPDU_START_MPDU_TYPE_MSB 0 -#define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 - -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 - -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c - -#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 -#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 -#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 - -#define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_MPDU_START_RESERVED_8A_LSB 9 -#define TX_MPDU_START_RESERVED_8A_MSB 31 -#define TX_MPDU_START_RESERVED_8A_MASK 0x00000000fffffe00 - -#define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TLV64_PADDING_LSB 32 -#define TX_MPDU_START_TLV64_PADDING_MSB 63 -#define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_msdu_extension.h b/drivers/staging/fw-api/hw/fig/v1/tx_msdu_extension.h deleted file mode 100644 index f8da5593497b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_msdu_extension.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MSDU_EXTENSION_H_ -#define _TX_MSDU_EXTENSION_H_ - -#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 - -struct tx_msdu_extension { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tso_enable : 1, - reserved_0a : 6, - tcp_flag : 9, - tcp_flag_mask : 9, - reserved_0b : 7; - uint32_t l2_length : 16, - ip_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t ip_identification : 16, - udp_length : 16; - uint32_t checksum_offset : 14, - partial_checksum_en : 1, - reserved_4a : 1, - payload_start_offset : 14, - reserved_4b : 2; - uint32_t payload_end_offset : 14, - reserved_5a : 2, - wds : 1, - reserved_5b : 15; - uint32_t buf0_ptr_31_0 : 32; - uint32_t buf0_ptr_39_32 : 8, - reserved_7a : 8, - buf0_len : 16; - uint32_t buf1_ptr_31_0 : 32; - uint32_t buf1_ptr_39_32 : 8, - reserved_9a : 8, - buf1_len : 16; - uint32_t buf2_ptr_31_0 : 32; - uint32_t buf2_ptr_39_32 : 8, - reserved_11a : 8, - buf2_len : 16; - uint32_t buf3_ptr_31_0 : 32; - uint32_t buf3_ptr_39_32 : 8, - reserved_13a : 8, - buf3_len : 16; - uint32_t buf4_ptr_31_0 : 32; - uint32_t buf4_ptr_39_32 : 8, - reserved_15a : 8, - buf4_len : 16; - uint32_t buf5_ptr_31_0 : 32; - uint32_t buf5_ptr_39_32 : 8, - reserved_17a : 8, - buf5_len : 16; -#else - uint32_t reserved_0b : 7, - tcp_flag_mask : 9, - tcp_flag : 9, - reserved_0a : 6, - tso_enable : 1; - uint32_t ip_length : 16, - l2_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t udp_length : 16, - ip_identification : 16; - uint32_t reserved_4b : 2, - payload_start_offset : 14, - reserved_4a : 1, - partial_checksum_en : 1, - checksum_offset : 14; - uint32_t reserved_5b : 15, - wds : 1, - reserved_5a : 2, - payload_end_offset : 14; - uint32_t buf0_ptr_31_0 : 32; - uint32_t buf0_len : 16, - reserved_7a : 8, - buf0_ptr_39_32 : 8; - uint32_t buf1_ptr_31_0 : 32; - uint32_t buf1_len : 16, - reserved_9a : 8, - buf1_ptr_39_32 : 8; - uint32_t buf2_ptr_31_0 : 32; - uint32_t buf2_len : 16, - reserved_11a : 8, - buf2_ptr_39_32 : 8; - uint32_t buf3_ptr_31_0 : 32; - uint32_t buf3_len : 16, - reserved_13a : 8, - buf3_ptr_39_32 : 8; - uint32_t buf4_ptr_31_0 : 32; - uint32_t buf4_len : 16, - reserved_15a : 8, - buf4_ptr_39_32 : 8; - uint32_t buf5_ptr_31_0 : 32; - uint32_t buf5_len : 16, - reserved_17a : 8, - buf5_ptr_39_32 : 8; -#endif -}; - -#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 -#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 -#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 - -#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 -#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 -#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e - -#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 -#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 - -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 - -#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 -#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 - -#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 -#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 -#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 -#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff - -#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 -#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 -#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 -#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff - -#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c -#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 -#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 -#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff - -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 - -#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 -#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 - -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 - -#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 -#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 - -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff - -#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 -#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 - -#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_WDS_LSB 16 -#define TX_MSDU_EXTENSION_WDS_MSB 16 -#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 - -#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 -#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 - -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_7A_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_RESERVED_7A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_7A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_7A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_msdu_start.h b/drivers/staging/fw-api/hw/fig/v1/tx_msdu_start.h deleted file mode 100644 index e62a76009f3a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_msdu_start.h +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MSDU_START_H_ -#define _TX_MSDU_START_H_ - -#define NUM_OF_DWORDS_TX_MSDU_START 8 - -#define NUM_OF_QWORDS_TX_MSDU_START 4 - -struct tx_msdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t msdu_len : 14, - first_msdu : 1, - last_msdu : 1, - encap_type : 2, - epd_en : 1, - da_sa_present : 2, - ipv4_checksum_en : 1, - udp_over_ipv4_checksum_en : 1, - udp_over_ipv6_checksum_en : 1, - tcp_over_ipv4_checksum_en : 1, - tcp_over_ipv6_checksum_en : 1, - dummy_msdu_delimitation : 1, - reserved_0a : 5; - uint32_t tso_enable : 1, - reserved_1a : 6, - tcp_flag : 9, - tcp_flag_mask : 9, - mesh_enable : 1, - reserved_1b : 6; - uint32_t l2_length : 16, - ip_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t ip_identification : 16, - checksum_offset : 13, - partial_checksum_en : 1, - reserved_4 : 2; - uint32_t payload_start_offset : 14, - reserved_5a : 2, - payload_end_offset : 14, - reserved_5b : 2; - uint32_t udp_length : 16, - reserved_6 : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 5, - dummy_msdu_delimitation : 1, - tcp_over_ipv6_checksum_en : 1, - tcp_over_ipv4_checksum_en : 1, - udp_over_ipv6_checksum_en : 1, - udp_over_ipv4_checksum_en : 1, - ipv4_checksum_en : 1, - da_sa_present : 2, - epd_en : 1, - encap_type : 2, - last_msdu : 1, - first_msdu : 1, - msdu_len : 14; - uint32_t reserved_1b : 6, - mesh_enable : 1, - tcp_flag_mask : 9, - tcp_flag : 9, - reserved_1a : 6, - tso_enable : 1; - uint32_t ip_length : 16, - l2_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t reserved_4 : 2, - partial_checksum_en : 1, - checksum_offset : 13, - ip_identification : 16; - uint32_t reserved_5b : 2, - payload_end_offset : 14, - reserved_5a : 2, - payload_start_offset : 14; - uint32_t reserved_6 : 16, - udp_length : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_MSDU_LEN_LSB 0 -#define TX_MSDU_START_MSDU_LEN_MSB 13 -#define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff - -#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000 -#define TX_MSDU_START_FIRST_MSDU_LSB 14 -#define TX_MSDU_START_FIRST_MSDU_MSB 14 -#define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000 - -#define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000 -#define TX_MSDU_START_LAST_MSDU_LSB 15 -#define TX_MSDU_START_LAST_MSDU_MSB 15 -#define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000 - -#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_ENCAP_TYPE_LSB 16 -#define TX_MSDU_START_ENCAP_TYPE_MSB 17 -#define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000 - -#define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_EPD_EN_LSB 18 -#define TX_MSDU_START_EPD_EN_MSB 18 -#define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000 - -#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000 -#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 -#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 -#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000 - -#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000 - -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000 - -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000 - -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000 - -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000 - -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000 - -#define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_0A_LSB 27 -#define TX_MSDU_START_RESERVED_0A_MSB 31 -#define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000 - -#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TSO_ENABLE_LSB 32 -#define TX_MSDU_START_TSO_ENABLE_MSB 32 -#define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000 - -#define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_1A_LSB 33 -#define TX_MSDU_START_RESERVED_1A_MSB 38 -#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000 - -#define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_FLAG_LSB 39 -#define TX_MSDU_START_TCP_FLAG_MSB 47 -#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000 - -#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_FLAG_MASK_LSB 48 -#define TX_MSDU_START_TCP_FLAG_MASK_MSB 56 -#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000 - -#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_MESH_ENABLE_LSB 57 -#define TX_MSDU_START_MESH_ENABLE_MSB 57 -#define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000 - -#define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_1B_LSB 58 -#define TX_MSDU_START_RESERVED_1B_MSB 63 -#define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000 - -#define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008 -#define TX_MSDU_START_L2_LENGTH_LSB 0 -#define TX_MSDU_START_L2_LENGTH_MSB 15 -#define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff - -#define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008 -#define TX_MSDU_START_IP_LENGTH_LSB 16 -#define TX_MSDU_START_IP_LENGTH_MSB 31 -#define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000 - -#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008 -#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32 -#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63 -#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 - -#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010 -#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 -#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 -#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff - -#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 -#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 -#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000 - -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000 - -#define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_4_LSB 30 -#define TX_MSDU_START_RESERVED_4_MSB 31 -#define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000 - -#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000 - -#define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_5A_LSB 46 -#define TX_MSDU_START_RESERVED_5A_MSB 47 -#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000 - -#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000 - -#define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_5B_LSB 62 -#define TX_MSDU_START_RESERVED_5B_MSB 63 -#define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000 - -#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018 -#define TX_MSDU_START_UDP_LENGTH_LSB 0 -#define TX_MSDU_START_UDP_LENGTH_MSB 15 -#define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff - -#define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018 -#define TX_MSDU_START_RESERVED_6_LSB 16 -#define TX_MSDU_START_RESERVED_6_MSB 31 -#define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000 - -#define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018 -#define TX_MSDU_START_TLV64_PADDING_LSB 32 -#define TX_MSDU_START_TLV64_PADDING_MSB 63 -#define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_peer_entry.h b/drivers/staging/fw-api/hw/fig/v1/tx_peer_entry.h deleted file mode 100644 index c26c7f6a3e05..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_peer_entry.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_PEER_ENTRY_H_ -#define _TX_PEER_ENTRY_H_ - -#define NUM_OF_DWORDS_TX_PEER_ENTRY 22 - -#define NUM_OF_QWORDS_TX_PEER_ENTRY 11 - -struct tx_peer_entry { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mac_addr_a_31_0 : 32; - uint32_t mac_addr_a_47_32 : 16, - mac_addr_b_15_0 : 16; - uint32_t mac_addr_b_47_16 : 32; - uint32_t use_ad_b : 1, - strip_insert_vlan_inner : 1, - strip_insert_vlan_outer : 1, - vlan_llc_mode : 1, - key_type : 4, - a_msdu_wds_ad3_ad4 : 3, - ignore_hard_filters : 1, - ignore_soft_filters : 1, - epd_output : 1, - wds : 1, - insert_or_strip : 1, - sw_filter_id : 16; - uint32_t temporal_key_31_0 : 32; - uint32_t temporal_key_63_32 : 32; - uint32_t temporal_key_95_64 : 32; - uint32_t temporal_key_127_96 : 32; - uint32_t temporal_key_159_128 : 32; - uint32_t temporal_key_191_160 : 32; - uint32_t temporal_key_223_192 : 32; - uint32_t temporal_key_255_224 : 32; - uint32_t sta_partial_aid : 11, - transmit_vif : 4, - block_this_user : 1, - mesh_amsdu_mode : 2, - use_qos_alt_mute_mask : 1, - dl_ul_direction : 1, - use_ad_c : 1, - a_msdu_11s_fromtods_10_ad3 : 2, - multi_link_addr_ad3_valid : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_ad1_trans_dis : 1, - data_fromtods_00_ad3 : 2, - mgmt_fromtods_00_ad3 : 2, - reserved_12 : 1; - uint32_t insert_vlan_outer_tci : 16, - insert_vlan_inner_tci : 16; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0008 : 16, - __reserved_g_0009 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t multi_link_addr_crypto_enable : 1, - a_msdu_fromtods_10_ad3 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_11_ad4 : 2, - reserved_17a : 9, - sw_peer_id : 16; - uint32_t mac_addr_c_31_0 : 32; - uint32_t mac_addr_c_47_32 : 16, - multi_link_addr_ad3_47_32 : 16; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t mac_addr_a_31_0 : 32; - uint32_t mac_addr_b_15_0 : 16, - mac_addr_a_47_32 : 16; - uint32_t mac_addr_b_47_16 : 32; - uint32_t sw_filter_id : 16, - insert_or_strip : 1, - wds : 1, - epd_output : 1, - ignore_soft_filters : 1, - ignore_hard_filters : 1, - a_msdu_wds_ad3_ad4 : 3, - key_type : 4, - vlan_llc_mode : 1, - strip_insert_vlan_outer : 1, - strip_insert_vlan_inner : 1, - use_ad_b : 1; - uint32_t temporal_key_31_0 : 32; - uint32_t temporal_key_63_32 : 32; - uint32_t temporal_key_95_64 : 32; - uint32_t temporal_key_127_96 : 32; - uint32_t temporal_key_159_128 : 32; - uint32_t temporal_key_191_160 : 32; - uint32_t temporal_key_223_192 : 32; - uint32_t temporal_key_255_224 : 32; - uint32_t reserved_12 : 1, - mgmt_fromtods_00_ad3 : 2, - data_fromtods_00_ad3 : 2, - multi_link_addr_ad1_trans_dis : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_ad3_valid : 1, - a_msdu_11s_fromtods_10_ad3 : 2, - use_ad_c : 1, - dl_ul_direction : 1, - use_qos_alt_mute_mask : 1, - mesh_amsdu_mode : 2, - block_this_user : 1, - transmit_vif : 4, - sta_partial_aid : 11; - uint32_t insert_vlan_inner_tci : 16, - insert_vlan_outer_tci : 16; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0009 : 16, - __reserved_g_0008 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t sw_peer_id : 16, - reserved_17a : 9, - a_msdu_fromtods_11_ad4 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_10_ad3 : 2, - multi_link_addr_crypto_enable : 1; - uint32_t mac_addr_c_31_0 : 32; - uint32_t multi_link_addr_ad3_47_32 : 16, - mac_addr_c_47_32 : 16; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_USE_AD_B_LSB 32 -#define TX_PEER_ENTRY_USE_AD_B_MSB 32 -#define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 - -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 - -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 - -#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 - -#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_KEY_TYPE_LSB 36 -#define TX_PEER_ENTRY_KEY_TYPE_MSB 39 -#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 - -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 - -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 - -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 - -#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 -#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 -#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 - -#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_WDS_LSB 46 -#define TX_PEER_ENTRY_WDS_MSB 46 -#define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 - -#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 - -#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 -#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 -#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff - -#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 -#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 -#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 - -#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 - -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 - -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 - -#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 - -#define TX_PEER_ENTRY_USE_AD_C_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_USE_AD_C_LSB 20 -#define TX_PEER_ENTRY_USE_AD_C_MSB 20 -#define TX_PEER_ENTRY_USE_AD_C_MASK 0x0000000000100000 - -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_LSB 21 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MSB 22 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MASK 0x0000000000600000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_LSB 23 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MSB 23 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MASK 0x0000000000800000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 24 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 24 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0000000001000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 25 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 25 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x0000000002000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 26 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 26 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x0000000004000000 - -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_LSB 27 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MSB 28 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MASK 0x0000000018000000 - -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_LSB 29 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MSB 30 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MASK 0x0000000060000000 - -#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_RESERVED_12_LSB 31 -#define TX_PEER_ENTRY_RESERVED_12_MSB 31 -#define TX_PEER_ENTRY_RESERVED_12_MASK 0x0000000080000000 - -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_LSB 33 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MSB 34 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MASK 0x0000000600000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_LSB 35 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MSB 36 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MASK 0x0000001800000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_LSB 37 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MSB 38 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MASK 0x0000006000000000 - -#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_RESERVED_17A_LSB 39 -#define TX_PEER_ENTRY_RESERVED_17A_MSB 47 -#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000ff8000000000 - -#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 -#define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 -#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_LSB 32 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MSB 47 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_LSB 48 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MSB 63 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_OFFSET 0x0000000000000050 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_LSB 0 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MSB 31 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TLV64_PADDING_OFFSET 0x0000000000000050 -#define TX_PEER_ENTRY_TLV64_PADDING_LSB 32 -#define TX_PEER_ENTRY_TLV64_PADDING_MSB 63 -#define TX_PEER_ENTRY_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_queue_extension.h b/drivers/staging/fw-api/hw/fig/v1/tx_queue_extension.h deleted file mode 100644 index 883383a9d8f2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_queue_extension.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_QUEUE_EXTENSION_H_ -#define _TX_QUEUE_EXTENSION_H_ - -#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 18 - -#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 9 - -struct tx_queue_extension { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t frame_ctl : 16, - qos_ctl : 16; - uint32_t ampdu_flag : 1, - tx_notify_no_htc_override : 1, - reserved_1a : 7, - checksum_tso_disable_for_frag : 1, - key_id : 8, - qos_buf_state_overwrite : 1, - buf_state_sta_id : 1, - buf_state_source : 1, - ht_control_overwrite_enable : 1, - ht_control_overwrite_source : 4, - reserved_1b : 6; - uint32_t ul_headroom_insertion_enable : 1, - ul_headroom_offset : 5, - bqrp_insertion_enable : 1, - bqrp_offset : 5, - ul_headroom_rsvd_7_6 : 2, - bqr_rsvd_9_8 : 2, - base_pn_63_48 : 16; - uint32_t base_pn_95_64 : 32; - uint32_t base_pn_127_96 : 32; - uint32_t ht_control_field_bw20 : 32; - uint32_t ht_control_field_bw40 : 32; - uint32_t ht_control_field_bw80 : 32; - uint32_t ht_control_field_bw160 : 32; - uint32_t ht_control_overwrite_mask : 32; - uint32_t cas_control_info : 8, - cas_offset : 5, - cas_insertion_enable : 1, - reserved_10a : 2, - ht_control_overwrite_source_for_srp : 4, - ht_control_overwrite_source_for_bsrp : 4, - pre_padding_fcs_overwrite_enable : 1, - reserved_10b : 5, - mpdu_hdr_len_override_en : 1, - bar_ssn_overwrite_enable : 1; - uint32_t bar_ssn_offset : 12, - mpdu_hdr_len_override_val : 9, - reserved_11a : 11; - uint32_t ht_control_field_bw320 : 32; - uint32_t fw2sw_info : 32; - uint32_t pre_padding_fcs_overwrite_offset : 16, - icf_blackout_info_offset : 16; - uint32_t trigger_common_info_length : 6, - cmf_overwrite_offset : 14, - reserved_15a : 12; - uint32_t hdr_ctrl_prot_key_id_byte_offset : 14, - hdr_ctrl_prot_key_id_bit_offset : 3, - ctrl_pkt_protect : 1, - mac_hdr_protect : 1, - hdr_ctrl_prot_tx_peer_idx : 11, - reserved_16a : 2; - uint32_t pad_byte_offset : 16, - pad_byte_offset_valid : 1, - reserved_17a : 15; -#else - uint32_t qos_ctl : 16, - frame_ctl : 16; - uint32_t reserved_1b : 6, - ht_control_overwrite_source : 4, - ht_control_overwrite_enable : 1, - buf_state_source : 1, - buf_state_sta_id : 1, - qos_buf_state_overwrite : 1, - key_id : 8, - checksum_tso_disable_for_frag : 1, - reserved_1a : 7, - tx_notify_no_htc_override : 1, - ampdu_flag : 1; - uint32_t base_pn_63_48 : 16, - bqr_rsvd_9_8 : 2, - ul_headroom_rsvd_7_6 : 2, - bqrp_offset : 5, - bqrp_insertion_enable : 1, - ul_headroom_offset : 5, - ul_headroom_insertion_enable : 1; - uint32_t base_pn_95_64 : 32; - uint32_t base_pn_127_96 : 32; - uint32_t ht_control_field_bw20 : 32; - uint32_t ht_control_field_bw40 : 32; - uint32_t ht_control_field_bw80 : 32; - uint32_t ht_control_field_bw160 : 32; - uint32_t ht_control_overwrite_mask : 32; - uint32_t bar_ssn_overwrite_enable : 1, - mpdu_hdr_len_override_en : 1, - reserved_10b : 5, - pre_padding_fcs_overwrite_enable : 1, - ht_control_overwrite_source_for_bsrp : 4, - ht_control_overwrite_source_for_srp : 4, - reserved_10a : 2, - cas_insertion_enable : 1, - cas_offset : 5, - cas_control_info : 8; - uint32_t reserved_11a : 11, - mpdu_hdr_len_override_val : 9, - bar_ssn_offset : 12; - uint32_t ht_control_field_bw320 : 32; - uint32_t fw2sw_info : 32; - uint32_t icf_blackout_info_offset : 16, - pre_padding_fcs_overwrite_offset : 16; - uint32_t reserved_15a : 12, - cmf_overwrite_offset : 14, - trigger_common_info_length : 6; - uint32_t reserved_16a : 2, - hdr_ctrl_prot_tx_peer_idx : 11, - mac_hdr_protect : 1, - ctrl_pkt_protect : 1, - hdr_ctrl_prot_key_id_bit_offset : 3, - hdr_ctrl_prot_key_id_byte_offset : 14; - uint32_t reserved_17a : 15, - pad_byte_offset_valid : 1, - pad_byte_offset : 16; -#endif -}; - -#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 -#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 -#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff - -#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 -#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 -#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 - -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 - -#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 -#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 -#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 - -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 - -#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 -#define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 -#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 - -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 - -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 - -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 -#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e - -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 - -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 - -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 - -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x0000000000000010 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x0000000000000020 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff - -#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 - -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 - -#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 -#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 -#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 - -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_LSB 24 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MSB 24 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MASK 0x0000000001000000 - -#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 25 -#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 -#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003e000000 - -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 - -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 - -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 - -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 -#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 32 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 63 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_LSB 0 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MSB 15 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MASK 0x000000000000ffff - -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_LSB 16 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MSB 31 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_LSB 32 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MSB 37 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MASK 0x0000003f00000000 - -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_LSB 38 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MSB 51 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MASK 0x000fffc000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_15A_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_RESERVED_15A_LSB 52 -#define TX_QUEUE_EXTENSION_RESERVED_15A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_15A_MASK 0xfff0000000000000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_LSB 0 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MSB 13 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MASK 0x0000000000003fff - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_LSB 14 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MSB 16 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MASK 0x000000000001c000 - -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_LSB 17 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MSB 17 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MASK 0x0000000000020000 - -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_LSB 18 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MSB 18 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MASK 0x0000000000040000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_LSB 19 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MSB 29 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MASK 0x000000003ff80000 - -#define TX_QUEUE_EXTENSION_RESERVED_16A_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_RESERVED_16A_LSB 30 -#define TX_QUEUE_EXTENSION_RESERVED_16A_MSB 31 -#define TX_QUEUE_EXTENSION_RESERVED_16A_MASK 0x00000000c0000000 - -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MSB 47 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MASK 0x0000ffff00000000 - -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_LSB 48 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MSB 48 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MASK 0x0001000000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_17A_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_RESERVED_17A_LSB 49 -#define TX_QUEUE_EXTENSION_RESERVED_17A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_17A_MASK 0xfffe000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/fig/v1/tx_rate_stats_info.h deleted file mode 100644 index ce84032dd353..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_rate_stats_info.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_RATE_STATS_INFO_H_ -#define _TX_RATE_STATS_INFO_H_ - -#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 - -struct tx_rate_stats_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_rate_stats_info_valid : 1, - transmit_bw : 3, - transmit_pkt_type : 4, - transmit_stbc : 1, - transmit_ldpc : 1, - transmit_sgi : 2, - transmit_mcs : 5, - unequal_modulation_info : 3, - ofdma_transmission : 1, - reserved_0a : 4, - tones_in_ru : 4, - transmit_nss : 3; - uint32_t ppdu_transmission_tsf : 32; -#else - uint32_t transmit_nss : 3, - tones_in_ru : 4, - reserved_0a : 4, - ofdma_transmission : 1, - unequal_modulation_info : 3, - transmit_mcs : 5, - transmit_sgi : 2, - transmit_ldpc : 1, - transmit_stbc : 1, - transmit_pkt_type : 4, - transmit_bw : 3, - tx_rate_stats_info_valid : 1; - uint32_t ppdu_transmission_tsf : 32; -#endif -}; - -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 - -#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e - -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0 - -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100 - -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200 - -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00 - -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 16 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0001f000 - -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_LSB 17 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MSB 19 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MASK 0x000e0000 - -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 20 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 20 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00100000 - -#define TX_RATE_STATS_INFO_RESERVED_0A_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_RESERVED_0A_LSB 21 -#define TX_RATE_STATS_INFO_RESERVED_0A_MSB 24 -#define TX_RATE_STATS_INFO_RESERVED_0A_MASK 0x01e00000 - -#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 25 -#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28 -#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1e000000 - -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB 29 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB 31 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK 0xe0000000 - -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/fig/v1/tx_raw_or_native_frame_setup.h deleted file mode 100644 index 220a82edf96d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_raw_or_native_frame_setup.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ -#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ - -#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 4 - -#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 - -struct tx_raw_or_native_frame_setup { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t fc_to_ds_mask : 1, - fc_from_ds_mask : 1, - fc_more_frag_mask : 1, - fc_retry_mask : 1, - fc_pwr_mgt_mask : 1, - fc_more_data_mask : 1, - fc_prot_frame_mask : 1, - fc_order_mask : 1, - duration_field_mask : 1, - sequence_control_mask : 1, - qc_tid_mask : 1, - qc_eosp_mask : 1, - qc_ack_policy_mask : 1, - qc_amsdu_mask : 1, - reserved_0a : 1, - qc_15to8_mask : 1, - iv_mask : 1, - fc_to_ds_setting : 1, - fc_from_ds_setting : 1, - fc_more_frag_setting : 1, - fc_retry_setting : 2, - fc_pwr_mgt_setting : 1, - fc_more_data_setting : 2, - fc_prot_frame_setting : 2, - fc_order_setting : 1, - qc_tid_setting : 4; - uint32_t qc_eosp_setting : 2, - qc_ack_policy_setting : 2, - qc_amsdu_setting : 1, - qc_15to8_setting : 8, - mlo_addr_override : 1, - mlo_ignore_addr3_override : 1, - sequence_control_source : 1, - fragment_number : 4, - sequence_number : 12; - uint32_t mlo_addr_override_for_ctrl : 1, - reserved_2a : 31; - uint32_t tlv64_padding : 32; -#else - uint32_t qc_tid_setting : 4, - fc_order_setting : 1, - fc_prot_frame_setting : 2, - fc_more_data_setting : 2, - fc_pwr_mgt_setting : 1, - fc_retry_setting : 2, - fc_more_frag_setting : 1, - fc_from_ds_setting : 1, - fc_to_ds_setting : 1, - iv_mask : 1, - qc_15to8_mask : 1, - reserved_0a : 1, - qc_amsdu_mask : 1, - qc_ack_policy_mask : 1, - qc_eosp_mask : 1, - qc_tid_mask : 1, - sequence_control_mask : 1, - duration_field_mask : 1, - fc_order_mask : 1, - fc_prot_frame_mask : 1, - fc_more_data_mask : 1, - fc_pwr_mgt_mask : 1, - fc_retry_mask : 1, - fc_more_frag_mask : 1, - fc_from_ds_mask : 1, - fc_to_ds_mask : 1; - uint32_t sequence_number : 12, - fragment_number : 4, - sequence_control_source : 1, - mlo_ignore_addr3_override : 1, - mlo_addr_override : 1, - qc_15to8_setting : 8, - qc_amsdu_setting : 1, - qc_ack_policy_setting : 2, - qc_eosp_setting : 2; - uint32_t reserved_2a : 31, - mlo_addr_override_for_ctrl : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x0000000000000001 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x0000000000000002 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x0000000000000004 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x0000000000000008 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x0000000000000010 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x0000000000000020 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x0000000000000040 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x0000000000000080 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x0000000000000100 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x0000000000000200 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x0000000000000400 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x0000000000000800 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x0000000000001000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x0000000000002000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x0000000000004000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x0000000000008000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x0000000000010000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x0000000000020000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x0000000000040000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x0000000000080000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x0000000000300000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x0000000000400000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x0000000001800000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x0000000006000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x0000000008000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0x00000000f0000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 32 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 33 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x0000000300000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 34 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 35 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c00000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 36 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 36 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x0000001000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 37 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 44 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 45 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 45 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x0000200000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 46 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 46 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x0000400000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 47 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 47 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x0000800000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 48 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 51 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f000000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 52 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 63 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff0000000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_LSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MASK 0x0000000000000001 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_LSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MSB 31 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MASK 0x00000000fffffffe - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_LSB 32 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MSB 63 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_basics.h deleted file mode 100644 index 4032a78ad617..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_basics.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_BUFFER_BASICS_H_ -#define _TXPCU_BUFFER_BASICS_H_ - -#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 - -struct txpcu_buffer_basics { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t available_memory : 8, - partial_tx_data_tlv_count : 8, - tx_data_tlv_count : 16; -#else - uint32_t tx_data_tlv_count : 16, - partial_tx_data_tlv_count : 8, - available_memory : 8; -#endif -}; - -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff - -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 - -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_status.h deleted file mode 100644 index 847ca277267d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_status.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_BUFFER_STATUS_H_ -#define _TXPCU_BUFFER_STATUS_H_ - -#include "txpcu_buffer_basics.h" -#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 - -#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1 - -struct txpcu_buffer_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct txpcu_buffer_basics txpcu_basix_buffer_info; - uint32_t reserved : 15, - msdu_end : 1, - tx_data_sync_value : 16; -#else - struct txpcu_buffer_basics txpcu_basix_buffer_info; - uint32_t tx_data_sync_value : 16, - msdu_end : 1, - reserved : 15; -#endif -}; - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 - -#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_RESERVED_LSB 32 -#define TXPCU_BUFFER_STATUS_RESERVED_MSB 46 -#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000 - -#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47 -#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47 -#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 - -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/fig/v1/txpcu_user_buffer_status.h deleted file mode 100644 index f6ad0fd73721..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/txpcu_user_buffer_status.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_USER_BUFFER_STATUS_H_ -#define _TXPCU_USER_BUFFER_STATUS_H_ - -#include "txpcu_buffer_basics.h" -#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 - -#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1 - -struct txpcu_user_buffer_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct txpcu_buffer_basics txpcu_basic_buffer_info; - uint32_t stored_word_count_user : 14, - reserved_1a : 1, - msdu_end : 1, - tx_data_sync_value : 16; -#else - struct txpcu_buffer_basics txpcu_basic_buffer_info; - uint32_t tx_data_sync_value : 16, - msdu_end : 1, - reserved_1a : 1, - stored_word_count_user : 14; -#endif -}; - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 - -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 32 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 45 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff00000000 - -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 46 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 46 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x0000400000000000 - -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 47 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 47 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 - -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_su_mu_info.h deleted file mode 100644 index 1a08f3ab39b2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_su_mu_info.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _U_SIG_EHT_SU_MU_INFO_H_ -#define _U_SIG_EHT_SU_MU_INFO_H_ - -#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 - -struct u_sig_eht_su_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_version : 3, - transmit_bw : 3, - dl_ul_flag : 1, - bss_color_id : 6, - txop_duration : 7, - disregard_0a : 5, - validate_0b : 1, - reserved_0c : 6; - uint32_t eht_ppdu_sig_cmn_type : 2, - validate_1a : 1, - punctured_channel_information : 5, - validate_1b : 1, - mcs_of_eht_sig : 2, - num_eht_sig_symbols : 5, - crc : 4, - tail : 6, - dot11ax_su_extended : 1, - reserved_1d : 3, - rx_ndp : 1, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0c : 6, - validate_0b : 1, - disregard_0a : 5, - txop_duration : 7, - bss_color_id : 6, - dl_ul_flag : 1, - transmit_bw : 3, - phy_version : 3; - uint32_t rx_integrity_check_passed : 1, - rx_ndp : 1, - reserved_1d : 3, - dot11ax_su_extended : 1, - tail : 6, - crc : 4, - num_eht_sig_symbols : 5, - mcs_of_eht_sig : 2, - validate_1b : 1, - punctured_channel_information : 5, - validate_1a : 1, - eht_ppdu_sig_cmn_type : 2; -#endif -}; - -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 - -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 - -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 - -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 - -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 - -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 - -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 - -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 - -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 - -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 - -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 - -#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 -#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 -#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 - -#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 -#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 -#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 - -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 - -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 - -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 - -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_tb_info.h deleted file mode 100644 index 8e417b38d233..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_tb_info.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _U_SIG_EHT_TB_INFO_H_ -#define _U_SIG_EHT_TB_INFO_H_ - -#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 - -struct u_sig_eht_tb_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_version : 3, - transmit_bw : 3, - dl_ul_flag : 1, - bss_color_id : 6, - txop_duration : 7, - disregard_0a : 6, - reserved_0c : 6; - uint32_t eht_ppdu_sig_cmn_type : 2, - validate_1a : 1, - spatial_reuse : 8, - disregard_1b : 5, - crc : 4, - tail : 6, - reserved_1c : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0c : 6, - disregard_0a : 6, - txop_duration : 7, - bss_color_id : 6, - dl_ul_flag : 1, - transmit_bw : 3, - phy_version : 3; - uint32_t rx_integrity_check_passed : 1, - reserved_1c : 5, - tail : 6, - crc : 4, - disregard_1b : 5, - spatial_reuse : 8, - validate_1a : 1, - eht_ppdu_sig_cmn_type : 2; -#endif -}; - -#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 - -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 - -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 - -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 - -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 - -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 - -#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 - -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 - -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 - -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 - -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 - -#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_CRC_LSB 16 -#define U_SIG_EHT_TB_INFO_CRC_MSB 19 -#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 - -#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 -#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 -#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 - -#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 - -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/fig/v1/unallocated_ru_160_info.h deleted file mode 100644 index ccd4a7bab9ad..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/unallocated_ru_160_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _UNALLOCATED_RU_160_INFO_H_ -#define _UNALLOCATED_RU_160_INFO_H_ - -#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 - -struct unallocated_ru_160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t subband80_0_cc0 : 8, - subband80_0_cc1 : 8, - subband80_1_cc0 : 8, - subband80_1_cc1 : 8; -#else - uint32_t subband80_1_cc1 : 8, - subband80_1_cc0 : 8, - subband80_0_cc1 : 8, - subband80_0_cc0 : 8; -#endif -}; - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/fig/v1/uniform_descriptor_header.h deleted file mode 100644 index 7a2de6ccd8df..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/uniform_descriptor_header.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ -#define _UNIFORM_DESCRIPTOR_HEADER_H_ - -#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 - -struct uniform_descriptor_header { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t owner : 4, - buffer_type : 4, - tx_mpdu_queue_number : 20, - reserved_0a : 4; -#else - uint32_t reserved_0a : 4, - tx_mpdu_queue_number : 20, - buffer_type : 4, - owner : 4; -#endif -}; - -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f - -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 - -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 - -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_a_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_a_info.h deleted file mode 100644 index acd20f43949e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_a_info.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_A_INFO_H_ -#define _VHT_SIG_A_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 - -struct vht_sig_a_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t bandwidth : 2, - vhta_reserved_0 : 1, - stbc : 1, - group_id : 6, - n_sts : 12, - txop_ps_not_allowed : 1, - vhta_reserved_0b : 1, - reserved_0 : 8; - uint32_t gi_setting : 2, - su_mu_coding : 1, - ldpc_extra_symbol : 1, - mcs : 4, - beamformed : 1, - vhta_reserved_1 : 1, - crc : 8, - tail : 6, - reserved_1 : 7, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0 : 8, - vhta_reserved_0b : 1, - txop_ps_not_allowed : 1, - n_sts : 12, - group_id : 6, - stbc : 1, - vhta_reserved_0 : 1, - bandwidth : 2; - uint32_t rx_integrity_check_passed : 1, - reserved_1 : 7, - tail : 6, - crc : 8, - vhta_reserved_1 : 1, - beamformed : 1, - mcs : 4, - ldpc_extra_symbol : 1, - su_mu_coding : 1, - gi_setting : 2; -#endif -}; - -#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0 -#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1 -#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004 - -#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_STBC_LSB 3 -#define VHT_SIG_A_INFO_STBC_MSB 3 -#define VHT_SIG_A_INFO_STBC_MASK 0x00000008 - -#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_GROUP_ID_LSB 4 -#define VHT_SIG_A_INFO_GROUP_ID_MSB 9 -#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0 - -#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_N_STS_LSB 10 -#define VHT_SIG_A_INFO_N_STS_MSB 21 -#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00 - -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000 - -#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_RESERVED_0_LSB 24 -#define VHT_SIG_A_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000 - -#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_GI_SETTING_LSB 0 -#define VHT_SIG_A_INFO_GI_SETTING_MSB 1 -#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003 - -#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2 -#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2 -#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004 - -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008 - -#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_MCS_LSB 4 -#define VHT_SIG_A_INFO_MCS_MSB 7 -#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0 - -#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8 -#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8 -#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200 - -#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_CRC_LSB 10 -#define VHT_SIG_A_INFO_CRC_MSB 17 -#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00 - -#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_TAIL_LSB 18 -#define VHT_SIG_A_INFO_TAIL_MSB 23 -#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000 - -#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_RESERVED_1_LSB 24 -#define VHT_SIG_A_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000 - -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu160_info.h deleted file mode 100644 index 13931c5c3556..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu160_info.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU160_INFO_H_ -#define _VHT_SIG_B_MU160_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 - -struct vht_sig_b_mu160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - mcs : 4, - tail : 6, - reserved_0 : 3; - uint32_t length_copy_a : 19, - mcs_copy_a : 4, - tail_copy_a : 6, - reserved_1 : 3; - uint32_t length_copy_b : 19, - mcs_copy_b : 4, - tail_copy_b : 6, - reserved_2 : 3; - uint32_t length_copy_c : 19, - mcs_copy_c : 4, - tail_copy_c : 6, - reserved_3 : 3; - uint32_t length_copy_d : 19, - mcs_copy_d : 4, - tail_copy_d : 6, - reserved_4 : 3; - uint32_t length_copy_e : 19, - mcs_copy_e : 4, - tail_copy_e : 6, - reserved_5 : 3; - uint32_t length_copy_f : 19, - mcs_copy_f : 4, - tail_copy_f : 6, - mu_user_number : 3; - uint32_t length_copy_g : 19, - mcs_copy_g : 4, - tail_copy_g : 6, - reserved_7 : 3; -#else - uint32_t reserved_0 : 3, - tail : 6, - mcs : 4, - length : 19; - uint32_t reserved_1 : 3, - tail_copy_a : 6, - mcs_copy_a : 4, - length_copy_a : 19; - uint32_t reserved_2 : 3, - tail_copy_b : 6, - mcs_copy_b : 4, - length_copy_b : 19; - uint32_t reserved_3 : 3, - tail_copy_c : 6, - mcs_copy_c : 4, - length_copy_c : 19; - uint32_t reserved_4 : 3, - tail_copy_d : 6, - mcs_copy_d : 4, - length_copy_d : 19; - uint32_t reserved_5 : 3, - tail_copy_e : 6, - mcs_copy_e : 4, - length_copy_e : 19; - uint32_t mu_user_number : 3, - tail_copy_f : 6, - mcs_copy_f : 4, - length_copy_f : 19; - uint32_t reserved_7 : 3, - tail_copy_g : 6, - mcs_copy_g : 4, - length_copy_g : 19; -#endif -}; - -#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu20_info.h deleted file mode 100644 index c51ac839a757..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu20_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU20_INFO_H_ -#define _VHT_SIG_B_MU20_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 - -struct vht_sig_b_mu20_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 16, - mcs : 4, - tail : 6, - mu_user_number : 3, - reserved_0 : 3; -#else - uint32_t reserved_0 : 3, - mu_user_number : 3, - tail : 6, - mcs : 4, - length : 16; -#endif -}; - -#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 -#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff - -#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 -#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 -#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 - -#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 -#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 -#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 - -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 - -#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu40_info.h deleted file mode 100644 index 0eb4c164cca1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu40_info.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU40_INFO_H_ -#define _VHT_SIG_B_MU40_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 - -struct vht_sig_b_mu40_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 17, - mcs : 4, - tail : 6, - reserved_0 : 2, - mu_user_number : 3; - uint32_t length_copy : 17, - mcs_copy : 4, - tail_copy : 6, - reserved_1 : 5; -#else - uint32_t mu_user_number : 3, - reserved_0 : 2, - tail : 6, - mcs : 4, - length : 17; - uint32_t reserved_1 : 5, - tail_copy : 6, - mcs_copy : 4, - length_copy : 17; -#endif -}; - -#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 -#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff - -#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 -#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 -#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 - -#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 -#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 -#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 - -#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 - -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff - -#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 - -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 - -#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu80_info.h deleted file mode 100644 index 33d0f1bc08fc..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu80_info.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU80_INFO_H_ -#define _VHT_SIG_B_MU80_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 - -struct vht_sig_b_mu80_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - mcs : 4, - tail : 6, - reserved_0 : 3; - uint32_t length_copy_a : 19, - mcs_copy_a : 4, - tail_copy_a : 6, - reserved_1 : 3; - uint32_t length_copy_b : 19, - mcs_copy_b : 4, - tail_copy_b : 6, - mu_user_number : 3; - uint32_t length_copy_c : 19, - mcs_copy_c : 4, - tail_copy_c : 6, - reserved_3 : 3; -#else - uint32_t reserved_0 : 3, - tail : 6, - mcs : 4, - length : 19; - uint32_t reserved_1 : 3, - tail_copy_a : 6, - mcs_copy_a : 4, - length_copy_a : 19; - uint32_t mu_user_number : 3, - tail_copy_b : 6, - mcs_copy_b : 4, - length_copy_b : 19; - uint32_t reserved_3 : 3, - tail_copy_c : 6, - mcs_copy_c : 4, - length_copy_c : 19; -#endif -}; - -#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su160_info.h deleted file mode 100644 index 7ba503724b56..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su160_info.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU160_INFO_H_ -#define _VHT_SIG_B_SU160_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 - -struct vht_sig_b_su160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 21, - vhtb_reserved : 2, - tail : 6, - reserved_0 : 2, - rx_ndp : 1; - uint32_t length_copy_a : 21, - vhtb_reserved_copy_a : 2, - tail_copy_a : 6, - reserved_1 : 2, - rx_ndp_copy_a : 1; - uint32_t length_copy_b : 21, - vhtb_reserved_copy_b : 2, - tail_copy_b : 6, - reserved_2 : 2, - rx_ndp_copy_b : 1; - uint32_t length_copy_c : 21, - vhtb_reserved_copy_c : 2, - tail_copy_c : 6, - reserved_3 : 2, - rx_ndp_copy_c : 1; - uint32_t length_copy_d : 21, - vhtb_reserved_copy_d : 2, - tail_copy_d : 6, - reserved_4 : 2, - rx_ndp_copy_d : 1; - uint32_t length_copy_e : 21, - vhtb_reserved_copy_e : 2, - tail_copy_e : 6, - reserved_5 : 2, - rx_ndp_copy_e : 1; - uint32_t length_copy_f : 21, - vhtb_reserved_copy_f : 2, - tail_copy_f : 6, - reserved_6 : 2, - rx_ndp_copy_f : 1; - uint32_t length_copy_g : 21, - vhtb_reserved_copy_g : 2, - tail_copy_g : 6, - reserved_7 : 2, - rx_ndp_copy_g : 1; -#else - uint32_t rx_ndp : 1, - reserved_0 : 2, - tail : 6, - vhtb_reserved : 2, - length : 21; - uint32_t rx_ndp_copy_a : 1, - reserved_1 : 2, - tail_copy_a : 6, - vhtb_reserved_copy_a : 2, - length_copy_a : 21; - uint32_t rx_ndp_copy_b : 1, - reserved_2 : 2, - tail_copy_b : 6, - vhtb_reserved_copy_b : 2, - length_copy_b : 21; - uint32_t rx_ndp_copy_c : 1, - reserved_3 : 2, - tail_copy_c : 6, - vhtb_reserved_copy_c : 2, - length_copy_c : 21; - uint32_t rx_ndp_copy_d : 1, - reserved_4 : 2, - tail_copy_d : 6, - vhtb_reserved_copy_d : 2, - length_copy_d : 21; - uint32_t rx_ndp_copy_e : 1, - reserved_5 : 2, - tail_copy_e : 6, - vhtb_reserved_copy_e : 2, - length_copy_e : 21; - uint32_t rx_ndp_copy_f : 1, - reserved_6 : 2, - tail_copy_f : 6, - vhtb_reserved_copy_f : 2, - length_copy_f : 21; - uint32_t rx_ndp_copy_g : 1, - reserved_7 : 2, - tail_copy_g : 6, - vhtb_reserved_copy_g : 2, - length_copy_g : 21; -#endif -}; - -#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su20_info.h deleted file mode 100644 index 2c7f11ba3c21..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su20_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU20_INFO_H_ -#define _VHT_SIG_B_SU20_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 - -struct vht_sig_b_su20_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 17, - vhtb_reserved : 3, - tail : 6, - reserved : 5, - rx_ndp : 1; -#else - uint32_t rx_ndp : 1, - reserved : 5, - tail : 6, - vhtb_reserved : 3, - length : 17; -#endif -}; - -#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 -#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff - -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 - -#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 -#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 -#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 - -#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 -#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 -#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 - -#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su40_info.h deleted file mode 100644 index 467259003e8d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su40_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU40_INFO_H_ -#define _VHT_SIG_B_SU40_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 - -struct vht_sig_b_su40_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - vhtb_reserved : 2, - tail : 6, - reserved : 4, - rx_ndp : 1; - uint32_t length_copy : 19, - vhtb_reserved_copy : 2, - tail_copy : 6, - reserved_copy : 4, - rx_ndp_copy : 1; -#else - uint32_t rx_ndp : 1, - reserved : 4, - tail : 6, - vhtb_reserved : 2, - length : 19; - uint32_t rx_ndp_copy : 1, - reserved_copy : 4, - tail_copy : 6, - vhtb_reserved_copy : 2, - length_copy : 19; -#endif -}; - -#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 - -#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 -#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 -#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 - -#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 -#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 -#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 - -#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff - -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 - -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 - -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 - -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su80_info.h deleted file mode 100644 index 92ceeab9b476..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su80_info.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU80_INFO_H_ -#define _VHT_SIG_B_SU80_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 - -struct vht_sig_b_su80_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 21, - vhtb_reserved : 2, - tail : 6, - reserved_0 : 2, - rx_ndp : 1; - uint32_t length_copy_a : 21, - vhtb_reserved_copy_a : 2, - tail_copy_a : 6, - reserved_1 : 2, - rx_ndp_copy_a : 1; - uint32_t length_copy_b : 21, - vhtb_reserved_copy_b : 2, - tail_copy_b : 6, - reserved_2 : 2, - rx_ndp_copy_b : 1; - uint32_t length_copy_c : 21, - vhtb_reserved_copy_c : 2, - tail_copy_c : 6, - reserved_3 : 2, - rx_ndp_copy_c : 1; -#else - uint32_t rx_ndp : 1, - reserved_0 : 2, - tail : 6, - vhtb_reserved : 2, - length : 21; - uint32_t rx_ndp_copy_a : 1, - reserved_1 : 2, - tail_copy_a : 6, - vhtb_reserved_copy_a : 2, - length_copy_a : 21; - uint32_t rx_ndp_copy_b : 1, - reserved_2 : 2, - tail_copy_b : 6, - vhtb_reserved_copy_b : 2, - length_copy_b : 21; - uint32_t rx_ndp_copy_c : 1, - reserved_3 : 2, - tail_copy_c : 6, - vhtb_reserved_copy_c : 2, - length_copy_c : 21; -#endif -}; - -#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wbm2sw_completion_ring_rx.h b/drivers/staging/fw-api/hw/fig/v1/wbm2sw_completion_ring_rx.h deleted file mode 100644 index e40a7e796a87..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wbm2sw_completion_ring_rx.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM2SW_COMPLETION_RING_RX_H_ -#define _WBM2SW_COMPLETION_RING_RX_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_mpdu_desc_info.h" -#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 - -struct wbm2sw_completion_ring_rx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t release_source_module : 3, - bm_action : 3, - buffer_or_desc_type : 3, - return_buffer_manager : 4, - reserved_2a : 2, - cache_id : 1, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_push_reason : 2, - reo_error_code : 5, - wbm_internal_error : 1; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t buffer_phys_addr_31_0 : 32; - uint32_t buffer_phys_addr_39_32 : 8, - sw_buffer_cookie : 20, - looping_count : 4; -#else - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t wbm_internal_error : 1, - reo_error_code : 5, - reo_push_reason : 2, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - cache_id : 1, - reserved_2a : 2, - return_buffer_manager : 4, - buffer_or_desc_type : 3, - bm_action : 3, - release_source_module : 3; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t buffer_phys_addr_31_0 : 32; - uint32_t looping_count : 4, - sw_buffer_cookie : 20, - buffer_phys_addr_39_32 : 8; -#endif -}; - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 - -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 - -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 - -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 - -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 - -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 - -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 - -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 - -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff - -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 - -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/fig/v1/wbm_buffer_ring.h deleted file mode 100644 index b1532e15595b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wbm_buffer_ring.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_BUFFER_RING_H_ -#define _WBM_BUFFER_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 - -struct wbm_buffer_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_addr_info; -#else - struct buffer_addr_info buf_addr_info; -#endif -}; - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/fig/v1/wbm_link_descriptor_ring.h deleted file mode 100644 index 851807aa4c1c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wbm_link_descriptor_ring.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ -#define _WBM_LINK_DESCRIPTOR_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 - -struct wbm_link_descriptor_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info desc_addr_info; -#else - struct buffer_addr_info desc_addr_info; -#endif -}; - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring.h b/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring.h deleted file mode 100644 index e86d52753912..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_H_ -#define _WBM_RELEASE_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 - -struct wbm_release_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - reserved_2a : 3, - buffer_or_desc_type : 3, - reserved_2b : 22, - wbm_internal_error : 1; - uint32_t reserved_3a : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_5a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 28, - looping_count : 4; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t wbm_internal_error : 1, - reserved_2b : 22, - buffer_or_desc_type : 3, - reserved_2a : 3, - release_source_module : 3; - uint32_t reserved_3a : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_5a : 32; - uint32_t reserved_6a : 32; - uint32_t looping_count : 4, - reserved_7a : 28; -#endif -}; - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RESERVED_2A_LSB 3 -#define WBM_RELEASE_RING_RESERVED_2A_MSB 5 -#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 - -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RESERVED_2B_LSB 9 -#define WBM_RELEASE_RING_RESERVED_2B_MSB 30 -#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 - -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 - -#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c -#define WBM_RELEASE_RING_RESERVED_3A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_3A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 -#define WBM_RELEASE_RING_RESERVED_4A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_4A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 -#define WBM_RELEASE_RING_RESERVED_5A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_5A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 -#define WBM_RELEASE_RING_RESERVED_6A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_6A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c -#define WBM_RELEASE_RING_RESERVED_7A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_7A_MSB 27 -#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff - -#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 -#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 -#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_rx.h b/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_rx.h deleted file mode 100644 index a68bc8115a82..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_rx.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_RX_H_ -#define _WBM_RELEASE_RING_RX_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 4 - -struct wbm_release_ring_rx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - buffer_or_desc_type : 3, - reserved_2a : 14, - mpdu_sequence_number : 12; - uint32_t reserved_3a : 32; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t mpdu_sequence_number : 12, - reserved_2a : 14, - buffer_or_desc_type : 3, - release_source_module : 3; - uint32_t reserved_3a : 32; -#endif -}; - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 3 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 5 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x00000038 - -#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 6 -#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 19 -#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x000fffc0 - -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_LSB 20 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MSB 31 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 - -#define WBM_RELEASE_RING_RX_RESERVED_3A_OFFSET 0x0000000c -#define WBM_RELEASE_RING_RX_RESERVED_3A_LSB 0 -#define WBM_RELEASE_RING_RX_RESERVED_3A_MSB 31 -#define WBM_RELEASE_RING_RX_RESERVED_3A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_tx.h b/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_tx.h deleted file mode 100644 index d1412153c6ae..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_tx.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_TX_H_ -#define _WBM_RELEASE_RING_TX_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 4 - -struct wbm_release_ring_tx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - buffer_or_desc_type : 3, - reserved_2a : 26; - uint32_t tqm_status_number : 32; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t reserved_2a : 26, - buffer_or_desc_type : 3, - release_source_module : 3; - uint32_t tqm_status_number : 32; -#endif -}; - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 3 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 5 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x00000038 - -#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 6 -#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 31 -#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0xffffffc0 - -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 31 -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwiobase.h deleted file mode 100644 index b96752690ea3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwiobase.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef WCSS_SEQ_HWIOBASE_H -#define WCSS_SEQ_HWIOBASE_H - -#define UMAC_NOC_BASE 0x140000 -#define UMAC_NOC_BASE_SIZE 0x00004480 -#define UMAC_NOC_BASE_PHYS 0x00140000 - -#define PHYA0_BASE 0x300000 -#define PHYA0_BASE_SIZE 0x00300000 -#define PHYA0_BASE_PHYS 0x00300000 - -#define PHYA1_BASE 0x600000 -#define PHYA1_BASE_SIZE 0x00300000 -#define PHYA1_BASE_PHYS 0x00600000 - -#define DMAC_BASE 0x900000 -#define DMAC_BASE_SIZE 0x00080000 -#define DMAC_BASE_PHYS 0x00900000 - -#define UMAC_BASE 0xa00000 -#define UMAC_BASE_SIZE 0x0004d000 -#define UMAC_BASE_PHYS 0x00a00000 - -#define PMAC0_BASE 0xa80000 -#define PMAC0_BASE_SIZE 0x00040000 -#define PMAC0_BASE_PHYS 0x00a80000 - -#define PMAC1_BASE 0xac0000 -#define PMAC1_BASE_SIZE 0x00040000 -#define PMAC1_BASE_PHYS 0x00ac0000 - -#define WFSS_AMCSS_BASE 0xb00000 -#define WFSS_AMCSS_BASE_SIZE 0x00040000 -#define WFSS_AMCSS_BASE_PHYS 0x00b00000 - -#define CXC_BASE 0xb40000 -#define CXC_BASE_SIZE 0x00010000 -#define CXC_BASE_PHYS 0x00b40000 - -#define WFSS_PMM_BASE 0xb50000 -#define WFSS_PMM_BASE_SIZE 0x00002401 -#define WFSS_PMM_BASE_PHYS 0x00b50000 - -#define WFSS_CC_BASE 0xb60000 -#define WFSS_CC_BASE_SIZE 0x00008000 -#define WFSS_CC_BASE_PHYS 0x00b60000 - -#define WCMN_CORE_BASE 0xb68000 -#define WCMN_CORE_BASE_SIZE 0x000008a9 -#define WCMN_CORE_BASE_PHYS 0x00b68000 - -#define WIFI_CFGBUS_APB_TSLV_BASE 0xb6b000 -#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000 -#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000 - -#define WFSS_CFGBUS_BASE 0xb6c000 -#define WFSS_CFGBUS_BASE_SIZE 0x000000a0 -#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000 - -#define WIFI_CFGBUS_AHB_TSLV_BASE 0xb6d000 -#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000 -#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000 - -#define UMAC_ACMT_BASE 0xb6e000 -#define UMAC_ACMT_BASE_SIZE 0x00001000 -#define UMAC_ACMT_BASE_PHYS 0x00b6e000 - -#define WCSS_CC_BASE 0xb80000 -#define WCSS_CC_BASE_SIZE 0x00010000 -#define WCSS_CC_BASE_PHYS 0x00b80000 - -#define PMM_TOP_BASE 0xb90000 -#define PMM_TOP_BASE_SIZE 0x00010000 -#define PMM_TOP_BASE_PHYS 0x00b90000 - -#define WCSS_TOP_CMN_BASE 0xba0000 -#define WCSS_TOP_CMN_BASE_SIZE 0x00004000 -#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000 - -#define WCSS_CFGBUS_BASE 0xba4000 -#define WCSS_CFGBUS_BASE_SIZE 0x00008000 -#define WCSS_CFGBUS_BASE_PHYS 0x00ba4000 - -#define MSIP_BASE 0xbb0000 -#define MSIP_BASE_SIZE 0x00010000 -#define MSIP_BASE_PHYS 0x00bb0000 - -#define RFA_BASE 0xbc0000 -#define RFA_BASE_SIZE 0x00040000 -#define RFA_BASE_PHYS 0x00bc0000 - -#define DBG_BASE 0x1000000 -#define DBG_BASE_SIZE 0x00100000 -#define DBG_BASE_PHYS 0x01000000 - -#define Q6SS_WLAN_BASE 0x1100000 -#define Q6SS_WLAN_BASE_SIZE 0x00100000 -#define Q6SS_WLAN_BASE_PHYS 0x01100000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_umac.h deleted file mode 100644 index 4fb391d29729..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_umac.h +++ /dev/null @@ -1,2475 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOREG_UMAC_H -#include "seq_hwio.h" -#include "wcss_seq_hwiobase.h" -#ifdef SCALE_INCLUDES -#include "HALhwio.h" -#else -#include "msmhwio.h" -#endif - -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x) ((x) + 0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x) ((x) + 0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS (0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK 0x7 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK 0x7 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x) ((x) + 0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x) ((x) + 0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS (0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR 0x00001ffe -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK 0x1ffe000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT 13 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK 0x1ffe -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT 1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK 0x1000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT 12 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK 0x800 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT 11 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK 0x400 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT 10 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK 0x200 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT 9 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x) ((x) + 0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x) ((x) + 0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS (0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK 0xff000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT 24 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK 0xff0000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT 16 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK 0xff00 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT 8 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK 0xff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n) ((base) + 0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n) ((base) + 0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n) (0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK 0xfff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn 31 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK 0xfff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT 0 - -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x) ((x) + 0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x) ((x) + 0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS (0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK 0x3 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x)) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK 0x2 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT 1 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT 0 - -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n) (0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn 63 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) - -#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x40) - -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x130) -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 - -#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x134) -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x138) - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x13c) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x140) - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x144) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x148) - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x14c) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x150) - -#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x24c) - -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0x51c) - -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0x52c) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS (0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK 0x3f -#define HWIO_WBM_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK 0x20 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT 5 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK 0x10 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT 4 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x) ((x) + 0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x) ((x) + 0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS (0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK 0xffffffff -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR 0x00000000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR 0x3 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x) \ - in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x)) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v) \ - out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x)) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK 0xffe00000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT 21 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK 0x1f0000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT 16 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK 0xf800 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT 11 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK 0x7c0 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT 6 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK 0x3e -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT 1 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK 0x1 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT 0 - -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x3ff -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000020 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK 0x200 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT 9 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK 0x100 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT 8 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn 255 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010) - -#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x3040) - -#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) - -#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x) ((x) + 0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x) ((x) + 0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS (0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR 0x76043210 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x) ((x) + 0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x) ((x) + 0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS (0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x6666ba98 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x) ((x) + 0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x) ((x) + 0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS (0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR 0x66666666 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x) ((x) + 0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x) ((x) + 0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS (0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR 0x66666666 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x38) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x3c) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x) ((x) + 0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x) ((x) + 0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS (0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR 0x00000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR 0x3 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x) ((x) + 0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x) ((x) + 0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS (0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR 0x00000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR 0x3 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT 0 - -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x) ((x) + 0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x) ((x) + 0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS (0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK 0x1ffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR 0x00000000 -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR 0x3 -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x) \ - in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v) \ - out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK 0x1ffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT 0 - -#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x6c) - -#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x70) -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 -#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 -#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff -#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 - -#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x344) - -#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x7d0) - -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x7d4) -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x7d8) - -#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) ((x) + 0x7dc) -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x7e0) -#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x7e4) - -#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x7e8) - -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7f4) - -#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x818) - -#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x81c) - -#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x820) - -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x824) - -#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x828) - -#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x82c) - -#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x830) - -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x844) -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x848) - -#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0xc08) - -#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_MISC_CFG_ADDR(x) ((x) + 0x1458) -#define HWIO_REO_R0_MISC_CFG_PHYS(x) ((x) + 0x1458) -#define HWIO_REO_R0_MISC_CFG_OFFS (0x1458) -#define HWIO_REO_R0_MISC_CFG_RMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_POR 0x00000000 -#define HWIO_REO_R0_MISC_CFG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MISC_CFG_ATTR 0x3 -#define HWIO_REO_R0_MISC_CFG_IN(x) \ - in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x)) -#define HWIO_REO_R0_MISC_CFG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m) -#define HWIO_REO_R0_MISC_CFG_OUT(x, v) \ - out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v) -#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x)) -#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT 0 - -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x) ((x) + 0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x) ((x) + 0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS (0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK 0x1ff -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR 0x0000002d -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR 0x3 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x) \ - in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v) \ - out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK 0x1fe -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT 1 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK 0x1 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT 0 - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0x1468) - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0x146c) - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0x1470) - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0x1474) - -#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0x14dc) -#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 -#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 -#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 -#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 - -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_REO_R0_CREDIT_ADDR(x) ((x) + 0x16d0) -#define HWIO_REO_R0_CREDIT_PHYS(x) ((x) + 0x16d0) -#define HWIO_REO_R0_CREDIT_OFFS (0x16d0) -#define HWIO_REO_R0_CREDIT_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_POR 0x00000000 -#define HWIO_REO_R0_CREDIT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_ATTR 0x3 -#define HWIO_REO_R0_CREDIT_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_ADDR(x)) -#define HWIO_REO_R0_CREDIT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_OUT(x, v) \ - out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v) -#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x)) -#define HWIO_REO_R0_CREDIT_VAL_BMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_VAL_SHFT 0 - -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x) ((x) + 0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x) ((x) + 0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS (0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK 0x7 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR 0x00000002 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR 0x3 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x)) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v) \ - out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x)) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK 0x7 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT 0 - -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x) ((x) + 0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x) ((x) + 0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS (0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR 0x00000000 -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR 0x1 -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x)) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT 0 - -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK 0x2000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT 13 - -#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_OFFS (0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_RMSK 0x7 -#define HWIO_REO_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_REO_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_REO_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x) ((x) + 0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x) ((x) + 0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS (0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK 0x3f -#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR 0x00000000 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR 0x1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x) \ - in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK 0x20 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT 5 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK 0x10 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT 4 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK 0x8 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT 3 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK 0x4 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT 2 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK 0x2 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT 1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK 0x1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT 0 - -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x) ((x) + 0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x) ((x) + 0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS (0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR 0x00000000 -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR 0x3 -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x) \ - in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v) \ - out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT 0 - -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn 255 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028) - -#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3070) - -#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x3074) - -#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3078) - -#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x30b8) - -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK 0x80 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT 7 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK 0x40 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT 6 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK 0x20 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT 5 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK 0x10 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT 4 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK 0x8 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT 3 - -#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK 0x80000000 -#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT 31 - -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK 0x8000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT 15 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK 0x4000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT 14 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK 0x2000 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT 13 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK 0x1000 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT 12 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK 0x800 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT 11 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK 0x400 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT 10 - -#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS (0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK 0xf -#define HWIO_TQM_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x) ((x) + 0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x) ((x) + 0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS (0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK 0x1ffff -#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR 0x00000000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR 0x3 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x) \ - in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x)) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v) \ - out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x)) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK 0x2 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT 1 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK 0x1 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT 0 - -#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK 0x20000000 -#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT 29 - -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x) ((x) + 0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x) ((x) + 0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS (0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT 0 - -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x) ((x) + 0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x) ((x) + 0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS (0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT 0 - -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x) ((x) + 0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x) ((x) + 0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS (0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT 0 - -#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x) ((x) + 0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x) ((x) + 0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS (0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK 0xfff -#define HWIO_TQM_R0_WATCHDOG_SRNG_POR 0x00000710 -#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR 0x3 -#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x) \ - in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)) -#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)) -#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK 0xfff -#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0 - -#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x) ((x) + 0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x) ((x) + 0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS (0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x) ((x) + 0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x) ((x) + 0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS (0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x) ((x) + 0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x) ((x) + 0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS (0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x) ((x) + 0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x) ((x) + 0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS (0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK 0xf -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR 0x00000000 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR 0x1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x)) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK 0x8 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT 3 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK 0x4 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT 2 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK 0x2 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT 1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK 0x1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT 0 - -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x) ((x) + 0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x) ((x) + 0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS (0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR 0x00000000 -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR 0x1 -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x) \ - in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x)) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT 0 - -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x) ((x) + 0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x) ((x) + 0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS (0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR 0x00000000 -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR 0x1 -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x) \ - in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x)) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT 0 - -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0xff -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn 127 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK 0x80 -#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT 7 - -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 28 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 27 - -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 - -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 - -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 - -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 - -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 28 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 27 - -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 - -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 - -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 - -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 - -#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK 0x40 -#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT 6 - -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x) ((x) + 0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x) ((x) + 0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS (0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK 0xf -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR 0x0000000a -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR 0x3 -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x) \ - in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK 0xf -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT 0 - -#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS (0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK 0x1f -#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK 0x10 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT 4 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK 0x8 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT 3 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK 0x4 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT 2 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK 0x2 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT 1 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_UMCMN_R0_LINK_ID_ADDR(x) ((x) + 0x170) -#define HWIO_UMCMN_R0_LINK_ID_PHYS(x) ((x) + 0x170) -#define HWIO_UMCMN_R0_LINK_ID_OFFS (0x170) -#define HWIO_UMCMN_R0_LINK_ID_RMSK 0xffff -#define HWIO_UMCMN_R0_LINK_ID_POR 0x000052c8 -#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_LINK_ID_ATTR 0x3 -#define HWIO_UMCMN_R0_LINK_ID_IN(x) \ - in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x)) -#define HWIO_UMCMN_R0_LINK_ID_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m) -#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v) -#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x)) -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK 0x80 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT 7 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK 0x40 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT 6 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK 0x38 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT 3 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK 0x7 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT 0 - -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK 0x4000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT 14 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK 0x2000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT 13 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK 0x1000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT 12 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK 0x800 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT 11 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK 0x400 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT 10 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK 0x200 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT 9 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK 0x100 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT 8 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK 0x80 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT 7 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK 0x40 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT 6 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK 0x20 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT 5 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK 0x10 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT 4 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK 0x8 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT 3 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK 0x4 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT 2 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK 0x2 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT 1 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK 0x1 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT 0 - -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x) ((x) + 0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x) ((x) + 0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS (0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK 0x1 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR 0x00000000 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR 0x3 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x) \ - in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x)) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x)) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK 0x1 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT 0 - -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x) ((x) + 0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x) ((x) + 0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS (0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK 0x1ffff -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR 0x00000000 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR 0x3 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x) \ - in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x)) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x)) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK 0x1fe00 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT 9 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK 0x1fe -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT 1 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK 0x1 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT 0 - -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x1ff -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK 0x100 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT 8 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK 0x80 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT 7 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK 0x40 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT 6 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK 0x20 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT 5 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n) ((base) + 0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n) ((base) + 0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n) (0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn 7 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR 0x00000000 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR 0x3 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n) \ - in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val) \ - out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n)) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT 0 - -#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) - -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 - -#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK 0x200000 -#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT 21 - -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X74 + (0x4*(n))) -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 - -#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X174 + (0x4*(n))) -#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff - -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK 0x800000 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT 23 - -#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK 0x40 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT 6 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK 0x20 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT 5 - -#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x) ((x) + 0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x) ((x) + 0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS (0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK 0x3 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR 0x00000000 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR 0x3 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x) \ - in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x)) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v) \ - out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x)) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK 0x2 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT 1 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK 0x1 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT 0 - -#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS (0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK 0x7 -#define HWIO_TCL_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x8c8) - -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x8cc) -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x8d0) -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x8d8) -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x8e4) - -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x8e8) - -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x8f8) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x8fc) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x910) - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x914) -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x918) - -#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x940) - -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x10000 -#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 16 - -#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x10000 -#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 16 - -#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS (0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK 0x1ff -#define HWIO_TCL_R1_TESTBUS_CTRL_POR 0x00000000 -#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR 0x3 -#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x) \ - in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)) -#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m) -#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v) -#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x)) -#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x100 -#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 8 -#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK 0xc0 -#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT 6 -#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK 0x3f -#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT 0 - -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn 511 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) - -#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) - -#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) - -#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x) ((x) + 0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_PHYS(x) ((x) + 0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OFFS (0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_RMSK 0x7ff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR 0x000003ff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR_RMSK 0xffffffff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ATTR 0x3 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x) \ - in_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x)) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x), m) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUT(x, v) \ - out_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),v) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),m,v,HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x)) - -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_BMSK 0x400 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_SHFT 10 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_BMSK 0x200 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_SHFT 9 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_BMSK 0x100 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_SHFT 8 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_BMSK 0x80 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_SHFT 7 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_BMSK 0x40 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_SHFT 6 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_BMSK 0x20 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_SHFT 5 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_BMSK 0x10 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_SHFT 4 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_BMSK 0x8 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_SHFT 3 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_BMSK 0x4 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_SHFT 2 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_BMSK 0x2 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_SHFT 1 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_BMSK 0x1 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_SHFT 0 - -#define TQM_REG_REG_BASE (UMAC_BASE + 0x0003c000) -#define TQM_REG_REG_BASE_SIZE 0x4000 - -#define HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_PHYS(x) ((x) + 0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OFFS (0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR 0x00000000 -#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PHYS(x) ((x) + 0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OFFS (0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_RMSK 0x7ffff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR 0x00011100 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_PHYS(x) ((x) + 0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OFFS (0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_RMSK 0x1ff -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR 0x000001fe -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_SHFT 7 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_SHFT 6 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_SHFT 5 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_SHFT 4 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_SHFT 3 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_SHFT 2 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_SHFT 1 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_SHFT 0 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x) ((x) + 0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PHYS(x) ((x) + 0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OFFS (0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RMSK 0x3fefff -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR 0x00080170 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ATTR 0x3 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x) \ - in_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x)) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x), m) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),v) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),m,v,HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x)) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_BMSK 0x200000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_SHFT 21 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_BMSK 0x100000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_SHFT 20 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x80000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT 19 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_BMSK 0x40000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_SHFT 18 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_BMSK 0x20000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_SHFT 17 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_BMSK 0x10000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_SHFT 16 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_BMSK 0x8000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_SHFT 15 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_BMSK 0x4000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_SHFT 14 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_BMSK 0x2000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_SHFT 13 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_BMSK 0x800 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_SHFT 11 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_BMSK 0x400 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_SHFT 10 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_BMSK 0x200 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_SHFT 9 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_BMSK 0x80 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_SHFT 7 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_BMSK 0x40 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_SHFT 6 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_BMSK 0x20 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_SHFT 5 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_BMSK 0x10 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_SHFT 4 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_BMSK 0x8 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_SHFT 3 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_BMSK 0x4 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_SHFT 2 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_SHFT 1 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OFFS (0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_PHYS(x) ((x) + 0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OFFS (0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OFFS (0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_PHYS(x) ((x) + 0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OFFS (0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_PHYS(x) ((x) + 0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OFFS (0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR 0x00060000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ATTR 0x3 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x), m) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),v) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_BMSK 0xf0000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_SHFT 28 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_BMSK 0xf000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_SHFT 24 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_BMSK 0xf00000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_SHFT 20 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_BMSK 0xf0000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_SHFT 16 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_BMSK 0xf000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_SHFT 12 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_BMSK 0xf00 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_SHFT 8 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_BMSK 0xf0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_SHFT 4 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_BMSK 0xf -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_SHFT 0 - -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_PHYS(x) ((x) + 0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OFFS (0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR 0x00060000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ATTR 0x3 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x), m) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),v) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_BMSK 0xf0000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_SHFT 28 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_BMSK 0xf000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_SHFT 24 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_BMSK 0xf00000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_SHFT 20 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_BMSK 0xf0000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_SHFT 16 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_BMSK 0xf000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_SHFT 12 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_BMSK 0xf00 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_SHFT 8 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_BMSK 0xf0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_SHFT 4 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_BMSK 0xf -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_SHFT 0 -#endif /* WCSS_SEQ_HWIOREG_UMAC_H */ diff --git a/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_wifi_top.h b/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_wifi_top.h deleted file mode 100644 index 072ec2ed4af7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_wifi_top.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOREG_WIFI_TOP_H -#define WCSS_SEQ_HWIOREG_WIFI_TOP_H - -#include "wcss_seq_hwiobase.h" - -#define WFSS_PMM_REG_BASE (WFSS_PMM_BASE + 0x00000000) - -#define HWIO_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_26_ADDR(x) ((x) + 0x164) - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wcss_version.h b/drivers/staging/fw-api/hw/fig/v1/wcss_version.h deleted file mode 100644 index 76c77489574d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wcss_version.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#define WCSS_VERSION 3150 diff --git a/drivers/staging/fw-api/hw/fig/v2/HALcomdef.h b/drivers/staging/fw-api/hw/fig/v2/HALcomdef.h deleted file mode 100644 index 60ee92e6cd2e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/HALcomdef.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef HAL_COMDEF_H -#define HAL_COMDEF_H - -#ifndef _ARM_ASM_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "com_dtypes.h" - -#ifndef _BOOL32_DEFINED -typedef unsigned long int bool32; -#define _BOOL32_DEFINED -#endif - -#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF - - #define inp(port) (*((volatile byte *) (port))) - #define inpw(port) (*((volatile word *) (port))) - #define inpdw(port) (*((volatile dword *)(port))) - - #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) - #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) - #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) - -#ifdef __cplusplus -} -#endif - -#endif - -#endif - diff --git a/drivers/staging/fw-api/hw/fig/v2/HALhwio.h b/drivers/staging/fw-api/hw/fig/v2/HALhwio.h deleted file mode 100644 index 94dd4185e173..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/HALhwio.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef HAL_HWIO_H -#define HAL_HWIO_H - -#include "HALcomdef.h" - -#define HWIO_BASE_PTR(base) base##_BASE_PTR - -#ifdef __ARMCC_VERSION - #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) -#else - #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) -#endif - -#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) -#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) -#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) -#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) - -#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) -#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) -#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) -#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) -#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) -#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) -#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) - -#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) -#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) -#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) -#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) -#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) -#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) -#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) - -#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) -#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) -#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) -#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) - -#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) -#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) -#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) -#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) - -#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) - -#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) -#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) -#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) -#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) -#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) -#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) -#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) - -#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) - -#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) -#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) -#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) -#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) - -#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) -#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) -#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) -#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) - -#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) - -#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) - -#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) -#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) -#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) -#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) - -#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) -#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) -#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) -#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) -#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) -#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) -#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) - -#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) -#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) -#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) - -#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) - -#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) - -#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) -#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) -#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) -#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) -#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) -#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) -#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) -#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) - -#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) -#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) - -#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN -#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) -#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) -#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) -#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) -#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) -#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) -#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) -#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) -#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) -#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) -#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) -#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) -#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) -#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) -#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) -#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR -#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) -#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) -#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) -#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS -#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) -#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) -#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) -#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS -#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) -#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) -#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) -#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK -#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) -#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK -#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT -#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT -#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow -#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) -#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL - -#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) -#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) -#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) -#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) -#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) -#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) -#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) -#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) -#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) -#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) -#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) -#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) -#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) -#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ - HWIO_##hwiosym##_OUTM(base, mask1, val1); \ - HWIO_##hwiosym##_OUTM(base, mask2, val2); \ - } -#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ - HWIO_##hwiosym##_OUTM(base, mask1, val1); \ - HWIO_##hwiosym##_OUTM(base, mask2, val2); \ - HWIO_##hwiosym##_OUTM(base, mask3, val3); \ - } -#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ - HWIO_##hwiosym##_OUTM(base, mask1, val1); \ - HWIO_##hwiosym##_OUTM(base, mask2, val2); \ - HWIO_##hwiosym##_OUTM(base, mask3, val3); \ - HWIO_##hwiosym##_OUTM(base, mask4, val4); \ - } - -#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) -#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) -#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) -#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) -#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) -#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) -#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) -#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) -#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) -#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) -#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) - -#define HWIO_INTLOCK() -#define HWIO_INTFREE() - -#define __inp(port) (*((volatile uint8 *) (port))) -#define __inpw(port) (*((volatile uint16 *) (port))) -#define __inpdw(port) (*((volatile uint32 *) (port))) -#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) -#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) -#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) - -#ifdef HAL_HWIO_EXTERNAL - -#undef __inp -#undef __inpw -#undef __inpdw -#undef __outp -#undef __outpw -#undef __outpdw - -#define __inp(port) __inp_extern(port) -#define __inpw(port) __inpw_extern(port) -#define __inpdw(port) __inpdw_extern(port) -#define __outp(port, val) __outp_extern(port, val) -#define __outpw(port, val) __outpw_extern(port, val) -#define __outpdw(port, val) __outpdw_extern(port, val) - -extern uint8 __inp_extern ( uint32 nAddr ); -extern uint16 __inpw_extern ( uint32 nAddr ); -extern uint32 __inpdw_extern ( uint32 nAddr ); -extern void __outp_extern ( uint32 nAddr, uint8 nData ); -extern void __outpw_extern ( uint32 nAddr, uint16 nData ); -extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); - -#endif - -#define in_byte(addr) (__inp(addr)) -#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) -#define out_byte(addr, val) __outp(addr,val) -#define out_byte_masked(io, mask, val, shadow) \ - HWIO_INTLOCK(); \ - out_byte( io, shadow); \ - shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ - HWIO_INTFREE() -#define out_byte_masked_ns(io, mask, val, current_reg_content) \ - out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ - ((uint16)((val) & (mask)))) ) - -#define in_word(addr) (__inpw(addr)) -#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) -#define out_word(addr, val) __outpw(addr,val) -#define out_word_masked(io, mask, val, shadow) \ - HWIO_INTLOCK( ); \ - shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ - out_word( io, shadow); \ - HWIO_INTFREE( ) -#define out_word_masked_ns(io, mask, val, current_reg_content) \ - out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ - ((uint16)((val) & (mask)))) ) - -#define in_dword(addr) (__inpdw(addr)) -#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) -#define out_dword(addr, val) __outpdw(addr,val) -#define out_dword_masked(io, mask, val, shadow) \ - HWIO_INTLOCK(); \ - shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ - out_dword( io, shadow); \ - HWIO_INTFREE() -#define out_dword_masked_ns(io, mask, val, current_reg_content) \ - out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ - ((uint32)((val) & (mask)))) ) - -#endif - diff --git a/drivers/staging/fw-api/hw/fig/v2/ack_report.h b/drivers/staging/fw-api/hw/fig/v2/ack_report.h deleted file mode 100644 index e78921b308fd..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/ack_report.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _ACK_REPORT_H_ -#define _ACK_REPORT_H_ - -#define NUM_OF_DWORDS_ACK_REPORT 1 - -struct ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t selfgen_response_reason : 4, - ax_trigger_type : 4, - sr_ppdu : 1, - reserved : 7, - frame_control : 16; -#else - uint32_t frame_control : 16, - reserved : 7, - sr_ppdu : 1, - ax_trigger_type : 4, - selfgen_response_reason : 4; -#endif -}; - -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f - -#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 -#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 -#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 -#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 - -#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 -#define ACK_REPORT_SR_PPDU_LSB 8 -#define ACK_REPORT_SR_PPDU_MSB 8 -#define ACK_REPORT_SR_PPDU_MASK 0x00000100 - -#define ACK_REPORT_RESERVED_OFFSET 0x00000000 -#define ACK_REPORT_RESERVED_LSB 9 -#define ACK_REPORT_RESERVED_MSB 15 -#define ACK_REPORT_RESERVED_MASK 0x0000fe00 - -#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 -#define ACK_REPORT_FRAME_CONTROL_LSB 16 -#define ACK_REPORT_FRAME_CONTROL_MSB 31 -#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/boron_top_reg.h b/drivers/staging/fw-api/hw/fig/v2/boron_top_reg.h deleted file mode 100644 index 306398284fe3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/boron_top_reg.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef BORON_TOP_REG_H -#define BORON_TOP_REG_H - -#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C) -#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050) - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/buffer_addr_info.h b/drivers/staging/fw-api/hw/fig/v2/buffer_addr_info.h deleted file mode 100644 index d65375b54715..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/buffer_addr_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _BUFFER_ADDR_INFO_H_ -#define _BUFFER_ADDR_INFO_H_ - -#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 - -struct buffer_addr_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_addr_31_0 : 32; - uint32_t buffer_addr_39_32 : 8, - return_buffer_manager : 4, - sw_buffer_cookie : 20; -#else - uint32_t buffer_addr_31_0 : 32; - uint32_t sw_buffer_cookie : 20, - return_buffer_manager : 4, - buffer_addr_39_32 : 8; -#endif -}; - -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/ce_src_desc.h b/drivers/staging/fw-api/hw/fig/v2/ce_src_desc.h deleted file mode 100644 index 4ecaedcab2a7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/ce_src_desc.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _CE_SRC_DESC_H_ -#define _CE_SRC_DESC_H_ - -#define NUM_OF_DWORDS_CE_SRC_DESC 4 - -struct ce_src_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t src_buffer_low : 32; - uint32_t src_buffer_high : 8, - toeplitz_en : 1, - src_swap : 1, - dest_swap : 1, - gather : 1, - ce_res_0 : 1, - barrier_read : 1, - ce_res_1 : 2, - length : 16; - uint32_t fw_metadata : 16, - ce_res_2 : 16; - uint32_t ce_res_3 : 20, - ring_id : 8, - looping_count : 4; -#else - uint32_t src_buffer_low : 32; - uint32_t length : 16, - ce_res_1 : 2, - barrier_read : 1, - ce_res_0 : 1, - gather : 1, - dest_swap : 1, - src_swap : 1, - toeplitz_en : 1, - src_buffer_high : 8; - uint32_t ce_res_2 : 16, - fw_metadata : 16; - uint32_t looping_count : 4, - ring_id : 8, - ce_res_3 : 20; -#endif -}; - -#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000 -#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0 -#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31 -#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff - -#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff - -#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004 -#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8 -#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8 -#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100 - -#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004 -#define CE_SRC_DESC_SRC_SWAP_LSB 9 -#define CE_SRC_DESC_SRC_SWAP_MSB 9 -#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200 - -#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004 -#define CE_SRC_DESC_DEST_SWAP_LSB 10 -#define CE_SRC_DESC_DEST_SWAP_MSB 10 -#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400 - -#define CE_SRC_DESC_GATHER_OFFSET 0x00000004 -#define CE_SRC_DESC_GATHER_LSB 11 -#define CE_SRC_DESC_GATHER_MSB 11 -#define CE_SRC_DESC_GATHER_MASK 0x00000800 - -#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004 -#define CE_SRC_DESC_CE_RES_0_LSB 12 -#define CE_SRC_DESC_CE_RES_0_MSB 12 -#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000 - -#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004 -#define CE_SRC_DESC_BARRIER_READ_LSB 13 -#define CE_SRC_DESC_BARRIER_READ_MSB 13 -#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000 - -#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004 -#define CE_SRC_DESC_CE_RES_1_LSB 14 -#define CE_SRC_DESC_CE_RES_1_MSB 15 -#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000 - -#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004 -#define CE_SRC_DESC_LENGTH_LSB 16 -#define CE_SRC_DESC_LENGTH_MSB 31 -#define CE_SRC_DESC_LENGTH_MASK 0xffff0000 - -#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008 -#define CE_SRC_DESC_FW_METADATA_LSB 0 -#define CE_SRC_DESC_FW_METADATA_MSB 15 -#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff - -#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008 -#define CE_SRC_DESC_CE_RES_2_LSB 16 -#define CE_SRC_DESC_CE_RES_2_MSB 31 -#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000 - -#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c -#define CE_SRC_DESC_CE_RES_3_LSB 0 -#define CE_SRC_DESC_CE_RES_3_MSB 19 -#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff - -#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c -#define CE_SRC_DESC_RING_ID_LSB 20 -#define CE_SRC_DESC_RING_ID_MSB 27 -#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000 - -#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c -#define CE_SRC_DESC_LOOPING_COUNT_LSB 28 -#define CE_SRC_DESC_LOOPING_COUNT_MSB 31 -#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/ce_stat_desc.h b/drivers/staging/fw-api/hw/fig/v2/ce_stat_desc.h deleted file mode 100644 index 0b9f9a221215..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/ce_stat_desc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _CE_STAT_DESC_H_ -#define _CE_STAT_DESC_H_ - -#define NUM_OF_DWORDS_CE_STAT_DESC 4 - -struct ce_stat_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ce_res_5 : 8, - toeplitz_en : 1, - src_swap : 1, - dest_swap : 1, - gather : 1, - barrier_read : 1, - ce_res_6 : 3, - length : 16; - uint32_t toeplitz_hash_0 : 32; - uint32_t toeplitz_hash_1 : 32; - uint32_t fw_metadata : 16, - ce_res_7 : 4, - ring_id : 8, - looping_count : 4; -#else - uint32_t length : 16, - ce_res_6 : 3, - barrier_read : 1, - gather : 1, - dest_swap : 1, - src_swap : 1, - toeplitz_en : 1, - ce_res_5 : 8; - uint32_t toeplitz_hash_0 : 32; - uint32_t toeplitz_hash_1 : 32; - uint32_t looping_count : 4, - ring_id : 8, - ce_res_7 : 4, - fw_metadata : 16; -#endif -}; - -#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000 -#define CE_STAT_DESC_CE_RES_5_LSB 0 -#define CE_STAT_DESC_CE_RES_5_MSB 7 -#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff - -#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000 -#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8 -#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8 -#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100 - -#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000 -#define CE_STAT_DESC_SRC_SWAP_LSB 9 -#define CE_STAT_DESC_SRC_SWAP_MSB 9 -#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200 - -#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000 -#define CE_STAT_DESC_DEST_SWAP_LSB 10 -#define CE_STAT_DESC_DEST_SWAP_MSB 10 -#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400 - -#define CE_STAT_DESC_GATHER_OFFSET 0x00000000 -#define CE_STAT_DESC_GATHER_LSB 11 -#define CE_STAT_DESC_GATHER_MSB 11 -#define CE_STAT_DESC_GATHER_MASK 0x00000800 - -#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000 -#define CE_STAT_DESC_BARRIER_READ_LSB 12 -#define CE_STAT_DESC_BARRIER_READ_MSB 12 -#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000 - -#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000 -#define CE_STAT_DESC_CE_RES_6_LSB 13 -#define CE_STAT_DESC_CE_RES_6_MSB 15 -#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000 - -#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000 -#define CE_STAT_DESC_LENGTH_LSB 16 -#define CE_STAT_DESC_LENGTH_MSB 31 -#define CE_STAT_DESC_LENGTH_MASK 0xffff0000 - -#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff - -#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff - -#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c -#define CE_STAT_DESC_FW_METADATA_LSB 0 -#define CE_STAT_DESC_FW_METADATA_MSB 15 -#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff - -#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c -#define CE_STAT_DESC_CE_RES_7_LSB 16 -#define CE_STAT_DESC_CE_RES_7_MSB 19 -#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000 - -#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c -#define CE_STAT_DESC_RING_ID_LSB 20 -#define CE_STAT_DESC_RING_ID_MSB 27 -#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000 - -#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c -#define CE_STAT_DESC_LOOPING_COUNT_LSB 28 -#define CE_STAT_DESC_LOOPING_COUNT_MSB 31 -#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/coex_rx_status.h b/drivers/staging/fw-api/hw/fig/v2/coex_rx_status.h deleted file mode 100644 index 7d9c6b4d2057..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/coex_rx_status.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_RX_STATUS_H_ -#define _COEX_RX_STATUS_H_ - -#define NUM_OF_DWORDS_COEX_RX_STATUS 2 - -#define NUM_OF_QWORDS_COEX_RX_STATUS 1 - -struct coex_rx_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_mac_frame_status : 2, - rx_with_tx_response : 1, - rx_rate : 5, - rx_bw : 3, - single_mpdu : 1, - filter_status : 1, - ampdu : 1, - directed : 1, - reserved_0 : 1, - rx_nss : 3, - rx_rssi : 8, - rx_type : 3, - retry_bit_setting : 1, - more_data_bit_setting : 1; - uint32_t remain_rx_packet_time : 16, - rx_remaining_fes_time : 16; -#else - uint32_t more_data_bit_setting : 1, - retry_bit_setting : 1, - rx_type : 3, - rx_rssi : 8, - rx_nss : 3, - reserved_0 : 1, - directed : 1, - ampdu : 1, - filter_status : 1, - single_mpdu : 1, - rx_bw : 3, - rx_rate : 5, - rx_with_tx_response : 1, - rx_mac_frame_status : 2; - uint32_t rx_remaining_fes_time : 16, - remain_rx_packet_time : 16; -#endif -}; - -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 - -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 - -#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_RATE_LSB 3 -#define COEX_RX_STATUS_RX_RATE_MSB 7 -#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 - -#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_BW_LSB 8 -#define COEX_RX_STATUS_RX_BW_MSB 10 -#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 - -#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 -#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 -#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 - -#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 -#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 -#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 - -#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_AMPDU_LSB 13 -#define COEX_RX_STATUS_AMPDU_MSB 13 -#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 - -#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_DIRECTED_LSB 14 -#define COEX_RX_STATUS_DIRECTED_MSB 14 -#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 - -#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RESERVED_0_LSB 15 -#define COEX_RX_STATUS_RESERVED_0_MSB 15 -#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 - -#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_NSS_LSB 16 -#define COEX_RX_STATUS_RX_NSS_MSB 18 -#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 - -#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_RSSI_LSB 19 -#define COEX_RX_STATUS_RX_RSSI_MSB 26 -#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 - -#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_TYPE_LSB 27 -#define COEX_RX_STATUS_RX_TYPE_MSB 29 -#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 - -#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 - -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 - -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 - -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/coex_tx_req.h b/drivers/staging/fw-api/hw/fig/v2/coex_tx_req.h deleted file mode 100644 index ed5b4c57bfd8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/coex_tx_req.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_TX_REQ_H_ -#define _COEX_TX_REQ_H_ - -#define NUM_OF_DWORDS_COEX_TX_REQ 6 - -#define NUM_OF_QWORDS_COEX_TX_REQ 3 - -struct coex_tx_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_pwr : 8, - min_tx_pwr : 8, - nss : 3, - tx_chain_mask : 8, - bw : 3, - reserved_0 : 2; - uint32_t alt_tx_pwr : 8, - alt_min_tx_pwr : 8, - alt_nss : 3, - alt_tx_chain_mask : 8, - alt_bw : 3, - reserved_1 : 2; - uint32_t tx_pwr_1 : 8, - alt_tx_pwr_1 : 8, - wlan_request_duration : 16; - uint32_t wlan_pkt_type : 4, - coex_tx_reason : 2, - response_frame_type : 5, - wlan_low_priority_slicing_allowed : 1, - wlan_high_priority_slicing_allowed : 1, - sch_tx_burst_ongoing : 1, - coex_tx_priority : 4, - blackout_details_en : 1, - blackout_peek_duration : 8, - reserved_3a : 5; - uint32_t frequency_channel_bonding_mask : 16, - num_blackout_windows : 8, - reserved_4a : 8; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0 : 2, - bw : 3, - tx_chain_mask : 8, - nss : 3, - min_tx_pwr : 8, - tx_pwr : 8; - uint32_t reserved_1 : 2, - alt_bw : 3, - alt_tx_chain_mask : 8, - alt_nss : 3, - alt_min_tx_pwr : 8, - alt_tx_pwr : 8; - uint32_t wlan_request_duration : 16, - alt_tx_pwr_1 : 8, - tx_pwr_1 : 8; - uint32_t reserved_3a : 5, - blackout_peek_duration : 8, - blackout_details_en : 1, - coex_tx_priority : 4, - sch_tx_burst_ongoing : 1, - wlan_high_priority_slicing_allowed : 1, - wlan_low_priority_slicing_allowed : 1, - response_frame_type : 5, - coex_tx_reason : 2, - wlan_pkt_type : 4; - uint32_t reserved_4a : 8, - num_blackout_windows : 8, - frequency_channel_bonding_mask : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_TX_PWR_LSB 0 -#define COEX_TX_REQ_TX_PWR_MSB 7 -#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff - -#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 -#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 -#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_NSS_LSB 16 -#define COEX_TX_REQ_NSS_MSB 18 -#define COEX_TX_REQ_NSS_MASK 0x0000000000070000 - -#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 -#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 -#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_BW_LSB 27 -#define COEX_TX_REQ_BW_MSB 29 -#define COEX_TX_REQ_BW_MASK 0x0000000038000000 - -#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_RESERVED_0_LSB 30 -#define COEX_TX_REQ_RESERVED_0_MSB 31 -#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000 - -#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_TX_PWR_LSB 32 -#define COEX_TX_REQ_ALT_TX_PWR_MSB 39 -#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_NSS_LSB 48 -#define COEX_TX_REQ_ALT_NSS_MSB 50 -#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000 - -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_BW_LSB 59 -#define COEX_TX_REQ_ALT_BW_MSB 61 -#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000 - -#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_RESERVED_1_LSB 62 -#define COEX_TX_REQ_RESERVED_1_MSB 63 -#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000 - -#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_TX_PWR_1_LSB 0 -#define COEX_TX_REQ_TX_PWR_1_MSB 7 -#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff - -#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 -#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 -#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00 - -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000 - -#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32 -#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35 -#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000 - -#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_COEX_TX_REASON_LSB 36 -#define COEX_TX_REQ_COEX_TX_REASON_MSB 37 -#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000 - -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000 - -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000 - -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000 - -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000 - -#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46 -#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49 -#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000 - -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_LSB 50 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MSB 50 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MASK 0x0004000000000000 - -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_LSB 51 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MSB 58 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MASK 0x07f8000000000000 - -#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_RESERVED_3A_LSB 59 -#define COEX_TX_REQ_RESERVED_3A_MSB 63 -#define COEX_TX_REQ_RESERVED_3A_MASK 0xf800000000000000 - -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_LSB 0 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MSB 15 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MASK 0x000000000000ffff - -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_LSB 16 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MSB 23 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MASK 0x0000000000ff0000 - -#define COEX_TX_REQ_RESERVED_4A_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_RESERVED_4A_LSB 24 -#define COEX_TX_REQ_RESERVED_4A_MSB 31 -#define COEX_TX_REQ_RESERVED_4A_MASK 0x00000000ff000000 - -#define COEX_TX_REQ_TLV64_PADDING_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_TLV64_PADDING_LSB 32 -#define COEX_TX_REQ_TLV64_PADDING_MSB 63 -#define COEX_TX_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/coex_tx_status.h b/drivers/staging/fw-api/hw/fig/v2/coex_tx_status.h deleted file mode 100644 index c47c29c2a5ba..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/coex_tx_status.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_TX_STATUS_H_ -#define _COEX_TX_STATUS_H_ - -#define NUM_OF_DWORDS_COEX_TX_STATUS 4 - -#define NUM_OF_QWORDS_COEX_TX_STATUS 2 - -struct coex_tx_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 7, - tx_bw : 3, - tx_status_reason : 3, - tx_wait_ack : 1, - fes_tx_is_gen_frame : 1, - sch_tx_burst_ongoing : 1, - current_tx_duration : 16; - uint32_t next_rx_active_time : 16, - remaining_fes_time : 16; - uint32_t tx_antenna_mask : 8, - shared_ant_tx_pwr : 8, - other_ant_tx_pwr : 8, - reserved_2 : 8; - uint32_t tlv64_padding : 32; -#else - uint32_t current_tx_duration : 16, - sch_tx_burst_ongoing : 1, - fes_tx_is_gen_frame : 1, - tx_wait_ack : 1, - tx_status_reason : 3, - tx_bw : 3, - reserved_0a : 7; - uint32_t remaining_fes_time : 16, - next_rx_active_time : 16; - uint32_t reserved_2 : 8, - other_ant_tx_pwr : 8, - shared_ant_tx_pwr : 8, - tx_antenna_mask : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_RESERVED_0A_LSB 0 -#define COEX_TX_STATUS_RESERVED_0A_MSB 6 -#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f - -#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_BW_LSB 7 -#define COEX_TX_STATUS_TX_BW_MSB 9 -#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 - -#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 -#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 -#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 - -#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 -#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 -#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 - -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 - -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 - -#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 - -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 - -#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 -#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 -#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 - -#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff - -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 - -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 - -#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_RESERVED_2_LSB 24 -#define COEX_TX_STATUS_RESERVED_2_MSB 31 -#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 - -#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_TLV64_PADDING_LSB 32 -#define COEX_TX_STATUS_TLV64_PADDING_MSB 63 -#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/com_dtypes.h b/drivers/staging/fw-api/hw/fig/v2/com_dtypes.h deleted file mode 100644 index aa7bf7a51845..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/com_dtypes.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef COM_DTYPES_H -#define COM_DTYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef T_WINNT - #ifndef WIN32 - #define WIN32 - #endif - #include -#endif - -#ifdef TRUE -#undef TRUE -#endif - -#ifdef FALSE -#undef FALSE -#endif - -#define TRUE 1 -#define FALSE 0 - -#define ON 1 -#define OFF 0 - -#ifndef NULL - #define NULL 0 -#endif - -#ifndef _ARM_ASM_ -#ifndef _BOOLEAN_DEFINED - -typedef unsigned char boolean; -#define _BOOLEAN_DEFINED -#endif - -#if defined(DALSTDDEF_H) -#define _BOOLEAN_DEFINED -#define _UINT32_DEFINED -#define _UINT16_DEFINED -#define _UINT8_DEFINED -#define _INT32_DEFINED -#define _INT16_DEFINED -#define _INT8_DEFINED -#define _UINT64_DEFINED -#define _INT64_DEFINED -#define _BYTE_DEFINED -#endif - -#ifndef _UINT32_DEFINED - -typedef unsigned int uint32; -#define _UINT32_DEFINED -#endif - -#ifndef _UINT16_DEFINED - -typedef unsigned short uint16; -#define _UINT16_DEFINED -#endif - -#ifndef _UINT8_DEFINED - -typedef unsigned char uint8; -#define _UINT8_DEFINED -#endif - -#ifndef _INT32_DEFINED - -typedef signed int int32; -#define _INT32_DEFINED -#endif - -#ifndef _INT16_DEFINED - -typedef signed short int16; -#define _INT16_DEFINED -#endif - -#ifndef _INT8_DEFINED - -typedef signed char int8; -#define _INT8_DEFINED -#endif - -#ifndef _BYTE_DEFINED - -typedef unsigned char byte; -#define _BYTE_DEFINED -#endif - -typedef unsigned short word; - -typedef unsigned long dword; - -typedef unsigned char uint1; - -typedef unsigned short uint2; - -typedef unsigned long uint4; - -typedef signed char int1; - -typedef signed short int2; - -typedef long int int4; - -typedef signed long sint31; - -typedef signed short sint15; - -typedef signed char sint7; - -typedef uint16 UWord16 ; -typedef uint32 UWord32 ; -typedef int32 Word32 ; -typedef int16 Word16 ; -typedef uint8 UWord8 ; -typedef int8 Word8 ; -typedef int32 Vect32 ; - -#if (! defined T_WINNT) && (! defined __GNUC__) - - #ifndef _INT64_DEFINED - - typedef long long int64; - #define _INT64_DEFINED - #endif - #ifndef _UINT64_DEFINED - - typedef unsigned long long uint64; - #define _UINT64_DEFINED - #endif -#else - - #if (defined __GNUC__) - #ifndef _INT64_DEFINED - typedef long long int64; - #define _INT64_DEFINED - #endif - #ifndef _UINT64_DEFINED - typedef unsigned long long uint64; - #define _UINT64_DEFINED - #endif - #else - typedef __int64 int64; - #ifndef _UINT64_DEFINED - typedef unsigned __int64 uint64; - #define _UINT64_DEFINED - #endif - #endif -#endif - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_mu_mimo_info.h deleted file mode 100644 index c9e20d75e648..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_mu_mimo_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ -#define _EHT_SIG_USR_MU_MIMO_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 - -struct eht_sig_usr_mu_mimo_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - sta_coding : 1, - sta_spatial_config : 6, - reserved_0a : 1, - rx_integrity_check_passed : 1, - subband80_cc_mask : 8; - uint32_t user_order_subband80_0 : 8, - user_order_subband80_1 : 8, - user_order_subband80_2 : 8, - user_order_subband80_3 : 8; -#else - uint32_t subband80_cc_mask : 8, - rx_integrity_check_passed : 1, - reserved_0a : 1, - sta_spatial_config : 6, - sta_coding : 1, - sta_mcs : 4, - sta_id : 11; - uint32_t user_order_subband80_3 : 8, - user_order_subband80_2 : 8, - user_order_subband80_1 : 8, - user_order_subband80_0 : 8; -#endif -}; - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 - -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 - -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 - -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_ofdma_info.h deleted file mode 100644 index f2520cccfde9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_ofdma_info.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ -#define _EHT_SIG_USR_OFDMA_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 - -struct eht_sig_usr_ofdma_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - validate_0a : 1, - nss : 4, - txbf : 1, - sta_coding : 1, - reserved_0b : 1, - rx_integrity_check_passed : 1, - subband80_cc_mask : 8; - uint32_t user_order_subband80_0 : 8, - user_order_subband80_1 : 8, - user_order_subband80_2 : 8, - user_order_subband80_3 : 8; -#else - uint32_t subband80_cc_mask : 8, - rx_integrity_check_passed : 1, - reserved_0b : 1, - sta_coding : 1, - txbf : 1, - nss : 4, - validate_0a : 1, - sta_mcs : 4, - sta_id : 11; - uint32_t user_order_subband80_3 : 8, - user_order_subband80_2 : 8, - user_order_subband80_1 : 8, - user_order_subband80_0 : 8; -#endif -}; - -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 - -#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 -#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 -#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 - -#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 - -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 - -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 - -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 - -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_su_info.h deleted file mode 100644 index 208cb4de0539..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_su_info.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_SU_INFO_H_ -#define _EHT_SIG_USR_SU_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 - -struct eht_sig_usr_su_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - validate_0a : 1, - nss : 4, - txbf : 1, - sta_coding : 1, - reserved_0b : 9, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0b : 9, - sta_coding : 1, - txbf : 1, - nss : 4, - validate_0a : 1, - sta_mcs : 4, - sta_id : 11; -#endif -}; - -#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 - -#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 -#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 -#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 - -#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 -#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 -#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 - -#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 -#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 -#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 - -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 - -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/expected_response.h b/drivers/staging/fw-api/hw/fig/v2/expected_response.h deleted file mode 100644 index b3ec83ceccf8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/expected_response.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EXPECTED_RESPONSE_H_ -#define _EXPECTED_RESPONSE_H_ - -#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 - -#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 - -struct expected_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_ad2_31_0 : 32; - uint32_t tx_ad2_47_32 : 16, - expected_response_type : 5, - response_to_response : 3, - su_ba_user_number : 1, - response_info_part2_required : 1, - transmitted_bssid_check_en : 1, - eht___reserved_g_0022_ndp_expected : 1, - reserved_1 : 4; - uint32_t ndp_sta_partial_aid_2_8_0 : 11, - reserved_2 : 10, - ndp_sta_partial_aid1_8_0 : 11; - uint32_t ast_index : 16, - capture_ack_ba_sounding : 1, - capture_sounding_1str_20mhz : 1, - capture_sounding_1str_40mhz : 1, - capture_sounding_1str_80mhz : 1, - capture_sounding_1str_160mhz : 1, - capture_sounding_1str_240mhz : 1, - capture_sounding_1str_320mhz : 1, - reserved_3a : 9; - uint32_t fcs : 9, - expect_rx_with_blackout_details : 1, - crc : 4, - scrambler_seed : 7, - reserved_4b : 11; - uint32_t tlv64_padding : 32; -#else - uint32_t tx_ad2_31_0 : 32; - uint32_t reserved_1 : 4, - eht___reserved_g_0022_ndp_expected : 1, - transmitted_bssid_check_en : 1, - response_info_part2_required : 1, - su_ba_user_number : 1, - response_to_response : 3, - expected_response_type : 5, - tx_ad2_47_32 : 16; - uint32_t ndp_sta_partial_aid1_8_0 : 11, - reserved_2 : 10, - ndp_sta_partial_aid_2_8_0 : 11; - uint32_t reserved_3a : 9, - capture_sounding_1str_320mhz : 1, - capture_sounding_1str_240mhz : 1, - capture_sounding_1str_160mhz : 1, - capture_sounding_1str_80mhz : 1, - capture_sounding_1str_40mhz : 1, - capture_sounding_1str_20mhz : 1, - capture_ack_ba_sounding : 1, - ast_index : 16; - uint32_t reserved_4b : 11, - scrambler_seed : 7, - crc : 4, - expect_rx_with_blackout_details : 1, - fcs : 9; - uint32_t tlv64_padding : 32; -#endif -}; - -#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 -#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 -#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff - -#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 -#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 -#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 - -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 - -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 - -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 - -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 - -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 - -#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESERVED_1_LSB 60 -#define EXPECTED_RESPONSE_RESERVED_1_MSB 63 -#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf000000000000000 - -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff - -#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 -#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 -#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 - -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 - -#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_AST_INDEX_LSB 32 -#define EXPECTED_RESPONSE_AST_INDEX_MSB 47 -#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 - -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 - -#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 -#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 -#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 - -#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_FCS_LSB 0 -#define EXPECTED_RESPONSE_FCS_MSB 8 -#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff - -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB 9 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB 9 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK 0x0000000000000200 - -#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_CRC_LSB 10 -#define EXPECTED_RESPONSE_CRC_MSB 13 -#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 - -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 - -#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 -#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 -#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 - -#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 -#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 -#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_dl_info.h deleted file mode 100644 index 84571eb65d3b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_dl_info.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_MU_DL_INFO_H_ -#define _HE_SIG_A_MU_DL_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 - -struct he_sig_a_mu_dl_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dl_ul_flag : 1, - mcs_of_sig_b : 3, - dcm_of_sig_b : 1, - bss_color_id : 6, - spatial_reuse : 4, - transmit_bw : 3, - num_sig_b_symbols : 4, - comp_mode_sig_b : 1, - cp_ltf_size : 2, - doppler_indication : 1, - reserved_0a : 6; - uint32_t txop_duration : 7, - reserved_1a : 1, - num_ltf_symbols : 3, - ldpc_extra_symbol : 1, - stbc : 1, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - crc : 4, - tail : 6, - reserved_1b : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0a : 6, - doppler_indication : 1, - cp_ltf_size : 2, - comp_mode_sig_b : 1, - num_sig_b_symbols : 4, - transmit_bw : 3, - spatial_reuse : 4, - bss_color_id : 6, - dcm_of_sig_b : 1, - mcs_of_sig_b : 3, - dl_ul_flag : 1; - uint32_t rx_integrity_check_passed : 1, - reserved_1b : 5, - tail : 6, - crc : 4, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - stbc : 1, - ldpc_extra_symbol : 1, - num_ltf_symbols : 3, - reserved_1a : 1, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 - -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e - -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 - -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 - -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 - -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 - -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 - -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 - -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 - -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 - -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 - -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 - -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 - -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 - -#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 -#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 -#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 - -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 - -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 - -#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 -#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 -#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 -#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 -#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 - -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_ul_info.h deleted file mode 100644 index e2d0ad73a66c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_ul_info.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_MU_UL_INFO_H_ -#define _HE_SIG_A_MU_UL_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 - -struct he_sig_a_mu_ul_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t format_indication : 1, - bss_color_id : 6, - spatial_reuse : 16, - reserved_0a : 1, - transmit_bw : 2, - reserved_0b : 6; - uint32_t txop_duration : 7, - reserved_1a : 9, - crc : 4, - tail : 6, - reserved_1b : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0b : 6, - transmit_bw : 2, - reserved_0a : 1, - spatial_reuse : 16, - bss_color_id : 6, - format_indication : 1; - uint32_t rx_integrity_check_passed : 1, - reserved_1b : 5, - tail : 6, - crc : 4, - reserved_1a : 9, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 - -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e - -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 - -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 - -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 - -#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 -#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 -#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 -#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 -#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 - -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_a_su_info.h deleted file mode 100644 index e4be3671016e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/he_sig_a_su_info.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_SU_INFO_H_ -#define _HE_SIG_A_SU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 - -struct he_sig_a_su_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t format_indication : 1, - beam_change : 1, - dl_ul_flag : 1, - transmit_mcs : 4, - dcm : 1, - bss_color_id : 6, - reserved_0a : 1, - spatial_reuse : 4, - transmit_bw : 2, - cp_ltf_size : 2, - nsts : 3, - reserved_0b : 6; - uint32_t txop_duration : 7, - coding : 1, - ldpc_extra_symbol : 1, - stbc : 1, - txbf : 1, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - reserved_1a : 1, - doppler_indication : 1, - crc : 4, - tail : 6, - dot11ax_su_extended : 1, - dot11ax_ext_ru_size : 3, - rx_ndp : 1, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0b : 6, - nsts : 3, - cp_ltf_size : 2, - transmit_bw : 2, - spatial_reuse : 4, - reserved_0a : 1, - bss_color_id : 6, - dcm : 1, - transmit_mcs : 4, - dl_ul_flag : 1, - beam_change : 1, - format_indication : 1; - uint32_t rx_integrity_check_passed : 1, - rx_ndp : 1, - dot11ax_ext_ru_size : 3, - dot11ax_su_extended : 1, - tail : 6, - crc : 4, - doppler_indication : 1, - reserved_1a : 1, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - txbf : 1, - stbc : 1, - ldpc_extra_symbol : 1, - coding : 1, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001 - -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002 - -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004 - -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078 - -#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_DCM_LSB 7 -#define HE_SIG_A_SU_INFO_DCM_MSB 7 -#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080 - -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00 - -#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000 - -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000 - -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000 - -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000 - -#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_NSTS_LSB 23 -#define HE_SIG_A_SU_INFO_NSTS_MSB 25 -#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000 - -#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26 -#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31 -#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000 - -#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_CODING_LSB 7 -#define HE_SIG_A_SU_INFO_CODING_MSB 7 -#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080 - -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100 - -#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_STBC_LSB 9 -#define HE_SIG_A_SU_INFO_STBC_MSB 9 -#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200 - -#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TXBF_LSB 10 -#define HE_SIG_A_SU_INFO_TXBF_MSB 10 -#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400 - -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 - -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 - -#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000 - -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000 - -#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_CRC_LSB 16 -#define HE_SIG_A_SU_INFO_CRC_MSB 19 -#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TAIL_LSB 20 -#define HE_SIG_A_SU_INFO_TAIL_MSB 25 -#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 - -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 - -#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30 -#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30 -#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000 - -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_b1_mu_info.h deleted file mode 100644 index a248c3dc67b3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/he_sig_b1_mu_info.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B1_MU_INFO_H_ -#define _HE_SIG_B1_MU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 - -struct he_sig_b1_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_allocation : 8, - reserved_0 : 23, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0 : 23, - ru_allocation : 8; -#endif -}; - -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff - -#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 -#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 -#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 - -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_mu_info.h deleted file mode 100644 index 83d6f3bc843f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_mu_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B2_MU_INFO_H_ -#define _HE_SIG_B2_MU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2 - -struct he_sig_b2_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_spatial_config : 4, - sta_mcs : 4, - reserved_set_to_1 : 1, - sta_coding : 1, - reserved_0a : 7, - nsts : 3, - rx_integrity_check_passed : 1; - uint32_t user_order : 8, - cc_mask : 8, - reserved_1a : 16; -#else - uint32_t rx_integrity_check_passed : 1, - nsts : 3, - reserved_0a : 7, - sta_coding : 1, - reserved_set_to_1 : 1, - sta_mcs : 4, - sta_spatial_config : 4, - sta_id : 11; - uint32_t reserved_1a : 16, - cc_mask : 8, - user_order : 8; -#endif -}; - -#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0 -#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10 -#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff - -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800 - -#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15 -#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18 -#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000 - -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000 - -#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20 -#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20 -#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000 - -#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000 - -#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_NSTS_LSB 28 -#define HE_SIG_B2_MU_INFO_NSTS_MSB 30 -#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000 - -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0 -#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7 -#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff - -#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8 -#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15 -#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00 - -#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_ofdma_info.h deleted file mode 100644 index 6357d216eb3a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_ofdma_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B2_OFDMA_INFO_H_ -#define _HE_SIG_B2_OFDMA_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 - -struct he_sig_b2_ofdma_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - nsts : 3, - txbf : 1, - sta_mcs : 4, - sta_dcm : 1, - sta_coding : 1, - reserved_0 : 10, - rx_integrity_check_passed : 1; - uint32_t user_order : 8, - cc_mask : 8, - reserved_1a : 16; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0 : 10, - sta_coding : 1, - sta_dcm : 1, - sta_mcs : 4, - txbf : 1, - nsts : 3, - sta_id : 11; - uint32_t reserved_1a : 16, - cc_mask : 8, - user_order : 8; -#endif -}; - -#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff - -#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 -#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 -#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 - -#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 -#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 -#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 - -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 - -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 - -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 - -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 - -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff - -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 - -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/ht_sig_info.h b/drivers/staging/fw-api/hw/fig/v2/ht_sig_info.h deleted file mode 100644 index d6a4a719e6e2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/ht_sig_info.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HT_SIG_INFO_H_ -#define _HT_SIG_INFO_H_ - -#define NUM_OF_DWORDS_HT_SIG_INFO 2 - -struct ht_sig_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mcs : 7, - cbw : 1, - length : 16, - reserved_0 : 8; - uint32_t smoothing : 1, - not_sounding : 1, - ht_reserved : 1, - aggregation : 1, - stbc : 2, - fec_coding : 1, - short_gi : 1, - num_ext_sp_str : 2, - crc : 8, - signal_tail : 6, - reserved_1 : 7, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0 : 8, - length : 16, - cbw : 1, - mcs : 7; - uint32_t rx_integrity_check_passed : 1, - reserved_1 : 7, - signal_tail : 6, - crc : 8, - num_ext_sp_str : 2, - short_gi : 1, - fec_coding : 1, - stbc : 2, - aggregation : 1, - ht_reserved : 1, - not_sounding : 1, - smoothing : 1; -#endif -}; - -#define HT_SIG_INFO_MCS_OFFSET 0x00000000 -#define HT_SIG_INFO_MCS_LSB 0 -#define HT_SIG_INFO_MCS_MSB 6 -#define HT_SIG_INFO_MCS_MASK 0x0000007f - -#define HT_SIG_INFO_CBW_OFFSET 0x00000000 -#define HT_SIG_INFO_CBW_LSB 7 -#define HT_SIG_INFO_CBW_MSB 7 -#define HT_SIG_INFO_CBW_MASK 0x00000080 - -#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000 -#define HT_SIG_INFO_LENGTH_LSB 8 -#define HT_SIG_INFO_LENGTH_MSB 23 -#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00 - -#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000 -#define HT_SIG_INFO_RESERVED_0_LSB 24 -#define HT_SIG_INFO_RESERVED_0_MSB 31 -#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000 - -#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004 -#define HT_SIG_INFO_SMOOTHING_LSB 0 -#define HT_SIG_INFO_SMOOTHING_MSB 0 -#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001 - -#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004 -#define HT_SIG_INFO_NOT_SOUNDING_LSB 1 -#define HT_SIG_INFO_NOT_SOUNDING_MSB 1 -#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002 - -#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004 -#define HT_SIG_INFO_HT_RESERVED_LSB 2 -#define HT_SIG_INFO_HT_RESERVED_MSB 2 -#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004 - -#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004 -#define HT_SIG_INFO_AGGREGATION_LSB 3 -#define HT_SIG_INFO_AGGREGATION_MSB 3 -#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008 - -#define HT_SIG_INFO_STBC_OFFSET 0x00000004 -#define HT_SIG_INFO_STBC_LSB 4 -#define HT_SIG_INFO_STBC_MSB 5 -#define HT_SIG_INFO_STBC_MASK 0x00000030 - -#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004 -#define HT_SIG_INFO_FEC_CODING_LSB 6 -#define HT_SIG_INFO_FEC_CODING_MSB 6 -#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040 - -#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004 -#define HT_SIG_INFO_SHORT_GI_LSB 7 -#define HT_SIG_INFO_SHORT_GI_MSB 7 -#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080 - -#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004 -#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8 -#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9 -#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300 - -#define HT_SIG_INFO_CRC_OFFSET 0x00000004 -#define HT_SIG_INFO_CRC_LSB 10 -#define HT_SIG_INFO_CRC_MSB 17 -#define HT_SIG_INFO_CRC_MASK 0x0003fc00 - -#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004 -#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18 -#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23 -#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000 - -#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004 -#define HT_SIG_INFO_RESERVED_1_LSB 24 -#define HT_SIG_INFO_RESERVED_1_MSB 30 -#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000 - -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/l_sig_a_info.h b/drivers/staging/fw-api/hw/fig/v2/l_sig_a_info.h deleted file mode 100644 index 6da0725dfee7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/l_sig_a_info.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _L_SIG_A_INFO_H_ -#define _L_SIG_A_INFO_H_ - -#define NUM_OF_DWORDS_L_SIG_A_INFO 1 - -struct l_sig_a_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rate : 4, - lsig_reserved : 1, - length : 12, - parity : 1, - tail : 6, - pkt_type : 4, - captured_implicit_sounding : 1, - reserved : 2, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved : 2, - captured_implicit_sounding : 1, - pkt_type : 4, - tail : 6, - parity : 1, - length : 12, - lsig_reserved : 1, - rate : 4; -#endif -}; - -#define L_SIG_A_INFO_RATE_OFFSET 0x00000000 -#define L_SIG_A_INFO_RATE_LSB 0 -#define L_SIG_A_INFO_RATE_MSB 3 -#define L_SIG_A_INFO_RATE_MASK 0x0000000f - -#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000 -#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4 -#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4 -#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010 - -#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000 -#define L_SIG_A_INFO_LENGTH_LSB 5 -#define L_SIG_A_INFO_LENGTH_MSB 16 -#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0 - -#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000 -#define L_SIG_A_INFO_PARITY_LSB 17 -#define L_SIG_A_INFO_PARITY_MSB 17 -#define L_SIG_A_INFO_PARITY_MASK 0x00020000 - -#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000 -#define L_SIG_A_INFO_TAIL_LSB 18 -#define L_SIG_A_INFO_TAIL_MSB 23 -#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000 - -#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000 -#define L_SIG_A_INFO_PKT_TYPE_LSB 24 -#define L_SIG_A_INFO_PKT_TYPE_MSB 27 -#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000 - -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 - -#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000 -#define L_SIG_A_INFO_RESERVED_LSB 29 -#define L_SIG_A_INFO_RESERVED_MSB 30 -#define L_SIG_A_INFO_RESERVED_MASK 0x60000000 - -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/l_sig_b_info.h b/drivers/staging/fw-api/hw/fig/v2/l_sig_b_info.h deleted file mode 100644 index f2052702e2de..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/l_sig_b_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _L_SIG_B_INFO_H_ -#define _L_SIG_B_INFO_H_ - -#define NUM_OF_DWORDS_L_SIG_B_INFO 1 - -struct l_sig_b_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rate : 4, - length : 12, - reserved : 15, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved : 15, - length : 12, - rate : 4; -#endif -}; - -#define L_SIG_B_INFO_RATE_OFFSET 0x00000000 -#define L_SIG_B_INFO_RATE_LSB 0 -#define L_SIG_B_INFO_RATE_MSB 3 -#define L_SIG_B_INFO_RATE_MASK 0x0000000f - -#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000 -#define L_SIG_B_INFO_LENGTH_LSB 4 -#define L_SIG_B_INFO_LENGTH_MSB 15 -#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0 - -#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000 -#define L_SIG_B_INFO_RESERVED_LSB 16 -#define L_SIG_B_INFO_RESERVED_MSB 30 -#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000 - -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v2/macrx_abort_request_info.h deleted file mode 100644 index 038f4038fa59..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/macrx_abort_request_info.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACRX_ABORT_REQUEST_INFO_H_ -#define _MACRX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 - -struct macrx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t macrx_abort_reason : 8, - reserved_0 : 8; -#else - uint16_t reserved_0 : 8, - macrx_abort_reason : 8; -#endif -}; - -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff - -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h deleted file mode 100644 index f29ca356a223..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ -#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ - -#include "eht_sig_usr_mu_mimo_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 - -struct mactx_eht_sig_usr_mu_mimo { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; -#else - struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; -#endif -}; - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_ofdma.h deleted file mode 100644 index 24bf6691978d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_ofdma.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ -#define _MACTX_EHT_SIG_USR_OFDMA_H_ - -#include "eht_sig_usr_ofdma_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1 - -struct mactx_eht_sig_usr_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; -#else - struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; -#endif -}; - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_su.h deleted file mode 100644 index 1fb82723c1ff..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_su.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_SU_H_ -#define _MACTX_EHT_SIG_USR_SU_H_ - -#include "eht_sig_usr_su_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1 - -struct mactx_eht_sig_usr_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; - uint32_t tlv64_padding : 32; -#else - struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_dl.h deleted file mode 100644 index 438f3af6f9e7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_dl.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_MU_DL_H_ -#define _MACTX_HE_SIG_A_MU_DL_H_ - -#include "he_sig_a_mu_dl_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1 - -struct mactx_he_sig_a_mu_dl { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; -#else - struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_ul.h deleted file mode 100644 index 96d2b912665a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_ul.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_MU_UL_H_ -#define _MACTX_HE_SIG_A_MU_UL_H_ - -#include "he_sig_a_mu_ul_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1 - -struct mactx_he_sig_a_mu_ul { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; -#else - struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_su.h deleted file mode 100644 index e51241d26559..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_su.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_SU_H_ -#define _MACTX_HE_SIG_A_SU_H_ - -#include "he_sig_a_su_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1 - -struct mactx_he_sig_a_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_su_info mactx_he_sig_a_su_info_details; -#else - struct he_sig_a_su_info mactx_he_sig_a_su_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b1_mu.h deleted file mode 100644 index 700528af2048..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b1_mu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B1_MU_H_ -#define _MACTX_HE_SIG_B1_MU_H_ - -#include "he_sig_b1_mu_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 - -struct mactx_he_sig_b1_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#else - struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_mu.h deleted file mode 100644 index ccc1c593fed6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_mu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B2_MU_H_ -#define _MACTX_HE_SIG_B2_MU_H_ - -#include "he_sig_b2_mu_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1 - -struct mactx_he_sig_b2_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; -#else - struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; -#endif -}; - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_ofdma.h deleted file mode 100644 index afc3c4b22841..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_ofdma.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ -#define _MACTX_HE_SIG_B2_OFDMA_H_ - -#include "he_sig_b2_ofdma_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1 - -struct mactx_he_sig_b2_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; -#else - struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; -#endif -}; - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_ht_sig.h b/drivers/staging/fw-api/hw/fig/v2/mactx_ht_sig.h deleted file mode 100644 index ec28824c590f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_ht_sig.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HT_SIG_H_ -#define _MACTX_HT_SIG_H_ - -#include "ht_sig_info.h" -#define NUM_OF_DWORDS_MACTX_HT_SIG 2 - -#define NUM_OF_QWORDS_MACTX_HT_SIG 1 - -struct mactx_ht_sig { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ht_sig_info mactx_ht_sig_info_details; -#else - struct ht_sig_info mactx_ht_sig_info_details; -#endif -}; - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_a.h deleted file mode 100644 index 061e46e28a2c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_a.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_L_SIG_A_H_ -#define _MACTX_L_SIG_A_H_ - -#include "l_sig_a_info.h" -#define NUM_OF_DWORDS_MACTX_L_SIG_A 2 - -#define NUM_OF_QWORDS_MACTX_L_SIG_A 1 - -struct mactx_l_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_a_info mactx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_a_info mactx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32 -#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63 -#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_b.h deleted file mode 100644 index 6d533acef675..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_b.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_L_SIG_B_H_ -#define _MACTX_L_SIG_B_H_ - -#include "l_sig_b_info.h" -#define NUM_OF_DWORDS_MACTX_L_SIG_B 2 - -#define NUM_OF_QWORDS_MACTX_L_SIG_B 1 - -struct mactx_l_sig_b { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_b_info mactx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_b_info mactx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32 -#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63 -#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_phy_desc.h b/drivers/staging/fw-api/hw/fig/v2/mactx_phy_desc.h deleted file mode 100644 index ee4ccdf65c28..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_phy_desc.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_PHY_DESC_H_ -#define _MACTX_PHY_DESC_H_ - -#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 - -#define NUM_OF_QWORDS_MACTX_PHY_DESC 2 - -struct mactx_phy_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 16, - bf_type : 2, - wait_sifs : 2, - dot11b_preamble_type : 1, - pkt_type : 4, - su_or_mu : 2, - mu_type : 1, - bandwidth : 3, - channel_capture : 1; - uint32_t mcs : 5, - global_ofdma_mimo_enable : 1, - stbc : 1, - dot11ax_su_extended : 1, - dot11ax_trigger_frame_embedded : 1, - tx_pwr_shared : 8, - tx_pwr_unshared : 8, - measure_power : 1, - tpc_glut_self_cal : 1, - back_to_back_transmission_expected : 1, - heavy_clip_nss : 3, - txbf_per_packet_no_csd_no_walsh : 1; - uint32_t ndp : 3, - ul_flag : 1, - triggered : 1, - ap_pkt_bw : 3, - ru_position_start : 8, - pcu_ppdu_setup_start_reason : 3, - tlv_source : 1, - reserved_2a : 1, - nss : 3, - stream_offset : 3, - reserved_2b : 2, - clpc_enable : 1, - mu_ndp : 1, - response_expected : 1; - uint32_t rx_chain_mask : 8, - rx_chain_mask_valid : 1, - ant_sel_valid : 1, - ant_sel : 1, - cp_setting : 2, - he_ppdu_subtype : 2, - active_channel : 3, - generate_phyrx_tx_start_timing : 1, - ltf_size : 2, - ru_size_updated_v2 : 4, - reserved_3c : 1, - u_sig_puncture_pattern_encoding : 6; -#else - uint32_t channel_capture : 1, - bandwidth : 3, - mu_type : 1, - su_or_mu : 2, - pkt_type : 4, - dot11b_preamble_type : 1, - wait_sifs : 2, - bf_type : 2, - reserved_0a : 16; - uint32_t txbf_per_packet_no_csd_no_walsh : 1, - heavy_clip_nss : 3, - back_to_back_transmission_expected : 1, - tpc_glut_self_cal : 1, - measure_power : 1, - tx_pwr_unshared : 8, - tx_pwr_shared : 8, - dot11ax_trigger_frame_embedded : 1, - dot11ax_su_extended : 1, - stbc : 1, - global_ofdma_mimo_enable : 1, - mcs : 5; - uint32_t response_expected : 1, - mu_ndp : 1, - clpc_enable : 1, - reserved_2b : 2, - stream_offset : 3, - nss : 3, - reserved_2a : 1, - tlv_source : 1, - pcu_ppdu_setup_start_reason : 3, - ru_position_start : 8, - ap_pkt_bw : 3, - triggered : 1, - ul_flag : 1, - ndp : 3; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_3c : 1, - ru_size_updated_v2 : 4, - ltf_size : 2, - generate_phyrx_tx_start_timing : 1, - active_channel : 3, - he_ppdu_subtype : 2, - cp_setting : 2, - ant_sel : 1, - ant_sel_valid : 1, - rx_chain_mask_valid : 1, - rx_chain_mask : 8; -#endif -}; - -#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 -#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 -#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff - -#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BF_TYPE_LSB 16 -#define MACTX_PHY_DESC_BF_TYPE_MSB 17 -#define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 - -#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 -#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 -#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 - -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 - -#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 -#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 -#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 - -#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 -#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 -#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 - -#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MU_TYPE_LSB 27 -#define MACTX_PHY_DESC_MU_TYPE_MSB 27 -#define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 - -#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 -#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 -#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 - -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 - -#define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MCS_LSB 32 -#define MACTX_PHY_DESC_MCS_MSB 36 -#define MACTX_PHY_DESC_MCS_MASK 0x0000001f00000000 - -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 37 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 37 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000002000000000 - -#define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_STBC_LSB 38 -#define MACTX_PHY_DESC_STBC_MSB 38 -#define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 - -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 - -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 - -#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 -#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 -#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 - -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 - -#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 -#define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 -#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 - -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 - -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 - -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 - -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 - -#define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_NDP_LSB 0 -#define MACTX_PHY_DESC_NDP_MSB 2 -#define MACTX_PHY_DESC_NDP_MASK 0x0000000000000007 - -#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_UL_FLAG_LSB 3 -#define MACTX_PHY_DESC_UL_FLAG_MSB 3 -#define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000008 - -#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_TRIGGERED_LSB 4 -#define MACTX_PHY_DESC_TRIGGERED_MSB 4 -#define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000010 - -#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_AP_PKT_BW_LSB 5 -#define MACTX_PHY_DESC_AP_PKT_BW_MSB 7 -#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000000000000e0 - -#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RU_POSITION_START_LSB 8 -#define MACTX_PHY_DESC_RU_POSITION_START_MSB 15 -#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x000000000000ff00 - -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 16 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 18 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000070000 - -#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_TLV_SOURCE_LSB 19 -#define MACTX_PHY_DESC_TLV_SOURCE_MSB 19 -#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000080000 - -#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_2A_LSB 20 -#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 -#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000100000 - -#define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_NSS_LSB 21 -#define MACTX_PHY_DESC_NSS_MSB 23 -#define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 - -#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 -#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 -#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 - -#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 -#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 -#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 - -#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 -#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 -#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 - -#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_MU_NDP_LSB 30 -#define MACTX_PHY_DESC_MU_NDP_MSB 30 -#define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 - -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 - -#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 - -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 - -#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 -#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 -#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 - -#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ANT_SEL_LSB 42 -#define MACTX_PHY_DESC_ANT_SEL_MSB 42 -#define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 - -#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_CP_SETTING_LSB 43 -#define MACTX_PHY_DESC_CP_SETTING_MSB 44 -#define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 - -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 - -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 - -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 - -#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_LTF_SIZE_LSB 51 -#define MACTX_PHY_DESC_LTF_SIZE_MSB 52 -#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 - -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 - -#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_3C_LSB 57 -#define MACTX_PHY_DESC_RESERVED_3C_MSB 57 -#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 - -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_su_mu.h deleted file mode 100644 index f46583e4c7ee..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_su_mu.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ -#define _MACTX_U_SIG_EHT_SU_MU_H_ - -#include "u_sig_eht_su_mu_info.h" -#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 - -#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1 - -struct mactx_u_sig_eht_su_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; -#else - struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; -#endif -}; - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_tb.h deleted file mode 100644 index 5e57312a9da2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_tb.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_U_SIG_EHT_TB_H_ -#define _MACTX_U_SIG_EHT_TB_H_ - -#include "u_sig_eht_tb_info.h" -#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 - -#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1 - -struct mactx_u_sig_eht_tb { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; -#else - struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; -#endif -}; - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_common.h deleted file mode 100644 index 04124271bbc9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_common.h +++ /dev/null @@ -1,482 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_USER_DESC_COMMON_H_ -#define _MACTX_USER_DESC_COMMON_H_ - -#include "unallocated_ru_160_info.h" -#include "ru_allocation_160_info.h" -#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 - -#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 - -struct mactx_user_desc_common { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t num_users : 6, - reserved_0b : 5, - ltf_size : 2, - reserved_0c : 3, - he_stf_long : 1, - reserved_0d : 7, - num_users_he_sigb_band0 : 8; - uint32_t num_ltf_symbols : 3, - reserved_1a : 5, - num_users_he_sigb_band1 : 8, - reserved_1b : 16; - uint32_t packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - packet_extension : 3, - reserved : 2, - he_sigb_dcm : 1, - reserved_2b : 7, - he_sigb_compression : 1, - reserved_2c : 15; - uint32_t he_sigb_0_mcs : 3, - reserved_3a : 13, - num_he_sigb_sym : 5, - center_ru_0 : 1, - center_ru_1 : 1, - reserved_3b : 1, - ftm_en : 1, - pe_nss : 3, - pe_ltf_size : 2, - pe_content : 1, - pe_chain_csd_en : 1; - struct ru_allocation_160_info ru_allocation_0123_details; - struct ru_allocation_160_info ru_allocation_4567_details; - struct unallocated_ru_160_info ru_allocation_160_0_details; - struct unallocated_ru_160_info ru_allocation_160_1_details; - uint32_t num_data_symbols : 16, - ndp_ru_tone_set_index : 7, - ndp_feedback_status : 1, - doppler_indication : 1, - reserved_14a : 7; - uint32_t spatial_reuse : 16, - distributed_ru : 1, - dru_spreading_bw : 2, - reserved_15a : 13; -#else - uint32_t num_users_he_sigb_band0 : 8, - reserved_0d : 7, - he_stf_long : 1, - reserved_0c : 3, - ltf_size : 2, - reserved_0b : 5, - num_users : 6; - uint32_t reserved_1b : 16, - num_users_he_sigb_band1 : 8, - reserved_1a : 5, - num_ltf_symbols : 3; - uint32_t reserved_2c : 15, - he_sigb_compression : 1, - reserved_2b : 7, - he_sigb_dcm : 1, - reserved : 2, - packet_extension : 3, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2; - uint32_t pe_chain_csd_en : 1, - pe_content : 1, - pe_ltf_size : 2, - pe_nss : 3, - ftm_en : 1, - reserved_3b : 1, - center_ru_1 : 1, - center_ru_0 : 1, - num_he_sigb_sym : 5, - reserved_3a : 13, - he_sigb_0_mcs : 3; - struct ru_allocation_160_info ru_allocation_0123_details; - struct ru_allocation_160_info ru_allocation_4567_details; - struct unallocated_ru_160_info ru_allocation_160_0_details; - struct unallocated_ru_160_info ru_allocation_160_1_details; - uint32_t reserved_14a : 7, - doppler_indication : 1, - ndp_feedback_status : 1, - ndp_ru_tone_set_index : 7, - num_data_symbols : 16; - uint32_t reserved_15a : 13, - dru_spreading_bw : 2, - distributed_ru : 1, - spatial_reuse : 16; -#endif -}; - -#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 -#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 -#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f - -#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 - -#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 - -#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 - -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 - -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 - -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 - -#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 -#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 -#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 - -#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 - -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 - -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 - -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 - -#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 -#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 -#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 - -#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 -#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 -#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 - -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 - -#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 - -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 - -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff - -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 - -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 - -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 - -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_LSB 48 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MSB 48 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MASK 0x0001000000000000 - -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_LSB 49 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MSB 50 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MASK 0x0006000000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 51 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xfff8000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_per_user.h deleted file mode 100644 index a68b50d9d639..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_per_user.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_USER_DESC_PER_USER_H_ -#define _MACTX_USER_DESC_PER_USER_H_ - -#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 6 - -#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 3 - -struct mactx_user_desc_per_user { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t psdu_length : 24, - reserved_0a : 8; - uint32_t ru_start_index : 8, - ru_size : 4, - reserved_1b : 4, - ofdma_mu_mimo_enabled : 1, - nss : 3, - stream_offset : 3, - reserved_1c : 1, - mcs : 5, - dcm : 1, - reserved_1d : 2; - uint32_t fec_type : 1, - reserved_2a : 1, - qam_diff1 : 2, - qam_diff2 : 2, - qam_diff3 : 2, - user_bf_type : 2, - a_factor_ldpc2x : 2, - extra_sym_ldpc2x : 1, - cw_len_2x : 2, - reserved_2b : 1, - drop_user_cbf : 1, - a_factor_ldpc1x : 2, - extra_sym_ldpc1x : 1, - cw_len_1x : 2, - ldpc1x_used : 1, - ldpc2x_used : 1, - ldpc_extra_symbol : 1, - force_extra_symbol : 1, - ldpc_2x_codeword : 1, - reserved_2d : 5; - uint32_t sw_peer_id : 16, - per_user_subband_mask : 16; - uint32_t ldpc_num_avbits : 27, - reserved_4a : 5; - uint32_t num_cw_1x : 16, - num_cw_2x : 16; -#else - uint32_t reserved_0a : 8, - psdu_length : 24; - uint32_t reserved_1d : 2, - dcm : 1, - mcs : 5, - reserved_1c : 1, - stream_offset : 3, - nss : 3, - ofdma_mu_mimo_enabled : 1, - reserved_1b : 4, - ru_size : 4, - ru_start_index : 8; - uint32_t reserved_2d : 5, - ldpc_2x_codeword : 1, - force_extra_symbol : 1, - ldpc_extra_symbol : 1, - ldpc2x_used : 1, - ldpc1x_used : 1, - cw_len_1x : 2, - extra_sym_ldpc1x : 1, - a_factor_ldpc1x : 2, - drop_user_cbf : 1, - reserved_2b : 1, - cw_len_2x : 2, - extra_sym_ldpc2x : 1, - a_factor_ldpc2x : 2, - user_bf_type : 2, - qam_diff3 : 2, - qam_diff2 : 2, - qam_diff1 : 2, - reserved_2a : 1, - fec_type : 1; - uint32_t per_user_subband_mask : 16, - sw_peer_id : 16; - uint32_t reserved_4a : 5, - ldpc_num_avbits : 27; - uint32_t num_cw_2x : 16, - num_cw_1x : 16; -#endif -}; - -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff - -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000 - -#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000 - -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000 - -#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_NSS_LSB 49 -#define MACTX_USER_DESC_PER_USER_NSS_MSB 51 -#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000 - -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000 - -#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_MCS_LSB 56 -#define MACTX_USER_DESC_PER_USER_MCS_MSB 60 -#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x1f00000000000000 - -#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_DCM_LSB 61 -#define MACTX_USER_DESC_PER_USER_DCM_MSB 61 -#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x2000000000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 62 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xc000000000000000 - -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 1 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x0000000000000002 - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_LSB 2 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MSB 3 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MASK 0x000000000000000c - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_LSB 4 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MSB 5 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MASK 0x0000000000000030 - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_LSB 6 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MSB 7 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MASK 0x00000000000000c0 - -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300 - -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_LSB 10 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MSB 11 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MASK 0x0000000000000c00 - -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_LSB 12 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MSB 12 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MASK 0x0000000000001000 - -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_LSB 13 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MSB 14 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MASK 0x0000000000006000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 15 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x0000000000008000 - -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_LSB 17 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MSB 18 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MASK 0x0000000000060000 - -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_LSB 19 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MSB 19 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MASK 0x0000000000080000 - -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_LSB 20 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MSB 21 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MASK 0x0000000000300000 - -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_LSB 22 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MSB 22 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MASK 0x0000000000400000 - -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_LSB 23 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MSB 23 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MASK 0x0000000000800000 - -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000 - -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000 - -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_LSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MASK 0x0000000004000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 27 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000f8000000 - -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000 - -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_LSB 0 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MASK 0x0000000007ffffff - -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_LSB 27 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MASK 0x00000000f8000000 - -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_LSB 32 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MSB 47 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_LSB 48 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MSB 63 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_a.h deleted file mode 100644 index 6dec145785d6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_a.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_A_H_ -#define _MACTX_VHT_SIG_A_H_ - -#include "vht_sig_a_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1 - -struct mactx_vht_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_a_info mactx_vht_sig_a_info_details; -#else - struct vht_sig_a_info mactx_vht_sig_a_info_details; -#endif -}; - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu160.h deleted file mode 100644 index b66278da930b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu160.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU160_H_ -#define _MACTX_VHT_SIG_B_MU160_H_ - -#include "vht_sig_b_mu160_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4 - -struct mactx_vht_sig_b_mu160 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; -#else - struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu20.h deleted file mode 100644 index 95feca30eaa3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu20.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU20_H_ -#define _MACTX_VHT_SIG_B_MU20_H_ - -#include "vht_sig_b_mu20_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1 - -struct mactx_vht_sig_b_mu20 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; - uint32_t tlv64_padding : 32; -#else - struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu40.h deleted file mode 100644 index c770db089203..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu40.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU40_H_ -#define _MACTX_VHT_SIG_B_MU40_H_ - -#include "vht_sig_b_mu40_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1 - -struct mactx_vht_sig_b_mu40 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; -#else - struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu80.h deleted file mode 100644 index 9e39d240b618..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu80.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU80_H_ -#define _MACTX_VHT_SIG_B_MU80_H_ - -#include "vht_sig_b_mu80_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2 - -struct mactx_vht_sig_b_mu80 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; -#else - struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su160.h deleted file mode 100644 index 01bc54e5ab89..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su160.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU160_H_ -#define _MACTX_VHT_SIG_B_SU160_H_ - -#include "vht_sig_b_su160_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4 - -struct mactx_vht_sig_b_su160 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; -#else - struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su20.h deleted file mode 100644 index c297cc0785e3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su20.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU20_H_ -#define _MACTX_VHT_SIG_B_SU20_H_ - -#include "vht_sig_b_su20_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1 - -struct mactx_vht_sig_b_su20 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; - uint32_t tlv64_padding : 32; -#else - struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su40.h deleted file mode 100644 index 002d72c430ca..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su40.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU40_H_ -#define _MACTX_VHT_SIG_B_SU40_H_ - -#include "vht_sig_b_su40_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1 - -struct mactx_vht_sig_b_su40 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; -#else - struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su80.h deleted file mode 100644 index b15646f03f4a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su80.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU80_H_ -#define _MACTX_VHT_SIG_B_SU80_H_ - -#include "vht_sig_b_su80_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2 - -struct mactx_vht_sig_b_su80 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; -#else - struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/fig/v2/mlo_sta_id_details.h deleted file mode 100644 index 952056890206..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mlo_sta_id_details.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MLO_STA_ID_DETAILS_H_ -#define _MLO_STA_ID_DETAILS_H_ - -#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 - -struct mlo_sta_id_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t nstr_mlo_sta_id : 10, - block_self_ml_sync : 1, - block_partner_ml_sync : 1, - nstr_mlo_sta_id_valid : 1, - reserved_0a : 3; -#else - uint16_t reserved_0a : 3, - nstr_mlo_sta_id_valid : 1, - block_partner_ml_sync : 1, - block_self_ml_sync : 1, - nstr_mlo_sta_id : 10; -#endif -}; - -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff - -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 - -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 - -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 - -#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 -#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 -#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mon_buffer_addr.h b/drivers/staging/fw-api/hw/fig/v2/mon_buffer_addr.h deleted file mode 100644 index 8cb6f5fd57b9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mon_buffer_addr.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_BUFFER_ADDR_H_ -#define _MON_BUFFER_ADDR_H_ - -#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 - -#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 - -struct mon_buffer_addr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t dma_length : 12, - reserved_2a : 4, - msdu_continuation : 1, - truncated : 1, - reserved_2b : 14; - uint32_t tlv64_padding : 32; -#else - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t reserved_2b : 14, - truncated : 1, - msdu_continuation : 1, - reserved_2a : 4, - dma_length : 12; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff - -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 - -#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 -#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 -#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff - -#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 -#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 -#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 - -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 - -#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 -#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 -#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 - -#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 -#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 -#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 - -#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 -#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 -#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mon_destination_ring.h b/drivers/staging/fw-api/hw/fig/v2/mon_destination_ring.h deleted file mode 100644 index 1f373b585fd5..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mon_destination_ring.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_DESTINATION_RING_H_ -#define _MON_DESTINATION_RING_H_ - -#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 - -struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t stat_buf_virt_addr_31_0 : 32; - uint32_t stat_buf_virt_addr_63_32 : 32; - uint32_t ppdu_id : 32; - uint32_t end_offset : 12, - reserved_3a : 2, - link_info : 2, - end_reason : 2, - initiator : 1, - empty_descriptor : 1, - pkt_buffer_cnt : 8, - looping_count : 4; -#else - uint32_t stat_buf_virt_addr_31_0 : 32; - uint32_t stat_buf_virt_addr_63_32 : 32; - uint32_t ppdu_id : 32; - uint32_t looping_count : 4, - pkt_buffer_cnt : 8, - empty_descriptor : 1, - initiator : 1, - end_reason : 2, - link_info : 2, - reserved_3a : 2, - end_offset : 12; -#endif -}; - -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff - -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff - -#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 -#define MON_DESTINATION_RING_PPDU_ID_LSB 0 -#define MON_DESTINATION_RING_PPDU_ID_MSB 31 -#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff - -#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c -#define MON_DESTINATION_RING_END_OFFSET_LSB 0 -#define MON_DESTINATION_RING_END_OFFSET_MSB 11 -#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff - -#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c -#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 -#define MON_DESTINATION_RING_RESERVED_3A_MSB 13 -#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x00003000 - -#define MON_DESTINATION_RING_LINK_INFO_OFFSET 0x0000000c -#define MON_DESTINATION_RING_LINK_INFO_LSB 14 -#define MON_DESTINATION_RING_LINK_INFO_MSB 15 -#define MON_DESTINATION_RING_LINK_INFO_MASK 0x0000c000 - -#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c -#define MON_DESTINATION_RING_END_REASON_LSB 16 -#define MON_DESTINATION_RING_END_REASON_MSB 17 -#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 - -#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c -#define MON_DESTINATION_RING_INITIATOR_LSB 18 -#define MON_DESTINATION_RING_INITIATOR_MSB 18 -#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 - -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 - -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_OFFSET 0x0000000c -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_LSB 20 -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MSB 27 -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MASK 0x0ff00000 - -#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c -#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 -#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 -#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mon_drop.h b/drivers/staging/fw-api/hw/fig/v2/mon_drop.h deleted file mode 100644 index d1135ecd0dc2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mon_drop.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_DROP_H_ -#define _MON_DROP_H_ - -#define NUM_OF_DWORDS_MON_DROP 2 - -#define NUM_OF_QWORDS_MON_DROP 1 - -struct mon_drop { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ppdu_id : 32; - uint32_t ppdu_drop_cnt : 10, - mpdu_drop_cnt : 10, - tlv_drop_cnt : 10, - end_of_ppdu_seen : 1, - reserved_1a : 1; -#else - uint32_t ppdu_id : 32; - uint32_t reserved_1a : 1, - end_of_ppdu_seen : 1, - tlv_drop_cnt : 10, - mpdu_drop_cnt : 10, - ppdu_drop_cnt : 10; -#endif -}; - -#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000 -#define MON_DROP_PPDU_ID_LSB 0 -#define MON_DROP_PPDU_ID_MSB 31 -#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff - -#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_PPDU_DROP_CNT_LSB 32 -#define MON_DROP_PPDU_DROP_CNT_MSB 41 -#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000 - -#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_MPDU_DROP_CNT_LSB 42 -#define MON_DROP_MPDU_DROP_CNT_MSB 51 -#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000 - -#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_TLV_DROP_CNT_LSB 52 -#define MON_DROP_TLV_DROP_CNT_MSB 61 -#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000 - -#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000 -#define MON_DROP_END_OF_PPDU_SEEN_LSB 62 -#define MON_DROP_END_OF_PPDU_SEEN_MSB 62 -#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000 - -#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000 -#define MON_DROP_RESERVED_1A_LSB 63 -#define MON_DROP_RESERVED_1A_MSB 63 -#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mon_ingress_ring.h b/drivers/staging/fw-api/hw/fig/v2/mon_ingress_ring.h deleted file mode 100644 index 76f4e80417e0..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mon_ingress_ring.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_INGRESS_RING_H_ -#define _MON_INGRESS_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_MON_INGRESS_RING 4 - -struct mon_ingress_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buffer_addr_info_details; - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; -#else - struct buffer_addr_info buffer_addr_info_details; - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; -#endif -}; - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff - -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/msmhwiobase.h b/drivers/staging/fw-api/hw/fig/v2/msmhwiobase.h deleted file mode 100644 index f7620cef5599..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/msmhwiobase.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef __MSMHWIOBASE_H__ -#define __MSMHWIOBASE_H__ - -#define SOC_WFSS_CE_REG_BASE 0x01b80000 -#define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 -#define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/msmhwioreg.h b/drivers/staging/fw-api/hw/fig/v2/msmhwioreg.h deleted file mode 100644 index 881c73e30f58..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/msmhwioreg.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef __MSMHWIOREG_H__ -#define __MSMHWIOREG_H__ - -#include "msmhwiobase.h" - -#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400) -#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058) - - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/no_ack_report.h b/drivers/staging/fw-api/hw/fig/v2/no_ack_report.h deleted file mode 100644 index 5f9660801de6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/no_ack_report.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _NO_ACK_REPORT_H_ -#define _NO_ACK_REPORT_H_ - -#define NUM_OF_DWORDS_NO_ACK_REPORT 4 - -struct no_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t no_ack_transmit_reason : 4, - macrx_abort_reason : 4, - phyrx_abort_reason : 8, - frame_control : 16; - uint32_t rx_ppdu_duration : 24, - sr_ppdu_during_obss : 1, - selfgen_response_reason_to_sr_ppdu : 4, - reserved_1 : 3; - uint32_t pre_bt_broadcast_status_details : 12, - first_bt_broadcast_status_details : 12, - reserved_2 : 8; - uint32_t second_bt_broadcast_status_details : 12, - reserved_3 : 20; -#else - uint32_t frame_control : 16, - phyrx_abort_reason : 8, - macrx_abort_reason : 4, - no_ack_transmit_reason : 4; - uint32_t reserved_1 : 3, - selfgen_response_reason_to_sr_ppdu : 4, - sr_ppdu_during_obss : 1, - rx_ppdu_duration : 24; - uint32_t reserved_2 : 8, - first_bt_broadcast_status_details : 12, - pre_bt_broadcast_status_details : 12; - uint32_t reserved_3 : 20, - second_bt_broadcast_status_details : 12; -#endif -}; - -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f - -#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 - -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 - -#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 -#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 -#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 -#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 - -#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 -#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 -#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 -#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff - -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 - -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 - -#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 -#define NO_ACK_REPORT_RESERVED_1_LSB 29 -#define NO_ACK_REPORT_RESERVED_1_MSB 31 -#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 - -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff - -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 - -#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 -#define NO_ACK_REPORT_RESERVED_2_LSB 24 -#define NO_ACK_REPORT_RESERVED_2_MSB 31 -#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 - -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff - -#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c -#define NO_ACK_REPORT_RESERVED_3_LSB 12 -#define NO_ACK_REPORT_RESERVED_3_MSB 31 -#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/fig/v2/ofdma_trigger_details.h deleted file mode 100644 index d1e667c885d4..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/ofdma_trigger_details.h +++ /dev/null @@ -1,944 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _OFDMA_TRIGGER_DETAILS_H_ -#define _OFDMA_TRIGGER_DETAILS_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 26 - -#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 13 - -struct ofdma_trigger_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ax_trigger_source : 1, - rx_trigger_frame_user_source : 2, - received_bandwidth : 3, - txop_duration_all_ones : 1, - eht_trigger_response : 1, - pre_rssi_comb : 8, - rssi_comb : 8, - rxpcu_pcie_l0_req_duration : 8; - uint32_t he_trigger_ul_ppdu_length : 5, - he_trigger_ru_allocation : 8, - he_trigger_dl_tx_power : 5, - he_trigger_ul_target_rssi : 5, - he_trigger_ul_mcs : 2, - he_trigger_reserved : 1, - bss_color : 6; - uint32_t trigger_type : 4, - lsig_response_length : 12, - cascade_indication : 1, - carrier_sense : 1, - bandwidth : 2, - cp_ltf_size : 2, - mu_mimo_ltf_mode : 1, - number_of_ltfs : 3, - stbc : 1, - ldpc_extra_symbol : 1, - ap_tx_power_lsb_part : 4; - uint32_t ap_tx_power_msb_part : 2, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - spatial_reuse : 16, - doppler : 1, - he_siga_reserved : 9, - reserved_3b : 1; - uint32_t aid12 : 12, - ru_allocation : 9, - mcs : 4, - dcm : 1, - start_spatial_stream : 3, - number_of_spatial_stream : 3; - uint32_t target_rssi : 7, - coding_type : 1, - mpdu_mu_spacing_factor : 2, - tid_aggregation_limit : 3, - reserved_5b : 1, - prefered_ac : 2, - bar_control_ack_policy : 1, - bar_control_multi_tid : 1, - bar_control_compressed_bitmap : 1, - bar_control_reserved : 9, - bar_control_tid_info : 4; - uint32_t nr0_per_tid_info_reserved : 12, - nr0_per_tid_info_tid_value : 4, - nr0_start_seq_ctrl_frag_number : 4, - nr0_start_seq_ctrl_start_seq_number : 12; - uint32_t nr1_per_tid_info_reserved : 12, - nr1_per_tid_info_tid_value : 4, - nr1_start_seq_ctrl_frag_number : 4, - nr1_start_seq_ctrl_start_seq_number : 12; - uint32_t nr2_per_tid_info_reserved : 12, - nr2_per_tid_info_tid_value : 4, - nr2_start_seq_ctrl_frag_number : 4, - nr2_start_seq_ctrl_start_seq_number : 12; - uint32_t nr3_per_tid_info_reserved : 12, - nr3_per_tid_info_tid_value : 4, - nr3_start_seq_ctrl_frag_number : 4, - nr3_start_seq_ctrl_start_seq_number : 12; - uint32_t nr4_per_tid_info_reserved : 12, - nr4_per_tid_info_tid_value : 4, - nr4_start_seq_ctrl_frag_number : 4, - nr4_start_seq_ctrl_start_seq_number : 12; - uint32_t nr5_per_tid_info_reserved : 12, - nr5_per_tid_info_tid_value : 4, - nr5_start_seq_ctrl_frag_number : 4, - nr5_start_seq_ctrl_start_seq_number : 12; - uint32_t nr6_per_tid_info_reserved : 12, - nr6_per_tid_info_tid_value : 4, - nr6_start_seq_ctrl_frag_number : 4, - nr6_start_seq_ctrl_start_seq_number : 12; - uint32_t nr7_per_tid_info_reserved : 12, - nr7_per_tid_info_tid_value : 4, - nr7_start_seq_ctrl_frag_number : 4, - nr7_start_seq_ctrl_start_seq_number : 12; - uint32_t fb_segment_retransmission_bitmap : 8, - reserved_14a : 2, - u_sig_puncture_pattern_encoding : 6, - dot11be_puncture_bitmap : 16; - uint32_t rx_chain_mask : 8, - rx_duration_field : 16, - scrambler_seed : 7, - rx_chain_mask_type : 1; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t normalized_pre_rssi_comb : 8, - normalized_rssi_comb : 8; - uint32_t sw_peer_id : 16, - response_tx_duration : 16; - uint32_t __reserved_g_0022_trigger_subtype : 4, - tbr_trigger_common_info_79_68 : 12, - tbr_trigger_sound_reserved_20_12 : 9, - i2r_rep : 3, - tbr_trigger_sound_reserved_25_24 : 2, - reserved_18a : 1, - qos_null_only_response_tx : 1; - uint32_t tbr_trigger_sound_sac : 16, - reserved_19a : 8, - u_sig_reserved2 : 5, - reserved_19b : 3; - uint32_t eht_special_aid12 : 12, - phy_version : 3, - bandwidth_ext : 2, - eht_spatial_reuse : 8, - u_sig_reserved1 : 7; - uint32_t eht_trigger_special_user_info_71_40 : 32; - uint32_t __reserved_g_0035 : 1, - __reserved_g_0035_trigger_subtype : 4, - blackout_details_en : 1, - uhr_trig_response : 1, - mcs_ext : 1, - dso_primary20_index_select : 4, - dso_icf_reception : 1, - dru_spreading_bw : 2, - dru_indication_per_80mhz : 4, - coding_type_ext : 1, - pad_duration : 5, - ects_as_tb_ppdu : 1, - reserved_22a : 6; - uint32_t dso_cca_puncture_pattern : 16, - dso_freq_subband_channel_bonding_mask : 16; - uint32_t __reserved_g_0017 : 1, - enable_steering : 1, - q2q_mba : 1, - reserved_24a : 29; - uint32_t reserved_25a : 32; -#else - uint32_t rxpcu_pcie_l0_req_duration : 8, - rssi_comb : 8, - pre_rssi_comb : 8, - eht_trigger_response : 1, - txop_duration_all_ones : 1, - received_bandwidth : 3, - rx_trigger_frame_user_source : 2, - ax_trigger_source : 1; - uint32_t bss_color : 6, - he_trigger_reserved : 1, - he_trigger_ul_mcs : 2, - he_trigger_ul_target_rssi : 5, - he_trigger_dl_tx_power : 5, - he_trigger_ru_allocation : 8, - he_trigger_ul_ppdu_length : 5; - uint32_t ap_tx_power_lsb_part : 4, - ldpc_extra_symbol : 1, - stbc : 1, - number_of_ltfs : 3, - mu_mimo_ltf_mode : 1, - cp_ltf_size : 2, - bandwidth : 2, - carrier_sense : 1, - cascade_indication : 1, - lsig_response_length : 12, - trigger_type : 4; - uint32_t reserved_3b : 1, - he_siga_reserved : 9, - doppler : 1, - spatial_reuse : 16, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - ap_tx_power_msb_part : 2; - uint32_t number_of_spatial_stream : 3, - start_spatial_stream : 3, - dcm : 1, - mcs : 4, - ru_allocation : 9, - aid12 : 12; - uint32_t bar_control_tid_info : 4, - bar_control_reserved : 9, - bar_control_compressed_bitmap : 1, - bar_control_multi_tid : 1, - bar_control_ack_policy : 1, - prefered_ac : 2, - reserved_5b : 1, - tid_aggregation_limit : 3, - mpdu_mu_spacing_factor : 2, - coding_type : 1, - target_rssi : 7; - uint32_t nr0_start_seq_ctrl_start_seq_number : 12, - nr0_start_seq_ctrl_frag_number : 4, - nr0_per_tid_info_tid_value : 4, - nr0_per_tid_info_reserved : 12; - uint32_t nr1_start_seq_ctrl_start_seq_number : 12, - nr1_start_seq_ctrl_frag_number : 4, - nr1_per_tid_info_tid_value : 4, - nr1_per_tid_info_reserved : 12; - uint32_t nr2_start_seq_ctrl_start_seq_number : 12, - nr2_start_seq_ctrl_frag_number : 4, - nr2_per_tid_info_tid_value : 4, - nr2_per_tid_info_reserved : 12; - uint32_t nr3_start_seq_ctrl_start_seq_number : 12, - nr3_start_seq_ctrl_frag_number : 4, - nr3_per_tid_info_tid_value : 4, - nr3_per_tid_info_reserved : 12; - uint32_t nr4_start_seq_ctrl_start_seq_number : 12, - nr4_start_seq_ctrl_frag_number : 4, - nr4_per_tid_info_tid_value : 4, - nr4_per_tid_info_reserved : 12; - uint32_t nr5_start_seq_ctrl_start_seq_number : 12, - nr5_start_seq_ctrl_frag_number : 4, - nr5_per_tid_info_tid_value : 4, - nr5_per_tid_info_reserved : 12; - uint32_t nr6_start_seq_ctrl_start_seq_number : 12, - nr6_start_seq_ctrl_frag_number : 4, - nr6_per_tid_info_tid_value : 4, - nr6_per_tid_info_reserved : 12; - uint32_t nr7_start_seq_ctrl_start_seq_number : 12, - nr7_start_seq_ctrl_frag_number : 4, - nr7_per_tid_info_tid_value : 4, - nr7_per_tid_info_reserved : 12; - uint32_t dot11be_puncture_bitmap : 16, - u_sig_puncture_pattern_encoding : 6, - reserved_14a : 2, - fb_segment_retransmission_bitmap : 8; - uint32_t rx_chain_mask_type : 1, - scrambler_seed : 7, - rx_duration_field : 16, - rx_chain_mask : 8; - uint32_t normalized_rssi_comb : 8, - normalized_pre_rssi_comb : 8; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint32_t response_tx_duration : 16, - sw_peer_id : 16; - uint32_t qos_null_only_response_tx : 1, - reserved_18a : 1, - tbr_trigger_sound_reserved_25_24 : 2, - i2r_rep : 3, - tbr_trigger_sound_reserved_20_12 : 9, - tbr_trigger_common_info_79_68 : 12, - __reserved_g_0022_trigger_subtype : 4; - uint32_t reserved_19b : 3, - u_sig_reserved2 : 5, - reserved_19a : 8, - tbr_trigger_sound_sac : 16; - uint32_t u_sig_reserved1 : 7, - eht_spatial_reuse : 8, - bandwidth_ext : 2, - phy_version : 3, - eht_special_aid12 : 12; - uint32_t eht_trigger_special_user_info_71_40 : 32; - uint32_t reserved_22a : 6, - ects_as_tb_ppdu : 1, - pad_duration : 5, - coding_type_ext : 1, - dru_indication_per_80mhz : 4, - dru_spreading_bw : 2, - dso_icf_reception : 1, - dso_primary20_index_select : 4, - mcs_ext : 1, - uhr_trig_response : 1, - blackout_details_en : 1, - __reserved_g_0035_trigger_subtype : 4, - __reserved_g_0035 : 1; - uint32_t dso_freq_subband_channel_bonding_mask : 16, - dso_cca_puncture_pattern : 16; - uint32_t reserved_24a : 29, - q2q_mba : 1, - enable_steering : 1, - __reserved_g_0017 : 1; - uint32_t reserved_25a : 32; -#endif -}; - -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001 - -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006 - -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038 - -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040 - -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080 - -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00 - -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000 - -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000 - -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000 - -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f - -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0 - -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000 - -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000 - -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000 - -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000 - -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000 - -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000 - -#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 -#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 -#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000 - -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000 - -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000 - -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000 - -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000 - -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000 - -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000 - -#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000 - -#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 -#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 -#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000 - -#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 -#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 -#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000 - -#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 -#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 -#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000 - -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000 - -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000 - -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000 - -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000 - -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000 - -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000 - -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff - -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00 - -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000 - -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000 - -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000 - -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000 - -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 - -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 - -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000 - -#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000 - -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000 - -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000 - -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000 - -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000 - -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000 - -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_LSB 5 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MSB 5 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MASK 0x0000000000000020 - -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_LSB 6 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MSB 6 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MASK 0x0000000000000040 - -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_LSB 7 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MSB 7 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MASK 0x0000000000000080 - -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_LSB 8 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MSB 11 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MASK 0x0000000000000f00 - -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MSB 12 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MASK 0x0000000000001000 - -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_LSB 13 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MSB 14 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MASK 0x0000000000006000 - -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_LSB 15 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MSB 18 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MASK 0x0000000000078000 - -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_LSB 19 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MSB 19 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MASK 0x0000000000080000 - -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_LSB 20 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MSB 24 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MASK 0x0000000001f00000 - -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 25 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 25 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x0000000002000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_LSB 26 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MASK 0x00000000fc000000 - -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_LSB 32 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MSB 47 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 48 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 63 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0xffff000000000000 - -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_LSB 1 -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MSB 1 -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MASK 0x0000000000000002 - -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_LSB 2 -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MSB 2 -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MASK 0x0000000000000004 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_LSB 3 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MASK 0x00000000fffffff8 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_LSB 32 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/fig/v2/pcu_ppdu_setup_init.h deleted file mode 100644 index f623a25ba4d4..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/pcu_ppdu_setup_init.h +++ /dev/null @@ -1,2316 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PCU_PPDU_SETUP_INIT_H_ -#define _PCU_PPDU_SETUP_INIT_H_ - -#include "pdg_response_rate_setting.h" -#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 - -#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29 - -struct pcu_ppdu_setup_init { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t medium_prot_type : 3, - response_type : 5, - response_info_part2_required : 1, - response_to_response : 3, - mba_user_order : 2, - expected_mba_size : 11, - required_ul_mu_resp_user_count : 6, - transmitted_bssid_check_en : 1; - uint32_t mprot_required_bw1 : 1, - mprot_required_bw20 : 1, - mprot_required_bw40 : 1, - mprot_required_bw80 : 1, - mprot_required_bw160 : 1, - mprot_required_bw240 : 1, - mprot_required_bw320 : 1, - ppdu_allowed_bw1 : 1, - ppdu_allowed_bw20 : 1, - ppdu_allowed_bw40 : 1, - ppdu_allowed_bw80 : 1, - ppdu_allowed_bw160 : 1, - ppdu_allowed_bw240 : 1, - ppdu_allowed_bw320 : 1, - set_fc_pwr_mgt : 1, - use_cts_duration_for_data_tx : 1, - update_timestamp_64 : 1, - update_timestamp_32_lower : 1, - update_timestamp_32_upper : 1, - reserved_1a : 13; - uint32_t insert_timestamp_offset_0 : 16, - insert_timestamp_offset_1 : 16; - uint32_t max_bw40_try_count : 4, - max_bw80_try_count : 4, - max_bw160_try_count : 4, - max_bw240_try_count : 4, - max_bw320_try_count : 4, - insert_wur_timestamp_offset : 6, - update_wur_timestamp : 1, - wur_embedded_bssid_present : 1, - insert_wur_fcs : 1, - q2q_trigger : 1, - reserved_3b : 2; - struct pdg_response_rate_setting response_to_response_rate_info_bw20; - struct pdg_response_rate_setting response_to_response_rate_info_bw40; - struct pdg_response_rate_setting response_to_response_rate_info_bw80; - struct pdg_response_rate_setting response_to_response_rate_info_bw160; - struct pdg_response_rate_setting response_to_response_rate_info_bw240; - struct pdg_response_rate_setting response_to_response_rate_info_bw320; - uint32_t r2r_hw_response_tx_duration : 16, - r2r_rx_duration_field : 16; - uint32_t r2r_group_id : 6, - r2r_response_frame_type : 4, - r2r_sta_partial_aid : 11, - use_address_fields_for_protection : 1, - r2r_set_required_response_time : 1, - reserved_29a : 3, - r2r_bw20_active_channel : 3, - r2r_bw40_active_channel : 3; - uint32_t r2r_bw80_active_channel : 3, - r2r_bw160_active_channel : 3, - r2r_bw240_active_channel : 3, - r2r_bw320_active_channel : 3, - r2r_bw20 : 3, - r2r_bw40 : 3, - r2r_bw80 : 3, - r2r_bw160 : 3, - r2r_bw240 : 3, - r2r_bw320 : 3, - tx_with_blackout_details : 1, - expect_rx_with_blackout_details : 1; - uint32_t mu_response_expected_bitmap_31_0 : 32; - uint32_t mu_response_expected_bitmap_36_32 : 5, - mu_expected_response_cbf_count : 6, - mu_expected_response_sta_count : 6, - transmit_includes_multidestination : 1, - insert_prev_tx_start_timing_info : 1, - insert_current_tx_start_timing_info : 1, - tx_start_transmit_time_byte_offset : 12; - uint32_t protection_frame_ad1_31_0 : 32; - uint32_t protection_frame_ad1_47_32 : 16, - protection_frame_ad2_15_0 : 16; - uint32_t protection_frame_ad2_47_16 : 32; - uint32_t dynamic_medium_prot_threshold : 24, - dynamic_medium_prot_type : 1, - reserved_54a : 7; - uint32_t protection_frame_ad3_31_0 : 32; - uint32_t protection_frame_ad3_47_32 : 16, - protection_frame_ad4_15_0 : 16; - uint32_t protection_frame_ad4_47_16 : 32; -#else - uint32_t transmitted_bssid_check_en : 1, - required_ul_mu_resp_user_count : 6, - expected_mba_size : 11, - mba_user_order : 2, - response_to_response : 3, - response_info_part2_required : 1, - response_type : 5, - medium_prot_type : 3; - uint32_t reserved_1a : 13, - update_timestamp_32_upper : 1, - update_timestamp_32_lower : 1, - update_timestamp_64 : 1, - use_cts_duration_for_data_tx : 1, - set_fc_pwr_mgt : 1, - ppdu_allowed_bw320 : 1, - ppdu_allowed_bw240 : 1, - ppdu_allowed_bw160 : 1, - ppdu_allowed_bw80 : 1, - ppdu_allowed_bw40 : 1, - ppdu_allowed_bw20 : 1, - ppdu_allowed_bw1 : 1, - mprot_required_bw320 : 1, - mprot_required_bw240 : 1, - mprot_required_bw160 : 1, - mprot_required_bw80 : 1, - mprot_required_bw40 : 1, - mprot_required_bw20 : 1, - mprot_required_bw1 : 1; - uint32_t insert_timestamp_offset_1 : 16, - insert_timestamp_offset_0 : 16; - uint32_t reserved_3b : 2, - q2q_trigger : 1, - insert_wur_fcs : 1, - wur_embedded_bssid_present : 1, - update_wur_timestamp : 1, - insert_wur_timestamp_offset : 6, - max_bw320_try_count : 4, - max_bw240_try_count : 4, - max_bw160_try_count : 4, - max_bw80_try_count : 4, - max_bw40_try_count : 4; - struct pdg_response_rate_setting response_to_response_rate_info_bw20; - struct pdg_response_rate_setting response_to_response_rate_info_bw40; - struct pdg_response_rate_setting response_to_response_rate_info_bw80; - struct pdg_response_rate_setting response_to_response_rate_info_bw160; - struct pdg_response_rate_setting response_to_response_rate_info_bw240; - struct pdg_response_rate_setting response_to_response_rate_info_bw320; - uint32_t r2r_rx_duration_field : 16, - r2r_hw_response_tx_duration : 16; - uint32_t r2r_bw40_active_channel : 3, - r2r_bw20_active_channel : 3, - reserved_29a : 3, - r2r_set_required_response_time : 1, - use_address_fields_for_protection : 1, - r2r_sta_partial_aid : 11, - r2r_response_frame_type : 4, - r2r_group_id : 6; - uint32_t expect_rx_with_blackout_details : 1, - tx_with_blackout_details : 1, - r2r_bw320 : 3, - r2r_bw240 : 3, - r2r_bw160 : 3, - r2r_bw80 : 3, - r2r_bw40 : 3, - r2r_bw20 : 3, - r2r_bw320_active_channel : 3, - r2r_bw240_active_channel : 3, - r2r_bw160_active_channel : 3, - r2r_bw80_active_channel : 3; - uint32_t mu_response_expected_bitmap_31_0 : 32; - uint32_t tx_start_transmit_time_byte_offset : 12, - insert_current_tx_start_timing_info : 1, - insert_prev_tx_start_timing_info : 1, - transmit_includes_multidestination : 1, - mu_expected_response_sta_count : 6, - mu_expected_response_cbf_count : 6, - mu_response_expected_bitmap_36_32 : 5; - uint32_t protection_frame_ad1_31_0 : 32; - uint32_t protection_frame_ad2_15_0 : 16, - protection_frame_ad1_47_32 : 16; - uint32_t protection_frame_ad2_47_16 : 32; - uint32_t reserved_54a : 7, - dynamic_medium_prot_type : 1, - dynamic_medium_prot_threshold : 24; - uint32_t protection_frame_ad3_31_0 : 32; - uint32_t protection_frame_ad4_15_0 : 16, - protection_frame_ad3_47_32 : 16; - uint32_t protection_frame_ad4_47_16 : 32; -#endif -}; - -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x0000000000000007 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x00000000000000f8 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0000000000000100 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x0000000000000e00 - -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x0000000000003000 - -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x0000000001ffc000 - -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x000000007e000000 - -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 32 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 32 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 33 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 33 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x0000000200000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 34 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 34 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x0000000400000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 35 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 35 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x0000000800000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 36 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 36 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x0000001000000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 37 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 37 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x0000002000000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 38 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 38 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x0000004000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 39 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 39 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 40 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 40 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x0000010000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 41 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 41 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x0000020000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 42 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 42 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 43 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 43 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 44 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 44 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 45 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 45 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 46 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 46 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 47 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 47 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 48 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 48 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x0001000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 49 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 49 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x0002000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 50 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 50 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x0004000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff8000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 32 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 35 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 36 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 39 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 40 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 43 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f0000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 44 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 47 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f00000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 48 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 51 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 52 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 57 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 58 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 58 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 59 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 59 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x0800000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 60 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 60 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x1000000000000000 - -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_LSB 61 -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_MSB 61 -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xc000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 37 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f00000000 - -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 38 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 41 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 42 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 52 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc0000000000 - -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 53 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 53 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 54 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 54 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x0040000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 55 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x0380000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 58 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 60 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c00000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 61 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 63 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe000000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x0000000000000007 - -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x0000000000000038 - -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x00000000000001c0 - -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x0000000000000e00 - -#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x0000000000007000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x0000000000038000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x0000000000e00000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x0000000007000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_LSB 30 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MSB 30 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB 31 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB 31 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x00000000000007e0 - -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x000000000001f800 - -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x0000000000020000 - -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x0000000000040000 - -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0x00000000fff00000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x0000000000ffffff - -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0x00000000fe000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/pdg_response.h b/drivers/staging/fw-api/hw/fig/v2/pdg_response.h deleted file mode 100644 index d94c69ff2645..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/pdg_response.h +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_RESPONSE_H_ -#define _PDG_RESPONSE_H_ - -#include "pdg_response_rate_setting.h" -#define NUM_OF_DWORDS_PDG_RESPONSE 14 - -#define NUM_OF_QWORDS_PDG_RESPONSE 7 - -struct pdg_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct pdg_response_rate_setting hw_response_rate_info; - uint32_t hw_response_tx_duration : 16, - rx_duration_field : 16; - uint32_t punctured_response_transmission : 1, - cca_subband_channel_bonding_mask : 16, - scrambler_seed_override : 2, - response_density_valid : 1, - response_density : 5, - more_data : 1, - duration_indication : 1, - blackout_details_en : 1, - cfp_protected_resp : 1, - bandwidth : 3; - uint32_t ack_id : 16, - block_ack_bitmap : 16; - uint32_t response_frame_type : 4, - ack_id_ext : 10, - ftm_en : 1, - group_id : 6, - sta_partial_aid : 11; - uint32_t ndp_ba_start_seq_ctrl : 12, - active_channel : 3, - txop_duration_all_ones : 1, - frame_length : 16; - uint32_t dso_primary20_index_select : 4, - dso_freq_subband_channel_bonding_mask : 16, - pad_duration : 5, - q2q_mba : 1, - reserved_12a : 6; - uint32_t tlv64_padding : 32; -#else - struct pdg_response_rate_setting hw_response_rate_info; - uint32_t rx_duration_field : 16, - hw_response_tx_duration : 16; - uint32_t bandwidth : 3, - cfp_protected_resp : 1, - blackout_details_en : 1, - duration_indication : 1, - more_data : 1, - response_density : 5, - response_density_valid : 1, - scrambler_seed_override : 2, - cca_subband_channel_bonding_mask : 16, - punctured_response_transmission : 1; - uint32_t block_ack_bitmap : 16, - ack_id : 16; - uint32_t sta_partial_aid : 11, - group_id : 6, - ftm_en : 1, - ack_id_ext : 10, - response_frame_type : 4; - uint32_t frame_length : 16, - txop_duration_all_ones : 1, - active_channel : 3, - ndp_ba_start_seq_ctrl : 12; - uint32_t reserved_12a : 6, - q2q_mba : 1, - pad_duration : 5, - dso_freq_subband_channel_bonding_mask : 16, - dso_primary20_index_select : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MSB 3 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MASK 0x000000000000000f - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 36 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 37 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000e000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 46 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00007c0000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_LSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000 - -#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48 -#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63 -#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000 - -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001 - -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe - -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000 - -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000 - -#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 -#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 -#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000 - -#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_MORE_DATA_LSB 25 -#define PDG_RESPONSE_MORE_DATA_MSB 25 -#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000 - -#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 -#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 -#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000 - -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_LSB 27 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MSB 27 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MASK 0x0000000008000000 - -#define PDG_RESPONSE_CFP_PROTECTED_RESP_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_CFP_PROTECTED_RESP_LSB 28 -#define PDG_RESPONSE_CFP_PROTECTED_RESP_MSB 28 -#define PDG_RESPONSE_CFP_PROTECTED_RESP_MASK 0x0000000010000000 - -#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BANDWIDTH_LSB 29 -#define PDG_RESPONSE_BANDWIDTH_MSB 31 -#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000 - -#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_ACK_ID_LSB 32 -#define PDG_RESPONSE_ACK_ID_MSB 47 -#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000 - -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000 - -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f - -#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 -#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 -#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0 - -#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_FTM_EN_LSB 14 -#define PDG_RESPONSE_FTM_EN_MSB 14 -#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000 - -#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_GROUP_ID_LSB 15 -#define PDG_RESPONSE_GROUP_ID_MSB 20 -#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000 - -#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 -#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 -#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000 - -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000 - -#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44 -#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46 -#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000 - -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000 - -#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_FRAME_LENGTH_LSB 48 -#define PDG_RESPONSE_FRAME_LENGTH_MSB 63 -#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000 - -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_LSB 0 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MSB 3 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MASK 0x000000000000000f - -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 4 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 19 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x00000000000ffff0 - -#define PDG_RESPONSE_PAD_DURATION_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_PAD_DURATION_LSB 20 -#define PDG_RESPONSE_PAD_DURATION_MSB 24 -#define PDG_RESPONSE_PAD_DURATION_MASK 0x0000000001f00000 - -#define PDG_RESPONSE_Q2Q_MBA_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_Q2Q_MBA_LSB 25 -#define PDG_RESPONSE_Q2Q_MBA_MSB 25 -#define PDG_RESPONSE_Q2Q_MBA_MASK 0x0000000002000000 - -#define PDG_RESPONSE_RESERVED_12A_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_RESERVED_12A_LSB 26 -#define PDG_RESPONSE_RESERVED_12A_MSB 31 -#define PDG_RESPONSE_RESERVED_12A_MASK 0x00000000fc000000 - -#define PDG_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_TLV64_PADDING_LSB 32 -#define PDG_RESPONSE_TLV64_PADDING_MSB 63 -#define PDG_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/pdg_response_rate_setting.h b/drivers/staging/fw-api/hw/fig/v2/pdg_response_rate_setting.h deleted file mode 100644 index eb123386f2bf..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/pdg_response_rate_setting.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_RESPONSE_RATE_SETTING_H_ -#define _PDG_RESPONSE_RATE_SETTING_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 - -struct pdg_response_rate_setting { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 1, - tx_antenna_sector_ctrl : 24, - pkt_type : 4, - smoothing : 1, - ldpc : 1, - stbc : 1; - uint32_t alt_tx_pwr : 8, - alt_min_tx_pwr : 8, - alt_nss : 3, - alt_tx_chain_mask : 8, - alt_bw : 3, - stf_ltf_3db_boost : 1, - force_extra_symbol : 1; - uint32_t reserved_2a : 4, - nss : 3, - dpd_enable : 1, - tx_pwr : 8, - min_tx_pwr : 8, - tx_chain_mask : 8; - uint32_t alt_rate_mcs : 5, - reserved_3a : 3, - sgi : 2, - rate_mcs : 5, - ldpc_2x_codeword : 1, - tx_pwr_1 : 8, - alt_tx_pwr_1 : 8; - uint32_t aggregation : 1, - dot11ax_bss_color_id : 6, - dot11ax_spatial_reuse : 4, - dot11ax_cp_ltf_size : 2, - dot11ax_dcm : 1, - dot11ax_doppler_indication : 1, - dot11ax_su_extended : 1, - dot11ax_min_packet_extension : 2, - dot11ax_pe_nss : 3, - dot11ax_pe_content : 1, - dot11ax_pe_ltf_size : 2, - dot11ax_chain_csd_en : 1, - dot11ax_pe_chain_csd_en : 1, - dot11ax_dl_ul_flag : 1, - reserved_4a : 5; - uint32_t dot11ax_ext_ru_start_index : 4, - dot11ax_ext_ru_size : 4, - eht_duplicate_mode : 2, - he_sigb_dcm : 1, - he_sigb_0_mcs : 3, - num_he_sigb_sym : 5, - required_response_time_source : 1, - reserved_5a : 6, - u_sig_puncture_pattern_encoding : 6; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t required_response_time : 12, - dot11be_params_placeholder : 4; -#else - uint32_t stbc : 1, - ldpc : 1, - smoothing : 1, - pkt_type : 4, - tx_antenna_sector_ctrl : 24, - reserved_0a : 1; - uint32_t force_extra_symbol : 1, - stf_ltf_3db_boost : 1, - alt_bw : 3, - alt_tx_chain_mask : 8, - alt_nss : 3, - alt_min_tx_pwr : 8, - alt_tx_pwr : 8; - uint32_t tx_chain_mask : 8, - min_tx_pwr : 8, - tx_pwr : 8, - dpd_enable : 1, - nss : 3, - reserved_2a : 4; - uint32_t alt_tx_pwr_1 : 8, - tx_pwr_1 : 8, - ldpc_2x_codeword : 1, - rate_mcs : 5, - sgi : 2, - reserved_3a : 3, - alt_rate_mcs : 5; - uint32_t reserved_4a : 5, - dot11ax_dl_ul_flag : 1, - dot11ax_pe_chain_csd_en : 1, - dot11ax_chain_csd_en : 1, - dot11ax_pe_ltf_size : 2, - dot11ax_pe_content : 1, - dot11ax_pe_nss : 3, - dot11ax_min_packet_extension : 2, - dot11ax_su_extended : 1, - dot11ax_doppler_indication : 1, - dot11ax_dcm : 1, - dot11ax_cp_ltf_size : 2, - dot11ax_spatial_reuse : 4, - dot11ax_bss_color_id : 6, - aggregation : 1; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_5a : 6, - required_response_time_source : 1, - num_he_sigb_sym : 5, - he_sigb_0_mcs : 3, - he_sigb_dcm : 1, - eht_duplicate_mode : 2, - dot11ax_ext_ru_size : 4, - dot11ax_ext_ru_start_index : 4; - uint32_t dot11be_params_placeholder : 4, - required_response_time : 12; - struct mlo_sta_id_details mlo_sta_id_details_rx; -#endif -}; - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 - -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe - -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 - -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 - -#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 -#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 -#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 - -#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 -#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff - -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 - -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 - -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 - -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MSB 3 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MASK 0x0000000f - -#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 -#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 -#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 - -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 - -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 - -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 - -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 4 -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000001f - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 5 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000e0 - -#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 - -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 14 -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00007c00 - -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_LSB 15 -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MASK 0x00008000 - -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 - -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 - -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 - -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 - -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 - -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 - -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 - -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 - -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/pdg_tx_req.h b/drivers/staging/fw-api/hw/fig/v2/pdg_tx_req.h deleted file mode 100644 index 6baf640807da..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/pdg_tx_req.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_TX_REQ_H_ -#define _PDG_TX_REQ_H_ - -#define NUM_OF_DWORDS_PDG_TX_REQ 2 - -#define NUM_OF_QWORDS_PDG_TX_REQ 1 - -struct pdg_tx_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_reason : 2, - use_puncture_pattern : 2, - req_bw : 3, - puncture_pattern_number : 6, - reserved_0b : 1, - req_paprd : 1, - duration_field_boundary_valid : 1, - duration_field_boundary : 16; - uint32_t puncture_subband_mask : 16, - reserved_0c : 16; -#else - uint32_t duration_field_boundary : 16, - duration_field_boundary_valid : 1, - req_paprd : 1, - reserved_0b : 1, - puncture_pattern_number : 6, - req_bw : 3, - use_puncture_pattern : 2, - tx_reason : 2; - uint32_t reserved_0c : 16, - puncture_subband_mask : 16; -#endif -}; - -#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_TX_REASON_LSB 0 -#define PDG_TX_REQ_TX_REASON_MSB 1 -#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003 - -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c - -#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_REQ_BW_LSB 4 -#define PDG_TX_REQ_REQ_BW_MSB 6 -#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070 - -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80 - -#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_RESERVED_0B_LSB 13 -#define PDG_TX_REQ_RESERVED_0B_MSB 13 -#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000 - -#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_REQ_PAPRD_LSB 14 -#define PDG_TX_REQ_REQ_PAPRD_MSB 14 -#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000 - -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000 - -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000 - -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000 - -#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_RESERVED_0C_LSB 48 -#define PDG_TX_REQ_RESERVED_0C_MSB 63 -#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_abort_request_info.h deleted file mode 100644 index 1f3bf4b817b9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_abort_request_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ -#define _PHYRX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 - -struct phyrx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phyrx_abort_reason : 8, - phy_enters_nap_state : 1, - phy_enters_defer_state : 1, - gain_change_by_main : 1, - gain_change_by_bt : 1, - main_tx_indication : 1, - bt_tx_indication : 1, - concurrent_mode : 1, - reserved_0 : 1, - receive_duration : 16; -#else - uint32_t receive_duration : 16, - reserved_0 : 1, - concurrent_mode : 1, - bt_tx_indication : 1, - main_tx_indication : 1, - gain_change_by_bt : 1, - gain_change_by_main : 1, - phy_enters_defer_state : 1, - phy_enters_nap_state : 1, - phyrx_abort_reason : 8; -#endif -}; - -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff - -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 - -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 - -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB 10 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB 10 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK 0x00000400 - -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB 11 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB 11 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK 0x00000800 - -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB 12 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB 12 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK 0x00001000 - -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB 13 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB 13 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK 0x00002000 - -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB 14 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB 14 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK 0x00004000 - -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 15 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x00008000 - -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_common_user_info.h deleted file mode 100644 index b0817f33c169..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_common_user_info.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_COMMON_USER_INFO_H_ -#define _PHYRX_COMMON_USER_INFO_H_ - -#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4 - -#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2 - -struct phyrx_common_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t receive_duration : 16, - reserved_0a : 16; - uint32_t u_sig_puncture_pattern_encoding : 6, - eht___reserved_g_0022_ndp : 1, - bss_color_id_2 : 6, - reserved_1a : 2, - obss_nav_update_enable : 1, - obss_nav_value : 16; - uint32_t eht_or_uhr_ppdu_type : 2, - bss_color_id : 6, - dl_ul_flag : 1, - txop_duration : 7, - cp_setting : 2, - ltf_size : 2, - spatial_reuse : 4, - rx_ndp : 1, - dot11bn_su_elr : 1, - combining_bandwidth : 3, - bss_flag : 1, - cobf_transmission : 1, - cosr_transmission : 1; - uint32_t eht_duplicate : 2, - eht_or_uhr_sig_cmn_field_type : 2, - doppler_indication : 1, - sta_id : 11, - puncture_bitmap : 16; -#else - uint32_t reserved_0a : 16, - receive_duration : 16; - uint32_t obss_nav_value : 16, - obss_nav_update_enable : 1, - reserved_1a : 2, - bss_color_id_2 : 6, - eht___reserved_g_0022_ndp : 1, - u_sig_puncture_pattern_encoding : 6; - uint32_t cosr_transmission : 1, - cobf_transmission : 1, - bss_flag : 1, - combining_bandwidth : 3, - dot11bn_su_elr : 1, - rx_ndp : 1, - spatial_reuse : 4, - ltf_size : 2, - cp_setting : 2, - txop_duration : 7, - dl_ul_flag : 1, - bss_color_id : 6, - eht_or_uhr_ppdu_type : 2; - uint32_t puncture_bitmap : 16, - sta_id : 11, - doppler_indication : 1, - eht_or_uhr_sig_cmn_field_type : 2, - eht_duplicate : 2; -#endif -}; - -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x000000000000ffff - -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0x00000000ffff0000 - -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 32 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 37 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f00000000 - -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_2_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_2_LSB 39 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_2_MSB 44 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_2_MASK 0x00001f8000000000 - -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 45 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 46 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0x0000600000000000 - -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB 47 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB 47 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK 0x0000800000000000 - -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB 48 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB 63 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK 0xffff000000000000 - -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_LSB 0 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MSB 1 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MASK 0x0000000000000003 - -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x00000000000000fc - -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x0000000000000100 - -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x000000000000fe00 - -#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x0000000000030000 - -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x00000000000c0000 - -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x0000000000f00000 - -#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24 -#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24 -#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x0000000001000000 - -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_LSB 25 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MSB 25 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MASK 0x0000000002000000 - -#define PHYRX_COMMON_USER_INFO_COMBINING_BANDWIDTH_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_COMBINING_BANDWIDTH_LSB 26 -#define PHYRX_COMMON_USER_INFO_COMBINING_BANDWIDTH_MSB 28 -#define PHYRX_COMMON_USER_INFO_COMBINING_BANDWIDTH_MASK 0x000000001c000000 - -#define PHYRX_COMMON_USER_INFO_BSS_FLAG_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_BSS_FLAG_LSB 29 -#define PHYRX_COMMON_USER_INFO_BSS_FLAG_MSB 29 -#define PHYRX_COMMON_USER_INFO_BSS_FLAG_MASK 0x0000000020000000 - -#define PHYRX_COMMON_USER_INFO_COBF_TRANSMISSION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_COBF_TRANSMISSION_LSB 30 -#define PHYRX_COMMON_USER_INFO_COBF_TRANSMISSION_MSB 30 -#define PHYRX_COMMON_USER_INFO_COBF_TRANSMISSION_MASK 0x0000000040000000 - -#define PHYRX_COMMON_USER_INFO_COSR_TRANSMISSION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_COSR_TRANSMISSION_LSB 31 -#define PHYRX_COMMON_USER_INFO_COSR_TRANSMISSION_MSB 31 -#define PHYRX_COMMON_USER_INFO_COSR_TRANSMISSION_MASK 0x0000000080000000 - -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 32 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 33 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x0000000300000000 - -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_LSB 34 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MSB 35 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MASK 0x0000000c00000000 - -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 36 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 36 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x0000001000000000 - -#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 37 -#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 47 -#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe000000000 - -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 48 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 63 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_dl.h deleted file mode 100644 index da4f1691b9f7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_dl.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ -#define _PHYRX_HE_SIG_A_MU_DL_H_ - -#include "he_sig_a_mu_dl_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1 - -struct phyrx_he_sig_a_mu_dl { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; -#else - struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_ul.h deleted file mode 100644 index ff9cf72a7237..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_ul.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ -#define _PHYRX_HE_SIG_A_MU_UL_H_ - -#include "he_sig_a_mu_ul_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1 - -struct phyrx_he_sig_a_mu_ul { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; -#else - struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_su.h deleted file mode 100644 index abca58673a90..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_su.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_SU_H_ -#define _PHYRX_HE_SIG_A_SU_H_ - -#include "he_sig_a_su_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1 - -struct phyrx_he_sig_a_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; -#else - struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b1_mu.h deleted file mode 100644 index ae784469331b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b1_mu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B1_MU_H_ -#define _PHYRX_HE_SIG_B1_MU_H_ - -#include "he_sig_b1_mu_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1 - -struct phyrx_he_sig_b1_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#else - struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_mu.h deleted file mode 100644 index 6035ecffde5d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_mu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B2_MU_H_ -#define _PHYRX_HE_SIG_B2_MU_H_ - -#include "he_sig_b2_mu_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1 - -struct phyrx_he_sig_b2_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; -#else - struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; -#endif -}; - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_ofdma.h deleted file mode 100644 index 126a9559e155..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_ofdma.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ -#define _PHYRX_HE_SIG_B2_OFDMA_H_ - -#include "he_sig_b2_ofdma_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1 - -struct phyrx_he_sig_b2_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; -#else - struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; -#endif -}; - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_ht_sig.h deleted file mode 100644 index 4dd90653d431..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_ht_sig.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HT_SIG_H_ -#define _PHYRX_HT_SIG_H_ - -#include "ht_sig_info.h" -#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 - -#define NUM_OF_QWORDS_PHYRX_HT_SIG 1 - -struct phyrx_ht_sig { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ht_sig_info phyrx_ht_sig_info_details; -#else - struct ht_sig_info phyrx_ht_sig_info_details; -#endif -}; - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_a.h deleted file mode 100644 index 2e70822f5d06..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_a.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_L_SIG_A_H_ -#define _PHYRX_L_SIG_A_H_ - -#include "l_sig_a_info.h" -#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2 - -#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1 - -struct phyrx_l_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_a_info phyrx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_a_info phyrx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32 -#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63 -#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_b.h deleted file mode 100644 index 461edd24dd4e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_b.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_L_SIG_B_H_ -#define _PHYRX_L_SIG_B_H_ - -#include "l_sig_b_info.h" -#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2 - -#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1 - -struct phyrx_l_sig_b { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_b_info phyrx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_b_info phyrx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32 -#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63 -#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_location.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_location.h deleted file mode 100644 index 15a8413e304a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_location.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_LOCATION_H_ -#define _PHYRX_LOCATION_H_ - -#include "rx_location_info.h" -#define NUM_OF_DWORDS_PHYRX_LOCATION 28 - -#define NUM_OF_QWORDS_PHYRX_LOCATION 14 - -struct phyrx_location { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_location_info rx_location_info_details; -#else - struct rx_location_info rx_location_info_details; -#endif -}; - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_other_receive_info_ru_details.h deleted file mode 100644 index a6090f721e1d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_other_receive_info_ru_details.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ -#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ - -#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4 - -#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2 - -struct phyrx_other_receive_info_ru_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_details_channel_0 : 32; - uint32_t ru_details_channel_1 : 32; - uint32_t spare : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t ru_details_channel_0 : 32; - uint32_t ru_details_channel_1 : 32; - uint32_t spare : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000 - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_pkt_end.h deleted file mode 100644 index 1d1675edc0e1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_pkt_end.h +++ /dev/null @@ -1,427 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_PKT_END_H_ -#define _PHYRX_PKT_END_H_ - -#include "phyrx_pkt_end_info.h" -#define NUM_OF_DWORDS_PHYRX_PKT_END 24 - -#define NUM_OF_QWORDS_PHYRX_PKT_END 12 - -struct phyrx_pkt_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct phyrx_pkt_end_info rx_pkt_end_details; -#else - struct phyrx_pkt_end_info rx_pkt_end_details; -#endif -}; - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 44 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 53 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff00000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB 54 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc0000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_pkt_end_info.h deleted file mode 100644 index a21edc94d24e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_pkt_end_info.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_PKT_END_INFO_H_ -#define _PHYRX_PKT_END_INFO_H_ - -#include "receive_rssi_info.h" -#include "rx_timing_info.h" -#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 - -struct phyrx_pkt_end_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0001 : 1, - location_info_valid : 1, - timing_info_valid : 1, - rssi_info_valid : 1, - reserved_0a : 1, - frameless_frame_received : 1, - reserved_0b : 2, - rssi_comb : 8, - reserved_0c : 16; - struct rx_timing_info rx_timing_info_details; - struct receive_rssi_info post_rssi_info_details; - uint32_t phy_sw_status_31_0 : 32; - uint32_t phy_sw_status_63_32 : 32; -#else - uint32_t reserved_0c : 16, - rssi_comb : 8, - reserved_0b : 2, - frameless_frame_received : 1, - reserved_0a : 1, - rssi_info_valid : 1, - timing_info_valid : 1, - location_info_valid : 1, - __reserved_g_0001 : 1; - struct rx_timing_info rx_timing_info_details; - struct receive_rssi_info post_rssi_info_details; - uint32_t phy_sw_status_31_0 : 32; - uint32_t phy_sw_status_63_32 : 32; -#endif -}; - -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 - -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 - -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 - -#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 -#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 -#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 - -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 - -#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 -#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 -#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 - -#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 -#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 -#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 -#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 -#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 12 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 21 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff000 - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB 22 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc00000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_rssi_legacy.h deleted file mode 100644 index 820ced6212ca..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_rssi_legacy.h +++ /dev/null @@ -1,806 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_RSSI_LEGACY_H_ -#define _PHYRX_RSSI_LEGACY_H_ - -#include "receive_rssi_info.h" -#include "receive_pkt_start_info.h" -#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 - -#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21 - -struct phyrx_rssi_legacy { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_pkt_start_info rx_pkt_start_details; - uint32_t sw_phy_meta_data : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 32; - struct receive_rssi_info pre_rssi_info_details; - struct receive_rssi_info preamble_rssi_info_details; - uint32_t pre_rssi_comb : 8, - rssi_comb : 8, - normalized_pre_rssi_comb : 8, - normalized_rssi_comb : 8; - uint32_t rssi_comb_ppdu : 8, - rssi_db_to_dbm_offset : 8, - rssi_for_spatial_reuse : 8, - rssi_for_trigger_resp : 8; -#else - struct receive_pkt_start_info rx_pkt_start_details; - uint32_t sw_phy_meta_data : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 32; - struct receive_rssi_info pre_rssi_info_details; - struct receive_rssi_info preamble_rssi_info_details; - uint32_t normalized_rssi_comb : 8, - normalized_pre_rssi_comb : 8, - rssi_comb : 8, - pre_rssi_comb : 8; - uint32_t rssi_for_trigger_resp : 8, - rssi_for_spatial_reuse : 8, - rssi_db_to_dbm_offset : 8, - rssi_comb_ppdu : 8; -#endif -}; - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB 3 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK 0x000000000000000f - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x0000000000000010 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB 5 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB 7 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00000000000000e0 - -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB 8 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB 15 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB 16 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB 32 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB 63 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB 32 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB 39 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB 40 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB 40 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK 0x0000010000000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB 41 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB 63 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK 0xfffffe0000000000 - -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x0000000000000010 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 31 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x0000000000000010 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 32 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 63 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x0000000000000018 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000000000000018 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 32 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 63 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 32 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 39 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 40 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 47 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 48 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 55 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 56 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 63 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_user_info.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_user_info.h deleted file mode 100644 index 784904450033..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_user_info.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_USER_INFO_H_ -#define _PHYRX_USER_INFO_H_ - -#include "receive_user_info.h" -#define NUM_OF_DWORDS_PHYRX_USER_INFO 8 - -#define NUM_OF_QWORDS_PHYRX_USER_INFO 4 - -struct phyrx_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_user_info receive_user_info_details; -#else - struct receive_user_info receive_user_info_details; -#endif -}; - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 36 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000001f00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 37 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 38 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000006000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 1 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x0000000000000002 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB 2 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB 3 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK 0x000000000000000c - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB 4 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB 5 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK 0x0000000000000030 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB 6 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB 7 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK 0x00000000000000c0 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_LSB 62 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MSB 62 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MASK 0x4000000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0x8000000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_vht_sig_a.h deleted file mode 100644 index e47f0e35adeb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_vht_sig_a.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_VHT_SIG_A_H_ -#define _PHYRX_VHT_SIG_A_H_ - -#include "vht_sig_a_info.h" -#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 - -#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1 - -struct phyrx_vht_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_a_info phyrx_vht_sig_a_info_details; -#else - struct vht_sig_a_info phyrx_vht_sig_a_info_details; -#endif -}; - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phytx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v2/phytx_abort_request_info.h deleted file mode 100644 index e4800f6a2d97..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phytx_abort_request_info.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ -#define _PHYTX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 - -struct phytx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t phytx_abort_reason : 8, - user_number : 6, - reserved : 2; -#else - uint16_t reserved : 2, - user_number : 6, - phytx_abort_reason : 8; -#endif -}; - -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff - -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 - -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phytx_pkt_end.h b/drivers/staging/fw-api/hw/fig/v2/phytx_pkt_end.h deleted file mode 100644 index 55911ea9edb3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phytx_pkt_end.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_PKT_END_H_ -#define _PHYTX_PKT_END_H_ - -#define NUM_OF_WORDS_PHYTX_PKT_END 28 - -#define NUM_OF_DWORDS_PHYTX_PKT_END 14 - -struct phytx_pkt_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t start_of_frame_timestamp_15_0 : 16; - uint16_t start_of_frame_timestamp_31_16 : 16; - uint16_t end_of_frame_timestamp_15_0 : 16; - uint16_t end_of_frame_timestamp_31_16 : 16; - uint16_t tx_group_delay : 12, - timing_status : 2, - phyrx_entered_nap_state : 1, - dpdtrain_done : 1; - uint16_t transmit_delay : 16; - uint16_t tpc_dbg_info_cmn_15_0 : 16; - uint16_t tpc_dbg_info_cmn_31_16 : 16; - uint16_t tpc_dbg_info_cmn_47_32 : 16; - uint16_t tpc_dbg_info_chn1_15_0 : 16; - uint16_t tpc_dbg_info_chn1_31_16 : 16; - uint16_t tpc_dbg_info_chn1_47_32 : 16; - uint16_t tpc_dbg_info_chn1_63_48 : 16; - uint16_t tpc_dbg_info_chn1_79_64 : 16; - uint16_t tpc_dbg_info_chn2_15_0 : 16; - uint16_t tpc_dbg_info_chn2_31_16 : 16; - uint16_t tpc_dbg_info_chn2_47_32 : 16; - uint16_t tpc_dbg_info_chn2_63_48 : 16; - uint16_t tpc_dbg_info_chn2_79_64 : 16; - uint16_t phytx_tx_end_sw_info_15_0 : 16; - uint16_t phytx_tx_end_sw_info_31_16 : 16; - uint16_t phytx_tx_end_sw_info_47_32 : 16; - uint16_t phytx_tx_end_sw_info_63_48 : 16; - uint16_t beamform_masked_user_bitmap_15_0 : 16; - uint16_t beamform_masked_user_bitmap_31_16 : 16; - uint16_t beamform_masked_user_bitmap_36_32 : 5, - reserved_23 : 11; - uint16_t reserved_26 : 16; - uint16_t reserved_27 : 16; -#else - uint16_t start_of_frame_timestamp_15_0 : 16; - uint16_t start_of_frame_timestamp_31_16 : 16; - uint16_t end_of_frame_timestamp_15_0 : 16; - uint16_t end_of_frame_timestamp_31_16 : 16; - uint16_t dpdtrain_done : 1, - phyrx_entered_nap_state : 1, - timing_status : 2, - tx_group_delay : 12; - uint16_t transmit_delay : 16; - uint16_t tpc_dbg_info_cmn_15_0 : 16; - uint16_t tpc_dbg_info_cmn_31_16 : 16; - uint16_t tpc_dbg_info_cmn_47_32 : 16; - uint16_t tpc_dbg_info_chn1_15_0 : 16; - uint16_t tpc_dbg_info_chn1_31_16 : 16; - uint16_t tpc_dbg_info_chn1_47_32 : 16; - uint16_t tpc_dbg_info_chn1_63_48 : 16; - uint16_t tpc_dbg_info_chn1_79_64 : 16; - uint16_t tpc_dbg_info_chn2_15_0 : 16; - uint16_t tpc_dbg_info_chn2_31_16 : 16; - uint16_t tpc_dbg_info_chn2_47_32 : 16; - uint16_t tpc_dbg_info_chn2_63_48 : 16; - uint16_t tpc_dbg_info_chn2_79_64 : 16; - uint16_t phytx_tx_end_sw_info_15_0 : 16; - uint16_t phytx_tx_end_sw_info_31_16 : 16; - uint16_t phytx_tx_end_sw_info_47_32 : 16; - uint16_t phytx_tx_end_sw_info_63_48 : 16; - uint16_t beamform_masked_user_bitmap_15_0 : 16; - uint16_t beamform_masked_user_bitmap_31_16 : 16; - uint16_t reserved_23 : 11, - beamform_masked_user_bitmap_36_32 : 5; - uint16_t reserved_26 : 16; - uint16_t reserved_27 : 16; -#endif -}; - -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000000 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000002 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 0 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 15 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000004 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000006 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 0 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 15 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET 0x00000008 -#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB 0 -#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB 11 -#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK 0x00000fff - -#define PHYTX_PKT_END_TIMING_STATUS_OFFSET 0x00000008 -#define PHYTX_PKT_END_TIMING_STATUS_LSB 12 -#define PHYTX_PKT_END_TIMING_STATUS_MSB 13 -#define PHYTX_PKT_END_TIMING_STATUS_MASK 0x00003000 - -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET 0x00000008 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB 14 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB 14 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK 0x00004000 - -#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET 0x00000008 -#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB 15 -#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB 15 -#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK 0x00008000 - -#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET 0x0000000a -#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB 0 -#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB 15 -#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000c -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000e -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET 0x00000010 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x00000012 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x00000014 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x00000016 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x00000018 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000001a -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000001c -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000001e -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x00000020 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x00000022 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x00000024 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x00000026 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x00000028 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000002a -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000002c -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000002e -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x00000030 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 15 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000032 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 4 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x0000001f - -#define PHYTX_PKT_END_RESERVED_23_OFFSET 0x00000032 -#define PHYTX_PKT_END_RESERVED_23_LSB 5 -#define PHYTX_PKT_END_RESERVED_23_MSB 15 -#define PHYTX_PKT_END_RESERVED_23_MASK 0x0000ffe0 - -#define PHYTX_PKT_END_RESERVED_26_OFFSET 0x00000034 -#define PHYTX_PKT_END_RESERVED_26_LSB 0 -#define PHYTX_PKT_END_RESERVED_26_MSB 15 -#define PHYTX_PKT_END_RESERVED_26_MASK 0x0000ffff - -#define PHYTX_PKT_END_RESERVED_27_OFFSET 0x00000036 -#define PHYTX_PKT_END_RESERVED_27_LSB 0 -#define PHYTX_PKT_END_RESERVED_27_MSB 15 -#define PHYTX_PKT_END_RESERVED_27_MASK 0x0000ffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phytx_ppdu_header_info_request.h b/drivers/staging/fw-api/hw/fig/v2/phytx_ppdu_header_info_request.h deleted file mode 100644 index 7fbecae41236..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phytx_ppdu_header_info_request.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ -#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ - -#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 - -#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 - -struct phytx_ppdu_header_info_request { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t request_type : 5, - reserved : 11; - uint16_t tlv32_padding : 16; -#else - uint16_t reserved : 11, - request_type : 5; - uint16_t tlv32_padding : 16; -#endif -}; - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/receive_pkt_start_info.h b/drivers/staging/fw-api/hw/fig/v2/receive_pkt_start_info.h deleted file mode 100644 index 7f7c81449a15..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/receive_pkt_start_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_PKT_START_INFO_H_ -#define _RECEIVE_PKT_START_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4 - -struct receive_pkt_start_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reception_type : 4, - rx_chain_mask_type : 1, - receive_bandwidth : 3, - rx_chain_mask : 8, - phy_ppdu_id : 16; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t preamble_time_to_rxframe : 8, - standalone_sniffer_mode : 1, - reserved_3a : 23; -#else - uint32_t phy_ppdu_id : 16, - rx_chain_mask : 8, - receive_bandwidth : 3, - rx_chain_mask_type : 1, - reception_type : 4; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t reserved_3a : 23, - standalone_sniffer_mode : 1, - preamble_time_to_rxframe : 8; -#endif -}; - -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB 0 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB 3 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK 0x0000000f - -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB 4 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB 4 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK 0x00000010 - -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB 5 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB 7 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK 0x000000e0 - -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB 8 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB 15 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK 0x0000ff00 - -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB 16 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB 31 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK 0xffff0000 - -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff - -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff - -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB 0 -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB 7 -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff - -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB 8 -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB 8 -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK 0x00000100 - -#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB 9 -#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB 31 -#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK 0xfffffe00 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/receive_rssi_info.h b/drivers/staging/fw-api/hw/fig/v2/receive_rssi_info.h deleted file mode 100644 index 9aaa98217d99..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/receive_rssi_info.h +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_RSSI_INFO_H_ -#define _RECEIVE_RSSI_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 - -struct receive_rssi_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rssi_pri20_chain0 : 8, - rssi_ext20_chain0 : 8, - rssi_ext40_low20_chain0 : 8, - rssi_ext40_high20_chain0 : 8; - uint32_t rssi_ext80_low20_chain0 : 8, - rssi_ext80_low_high20_chain0 : 8, - rssi_ext80_high_low20_chain0 : 8, - rssi_ext80_high20_chain0 : 8; - uint32_t rssi_ext160_0_chain0 : 8, - rssi_ext160_1_chain0 : 8, - rssi_ext160_2_chain0 : 8, - rssi_ext160_3_chain0 : 8; - uint32_t rssi_ext160_4_chain0 : 8, - rssi_ext160_5_chain0 : 8, - rssi_ext160_6_chain0 : 8, - rssi_ext160_7_chain0 : 8; - uint32_t rssi_pri20_chain1 : 8, - rssi_ext20_chain1 : 8, - rssi_ext40_low20_chain1 : 8, - rssi_ext40_high20_chain1 : 8; - uint32_t rssi_ext80_low20_chain1 : 8, - rssi_ext80_low_high20_chain1 : 8, - rssi_ext80_high_low20_chain1 : 8, - rssi_ext80_high20_chain1 : 8; - uint32_t rssi_ext160_0_chain1 : 8, - rssi_ext160_1_chain1 : 8, - rssi_ext160_2_chain1 : 8, - rssi_ext160_3_chain1 : 8; - uint32_t rssi_ext160_4_chain1 : 8, - rssi_ext160_5_chain1 : 8, - rssi_ext160_6_chain1 : 8, - rssi_ext160_7_chain1 : 8; - uint32_t rssi_pri20_chain2 : 8, - rssi_ext20_chain2 : 8, - rssi_ext40_low20_chain2 : 8, - rssi_ext40_high20_chain2 : 8; - uint32_t rssi_ext80_low20_chain2 : 8, - rssi_ext80_low_high20_chain2 : 8, - rssi_ext80_high_low20_chain2 : 8, - rssi_ext80_high20_chain2 : 8; - uint32_t rssi_ext160_0_chain2 : 8, - rssi_ext160_1_chain2 : 8, - rssi_ext160_2_chain2 : 8, - rssi_ext160_3_chain2 : 8; - uint32_t rssi_ext160_4_chain2 : 8, - rssi_ext160_5_chain2 : 8, - rssi_ext160_6_chain2 : 8, - rssi_ext160_7_chain2 : 8; - uint32_t rssi_pri20_chain3 : 8, - rssi_ext20_chain3 : 8, - rssi_ext40_low20_chain3 : 8, - rssi_ext40_high20_chain3 : 8; - uint32_t rssi_ext80_low20_chain3 : 8, - rssi_ext80_low_high20_chain3 : 8, - rssi_ext80_high_low20_chain3 : 8, - rssi_ext80_high20_chain3 : 8; - uint32_t rssi_ext160_0_chain3 : 8, - rssi_ext160_1_chain3 : 8, - rssi_ext160_2_chain3 : 8, - rssi_ext160_3_chain3 : 8; - uint32_t rssi_ext160_4_chain3 : 8, - rssi_ext160_5_chain3 : 8, - rssi_ext160_6_chain3 : 8, - rssi_ext160_7_chain3 : 8; -#else - uint32_t rssi_ext40_high20_chain0 : 8, - rssi_ext40_low20_chain0 : 8, - rssi_ext20_chain0 : 8, - rssi_pri20_chain0 : 8; - uint32_t rssi_ext80_high20_chain0 : 8, - rssi_ext80_high_low20_chain0 : 8, - rssi_ext80_low_high20_chain0 : 8, - rssi_ext80_low20_chain0 : 8; - uint32_t rssi_ext160_3_chain0 : 8, - rssi_ext160_2_chain0 : 8, - rssi_ext160_1_chain0 : 8, - rssi_ext160_0_chain0 : 8; - uint32_t rssi_ext160_7_chain0 : 8, - rssi_ext160_6_chain0 : 8, - rssi_ext160_5_chain0 : 8, - rssi_ext160_4_chain0 : 8; - uint32_t rssi_ext40_high20_chain1 : 8, - rssi_ext40_low20_chain1 : 8, - rssi_ext20_chain1 : 8, - rssi_pri20_chain1 : 8; - uint32_t rssi_ext80_high20_chain1 : 8, - rssi_ext80_high_low20_chain1 : 8, - rssi_ext80_low_high20_chain1 : 8, - rssi_ext80_low20_chain1 : 8; - uint32_t rssi_ext160_3_chain1 : 8, - rssi_ext160_2_chain1 : 8, - rssi_ext160_1_chain1 : 8, - rssi_ext160_0_chain1 : 8; - uint32_t rssi_ext160_7_chain1 : 8, - rssi_ext160_6_chain1 : 8, - rssi_ext160_5_chain1 : 8, - rssi_ext160_4_chain1 : 8; - uint32_t rssi_ext40_high20_chain2 : 8, - rssi_ext40_low20_chain2 : 8, - rssi_ext20_chain2 : 8, - rssi_pri20_chain2 : 8; - uint32_t rssi_ext80_high20_chain2 : 8, - rssi_ext80_high_low20_chain2 : 8, - rssi_ext80_low_high20_chain2 : 8, - rssi_ext80_low20_chain2 : 8; - uint32_t rssi_ext160_3_chain2 : 8, - rssi_ext160_2_chain2 : 8, - rssi_ext160_1_chain2 : 8, - rssi_ext160_0_chain2 : 8; - uint32_t rssi_ext160_7_chain2 : 8, - rssi_ext160_6_chain2 : 8, - rssi_ext160_5_chain2 : 8, - rssi_ext160_4_chain2 : 8; - uint32_t rssi_ext40_high20_chain3 : 8, - rssi_ext40_low20_chain3 : 8, - rssi_ext20_chain3 : 8, - rssi_pri20_chain3 : 8; - uint32_t rssi_ext80_high20_chain3 : 8, - rssi_ext80_high_low20_chain3 : 8, - rssi_ext80_low_high20_chain3 : 8, - rssi_ext80_low20_chain3 : 8; - uint32_t rssi_ext160_3_chain3 : 8, - rssi_ext160_2_chain3 : 8, - rssi_ext160_1_chain3 : 8, - rssi_ext160_0_chain3 : 8; - uint32_t rssi_ext160_7_chain3 : 8, - rssi_ext160_6_chain3 : 8, - rssi_ext160_5_chain3 : 8, - rssi_ext160_4_chain3 : 8; -#endif -}; - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/receive_user_info.h b/drivers/staging/fw-api/hw/fig/v2/receive_user_info.h deleted file mode 100644 index 51617cc781c0..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/receive_user_info.h +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_USER_INFO_H_ -#define _RECEIVE_USER_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8 - -struct receive_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - user_rssi : 8, - pkt_type : 4, - stbc : 1, - reception_type : 3; - uint32_t rate_mcs : 5, - sgi : 2, - __reserved_g_0004 : 1, - mimo_ss_bitmap : 8, - receive_bandwidth : 3, - reserved_1b : 5, - dl_ofdma_user_index : 8; - uint32_t dl_ofdma_content_channel : 1, - reserved_2a : 1, - qam_diff1 : 2, - qam_diff2 : 2, - qam_diff3 : 2, - nss : 3, - stream_offset : 3, - sta_dcm : 1, - ldpc : 1, - ru_type_80_0 : 4, - ru_type_80_1 : 4, - ru_type_80_2 : 4, - ru_type_80_3 : 4; - uint32_t ru_start_index_80_0 : 6, - reserved_3a : 2, - ru_start_index_80_1 : 6, - reserved_3b : 2, - ru_start_index_80_2 : 6, - reserved_3c : 2, - ru_start_index_80_3 : 6, - ldpc_2x_codeword : 1, - reserved_3d : 1; - uint32_t user_fd_rssi_seg0 : 32; - uint32_t user_fd_rssi_seg1 : 32; - uint32_t user_fd_rssi_seg2 : 32; - uint32_t user_fd_rssi_seg3 : 32; -#else - uint32_t reception_type : 3, - stbc : 1, - pkt_type : 4, - user_rssi : 8, - phy_ppdu_id : 16; - uint32_t dl_ofdma_user_index : 8, - reserved_1b : 5, - receive_bandwidth : 3, - mimo_ss_bitmap : 8, - __reserved_g_0004 : 1, - sgi : 2, - rate_mcs : 5; - uint32_t ru_type_80_3 : 4, - ru_type_80_2 : 4, - ru_type_80_1 : 4, - ru_type_80_0 : 4, - ldpc : 1, - sta_dcm : 1, - stream_offset : 3, - nss : 3, - qam_diff3 : 2, - qam_diff2 : 2, - qam_diff1 : 2, - reserved_2a : 1, - dl_ofdma_content_channel : 1; - uint32_t reserved_3d : 1, - ldpc_2x_codeword : 1, - ru_start_index_80_3 : 6, - reserved_3c : 2, - ru_start_index_80_2 : 6, - reserved_3b : 2, - ru_start_index_80_1 : 6, - reserved_3a : 2, - ru_start_index_80_0 : 6; - uint32_t user_fd_rssi_seg0 : 32; - uint32_t user_fd_rssi_seg1 : 32; - uint32_t user_fd_rssi_seg2 : 32; - uint32_t user_fd_rssi_seg3 : 32; -#endif -}; - -#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff - -#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_USER_RSSI_LSB 16 -#define RECEIVE_USER_INFO_USER_RSSI_MSB 23 -#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 - -#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 -#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 -#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 - -#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_STBC_LSB 28 -#define RECEIVE_USER_INFO_STBC_MSB 28 -#define RECEIVE_USER_INFO_STBC_MASK 0x10000000 - -#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 - -#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RATE_MCS_LSB 0 -#define RECEIVE_USER_INFO_RATE_MCS_MSB 4 -#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000001f - -#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_SGI_LSB 5 -#define RECEIVE_USER_INFO_SGI_MSB 6 -#define RECEIVE_USER_INFO_SGI_MASK 0x00000060 - -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 - -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 - -#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 -#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 -#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 - -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 - -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 - -#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 -#define RECEIVE_USER_INFO_RESERVED_2A_MSB 1 -#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x00000002 - -#define RECEIVE_USER_INFO_QAM_DIFF1_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF1_LSB 2 -#define RECEIVE_USER_INFO_QAM_DIFF1_MSB 3 -#define RECEIVE_USER_INFO_QAM_DIFF1_MASK 0x0000000c - -#define RECEIVE_USER_INFO_QAM_DIFF2_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF2_LSB 4 -#define RECEIVE_USER_INFO_QAM_DIFF2_MSB 5 -#define RECEIVE_USER_INFO_QAM_DIFF2_MASK 0x00000030 - -#define RECEIVE_USER_INFO_QAM_DIFF3_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF3_LSB 6 -#define RECEIVE_USER_INFO_QAM_DIFF3_MSB 7 -#define RECEIVE_USER_INFO_QAM_DIFF3_MASK 0x000000c0 - -#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_NSS_LSB 8 -#define RECEIVE_USER_INFO_NSS_MSB 10 -#define RECEIVE_USER_INFO_NSS_MASK 0x00000700 - -#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 -#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 -#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 - -#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_STA_DCM_LSB 14 -#define RECEIVE_USER_INFO_STA_DCM_MSB 14 -#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 - -#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_LDPC_LSB 15 -#define RECEIVE_USER_INFO_LDPC_MSB 15 -#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f - -#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 -#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 -#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 - -#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 -#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 -#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 - -#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 -#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 -#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 - -#define RECEIVE_USER_INFO_LDPC_2X_CODEWORD_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_LDPC_2X_CODEWORD_LSB 30 -#define RECEIVE_USER_INFO_LDPC_2X_CODEWORD_MSB 30 -#define RECEIVE_USER_INFO_LDPC_2X_CODEWORD_MASK 0x40000000 - -#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3D_LSB 31 -#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 -#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0x80000000 - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_response_user_15_8.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_15_8.h deleted file mode 100644 index 6cf8117ff02f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_response_user_15_8.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ -#define _RECEIVED_RESPONSE_USER_15_8_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32 - -struct received_response_user_15_8 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user8; - struct received_response_user_info received_response_details_user9; - struct received_response_user_info received_response_details_user10; - struct received_response_user_info received_response_details_user11; - struct received_response_user_info received_response_details_user12; - struct received_response_user_info received_response_details_user13; - struct received_response_user_info received_response_details_user14; - struct received_response_user_info received_response_details_user15; -#else - struct received_response_user_info received_response_details_user8; - struct received_response_user_info received_response_details_user9; - struct received_response_user_info received_response_details_user10; - struct received_response_user_info received_response_details_user11; - struct received_response_user_info received_response_details_user12; - struct received_response_user_info received_response_details_user13; - struct received_response_user_info received_response_details_user14; - struct received_response_user_info received_response_details_user15; -#endif -}; - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_response_user_23_16.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_23_16.h deleted file mode 100644 index ff56f4d96472..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_response_user_23_16.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ -#define _RECEIVED_RESPONSE_USER_23_16_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32 - -struct received_response_user_23_16 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user16; - struct received_response_user_info received_response_details_user17; - struct received_response_user_info received_response_details_user18; - struct received_response_user_info received_response_details_user19; - struct received_response_user_info received_response_details_user20; - struct received_response_user_info received_response_details_user21; - struct received_response_user_info received_response_details_user22; - struct received_response_user_info received_response_details_user23; -#else - struct received_response_user_info received_response_details_user16; - struct received_response_user_info received_response_details_user17; - struct received_response_user_info received_response_details_user18; - struct received_response_user_info received_response_details_user19; - struct received_response_user_info received_response_details_user20; - struct received_response_user_info received_response_details_user21; - struct received_response_user_info received_response_details_user22; - struct received_response_user_info received_response_details_user23; -#endif -}; - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_response_user_31_24.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_31_24.h deleted file mode 100644 index aaa90838daa9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_response_user_31_24.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ -#define _RECEIVED_RESPONSE_USER_31_24_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32 - -struct received_response_user_31_24 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user24; - struct received_response_user_info received_response_details_user25; - struct received_response_user_info received_response_details_user26; - struct received_response_user_info received_response_details_user27; - struct received_response_user_info received_response_details_user28; - struct received_response_user_info received_response_details_user29; - struct received_response_user_info received_response_details_user30; - struct received_response_user_info received_response_details_user31; -#else - struct received_response_user_info received_response_details_user24; - struct received_response_user_info received_response_details_user25; - struct received_response_user_info received_response_details_user26; - struct received_response_user_info received_response_details_user27; - struct received_response_user_info received_response_details_user28; - struct received_response_user_info received_response_details_user29; - struct received_response_user_info received_response_details_user30; - struct received_response_user_info received_response_details_user31; -#endif -}; - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_response_user_36_32.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_36_32.h deleted file mode 100644 index 3f33fdab635e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_response_user_36_32.h +++ /dev/null @@ -1,705 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ -#define _RECEIVED_RESPONSE_USER_36_32_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20 - -struct received_response_user_36_32 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user32; - struct received_response_user_info received_response_details_user33; - struct received_response_user_info received_response_details_user34; - struct received_response_user_info received_response_details_user35; - struct received_response_user_info received_response_details_user36; -#else - struct received_response_user_info received_response_details_user32; - struct received_response_user_info received_response_details_user33; - struct received_response_user_info received_response_details_user34; - struct received_response_user_info received_response_details_user35; - struct received_response_user_info received_response_details_user36; -#endif -}; - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_response_user_7_0.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_7_0.h deleted file mode 100644 index f785aca46840..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_response_user_7_0.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ -#define _RECEIVED_RESPONSE_USER_7_0_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32 - -struct received_response_user_7_0 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user0; - struct received_response_user_info received_response_details_user1; - struct received_response_user_info received_response_details_user2; - struct received_response_user_info received_response_details_user3; - struct received_response_user_info received_response_details_user4; - struct received_response_user_info received_response_details_user5; - struct received_response_user_info received_response_details_user6; - struct received_response_user_info received_response_details_user7; -#else - struct received_response_user_info received_response_details_user0; - struct received_response_user_info received_response_details_user1; - struct received_response_user_info received_response_details_user2; - struct received_response_user_info received_response_details_user3; - struct received_response_user_info received_response_details_user4; - struct received_response_user_info received_response_details_user5; - struct received_response_user_info received_response_details_user6; - struct received_response_user_info received_response_details_user7; -#endif -}; - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_response_user_info.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_info.h deleted file mode 100644 index 3c3faf119635..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_response_user_info.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ -#define _RECEIVED_RESPONSE_USER_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 - -struct received_response_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mpdu_fcs_pass_count : 12, - mpdu_fcs_fail_count : 12, - qosnull_frame_count : 4, - reserved_0a : 3, - user_info_valid : 1; - uint32_t null_delimiter_count : 22, - reserved_1a : 9, - ht_control_valid : 1; - uint32_t ht_control : 32; - uint32_t qos_control_valid : 16, - eosp : 16; - uint32_t qos_control_15_8_tid_0 : 8, - qos_control_15_8_tid_1 : 8, - qos_control_15_8_tid_2 : 8, - qos_control_15_8_tid_3 : 8; - uint32_t qos_control_15_8_tid_4 : 8, - qos_control_15_8_tid_5 : 8, - qos_control_15_8_tid_6 : 8, - qos_control_15_8_tid_7 : 8; - uint32_t qos_control_15_8_tid_8 : 8, - qos_control_15_8_tid_9 : 8, - qos_control_15_8_tid_10 : 8, - qos_control_15_8_tid_11 : 8; - uint32_t qos_control_15_8_tid_12 : 8, - qos_control_15_8_tid_13 : 8, - qos_control_15_8_tid_14 : 8, - qos_control_15_8_tid_15 : 8; -#else - uint32_t user_info_valid : 1, - reserved_0a : 3, - qosnull_frame_count : 4, - mpdu_fcs_fail_count : 12, - mpdu_fcs_pass_count : 12; - uint32_t ht_control_valid : 1, - reserved_1a : 9, - null_delimiter_count : 22; - uint32_t ht_control : 32; - uint32_t eosp : 16, - qos_control_valid : 16; - uint32_t qos_control_15_8_tid_3 : 8, - qos_control_15_8_tid_2 : 8, - qos_control_15_8_tid_1 : 8, - qos_control_15_8_tid_0 : 8; - uint32_t qos_control_15_8_tid_7 : 8, - qos_control_15_8_tid_6 : 8, - qos_control_15_8_tid_5 : 8, - qos_control_15_8_tid_4 : 8; - uint32_t qos_control_15_8_tid_11 : 8, - qos_control_15_8_tid_10 : 8, - qos_control_15_8_tid_9 : 8, - qos_control_15_8_tid_8 : 8; - uint32_t qos_control_15_8_tid_15 : 8, - qos_control_15_8_tid_14 : 8, - qos_control_15_8_tid_13 : 8, - qos_control_15_8_tid_12 : 8; -#endif -}; - -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff - -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 - -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 - -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 - -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 - -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff - -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 - -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 - -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff - -#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c -#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_trigger_info.h b/drivers/staging/fw-api/hw/fig/v2/received_trigger_info.h deleted file mode 100644 index ff464f4e3bb5..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_trigger_info.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_TRIGGER_INFO_H_ -#define _RECEIVED_TRIGGER_INFO_H_ - -#include "received_trigger_info_details.h" -#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6 - -#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3 - -struct received_trigger_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_trigger_info_details received_trigger_details; -#else - struct received_trigger_info_details received_trigger_details; -#endif -}; - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB 29 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB 30 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK 0x0000000060000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x0000000080000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_LSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MASK 0x2000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x4000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0x8000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 48 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 56 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xc000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x0000000100000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 33 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 36 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 37 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 39 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_LSB 40 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MASK 0xffffff0000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_trigger_info_details.h b/drivers/staging/fw-api/hw/fig/v2/received_trigger_info_details.h deleted file mode 100644 index 071942ba26bd..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_trigger_info_details.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ -#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ - -#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 6 - -struct received_trigger_info_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t trigger_type : 4, - ax_trigger_source : 1, - ax_trigger_type : 4, - trigger_source_sta_full_aid : 13, - frame_control_valid : 1, - qos_control_valid : 1, - he_control_info_valid : 1, - __reserved_g_0022_trigger_subtype : 4, - txop_sharing_mode : 2, - tid_aggregation_limit_is_zero : 1; - uint32_t phy_ppdu_id : 16, - lsig_response_length : 12, - __reserved_g_0035 : 1, - scsid_valid : 1, - ects_as_tb_ppdu : 1, - reserved_1a : 1; - uint32_t frame_control : 16, - qos_control : 16; - uint32_t sw_peer_id : 16, - txop_sharing_allocation_duration : 9, - __reserved_g_0035_trigger_subtype : 4, - __reserved_g_0017 : 1, - reserved_3a : 2; - uint32_t he_control : 32; - uint32_t txop_sharing_duration_from_durid : 1, - frame_durationid_lower_4 : 4, - frame_durationid_upper_3 : 3, - reserved_5a : 24; -#else - uint32_t tid_aggregation_limit_is_zero : 1, - txop_sharing_mode : 2, - __reserved_g_0022_trigger_subtype : 4, - he_control_info_valid : 1, - qos_control_valid : 1, - frame_control_valid : 1, - trigger_source_sta_full_aid : 13, - ax_trigger_type : 4, - ax_trigger_source : 1, - trigger_type : 4; - uint32_t reserved_1a : 1, - ects_as_tb_ppdu : 1, - scsid_valid : 1, - __reserved_g_0035 : 1, - lsig_response_length : 12, - phy_ppdu_id : 16; - uint32_t qos_control : 16, - frame_control : 16; - uint32_t reserved_3a : 2, - __reserved_g_0017 : 1, - __reserved_g_0035_trigger_subtype : 4, - txop_sharing_allocation_duration : 9, - sw_peer_id : 16; - uint32_t he_control : 32; - uint32_t reserved_5a : 24, - frame_durationid_upper_3 : 3, - frame_durationid_lower_4 : 4, - txop_sharing_duration_from_durid : 1; -#endif -}; - -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f - -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 - -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MASK 0x20000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_LSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MASK 0x40000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0x80000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xc0000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x00000001 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 1 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 5 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 7 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e0 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_LSB 8 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MASK 0xffffff00 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring.h b/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring.h deleted file mode 100644 index 5147635121c1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_DESTINATION_RING_H_ -#define _REO_DESTINATION_RING_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_mpdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_REO_DESTINATION_RING 8 - -struct reo_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t release_source_module : 3, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_delink_error : 1, - sw_buffer_cookie : 20; - uint32_t msdu_link_desc_index : 4, - reserved_6a : 28; - uint32_t reo_dest_buffer_type : 1, - reo_push_reason : 2, - reo_error_code : 5, - captured_msdu_data_size : 4, - sw_exception : 1, - src_link_id : 3, - reo_destination_struct_signature : 4, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t sw_buffer_cookie : 20, - reo_delink_error : 1, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - release_source_module : 3; - uint32_t reserved_6a : 28, - msdu_link_desc_index : 4; - uint32_t looping_count : 4, - ring_id : 8, - reo_destination_struct_signature : 4, - src_link_id : 3, - sw_exception : 1, - captured_msdu_data_size : 4, - reo_error_code : 5, - reo_push_reason : 2, - reo_dest_buffer_type : 1; -#endif -}; - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_LSB 3 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MSB 3 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MASK 0x00000008 - -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_LSB 4 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MSB 5 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MASK 0x00000030 - -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_LSB 6 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MSB 10 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MASK 0x000007c0 - -#define REO_DESTINATION_RING_REO_DELINK_ERROR_OFFSET 0x00000014 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_LSB 11 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_MSB 11 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_MASK 0x00000800 - -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_LSB 0 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MSB 3 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MASK 0x0000000f - -#define REO_DESTINATION_RING_RESERVED_6A_OFFSET 0x00000018 -#define REO_DESTINATION_RING_RESERVED_6A_LSB 4 -#define REO_DESTINATION_RING_RESERVED_6A_MSB 31 -#define REO_DESTINATION_RING_RESERVED_6A_MASK 0xfffffff0 - -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 - -#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 -#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 -#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 - -#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 -#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 -#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 - -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 - -#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c -#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 -#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 -#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 - -#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 -#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 -#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 - -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 - -#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_RING_ID_LSB 20 -#define REO_DESTINATION_RING_RING_ID_MSB 27 -#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 - -#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 -#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 -#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring_with_pn.h b/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring_with_pn.h deleted file mode 100644 index b486a8658388..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring_with_pn.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_DESTINATION_RING_WITH_PN_H_ -#define _REO_DESTINATION_RING_WITH_PN_H_ - -#include "rx_msdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8 - -struct reo_destination_ring_with_pn { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - uint32_t msdu_count : 8, - prev_pn_23_0 : 24; - uint32_t prev_pn_47_24 : 24, - prev_pn_127_48_info : 2, - reserved_3a : 6; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t release_source_module : 3, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_delink_error : 1, - sw_buffer_cookie : 20; - uint32_t msdu_link_desc_index : 4, - reserved_6a : 28; - uint32_t reo_dest_buffer_type : 1, - reo_push_reason : 2, - reo_error_code : 5, - captured_msdu_data_size : 4, - sw_exception : 1, - src_link_id : 3, - reo_destination_struct_signature : 4, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - uint32_t prev_pn_23_0 : 24, - msdu_count : 8; - uint32_t reserved_3a : 6, - prev_pn_127_48_info : 2, - prev_pn_47_24 : 24; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t sw_buffer_cookie : 20, - reo_delink_error : 1, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - release_source_module : 3; - uint32_t reserved_6a : 28, - msdu_link_desc_index : 4; - uint32_t looping_count : 4, - ring_id : 8, - reo_destination_struct_signature : 4, - src_link_id : 3, - sw_exception : 1, - captured_msdu_data_size : 4, - reo_error_code : 5, - reo_push_reason : 2, - reo_dest_buffer_type : 1; -#endif -}; - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00 - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MSB 23 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MASK 0x00ffffff - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_LSB 24 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MSB 25 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MASK 0x03000000 - -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_LSB 26 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MASK 0xfc000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MSB 3 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MASK 0x00000008 - -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_LSB 4 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MSB 5 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MASK 0x00000030 - -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_LSB 6 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MSB 10 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MASK 0x000007c0 - -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_LSB 11 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MASK 0x00000800 - -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MSB 3 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MASK 0x0000000f - -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_OFFSET 0x00000018 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_LSB 4 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MASK 0xfffffff0 - -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0 -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001 - -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1 -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006 - -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8 - -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 - -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000 - -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13 -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15 -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000 - -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 - -#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20 -#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27 -#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000 - -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28 -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/reo_entrance_ring.h b/drivers/staging/fw-api/hw/fig/v2/reo_entrance_ring.h deleted file mode 100644 index 17a68d08ce25..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/reo_entrance_ring.h +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_ENTRANCE_RING_H_ -#define _REO_ENTRANCE_RING_H_ - -#include "rx_mpdu_details.h" -#define NUM_OF_DWORDS_REO_ENTRANCE_RING 12 - -struct reo_entrance_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_mpdu_details reo_level_mpdu_frame_info; - uint32_t rx_preamble_timestamp : 32; - uint32_t reserved_7a : 8, - rounded_mpdu_byte_count : 14, - reo_destination_indication : 5, - frameless_bar : 1, - reserved_7b : 4; - uint32_t rxdma_push_reason : 2, - rxdma_error_code : 5, - mpdu_fragment_number : 4, - sw_exception : 1, - sw_exception_mpdu_delink : 1, - sw_exception_destination_ring_valid : 1, - sw_exception_destination_ring : 5, - mpdu_sequence_number : 12, - no_ack : 1; - uint32_t phy_ppdu_id : 16, - src_link_id : 3, - reserved_9a : 5, - rx_reo_queue_desc_addr_39_32 : 8; - uint32_t receive_queue_number : 16, - fw_reorder_push_reason : 2, - fw_reorder_error_code : 5, - reo_bypass : 1, - reserved_10a : 8; - uint32_t phy_lmac_latency : 16, - reserved_15a : 4, - ring_id : 8, - looping_count : 4; -#else - struct rx_mpdu_details reo_level_mpdu_frame_info; - uint32_t rx_preamble_timestamp : 32; - uint32_t reserved_7b : 4, - frameless_bar : 1, - reo_destination_indication : 5, - rounded_mpdu_byte_count : 14, - reserved_7a : 8; - uint32_t no_ack : 1, - mpdu_sequence_number : 12, - sw_exception_destination_ring : 5, - sw_exception_destination_ring_valid : 1, - sw_exception_mpdu_delink : 1, - sw_exception : 1, - mpdu_fragment_number : 4, - rxdma_error_code : 5, - rxdma_push_reason : 2; - uint32_t rx_reo_queue_desc_addr_39_32 : 8, - reserved_9a : 5, - src_link_id : 3, - phy_ppdu_id : 16; - uint32_t reserved_10a : 8, - reo_bypass : 1, - fw_reorder_error_code : 5, - fw_reorder_push_reason : 2, - receive_queue_number : 16; - uint32_t looping_count : 4, - ring_id : 8, - reserved_15a : 4, - phy_lmac_latency : 16; -#endif -}; - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000 - -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_OFFSET 0x00000018 -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_LSB 0 -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MSB 31 -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_RESERVED_7A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_7A_MSB 7 -#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x000000ff - -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 - -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 - -#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 -#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 -#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 - -#define REO_ENTRANCE_RING_RESERVED_7B_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_RESERVED_7B_LSB 28 -#define REO_ENTRANCE_RING_RESERVED_7B_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_7B_MASK 0xf0000000 - -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 - -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c - -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 - -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 - -#define REO_ENTRANCE_RING_NO_ACK_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_NO_ACK_LSB 31 -#define REO_ENTRANCE_RING_NO_ACK_MSB 31 -#define REO_ENTRANCE_RING_NO_ACK_MASK 0x80000000 - -#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 -#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 -#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 - -#define REO_ENTRANCE_RING_RESERVED_9A_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_RESERVED_9A_LSB 19 -#define REO_ENTRANCE_RING_RESERVED_9A_MSB 23 -#define REO_ENTRANCE_RING_RESERVED_9A_MASK 0x00f80000 - -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 24 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 31 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0xff000000 - -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_LSB 0 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MSB 15 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_LSB 16 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MSB 17 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MASK 0x00030000 - -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_LSB 18 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MSB 22 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MASK 0x007c0000 - -#define REO_ENTRANCE_RING_REO_BYPASS_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_REO_BYPASS_LSB 23 -#define REO_ENTRANCE_RING_REO_BYPASS_MSB 23 -#define REO_ENTRANCE_RING_REO_BYPASS_MASK 0x00800000 - -#define REO_ENTRANCE_RING_RESERVED_10A_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_RESERVED_10A_LSB 24 -#define REO_ENTRANCE_RING_RESERVED_10A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_10A_MASK 0xff000000 - -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_LSB 0 -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MSB 15 -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_RESERVED_15A_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_RESERVED_15A_LSB 16 -#define REO_ENTRANCE_RING_RESERVED_15A_MSB 19 -#define REO_ENTRANCE_RING_RESERVED_15A_MASK 0x000f0000 - -#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_RING_ID_LSB 20 -#define REO_ENTRANCE_RING_RING_ID_MSB 27 -#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 - -#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 -#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 -#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/response_end_status.h b/drivers/staging/fw-api/hw/fig/v2/response_end_status.h deleted file mode 100644 index a5dda1fec669..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/response_end_status.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RESPONSE_END_STATUS_H_ -#define _RESPONSE_END_STATUS_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10 - -#define NUM_OF_QWORDS_RESPONSE_END_STATUS 5 - -struct response_end_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0072 : 1, - __reserved_g_0065 : 1, - __reserved_g_0062 : 1, - global_data_underflow_warning : 1, - response_transmit_status : 4, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - generated_response : 3, - mba_user_count : 7, - mba_fake_bitmap_count : 7, - coex_based_tx_bw : 3, - trig_response_related : 1, - __reserved_g_0035 : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t cbf_segment_request_mask : 8, - cbf_segment_sent_mask : 8; - uint32_t underflow_mpdu_count : 9, - data_underflow_warning : 2, - reserved_2b : 10, - only_null_delim_sent : 1, - brp_info_valid : 1, - __reserved_g_0067 : 1, - __reserved_g_0069 : 1, - __reserved_g_0051 : 1, - __reserved_g_0049 : 1, - __reserved_g_0047 : 1, - __reserved_g_0045 : 1, - __reserved_g_0043 : 1, - __reserved_g_0041 : 1, - __reserved_g_0030 : 1; - uint32_t mu_response_bitmap_31_0 : 32; - uint32_t mu_response_bitmap_36_32 : 5, - overwritten_blackout_window_bitmap : 4, - mic_overwritten : 1, - trig_resp_cmd_found : 1, - reserved_4a : 21; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t addr3_47_32 : 16, - __reserved_g_0022 : 1, - secure : 1, - __reserved_g_0022_ftm_frame_sent : 1, - reserved_20a : 13; -#else - uint32_t __reserved_g_0035 : 1, - trig_response_related : 1, - coex_based_tx_bw : 3, - mba_fake_bitmap_count : 7, - mba_user_count : 7, - generated_response : 3, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - response_transmit_status : 4, - global_data_underflow_warning : 1, - __reserved_g_0062 : 1, - __reserved_g_0065 : 1, - __reserved_g_0072 : 1; - uint32_t cbf_segment_sent_mask : 8, - cbf_segment_request_mask : 8; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t __reserved_g_0030 : 1, - __reserved_g_0041 : 1, - __reserved_g_0043 : 1, - __reserved_g_0045 : 1, - __reserved_g_0047 : 1, - __reserved_g_0049 : 1, - __reserved_g_0051 : 1, - __reserved_g_0069 : 1, - __reserved_g_0067 : 1, - brp_info_valid : 1, - only_null_delim_sent : 1, - reserved_2b : 10, - data_underflow_warning : 2, - underflow_mpdu_count : 9; - uint32_t mu_response_bitmap_31_0 : 32; - uint32_t reserved_4a : 21, - trig_resp_cmd_found : 1, - mic_overwritten : 1, - overwritten_blackout_window_bitmap : 4, - mu_response_bitmap_36_32 : 5; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t reserved_20a : 13, - __reserved_g_0022_ftm_frame_sent : 1, - secure : 1, - __reserved_g_0022 : 1, - addr3_47_32 : 16; -#endif -}; - -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 - -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 - -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 - -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 - -#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 - -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 - -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 - -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 - -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 - -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff - -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 - -#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_RESERVED_2B_LSB 11 -#define RESPONSE_END_STATUS_RESERVED_2B_MSB 20 -#define RESPONSE_END_STATUS_RESERVED_2B_MASK 0x00000000001ff800 - -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 - -#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 - -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f - -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_LSB 5 -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MSB 8 -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MASK 0x00000000000001e0 - -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_LSB 9 -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MSB 9 -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MASK 0x0000000000000200 - -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_LSB 10 -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MSB 10 -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MASK 0x0000000000000400 - -#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_RESERVED_4A_LSB 11 -#define RESPONSE_END_STATUS_RESERVED_4A_MSB 31 -#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x00000000fffff800 - -#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 32 -#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 63 -#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 0 -#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 15 -#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x000000000000ffff - -#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 16 -#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 31 -#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0x00000000ffff0000 - -#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 32 -#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 63 -#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 0 -#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 31 -#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0x00000000ffffffff - -#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 32 -#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 47 -#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x0000ffff00000000 - -#define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_SECURE_LSB 49 -#define RESPONSE_END_STATUS_SECURE_MSB 49 -#define RESPONSE_END_STATUS_SECURE_MASK 0x0002000000000000 - -#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_RESERVED_20A_LSB 51 -#define RESPONSE_END_STATUS_RESERVED_20A_MSB 63 -#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0xfff8000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/response_start_status.h b/drivers/staging/fw-api/hw/fig/v2/response_start_status.h deleted file mode 100644 index 0a3090f219fe..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/response_start_status.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RESPONSE_START_STATUS_H_ -#define _RESPONSE_START_STATUS_H_ - -#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 - -#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 - -struct response_start_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t generated_response : 3, - __reserved_g_0012 : 2, - trig_response_related : 1, - response_sta_count : 7, - mba_for_cfp_ba : 1, - mba_for_cfp_ack : 1, - ects_response_type : 2, - eba_response_type : 2, - cfp_mba : 1, - mba_for_ll_ack : 1, - mba_for_ll_ba : 1, - reserved : 10; - uint32_t phy_ppdu_id : 16, - sw_peer_id : 16; -#else - uint32_t reserved : 10, - mba_for_ll_ba : 1, - mba_for_ll_ack : 1, - cfp_mba : 1, - eba_response_type : 2, - ects_response_type : 2, - mba_for_cfp_ack : 1, - mba_for_cfp_ba : 1, - response_sta_count : 7, - trig_response_related : 1, - __reserved_g_0012 : 2, - generated_response : 3; - uint32_t sw_peer_id : 16, - phy_ppdu_id : 16; -#endif -}; - -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 - -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 - -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 - -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_LSB 13 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_MSB 13 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_MASK 0x0000000000002000 - -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_LSB 14 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_MSB 14 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_MASK 0x0000000000004000 - -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_LSB 15 -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_MSB 16 -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_MASK 0x0000000000018000 - -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_LSB 17 -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_MSB 18 -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_MASK 0x0000000000060000 - -#define RESPONSE_START_STATUS_CFP_MBA_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_CFP_MBA_LSB 19 -#define RESPONSE_START_STATUS_CFP_MBA_MSB 19 -#define RESPONSE_START_STATUS_CFP_MBA_MASK 0x0000000000080000 - -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_LSB 20 -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_MSB 20 -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_MASK 0x0000000000100000 - -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_LSB 21 -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_MSB 21 -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_MASK 0x0000000000200000 - -#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_RESERVED_LSB 22 -#define RESPONSE_START_STATUS_RESERVED_MSB 31 -#define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffc00000 - -#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 - -#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 -#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 -#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/ru_allocation_160_info.h b/drivers/staging/fw-api/hw/fig/v2/ru_allocation_160_info.h deleted file mode 100644 index 57d51dc44f8a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/ru_allocation_160_info.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RU_ALLOCATION_160_INFO_H_ -#define _RU_ALLOCATION_160_INFO_H_ - -#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 - -struct ru_allocation_160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_allocation_band0_0 : 9, - ru_allocation_band0_1 : 9, - reserved_0a : 6, - ru_allocations_01_subband80_mask : 4, - ru_allocations_23_subband80_mask : 4; - uint32_t ru_allocation_band0_2 : 9, - ru_allocation_band0_3 : 9, - reserved_1a : 14; - uint32_t ru_allocation_band1_0 : 9, - ru_allocation_band1_1 : 9, - reserved_2a : 14; - uint32_t ru_allocation_band1_2 : 9, - ru_allocation_band1_3 : 9, - reserved_3a : 14; -#else - uint32_t ru_allocations_23_subband80_mask : 4, - ru_allocations_01_subband80_mask : 4, - reserved_0a : 6, - ru_allocation_band0_1 : 9, - ru_allocation_band0_0 : 9; - uint32_t reserved_1a : 14, - ru_allocation_band0_3 : 9, - ru_allocation_band0_2 : 9; - uint32_t reserved_2a : 14, - ru_allocation_band1_1 : 9, - ru_allocation_band1_0 : 9; - uint32_t reserved_3a : 14, - ru_allocation_band1_3 : 9, - ru_allocation_band1_2 : 9; -#endif -}; - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_attention.h b/drivers/staging/fw-api/hw/fig/v2/rx_attention.h deleted file mode 100644 index cac7c2fb52c3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_attention.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_ATTENTION_H_ -#define _RX_ATTENTION_H_ - -#define NUM_OF_DWORDS_RX_ATTENTION 4 - -#define NUM_OF_QWORDS_RX_ATTENTION 2 - -struct rx_attention { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t first_mpdu : 1, - reserved_1a : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - a_msdu_error : 1, - fragment_flag : 1, - order : 1, - cce_match : 1, - overflow_err : 1, - msdu_length_err : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - sa_idx_invalid : 1, - da_idx_invalid : 1, - reserved_1b : 1, - rx_in_tx_decrypt_byp : 1, - encrypt_required : 1, - directed : 1, - buffer_fragment : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - fcs_err : 1; - uint32_t flow_idx_timeout : 1, - flow_idx_invalid : 1, - wifi_parser_error : 1, - amsdu_parser_error : 1, - sa_idx_timeout : 1, - da_idx_timeout : 1, - msdu_limit_error : 1, - da_is_valid : 1, - da_is_mcbc : 1, - sa_is_valid : 1, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - reserved_2 : 17, - msdu_done : 1; - uint32_t tlv64_padding : 32; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t fcs_err : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - buffer_fragment : 1, - directed : 1, - encrypt_required : 1, - rx_in_tx_decrypt_byp : 1, - reserved_1b : 1, - da_idx_invalid : 1, - sa_idx_invalid : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - msdu_length_err : 1, - overflow_err : 1, - cce_match : 1, - order : 1, - fragment_flag : 1, - a_msdu_error : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - reserved_1a : 1, - first_mpdu : 1; - uint32_t msdu_done : 1, - reserved_2 : 17, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - sa_is_valid : 1, - da_is_mcbc : 1, - da_is_valid : 1, - msdu_limit_error : 1, - da_idx_timeout : 1, - sa_idx_timeout : 1, - amsdu_parser_error : 1, - wifi_parser_error : 1, - flow_idx_invalid : 1, - flow_idx_timeout : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_0_LSB 9 -#define RX_ATTENTION_RESERVED_0_MSB 15 -#define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_PHY_PPDU_ID_LSB 16 -#define RX_ATTENTION_PHY_PPDU_ID_MSB 31 -#define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FIRST_MPDU_LSB 32 -#define RX_ATTENTION_FIRST_MPDU_MSB 32 -#define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 - -#define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_1A_LSB 33 -#define RX_ATTENTION_RESERVED_1A_MSB 33 -#define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 - -#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MCAST_BCAST_LSB 34 -#define RX_ATTENTION_MCAST_BCAST_MSB 34 -#define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 - -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 - -#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 - -#define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_POWER_MGMT_LSB 37 -#define RX_ATTENTION_POWER_MGMT_MSB 37 -#define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 - -#define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 -#define RX_ATTENTION_NON_QOS_LSB 38 -#define RX_ATTENTION_NON_QOS_MSB 38 -#define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 - -#define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 -#define RX_ATTENTION_NULL_DATA_LSB 39 -#define RX_ATTENTION_NULL_DATA_MSB 39 -#define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 - -#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MGMT_TYPE_LSB 40 -#define RX_ATTENTION_MGMT_TYPE_MSB 40 -#define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 - -#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 -#define RX_ATTENTION_CTRL_TYPE_LSB 41 -#define RX_ATTENTION_CTRL_TYPE_MSB 41 -#define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 - -#define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MORE_DATA_LSB 42 -#define RX_ATTENTION_MORE_DATA_MSB 42 -#define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 - -#define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 -#define RX_ATTENTION_EOSP_LSB 43 -#define RX_ATTENTION_EOSP_MSB 43 -#define RX_ATTENTION_EOSP_MASK 0x0000080000000000 - -#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_A_MSDU_ERROR_LSB 44 -#define RX_ATTENTION_A_MSDU_ERROR_MSB 44 -#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 - -#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 -#define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 -#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 - -#define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 -#define RX_ATTENTION_ORDER_LSB 46 -#define RX_ATTENTION_ORDER_MSB 46 -#define RX_ATTENTION_ORDER_MASK 0x0000400000000000 - -#define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 -#define RX_ATTENTION_CCE_MATCH_LSB 47 -#define RX_ATTENTION_CCE_MATCH_MSB 47 -#define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 - -#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_OVERFLOW_ERR_LSB 48 -#define RX_ATTENTION_OVERFLOW_ERR_MSB 48 -#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 - -#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 -#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 -#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 - -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 - -#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 -#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 -#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 -#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 - -#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_SA_IDX_INVALID_LSB 52 -#define RX_ATTENTION_SA_IDX_INVALID_MSB 52 -#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 - -#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DA_IDX_INVALID_LSB 53 -#define RX_ATTENTION_DA_IDX_INVALID_MSB 53 -#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 - -#define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_1B_LSB 54 -#define RX_ATTENTION_RESERVED_1B_MSB 54 -#define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 - -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 - -#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 -#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 -#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 -#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 - -#define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DIRECTED_LSB 57 -#define RX_ATTENTION_DIRECTED_MSB 57 -#define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 - -#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 -#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 -#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 - -#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 -#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 -#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 - -#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 -#define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 -#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 - -#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DECRYPT_ERR_LSB 61 -#define RX_ATTENTION_DECRYPT_ERR_MSB 61 -#define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 - -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 - -#define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FCS_ERR_LSB 63 -#define RX_ATTENTION_FCS_ERR_MSB 63 -#define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 - -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 - -#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 -#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 -#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 - -#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 -#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 -#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 - -#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 - -#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 -#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 -#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 - -#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 -#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 -#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 - -#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 - -#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IS_VALID_LSB 7 -#define RX_ATTENTION_DA_IS_VALID_MSB 7 -#define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 - -#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IS_MCBC_LSB 8 -#define RX_ATTENTION_DA_IS_MCBC_MSB 8 -#define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 - -#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_SA_IS_VALID_LSB 9 -#define RX_ATTENTION_SA_IS_VALID_MSB 9 -#define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 - -#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 - -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 - -#define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 -#define RX_ATTENTION_RESERVED_2_LSB 14 -#define RX_ATTENTION_RESERVED_2_MSB 30 -#define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 - -#define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 -#define RX_ATTENTION_MSDU_DONE_LSB 31 -#define RX_ATTENTION_MSDU_DONE_MSB 31 -#define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 - -#define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 -#define RX_ATTENTION_TLV64_PADDING_LSB 32 -#define RX_ATTENTION_TLV64_PADDING_MSB 63 -#define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/fig/v2/rx_flow_search_entry.h deleted file mode 100644 index 25f1f81c439f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_flow_search_entry.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FLOW_SEARCH_ENTRY_H_ -#define _RX_FLOW_SEARCH_ENTRY_H_ - -#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 - -struct rx_flow_search_entry { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t src_ip_127_96 : 32; - uint32_t src_ip_95_64 : 32; - uint32_t src_ip_63_32 : 32; - uint32_t src_ip_31_0 : 32; - uint32_t dest_ip_127_96 : 32; - uint32_t dest_ip_95_64 : 32; - uint32_t dest_ip_63_32 : 32; - uint32_t dest_ip_31_0 : 32; - uint32_t src_port : 16, - dest_port : 16; - uint32_t l4_protocol : 8, - valid : 1, - reserved_9 : 4, - service_code : 9, - priority_valid : 1, - use_ppe : 1, - reo_destination_indication : 5, - msdu_drop : 1, - reo_destination_handler : 2; - uint32_t metadata : 32; - uint32_t aggregation_count : 7, - lro_eligible : 1, - msdu_count : 24; - uint32_t msdu_byte_count : 32; - uint32_t timestamp : 32; - uint32_t cumulative_ip_length_pmac1 : 16, - cumulative_ip_length : 16; - uint32_t tcp_sequence_number : 32; -#else - uint32_t src_ip_127_96 : 32; - uint32_t src_ip_95_64 : 32; - uint32_t src_ip_63_32 : 32; - uint32_t src_ip_31_0 : 32; - uint32_t dest_ip_127_96 : 32; - uint32_t dest_ip_95_64 : 32; - uint32_t dest_ip_63_32 : 32; - uint32_t dest_ip_31_0 : 32; - uint32_t dest_port : 16, - src_port : 16; - uint32_t reo_destination_handler : 2, - msdu_drop : 1, - reo_destination_indication : 5, - use_ppe : 1, - priority_valid : 1, - service_code : 9, - reserved_9 : 4, - valid : 1, - l4_protocol : 8; - uint32_t metadata : 32; - uint32_t msdu_count : 24, - lro_eligible : 1, - aggregation_count : 7; - uint32_t msdu_byte_count : 32; - uint32_t timestamp : 32; - uint32_t cumulative_ip_length : 16, - cumulative_ip_length_pmac1 : 16; - uint32_t tcp_sequence_number : 32; -#endif -}; - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 - -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff - -#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 -#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 -#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 - -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 - -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 - -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 - -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 - -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 - -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 - -#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 -#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f - -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff - -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 - -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_frame_1k_bitmap_ack.h b/drivers/staging/fw-api/hw/fig/v2/rx_frame_1k_bitmap_ack.h deleted file mode 100644 index a43548b14a07..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_frame_1k_bitmap_ack.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ -#define _RX_FRAME_1K_BITMAP_ACK_H_ - -#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 - -#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 - -struct rx_frame_1k_bitmap_ack { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 5, - ba_bitmap_size : 2, - gen_mlo_notification : 1, - reserved_0b : 2, - ba_tid : 4, - sta_full_aid : 13, - reserved_0c : 5; - uint32_t mlo_sta_id : 10, - ba_size_1024_allowed : 1, - ba_size_512_allowed : 1, - reserved_1a : 20; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_ctrl : 16, - ba_ts_seq : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; - uint32_t ba_ts_bitmap_287_256 : 32; - uint32_t ba_ts_bitmap_319_288 : 32; - uint32_t ba_ts_bitmap_351_320 : 32; - uint32_t ba_ts_bitmap_383_352 : 32; - uint32_t ba_ts_bitmap_415_384 : 32; - uint32_t ba_ts_bitmap_447_416 : 32; - uint32_t ba_ts_bitmap_479_448 : 32; - uint32_t ba_ts_bitmap_511_480 : 32; - uint32_t ba_ts_bitmap_543_512 : 32; - uint32_t ba_ts_bitmap_575_544 : 32; - uint32_t ba_ts_bitmap_607_576 : 32; - uint32_t ba_ts_bitmap_639_608 : 32; - uint32_t ba_ts_bitmap_671_640 : 32; - uint32_t ba_ts_bitmap_703_672 : 32; - uint32_t ba_ts_bitmap_735_704 : 32; - uint32_t ba_ts_bitmap_767_736 : 32; - uint32_t ba_ts_bitmap_799_768 : 32; - uint32_t ba_ts_bitmap_831_800 : 32; - uint32_t ba_ts_bitmap_863_832 : 32; - uint32_t ba_ts_bitmap_895_864 : 32; - uint32_t ba_ts_bitmap_927_896 : 32; - uint32_t ba_ts_bitmap_959_928 : 32; - uint32_t ba_ts_bitmap_991_960 : 32; - uint32_t ba_ts_bitmap_1023_992 : 32; -#else - uint32_t reserved_0c : 5, - sta_full_aid : 13, - ba_tid : 4, - reserved_0b : 2, - gen_mlo_notification : 1, - ba_bitmap_size : 2, - reserved_0a : 5; - uint32_t reserved_1a : 20, - ba_size_512_allowed : 1, - ba_size_1024_allowed : 1, - mlo_sta_id : 10; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_seq : 16, - ba_ts_ctrl : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; - uint32_t ba_ts_bitmap_287_256 : 32; - uint32_t ba_ts_bitmap_319_288 : 32; - uint32_t ba_ts_bitmap_351_320 : 32; - uint32_t ba_ts_bitmap_383_352 : 32; - uint32_t ba_ts_bitmap_415_384 : 32; - uint32_t ba_ts_bitmap_447_416 : 32; - uint32_t ba_ts_bitmap_479_448 : 32; - uint32_t ba_ts_bitmap_511_480 : 32; - uint32_t ba_ts_bitmap_543_512 : 32; - uint32_t ba_ts_bitmap_575_544 : 32; - uint32_t ba_ts_bitmap_607_576 : 32; - uint32_t ba_ts_bitmap_639_608 : 32; - uint32_t ba_ts_bitmap_671_640 : 32; - uint32_t ba_ts_bitmap_703_672 : 32; - uint32_t ba_ts_bitmap_735_704 : 32; - uint32_t ba_ts_bitmap_767_736 : 32; - uint32_t ba_ts_bitmap_799_768 : 32; - uint32_t ba_ts_bitmap_831_800 : 32; - uint32_t ba_ts_bitmap_863_832 : 32; - uint32_t ba_ts_bitmap_895_864 : 32; - uint32_t ba_ts_bitmap_927_896 : 32; - uint32_t ba_ts_bitmap_959_928 : 32; - uint32_t ba_ts_bitmap_991_960 : 32; - uint32_t ba_ts_bitmap_1023_992 : 32; -#endif -}; - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f - -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 - -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB 7 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB 7 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK 0x0000000000000080 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 8 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000300 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 - -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 - -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MSB 41 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MASK 0x000003ff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB 42 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB 42 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK 0x0000040000000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB 43 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB 43 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK 0x0000080000000000 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_LSB 44 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MASK 0xfffff00000000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 47 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 48 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 47 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 48 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff000000000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000020 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000028 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000030 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000038 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000040 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000048 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000050 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000058 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000060 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000068 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000070 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000078 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000080 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000088 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000090 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_ack.h b/drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_ack.h deleted file mode 100644 index 0b68486b038e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_ack.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_BITMAP_ACK_H_ -#define _RX_FRAME_BITMAP_ACK_H_ - -#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 - -#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 - -struct rx_frame_bitmap_ack { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t no_bitmap_available : 1, - explicit_ack : 1, - explict_ack_type : 3, - ba_bitmap_size : 2, - gen_mlo_notification : 1, - reserved_0a : 2, - ba_tid : 4, - sta_full_aid : 13, - reserved_0b : 5; - uint32_t mlo_sta_id : 10, - ba_size_1024_allowed : 1, - ba_size_512_allowed : 1, - ba_size_256_allowed : 1, - ba_size_128_allowed : 1, - ba_size_64_allowed : 1, - ba_size_32_allowed : 1, - reserved_1a : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_ctrl : 16, - ba_ts_seq : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; -#else - uint32_t reserved_0b : 5, - sta_full_aid : 13, - ba_tid : 4, - reserved_0a : 2, - gen_mlo_notification : 1, - ba_bitmap_size : 2, - explict_ack_type : 3, - explicit_ack : 1, - no_bitmap_available : 1; - uint32_t reserved_1a : 16, - ba_size_32_allowed : 1, - ba_size_64_allowed : 1, - ba_size_128_allowed : 1, - ba_size_256_allowed : 1, - ba_size_512_allowed : 1, - ba_size_1024_allowed : 1, - mlo_sta_id : 10; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_seq : 16, - ba_ts_ctrl : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; -#endif -}; - -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 - -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 - -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c - -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 - -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB 7 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB 7 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK 0x0000000000000080 - -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 8 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000300 - -#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 -#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 -#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 - -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 - -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 - -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_LSB 32 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MSB 41 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MASK 0x000003ff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB 42 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB 42 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK 0x0000040000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB 43 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB 43 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK 0x0000080000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_LSB 44 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MSB 44 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MASK 0x0000100000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_LSB 45 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MSB 45 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MASK 0x0000200000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_LSB 46 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MSB 46 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MASK 0x0000400000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_LSB 47 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MSB 47 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MASK 0x0000800000000000 - -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_LSB 48 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MSB 63 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 0 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 31 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 32 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 47 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 48 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 63 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 0 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 31 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 47 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 48 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000020 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000028 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000030 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_req.h b/drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_req.h deleted file mode 100644 index 24f8ddd1c57c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_req.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_BITMAP_REQ_H_ -#define _RX_FRAME_BITMAP_REQ_H_ - -#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2 - -#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1 - -struct rx_frame_bitmap_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t explicit_user_request : 1, - user_request_type : 1, - user_number : 6, - sw_peer_id : 16, - tid_specific_request : 1, - requested_tid : 4, - reserved_0 : 3; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0 : 3, - requested_tid : 4, - tid_specific_request : 1, - sw_peer_id : 16, - user_number : 6, - user_request_type : 1, - explicit_user_request : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x0000000000000001 - -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x0000000000000002 - -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x00000000000000fc - -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x0000000000ffff00 - -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x0000000001000000 - -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x000000001e000000 - -#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0x00000000e0000000 - -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB 32 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB 63 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_location_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_location_info.h deleted file mode 100644 index ee000f6d4cda..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_location_info.h +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_LOCATION_INFO_H_ -#define _RX_LOCATION_INFO_H_ - -#define NUM_OF_DWORDS_RX_LOCATION_INFO 28 - -struct rx_location_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_location_info_valid : 1, - rtt_hw_ifft_mode : 1, - rtt___reserved_g_0020_mode : 2, - reserved_0 : 4, - rtt_num_fac : 8, - rtt_rx_chain_mask : 8, - rtt_num_streams : 8; - uint32_t rtt_first_selected_chain : 8, - rtt_second_selected_chain : 8, - rtt_cfr_status : 8, - rtt_cir_status : 8; - uint32_t rtt_che_buffer_pointer_low32 : 32; - uint32_t rtt_che_buffer_pointer_high8 : 8, - reserved_3 : 8, - rtt_pkt_bw_vht : 4, - rtt_pkt_bw_leg : 4, - rtt_mcs_rate : 8; - uint32_t rtt_cfo_measurement : 16, - rtt_preamble_type : 8, - rtt_gi_type : 8; - uint32_t rx_start_ts : 32; - uint32_t rx_start_ts_upper : 32; - uint32_t rx_end_ts : 32; - uint32_t gain_chain0 : 16, - gain_chain1 : 16; - uint32_t gain_chain2 : 16, - gain_chain3 : 16; - uint32_t gain_report_status : 8, - rtt_timing_backoff_sel : 8, - rtt_fac_combined : 16; - uint32_t rtt_fac_0 : 16, - rtt_fac_1 : 16; - uint32_t rtt_fac_2 : 16, - rtt_fac_3 : 16; - uint32_t rtt_fac_4 : 16, - rtt_fac_5 : 16; - uint32_t rtt_fac_6 : 16, - rtt_fac_7 : 16; - uint32_t rtt_fac_8 : 16, - rtt_fac_9 : 16; - uint32_t rtt_fac_10 : 16, - rtt_fac_11 : 16; - uint32_t rtt_fac_12 : 16, - rtt_fac_13 : 16; - uint32_t rtt_fac_14 : 16, - rtt_fac_15 : 16; - uint32_t rtt_fac_16 : 16, - rtt_fac_17 : 16; - uint32_t rtt_fac_18 : 16, - rtt_fac_19 : 16; - uint32_t rtt_fac_20 : 16, - rtt_fac_21 : 16; - uint32_t rtt_fac_22 : 16, - rtt_fac_23 : 16; - uint32_t rtt_fac_24 : 16, - rtt_fac_25 : 16; - uint32_t rtt_fac_26 : 16, - rtt_fac_27 : 16; - uint32_t rtt_fac_28 : 16, - rtt_fac_29 : 16; - uint32_t rtt_fac_30 : 16, - rtt_fac_31 : 16; - uint32_t reserved_27a : 32; -#else - uint32_t rtt_num_streams : 8, - rtt_rx_chain_mask : 8, - rtt_num_fac : 8, - reserved_0 : 4, - rtt___reserved_g_0020_mode : 2, - rtt_hw_ifft_mode : 1, - rx_location_info_valid : 1; - uint32_t rtt_cir_status : 8, - rtt_cfr_status : 8, - rtt_second_selected_chain : 8, - rtt_first_selected_chain : 8; - uint32_t rtt_che_buffer_pointer_low32 : 32; - uint32_t rtt_mcs_rate : 8, - rtt_pkt_bw_leg : 4, - rtt_pkt_bw_vht : 4, - reserved_3 : 8, - rtt_che_buffer_pointer_high8 : 8; - uint32_t rtt_gi_type : 8, - rtt_preamble_type : 8, - rtt_cfo_measurement : 16; - uint32_t rx_start_ts : 32; - uint32_t rx_start_ts_upper : 32; - uint32_t rx_end_ts : 32; - uint32_t gain_chain1 : 16, - gain_chain0 : 16; - uint32_t gain_chain3 : 16, - gain_chain2 : 16; - uint32_t rtt_fac_combined : 16, - rtt_timing_backoff_sel : 8, - gain_report_status : 8; - uint32_t rtt_fac_1 : 16, - rtt_fac_0 : 16; - uint32_t rtt_fac_3 : 16, - rtt_fac_2 : 16; - uint32_t rtt_fac_5 : 16, - rtt_fac_4 : 16; - uint32_t rtt_fac_7 : 16, - rtt_fac_6 : 16; - uint32_t rtt_fac_9 : 16, - rtt_fac_8 : 16; - uint32_t rtt_fac_11 : 16, - rtt_fac_10 : 16; - uint32_t rtt_fac_13 : 16, - rtt_fac_12 : 16; - uint32_t rtt_fac_15 : 16, - rtt_fac_14 : 16; - uint32_t rtt_fac_17 : 16, - rtt_fac_16 : 16; - uint32_t rtt_fac_19 : 16, - rtt_fac_18 : 16; - uint32_t rtt_fac_21 : 16, - rtt_fac_20 : 16; - uint32_t rtt_fac_23 : 16, - rtt_fac_22 : 16; - uint32_t rtt_fac_25 : 16, - rtt_fac_24 : 16; - uint32_t rtt_fac_27 : 16, - rtt_fac_26 : 16; - uint32_t rtt_fac_29 : 16, - rtt_fac_28 : 16; - uint32_t rtt_fac_31 : 16, - rtt_fac_30 : 16; - uint32_t reserved_27a : 32; -#endif -}; - -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001 - -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002 - -#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RESERVED_0_LSB 4 -#define RX_LOCATION_INFO_RESERVED_0_MSB 7 -#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0 - -#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8 -#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15 -#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff - -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff - -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff - -#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RESERVED_3_LSB 8 -#define RX_LOCATION_INFO_RESERVED_3_MSB 15 -#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16 -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19 -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000 - -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20 -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23 -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000 - -#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24 -#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31 -#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24 -#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31 -#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000 - -#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014 -#define RX_LOCATION_INFO_RX_START_TS_LSB 0 -#define RX_LOCATION_INFO_RX_START_TS_MSB 31 -#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff - -#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff - -#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c -#define RX_LOCATION_INFO_RX_END_TS_LSB 0 -#define RX_LOCATION_INFO_RX_END_TS_MSB 31 -#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff - -#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020 -#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0 -#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15 -#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff - -#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020 -#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16 -#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31 -#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000 - -#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024 -#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0 -#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15 -#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff - -#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024 -#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16 -#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31 -#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000 - -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff - -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c -#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c -#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030 -#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030 -#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034 -#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034 -#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038 -#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038 -#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c -#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c -#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040 -#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040 -#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044 -#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044 -#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048 -#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048 -#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c -#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c -#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050 -#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050 -#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054 -#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054 -#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058 -#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058 -#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c -#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c -#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060 -#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060 -#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064 -#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064 -#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068 -#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068 -#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c -#define RX_LOCATION_INFO_RESERVED_27A_LSB 0 -#define RX_LOCATION_INFO_RESERVED_27A_MSB 31 -#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_desc_info.h deleted file mode 100644 index 30f538fb1228..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_desc_info.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_DESC_INFO_H_ -#define _RX_MPDU_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 - -struct rx_mpdu_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t msdu_count : 8, - fragment_flag : 1, - mpdu_retry_bit : 1, - ampdu_flag : 1, - bar_frame : 1, - pn_fields_contain_valid_info : 1, - raw_mpdu : 1, - more_fragment_flag : 1, - src_info : 12, - mpdu_qos_control_valid : 1, - tid : 4; - uint32_t peer_meta_data : 32; -#else - uint32_t tid : 4, - mpdu_qos_control_valid : 1, - src_info : 12, - more_fragment_flag : 1, - raw_mpdu : 1, - pn_fields_contain_valid_info : 1, - bar_frame : 1, - ampdu_flag : 1, - mpdu_retry_bit : 1, - fragment_flag : 1, - msdu_count : 8; - uint32_t peer_meta_data : 32; -#endif -}; - -#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff - -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 - -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 - -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 - -#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 -#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 -#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 - -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 -#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 -#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 - -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 -#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 -#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 - -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_TID_LSB 28 -#define RX_MPDU_DESC_INFO_TID_MSB 31 -#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 - -#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_details.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_details.h deleted file mode 100644 index d2d96a0a9996..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_details.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_DETAILS_H_ -#define _RX_MPDU_DETAILS_H_ - -#include "rx_mpdu_ext_desc_info.h" -#include "rx_mpdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MPDU_DETAILS 6 - -struct rx_mpdu_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info msdu_link_desc_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_mpdu_ext_desc_info rx_mpdu_ext_desc_info_details; -#else - struct buffer_addr_info msdu_link_desc_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_mpdu_ext_desc_info rx_mpdu_ext_desc_info_details; -#endif -}; - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000 - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_end.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_end.h deleted file mode 100644 index dc54ea129fdd..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_end.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_END_H_ -#define _RX_MPDU_END_H_ - -#define NUM_OF_DWORDS_RX_MPDU_END 4 - -#define NUM_OF_QWORDS_RX_MPDU_END 2 - -struct rx_mpdu_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t reserved_1a : 9, - cfp_mic_err : 1, - cfp_pn_chk_err : 1, - unsup_ktype_short_frame : 1, - rx_in_tx_decrypt_byp : 1, - overflow_err : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - pn_fields_contain_valid_info : 1, - fcs_err : 1, - msdu_length_err : 1, - reserved1c : 6, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - ifcs_present : 1; - uint32_t mpdu_crc_ok_intermediate_fcs : 1, - mpdu_length_intermediate_fcs : 14, - rxpcu_mgmt_sequence_nr_valid : 1, - rxpcu_mgmt_sequence_nr : 16; - uint32_t __reserved_g_0002 : 32; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t ifcs_present : 1, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - reserved1c : 6, - msdu_length_err : 1, - fcs_err : 1, - pn_fields_contain_valid_info : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - overflow_err : 1, - rx_in_tx_decrypt_byp : 1, - unsup_ktype_short_frame : 1, - cfp_pn_chk_err : 1, - cfp_mic_err : 1, - reserved_1a : 9; - uint32_t rxpcu_mgmt_sequence_nr : 16, - rxpcu_mgmt_sequence_nr_valid : 1, - mpdu_length_intermediate_fcs : 14, - mpdu_crc_ok_intermediate_fcs : 1; - uint32_t __reserved_g_0002 : 32; -#endif -}; - -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_0_LSB 9 -#define RX_MPDU_END_RESERVED_0_MSB 15 -#define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MPDU_END_PHY_PPDU_ID_LSB 16 -#define RX_MPDU_END_PHY_PPDU_ID_MSB 31 -#define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_1A_LSB 32 -#define RX_MPDU_END_RESERVED_1A_MSB 40 -#define RX_MPDU_END_RESERVED_1A_MASK 0x000001ff00000000 - -#define RX_MPDU_END_CFP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_CFP_MIC_ERR_LSB 41 -#define RX_MPDU_END_CFP_MIC_ERR_MSB 41 -#define RX_MPDU_END_CFP_MIC_ERR_MASK 0x0000020000000000 - -#define RX_MPDU_END_CFP_PN_CHK_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_CFP_PN_CHK_ERR_LSB 42 -#define RX_MPDU_END_CFP_PN_CHK_ERR_MSB 42 -#define RX_MPDU_END_CFP_PN_CHK_ERR_MASK 0x0000040000000000 - -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 - -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 - -#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_OVERFLOW_ERR_LSB 45 -#define RX_MPDU_END_OVERFLOW_ERR_MSB 45 -#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 - -#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 -#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 -#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 - -#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 -#define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 -#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 - -#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_DECRYPT_ERR_LSB 48 -#define RX_MPDU_END_DECRYPT_ERR_MSB 48 -#define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 - -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 - -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 - -#define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_FCS_ERR_LSB 51 -#define RX_MPDU_END_FCS_ERR_MSB 51 -#define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 - -#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 -#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 -#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 - -#define RX_MPDU_END_RESERVED1C_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED1C_LSB 53 -#define RX_MPDU_END_RESERVED1C_MSB 58 -#define RX_MPDU_END_RESERVED1C_MASK 0x07e0000000000000 - -#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 - -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 - -#define RX_MPDU_END_IFCS_PRESENT_OFFSET 0x0000000000000000 -#define RX_MPDU_END_IFCS_PRESENT_LSB 63 -#define RX_MPDU_END_IFCS_PRESENT_MSB 63 -#define RX_MPDU_END_IFCS_PRESENT_MASK 0x8000000000000000 - -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_OFFSET 0x0000000000000008 -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_LSB 0 -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_MSB 0 -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_MASK 0x0000000000000001 - -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_OFFSET 0x0000000000000008 -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_LSB 1 -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_MSB 14 -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_MASK 0x0000000000007ffe - -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 - -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_ext_desc_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_ext_desc_info.h deleted file mode 100644 index 83f4df333c88..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_ext_desc_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_EXT_DESC_INFO_H_ -#define _RX_MPDU_EXT_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MPDU_EXT_DESC_INFO 2 - -struct rx_mpdu_ext_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pn_31_0 : 32; - uint32_t pn_47_32 : 16, - pn_127_48_info : 2, - msdu_link_desc_index : 4, - reserved_1a : 10; -#else - uint32_t pn_31_0 : 32; - uint32_t reserved_1a : 10, - msdu_link_desc_index : 4, - pn_127_48_info : 2, - pn_47_32 : 16; -#endif -}; - -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_OFFSET 0x00000000 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_LSB 0 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MSB 31 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_LSB 0 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MSB 15 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MASK 0x0000ffff - -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_LSB 16 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MSB 17 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MASK 0x00030000 - -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_LSB 18 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MSB 21 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_LSB 22 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MSB 31 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_info.h deleted file mode 100644 index 7a3e9a8d525a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_info.h +++ /dev/null @@ -1,972 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_INFO_H_ -#define _RX_MPDU_INFO_H_ - -#include "rxpt_classify_info.h" -#define NUM_OF_DWORDS_RX_MPDU_INFO 30 - -struct rx_mpdu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rxpt_classify_info rxpt_classify_info_details; - uint32_t epd_en : 1, - all_frames_shall_be_encrypted : 1, - encrypt_type : 4, - wep_key_width_for_variable_key : 2, - __reserved_g_0003 : 2, - bssid_hit : 1, - bssid_number : 4, - tid : 4, - reserved_7a : 13; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t rx_reo_queue_desc_addr_39_32 : 8, - receive_queue_number : 16, - pre_delim_err_warning : 1, - first_delim_err : 1, - reserved_2a : 6; - uint32_t pn_31_0 : 32; - uint32_t pn_63_32 : 32; - uint32_t pn_95_64 : 32; - uint32_t pn_127_96 : 32; - uint32_t mpdu_frame_control_valid : 1, - mpdu_duration_valid : 1, - mac_addr_ad1_valid : 1, - mac_addr_ad2_valid : 1, - mac_addr_ad3_valid : 1, - mac_addr_ad4_valid : 1, - mpdu_sequence_control_valid : 1, - mpdu_qos_control_valid : 1, - mpdu_ht_control_valid : 1, - frame_encryption_info_valid : 1, - mpdu_fragment_number : 4, - more_fragment_flag : 1, - protected_cbf_cqi : 1, - fr_ds : 1, - to_ds : 1, - encrypted : 1, - mpdu_retry : 1, - mpdu_sequence_number : 12; - uint32_t peer_meta_data : 32; - uint32_t ast_index : 16, - sw_peer_id : 16; - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - ndp_frame : 1, - phy_err : 1, - phy_err_during_mpdu_header : 1, - protocol_version_err : 1, - ast_based_lookup_valid : 1, - __reserved_g_0022 : 1, - __reserved_g_0035 : 1, - phy_ppdu_id : 16; - uint32_t key_id_octet : 8, - new_peer_entry : 1, - decrypt_needed : 1, - decap_type : 2, - rx_insert_vlan_c_tag_padding : 1, - rx_insert_vlan_s_tag_padding : 1, - strip_vlan_c_tag_decap : 1, - strip_vlan_s_tag_decap : 1, - pre_delim_count : 12, - ampdu_flag : 1, - bar_frame : 1, - raw_mpdu : 1, - reserved_12 : 1; - uint32_t mpdu_length : 14, - first_mpdu : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - fragment_flag : 1, - order : 1, - u_apsd_trigger : 1, - encrypt_required : 1, - directed : 1, - amsdu_present : 1, - reserved_13 : 1; - uint32_t mpdu_frame_control_field : 16, - mpdu_duration_field : 16; - uint32_t mac_addr_ad1_31_0 : 32; - uint32_t mac_addr_ad1_47_32 : 16, - mac_addr_ad2_15_0 : 16; - uint32_t mac_addr_ad2_47_16 : 32; - uint32_t mac_addr_ad3_31_0 : 32; - uint32_t mac_addr_ad3_47_32 : 16, - mpdu_sequence_control_field : 16; - uint32_t mac_addr_ad4_31_0 : 32; - uint32_t mac_addr_ad4_47_32 : 16, - mpdu_qos_control_field : 16; - uint32_t mpdu_ht_control_field : 32; - uint32_t vdev_id : 8, - service_code : 9, - priority_valid : 1, - src_info : 12, - smr_frame : 1, - __reserved_g_0029 : 1; - uint32_t __reserved_g_0060 : 32; - uint32_t __reserved_g_0057 : 16, - __reserved_g_0059 : 16; - uint32_t __reserved_g_0056 : 32; - uint32_t authorized_to_send_wds : 1, - disallow_mcbc_da_in_unicast_mpdu : 1, - fromtods_00_fnf_check_dis : 1, - fromtods_01_fnf_check_dis : 1, - fromtods_10_fnf_check_dis : 1, - fromtods_11_fnf_check_dis : 1, - rx_misc_config : 3, - a_msdu_fromtods_10_ad3 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_11_ad4 : 2, - multi_link_ds_addr_fromtods_00_raw_en : 1, - multi_link_ds_addr_fromtods_non00_raw_en : 1, - multi_link_ds_addr_ad3_valid : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_ad1_trans_dis : 1, - data_fromtods_00_ad3 : 2, - mgmt_fromtods_00_ad3 : 2, - multi_link_ds_addr_mgmt_en : 1, - multi_link_ds_addr_ctrl_en : 1, - reserved_27a : 5; - uint32_t multi_link_ds_addr_ad3_31_0 : 32; - uint32_t multi_link_ds_addr_ad3_47_32 : 16, - cfp_mic_err : 1, - cfp_pn_chk_err : 1, - reserved_29a : 14; -#else - struct rxpt_classify_info rxpt_classify_info_details; - uint32_t reserved_7a : 13, - tid : 4, - bssid_number : 4, - bssid_hit : 1, - __reserved_g_0003 : 2, - wep_key_width_for_variable_key : 2, - encrypt_type : 4, - all_frames_shall_be_encrypted : 1, - epd_en : 1; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t reserved_2a : 6, - first_delim_err : 1, - pre_delim_err_warning : 1, - receive_queue_number : 16, - rx_reo_queue_desc_addr_39_32 : 8; - uint32_t pn_31_0 : 32; - uint32_t pn_63_32 : 32; - uint32_t pn_95_64 : 32; - uint32_t pn_127_96 : 32; - uint32_t mpdu_sequence_number : 12, - mpdu_retry : 1, - encrypted : 1, - to_ds : 1, - fr_ds : 1, - protected_cbf_cqi : 1, - more_fragment_flag : 1, - mpdu_fragment_number : 4, - frame_encryption_info_valid : 1, - mpdu_ht_control_valid : 1, - mpdu_qos_control_valid : 1, - mpdu_sequence_control_valid : 1, - mac_addr_ad4_valid : 1, - mac_addr_ad3_valid : 1, - mac_addr_ad2_valid : 1, - mac_addr_ad1_valid : 1, - mpdu_duration_valid : 1, - mpdu_frame_control_valid : 1; - uint32_t peer_meta_data : 32; - uint32_t sw_peer_id : 16, - ast_index : 16; - uint32_t phy_ppdu_id : 16, - __reserved_g_0035 : 1, - __reserved_g_0022 : 1, - ast_based_lookup_valid : 1, - protocol_version_err : 1, - phy_err_during_mpdu_header : 1, - phy_err : 1, - ndp_frame : 1, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_12 : 1, - raw_mpdu : 1, - bar_frame : 1, - ampdu_flag : 1, - pre_delim_count : 12, - strip_vlan_s_tag_decap : 1, - strip_vlan_c_tag_decap : 1, - rx_insert_vlan_s_tag_padding : 1, - rx_insert_vlan_c_tag_padding : 1, - decap_type : 2, - decrypt_needed : 1, - new_peer_entry : 1, - key_id_octet : 8; - uint32_t reserved_13 : 1, - amsdu_present : 1, - directed : 1, - encrypt_required : 1, - u_apsd_trigger : 1, - order : 1, - fragment_flag : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - first_mpdu : 1, - mpdu_length : 14; - uint32_t mpdu_duration_field : 16, - mpdu_frame_control_field : 16; - uint32_t mac_addr_ad1_31_0 : 32; - uint32_t mac_addr_ad2_15_0 : 16, - mac_addr_ad1_47_32 : 16; - uint32_t mac_addr_ad2_47_16 : 32; - uint32_t mac_addr_ad3_31_0 : 32; - uint32_t mpdu_sequence_control_field : 16, - mac_addr_ad3_47_32 : 16; - uint32_t mac_addr_ad4_31_0 : 32; - uint32_t mpdu_qos_control_field : 16, - mac_addr_ad4_47_32 : 16; - uint32_t mpdu_ht_control_field : 32; - uint32_t __reserved_g_0029 : 1, - smr_frame : 1, - src_info : 12, - priority_valid : 1, - service_code : 9, - vdev_id : 8; - uint32_t __reserved_g_0060 : 32; - uint32_t __reserved_g_0059 : 16, - __reserved_g_0057 : 16; - uint32_t __reserved_g_0056 : 32; - uint32_t reserved_27a : 5, - multi_link_ds_addr_ctrl_en : 1, - multi_link_ds_addr_mgmt_en : 1, - mgmt_fromtods_00_ad3 : 2, - data_fromtods_00_ad3 : 2, - multi_link_addr_ad1_trans_dis : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_ds_addr_ad3_valid : 1, - multi_link_ds_addr_fromtods_non00_raw_en : 1, - multi_link_ds_addr_fromtods_00_raw_en : 1, - a_msdu_fromtods_11_ad4 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_10_ad3 : 2, - rx_misc_config : 3, - fromtods_11_fnf_check_dis : 1, - fromtods_10_fnf_check_dis : 1, - fromtods_01_fnf_check_dis : 1, - fromtods_00_fnf_check_dis : 1, - disallow_mcbc_da_in_unicast_mpdu : 1, - authorized_to_send_wds : 1; - uint32_t multi_link_ds_addr_ad3_31_0 : 32; - uint32_t reserved_29a : 14, - cfp_pn_chk_err : 1, - cfp_mic_err : 1, - multi_link_ds_addr_ad3_47_32 : 16; -#endif -}; - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000 - -#define RX_MPDU_INFO_EPD_EN_OFFSET 0x00000004 -#define RX_MPDU_INFO_EPD_EN_LSB 0 -#define RX_MPDU_INFO_EPD_EN_MSB 0 -#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 - -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 - -#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x00000004 -#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 -#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 -#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c - -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 - -#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x00000004 -#define RX_MPDU_INFO_BSSID_HIT_LSB 10 -#define RX_MPDU_INFO_BSSID_HIT_MSB 10 -#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 - -#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x00000004 -#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 -#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 -#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 - -#define RX_MPDU_INFO_TID_OFFSET 0x00000004 -#define RX_MPDU_INFO_TID_LSB 15 -#define RX_MPDU_INFO_TID_MSB 18 -#define RX_MPDU_INFO_TID_MASK 0x00078000 - -#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x00000004 -#define RX_MPDU_INFO_RESERVED_7A_LSB 19 -#define RX_MPDU_INFO_RESERVED_7A_MSB 31 -#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 - -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 - -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 - -#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x0000000c -#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 -#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 -#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 - -#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x0000000c -#define RX_MPDU_INFO_RESERVED_2A_LSB 26 -#define RX_MPDU_INFO_RESERVED_2A_MSB 31 -#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 - -#define RX_MPDU_INFO_PN_31_0_OFFSET 0x00000010 -#define RX_MPDU_INFO_PN_31_0_LSB 0 -#define RX_MPDU_INFO_PN_31_0_MSB 31 -#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000014 -#define RX_MPDU_INFO_PN_63_32_LSB 0 -#define RX_MPDU_INFO_PN_63_32_MSB 31 -#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000018 -#define RX_MPDU_INFO_PN_95_64_LSB 0 -#define RX_MPDU_INFO_PN_95_64_MSB 31 -#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_127_96_OFFSET 0x0000001c -#define RX_MPDU_INFO_PN_127_96_LSB 0 -#define RX_MPDU_INFO_PN_127_96_MSB 31 -#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff - -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 - -#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 - -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 - -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 - -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 - -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 - -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 - -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 - -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 - -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 - -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 - -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000020 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_OFFSET 0x00000020 -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_LSB 15 -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_MSB 15 -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_MASK 0x00008000 - -#define RX_MPDU_INFO_FR_DS_OFFSET 0x00000020 -#define RX_MPDU_INFO_FR_DS_LSB 16 -#define RX_MPDU_INFO_FR_DS_MSB 16 -#define RX_MPDU_INFO_FR_DS_MASK 0x00010000 - -#define RX_MPDU_INFO_TO_DS_OFFSET 0x00000020 -#define RX_MPDU_INFO_TO_DS_LSB 17 -#define RX_MPDU_INFO_TO_DS_MSB 17 -#define RX_MPDU_INFO_TO_DS_MASK 0x00020000 - -#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x00000020 -#define RX_MPDU_INFO_ENCRYPTED_LSB 18 -#define RX_MPDU_INFO_ENCRYPTED_MSB 18 -#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 - -#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_RETRY_LSB 19 -#define RX_MPDU_INFO_MPDU_RETRY_MSB 19 -#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 - -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 - -#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000024 -#define RX_MPDU_INFO_PEER_META_DATA_LSB 0 -#define RX_MPDU_INFO_PEER_META_DATA_MSB 31 -#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff - -#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 -#define RX_MPDU_INFO_AST_INDEX_LSB 0 -#define RX_MPDU_INFO_AST_INDEX_MSB 15 -#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff - -#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 -#define RX_MPDU_INFO_SW_PEER_ID_LSB 16 -#define RX_MPDU_INFO_SW_PEER_ID_MSB 31 -#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 - -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 - -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x0000002c -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc - -#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x0000002c -#define RX_MPDU_INFO_NDP_FRAME_LSB 9 -#define RX_MPDU_INFO_NDP_FRAME_MSB 9 -#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 - -#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_ERR_LSB 10 -#define RX_MPDU_INFO_PHY_ERR_MSB 10 -#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 - -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 - -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 - -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 - -#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 -#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 -#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 - -#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 -#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 -#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 -#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff - -#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 - -#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 -#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 -#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 -#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 - -#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 -#define RX_MPDU_INFO_DECAP_TYPE_LSB 10 -#define RX_MPDU_INFO_DECAP_TYPE_MSB 11 -#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 - -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 - -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 - -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 - -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 - -#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 - -#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 -#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 -#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 -#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 - -#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 -#define RX_MPDU_INFO_BAR_FRAME_LSB 29 -#define RX_MPDU_INFO_BAR_FRAME_MSB 29 -#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 - -#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 -#define RX_MPDU_INFO_RAW_MPDU_LSB 30 -#define RX_MPDU_INFO_RAW_MPDU_MSB 30 -#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 - -#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 -#define RX_MPDU_INFO_RESERVED_12_LSB 31 -#define RX_MPDU_INFO_RESERVED_12_MSB 31 -#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 - -#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 -#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 -#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 -#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff - -#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 -#define RX_MPDU_INFO_FIRST_MPDU_LSB 14 -#define RX_MPDU_INFO_FIRST_MPDU_MSB 14 -#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 - -#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 -#define RX_MPDU_INFO_MCAST_BCAST_LSB 15 -#define RX_MPDU_INFO_MCAST_BCAST_MSB 15 -#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 - -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 - -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 - -#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 -#define RX_MPDU_INFO_POWER_MGMT_LSB 18 -#define RX_MPDU_INFO_POWER_MGMT_MSB 18 -#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 - -#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 -#define RX_MPDU_INFO_NON_QOS_LSB 19 -#define RX_MPDU_INFO_NON_QOS_MSB 19 -#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 - -#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 -#define RX_MPDU_INFO_NULL_DATA_LSB 20 -#define RX_MPDU_INFO_NULL_DATA_MSB 20 -#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 - -#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 -#define RX_MPDU_INFO_MGMT_TYPE_LSB 21 -#define RX_MPDU_INFO_MGMT_TYPE_MSB 21 -#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 - -#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 -#define RX_MPDU_INFO_CTRL_TYPE_LSB 22 -#define RX_MPDU_INFO_CTRL_TYPE_MSB 22 -#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 - -#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 -#define RX_MPDU_INFO_MORE_DATA_LSB 23 -#define RX_MPDU_INFO_MORE_DATA_MSB 23 -#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 - -#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 -#define RX_MPDU_INFO_EOSP_LSB 24 -#define RX_MPDU_INFO_EOSP_MSB 24 -#define RX_MPDU_INFO_EOSP_MASK 0x01000000 - -#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 -#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 -#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 -#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 - -#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 -#define RX_MPDU_INFO_ORDER_LSB 26 -#define RX_MPDU_INFO_ORDER_MSB 26 -#define RX_MPDU_INFO_ORDER_MASK 0x04000000 - -#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 -#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 -#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 -#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 - -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 - -#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 -#define RX_MPDU_INFO_DIRECTED_LSB 29 -#define RX_MPDU_INFO_DIRECTED_MSB 29 -#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 - -#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 -#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 -#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 -#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 - -#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 -#define RX_MPDU_INFO_RESERVED_13_LSB 31 -#define RX_MPDU_INFO_RESERVED_13_MSB 31 -#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 - -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff - -#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c -#define RX_MPDU_INFO_VDEV_ID_LSB 0 -#define RX_MPDU_INFO_VDEV_ID_MSB 7 -#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff - -#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c -#define RX_MPDU_INFO_SERVICE_CODE_LSB 8 -#define RX_MPDU_INFO_SERVICE_CODE_MSB 16 -#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 - -#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c -#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 -#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 -#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 - -#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c -#define RX_MPDU_INFO_SRC_INFO_LSB 18 -#define RX_MPDU_INFO_SRC_INFO_MSB 29 -#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 - -#define RX_MPDU_INFO_SMR_FRAME_OFFSET 0x0000005c -#define RX_MPDU_INFO_SMR_FRAME_LSB 30 -#define RX_MPDU_INFO_SMR_FRAME_MSB 30 -#define RX_MPDU_INFO_SMR_FRAME_MASK 0x40000000 - -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 - -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET 0x0000006c -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB 1 -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB 1 -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK 0x00000002 - -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_LSB 2 -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MSB 2 -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MASK 0x00000004 - -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_LSB 3 -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MSB 3 -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MASK 0x00000008 - -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_LSB 4 -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MSB 4 -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MASK 0x00000010 - -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_LSB 5 -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MSB 5 -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MASK 0x00000020 - -#define RX_MPDU_INFO_RX_MISC_CONFIG_OFFSET 0x0000006c -#define RX_MPDU_INFO_RX_MISC_CONFIG_LSB 6 -#define RX_MPDU_INFO_RX_MISC_CONFIG_MSB 8 -#define RX_MPDU_INFO_RX_MISC_CONFIG_MASK 0x000001c0 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_LSB 9 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MSB 10 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MASK 0x00000600 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_LSB 11 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MSB 12 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MASK 0x00001800 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_LSB 13 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MSB 14 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MASK 0x00006000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_LSB 15 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MSB 15 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MASK 0x00008000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_LSB 16 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MSB 16 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x00010000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_LSB 17 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_MSB 17 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_MASK 0x00020000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 18 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 18 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x00040000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 19 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 19 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x00080000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 20 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 20 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x00100000 - -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_LSB 21 -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MSB 22 -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MASK 0x00600000 - -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_LSB 23 -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MSB 24 -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MASK 0x01800000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_LSB 25 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_MSB 25 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_MASK 0x02000000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_LSB 26 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_MSB 26 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_MASK 0x04000000 - -#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c -#define RX_MPDU_INFO_RESERVED_27A_LSB 27 -#define RX_MPDU_INFO_RESERVED_27A_MSB 31 -#define RX_MPDU_INFO_RESERVED_27A_MASK 0xf8000000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_OFFSET 0x00000070 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_OFFSET 0x00000074 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_LSB 0 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_MSB 15 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_CFP_MIC_ERR_OFFSET 0x00000074 -#define RX_MPDU_INFO_CFP_MIC_ERR_LSB 16 -#define RX_MPDU_INFO_CFP_MIC_ERR_MSB 16 -#define RX_MPDU_INFO_CFP_MIC_ERR_MASK 0x00010000 - -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_OFFSET 0x00000074 -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_LSB 17 -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_MSB 17 -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_MASK 0x00020000 - -#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 -#define RX_MPDU_INFO_RESERVED_29A_LSB 18 -#define RX_MPDU_INFO_RESERVED_29A_MSB 31 -#define RX_MPDU_INFO_RESERVED_29A_MASK 0xfffc0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_link_ptr.h deleted file mode 100644 index e9d7e83a92cc..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_link_ptr.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_LINK_PTR_H_ -#define _RX_MPDU_LINK_PTR_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 - -struct rx_mpdu_link_ptr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info mpdu_link_desc_addr_info; -#else - struct buffer_addr_info mpdu_link_desc_addr_info; -#endif -}; - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_start.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_start.h deleted file mode 100644 index fc5029dc2da3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_start.h +++ /dev/null @@ -1,712 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_START_H_ -#define _RX_MPDU_START_H_ - -#include "rx_mpdu_info.h" -#define NUM_OF_DWORDS_RX_MPDU_START 30 - -#define NUM_OF_QWORDS_RX_MPDU_START 15 - -struct rx_mpdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_mpdu_info rx_mpdu_info_details; -#else - struct rx_mpdu_info rx_mpdu_info_details; -#endif -}; - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x0000000000100000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x0000000000400000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ff800000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x0000000100000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x0000000200000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 38 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x0000040000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x0000780000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x0007800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff8000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff0000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x0100000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc00000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000000000010 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x0000000000000010 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x0000000000000018 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000000000000018 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x0000000000000001 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 1 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x0000000000000002 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 2 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x0000000000000004 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 3 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x0000000000000008 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x0000000000000010 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x0000000000000020 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x0000000000000040 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x0000000000000080 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x0000000000003c00 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x0000000000004000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_LSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_MASK 0x0000000000008000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x0000000000010000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x0000000000020000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x0000000000040000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x0000000000080000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x00000000fff00000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000300000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x0000020000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x0000040000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x0000080000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x0000100000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x0000200000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x00000000000000ff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x0000000000000c00 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x0000000000001000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x0000000000002000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x0000000000004000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x0000000000008000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x000000000fff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x0000000010000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x0000000020000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x0000000040000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x0000000080000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x0000400000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x0000800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x0004000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x0008000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x0010000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x0020000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x0040000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x0080000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x0100000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x0400000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x0800000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 60 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 60 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x1000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x2000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x4000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x8000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff0000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_LSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_MSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_MASK 0x4000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x0000000100000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK 0x0000000200000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MASK 0x0000000400000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_LSB 35 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MSB 35 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MASK 0x0000000800000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_LSB 36 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MSB 36 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MASK 0x0000001000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_LSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MASK 0x0000002000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_LSB 38 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MASK 0x000001c000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_LSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MASK 0x0000060000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MASK 0x0000180000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_LSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MASK 0x0000600000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MASK 0x0000800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0004000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x0008000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x0010000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_LSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MASK 0x0060000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_LSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MASK 0x0180000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_MSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_MASK 0x0400000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xf800000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xfffc000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_desc_info.h deleted file mode 100644 index 88569b653b64..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_desc_info.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_DESC_INFO_H_ -#define _RX_MSDU_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 - -struct rx_msdu_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t first_msdu_in_mpdu_flag : 1, - last_msdu_in_mpdu_flag : 1, - msdu_continuation : 1, - msdu_length : 14, - msdu_drop : 1, - sa_is_valid : 1, - da_is_valid : 1, - da_is_mcbc : 1, - l3_header_padding_msb : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - fr_ds : 1, - to_ds : 1, - intra_bss : 1, - dest_chip_id : 2, - decap_format : 2, - __reserved_g_0015 : 1; -#else - uint32_t __reserved_g_0015 : 1, - decap_format : 2, - dest_chip_id : 2, - intra_bss : 1, - to_ds : 1, - fr_ds : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - l3_header_padding_msb : 1, - da_is_mcbc : 1, - da_is_valid : 1, - sa_is_valid : 1, - msdu_drop : 1, - msdu_length : 14, - msdu_continuation : 1, - last_msdu_in_mpdu_flag : 1, - first_msdu_in_mpdu_flag : 1; -#endif -}; - -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 -#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 -#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_FR_DS_LSB 24 -#define RX_MSDU_DESC_INFO_FR_DS_MSB 24 -#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 - -#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_TO_DS_LSB 25 -#define RX_MSDU_DESC_INFO_TO_DS_MSB 25 -#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 - -#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 -#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 -#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_details.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_details.h deleted file mode 100644 index 0b763a473ce6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_details.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_DETAILS_H_ -#define _RX_MSDU_DETAILS_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_msdu_ext_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 - -struct rx_msdu_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buffer_addr_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; -#else - struct buffer_addr_info buffer_addr_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; -#endif -}; - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xe0000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_end.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_end.h deleted file mode 100644 index b05c9896b09a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_end.h +++ /dev/null @@ -1,1094 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_END_H_ -#define _RX_MSDU_END_H_ - -#define NUM_OF_DWORDS_RX_MSDU_END 32 - -#define NUM_OF_QWORDS_RX_MSDU_END 16 - -struct rx_msdu_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t ip_hdr_chksum : 16, - reported_mpdu_length : 14, - reserved_1a : 2; - uint32_t reserved_2a : 8, - cce_super_rule : 6, - cce_classify_not_done_truncate : 1, - cce_classify_not_done_cce_dis : 1, - cumulative_l3_checksum : 16; - uint32_t rule_indication_31_0 : 32; - uint32_t ipv6_options_crc : 32; - uint32_t da_offset : 6, - sa_offset : 6, - da_offset_valid : 1, - sa_offset_valid : 1, - reserved_5a : 2, - l3_type : 16; - uint32_t rule_indication_63_32 : 32; - uint32_t tcp_seq_number : 32; - uint32_t tcp_ack_number : 32; - uint32_t tcp_flag : 9, - lro_eligible : 1, - reserved_9a : 6, - window_size : 16; - uint32_t sa_sw_peer_id : 16, - sa_idx_timeout : 1, - da_idx_timeout : 1, - to_ds : 1, - tid : 4, - sa_is_valid : 1, - da_is_valid : 1, - da_is_mcbc : 1, - l3_header_padding : 2, - first_msdu : 1, - last_msdu : 1, - fr_ds : 1, - ip_chksum_fail_copy : 1; - uint32_t sa_idx : 16, - da_idx_or_sw_peer_id : 16; - uint32_t msdu_drop : 1, - reo_destination_indication : 5, - flow_idx : 20, - use_ppe : 1, - __reserved_g_0003 : 2, - vlan_ctag_stripped : 1, - vlan_stag_stripped : 1, - fragment_flag : 1; - uint32_t fse_metadata : 32; - uint32_t cce_metadata : 16, - tcp_udp_chksum : 16; - uint32_t aggregation_count : 8, - flow_aggregation_continuation : 1, - fisa_timeout : 1, - tcp_udp_chksum_fail_copy : 1, - msdu_limit_error : 1, - flow_idx_timeout : 1, - flow_idx_invalid : 1, - cce_match : 1, - amsdu_parser_error : 1, - cumulative_ip_length : 16; - uint32_t key_id_octet : 8, - reserved_16a : 24; - uint32_t reserved_17a : 6, - service_code : 9, - priority_valid : 1, - intra_bss : 1, - dest_chip_id : 2, - multicast_echo : 1, - wds_learning_event : 1, - wds_roaming_event : 1, - wds_keep_alive_event : 1, - __reserved_g_0015 : 1, - reserved_17b : 8; - uint32_t msdu_length : 14, - stbc : 1, - ipsec_esp : 1, - l3_offset : 7, - ipsec_ah : 1, - l4_offset : 8; - uint32_t msdu_number : 8, - decap_format : 2, - ipv4_proto : 1, - ipv6_proto : 1, - tcp_proto : 1, - udp_proto : 1, - ip_frag : 1, - tcp_only_ack : 1, - da_is_bcast_mcast : 1, - toeplitz_hash_sel : 2, - ip_fixed_header_valid : 1, - ip_extn_header_valid : 1, - tcp_udp_header_valid : 1, - mesh_control_present : 1, - ldpc : 1, - ip4_protocol_ip6_next_header : 8; - uint32_t vlan_ctag_ci : 16, - vlan_stag_ci : 16; - uint32_t peer_meta_data : 32; - uint32_t user_rssi : 8, - pkt_type : 4, - sgi : 2, - rate_mcs : 5, - receive_bandwidth : 3, - reception_type : 3, - mimo_ss_bitmap : 6, - msdu_done_copy : 1; - uint32_t flow_id_toeplitz : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t reserved_28a : 16, - sa_15_0 : 16; - uint32_t sa_47_16 : 32; - uint32_t first_mpdu : 1, - reserved_30a : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - a_msdu_error : 1, - reserved_30b : 1, - order : 1, - wifi_parser_error : 1, - overflow_err : 1, - msdu_length_err : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - sa_idx_invalid : 1, - da_idx_invalid : 1, - amsdu_addr_mismatch : 1, - rx_in_tx_decrypt_byp : 1, - encrypt_required : 1, - directed : 1, - buffer_fragment : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - fcs_err : 1; - uint32_t reserved_31a : 10, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - ifcs_present : 1, - reserved_31b : 16, - msdu_done : 1; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_1a : 2, - reported_mpdu_length : 14, - ip_hdr_chksum : 16; - uint32_t cumulative_l3_checksum : 16, - cce_classify_not_done_cce_dis : 1, - cce_classify_not_done_truncate : 1, - cce_super_rule : 6, - reserved_2a : 8; - uint32_t rule_indication_31_0 : 32; - uint32_t ipv6_options_crc : 32; - uint32_t l3_type : 16, - reserved_5a : 2, - sa_offset_valid : 1, - da_offset_valid : 1, - sa_offset : 6, - da_offset : 6; - uint32_t rule_indication_63_32 : 32; - uint32_t tcp_seq_number : 32; - uint32_t tcp_ack_number : 32; - uint32_t window_size : 16, - reserved_9a : 6, - lro_eligible : 1, - tcp_flag : 9; - uint32_t ip_chksum_fail_copy : 1, - fr_ds : 1, - last_msdu : 1, - first_msdu : 1, - l3_header_padding : 2, - da_is_mcbc : 1, - da_is_valid : 1, - sa_is_valid : 1, - tid : 4, - to_ds : 1, - da_idx_timeout : 1, - sa_idx_timeout : 1, - sa_sw_peer_id : 16; - uint32_t da_idx_or_sw_peer_id : 16, - sa_idx : 16; - uint32_t fragment_flag : 1, - vlan_stag_stripped : 1, - vlan_ctag_stripped : 1, - __reserved_g_0003 : 2, - use_ppe : 1, - flow_idx : 20, - reo_destination_indication : 5, - msdu_drop : 1; - uint32_t fse_metadata : 32; - uint32_t tcp_udp_chksum : 16, - cce_metadata : 16; - uint32_t cumulative_ip_length : 16, - amsdu_parser_error : 1, - cce_match : 1, - flow_idx_invalid : 1, - flow_idx_timeout : 1, - msdu_limit_error : 1, - tcp_udp_chksum_fail_copy : 1, - fisa_timeout : 1, - flow_aggregation_continuation : 1, - aggregation_count : 8; - uint32_t reserved_16a : 24, - key_id_octet : 8; - uint32_t reserved_17b : 8, - __reserved_g_0015 : 1, - wds_keep_alive_event : 1, - wds_roaming_event : 1, - wds_learning_event : 1, - multicast_echo : 1, - dest_chip_id : 2, - intra_bss : 1, - priority_valid : 1, - service_code : 9, - reserved_17a : 6; - uint32_t l4_offset : 8, - ipsec_ah : 1, - l3_offset : 7, - ipsec_esp : 1, - stbc : 1, - msdu_length : 14; - uint32_t ip4_protocol_ip6_next_header : 8, - ldpc : 1, - mesh_control_present : 1, - tcp_udp_header_valid : 1, - ip_extn_header_valid : 1, - ip_fixed_header_valid : 1, - toeplitz_hash_sel : 2, - da_is_bcast_mcast : 1, - tcp_only_ack : 1, - ip_frag : 1, - udp_proto : 1, - tcp_proto : 1, - ipv6_proto : 1, - ipv4_proto : 1, - decap_format : 2, - msdu_number : 8; - uint32_t vlan_stag_ci : 16, - vlan_ctag_ci : 16; - uint32_t peer_meta_data : 32; - uint32_t msdu_done_copy : 1, - mimo_ss_bitmap : 6, - reception_type : 3, - receive_bandwidth : 3, - rate_mcs : 5, - sgi : 2, - pkt_type : 4, - user_rssi : 8; - uint32_t flow_id_toeplitz : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t sa_15_0 : 16, - reserved_28a : 16; - uint32_t sa_47_16 : 32; - uint32_t fcs_err : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - buffer_fragment : 1, - directed : 1, - encrypt_required : 1, - rx_in_tx_decrypt_byp : 1, - amsdu_addr_mismatch : 1, - da_idx_invalid : 1, - sa_idx_invalid : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - msdu_length_err : 1, - overflow_err : 1, - wifi_parser_error : 1, - order : 1, - reserved_30b : 1, - a_msdu_error : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - reserved_30a : 1, - first_mpdu : 1; - uint32_t msdu_done : 1, - reserved_31b : 16, - ifcs_present : 1, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - reserved_31a : 10; -#endif -}; - -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RESERVED_0_LSB 9 -#define RX_MSDU_END_RESERVED_0_MSB 15 -#define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_END_PHY_PPDU_ID_LSB 16 -#define RX_MSDU_END_PHY_PPDU_ID_MSB 31 -#define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 -#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 -#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 -#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 - -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 - -#define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RESERVED_1A_LSB 62 -#define RX_MSDU_END_RESERVED_1A_MSB 63 -#define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 - -#define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MSDU_END_RESERVED_2A_LSB 0 -#define RX_MSDU_END_RESERVED_2A_MSB 7 -#define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff - -#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 -#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 -#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 - -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 - -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 - -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 -#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 -#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 -#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 - -#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff - -#define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 -#define RX_MSDU_END_DA_OFFSET_LSB 32 -#define RX_MSDU_END_DA_OFFSET_MSB 37 -#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 - -#define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 -#define RX_MSDU_END_SA_OFFSET_LSB 38 -#define RX_MSDU_END_SA_OFFSET_MSB 43 -#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 - -#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 -#define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 -#define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 -#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 - -#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 -#define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 -#define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 -#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 - -#define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 -#define RX_MSDU_END_RESERVED_5A_LSB 46 -#define RX_MSDU_END_RESERVED_5A_MSB 47 -#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 - -#define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_END_L3_TYPE_LSB 48 -#define RX_MSDU_END_L3_TYPE_MSB 63 -#define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 - -#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 -#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 -#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 -#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 -#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 -#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 - -#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 -#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 -#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 -#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 -#define RX_MSDU_END_TCP_FLAG_LSB 32 -#define RX_MSDU_END_TCP_FLAG_MSB 40 -#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 - -#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 -#define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 -#define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 -#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 - -#define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 -#define RX_MSDU_END_RESERVED_9A_LSB 42 -#define RX_MSDU_END_RESERVED_9A_MSB 47 -#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 - -#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 -#define RX_MSDU_END_WINDOW_SIZE_LSB 48 -#define RX_MSDU_END_WINDOW_SIZE_MSB 63 -#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 - -#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 -#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 -#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff - -#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 -#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 -#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 - -#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 -#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 -#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 - -#define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 -#define RX_MSDU_END_TO_DS_LSB 18 -#define RX_MSDU_END_TO_DS_MSB 18 -#define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 - -#define RX_MSDU_END_TID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_TID_LSB 19 -#define RX_MSDU_END_TID_MSB 22 -#define RX_MSDU_END_TID_MASK 0x0000000000780000 - -#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IS_VALID_LSB 23 -#define RX_MSDU_END_SA_IS_VALID_MSB 23 -#define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 - -#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IS_VALID_LSB 24 -#define RX_MSDU_END_DA_IS_VALID_MSB 24 -#define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 - -#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IS_MCBC_LSB 25 -#define RX_MSDU_END_DA_IS_MCBC_MSB 25 -#define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 - -#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 -#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 -#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 -#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 - -#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 -#define RX_MSDU_END_FIRST_MSDU_LSB 28 -#define RX_MSDU_END_FIRST_MSDU_MSB 28 -#define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 - -#define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 -#define RX_MSDU_END_LAST_MSDU_LSB 29 -#define RX_MSDU_END_LAST_MSDU_MSB 29 -#define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 - -#define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 -#define RX_MSDU_END_FR_DS_LSB 30 -#define RX_MSDU_END_FR_DS_MSB 30 -#define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 - -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 - -#define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IDX_LSB 32 -#define RX_MSDU_END_SA_IDX_MSB 47 -#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 - -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 - -#define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 -#define RX_MSDU_END_MSDU_DROP_LSB 0 -#define RX_MSDU_END_MSDU_DROP_MSB 0 -#define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 - -#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e - -#define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FLOW_IDX_LSB 6 -#define RX_MSDU_END_FLOW_IDX_MSB 25 -#define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 - -#define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 -#define RX_MSDU_END_USE_PPE_LSB 26 -#define RX_MSDU_END_USE_PPE_MSB 26 -#define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 - -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 - -#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 - -#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 -#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 -#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 - -#define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FSE_METADATA_LSB 32 -#define RX_MSDU_END_FSE_METADATA_MSB 63 -#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CCE_METADATA_LSB 0 -#define RX_MSDU_END_CCE_METADATA_MSB 15 -#define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff - -#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 -#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 -#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 -#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 -#define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 -#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 - -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 - -#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FISA_TIMEOUT_LSB 41 -#define RX_MSDU_END_FISA_TIMEOUT_MSB 41 -#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 - -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 - -#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 - -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 - -#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 -#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 -#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 - -#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CCE_MATCH_LSB 46 -#define RX_MSDU_END_CCE_MATCH_MSB 46 -#define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 - -#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 - -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 - -#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 -#define RX_MSDU_END_KEY_ID_OCTET_LSB 0 -#define RX_MSDU_END_KEY_ID_OCTET_MSB 7 -#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff - -#define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_16A_LSB 8 -#define RX_MSDU_END_RESERVED_16A_MSB 31 -#define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 - -#define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_17A_LSB 32 -#define RX_MSDU_END_RESERVED_17A_MSB 37 -#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 - -#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 -#define RX_MSDU_END_SERVICE_CODE_LSB 38 -#define RX_MSDU_END_SERVICE_CODE_MSB 46 -#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 - -#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 -#define RX_MSDU_END_PRIORITY_VALID_LSB 47 -#define RX_MSDU_END_PRIORITY_VALID_MSB 47 -#define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 - -#define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 -#define RX_MSDU_END_INTRA_BSS_LSB 48 -#define RX_MSDU_END_INTRA_BSS_MSB 48 -#define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 - -#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 -#define RX_MSDU_END_DEST_CHIP_ID_LSB 49 -#define RX_MSDU_END_DEST_CHIP_ID_MSB 50 -#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 - -#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 -#define RX_MSDU_END_MULTICAST_ECHO_LSB 51 -#define RX_MSDU_END_MULTICAST_ECHO_MSB 51 -#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 - -#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 -#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 -#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 - -#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 -#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 -#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 - -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 - -#define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_17B_LSB 56 -#define RX_MSDU_END_RESERVED_17B_MSB 63 -#define RX_MSDU_END_RESERVED_17B_MASK 0xff00000000000000 - -#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MSDU_LENGTH_LSB 0 -#define RX_MSDU_END_MSDU_LENGTH_MSB 13 -#define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff - -#define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 -#define RX_MSDU_END_STBC_LSB 14 -#define RX_MSDU_END_STBC_MSB 14 -#define RX_MSDU_END_STBC_MASK 0x0000000000004000 - -#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPSEC_ESP_LSB 15 -#define RX_MSDU_END_IPSEC_ESP_MSB 15 -#define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 - -#define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 -#define RX_MSDU_END_L3_OFFSET_LSB 16 -#define RX_MSDU_END_L3_OFFSET_MSB 22 -#define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 - -#define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPSEC_AH_LSB 23 -#define RX_MSDU_END_IPSEC_AH_MSB 23 -#define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 - -#define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 -#define RX_MSDU_END_L4_OFFSET_LSB 24 -#define RX_MSDU_END_L4_OFFSET_MSB 31 -#define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 - -#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MSDU_NUMBER_LSB 32 -#define RX_MSDU_END_MSDU_NUMBER_MSB 39 -#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 - -#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 -#define RX_MSDU_END_DECAP_FORMAT_LSB 40 -#define RX_MSDU_END_DECAP_FORMAT_MSB 41 -#define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 - -#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPV4_PROTO_LSB 42 -#define RX_MSDU_END_IPV4_PROTO_MSB 42 -#define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 - -#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPV6_PROTO_LSB 43 -#define RX_MSDU_END_IPV6_PROTO_MSB 43 -#define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 - -#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_PROTO_LSB 44 -#define RX_MSDU_END_TCP_PROTO_MSB 44 -#define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 - -#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_UDP_PROTO_LSB 45 -#define RX_MSDU_END_UDP_PROTO_MSB 45 -#define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 - -#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_FRAG_LSB 46 -#define RX_MSDU_END_IP_FRAG_MSB 46 -#define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 - -#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 -#define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 -#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 - -#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 - -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 - -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 - -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 - -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 - -#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 - -#define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 -#define RX_MSDU_END_LDPC_LSB 55 -#define RX_MSDU_END_LDPC_MSB 55 -#define RX_MSDU_END_LDPC_MASK 0x0080000000000000 - -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 - -#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 -#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 -#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 -#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff - -#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 -#define RX_MSDU_END_VLAN_STAG_CI_LSB 16 -#define RX_MSDU_END_VLAN_STAG_CI_MSB 31 -#define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 -#define RX_MSDU_END_PEER_META_DATA_LSB 32 -#define RX_MSDU_END_PEER_META_DATA_MSB 63 -#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 -#define RX_MSDU_END_USER_RSSI_LSB 0 -#define RX_MSDU_END_USER_RSSI_MSB 7 -#define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff - -#define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 -#define RX_MSDU_END_PKT_TYPE_LSB 8 -#define RX_MSDU_END_PKT_TYPE_MSB 11 -#define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 - -#define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 -#define RX_MSDU_END_SGI_LSB 12 -#define RX_MSDU_END_SGI_MSB 13 -#define RX_MSDU_END_SGI_MASK 0x0000000000003000 - -#define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RATE_MCS_LSB 14 -#define RX_MSDU_END_RATE_MCS_MSB 18 -#define RX_MSDU_END_RATE_MCS_MASK 0x000000000007c000 - -#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 19 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 21 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x0000000000380000 - -#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RECEPTION_TYPE_LSB 22 -#define RX_MSDU_END_RECEPTION_TYPE_MSB 24 -#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000001c00000 - -#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 -#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 25 -#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 -#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007e000000 - -#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 -#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 -#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 -#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 - -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 - -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff - -#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 -#define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 -#define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 -#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 - -#define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 -#define RX_MSDU_END_RESERVED_28A_LSB 0 -#define RX_MSDU_END_RESERVED_28A_MSB 15 -#define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff - -#define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 -#define RX_MSDU_END_SA_15_0_LSB 16 -#define RX_MSDU_END_SA_15_0_MSB 31 -#define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 -#define RX_MSDU_END_SA_47_16_LSB 32 -#define RX_MSDU_END_SA_47_16_MSB 63 -#define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 - -#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 -#define RX_MSDU_END_FIRST_MPDU_LSB 0 -#define RX_MSDU_END_FIRST_MPDU_MSB 0 -#define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 - -#define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_30A_LSB 1 -#define RX_MSDU_END_RESERVED_30A_MSB 1 -#define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 - -#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MCAST_BCAST_LSB 2 -#define RX_MSDU_END_MCAST_BCAST_MSB 2 -#define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 - -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 - -#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 - -#define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_POWER_MGMT_LSB 5 -#define RX_MSDU_END_POWER_MGMT_MSB 5 -#define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 - -#define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 -#define RX_MSDU_END_NON_QOS_LSB 6 -#define RX_MSDU_END_NON_QOS_MSB 6 -#define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 - -#define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 -#define RX_MSDU_END_NULL_DATA_LSB 7 -#define RX_MSDU_END_NULL_DATA_MSB 7 -#define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 - -#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MGMT_TYPE_LSB 8 -#define RX_MSDU_END_MGMT_TYPE_MSB 8 -#define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 - -#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_CTRL_TYPE_LSB 9 -#define RX_MSDU_END_CTRL_TYPE_MSB 9 -#define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 - -#define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MORE_DATA_LSB 10 -#define RX_MSDU_END_MORE_DATA_MSB 10 -#define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 - -#define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 -#define RX_MSDU_END_EOSP_LSB 11 -#define RX_MSDU_END_EOSP_MSB 11 -#define RX_MSDU_END_EOSP_MASK 0x0000000000000800 - -#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_A_MSDU_ERROR_LSB 12 -#define RX_MSDU_END_A_MSDU_ERROR_MSB 12 -#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 - -#define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_30B_LSB 13 -#define RX_MSDU_END_RESERVED_30B_MSB 13 -#define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 - -#define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 -#define RX_MSDU_END_ORDER_LSB 14 -#define RX_MSDU_END_ORDER_MSB 14 -#define RX_MSDU_END_ORDER_MASK 0x0000000000004000 - -#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 -#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 -#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 - -#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_OVERFLOW_ERR_LSB 16 -#define RX_MSDU_END_OVERFLOW_ERR_MSB 16 -#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 - -#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 -#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 -#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 - -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 - -#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 -#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 -#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 -#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 - -#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 -#define RX_MSDU_END_SA_IDX_INVALID_LSB 20 -#define RX_MSDU_END_SA_IDX_INVALID_MSB 20 -#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 - -#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DA_IDX_INVALID_LSB 21 -#define RX_MSDU_END_DA_IDX_INVALID_MSB 21 -#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 - -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 - -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 - -#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 -#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 -#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 - -#define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DIRECTED_LSB 25 -#define RX_MSDU_END_DIRECTED_MSB 25 -#define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 - -#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 -#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 -#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 - -#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 -#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 -#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 - -#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 -#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 -#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 - -#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DECRYPT_ERR_LSB 29 -#define RX_MSDU_END_DECRYPT_ERR_MSB 29 -#define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 - -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 - -#define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_FCS_ERR_LSB 31 -#define RX_MSDU_END_FCS_ERR_MSB 31 -#define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 - -#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_31A_LSB 32 -#define RX_MSDU_END_RESERVED_31A_MSB 41 -#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 - -#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 - -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 - -#define RX_MSDU_END_IFCS_PRESENT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_IFCS_PRESENT_LSB 46 -#define RX_MSDU_END_IFCS_PRESENT_MSB 46 -#define RX_MSDU_END_IFCS_PRESENT_MASK 0x0000400000000000 - -#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_31B_LSB 47 -#define RX_MSDU_END_RESERVED_31B_MSB 62 -#define RX_MSDU_END_RESERVED_31B_MASK 0x7fff800000000000 - -#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MSDU_DONE_LSB 63 -#define RX_MSDU_END_MSDU_DONE_MSB 63 -#define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_ext_desc_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_ext_desc_info.h deleted file mode 100644 index 70bda69ddfec..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_ext_desc_info.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_EXT_DESC_INFO_H_ -#define _RX_MSDU_EXT_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 - -struct rx_msdu_ext_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reo_destination_indication : 5, - service_code : 9, - priority_valid : 1, - data_offset : 12, - src_link_id : 3, - reserved_0a : 2; -#else - uint32_t reserved_0a : 2, - src_link_id : 3, - data_offset : 12, - priority_valid : 1, - service_code : 9, - reo_destination_indication : 5; -#endif -}; - -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_link.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_link.h deleted file mode 100644 index c54357dae2ef..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_link.h +++ /dev/null @@ -1,2051 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_LINK_H_ -#define _RX_MSDU_LINK_H_ - -#include "uniform_descriptor_header.h" -#include "buffer_addr_info.h" -#include "rx_msdu_details.h" -#define NUM_OF_DWORDS_RX_MSDU_LINK 64 - -struct rx_msdu_link { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct uniform_descriptor_header descriptor_header; - struct buffer_addr_info next_msdu_link_desc_addr_info; - uint32_t reserved_3a : 32; - struct rx_msdu_details msdu_0; - struct rx_msdu_details msdu_1; - struct rx_msdu_details msdu_2; - struct rx_msdu_details msdu_3; - struct rx_msdu_details msdu_4; - struct rx_msdu_details msdu_5; - struct rx_msdu_details msdu_6; - struct rx_msdu_details msdu_7; - struct rx_msdu_details msdu_8; - struct rx_msdu_details msdu_9; - struct rx_msdu_details msdu_10; - struct rx_msdu_details msdu_11; - struct rx_msdu_details msdu_12; - struct rx_msdu_details msdu_13; - struct rx_msdu_details msdu_14; -#else - struct uniform_descriptor_header descriptor_header; - struct buffer_addr_info next_msdu_link_desc_addr_info; - uint32_t reserved_3a : 32; - struct rx_msdu_details msdu_0; - struct rx_msdu_details msdu_1; - struct rx_msdu_details msdu_2; - struct rx_msdu_details msdu_3; - struct rx_msdu_details msdu_4; - struct rx_msdu_details msdu_5; - struct rx_msdu_details msdu_6; - struct rx_msdu_details msdu_7; - struct rx_msdu_details msdu_8; - struct rx_msdu_details msdu_9; - struct rx_msdu_details msdu_10; - struct rx_msdu_details msdu_11; - struct rx_msdu_details msdu_12; - struct rx_msdu_details msdu_13; - struct rx_msdu_details msdu_14; -#endif -}; - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c -#define RX_MSDU_LINK_RESERVED_3A_LSB 0 -#define RX_MSDU_LINK_RESERVED_3A_MSB 31 -#define RX_MSDU_LINK_RESERVED_3A_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000010 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000080 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000090 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000a0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000b0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000c0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000d0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000e0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000f0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_start.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_start.h deleted file mode 100644 index e1e99c027c85..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_start.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_START_H_ -#define _RX_MSDU_START_H_ - -#define NUM_OF_DWORDS_RX_MSDU_START 10 - -#define NUM_OF_QWORDS_RX_MSDU_START 5 - -struct rx_msdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - rate_mcs : 5, - reserved_0 : 2, - phy_ppdu_id : 16; - uint32_t msdu_length : 14, - stbc : 1, - ipsec_esp : 1, - l3_offset : 7, - ipsec_ah : 1, - l4_offset : 8; - uint32_t msdu_number : 8, - decap_format : 2, - ipv4_proto : 1, - ipv6_proto : 1, - tcp_proto : 1, - udp_proto : 1, - ip_frag : 1, - tcp_only_ack : 1, - da_is_bcast_mcast : 1, - toeplitz_hash_sel : 2, - ip_fixed_header_valid : 1, - ip_extn_header_valid : 1, - tcp_udp_header_valid : 1, - mesh_control_present : 1, - ldpc : 1, - ip4_protocol_ip6_next_header : 8; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t flow_id_toeplitz : 32; - uint32_t user_rssi : 8, - pkt_type : 4, - sgi : 2, - reserved_5a : 4, - receive_bandwidth : 3, - reception_type : 3, - mimo_ss_bitmap : 8; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t vlan_ctag_ci : 16, - vlan_stag_ci : 16; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 2, - rate_mcs : 5, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t l4_offset : 8, - ipsec_ah : 1, - l3_offset : 7, - ipsec_esp : 1, - stbc : 1, - msdu_length : 14; - uint32_t ip4_protocol_ip6_next_header : 8, - ldpc : 1, - mesh_control_present : 1, - tcp_udp_header_valid : 1, - ip_extn_header_valid : 1, - ip_fixed_header_valid : 1, - toeplitz_hash_sel : 2, - da_is_bcast_mcast : 1, - tcp_only_ack : 1, - ip_frag : 1, - udp_proto : 1, - tcp_proto : 1, - ipv6_proto : 1, - ipv4_proto : 1, - decap_format : 2, - msdu_number : 8; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t flow_id_toeplitz : 32; - uint32_t mimo_ss_bitmap : 8, - reception_type : 3, - receive_bandwidth : 3, - reserved_5a : 4, - sgi : 2, - pkt_type : 4, - user_rssi : 8; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t vlan_stag_ci : 16, - vlan_ctag_ci : 16; -#endif -}; - -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MSDU_START_RATE_MCS_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RATE_MCS_LSB 9 -#define RX_MSDU_START_RATE_MCS_MSB 13 -#define RX_MSDU_START_RATE_MCS_MASK 0x0000000000003e00 - -#define RX_MSDU_START_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RESERVED_0_LSB 14 -#define RX_MSDU_START_RESERVED_0_MSB 15 -#define RX_MSDU_START_RESERVED_0_MASK 0x000000000000c000 - -#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_START_PHY_PPDU_ID_LSB 16 -#define RX_MSDU_START_PHY_PPDU_ID_MSB 31 -#define RX_MSDU_START_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x0000000000000000 -#define RX_MSDU_START_MSDU_LENGTH_LSB 32 -#define RX_MSDU_START_MSDU_LENGTH_MSB 45 -#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff00000000 - -#define RX_MSDU_START_STBC_OFFSET 0x0000000000000000 -#define RX_MSDU_START_STBC_LSB 46 -#define RX_MSDU_START_STBC_MSB 46 -#define RX_MSDU_START_STBC_MASK 0x0000400000000000 - -#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x0000000000000000 -#define RX_MSDU_START_IPSEC_ESP_LSB 47 -#define RX_MSDU_START_IPSEC_ESP_MSB 47 -#define RX_MSDU_START_IPSEC_ESP_MASK 0x0000800000000000 - -#define RX_MSDU_START_L3_OFFSET_OFFSET 0x0000000000000000 -#define RX_MSDU_START_L3_OFFSET_LSB 48 -#define RX_MSDU_START_L3_OFFSET_MSB 54 -#define RX_MSDU_START_L3_OFFSET_MASK 0x007f000000000000 - -#define RX_MSDU_START_IPSEC_AH_OFFSET 0x0000000000000000 -#define RX_MSDU_START_IPSEC_AH_LSB 55 -#define RX_MSDU_START_IPSEC_AH_MSB 55 -#define RX_MSDU_START_IPSEC_AH_MASK 0x0080000000000000 - -#define RX_MSDU_START_L4_OFFSET_OFFSET 0x0000000000000000 -#define RX_MSDU_START_L4_OFFSET_LSB 56 -#define RX_MSDU_START_L4_OFFSET_MSB 63 -#define RX_MSDU_START_L4_OFFSET_MASK 0xff00000000000000 - -#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x0000000000000008 -#define RX_MSDU_START_MSDU_NUMBER_LSB 0 -#define RX_MSDU_START_MSDU_NUMBER_MSB 7 -#define RX_MSDU_START_MSDU_NUMBER_MASK 0x00000000000000ff - -#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x0000000000000008 -#define RX_MSDU_START_DECAP_FORMAT_LSB 8 -#define RX_MSDU_START_DECAP_FORMAT_MSB 9 -#define RX_MSDU_START_DECAP_FORMAT_MASK 0x0000000000000300 - -#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IPV4_PROTO_LSB 10 -#define RX_MSDU_START_IPV4_PROTO_MSB 10 -#define RX_MSDU_START_IPV4_PROTO_MASK 0x0000000000000400 - -#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IPV6_PROTO_LSB 11 -#define RX_MSDU_START_IPV6_PROTO_MSB 11 -#define RX_MSDU_START_IPV6_PROTO_MASK 0x0000000000000800 - -#define RX_MSDU_START_TCP_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_PROTO_LSB 12 -#define RX_MSDU_START_TCP_PROTO_MSB 12 -#define RX_MSDU_START_TCP_PROTO_MASK 0x0000000000001000 - -#define RX_MSDU_START_UDP_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_UDP_PROTO_LSB 13 -#define RX_MSDU_START_UDP_PROTO_MSB 13 -#define RX_MSDU_START_UDP_PROTO_MASK 0x0000000000002000 - -#define RX_MSDU_START_IP_FRAG_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_FRAG_LSB 14 -#define RX_MSDU_START_IP_FRAG_MSB 14 -#define RX_MSDU_START_IP_FRAG_MASK 0x0000000000004000 - -#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 -#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 -#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x0000000000008000 - -#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000008 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x0000000000010000 - -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x0000000000060000 - -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x0000000000080000 - -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x0000000000100000 - -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x0000000000200000 - -#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000008 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x0000000000400000 - -#define RX_MSDU_START_LDPC_OFFSET 0x0000000000000008 -#define RX_MSDU_START_LDPC_LSB 23 -#define RX_MSDU_START_LDPC_MSB 23 -#define RX_MSDU_START_LDPC_MASK 0x0000000000800000 - -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00000000ff000000 - -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 32 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 63 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 - -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000010 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0x00000000ffffffff - -#define RX_MSDU_START_USER_RSSI_OFFSET 0x0000000000000010 -#define RX_MSDU_START_USER_RSSI_LSB 32 -#define RX_MSDU_START_USER_RSSI_MSB 39 -#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff00000000 - -#define RX_MSDU_START_PKT_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_START_PKT_TYPE_LSB 40 -#define RX_MSDU_START_PKT_TYPE_MSB 43 -#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f0000000000 - -#define RX_MSDU_START_SGI_OFFSET 0x0000000000000010 -#define RX_MSDU_START_SGI_LSB 44 -#define RX_MSDU_START_SGI_MSB 45 -#define RX_MSDU_START_SGI_MASK 0x0000300000000000 - -#define RX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RESERVED_5A_LSB 46 -#define RX_MSDU_START_RESERVED_5A_MSB 49 -#define RX_MSDU_START_RESERVED_5A_MASK 0x0003c00000000000 - -#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 50 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 52 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c000000000000 - -#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RECEPTION_TYPE_LSB 53 -#define RX_MSDU_START_RECEPTION_TYPE_MSB 55 -#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e0000000000000 - -#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x0000000000000010 -#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 56 -#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 63 -#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff00000000000000 - -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000018 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000018 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 - -#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000020 -#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 -#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 -#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0x00000000ffffffff - -#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x0000000000000020 -#define RX_MSDU_START_VLAN_CTAG_CI_LSB 32 -#define RX_MSDU_START_VLAN_CTAG_CI_MSB 47 -#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff00000000 - -#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x0000000000000020 -#define RX_MSDU_START_VLAN_STAG_CI_LSB 48 -#define RX_MSDU_START_VLAN_STAG_CI_MSB 63 -#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_ack_report.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_ack_report.h deleted file mode 100644 index 345b14ea4255..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_ack_report.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_ACK_REPORT_H_ -#define _RX_PPDU_ACK_REPORT_H_ - -#include "ack_report.h" -#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2 - -#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1 - -struct rx_ppdu_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ack_report ack_report_details; - uint32_t tlv64_padding : 32; -#else - struct ack_report ack_report_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x000000000000000f - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000000f0 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x0000000000000100 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x000000000000fe00 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 - -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB 32 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB 63 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats.h deleted file mode 100644 index 51db8f35a6ab..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats.h +++ /dev/null @@ -1,679 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_END_USER_STATS_H_ -#define _RX_PPDU_END_USER_STATS_H_ - -#include "rx_rxpcu_classification_overview.h" -#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 - -#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15 - -struct rx_ppdu_end_user_stats { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t sta_full_aid : 13, - mcs : 5, - nss : 3, - expected_response_ack_or_ba : 1, - reserved_1a : 10; - uint32_t sw_peer_id : 16, - mpdu_cnt_fcs_err : 11, - sw2rxdma0_buf_source_used : 1, - fw2rxdma0_buf_source_used : 1, - sw2rxdma1_buf_source_used : 1, - sw2rxdma2_buf_source_used : 1, - fw2rxdma1_buf_source_used : 1; - uint32_t mpdu_cnt_fcs_ok : 11, - frame_control_info_valid : 1, - qos_control_info_valid : 1, - ht_control_info_valid : 1, - data_sequence_control_info_valid : 1, - ht_control_info_null_valid : 1, - rxdma2fw0_ring_used : 1, - rxdma2fw1_ring_used : 1, - rxdma2fwreo_0_ring_used : 1, - rxdma2fwreo_1_ring_used : 1, - reserved_3a : 1, - ht_control_field_pkt_type : 4, - reserved_3b : 7; - uint32_t ast_index : 16, - frame_control_field : 16; - uint32_t first_data_seq_ctrl : 16, - qos_control_field : 16; - uint32_t ht_control_field : 32; - uint32_t fcs_ok_bitmap_31_0 : 32; - uint32_t fcs_ok_bitmap_63_32 : 32; - uint32_t udp_msdu_count : 16, - tcp_msdu_count : 16; - uint32_t other_msdu_count : 16, - tcp_ack_msdu_count : 16; - uint32_t sw_response_reference_ptr : 32; - uint32_t received_qos_data_tid_bitmap : 16, - received_qos_data_tid_eosp_bitmap : 16; - uint32_t qosctrl_15_8_tid0 : 8, - qosctrl_15_8_tid1 : 8, - qosctrl_15_8_tid2 : 8, - qosctrl_15_8_tid3 : 8; - uint32_t qosctrl_15_8_tid4 : 8, - qosctrl_15_8_tid5 : 8, - qosctrl_15_8_tid6 : 8, - qosctrl_15_8_tid7 : 8; - uint32_t qosctrl_15_8_tid8 : 8, - qosctrl_15_8_tid9 : 8, - qosctrl_15_8_tid10 : 8, - qosctrl_15_8_tid11 : 8; - uint32_t qosctrl_15_8_tid12 : 8, - qosctrl_15_8_tid13 : 8, - qosctrl_15_8_tid14 : 8, - qosctrl_15_8_tid15 : 8; - uint32_t mpdu_ok_byte_count : 25, - ampdu_delim_ok_count_6_0 : 7; - uint32_t ampdu_delim_err_count : 25, - ampdu_delim_ok_count_13_7 : 7; - uint32_t mpdu_err_byte_count : 25, - ampdu_delim_ok_count_20_14 : 7; - uint32_t non_consecutive_delimiter_err : 16, - retried_msdu_count : 16; - uint32_t ht_control_null_field : 32; - uint32_t sw_response_reference_ptr_ext : 32; - uint32_t corrupted_due_to_fifo_delay : 1, - frame_control_info_null_valid : 1, - frame_control_field_null : 16, - retried_mpdu_count : 11, - reserved_23a : 3; - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_24a : 4, - frame_control_info_mgmt_ctrl_valid : 1, - mac_addr_ad2_valid : 1, - mcast_bcast : 1, - frame_control_field_mgmt_ctrl : 16; - uint32_t user_ppdu_len : 24, - reserved_25a : 8; - uint32_t mac_addr_ad2_31_0 : 32; - uint32_t mac_addr_ad2_47_32 : 16, - amsdu_msdu_count : 16; - uint32_t non_amsdu_msdu_count : 16, - ucast_msdu_count : 16; - uint32_t bcast_msdu_count : 16, - mcast_bcast_msdu_count : 16; -#else - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t reserved_1a : 10, - expected_response_ack_or_ba : 1, - nss : 3, - mcs : 5, - sta_full_aid : 13; - uint32_t fw2rxdma1_buf_source_used : 1, - sw2rxdma2_buf_source_used : 1, - sw2rxdma1_buf_source_used : 1, - fw2rxdma0_buf_source_used : 1, - sw2rxdma0_buf_source_used : 1, - mpdu_cnt_fcs_err : 11, - sw_peer_id : 16; - uint32_t reserved_3b : 7, - ht_control_field_pkt_type : 4, - reserved_3a : 1, - rxdma2fwreo_1_ring_used : 1, - rxdma2fwreo_0_ring_used : 1, - rxdma2fw1_ring_used : 1, - rxdma2fw0_ring_used : 1, - ht_control_info_null_valid : 1, - data_sequence_control_info_valid : 1, - ht_control_info_valid : 1, - qos_control_info_valid : 1, - frame_control_info_valid : 1, - mpdu_cnt_fcs_ok : 11; - uint32_t frame_control_field : 16, - ast_index : 16; - uint32_t qos_control_field : 16, - first_data_seq_ctrl : 16; - uint32_t ht_control_field : 32; - uint32_t fcs_ok_bitmap_31_0 : 32; - uint32_t fcs_ok_bitmap_63_32 : 32; - uint32_t tcp_msdu_count : 16, - udp_msdu_count : 16; - uint32_t tcp_ack_msdu_count : 16, - other_msdu_count : 16; - uint32_t sw_response_reference_ptr : 32; - uint32_t received_qos_data_tid_eosp_bitmap : 16, - received_qos_data_tid_bitmap : 16; - uint32_t qosctrl_15_8_tid3 : 8, - qosctrl_15_8_tid2 : 8, - qosctrl_15_8_tid1 : 8, - qosctrl_15_8_tid0 : 8; - uint32_t qosctrl_15_8_tid7 : 8, - qosctrl_15_8_tid6 : 8, - qosctrl_15_8_tid5 : 8, - qosctrl_15_8_tid4 : 8; - uint32_t qosctrl_15_8_tid11 : 8, - qosctrl_15_8_tid10 : 8, - qosctrl_15_8_tid9 : 8, - qosctrl_15_8_tid8 : 8; - uint32_t qosctrl_15_8_tid15 : 8, - qosctrl_15_8_tid14 : 8, - qosctrl_15_8_tid13 : 8, - qosctrl_15_8_tid12 : 8; - uint32_t ampdu_delim_ok_count_6_0 : 7, - mpdu_ok_byte_count : 25; - uint32_t ampdu_delim_ok_count_13_7 : 7, - ampdu_delim_err_count : 25; - uint32_t ampdu_delim_ok_count_20_14 : 7, - mpdu_err_byte_count : 25; - uint32_t retried_msdu_count : 16, - non_consecutive_delimiter_err : 16; - uint32_t ht_control_null_field : 32; - uint32_t sw_response_reference_ptr_ext : 32; - uint32_t reserved_23a : 3, - retried_mpdu_count : 11, - frame_control_field_null : 16, - frame_control_info_null_valid : 1, - corrupted_due_to_fifo_delay : 1; - uint32_t frame_control_field_mgmt_ctrl : 16, - mcast_bcast : 1, - mac_addr_ad2_valid : 1, - frame_control_info_mgmt_ctrl_valid : 1, - reserved_24a : 4, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_25a : 8, - user_ppdu_len : 24; - uint32_t mac_addr_ad2_31_0 : 32; - uint32_t amsdu_msdu_count : 16, - mac_addr_ad2_47_32 : 16; - uint32_t ucast_msdu_count : 16, - non_amsdu_msdu_count : 16; - uint32_t mcast_bcast_msdu_count : 16, - bcast_msdu_count : 16; -#endif -}; - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 - -#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_MCS_LSB 45 -#define RX_PPDU_END_USER_STATS_MCS_MSB 49 -#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0003e00000000000 - -#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_NSS_LSB 50 -#define RX_PPDU_END_USER_STATS_NSS_MSB 52 -#define RX_PPDU_END_USER_STATS_NSS_MASK 0x001c000000000000 - -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 53 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 53 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0020000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 54 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffc0000000000000 - -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 - -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_LSB 28 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MSB 28 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000010000000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_LSB 30 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MSB 30 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MASK 0x0000000040000000 - -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_LSB 31 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MSB 31 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000080000000 - -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 - -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 - -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_LSB 48 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MSB 48 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MASK 0x0001000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_LSB 49 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MSB 49 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MASK 0x0002000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_LSB 50 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MSB 50 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MASK 0x0004000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_LSB 51 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MSB 51 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MASK 0x0008000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_LSB 52 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_MSB 52 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_MASK 0x0010000000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 57 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 -#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 -#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 - -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 - -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 - -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 - -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x0000000000001e00 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x0000000000002000 - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x0000000000004000 - -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x0000000000008000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 32 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 55 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff00000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 56 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 32 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 47 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 47 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats_ext.h deleted file mode 100644 index 0a11202db481..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats_ext.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ -#define _RX_PPDU_END_USER_STATS_EXT_H_ - -#include "rx_rxpcu_classification_overview.h" -#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 - -#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4 - -struct rx_ppdu_end_user_stats_ext { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t fcs_ok_bitmap_95_64 : 32; - uint32_t fcs_ok_bitmap_127_96 : 32; - uint32_t fcs_ok_bitmap_159_128 : 32; - uint32_t fcs_ok_bitmap_191_160 : 32; - uint32_t fcs_ok_bitmap_223_192 : 32; - uint32_t fcs_ok_bitmap_255_224 : 32; - uint32_t corrupted_due_to_fifo_delay : 1, - reserved_7a : 31; -#else - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t fcs_ok_bitmap_95_64 : 32; - uint32_t fcs_ok_bitmap_127_96 : 32; - uint32_t fcs_ok_bitmap_159_128 : 32; - uint32_t fcs_ok_bitmap_191_160 : 32; - uint32_t fcs_ok_bitmap_223_192 : 32; - uint32_t fcs_ok_bitmap_255_224 : 32; - uint32_t reserved_7a : 31, - corrupted_due_to_fifo_delay : 1; -#endif -}; - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 - -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 33 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_no_ack_report.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_no_ack_report.h deleted file mode 100644 index d9c54c04df32..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_no_ack_report.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_NO_ACK_REPORT_H_ -#define _RX_PPDU_NO_ACK_REPORT_H_ - -#include "no_ack_report.h" -#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 - -#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2 - -struct rx_ppdu_no_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct no_ack_report no_ack_report_details; -#else - struct no_ack_report no_ack_report_details; -#endif -}; - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x000000000000000f - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000f0 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000000000ff00 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 32 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 55 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff00000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 56 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 56 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x0100000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 61 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 63 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0x00000000ff000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 44 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 63 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff00000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start.h deleted file mode 100644 index 19765eb4409b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_START_H_ -#define _RX_PPDU_START_H_ - -#define NUM_OF_DWORDS_RX_PPDU_START 6 - -#define NUM_OF_QWORDS_RX_PPDU_START 3 - -struct rx_ppdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - preamble_time_to_rxframe : 8, - reserved_0a : 8; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t rxframe_assert_timestamp : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 8, - preamble_time_to_rxframe : 8, - phy_ppdu_id : 16; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t rxframe_assert_timestamp : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_START_PHY_PPDU_ID_LSB 0 -#define RX_PPDU_START_PHY_PPDU_ID_MSB 15 -#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 - -#define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_PPDU_START_RESERVED_0A_LSB 24 -#define RX_PPDU_START_RESERVED_0A_MSB 31 -#define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 - -#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 -#define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 -#define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 -#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 - -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 - -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff - -#define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 -#define RX_PPDU_START_TLV64_PADDING_LSB 32 -#define RX_PPDU_START_TLV64_PADDING_MSB 63 -#define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start_user_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start_user_info.h deleted file mode 100644 index 16d3bb33edb4..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start_user_info.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_START_USER_INFO_H_ -#define _RX_PPDU_START_USER_INFO_H_ - -#include "receive_user_info.h" -#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8 - -#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 4 - -struct rx_ppdu_start_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_user_info receive_user_info_details; -#else - struct receive_user_info receive_user_info_details; -#endif -}; - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 36 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000001f00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 37 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 38 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000006000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 1 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x0000000000000002 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB 2 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB 3 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK 0x000000000000000c - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB 4 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB 5 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK 0x0000000000000030 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB 6 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB 7 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK 0x00000000000000c0 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_LSB 62 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MSB 62 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MASK 0x4000000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0x8000000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_preamble.h b/drivers/staging/fw-api/hw/fig/v2/rx_preamble.h deleted file mode 100644 index 807463753865..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_preamble.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PREAMBLE_H_ -#define _RX_PREAMBLE_H_ - -#define NUM_OF_DWORDS_RX_PREAMBLE 2 - -#define NUM_OF_QWORDS_RX_PREAMBLE 1 - -struct rx_preamble { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t num_users : 6, - pkt_type : 4, - direction : 1, - reserved_0a : 21; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 21, - direction : 1, - pkt_type : 4, - num_users : 6; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PREAMBLE_NUM_USERS_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_NUM_USERS_LSB 0 -#define RX_PREAMBLE_NUM_USERS_MSB 5 -#define RX_PREAMBLE_NUM_USERS_MASK 0x000000000000003f - -#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_PKT_TYPE_LSB 6 -#define RX_PREAMBLE_PKT_TYPE_MSB 9 -#define RX_PREAMBLE_PKT_TYPE_MASK 0x00000000000003c0 - -#define RX_PREAMBLE_DIRECTION_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_DIRECTION_LSB 10 -#define RX_PREAMBLE_DIRECTION_MSB 10 -#define RX_PREAMBLE_DIRECTION_MASK 0x0000000000000400 - -#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_RESERVED_0A_LSB 11 -#define RX_PREAMBLE_RESERVED_0A_MSB 31 -#define RX_PREAMBLE_RESERVED_0A_MASK 0x00000000fffff800 - -#define RX_PREAMBLE_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_TLV64_PADDING_LSB 32 -#define RX_PREAMBLE_TLV64_PADDING_MSB 63 -#define RX_PREAMBLE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_response_required_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_response_required_info.h deleted file mode 100644 index 11da8b5e0bb2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_response_required_info.h +++ /dev/null @@ -1,764 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ -#define _RX_RESPONSE_REQUIRED_INFO_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 - -#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 - -struct rx_response_required_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - su_or_uplink_mu_reception : 1, - trigger_frame_received : 1, - __reserved_g_0012 : 2, - tb___reserved_g_0022_response_required : 2, - mac_security : 1, - filter_pass_monitor_ovrd : 1, - ast_search_incomplete : 1, - r2r_end_status_to_follow : 1, - __reserved_g_0016_listen_cca_check_at_phy_desc : 1, - __reserved_g_0016_listen_indication : 1, - three_or_more_type_subtypes : 1, - wait_sifs_config_valid : 1, - wait_sifs : 2; - uint32_t general_frame_control : 16, - second_frame_control : 16; - uint32_t duration : 16, - pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5, - sgi : 2, - stbc : 1, - ldpc : 1, - ampdu : 1, - rts_ta_grp_bit : 1; - uint32_t ctrl_frame_soliciting_resp : 1, - ast_fail_for_dot11ax_su_ext : 1, - service_dynamic : 1, - m_pkt : 1, - sta_partial_aid : 12, - group_id : 6, - ctrl_resp_pwr_mgmt : 1, - response_indication : 2, - ndp_indication : 1, - ndp_frame_type : 3, - second_frame_control_valid : 1, - ack_ba_resp_more_data : 1, - vht_ack : 1; - uint32_t sta_aid : 11, - interference : 1, - ects_as_tb_ppdu : 1, - ll_traffic_indication : 1, - reserved_4a : 2, - ack_id_ext : 10, - agc_cbw : 3, - service_cbw : 3; - uint32_t response_sta_count : 7, - __reserved_g_0035 : 1, - blackout_details_en : 1, - reserved : 2, - ht_vht_sig_cbw : 3, - cts_cbw : 3, - response_ack_count : 7, - response_assoc_ack_count : 7, - txop_duration_all_ones : 1; - uint32_t response_ba32_count : 7, - response_ba64_count : 7, - response_ba128_count : 7, - response_ba256_count : 7, - multi_tid : 1, - sw_response_tlv_from_crypto : 1, - dot11ax_dl_ul_flag : 1, - emlsr_main_tlv_if : 1; - uint32_t sw_response_frame_length : 16, - response_ba512_count : 7, - response_ba1024_count : 7, - reserved_7a : 2; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t dot11ax_received_format_indication : 1, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_bss_color_id : 6, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_cp_size : 2, - dot11ax_received_ltf_size : 2, - dot11ax_received_coding : 1, - dot11ax_received_dcm : 1, - dot11ax_received_doppler_indication : 1, - dot11ax_received_ext_ru_size : 4, - ftm_fields_valid : 1, - ftm_pe_nss : 3, - ftm_pe_ltf_size : 2, - ftm_pe_content : 1, - ftm_chain_csd_en : 1, - ftm_pe_chain_csd_en : 1; - uint32_t dot11ax_response_rate_source : 8, - dot11ax_ext_response_rate_source : 8, - sw_peer_id : 16; - uint32_t dot11be_puncture_bitmap : 16, - dot11be_response : 1, - punctured_response : 1, - eht_duplicate_mode : 2, - force_extra_symbol : 1, - ctrl_pkt_protect : 1, - mac_hdr_protect : 1, - reserved_13a : 3, - u_sig_puncture_pattern_encoding : 6; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t he_a_control_response_time : 12, - reserved_after_struct16 : 4; - uint32_t dso_primary20_index_select : 4, - dso_freq_subband_channel_bonding_mask : 16, - pad_duration : 5, - q2q_mba : 1, - reserved_15a : 6; -#else - uint32_t wait_sifs : 2, - wait_sifs_config_valid : 1, - three_or_more_type_subtypes : 1, - __reserved_g_0016_listen_indication : 1, - __reserved_g_0016_listen_cca_check_at_phy_desc : 1, - r2r_end_status_to_follow : 1, - ast_search_incomplete : 1, - filter_pass_monitor_ovrd : 1, - mac_security : 1, - tb___reserved_g_0022_response_required : 2, - __reserved_g_0012 : 2, - trigger_frame_received : 1, - su_or_uplink_mu_reception : 1, - phy_ppdu_id : 16; - uint32_t second_frame_control : 16, - general_frame_control : 16; - uint32_t rts_ta_grp_bit : 1, - ampdu : 1, - ldpc : 1, - stbc : 1, - sgi : 2, - rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4, - duration : 16; - uint32_t vht_ack : 1, - ack_ba_resp_more_data : 1, - second_frame_control_valid : 1, - ndp_frame_type : 3, - ndp_indication : 1, - response_indication : 2, - ctrl_resp_pwr_mgmt : 1, - group_id : 6, - sta_partial_aid : 12, - m_pkt : 1, - service_dynamic : 1, - ast_fail_for_dot11ax_su_ext : 1, - ctrl_frame_soliciting_resp : 1; - uint32_t service_cbw : 3, - agc_cbw : 3, - ack_id_ext : 10, - reserved_4a : 2, - ll_traffic_indication : 1, - ects_as_tb_ppdu : 1, - interference : 1, - sta_aid : 11; - uint32_t txop_duration_all_ones : 1, - response_assoc_ack_count : 7, - response_ack_count : 7, - cts_cbw : 3, - ht_vht_sig_cbw : 3, - reserved : 2, - blackout_details_en : 1, - __reserved_g_0035 : 1, - response_sta_count : 7; - uint32_t emlsr_main_tlv_if : 1, - dot11ax_dl_ul_flag : 1, - sw_response_tlv_from_crypto : 1, - multi_tid : 1, - response_ba256_count : 7, - response_ba128_count : 7, - response_ba64_count : 7, - response_ba32_count : 7; - uint32_t reserved_7a : 2, - response_ba1024_count : 7, - response_ba512_count : 7, - sw_response_frame_length : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ftm_pe_chain_csd_en : 1, - ftm_chain_csd_en : 1, - ftm_pe_content : 1, - ftm_pe_ltf_size : 2, - ftm_pe_nss : 3, - ftm_fields_valid : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_received_doppler_indication : 1, - dot11ax_received_dcm : 1, - dot11ax_received_coding : 1, - dot11ax_received_ltf_size : 2, - dot11ax_received_cp_size : 2, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_bss_color_id : 6, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_format_indication : 1; - uint32_t sw_peer_id : 16, - dot11ax_ext_response_rate_source : 8, - dot11ax_response_rate_source : 8; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_13a : 3, - mac_hdr_protect : 1, - ctrl_pkt_protect : 1, - force_extra_symbol : 1, - eht_duplicate_mode : 2, - punctured_response : 1, - dot11be_response : 1, - dot11be_puncture_bitmap : 16; - uint32_t reserved_after_struct16 : 4, - he_a_control_response_time : 12; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint32_t reserved_15a : 6, - q2q_mba : 1, - pad_duration : 5, - dso_freq_subband_channel_bonding_mask : 16, - dso_primary20_index_select : 4; -#endif -}; - -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 - -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 - -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 - -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 - -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 - -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 - -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 - -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff - -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 - -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000003e00000 - -#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 26 -#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x000000000c000000 - -#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 30 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000040000000 - -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 - -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 - -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 - -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 - -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 - -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK 0x4000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MSB 10 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MASK 0x00000000000007ff - -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_LSB 11 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MSB 11 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MASK 0x0000000000000800 - -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_LSB 12 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MSB 12 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MASK 0x0000000000001000 - -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_LSB 13 -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_MSB 13 -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_MASK 0x0000000000002000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_LSB 14 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MASK 0x000000000000c000 - -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 - -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 - -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 - -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_LSB 40 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MSB 40 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MASK 0x0000010000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 41 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000060000000000 - -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 - -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 - -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB 31 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK 0x0000000080000000 - -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 - -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_LSB 53 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MSB 53 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MASK 0x0020000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_LSB 54 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MASK 0x0040000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x0380000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 - -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MSB 35 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MASK 0x0000000f00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 36 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 51 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000ffff000000000 - -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_LSB 52 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MSB 56 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MASK 0x01f0000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_LSB 57 -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_MASK 0x0200000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MASK 0xfc00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/fig/v2/rx_rxpcu_classification_overview.h deleted file mode 100644 index 92489a5f5b2d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_rxpcu_classification_overview.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ -#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ - -#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 - -struct rx_rxpcu_classification_overview { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t filter_pass_mpdus : 1, - filter_pass_mpdus_fcs_ok : 1, - monitor_direct_mpdus : 1, - monitor_direct_mpdus_fcs_ok : 1, - monitor_other_mpdus : 1, - monitor_other_mpdus_fcs_ok : 1, - phyrx_abort_received : 1, - filter_pass_monitor_ovrd_mpdus : 1, - filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, - reserved_0 : 7, - phy_ppdu_id : 16; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, - filter_pass_monitor_ovrd_mpdus : 1, - phyrx_abort_received : 1, - monitor_other_mpdus_fcs_ok : 1, - monitor_other_mpdus : 1, - monitor_direct_mpdus_fcs_ok : 1, - monitor_direct_mpdus : 1, - filter_pass_mpdus_fcs_ok : 1, - filter_pass_mpdus : 1; -#endif -}; - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_start_param.h b/drivers/staging/fw-api/hw/fig/v2/rx_start_param.h deleted file mode 100644 index bb2b87e3cc97..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_start_param.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_START_PARAM_H_ -#define _RX_START_PARAM_H_ - -#define NUM_OF_DWORDS_RX_START_PARAM 2 - -#define NUM_OF_QWORDS_RX_START_PARAM 1 - -struct rx_start_param { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pkt_type : 4, - reserved_0a : 12, - remaining_rx_time : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t remaining_rx_time : 16, - reserved_0a : 12, - pkt_type : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_START_PARAM_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_START_PARAM_PKT_TYPE_LSB 0 -#define RX_START_PARAM_PKT_TYPE_MSB 3 -#define RX_START_PARAM_PKT_TYPE_MASK 0x000000000000000f - -#define RX_START_PARAM_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_START_PARAM_RESERVED_0A_LSB 4 -#define RX_START_PARAM_RESERVED_0A_MSB 15 -#define RX_START_PARAM_RESERVED_0A_MASK 0x000000000000fff0 - -#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x0000000000000000 -#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 -#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 -#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0x00000000ffff0000 - -#define RX_START_PARAM_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_START_PARAM_TLV64_PADDING_LSB 32 -#define RX_START_PARAM_TLV64_PADDING_MSB 63 -#define RX_START_PARAM_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_timing_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_timing_info.h deleted file mode 100644 index ea6780e25c55..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_timing_info.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_TIMING_INFO_H_ -#define _RX_TIMING_INFO_H_ - -#define NUM_OF_DWORDS_RX_TIMING_INFO 5 - -struct rx_timing_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_timestamp_1_lower_32 : 32; - uint32_t phy_timestamp_1_upper_32 : 32; - uint32_t phy_timestamp_2_lower_32 : 32; - uint32_t phy_timestamp_2_upper_32 : 32; - uint32_t residual_phase_offset : 12, - sub_usec_ts_rx_end : 10, - reserved : 10; -#else - uint32_t phy_timestamp_1_lower_32 : 32; - uint32_t phy_timestamp_1_upper_32 : 32; - uint32_t phy_timestamp_2_lower_32 : 32; - uint32_t phy_timestamp_2_upper_32 : 32; - uint32_t reserved : 10, - sub_usec_ts_rx_end : 10, - residual_phase_offset : 12; -#endif -}; - -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000000 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000004 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x00000008 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000c -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000010 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB 0 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB 11 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff - -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_OFFSET 0x00000010 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_LSB 12 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MSB 21 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MASK 0x003ff000 - -#define RX_TIMING_INFO_RESERVED_OFFSET 0x00000010 -#define RX_TIMING_INFO_RESERVED_LSB 22 -#define RX_TIMING_INFO_RESERVED_MSB 31 -#define RX_TIMING_INFO_RESERVED_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_trig_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_trig_info.h deleted file mode 100644 index b6b074118bea..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_trig_info.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_TRIG_INFO_H_ -#define _RX_TRIG_INFO_H_ - -#define NUM_OF_DWORDS_RX_TRIG_INFO 2 - -#define NUM_OF_QWORDS_RX_TRIG_INFO 1 - -struct rx_trig_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_trigger_frame_type : 2, - trigger_resp_type : 3, - reserved_0 : 27; - uint32_t ppdu_duration : 16, - unique_destination_id : 16; -#else - uint32_t reserved_0 : 27, - trigger_resp_type : 3, - rx_trigger_frame_type : 2; - uint32_t unique_destination_id : 16, - ppdu_duration : 16; -#endif -}; - -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003 - -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c - -#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_RESERVED_0_LSB 5 -#define RX_TRIG_INFO_RESERVED_0_MSB 31 -#define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0 - -#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_PPDU_DURATION_LSB 32 -#define RX_TRIG_INFO_PPDU_DURATION_MSB 47 -#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000 - -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rxpcu_early_rx_indication.h b/drivers/staging/fw-api/hw/fig/v2/rxpcu_early_rx_indication.h deleted file mode 100644 index d2dc464cf1cf..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rxpcu_early_rx_indication.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_EARLY_RX_INDICATION_H_ -#define _RXPCU_EARLY_RX_INDICATION_H_ - -#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2 - -#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1 - -struct rxpcu_early_rx_indication { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5, - dot11ax_received_ext_ru_size : 4, - reserved_0a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 18, - dot11ax_received_ext_ru_size : 4, - rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x000000000000000f - -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x0000000000000010 - -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 9 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x00000000000003e0 - -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 10 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 13 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0000000000003c00 - -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 14 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0x00000000ffffc000 - -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB 32 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB 63 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_info.h deleted file mode 100644 index c97ad08c26a4..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_info.h +++ /dev/null @@ -1,925 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_PPDU_END_INFO_H_ -#define _RXPCU_PPDU_END_INFO_H_ - -#include "phyrx_abort_request_info.h" -#include "macrx_abort_request_info.h" -#include "rxpcu_ppdu_end_layout_info.h" -#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 32 - -#define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 16 - -struct rxpcu_ppdu_end_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t wb_timestamp_lower_32 : 32; - uint32_t wb_timestamp_upper_32 : 32; - uint32_t rx_antenna : 24, - tx_ht_vht_ack : 1, - unsupported_mu_nc : 1, - otp_txbf_disable : 1, - previous_tlv_corrupted : 1, - phyrx_abort_request_info_valid : 1, - macrx_abort_request_info_valid : 1, - coex_wan_tx_from_start_of_rx_ratid1 : 1, - coex_wan_tx_after_start_of_rx_ratid1 : 1; - uint32_t coex_bt_tx_from_start_of_rx : 1, - coex_bt_tx_after_start_of_rx : 1, - coex_wan_tx_from_start_of_rx : 1, - coex_wan_tx_after_start_of_rx : 1, - coex_wlan_tx_from_start_of_rx : 1, - coex_wlan_tx_after_start_of_rx : 1, - mpdu_delimiter_errors_seen : 1, - __reserved_g_0012 : 2, - dialog_token : 8, - follow_up_dialog_token : 8, - bb_captured_channel : 1, - bb_captured_reason : 3, - bb_captured_timeout : 1, - __reserved_g_0054 : 1, - __reserved_g_0058 : 1; - uint32_t before_mpdu_count_passing_fcs : 10, - before_mpdu_count_failing_fcs : 10, - after_mpdu_count_passing_fcs : 10, - reserved_4 : 2; - uint32_t after_mpdu_count_failing_fcs : 10, - reserved_5 : 22; - uint32_t phy_timestamp_tx_lower_32 : 32; - uint32_t phy_timestamp_tx_upper_32 : 32; - uint32_t bb_length : 16, - bb_data : 1, - reserved_8 : 3, - first_bt_broadcast_status_details : 12; - uint32_t rx_ppdu_duration : 24, - reserved_9 : 8; - uint32_t ast_index : 16, - ast_index_valid : 1, - reserved_10 : 3, - second_bt_broadcast_status_details : 12; - struct phyrx_abort_request_info phyrx_abort_request_info_details; - struct macrx_abort_request_info macrx_abort_request_info_details; - uint16_t pre_bt_broadcast_status_details : 12, - reserved_12a : 4; - uint32_t non_qos_sn_info_valid : 1, - rts_or_trig_protected_ppdu : 1, - rts_or_trig_prot_type : 2, - reserved_13a : 2, - non_qos_sn_highest : 12, - non_qos_sn_highest_retry_setting : 1, - non_qos_sn_lowest : 12, - non_qos_sn_lowest_retry_setting : 1; - uint32_t qos_sn_1_info_valid : 1, - reserved_14a : 1, - qos_sn_1_tid : 4, - qos_sn_1_highest : 12, - qos_sn_1_highest_retry_setting : 1, - qos_sn_1_lowest : 12, - qos_sn_1_lowest_retry_setting : 1; - uint32_t qos_sn_2_info_valid : 1, - reserved_15a : 1, - qos_sn_2_tid : 4, - qos_sn_2_highest : 12, - qos_sn_2_highest_retry_setting : 1, - qos_sn_2_lowest : 12, - qos_sn_2_lowest_retry_setting : 1; - struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; - uint32_t corrupted_due_to_fifo_delay : 1, - qos_sn_1_more_frag_state : 1, - qos_sn_1_frag_num_state : 4, - qos_sn_2_more_frag_state : 1, - qos_sn_2_frag_num_state : 4, - rts_or_trig_prot_non_11a : 1, - rts_or_trig_prot_rate_mcs : 4, - rts_or_trig_prot_peer_addr_15_0 : 16; - uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; - uint32_t rts_or_trig_rx_count : 32; - uint32_t cts_or_null_tx_count : 32; - uint32_t coex_tracker2_tx_from_start_of_rx : 1, - coex_tracker2_tx_after_start_of_rx : 1, - coex_tracker3_tx_from_start_of_rx : 1, - coex_tracker3_tx_after_start_of_rx : 1, - coex_tracker4_tx_from_start_of_rx : 1, - coex_tracker4_tx_after_start_of_rx : 1, - coex_tracker5_tx_from_start_of_rx : 1, - coex_tracker5_tx_after_start_of_rx : 1, - coex_tracker6_tx_from_start_of_rx : 1, - coex_tracker6_tx_after_start_of_rx : 1, - reserved_30a : 22; - uint32_t rx_ppdu_end_marker : 32; -#else - uint32_t wb_timestamp_lower_32 : 32; - uint32_t wb_timestamp_upper_32 : 32; - uint32_t coex_wan_tx_after_start_of_rx_ratid1 : 1, - coex_wan_tx_from_start_of_rx_ratid1 : 1, - macrx_abort_request_info_valid : 1, - phyrx_abort_request_info_valid : 1, - previous_tlv_corrupted : 1, - otp_txbf_disable : 1, - unsupported_mu_nc : 1, - tx_ht_vht_ack : 1, - rx_antenna : 24; - uint32_t __reserved_g_0058 : 1, - __reserved_g_0054 : 1, - bb_captured_timeout : 1, - bb_captured_reason : 3, - bb_captured_channel : 1, - follow_up_dialog_token : 8, - dialog_token : 8, - __reserved_g_0012 : 2, - mpdu_delimiter_errors_seen : 1, - coex_wlan_tx_after_start_of_rx : 1, - coex_wlan_tx_from_start_of_rx : 1, - coex_wan_tx_after_start_of_rx : 1, - coex_wan_tx_from_start_of_rx : 1, - coex_bt_tx_after_start_of_rx : 1, - coex_bt_tx_from_start_of_rx : 1; - uint32_t reserved_4 : 2, - after_mpdu_count_passing_fcs : 10, - before_mpdu_count_failing_fcs : 10, - before_mpdu_count_passing_fcs : 10; - uint32_t reserved_5 : 22, - after_mpdu_count_failing_fcs : 10; - uint32_t phy_timestamp_tx_lower_32 : 32; - uint32_t phy_timestamp_tx_upper_32 : 32; - uint32_t first_bt_broadcast_status_details : 12, - reserved_8 : 3, - bb_data : 1, - bb_length : 16; - uint32_t reserved_9 : 8, - rx_ppdu_duration : 24; - uint32_t second_bt_broadcast_status_details : 12, - reserved_10 : 3, - ast_index_valid : 1, - ast_index : 16; - struct phyrx_abort_request_info phyrx_abort_request_info_details; - uint32_t reserved_12a : 4, - pre_bt_broadcast_status_details : 12; - struct macrx_abort_request_info macrx_abort_request_info_details; - uint32_t non_qos_sn_lowest_retry_setting : 1, - non_qos_sn_lowest : 12, - non_qos_sn_highest_retry_setting : 1, - non_qos_sn_highest : 12, - reserved_13a : 2, - rts_or_trig_prot_type : 2, - rts_or_trig_protected_ppdu : 1, - non_qos_sn_info_valid : 1; - uint32_t qos_sn_1_lowest_retry_setting : 1, - qos_sn_1_lowest : 12, - qos_sn_1_highest_retry_setting : 1, - qos_sn_1_highest : 12, - qos_sn_1_tid : 4, - reserved_14a : 1, - qos_sn_1_info_valid : 1; - uint32_t qos_sn_2_lowest_retry_setting : 1, - qos_sn_2_lowest : 12, - qos_sn_2_highest_retry_setting : 1, - qos_sn_2_highest : 12, - qos_sn_2_tid : 4, - reserved_15a : 1, - qos_sn_2_info_valid : 1; - struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; - uint32_t rts_or_trig_prot_peer_addr_15_0 : 16, - rts_or_trig_prot_rate_mcs : 4, - rts_or_trig_prot_non_11a : 1, - qos_sn_2_frag_num_state : 4, - qos_sn_2_more_frag_state : 1, - qos_sn_1_frag_num_state : 4, - qos_sn_1_more_frag_state : 1, - corrupted_due_to_fifo_delay : 1; - uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; - uint32_t rts_or_trig_rx_count : 32; - uint32_t cts_or_null_tx_count : 32; - uint32_t reserved_30a : 22, - coex_tracker6_tx_after_start_of_rx : 1, - coex_tracker6_tx_from_start_of_rx : 1, - coex_tracker5_tx_after_start_of_rx : 1, - coex_tracker5_tx_from_start_of_rx : 1, - coex_tracker4_tx_after_start_of_rx : 1, - coex_tracker4_tx_from_start_of_rx : 1, - coex_tracker3_tx_after_start_of_rx : 1, - coex_tracker3_tx_from_start_of_rx : 1, - coex_tracker2_tx_after_start_of_rx : 1, - coex_tracker2_tx_from_start_of_rx : 1; - uint32_t rx_ppdu_end_marker : 32; -#endif -}; - -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff - -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 - -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 - -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 - -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_LSB 30 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MSB 30 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MASK 0x0000000040000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_LSB 31 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MSB 31 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MASK 0x0000000080000000 - -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 - -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 - -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 - -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 - -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 - -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 - -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff - -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 - -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 - -#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 -#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 - -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 -#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 -#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 - -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff - -#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 -#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 -#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 - -#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 -#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 -#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 - -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 - -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 -#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 -#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 - -#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 -#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 -#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff - -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 - -#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 -#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 -#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 - -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 42 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 42 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x0000040000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB 43 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB 43 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x0000080000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 44 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 44 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x0000100000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB 45 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB 45 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK 0x0000200000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB 46 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB 46 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK 0x0000400000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 47 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000800000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 - -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 - -#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB 33 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB 33 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB 34 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB 35 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK 0x0000000c00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 36 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB 11 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB 11 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK 0x0000000000000800 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB 12 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB 15 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK 0x000000000000f000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB 16 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB 31 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK 0x00000000ffff0000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB 32 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB 63 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET 0x0000000000000070 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB 0 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB 31 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET 0x0000000000000070 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB 32 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB 63 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_LSB 0 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MSB 0 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_LSB 1 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MSB 1 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_LSB 2 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MSB 2 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MASK 0x0000000000000004 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_LSB 3 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MSB 3 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MASK 0x0000000000000008 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_LSB 4 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MSB 4 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MASK 0x0000000000000010 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_LSB 5 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MSB 5 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MASK 0x0000000000000020 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_LSB 6 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MSB 6 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MASK 0x0000000000000040 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_LSB 7 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MSB 7 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MASK 0x0000000000000080 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_LSB 8 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MSB 8 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MASK 0x0000000000000100 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_LSB 9 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MSB 9 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MASK 0x0000000000000200 - -#define RXPCU_PPDU_END_INFO_RESERVED_30A_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_LSB 10 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_MASK 0x00000000fffffc00 - -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_layout_info.h b/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_layout_info.h deleted file mode 100644 index 9d54e91522ec..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_layout_info.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ -#define _RXPCU_PPDU_END_LAYOUT_INFO_H_ - -#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 - -struct rxpcu_ppdu_end_layout_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rssi_legacy_offset : 2, - l_sig_a_offset : 6, - l_sig_b_offset : 6, - ht_sig_offset : 6, - vht_sig_a_offset : 6, - repeat_l_sig_a_offset : 6; - uint32_t he_sig_a_su_offset : 6, - he_sig_a_mu_dl_offset : 6, - he_sig_a_mu_ul_offset : 6, - generic_u_sig_offset : 6, - rssi_ht_offset : 7, - reserved_1a : 1; - uint32_t vht_sig_b_su20_offset : 7, - vht_sig_b_su40_offset : 7, - vht_sig_b_su80_offset : 7, - vht_sig_b_su160_offset : 7, - reserved_2a : 4; - uint32_t vht_sig_b_mu20_offset : 7, - vht_sig_b_mu40_offset : 7, - vht_sig_b_mu80_offset : 7, - vht_sig_b_mu160_offset : 7, - reserved_3a : 4; - uint32_t he_sig_b1_mu_offset : 7, - he_sig_b2_mu_offset : 7, - he_sig_b2_ofdma_offset : 7, - first_generic_eht_sig_offset : 7, - multiple_generic_eht_sig_included : 1, - reserved_4a : 3; - uint32_t common_user_info_offset : 7, - first_debug_info_offset : 8, - multiple_debug_info_included : 1, - first_other_receive_info_offset : 8, - multiple_other_receive_info_included : 1, - reserved_5a : 7; - uint32_t data_done_offset : 8, - generated_cbf_details_offset : 8, - pkt_end_part1_offset : 8, - location_offset : 8; - uint32_t __reserved_g_0011 : 8, - pkt_end_offset : 8, - abort_request_ack_offset : 8, - reserved_7a : 8; - uint32_t reserved_8a : 32; - uint32_t reserved_9a : 32; -#else - uint32_t repeat_l_sig_a_offset : 6, - vht_sig_a_offset : 6, - ht_sig_offset : 6, - l_sig_b_offset : 6, - l_sig_a_offset : 6, - rssi_legacy_offset : 2; - uint32_t reserved_1a : 1, - rssi_ht_offset : 7, - generic_u_sig_offset : 6, - he_sig_a_mu_ul_offset : 6, - he_sig_a_mu_dl_offset : 6, - he_sig_a_su_offset : 6; - uint32_t reserved_2a : 4, - vht_sig_b_su160_offset : 7, - vht_sig_b_su80_offset : 7, - vht_sig_b_su40_offset : 7, - vht_sig_b_su20_offset : 7; - uint32_t reserved_3a : 4, - vht_sig_b_mu160_offset : 7, - vht_sig_b_mu80_offset : 7, - vht_sig_b_mu40_offset : 7, - vht_sig_b_mu20_offset : 7; - uint32_t reserved_4a : 3, - multiple_generic_eht_sig_included : 1, - first_generic_eht_sig_offset : 7, - he_sig_b2_ofdma_offset : 7, - he_sig_b2_mu_offset : 7, - he_sig_b1_mu_offset : 7; - uint32_t reserved_5a : 7, - multiple_other_receive_info_included : 1, - first_other_receive_info_offset : 8, - multiple_debug_info_included : 1, - first_debug_info_offset : 8, - common_user_info_offset : 7; - uint32_t location_offset : 8, - pkt_end_part1_offset : 8, - generated_cbf_details_offset : 8, - data_done_offset : 8; - uint32_t reserved_7a : 8, - abort_request_ack_offset : 8, - pkt_end_offset : 8, - __reserved_g_0011 : 8; - uint32_t reserved_8a : 32; - uint32_t reserved_9a : 32; -#endif -}; - -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 - -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc - -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff - -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rxpt_classify_info.h b/drivers/staging/fw-api/hw/fig/v2/rxpt_classify_info.h deleted file mode 100644 index 7fc572ae2474..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rxpt_classify_info.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPT_CLASSIFY_INFO_H_ -#define _RXPT_CLASSIFY_INFO_H_ - -#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 - -struct rxpt_classify_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reo_destination_indication : 5, - lmac_peer_id_msb : 2, - use_flow_id_toeplitz_clfy : 1, - pkt_selection_fp_ucast_data : 1, - pkt_selection_fp_mcast_data : 1, - pkt_selection_fp_1000 : 1, - rxdma0_source_ring_selection : 3, - rxdma0_destination_ring_selection : 3, - mcast_echo_drop_enable : 1, - wds_learning_detect_en : 1, - intrabss_check_en : 1, - use_ppe : 1, - ppe_routing_enable : 1, - cce_source_sel_en : 1, - reserved_0b : 9; -#else - uint32_t reserved_0b : 9, - cce_source_sel_en : 1, - ppe_routing_enable : 1, - use_ppe : 1, - intrabss_check_en : 1, - wds_learning_detect_en : 1, - mcast_echo_drop_enable : 1, - rxdma0_destination_ring_selection : 3, - rxdma0_source_ring_selection : 3, - pkt_selection_fp_1000 : 1, - pkt_selection_fp_mcast_data : 1, - pkt_selection_fp_ucast_data : 1, - use_flow_id_toeplitz_clfy : 1, - lmac_peer_id_msb : 2, - reo_destination_indication : 5; -#endif -}; - -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060 - -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400 - -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 - -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 - -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 - -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000 - -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000 - -#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20 -#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20 -#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000 - -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000 - -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB 22 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB 22 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK 0x00400000 - -#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 23 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xff800000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/seq_hwio.h b/drivers/staging/fw-api/hw/fig/v2/seq_hwio.h deleted file mode 100644 index 69111d08d535..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/seq_hwio.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef __SEQ_H__ -#define __SEQ_H__ - -#include "HALhwio.h" - -#define SEQ_INH(base, regtype, reg) \ - SEQ_##regtype##_INH(base, reg) - -#define SEQ_INMH(base, regtype, reg, mask) \ - SEQ_##regtype##_INMH(base, reg, mask) - -#define SEQ_INFH(base, regtype, reg, fld) \ - (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) - -#define SEQ_OUTH(base, regtype, reg, val) \ - SEQ_##regtype##_OUTH(base, reg, val) - -#define SEQ_OUTMH(base, regtype, reg, mask, val) \ - SEQ_##regtype##_OUTMH(base, reg, mask, val) - -#define SEQ_OUTFH(base, regtype, reg, fld, val) \ - SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) - -typedef enum { - SEC, - MS, - US, - NS -} SEQ_TimeUnit; - -extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); - -extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); - -#endif - diff --git a/drivers/staging/fw-api/hw/fig/v2/tcl_assist_cmd.h b/drivers/staging/fw-api/hw/fig/v2/tcl_assist_cmd.h deleted file mode 100644 index f7a5bd5287cb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tcl_assist_cmd.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TCL_ASSIST_CMD_H_ -#define _TCL_ASSIST_CMD_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_TCL_ASSIST_CMD 16 - -struct tcl_assist_cmd { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_addr_info; - uint32_t buf_or_ext_desc_type : 1, - bank_id : 6, - vdev_id : 8, - data_length : 14, - to_fw_tqm : 2, - reserved_2a : 1; - uint32_t reserved_3a : 25, - metadata_length : 7; - uint32_t txpt_classify_info_index : 8, - txpt_classify_info_sel : 5, - txpt_classify_info_override : 1, - flow_override_enable : 1, - flow_select : 1, - hlos_tid : 4, - hlos_tid_overwrite : 1, - tos_tc_value : 8, - reserved_4a : 3; - uint32_t reserved_5a : 16, - l3_type : 16; - uint32_t l4_protocol : 8, - l4_port : 16, - l4_port_type : 1, - da_is_bcast_mcast : 1, - da_is_bcast : 1, - reserved_6a : 5; - uint32_t ip_address_31_0 : 32; - uint32_t ip_address_63_32 : 32; - uint32_t ip_address_95_64 : 32; - uint32_t ip_address_127_96 : 32; - uint32_t ip_da_or_sa : 1, - encap_length_change : 6, - encap_length_decrease : 1, - encap_length_override : 1, - type_or_length : 1, - snap_oui_zero_or_f8 : 1, - snap_oui_not_zero_and_not_f8 : 1, - msdu_color : 2, - tx_notify_frame : 3, - tqm_no_drop : 1, - reserved_11a : 12, - l3_checksum_enable : 1, - l4_checksum_enable : 1; - uint32_t buffer_timestamp : 19, - buffer_timestamp_valid : 1, - s_vlan_tag_present : 1, - c_vlan_tag_present : 1, - wmac_hdr_len : 7, - reserved_12a : 3; - uint32_t tcl_cmd_number : 32; - uint32_t reserved_14a : 32; - uint32_t reserved_15a : 20, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_addr_info; - uint32_t reserved_2a : 1, - to_fw_tqm : 2, - data_length : 14, - vdev_id : 8, - bank_id : 6, - buf_or_ext_desc_type : 1; - uint32_t metadata_length : 7, - reserved_3a : 25; - uint32_t reserved_4a : 3, - tos_tc_value : 8, - hlos_tid_overwrite : 1, - hlos_tid : 4, - flow_select : 1, - flow_override_enable : 1, - txpt_classify_info_override : 1, - txpt_classify_info_sel : 5, - txpt_classify_info_index : 8; - uint32_t l3_type : 16, - reserved_5a : 16; - uint32_t reserved_6a : 5, - da_is_bcast : 1, - da_is_bcast_mcast : 1, - l4_port_type : 1, - l4_port : 16, - l4_protocol : 8; - uint32_t ip_address_31_0 : 32; - uint32_t ip_address_63_32 : 32; - uint32_t ip_address_95_64 : 32; - uint32_t ip_address_127_96 : 32; - uint32_t l4_checksum_enable : 1, - l3_checksum_enable : 1, - reserved_11a : 12, - tqm_no_drop : 1, - tx_notify_frame : 3, - msdu_color : 2, - snap_oui_not_zero_and_not_f8 : 1, - snap_oui_zero_or_f8 : 1, - type_or_length : 1, - encap_length_override : 1, - encap_length_decrease : 1, - encap_length_change : 6, - ip_da_or_sa : 1; - uint32_t reserved_12a : 3, - wmac_hdr_len : 7, - c_vlan_tag_present : 1, - s_vlan_tag_present : 1, - buffer_timestamp_valid : 1, - buffer_timestamp : 19; - uint32_t tcl_cmd_number : 32; - uint32_t reserved_14a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_15a : 20; -#endif -}; - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_LSB 0 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MSB 0 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001 - -#define TCL_ASSIST_CMD_BANK_ID_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_BANK_ID_LSB 1 -#define TCL_ASSIST_CMD_BANK_ID_MSB 6 -#define TCL_ASSIST_CMD_BANK_ID_MASK 0x0000007e - -#define TCL_ASSIST_CMD_VDEV_ID_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_VDEV_ID_LSB 7 -#define TCL_ASSIST_CMD_VDEV_ID_MSB 14 -#define TCL_ASSIST_CMD_VDEV_ID_MASK 0x00007f80 - -#define TCL_ASSIST_CMD_DATA_LENGTH_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_DATA_LENGTH_LSB 15 -#define TCL_ASSIST_CMD_DATA_LENGTH_MSB 28 -#define TCL_ASSIST_CMD_DATA_LENGTH_MASK 0x1fff8000 - -#define TCL_ASSIST_CMD_TO_FW_TQM_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_TO_FW_TQM_LSB 29 -#define TCL_ASSIST_CMD_TO_FW_TQM_MSB 30 -#define TCL_ASSIST_CMD_TO_FW_TQM_MASK 0x60000000 - -#define TCL_ASSIST_CMD_RESERVED_2A_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_RESERVED_2A_LSB 31 -#define TCL_ASSIST_CMD_RESERVED_2A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_2A_MASK 0x80000000 - -#define TCL_ASSIST_CMD_RESERVED_3A_OFFSET 0x0000000c -#define TCL_ASSIST_CMD_RESERVED_3A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_3A_MSB 24 -#define TCL_ASSIST_CMD_RESERVED_3A_MASK 0x01ffffff - -#define TCL_ASSIST_CMD_METADATA_LENGTH_OFFSET 0x0000000c -#define TCL_ASSIST_CMD_METADATA_LENGTH_LSB 25 -#define TCL_ASSIST_CMD_METADATA_LENGTH_MSB 31 -#define TCL_ASSIST_CMD_METADATA_LENGTH_MASK 0xfe000000 - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_LSB 0 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MSB 7 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MASK 0x000000ff - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_LSB 8 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MSB 12 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MASK 0x00001f00 - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_LSB 13 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MSB 13 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MASK 0x00002000 - -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_LSB 14 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MSB 14 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00004000 - -#define TCL_ASSIST_CMD_FLOW_SELECT_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_FLOW_SELECT_LSB 15 -#define TCL_ASSIST_CMD_FLOW_SELECT_MSB 15 -#define TCL_ASSIST_CMD_FLOW_SELECT_MASK 0x00008000 - -#define TCL_ASSIST_CMD_HLOS_TID_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_HLOS_TID_LSB 16 -#define TCL_ASSIST_CMD_HLOS_TID_MSB 19 -#define TCL_ASSIST_CMD_HLOS_TID_MASK 0x000f0000 - -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_LSB 20 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MSB 20 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MASK 0x00100000 - -#define TCL_ASSIST_CMD_TOS_TC_VALUE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_LSB 21 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_MSB 28 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_MASK 0x1fe00000 - -#define TCL_ASSIST_CMD_RESERVED_4A_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_RESERVED_4A_LSB 29 -#define TCL_ASSIST_CMD_RESERVED_4A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_4A_MASK 0xe0000000 - -#define TCL_ASSIST_CMD_RESERVED_5A_OFFSET 0x00000014 -#define TCL_ASSIST_CMD_RESERVED_5A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_5A_MSB 15 -#define TCL_ASSIST_CMD_RESERVED_5A_MASK 0x0000ffff - -#define TCL_ASSIST_CMD_L3_TYPE_OFFSET 0x00000014 -#define TCL_ASSIST_CMD_L3_TYPE_LSB 16 -#define TCL_ASSIST_CMD_L3_TYPE_MSB 31 -#define TCL_ASSIST_CMD_L3_TYPE_MASK 0xffff0000 - -#define TCL_ASSIST_CMD_L4_PROTOCOL_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PROTOCOL_LSB 0 -#define TCL_ASSIST_CMD_L4_PROTOCOL_MSB 7 -#define TCL_ASSIST_CMD_L4_PROTOCOL_MASK 0x000000ff - -#define TCL_ASSIST_CMD_L4_PORT_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PORT_LSB 8 -#define TCL_ASSIST_CMD_L4_PORT_MSB 23 -#define TCL_ASSIST_CMD_L4_PORT_MASK 0x00ffff00 - -#define TCL_ASSIST_CMD_L4_PORT_TYPE_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_LSB 24 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_MSB 24 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_MASK 0x01000000 - -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_LSB 25 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MSB 25 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MASK 0x02000000 - -#define TCL_ASSIST_CMD_DA_IS_BCAST_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_DA_IS_BCAST_LSB 26 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MSB 26 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MASK 0x04000000 - -#define TCL_ASSIST_CMD_RESERVED_6A_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_RESERVED_6A_LSB 27 -#define TCL_ASSIST_CMD_RESERVED_6A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_6A_MASK 0xf8000000 - -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_OFFSET 0x0000001c -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_OFFSET 0x00000020 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_OFFSET 0x00000024 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_OFFSET 0x00000028 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_DA_OR_SA_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_IP_DA_OR_SA_LSB 0 -#define TCL_ASSIST_CMD_IP_DA_OR_SA_MSB 0 -#define TCL_ASSIST_CMD_IP_DA_OR_SA_MASK 0x00000001 - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_LSB 1 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MSB 6 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MASK 0x0000007e - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_LSB 7 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MSB 7 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MASK 0x00000080 - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_LSB 8 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MSB 8 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MASK 0x00000100 - -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_LSB 9 -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MSB 9 -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MASK 0x00000200 - -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_LSB 10 -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MSB 10 -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MASK 0x00000400 - -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_LSB 11 -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MSB 11 -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MASK 0x00000800 - -#define TCL_ASSIST_CMD_MSDU_COLOR_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_MSDU_COLOR_LSB 12 -#define TCL_ASSIST_CMD_MSDU_COLOR_MSB 13 -#define TCL_ASSIST_CMD_MSDU_COLOR_MASK 0x00003000 - -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_LSB 14 -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MSB 16 -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MASK 0x0001c000 - -#define TCL_ASSIST_CMD_TQM_NO_DROP_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TQM_NO_DROP_LSB 17 -#define TCL_ASSIST_CMD_TQM_NO_DROP_MSB 17 -#define TCL_ASSIST_CMD_TQM_NO_DROP_MASK 0x00020000 - -#define TCL_ASSIST_CMD_RESERVED_11A_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_RESERVED_11A_LSB 18 -#define TCL_ASSIST_CMD_RESERVED_11A_MSB 29 -#define TCL_ASSIST_CMD_RESERVED_11A_MASK 0x3ffc0000 - -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_LSB 30 -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MSB 30 -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MASK 0x40000000 - -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_LSB 31 -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MSB 31 -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MASK 0x80000000 - -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_LSB 0 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MSB 18 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MASK 0x0007ffff - -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_LSB 19 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MSB 19 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x00080000 - -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_LSB 20 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MSB 20 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MASK 0x00100000 - -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_LSB 21 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MSB 21 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MASK 0x00200000 - -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_LSB 22 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MSB 28 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MASK 0x1fc00000 - -#define TCL_ASSIST_CMD_RESERVED_12A_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_RESERVED_12A_LSB 29 -#define TCL_ASSIST_CMD_RESERVED_12A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_12A_MASK 0xe0000000 - -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_OFFSET 0x00000034 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_LSB 0 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MSB 31 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MASK 0xffffffff - -#define TCL_ASSIST_CMD_RESERVED_14A_OFFSET 0x00000038 -#define TCL_ASSIST_CMD_RESERVED_14A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_14A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_14A_MASK 0xffffffff - -#define TCL_ASSIST_CMD_RESERVED_15A_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_RESERVED_15A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_15A_MSB 19 -#define TCL_ASSIST_CMD_RESERVED_15A_MASK 0x000fffff - -#define TCL_ASSIST_CMD_RING_ID_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_RING_ID_LSB 20 -#define TCL_ASSIST_CMD_RING_ID_MSB 27 -#define TCL_ASSIST_CMD_RING_ID_MASK 0x0ff00000 - -#define TCL_ASSIST_CMD_LOOPING_COUNT_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_LOOPING_COUNT_LSB 28 -#define TCL_ASSIST_CMD_LOOPING_COUNT_MSB 31 -#define TCL_ASSIST_CMD_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tcl_status_ring.h b/drivers/staging/fw-api/hw/fig/v2/tcl_status_ring.h deleted file mode 100644 index 5a24217c95d5..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tcl_status_ring.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TCL_STATUS_RING_H_ -#define _TCL_STATUS_RING_H_ - -#define NUM_OF_DWORDS_TCL_STATUS_RING 8 - -struct tcl_status_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t gse_ctrl : 4, - ase_fse_sel : 1, - cache_op_res : 2, - index_search_en : 1, - msdu_cnt_n : 24; - uint32_t msdu_byte_cnt_n : 32; - uint32_t msdu_timestmp_n : 32; - uint32_t cmd_meta_data_31_0 : 32; - uint32_t cmd_meta_data_63_32 : 32; - uint32_t hash_indx_val : 20, - cache_set_num : 4, - reserved_5a : 8; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 20, - ring_id : 8, - looping_count : 4; -#else - uint32_t msdu_cnt_n : 24, - index_search_en : 1, - cache_op_res : 2, - ase_fse_sel : 1, - gse_ctrl : 4; - uint32_t msdu_byte_cnt_n : 32; - uint32_t msdu_timestmp_n : 32; - uint32_t cmd_meta_data_31_0 : 32; - uint32_t cmd_meta_data_63_32 : 32; - uint32_t reserved_5a : 8, - cache_set_num : 4, - hash_indx_val : 20; - uint32_t reserved_6a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_7a : 20; -#endif -}; - -#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 -#define TCL_STATUS_RING_GSE_CTRL_LSB 0 -#define TCL_STATUS_RING_GSE_CTRL_MSB 3 -#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f - -#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 -#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 -#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 -#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 - -#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 -#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 -#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 -#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 - -#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 - -#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 -#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 -#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 -#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 - -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff - -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff - -#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c -#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 -#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 -#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff - -#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff - -#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 -#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 -#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 -#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff - -#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 -#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 -#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 -#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 - -#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 -#define TCL_STATUS_RING_RESERVED_5A_LSB 24 -#define TCL_STATUS_RING_RESERVED_5A_MSB 31 -#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 - -#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 -#define TCL_STATUS_RING_RESERVED_6A_LSB 0 -#define TCL_STATUS_RING_RESERVED_6A_MSB 31 -#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff - -#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c -#define TCL_STATUS_RING_RESERVED_7A_LSB 0 -#define TCL_STATUS_RING_RESERVED_7A_MSB 19 -#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff - -#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c -#define TCL_STATUS_RING_RING_ID_LSB 20 -#define TCL_STATUS_RING_RING_ID_MSB 27 -#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 - -#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 -#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 -#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tlv_hdr.h b/drivers/staging/fw-api/hw/fig/v2/tlv_hdr.h deleted file mode 100644 index a2defe7be508..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tlv_hdr.h +++ /dev/null @@ -1,634 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TLV_HDR_H_ -#define _TLV_HDR_H_ - -#define _TLV_USERID_WIDTH_ 6 - -#define _TLV_MRV_EN_LEN_WIDTH_ 9 -#define _TLV_MRV_DIS_LEN_WIDTH_ 12 - -#define _TLV_DATA_WIDTH_ 32 -#define _TLV_64_DATA_WIDTH_ 64 -#define _TLV_CDATA_WIDTH_ 32 -#define _TLV_77_DATA_WIDTH_ 77 -#define _TLV_CDATA_77_WIDTH_ 64 - -#define _TLV_TAG_WIDTH_ 10 -#define _TLV_CTAG_WIDTH_ 6 - -struct tlv_mlo_usr_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mlo_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_32_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_32_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : 6; -#else - uint32_t tlv_reserved : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_64_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_64_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_c_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata_lower_52 : 52; - uint64_t tlv_cdata_upper_12 : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - tlv_cdata_upper_12 : 12; - uint64_t tlv_cdata_lower_52 : 52, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_; -#endif -}; - -struct tlv_mlo_usr_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mlo_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_reserved : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mac_usr_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mac_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_reserved : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_usr_c_77_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata_lower_20 : 20; - uint32_t tlv_cdata_middle_32 : 32; - uint32_t tlv_cdata_upper_12 : 12, - tlv_compression : 1, - pad_77to96_bit : 19; - uint32_t pad_96to128_bit : 32; -#else - uint32_t tlv_cdata_lower_20 : 20, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_; - uint32_t tlv_cdata_middle_32 : 32; - uint32_t pad_77to96_bit : 20, - tlv_compression : 1, - tlv_cdata_upper_12 : 12; - uint32_t pad_96to128_bit : 32; -#endif -}; - -struct tlv_usr_32_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_reserved : 32; -#else - uint64_t tlv_reserved : 32, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_32_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : 6, - pad_32to64_bit : 32; -#else - uint64_t pad_32to64_bit : 32, - tlv_reserved : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_77_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint32_t pad_64to75_bit : 12, - tlv_compression : 1, - pad_77to95_bit : 19; -#else - uint32_t pad_77to95_bit : 19, - tlv_compression : 1, - pad_64to75_bit : 12; - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_77_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint32_t pad_64to75_bit : 12, - tlv_compression : 1, - pad_77to96_bit : 19; -#else - uint32_t pad_77to96_bit : 19, - tlv_compression : 1, - pad_64to75_bit : 12; - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_c_44_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata : _TLV_CDATA_WIDTH_, - pad_44to64_bit : 20; -#else - uint64_t tlv_cdata_lower_20 : 20, - pad_44to64_bit : 20, - tlv_cdata_upper_12 : 12; - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_, -#endif -}; - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tlv_tag_def.h b/drivers/staging/fw-api/hw/fig/v2/tlv_tag_def.h deleted file mode 100644 index 27ccee515a00..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tlv_tag_def.h +++ /dev/null @@ -1,1948 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TLV_TAG_DEF_ -#define _TLV_TAG_DEF_ - -typedef enum tlv_tag_def { - WIFIMACTX_CBF_START_E = 0 , - WIFIPHYRX_DATA_E = 1 , - WIFIPHYRX_CBF_DATA_RESP_E = 2 , - WIFIPHYRX_ABORT_REQUEST_E = 3 , - WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , - WIFIMACTX_DATA_RESP_E = 5 , - WIFIMACTX_CBF_DATA_E = 6 , - WIFIMACTX_CBF_DONE_E = 7 , - WIFIPHYRX_LMR_DATA_RESP_E = 8 , - WIFIRXPCU_TO_UCODE_START_E = 9 , - WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , - WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , - WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 , - WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , - WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , - WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , - WIFIRXPCU_TO_UCODE_END_E = 16 , - WIFIPHYRX_RSSI_LEGACY_20MHZ_E = 17 , - WIFIPHYRX_NC_ABORT_REQUEST_E = 18 , - WIFIPHYRX_PKT_END_20MHZ_E = 19 , - WIFIPHYRX_NC_DATA_E = 20 , - WIFIMACRX_CBF_READ_REQUEST_E = 64 , - WIFIMACRX_CBF_DATA_REQUEST_E = 65 , - WIFIMACRX_EXPECT_NDP_RECEPTION_E = 66 , - WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 67 , - WIFIMACRX_NDP_TIMEOUT_E = 68 , - WIFIMACRX_ABORT_ACK_E = 69 , - WIFIMACRX_REQ_IMPLICIT_FB_E = 70 , - WIFIMACRX_CHAIN_MASK_E = 71 , - WIFIMACRX_NAP_USER_E = 72 , - WIFIMACRX_ABORT_REQUEST_E = 73 , - WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 74 , - WIFIPHYTX_ABORT_ACK_E = 75 , - WIFIPHYTX_ABORT_REQUEST_E = 76 , - WIFIPHYTX_PKT_END_E = 77 , - WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 78 , - WIFIPHYTX_REQUEST_CTRL_INFO_E = 79 , - WIFIPHYTX_DATA_REQUEST_E = 80 , - WIFIPHYTX_BF_CV_LOADING_DONE_E = 81 , - WIFIPHYTX_NAP_ACK_E = 82 , - WIFIPHYTX_NAP_DONE_E = 83 , - WIFIPHYTX_OFF_ACK_E = 84 , - WIFIPHYTX_ON_ACK_E = 85 , - WIFIPHYTX_SYNTH_OFF_ACK_E = 86 , - WIFIPHYTX_DEBUG16_E = 87 , - WIFIMACTX_ABORT_REQUEST_E = 88 , - WIFIMACTX_ABORT_ACK_E = 89 , - WIFIMACTX_PKT_END_E = 90 , - WIFIMACTX_PRE_PHY_DESC_E = 91 , - WIFIMACTX_BF_PARAMS_COMMON_E = 92 , - WIFIMACTX_BF_PARAMS_PER_USER_E = 93 , - WIFIMACTX_PREFETCH_CV_E = 94 , - WIFIMACTX_USER_DESC_COMMON_E = 95 , - WIFIMACTX_USER_DESC_PER_USER_E = 96 , - WIFIEXAMPLE_USER_TLV_16_E = 97 , - WIFIEXAMPLE_TLV_16_E = 98 , - WIFIMACTX_PHY_OFF_E = 99 , - WIFIMACTX_PHY_ON_E = 100 , - WIFIMACTX_SYNTH_OFF_E = 101 , - WIFIMACTX_EXPECT_CBF_COMMON_E = 102 , - WIFIMACTX_EXPECT_CBF_PER_USER_E = 103 , - WIFIMACTX_PHY_DESC_E = 104 , - WIFIMACTX_L_SIG_A_E = 105 , - WIFIMACTX_L_SIG_B_E = 106 , - WIFIMACTX_HT_SIG_E = 107 , - WIFIMACTX_VHT_SIG_A_E = 108 , - WIFIMACTX_VHT_SIG_B_SU20_E = 109 , - WIFIMACTX_VHT_SIG_B_SU40_E = 110 , - WIFIMACTX_VHT_SIG_B_SU80_E = 111 , - WIFIMACTX_VHT_SIG_B_SU160_E = 112 , - WIFIMACTX_VHT_SIG_B_MU20_E = 113 , - WIFIMACTX_VHT_SIG_B_MU40_E = 114 , - WIFIMACTX_VHT_SIG_B_MU80_E = 115 , - WIFIMACTX_VHT_SIG_B_MU160_E = 116 , - WIFIMACTX_SERVICE_E = 117 , - WIFIMACTX_HE_SIG_A_SU_E = 118 , - WIFIMACTX_HE_SIG_A_MU_DL_E = 119 , - WIFIMACTX_HE_SIG_A_MU_UL_E = 120 , - WIFIMACTX_HE_SIG_B1_MU_E = 121 , - WIFIMACTX_HE_SIG_B2_MU_E = 122 , - WIFIMACTX_HE_SIG_B2_OFDMA_E = 123 , - WIFIMACTX_DELETE_CV_E = 124 , - WIFIMACTX_MU_UPLINK_COMMON_E = 125 , - WIFIMACTX_MU_UPLINK_USER_SETUP_E = 126 , - WIFIMACTX_OTHER_TRANSMIT_INFO_E = 127 , - WIFIMACTX_PHY_NAP_E = 128 , - WIFIMACTX_DEBUG_E = 129 , - WIFIPHYRX_ABORT_ACK_E = 130 , - WIFIPHYRX_GENERATED_CBF_DETAILS_E = 131 , - WIFIPHYRX_RSSI_LEGACY_E = 132 , - WIFIPHYRX_RSSI_HT_E = 133 , - WIFIPHYRX_USER_INFO_E = 134 , - WIFIPHYRX_PKT_END_E = 135 , - WIFIPHYRX_DEBUG_E = 136 , - WIFIPHYRX_CBF_TRANSFER_DONE_E = 137 , - WIFIPHYRX_CBF_TRANSFER_ABORT_E = 138 , - WIFIPHYRX_L_SIG_A_E = 139 , - WIFIPHYRX_L_SIG_B_E = 140 , - WIFIPHYRX_HT_SIG_E = 141 , - WIFIPHYRX_VHT_SIG_A_E = 142 , - WIFIPHYRX_VHT_SIG_B_SU20_E = 143 , - WIFIPHYRX_VHT_SIG_B_SU40_E = 144 , - WIFIPHYRX_VHT_SIG_B_SU80_E = 145 , - WIFIPHYRX_VHT_SIG_B_SU160_E = 146 , - WIFIPHYRX_VHT_SIG_B_MU20_E = 147 , - WIFIPHYRX_VHT_SIG_B_MU40_E = 148 , - WIFIPHYRX_VHT_SIG_B_MU80_E = 149 , - WIFIPHYRX_VHT_SIG_B_MU160_E = 150 , - WIFIPHYRX_HE_SIG_A_SU_E = 151 , - WIFIPHYRX_HE_SIG_A_MU_DL_E = 152 , - WIFIPHYRX_HE_SIG_A_MU_UL_E = 153 , - WIFIPHYRX_HE_SIG_B1_MU_E = 154 , - WIFIPHYRX_HE_SIG_B2_MU_E = 155 , - WIFIPHYRX_HE_SIG_B2_OFDMA_E = 156 , - WIFIPHYRX_OTHER_RECEIVE_INFO_E = 157 , - WIFIPHYRX_COMMON_USER_INFO_E = 158 , - WIFIPHYRX_DATA_DONE_E = 159 , - WIFICOEX_TX_REQ_E = 160 , - WIFIDUMMY_E = 161 , - WIFIEXAMPLE_TLV_32_NAME_E = 162 , - WIFIMPDU_LIMIT_E = 163 , - WIFINA_LENGTH_END_E = 164 , - WIFIOLE_BUF_STATUS_E = 165 , - WIFIPCU_PPDU_SETUP_DONE_E = 166 , - WIFIPCU_PPDU_SETUP_END_E = 167 , - WIFIPCU_PPDU_SETUP_INIT_E = 168 , - WIFIPCU_PPDU_SETUP_START_E = 169 , - WIFIPDG_FES_SETUP_E = 170 , - WIFIPDG_RESPONSE_E = 171 , - WIFIPDG_TX_REQ_E = 172 , - WIFISCH_WAIT_INSTR_E = 173 , - WIFIMACTX_SWITCH_TO_MAIN_E = 174 , - WIFIPHYTX_LINK_STATE_E = 175 , - WIFIAUX_PPDU_END_E = 176 , - WIFITQM_GEN_MPDU_LENGTH_LIST_E = 177 , - WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 178 , - WIFITQM_GEN_MPDUS_E = 179 , - WIFITQM_GEN_MPDUS_STATUS_E = 180 , - WIFITQM_REMOVE_MPDU_E = 181 , - WIFITQM_REMOVE_MPDU_STATUS_E = 182 , - WIFITQM_REMOVE_MSDU_E = 183 , - WIFITQM_REMOVE_MSDU_STATUS_E = 184 , - WIFITQM_UPDATE_TX_MPDU_COUNT_E = 185 , - WIFITQM_WRITE_CMD_E = 186 , - WIFIOFDMA_TRIGGER_DETAILS_E = 187 , - WIFITX_DATA_E = 188 , - WIFITX_FES_SETUP_E = 189 , - WIFIRX_PACKET_E = 190 , - WIFIEXPECTED_RESPONSE_E = 191 , - WIFITX_MPDU_END_E = 192 , - WIFITX_MPDU_START_E = 193 , - WIFITX_MSDU_END_E = 194 , - WIFITX_MSDU_START_E = 195 , - WIFITX_SW_MODE_SETUP_E = 196 , - WIFITXPCU_BUFFER_STATUS_E = 197 , - WIFITXPCU_USER_BUFFER_STATUS_E = 198 , - WIFIDATA_TO_TIME_CONFIG_E = 199 , - WIFIEXAMPLE_USER_TLV_32_E = 200 , - WIFIMPDU_INFO_E = 201 , - WIFIPDG_USER_SETUP_E = 202 , - WIFITX_11AH_SETUP_E = 203 , - WIFITX_PEER_ENTRY_E = 205 , - WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 206 , - WIFIEXAMPLE_USER_TLV_44_E = 207 , - WIFITX_FLUSH_E = 208 , - WIFITX_FLUSH_REQ_E = 209 , - WIFITQM_WRITE_CMD_STATUS_E = 210 , - WIFITQM_GET_MPDU_QUEUE_STATS_E = 211 , - WIFITQM_GET_MSDU_FLOW_STATS_E = 212 , - WIFIEXAMPLE_USER_CTLV_44_E = 213 , - WIFITX_FES_STATUS_START_E = 214 , - WIFITX_FES_STATUS_USER_PPDU_E = 215 , - WIFITX_FES_STATUS_USER_RESPONSE_E = 216 , - WIFITX_FES_STATUS_END_E = 217 , - WIFIRX_TRIG_INFO_E = 218 , - WIFIRXPCU_TX_SETUP_CLEAR_E = 219 , - WIFIRX_FRAME_BITMAP_REQ_E = 220 , - WIFIRX_FRAME_BITMAP_ACK_E = 221 , - WIFICOEX_RX_STATUS_E = 222 , - WIFIRX_START_PARAM_E = 223 , - WIFIRX_PPDU_START_E = 224 , - WIFIRX_PPDU_END_E = 225 , - WIFIRX_MPDU_START_E = 226 , - WIFIRX_MPDU_END_E = 227 , - WIFIRX_MSDU_START_E = 228 , - WIFIRX_MSDU_END_E = 229 , - WIFIRX_ATTENTION_E = 230 , - WIFIRECEIVED_RESPONSE_INFO_E = 231 , - WIFIRX_PHY_SLEEP_E = 232 , - WIFIRX_HEADER_E = 233 , - WIFIRX_PEER_ENTRY_E = 234 , - WIFIRX_FLUSH_E = 235 , - WIFIRX_RESPONSE_REQUIRED_INFO_E = 236 , - WIFIRX_FRAMELESS_BAR_DETAILS_E = 237 , - WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 238 , - WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 239 , - WIFITX_CBF_INFO_E = 240 , - WIFIPCU_PPDU_SETUP_USER_E = 241 , - WIFIRX_MPDU_PCU_START_E = 242 , - WIFIRX_PM_INFO_E = 243 , - WIFIRX_USER_PPDU_END_E = 244 , - WIFIRX_PRE_PPDU_START_E = 245 , - WIFIRX_PREAMBLE_E = 246 , - WIFITX_FES_SETUP_COMPLETE_E = 247 , - WIFITX_LAST_MPDU_FETCHED_E = 248 , - WIFITXDMA_STOP_REQUEST_E = 249 , - WIFIRXPCU_SETUP_E = 250 , - WIFIRXPCU_USER_SETUP_E = 251 , - WIFITX_FES_STATUS_ACK_OR_BA_E = 252 , - WIFITQM_ACKED_MPDU_E = 253 , - WIFICOEX_TX_RESP_E = 254 , - WIFICOEX_TX_STATUS_E = 255 , - WIFIMACTX_COEX_PHY_CTRL_E = 256 , - WIFICOEX_STATUS_BROADCAST_E = 257 , - WIFIRESPONSE_START_STATUS_E = 258 , - WIFIRESPONSE_END_STATUS_E = 259 , - WIFICRYPTO_STATUS_E = 260 , - WIFIRECEIVED_TRIGGER_INFO_E = 261 , - WIFICOEX_TX_STOP_CTRL_E = 262 , - WIFIRX_PPDU_ACK_REPORT_E = 263 , - WIFIRX_PPDU_NO_ACK_REPORT_E = 264 , - WIFISCH_COEX_STATUS_E = 265 , - WIFISCHEDULER_COMMAND_STATUS_E = 266 , - WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 267 , - WIFITX_FES_STATUS_PROT_E = 268 , - WIFITX_FES_STATUS_START_PPDU_E = 269 , - WIFITX_FES_STATUS_START_PROT_E = 270 , - WIFITXPCU_PHYTX_DEBUG32_E = 271 , - WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 272 , - WIFITX_MPDU_COUNT_TRANSFER_END_E = 273 , - WIFIWHO_ANCHOR_OFFSET_E = 274 , - WIFIWHO_ANCHOR_VALUE_E = 275 , - WIFIWHO_CCE_INFO_E = 276 , - WIFIWHO_COMMIT_E = 277 , - WIFIWHO_COMMIT_DONE_E = 278 , - WIFIWHO_FLUSH_E = 279 , - WIFIWHO_L2_LLC_E = 280 , - WIFIWHO_L2_PAYLOAD_E = 281 , - WIFIWHO_L3_CHECKSUM_E = 282 , - WIFIWHO_L3_INFO_E = 283 , - WIFIWHO_L4_CHECKSUM_E = 284 , - WIFIWHO_L4_INFO_E = 285 , - WIFIWHO_MSDU_E = 286 , - WIFIWHO_MSDU_MISC_E = 287 , - WIFIWHO_PACKET_DATA_E = 288 , - WIFIWHO_PACKET_HDR_E = 289 , - WIFIWHO_PPDU_END_E = 290 , - WIFIWHO_PPDU_START_E = 291 , - WIFIWHO_TSO_E = 292 , - WIFIWHO_WMAC_HEADER_PV0_E = 293 , - WIFIWHO_WMAC_HEADER_PV1_E = 294 , - WIFIWHO_WMAC_IV_E = 295 , - WIFIMPDU_INFO_END_E = 296 , - WIFIMPDU_INFO_BITMAP_E = 297 , - WIFITX_QUEUE_EXTENSION_E = 298 , - WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 299 , - WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 300 , - WIFITQM_ACKED_MPDU_STATUS_E = 301 , - WIFITQM_ADD_MSDU_STATUS_E = 302 , - WIFITQM_LIST_GEN_DONE_E = 303 , - WIFIWHO_TERMINATE_E = 304 , - WIFITX_LAST_MPDU_END_E = 305 , - WIFITX_CV_DATA_E = 306 , - WIFIPPDU_TX_END_E = 307 , - WIFIPROT_TX_END_E = 308 , - WIFIMPDU_INFO_GLOBAL_END_E = 309 , - WIFITQM_SCH_INSTR_GLOBAL_END_E = 310 , - WIFIRX_PPDU_END_USER_STATS_E = 311 , - WIFIRX_PPDU_END_USER_STATS_EXT_E = 312 , - WIFITQM_FLUSH_CACHE_E = 321 , - WIFITQM_UNBLOCK_CACHE_E = 322 , - WIFITQM_FLUSH_CACHE_STATUS_E = 323 , - WIFITQM_UNBLOCK_CACHE_STATUS_E = 324 , - WIFIRX_PPDU_END_STATUS_DONE_E = 325 , - WIFIRX_STATUS_BUFFER_DONE_E = 326 , - WIFISCHEDULER_MLO_SW_MSG_STATUS_E = 327 , - WIFISCHEDULER_TXOP_DURATION_TRIGGER_E = 328 , - WIFITX_DATA_SYNC_E = 329 , - WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 330 , - WIFITQM_GET_MPDU_HEAD_INFO_E = 331 , - WIFITQM_SYNC_CMD_E = 332 , - WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 333 , - WIFITQM_SYNC_CMD_STATUS_E = 334 , - WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 335 , - WIFITCC_TQM_WRAPPER_CMD_E = 336 , - WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 340 , - WIFIEXAMPLE_USER_TLV_32_NAME_E = 341 , - WIFIRX_PPDU_START_USER_INFO_E = 342 , - WIFIRX_RING_MASK_E = 343 , - WIFICOEX_MAC_NAP_E = 344 , - WIFIRXPCU_PPDU_END_INFO_E = 345 , - WIFIWHO_MESH_CONTROL_E = 346 , - WIFIPDG_SW_MODE_BW_START_E = 347 , - WIFIPDG_SW_MODE_BW_END_E = 348 , - WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 349 , - WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 350 , - WIFISCHEDULER_END_E = 351 , - WIFIRX_PPDU_START_DROPPED_E = 352 , - WIFIRX_PPDU_END_DROPPED_E = 353 , - WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 354 , - WIFIRX_MPDU_START_DROPPED_E = 355 , - WIFIRX_MSDU_START_DROPPED_E = 356 , - WIFIRX_MSDU_END_DROPPED_E = 357 , - WIFIRX_MPDU_END_DROPPED_E = 358 , - WIFIRX_ATTENTION_DROPPED_E = 359 , - WIFITXPCU_USER_SETUP_E = 360 , - WIFIRXPCU_USER_SETUP_EXT_E = 361 , - WIFICMD_PART_0_END_E = 362 , - WIFIMACTX_SYNTH_ON_E = 363 , - WIFISCH_CRITICAL_TLV_REFERENCE_E = 364 , - WIFITQM_MPDU_GLOBAL_START_E = 365 , - WIFIEXAMPLE_TLV_32_E = 366 , - WIFITQM_UPDATE_TX_MSDU_FLOW_E = 367 , - WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 368 , - WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 369 , - WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 370 , - WIFITQM_2_SCH_MPDU_AVAILABLE_E = 372 , - WIFIPDG_TRIG_RESPONSE_E = 373 , - WIFITRIGGER_RESPONSE_TX_DONE_E = 374 , - WIFIABORT_FROM_PHYRX_DETAILS_E = 375 , - WIFISCH_TQM_CMD_WRAPPER_E = 376 , - WIFIMPDUS_AVAILABLE_E = 377 , - WIFIRECEIVED_RESPONSE_INFO_PART2_E = 378 , - WIFIPHYRX_TX_START_TIMING_E = 379 , - WIFITXPCU_PREAMBLE_DONE_E = 380 , - WIFINDP_PREAMBLE_DONE_E = 381 , - WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 382 , - WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 383 , - WIFIMACTX_CLEAR_PREV_TX_INFO_E = 384 , - WIFITX_PUNCTURE_SETUP_E = 385 , - WIFIR2R_STATUS_END_E = 386 , - WIFIMACTX_PREFETCH_CV_COMMON_E = 387 , - WIFIEND_OF_FLUSH_MARKER_E = 388 , - WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 389 , - WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 390 , - WIFIRECEIVED_RESPONSE_USER_7_0_E = 391 , - WIFIRECEIVED_RESPONSE_USER_15_8_E = 392 , - WIFIRECEIVED_RESPONSE_USER_23_16_E = 393 , - WIFIRECEIVED_RESPONSE_USER_31_24_E = 394 , - WIFIRECEIVED_RESPONSE_USER_36_32_E = 395 , - WIFITX_LOOPBACK_SETUP_E = 396 , - WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 397 , - WIFISCH_WAIT_INSTR_TX_PATH_E = 398 , - WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 399 , - WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 400 , - WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 401 , - WIFITX_WUR_DATA_E = 402 , - WIFIRX_PPDU_END_START_E = 403 , - WIFIRX_PPDU_END_MIDDLE_E = 404 , - WIFIRX_PPDU_END_LAST_E = 405 , - WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 406 , - WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 407 , - WIFISRP_INFO_E = 408 , - WIFIOBSS_SR_INFO_E = 409 , - WIFISCHEDULER_SW_MSG_STATUS_E = 410 , - WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 411 , - WIFIRXPCU_SETUP_COMPLETE_E = 412 , - WIFIMACTX_MCC_SWITCH_E = 413 , - WIFIMACTX_MCC_SWITCH_BACK_E = 414 , - WIFIPHYTX_MCC_SWITCH_ACK_E = 415 , - WIFIPHYTX_MCC_SWITCH_BACK_ACK_E = 416 , - WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E = 417 , - WIFILMR_TX_END_E = 418 , - WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 419 , - WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 420 , - WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 421 , - WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 422 , - WIFISCH_TLV_WRAPPER_E = 423 , - WIFISCHEDULER_STATUS_WRAPPER_E = 424 , - WIFIMPDU_INFO_6X_E = 425 , - WIFIMACTX___RESERVED_G_0013 = 426 , - WIFIMACTX_U_SIG_EHT_SU_MU_E = 427 , - WIFIMACTX_U_SIG_EHT_TB_E = 428 , - WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E = 429 , - WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E = 430 , - WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E = 431 , - WIFIPHYRX_U_SIG_EHT_SU_MU_E = 432 , - WIFIPHYRX_U_SIG_EHT_TB_E = 433 , - WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E = 434 , - WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 435 , - WIFITX_PUNCTURE_6PATTERNS_SETUP_E = 436 , - WIFIMACRX_LMR_READ_REQUEST_E = 437 , - WIFIMACRX_LMR_DATA_REQUEST_E = 438 , - WIFIPHYRX_LMR_TRANSFER_DONE_E = 439 , - WIFIPHYRX_LMR_TRANSFER_ABORT_E = 440 , - WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 441 , - WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 442 , - WIFIPHYRX_USER_INFO_MU_UL_E = 443 , - WIFIMPDU_QUEUE_OVERVIEW_E = 444 , - WIFISCHEDULER_NAV_INFO_E = 445 , - WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 446 , - WIFILMR_PEER_ENTRY_E = 447 , - WIFILMR_MPDU_START_E = 448 , - WIFILMR_DATA_E = 449 , - WIFILMR_MPDU_END_E = 450 , - WIFIRX_FRAME_1K_BITMAP_ACK_E = 452 , - WIFITX_FES_STATUS_1K_BA_E = 453 , - WIFITQM_ACKED_1K_MPDU_E = 454 , - WIFIMACRX_INBSS_OBSS_IND_E = 455 , - WIFIPHYRX_LOCATION_E = 456 , - WIFIMLO_TX_NOTIFICATION_SU_E = 457 , - WIFIMLO_TX_NOTIFICATION_MU_E = 458 , - WIFIMLO_TX_REQ_SU_E = 459 , - WIFIMLO_TX_REQ_MU_E = 460 , - WIFIMLO_TX_RESP_E = 461 , - WIFIMLO_RX_NOTIFICATION_E = 462 , - WIFIMLO_BKOFF_TRUNC_REQ_E = 463 , - WIFIMLO_TBTT_NOTIFICATION_E = 464 , - WIFIMLO_MESSAGE_E = 465 , - WIFIMLO_TS_SYNC_MSG_E = 466 , - WIFIMLO_FES_SETUP_E = 467 , - WIFIMLO_PDG_FES_SETUP_SU_E = 468 , - WIFIMLO_PDG_FES_SETUP_MU_E = 469 , - WIFIMPDU_INFO_1K_BITMAP_E = 470 , - WIFIMON_BUFFER_ADDR_E = 471 , - WIFITX_FRAG_STATE_E = 472 , - WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 473 , - WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 474 , - WIFIMACTX_EHT_SIG_USR_OFDMA_E = 475 , - WIFIMACTX_U_SIG_UHR_SU_MU_E = 476 , - WIFIMACTX_U_SIG_UHR_TB_E = 477 , - WIFITX_MPDU_COMPRESSED_DETAILS_TLV_E = 478 , - WIFITX_MSDU_COMPRESSED_DETAILS_TLV_E = 479 , - WIFITX_MSDU_COMPONENT_DETAILS_TLV_E = 480 , - WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 481 , - WIFISCHEDULER_IU_TEMPLATE_ID_E = 482 , - WIFIPHYRX_PKT_END_PART1_E = 483 , - WIFIMACTX_EXPECT_NDP_RECEPTION_E = 484 , - WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 485 , - WIFITX_MPDU_LENGTH_AND_RESTRICTIONS_E = 486 , - WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 487 , - WIFIPHYRX___RESERVED_G_0014 = 488 , - WIFIPHYTX_LOCATION_E = 489 , - WIFIPHYTX___RESERVED_G_0014 = 490 , - WIFIMPDU_LENGTH_STRUCTS_START_E = 491 , - WIFIMACTX_EHT_SIG_USR_SU_E = 492 , - WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 493 , - WIFIPHYRX_EHT_SIG_USR_SU_E = 494 , - WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 495 , - WIFIPHYRX_GENERIC_U_SIG_E = 496 , - WIFIPHYRX_GENERIC_EHT_OR_UHR_SIG_E = 497 , - WIFIOVERWRITE_RESP_START_E = 498 , - WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 499 , - WIFIOVERWRITE_RESP_FRAME_INFO_E = 500 , - WIFIOVERWRITE_RESP_END_E = 501 , - WIFIRXPCU_EARLY_RX_INDICATION_E = 502 , - WIFIMON_DROP_E = 503 , - WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 504 , - WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 505 , - WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 506 , - WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 507 , - WIFIMACTX_PREFETCH_CV_DMA_E = 508 , - WIFIMACTX_PREFETCH_CV_PER_USER_E = 509 , - WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 510 , - WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 511 , - WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 512 , - WIFIRANGING_USER_DETAILS_E = 513 , - WIFIPHYTX_CV_CORR_STATUS_E = 514 , - WIFIPHYTX_CV_CORR_COMMON_E = 515 , - WIFIPHYTX_CV_CORR_USER_E = 516 , - WIFIMACTX_CV_CORR_COMMON_E = 517 , - WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 518 , - WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 519 , - WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 520 , - WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 521 , - WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 522 , - WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 523 , - WIFIRX_PPDU_END_USER_STATS_EXT2_E = 524 , - WIFIFW2SW_MON_E = 525 , - WIFIWSI_DIRECT_MESSAGE_E = 526 , - WIFIMACTX_EMLSR_PRE_SWITCH_E = 527 , - WIFIMACTX_EMLSR_SWITCH_E = 528 , - WIFIMACTX_EMLSR_SWITCH_BACK_E = 529 , - WIFIPHYTX_EMLSR_SWITCH_ACK_E = 530 , - WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 531 , - WIFIEAD_COMMAND_E = 532 , - WIFIEAD_LEGACY_STATUS_CONTROL_E = 533 , - WIFIEAD_LEGACY_INTERRUPT_CONTROL_E = 534 , - WIFITPI_TX_INITIALIZATION_CONFIG_E = 535 , - WIFITPI_ENABLE_RESPONSE_TIMEOUT_E = 536 , - WIFITPI_LEGACY_STATUS_CONTROL_E = 537 , - WIFITPI_LEGACY_INTERRUPT_CONTROL_E = 538 , - WIFITPI_MPDU_START_E = 539 , - WIFITPI_MPDU_CONTINUATION_E = 540 , - WIFITPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E = 541 , - WIFITPI_SEND_TLV_TO_PHYTX_E = 542 , - WIFITPI_TX_START_TIME_ARRIVED_E = 543 , - WIFITPI_STATUS_E = 544 , - WIFITPI_ERROR_STATUS_E = 545 , - WIFITPI_TIMESTAMP_STATUS_E = 546 , - WIFIRPI_SEND_TLV_TO_PHYRX_E = 547 , - WIFIRPI_LEGACY_STATUS_CONTROL_E = 548 , - WIFIRPI_LEGACY_INTERRUPT_CONTROL_E = 549 , - WIFIRPI_STATUS_E = 550 , - WIFIRPI_ERROR_STATUS_E = 551 , - WIFIRPI_TIMESTAMP_STATUS_E = 552 , - WIFIRPI_RX_FRAME_UPDATE_STATUS_E = 553 , - WIFITCC_PUSH_TRANSMIT_COMMAND_E = 554 , - WIFITCC_TLV_FETCH_E = 555 , - WIFITCC_LEGACY_STATUS_CONTROL_E = 556 , - WIFITCC_LEGACY_INTERRUPT_CONTROL_E = 557 , - WIFITCC_STATUS_E = 558 , - WIFITCC_ERROR_STATUS_E = 559 , - WIFITCC_TIMESTAMP_STATUS_E = 560 , - WIFITCC_PRE_BACKOFF_CMD_AVAILABLE_E = 561 , - WIFITCC_SCHEDULER_CMD_E = 562 , - WIFITCC_BURST_CMD_AVAILABLE_E = 563 , - WIFIRPI_NON_DATA_CTLV_44_FROM_PHYRX_E = 564 , - WIFIEAD_RING_AIR_TIME_REFERENCE_E = 565 , - WIFIRPI_FETCH_INFO_FROM_EXT_MEM_E = 566 , - WIFIRPI_WRITE_INFO_TO_EXT_MEM_E = 567 , - WIFIRPI_INIT_CBF_DATA_RESP_ADDR_E = 568 , - WIFIRPI_INIT_LMR_DATA_RESP_ADDR_E = 569 , - WIFITPI_SEND_CBF_DATA_TO_PHYTX_E = 570 , - WIFITPI_SEND_CTLV_44_TO_PHYTX_E = 571 , - WIFITCC_FES_END_MESSAGE_E = 572 , - WIFITPI_TX_FRAME_UPDATE_STATUS_E = 573 , - WIFITPI_DISABLE_RESPONSE_TIMEOUT_E = 574 , - WIFIEAD_MPDU_DATA_FETCH_CONTINUATION_E = 575 , - WIFIEAD_MSDU_STATUS_START_E = 576 , - WIFIEAD_MSDU_STATUS_DETAILS_E = 577 , - WIFIMACTX_UHR_SIG_USR_SU_E = 578 , - WIFIMACTX_UHR_SIG_USR_MU_MIMO_E = 579 , - WIFIMACTX_UHR_SIG_USR_OFDMA_E = 580 , - WIFIMACTX_ELR_SIG_UHR_SU_E = 581 , - WIFICOEX_BLACKOUT_DETAILS_E = 582 , - WIFIPEER_BLACKOUT_DETAILS_E = 583 , - WIFIMACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E = 584 , - WIFIHDR_CTRL_PROT_PEER_ENTRY_E = 585 , - WIFIHDR_CTRL_PROT_MPDU_START_E = 586 , - WIFIHDR_CTRL_PROT_DATA_E = 587 , - WIFIHDR_CTRL_PROT_MPDU_END_E = 588 , - WIFIHDR_CTRL_PROT_MIC_STATUS_E = 589 , - WIFIHDR_CTRL_PROT_PEER_INFO_E = 590 , - WIFIHDR_CTRL_PROT_PEER_ENTRY_DONE_E = 591 , - WIFIMACTX_U_SIG_UHR_ELR_SU_E = 592 , - WIFIMACTX_U_SIG_UHR_COBF_E = 593 , - WIFIMACTX_UHR_SIG_USR_COBF_E = 594 , - WIFIMACTX_U_SIG_UHR_COSR_E = 595 , - WIFIMACTX_UHR_SIG_USR_COSR_E = 596 , - WIFIOVERWRITE_CFP_INFO_E = 597 , - WIFISPARE_REUSE_TAG_0_E = 598 , - WIFISPARE_REUSE_TAG_1_E = 599 , - WIFISPARE_REUSE_TAG_2_E = 600 , - WIFISPARE_REUSE_TAG_3_E = 601 , - WIFISPARE_REUSE_TAG_4_E = 602 , - WIFISPARE_REUSE_TAG_5_E = 603 , - WIFISPARE_REUSE_TAG_6_E = 604 , - WIFISPARE_REUSE_TAG_7_E = 605 , - WIFISPARE_REUSE_TAG_8_E = 606 , - WIFISPARE_REUSE_TAG_9_E = 607 , - WIFISPARE_REUSE_TAG_10_E = 608 , - WIFISPARE_REUSE_TAG_11_E = 609 , - WIFISPARE_REUSE_TAG_12_E = 610 , - WIFISPARE_REUSE_TAG_13_E = 611 , - WIFISPARE_REUSE_TAG_14_E = 612 , - WIFISPARE_REUSE_TAG_15_E = 613 , - WIFISPARE_REUSE_TAG_16_E = 614 , - WIFISPARE_REUSE_TAG_17_E = 615 , - WIFISPARE_REUSE_TAG_18_E = 616 , - WIFISPARE_REUSE_TAG_19_E = 617 , - WIFISPARE_REUSE_TAG_20_E = 618 , - WIFISPARE_REUSE_TAG_21_E = 619 , - WIFISPARE_REUSE_TAG_22_E = 620 , - WIFISPARE_REUSE_TAG_23_E = 621 , - WIFISPARE_REUSE_TAG_24_E = 622 , - WIFISPARE_REUSE_TAG_25_E = 623 , - WIFISPARE_REUSE_TAG_26_E = 624 , - WIFISPARE_REUSE_TAG_27_E = 625 , - WIFISPARE_REUSE_TAG_28_E = 626 , - WIFISPARE_REUSE_TAG_29_E = 627 , - WIFISPARE_REUSE_TAG_30_E = 628 , - WIFISPARE_REUSE_TAG_31_E = 629 , - WIFISPARE_REUSE_TAG_32_E = 630 , - WIFISPARE_REUSE_TAG_33_E = 631 , - WIFISPARE_REUSE_TAG_34_E = 632 , - WIFISPARE_REUSE_TAG_35_E = 633 , - WIFISPARE_REUSE_TAG_36_E = 634 , - WIFISPARE_REUSE_TAG_37_E = 635 , - WIFISPARE_REUSE_TAG_38_E = 636 , - WIFISPARE_REUSE_TAG_39_E = 637 , - WIFISPARE_REUSE_TAG_40_E = 638 , - WIFISPARE_REUSE_TAG_41_E = 639 , - WIFISPARE_REUSE_TAG_42_E = 640 , - WIFISPARE_REUSE_TAG_43_E = 641 , - WIFISPARE_REUSE_TAG_44_E = 642 , - WIFISPARE_REUSE_TAG_45_E = 643 , - WIFISPARE_REUSE_TAG_46_E = 644 , - WIFISPARE_REUSE_TAG_47_E = 645 , - WIFISPARE_REUSE_TAG_48_E = 646 , - WIFISPARE_REUSE_TAG_49_E = 647 , - WIFISPARE_REUSE_TAG_50_E = 648 , - WIFISPARE_REUSE_TAG_51_E = 649 , - WIFISPARE_REUSE_TAG_52_E = 650 , - WIFISPARE_REUSE_TAG_53_E = 651 , - WIFISPARE_REUSE_TAG_54_E = 652 , - WIFISPARE_REUSE_TAG_55_E = 653 , - WIFISPARE_REUSE_TAG_56_E = 654 , - WIFISPARE_REUSE_TAG_57_E = 655 , - WIFISPARE_REUSE_TAG_58_E = 656 , - WIFISPARE_REUSE_TAG_59_E = 657 , - WIFISPARE_REUSE_TAG_60_E = 658 , - WIFISPARE_REUSE_TAG_61_E = 659 , - WIFISPARE_REUSE_TAG_62_E = 660 , - WIFISPARE_REUSE_TAG_63_E = 661 , - WIFISPARE_REUSE_TAG_64_E = 662 , - WIFISPARE_REUSE_TAG_65_E = 663 , - WIFISPARE_REUSE_TAG_66_E = 664 , - WIFISPARE_REUSE_TAG_67_E = 665 , - WIFISPARE_REUSE_TAG_68_E = 666 , - WIFISPARE_REUSE_TAG_69_E = 667 , - WIFISPARE_REUSE_TAG_70_E = 668 , - WIFISPARE_REUSE_TAG_71_E = 669 , - WIFISPARE_REUSE_TAG_72_E = 670 , - WIFISPARE_REUSE_TAG_73_E = 671 , - WIFISPARE_REUSE_TAG_74_E = 672 , - WIFISPARE_REUSE_TAG_75_E = 673 , - WIFISPARE_REUSE_TAG_76_E = 674 , - WIFISPARE_REUSE_TAG_77_E = 675 , - WIFISPARE_REUSE_TAG_78_E = 676 , - WIFISPARE_REUSE_TAG_79_E = 677 , - WIFISPARE_REUSE_TAG_80_E = 678 , - WIFISPARE_REUSE_TAG_81_E = 679 , - WIFISPARE_REUSE_TAG_82_E = 680 , - WIFISPARE_REUSE_TAG_83_E = 681 , - WIFISPARE_REUSE_TAG_84_E = 682 , - WIFISPARE_REUSE_TAG_85_E = 683 , - WIFISPARE_REUSE_TAG_86_E = 684 , - WIFISPARE_REUSE_TAG_87_E = 685 , - WIFISPARE_REUSE_TAG_88_E = 686 , - WIFISPARE_REUSE_TAG_89_E = 687 , - WIFISPARE_REUSE_TAG_90_E = 688 , - WIFISPARE_REUSE_TAG_91_E = 689 , - WIFISPARE_REUSE_TAG_92_E = 690 , - WIFISPARE_REUSE_TAG_93_E = 691 , - WIFISPARE_REUSE_TAG_94_E = 692 , - WIFISPARE_REUSE_TAG_95_E = 693 , - WIFISPARE_REUSE_TAG_96_E = 694 , - WIFISPARE_REUSE_TAG_97_E = 695 , - WIFISPARE_REUSE_TAG_98_E = 696 , - WIFISPARE_REUSE_TAG_99_E = 697 , - WIFISPARE_REUSE_TAG_100_E = 698 , - WIFISPARE_REUSE_TAG_101_E = 699 , - WIFISPARE_REUSE_TAG_102_E = 700 , - WIFISPARE_REUSE_TAG_103_E = 701 , - WIFISPARE_REUSE_TAG_104_E = 702 , - WIFISPARE_REUSE_TAG_105_E = 703 , - WIFISPARE_REUSE_TAG_106_E = 704 , - WIFISPARE_REUSE_TAG_107_E = 705 , - WIFISPARE_REUSE_TAG_108_E = 706 , - WIFISPARE_REUSE_TAG_109_E = 707 , - WIFISPARE_REUSE_TAG_110_E = 708 , - WIFISPARE_REUSE_TAG_111_E = 709 , - WIFISPARE_REUSE_TAG_112_E = 710 , - WIFISPARE_REUSE_TAG_113_E = 711 , - WIFISPARE_REUSE_TAG_114_E = 712 , - WIFISPARE_REUSE_TAG_115_E = 713 , - WIFISPARE_REUSE_TAG_116_E = 714 , - WIFISPARE_REUSE_TAG_117_E = 715 , - WIFISPARE_REUSE_TAG_118_E = 716 , - WIFISPARE_REUSE_TAG_119_E = 717 , - WIFISPARE_REUSE_TAG_120_E = 718 , - WIFISPARE_REUSE_TAG_121_E = 719 , - WIFISPARE_REUSE_TAG_122_E = 720 , - WIFISPARE_REUSE_TAG_123_E = 721 , - WIFISPARE_REUSE_TAG_124_E = 722 , - WIFISPARE_REUSE_TAG_125_E = 723 , - WIFISPARE_REUSE_TAG_126_E = 724 , - WIFISPARE_REUSE_TAG_127_E = 725 , - WIFISPARE_REUSE_TAG_128_E = 726 , - WIFISPARE_REUSE_TAG_129_E = 727 , - WIFISPARE_REUSE_TAG_130_E = 728 , - WIFISPARE_REUSE_TAG_131_E = 729 , - WIFISPARE_REUSE_TAG_132_E = 730 , - WIFISPARE_REUSE_TAG_133_E = 731 , - WIFISPARE_REUSE_TAG_134_E = 732 , - WIFISPARE_REUSE_TAG_135_E = 733 , - WIFISPARE_REUSE_TAG_136_E = 734 , - WIFISPARE_REUSE_TAG_137_E = 735 , - WIFISPARE_REUSE_TAG_138_E = 736 , - WIFISPARE_REUSE_TAG_139_E = 737 , - WIFISPARE_REUSE_TAG_140_E = 738 , - WIFISPARE_REUSE_TAG_141_E = 739 , - WIFISPARE_REUSE_TAG_142_E = 740 , - WIFISPARE_REUSE_TAG_143_E = 741 , - WIFISPARE_REUSE_TAG_144_E = 742 , - WIFISPARE_REUSE_TAG_145_E = 743 , - WIFISPARE_REUSE_TAG_146_E = 744 , - WIFISPARE_REUSE_TAG_147_E = 745 , - WIFISPARE_REUSE_TAG_148_E = 746 , - WIFISPARE_REUSE_TAG_149_E = 747 , - WIFISPARE_REUSE_TAG_150_E = 748 , - WIFISPARE_REUSE_TAG_151_E = 749 , - WIFISPARE_REUSE_TAG_152_E = 750 , - WIFISPARE_REUSE_TAG_153_E = 751 , - WIFISPARE_REUSE_TAG_154_E = 752 , - WIFISPARE_REUSE_TAG_155_E = 753 , - WIFISPARE_REUSE_TAG_156_E = 754 , - WIFISPARE_REUSE_TAG_157_E = 755 , - WIFISPARE_REUSE_TAG_158_E = 756 , - WIFISPARE_REUSE_TAG_159_E = 757 , - WIFISPARE_REUSE_TAG_160_E = 758 , - WIFISPARE_REUSE_TAG_161_E = 759 , - WIFISPARE_REUSE_TAG_162_E = 760 , - WIFISPARE_REUSE_TAG_163_E = 761 , - WIFISPARE_REUSE_TAG_164_E = 762 , - WIFISPARE_REUSE_TAG_165_E = 763 , - WIFISPARE_REUSE_TAG_166_E = 764 , - WIFISPARE_REUSE_TAG_167_E = 765 , - WIFISPARE_REUSE_TAG_168_E = 766 , - WIFISPARE_REUSE_TAG_169_E = 767 , - WIFISPARE_REUSE_TAG_170_E = 768 , - WIFISPARE_REUSE_TAG_171_E = 769 , - WIFISPARE_REUSE_TAG_172_E = 770 , - WIFISPARE_REUSE_TAG_173_E = 771 , - WIFISPARE_REUSE_TAG_174_E = 772 , - WIFISPARE_REUSE_TAG_175_E = 773 , - WIFISPARE_REUSE_TAG_176_E = 774 , - WIFISPARE_REUSE_TAG_177_E = 775 , - WIFISPARE_REUSE_TAG_178_E = 776 , - WIFISPARE_REUSE_TAG_179_E = 777 , - WIFISPARE_REUSE_TAG_180_E = 778 , - WIFISPARE_REUSE_TAG_181_E = 779 , - WIFISPARE_REUSE_TAG_182_E = 780 , - WIFISPARE_REUSE_TAG_183_E = 781 , - WIFISPARE_REUSE_TAG_184_E = 782 , - WIFISPARE_REUSE_TAG_185_E = 783 , - WIFISPARE_REUSE_TAG_186_E = 784 , - WIFISPARE_REUSE_TAG_187_E = 785 , - WIFISPARE_REUSE_TAG_188_E = 786 , - WIFISPARE_REUSE_TAG_189_E = 787 , - WIFISPARE_REUSE_TAG_190_E = 788 , - WIFISPARE_REUSE_TAG_191_E = 789 , - WIFISPARE_REUSE_TAG_192_E = 790 , - WIFISPARE_REUSE_TAG_193_E = 791 , - WIFISPARE_REUSE_TAG_194_E = 792 , - WIFISPARE_REUSE_TAG_195_E = 793 , - WIFISPARE_REUSE_TAG_196_E = 794 , - WIFISPARE_REUSE_TAG_197_E = 795 , - WIFISPARE_REUSE_TAG_198_E = 796 , - WIFISPARE_REUSE_TAG_199_E = 797 , - WIFISPARE_REUSE_TAG_200_E = 798 , - WIFISPARE_REUSE_TAG_201_E = 799 , - WIFISPARE_REUSE_TAG_202_E = 800 , - WIFISPARE_REUSE_TAG_203_E = 801 , - WIFISPARE_REUSE_TAG_204_E = 802 , - WIFISPARE_REUSE_TAG_205_E = 803 , - WIFISPARE_REUSE_TAG_206_E = 804 , - WIFISPARE_REUSE_TAG_207_E = 805 , - WIFISPARE_REUSE_TAG_208_E = 806 , - WIFISPARE_REUSE_TAG_209_E = 807 , - WIFISPARE_REUSE_TAG_210_E = 808 , - WIFISPARE_REUSE_TAG_211_E = 809 , - WIFISPARE_REUSE_TAG_212_E = 810 , - WIFISPARE_REUSE_TAG_213_E = 811 , - WIFISPARE_REUSE_TAG_214_E = 812 , - WIFISPARE_REUSE_TAG_215_E = 813 , - WIFISPARE_REUSE_TAG_216_E = 814 , - WIFISPARE_REUSE_TAG_217_E = 815 , - WIFISPARE_REUSE_TAG_218_E = 816 , - WIFISPARE_REUSE_TAG_219_E = 817 , - WIFISPARE_REUSE_TAG_220_E = 818 , - WIFISPARE_REUSE_TAG_221_E = 819 , - WIFISPARE_REUSE_TAG_222_E = 820 , - WIFISPARE_REUSE_TAG_223_E = 821 , - WIFISPARE_REUSE_TAG_224_E = 822 , - WIFISPARE_REUSE_TAG_225_E = 823 , - WIFISPARE_REUSE_TAG_226_E = 824 , - WIFISPARE_REUSE_TAG_227_E = 825 , - WIFISPARE_REUSE_TAG_228_E = 826 , - WIFISPARE_REUSE_TAG_229_E = 827 , - WIFISPARE_REUSE_TAG_230_E = 828 , - WIFISPARE_REUSE_TAG_231_E = 829 , - WIFISPARE_REUSE_TAG_232_E = 830 , - WIFISPARE_REUSE_TAG_233_E = 831 , - WIFISPARE_REUSE_TAG_234_E = 832 , - WIFISPARE_REUSE_TAG_235_E = 833 , - WIFISPARE_REUSE_TAG_236_E = 834 , - WIFISPARE_REUSE_TAG_237_E = 835 , - WIFISPARE_REUSE_TAG_238_E = 836 , - WIFISPARE_REUSE_TAG_239_E = 837 , - WIFISPARE_REUSE_TAG_240_E = 838 , - WIFISPARE_REUSE_TAG_241_E = 839 , - WIFISPARE_REUSE_TAG_242_E = 840 , - WIFISPARE_REUSE_TAG_243_E = 841 , - WIFISPARE_REUSE_TAG_244_E = 842 , - WIFISPARE_REUSE_TAG_245_E = 843 , - WIFISPARE_REUSE_TAG_246_E = 844 , - WIFISPARE_REUSE_TAG_247_E = 845 , - WIFISPARE_REUSE_TAG_248_E = 846 , - WIFISPARE_REUSE_TAG_249_E = 847 , - WIFISPARE_REUSE_TAG_250_E = 848 , - WIFISPARE_REUSE_TAG_251_E = 849 , - WIFISPARE_REUSE_TAG_252_E = 850 , - WIFISPARE_REUSE_TAG_253_E = 851 , - WIFISPARE_REUSE_TAG_254_E = 852 , - WIFISPARE_REUSE_TAG_255_E = 853 , - WIFISPARE_REUSE_TAG_256_E = 854 , - WIFISPARE_REUSE_TAG_257_E = 855 , - WIFISPARE_REUSE_TAG_258_E = 856 , - WIFISPARE_REUSE_TAG_259_E = 857 , - WIFISPARE_REUSE_TAG_260_E = 858 , - WIFISPARE_REUSE_TAG_261_E = 859 , - WIFISPARE_REUSE_TAG_262_E = 860 , - WIFISPARE_REUSE_TAG_263_E = 861 , - WIFISPARE_REUSE_TAG_264_E = 862 , - WIFISPARE_REUSE_TAG_265_E = 863 , - WIFISPARE_REUSE_TAG_266_E = 864 , - WIFISPARE_REUSE_TAG_267_E = 865 , - WIFISPARE_REUSE_TAG_268_E = 866 , - WIFISPARE_REUSE_TAG_269_E = 867 , - WIFISPARE_REUSE_TAG_270_E = 868 , - WIFISPARE_REUSE_TAG_271_E = 869 , - WIFISPARE_REUSE_TAG_272_E = 870 , - WIFISPARE_REUSE_TAG_273_E = 871 , - WIFISPARE_REUSE_TAG_274_E = 872 , - WIFISPARE_REUSE_TAG_275_E = 873 , - WIFISPARE_REUSE_TAG_276_E = 874 , - WIFISPARE_REUSE_TAG_277_E = 875 , - WIFISPARE_REUSE_TAG_278_E = 876 , - WIFISPARE_REUSE_TAG_279_E = 877 , - WIFISPARE_REUSE_TAG_280_E = 878 , - WIFISPARE_REUSE_TAG_281_E = 879 , - WIFISPARE_REUSE_TAG_282_E = 880 , - WIFISPARE_REUSE_TAG_283_E = 881 , - WIFISPARE_REUSE_TAG_284_E = 882 , - WIFISPARE_REUSE_TAG_285_E = 883 , - WIFISPARE_REUSE_TAG_286_E = 884 , - WIFISPARE_REUSE_TAG_287_E = 885 , - WIFISPARE_REUSE_TAG_288_E = 886 , - WIFISPARE_REUSE_TAG_289_E = 887 , - WIFISPARE_REUSE_TAG_290_E = 888 , - WIFISPARE_REUSE_TAG_291_E = 889 , - WIFISPARE_REUSE_TAG_292_E = 890 , - WIFISPARE_REUSE_TAG_293_E = 891 , - WIFISPARE_REUSE_TAG_294_E = 892 , - WIFISPARE_REUSE_TAG_295_E = 893 , - WIFISPARE_REUSE_TAG_296_E = 894 , - WIFISPARE_REUSE_TAG_297_E = 895 , - WIFISPARE_REUSE_TAG_298_E = 896 , - WIFISPARE_REUSE_TAG_299_E = 897 , - WIFISPARE_REUSE_TAG_300_E = 898 , - WIFISPARE_REUSE_TAG_301_E = 899 , - WIFISPARE_REUSE_TAG_302_E = 900 , - WIFISPARE_REUSE_TAG_303_E = 901 , - WIFISPARE_REUSE_TAG_304_E = 902 , - WIFISPARE_REUSE_TAG_305_E = 903 , - WIFISPARE_REUSE_TAG_306_E = 904 , - WIFISPARE_REUSE_TAG_307_E = 905 , - WIFISPARE_REUSE_TAG_308_E = 906 , - WIFISPARE_REUSE_TAG_309_E = 907 , - WIFISPARE_REUSE_TAG_310_E = 908 , - WIFISPARE_REUSE_TAG_311_E = 909 , - WIFISPARE_REUSE_TAG_312_E = 910 , - WIFISPARE_REUSE_TAG_313_E = 911 , - WIFISPARE_REUSE_TAG_314_E = 912 , - WIFISPARE_REUSE_TAG_315_E = 913 , - WIFISPARE_REUSE_TAG_316_E = 914 , - WIFISPARE_REUSE_TAG_317_E = 915 , - WIFISPARE_REUSE_TAG_318_E = 916 , - WIFISPARE_REUSE_TAG_319_E = 917 , - WIFISPARE_REUSE_TAG_320_E = 918 , - WIFISPARE_REUSE_TAG_321_E = 919 , - WIFISPARE_REUSE_TAG_322_E = 920 , - WIFISPARE_REUSE_TAG_323_E = 921 , - WIFISPARE_REUSE_TAG_324_E = 922 , - WIFISPARE_REUSE_TAG_325_E = 923 , - WIFISPARE_REUSE_TAG_326_E = 924 , - WIFISPARE_REUSE_TAG_327_E = 925 , - WIFISPARE_REUSE_TAG_328_E = 926 , - WIFISPARE_REUSE_TAG_329_E = 927 , - WIFISPARE_REUSE_TAG_330_E = 928 , - WIFISPARE_REUSE_TAG_331_E = 929 , - WIFISPARE_REUSE_TAG_332_E = 930 , - WIFISPARE_REUSE_TAG_333_E = 931 , - WIFISPARE_REUSE_TAG_334_E = 932 , - WIFISPARE_REUSE_TAG_335_E = 933 , - WIFISPARE_REUSE_TAG_336_E = 934 , - WIFISPARE_REUSE_TAG_337_E = 935 , - WIFISPARE_REUSE_TAG_338_E = 936 , - WIFISPARE_REUSE_TAG_339_E = 937 , - WIFISPARE_REUSE_TAG_340_E = 938 , - WIFISPARE_REUSE_TAG_341_E = 939 , - WIFISPARE_REUSE_TAG_342_E = 940 , - WIFISPARE_REUSE_TAG_343_E = 941 , - WIFISPARE_REUSE_TAG_344_E = 942 , - WIFISPARE_REUSE_TAG_345_E = 943 , - WIFISPARE_REUSE_TAG_346_E = 944 , - WIFISPARE_REUSE_TAG_347_E = 945 , - WIFISPARE_REUSE_TAG_348_E = 946 , - WIFISPARE_REUSE_TAG_349_E = 947 , - WIFISPARE_REUSE_TAG_350_E = 948 , - WIFISPARE_REUSE_TAG_351_E = 949 , - WIFISPARE_REUSE_TAG_352_E = 950 , - WIFISPARE_REUSE_TAG_353_E = 951 , - WIFISPARE_REUSE_TAG_354_E = 952 , - WIFISPARE_REUSE_TAG_355_E = 953 , - WIFISPARE_REUSE_TAG_356_E = 954 , - WIFISPARE_REUSE_TAG_357_E = 955 , - WIFISPARE_REUSE_TAG_358_E = 956 , - WIFISPARE_REUSE_TAG_359_E = 957 , - WIFISPARE_REUSE_TAG_360_E = 958 , - WIFISPARE_REUSE_TAG_361_E = 959 , - WIFISPARE_REUSE_TAG_362_E = 960 , - WIFISPARE_REUSE_TAG_363_E = 961 , - WIFISPARE_REUSE_TAG_364_E = 962 , - WIFISPARE_REUSE_TAG_365_E = 963 , - WIFISPARE_REUSE_TAG_366_E = 964 , - WIFISPARE_REUSE_TAG_367_E = 965 , - WIFISPARE_REUSE_TAG_368_E = 966 , - WIFISPARE_REUSE_TAG_369_E = 967 , - WIFISPARE_REUSE_TAG_370_E = 968 , - WIFISPARE_REUSE_TAG_371_E = 969 , - WIFISPARE_REUSE_TAG_372_E = 970 , - WIFISPARE_REUSE_TAG_373_E = 971 , - WIFISPARE_REUSE_TAG_374_E = 972 , - WIFISPARE_REUSE_TAG_375_E = 973 , - WIFISPARE_REUSE_TAG_376_E = 974 , - WIFISPARE_REUSE_TAG_377_E = 975 , - WIFISPARE_REUSE_TAG_378_E = 976 , - WIFISPARE_REUSE_TAG_379_E = 977 , - WIFISPARE_REUSE_TAG_380_E = 978 , - WIFISPARE_REUSE_TAG_381_E = 979 , - WIFISPARE_REUSE_TAG_382_E = 980 , - WIFISPARE_REUSE_TAG_383_E = 981 , - WIFISPARE_REUSE_TAG_384_E = 982 , - WIFISPARE_REUSE_TAG_385_E = 983 , - WIFISPARE_REUSE_TAG_386_E = 984 , - WIFISPARE_REUSE_TAG_387_E = 985 , - WIFISPARE_REUSE_TAG_388_E = 986 , - WIFISPARE_REUSE_TAG_389_E = 987 , - WIFISPARE_REUSE_TAG_390_E = 988 , - WIFISPARE_REUSE_TAG_391_E = 989 , - WIFISPARE_REUSE_TAG_392_E = 990 , - WIFISPARE_REUSE_TAG_393_E = 991 , - WIFISPARE_REUSE_TAG_394_E = 992 , - WIFISPARE_REUSE_TAG_395_E = 993 , - WIFISPARE_REUSE_TAG_396_E = 994 , - WIFISPARE_REUSE_TAG_397_E = 995 , - WIFISPARE_REUSE_TAG_398_E = 996 , - WIFISPARE_REUSE_TAG_399_E = 997 , - WIFISPARE_REUSE_TAG_400_E = 998 , - WIFISPARE_REUSE_TAG_401_E = 999 , - WIFISPARE_REUSE_TAG_402_E = 1000 , - WIFISPARE_REUSE_TAG_403_E = 1001 , - WIFISPARE_REUSE_TAG_404_E = 1002 , - WIFISPARE_REUSE_TAG_405_E = 1003 , - WIFISPARE_REUSE_TAG_406_E = 1004 , - WIFISPARE_REUSE_TAG_407_E = 1005 , - WIFISPARE_REUSE_TAG_408_E = 1006 , - WIFISPARE_REUSE_TAG_409_E = 1007 , - WIFISPARE_REUSE_TAG_410_E = 1008 , - WIFISPARE_REUSE_TAG_411_E = 1009 , - WIFISPARE_REUSE_TAG_412_E = 1010 , - WIFISPARE_REUSE_TAG_413_E = 1011 , - WIFISPARE_REUSE_TAG_414_E = 1012 , - WIFISPARE_REUSE_TAG_415_E = 1013 , - WIFISPARE_REUSE_TAG_416_E = 1014 , - WIFISPARE_REUSE_TAG_417_E = 1015 , - WIFISPARE_REUSE_TAG_418_E = 1016 , - WIFISPARE_REUSE_TAG_419_E = 1017 , - WIFISPARE_REUSE_TAG_420_E = 1018 , - WIFISPARE_REUSE_TAG_421_E = 1019 , - WIFISPARE_REUSE_TAG_422_E = 1020 , - WIFISPARE_REUSE_TAG_423_E = 1021 -} tlv_tag_def__e; - -typedef enum { - WIFI_EXT_PHYRX_DATA_E = 1 , - WIFI_EXT_PHYRX_ABORT_REQUEST_E = 3 , - WIFI_EXT_MACTX_DATA_RESP_E = 5 , - WIFI_EXT_MACTX_CBF_DONE_E = 7 , - WIFI_EXT_RXPCU_TO_UCODE_START_E = 9 , - WIFI_EXT_RXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , - WIFI_EXT_RXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , - WIFI_EXT_RXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , - WIFI_EXT_PHYRX_RSSI_LEGACY_20MHZ_E = 17 , - WIFI_EXT_PHYRX_PKT_END_20MHZ_E = 19 , - WIFI_EXT_MACRX_CBF_DATA_REQUEST_E = 65 , - WIFI_EXT_MACRX_FREEZE_CAPTURE_CHANNEL_E = 67 , - WIFI_EXT_MACRX_ABORT_ACK_E = 69 , - WIFI_EXT_MACRX_CHAIN_MASK_E = 71 , - WIFI_EXT_MACRX_ABORT_REQUEST_E = 73 , - WIFI_EXT_PHYTX_ABORT_ACK_E = 75 , - WIFI_EXT_PHYTX_PKT_END_E = 77 , - WIFI_EXT_PHYTX_REQUEST_CTRL_INFO_E = 79 , - WIFI_EXT_PHYTX_BF_CV_LOADING_DONE_E = 81 , - WIFI_EXT_PHYTX_NAP_DONE_E = 83 , - WIFI_EXT_PHYTX_ON_ACK_E = 85 , - WIFI_EXT_PHYTX_DEBUG16_E = 87 , - WIFI_EXT_MACTX_ABORT_ACK_E = 89 , - WIFI_EXT_MACTX_PRE_PHY_DESC_E = 91 , - WIFI_EXT_MACTX_BF_PARAMS_PER_USER_E = 93 , - WIFI_EXT_MACTX_USER_DESC_COMMON_E = 95 , - WIFI_EXT_EXAMPLE_USER_TLV_16_E = 97 , - WIFI_EXT_MACTX_PHY_OFF_E = 99 , - WIFI_EXT_MACTX_SYNTH_OFF_E = 101 , - WIFI_EXT_MACTX_EXPECT_CBF_PER_USER_E = 103 , - WIFI_EXT_MACTX_L_SIG_A_E = 105 , - WIFI_EXT_MACTX_HT_SIG_E = 107 , - WIFI_EXT_MACTX_VHT_SIG_B_SU20_E = 109 , - WIFI_EXT_MACTX_VHT_SIG_B_SU80_E = 111 , - WIFI_EXT_MACTX_VHT_SIG_B_MU20_E = 113 , - WIFI_EXT_MACTX_VHT_SIG_B_MU80_E = 115 , - WIFI_EXT_MACTX_SERVICE_E = 117 , - WIFI_EXT_MACTX_HE_SIG_A_MU_DL_E = 119 , - WIFI_EXT_MACTX_HE_SIG_B1_MU_E = 121 , - WIFI_EXT_MACTX_HE_SIG_B2_OFDMA_E = 123 , - WIFI_EXT_MACTX_MU_UPLINK_COMMON_E = 125 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_E = 127 , - WIFI_EXT_MACTX_DEBUG_E = 129 , - WIFI_EXT_PHYRX_GENERATED_CBF_DETAILS_E = 131 , - WIFI_EXT_PHYRX_RSSI_HT_E = 133 , - WIFI_EXT_PHYRX_PKT_END_E = 135 , - WIFI_EXT_PHYRX_CBF_TRANSFER_DONE_E = 137 , - WIFI_EXT_PHYRX_L_SIG_A_E = 139 , - WIFI_EXT_PHYRX_HT_SIG_E = 141 , - WIFI_EXT_PHYRX_VHT_SIG_B_SU20_E = 143 , - WIFI_EXT_PHYRX_VHT_SIG_B_SU80_E = 145 , - WIFI_EXT_PHYRX_VHT_SIG_B_MU20_E = 147 , - WIFI_EXT_PHYRX_VHT_SIG_B_MU80_E = 149 , - WIFI_EXT_PHYRX_HE_SIG_A_SU_E = 151 , - WIFI_EXT_PHYRX_HE_SIG_A_MU_UL_E = 153 , - WIFI_EXT_PHYRX_HE_SIG_B2_MU_E = 155 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_E = 157 , - WIFI_EXT_PHYRX_DATA_DONE_E = 159 , - WIFI_EXT_DUMMY_E = 161 , - WIFI_EXT_MPDU_LIMIT_E = 163 , - WIFI_EXT_OLE_BUF_STATUS_E = 165 , - WIFI_EXT_PCU_PPDU_SETUP_END_E = 167 , - WIFI_EXT_PCU_PPDU_SETUP_START_E = 169 , - WIFI_EXT_PDG_RESPONSE_E = 171 , - WIFI_EXT_SCH_WAIT_INSTR_E = 173 , - WIFI_EXT_PHYTX_LINK_STATE_E = 175 , - WIFI_EXT_TQM_GEN_MPDU_LENGTH_LIST_E = 177 , - WIFI_EXT_TQM_GEN_MPDUS_E = 179 , - WIFI_EXT_TQM_REMOVE_MPDU_E = 181 , - WIFI_EXT_TQM_REMOVE_MSDU_E = 183 , - WIFI_EXT_TQM_UPDATE_TX_MPDU_COUNT_E = 185 , - WIFI_EXT_OFDMA_TRIGGER_DETAILS_E = 187 , - WIFI_EXT_TX_FES_SETUP_E = 189 , - WIFI_EXT_EXPECTED_RESPONSE_E = 191 , - WIFI_EXT_TX_MPDU_START_E = 193 , - WIFI_EXT_TX_MSDU_START_E = 195 , - WIFI_EXT_TXPCU_BUFFER_STATUS_E = 197 , - WIFI_EXT_DATA_TO_TIME_CONFIG_E = 199 , - WIFI_EXT_MPDU_INFO_E = 201 , - WIFI_EXT_TX_11AH_SETUP_E = 203 , - WIFI_EXT_TX_PEER_ENTRY_E = 205 , - WIFI_EXT_EXAMPLE_USER_TLV_44_E = 207 , - WIFI_EXT_TX_FLUSH_REQ_E = 209 , - WIFI_EXT_TQM_GET_MPDU_QUEUE_STATS_E = 211 , - WIFI_EXT_EXAMPLE_USER_CTLV_44_E = 213 , - WIFI_EXT_TX_FES_STATUS_USER_PPDU_E = 215 , - WIFI_EXT_TX_FES_STATUS_END_E = 217 , - WIFI_EXT_RXPCU_TX_SETUP_CLEAR_E = 219 , - WIFI_EXT_RX_FRAME_BITMAP_ACK_E = 221 , - WIFI_EXT_RX_START_PARAM_E = 223 , - WIFI_EXT_RX_PPDU_END_E = 225 , - WIFI_EXT_RX_MPDU_END_E = 227 , - WIFI_EXT_RX_MSDU_END_E = 229 , - WIFI_EXT_RECEIVED_RESPONSE_INFO_E = 231 , - WIFI_EXT_RX_HEADER_E = 233 , - WIFI_EXT_RX_FLUSH_E = 235 , - WIFI_EXT_RX_FRAMELESS_BAR_DETAILS_E = 237 , - WIFI_EXT_TQM_GET_MSDU_FLOW_STATS_STATUS_E = 239 , - WIFI_EXT_PCU_PPDU_SETUP_USER_E = 241 , - WIFI_EXT_RX_PM_INFO_E = 243 , - WIFI_EXT_RX_PRE_PPDU_START_E = 245 , - WIFI_EXT_TX_FES_SETUP_COMPLETE_E = 247 , - WIFI_EXT_TXDMA_STOP_REQUEST_E = 249 , - WIFI_EXT_RXPCU_USER_SETUP_E = 251 , - WIFI_EXT_TQM_ACKED_MPDU_E = 253 , - WIFI_EXT_COEX_TX_STATUS_E = 255 , - WIFI_EXT_COEX_STATUS_BROADCAST_E = 257 , - WIFI_EXT_RESPONSE_END_STATUS_E = 259 , - WIFI_EXT_RECEIVED_TRIGGER_INFO_E = 261 , - WIFI_EXT_RX_PPDU_ACK_REPORT_E = 263 , - WIFI_EXT_SCH_COEX_STATUS_E = 265 , - WIFI_EXT_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 267 , - WIFI_EXT_TX_FES_STATUS_START_PPDU_E = 269 , - WIFI_EXT_TXPCU_PHYTX_DEBUG32_E = 271 , - WIFI_EXT_TX_MPDU_COUNT_TRANSFER_END_E = 273 , - WIFI_EXT_WHO_ANCHOR_VALUE_E = 275 , - WIFI_EXT_WHO_COMMIT_E = 277 , - WIFI_EXT_WHO_FLUSH_E = 279 , - WIFI_EXT_WHO_L2_PAYLOAD_E = 281 , - WIFI_EXT_WHO_L3_INFO_E = 283 , - WIFI_EXT_WHO_L4_INFO_E = 285 , - WIFI_EXT_WHO_MSDU_MISC_E = 287 , - WIFI_EXT_WHO_PACKET_HDR_E = 289 , - WIFI_EXT_WHO_PPDU_START_E = 291 , - WIFI_EXT_WHO_WMAC_HEADER_PV0_E = 293 , - WIFI_EXT_WHO_WMAC_IV_E = 295 , - WIFI_EXT_MPDU_INFO_BITMAP_E = 297 , - WIFI_EXT_SCHEDULER_SELFGEN_RESPONSE_STATUS_E = 299 , - WIFI_EXT_TQM_ACKED_MPDU_STATUS_E = 301 , - WIFI_EXT_TQM_LIST_GEN_DONE_E = 303 , - WIFI_EXT_TX_LAST_MPDU_END_E = 305 , - WIFI_EXT_PPDU_TX_END_E = 307 , - WIFI_EXT_MPDU_INFO_GLOBAL_END_E = 309 , - WIFI_EXT_RX_PPDU_END_USER_STATS_E = 311 , - WIFI_EXT_TQM_FLUSH_CACHE_E = 321 , - WIFI_EXT_TQM_FLUSH_CACHE_STATUS_E = 323 , - WIFI_EXT_RX_PPDU_END_STATUS_DONE_E = 325 , - WIFI_EXT_SCHEDULER_MLO_SW_MSG_STATUS_E = 327 , - WIFI_EXT_TX_DATA_SYNC_E = 329 , - WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_E = 331 , - WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_STATUS_E = 333 , - WIFI_EXT_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 335 , - WIFI_EXT_EXAMPLE_USER_TLV_32_NAME_E = 341 , - WIFI_EXT_RX_RING_MASK_E = 343 , - WIFI_EXT_RXPCU_PPDU_END_INFO_E = 345 , - WIFI_EXT_PDG_SW_MODE_BW_START_E = 347 , - WIFI_EXT_PDG_WAIT_FOR_MAC_REQUEST_E = 349 , - WIFI_EXT_SCHEDULER_END_E = 351 , - WIFI_EXT_RX_PPDU_END_DROPPED_E = 353 , - WIFI_EXT_RX_MPDU_START_DROPPED_E = 355 , - WIFI_EXT_RX_MSDU_END_DROPPED_E = 357 , - WIFI_EXT_RX_ATTENTION_DROPPED_E = 359 , - WIFI_EXT_RXPCU_USER_SETUP_EXT_E = 361 , - WIFI_EXT_MACTX_SYNTH_ON_E = 363 , - WIFI_EXT_TQM_MPDU_GLOBAL_START_E = 365 , - WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_E = 367 , - WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 369 , - WIFI_EXT_PDG_TRIG_RESPONSE_E = 373 , - WIFI_EXT_ABORT_FROM_PHYRX_DETAILS_E = 375 , - WIFI_EXT_MPDUS_AVAILABLE_E = 377 , - WIFI_EXT_PHYRX_TX_START_TIMING_E = 379 , - WIFI_EXT_NDP_PREAMBLE_DONE_E = 381 , - WIFI_EXT_SCH_TQM_CMD_WRAPPER_CONT_DROP_E = 383 , - WIFI_EXT_TX_PUNCTURE_SETUP_E = 385 , - WIFI_EXT_MACTX_PREFETCH_CV_COMMON_E = 387 , - WIFI_EXT_MACTX_MU_UPLINK_COMMON_PUNC_E = 389 , - WIFI_EXT_RECEIVED_RESPONSE_USER_7_0_E = 391 , - WIFI_EXT_RECEIVED_RESPONSE_USER_23_16_E = 393 , - WIFI_EXT_RECEIVED_RESPONSE_USER_36_32_E = 395 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 397 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 399 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 401 , - WIFI_EXT_RX_PPDU_END_START_E = 403 , - WIFI_EXT_RX_PPDU_END_LAST_E = 405 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 407 , - WIFI_EXT_OBSS_SR_INFO_E = 409 , - WIFI_EXT_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 411 , - WIFI_EXT_MACTX_MCC_SWITCH_E = 413 , - WIFI_EXT_PHYTX_MCC_SWITCH_ACK_E = 415 , - WIFI_EXT_PHYTX_EMLSR_PRE_SWITCH_ACK_E = 417 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 419 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 421 , - WIFI_EXT_SCH_TLV_WRAPPER_E = 423 , - WIFI_EXT_MPDU_INFO_6X_E = 425 , - WIFI_EXT_MACTX_U_SIG_EHT_SU_MU_E = 427 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG0_CFG_E = 429 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG2_CFG_E = 431 , - WIFI_EXT_PHYRX_U_SIG_EHT_TB_E = 433 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 435 , - WIFI_EXT_MACRX_LMR_READ_REQUEST_E = 437 , - WIFI_EXT_PHYRX_LMR_TRANSFER_DONE_E = 439 , - WIFI_EXT_PHYRX_LMR_READ_REQUEST_ACK_E = 441 , - WIFI_EXT_PHYRX_USER_INFO_MU_UL_E = 443 , - WIFI_EXT_SCHEDULER_NAV_INFO_E = 445 , - WIFI_EXT_LMR_PEER_ENTRY_E = 447 , - WIFI_EXT_LMR_DATA_E = 449 , - WIFI_EXT_TX_FES_STATUS_1K_BA_E = 453 , - WIFI_EXT_MACRX_INBSS_OBSS_IND_E = 455 , - WIFI_EXT_MLO_TX_NOTIFICATION_SU_E = 457 , - WIFI_EXT_MLO_TX_REQ_SU_E = 459 , - WIFI_EXT_MLO_TX_RESP_E = 461 , - WIFI_EXT_MLO_BKOFF_TRUNC_REQ_E = 463 , - WIFI_EXT_MLO_MESSAGE_E = 465 , - WIFI_EXT_MLO_FES_SETUP_E = 467 , - WIFI_EXT_MLO_PDG_FES_SETUP_MU_E = 469 , - WIFI_EXT_MON_BUFFER_ADDR_E = 471 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 473 , - WIFI_EXT_MACTX_EHT_SIG_USR_OFDMA_E = 475 , - WIFI_EXT_MACTX_U_SIG_UHR_TB_E = 477 , - WIFI_EXT_TX_MSDU_COMPRESSED_DETAILS_TLV_E = 479 , - WIFI_EXT_PHYRX_EHT_SIG_USR_OFDMA_E = 481 , - WIFI_EXT_PHYRX_PKT_END_PART1_E = 483 , - WIFI_EXT_MACTX_SECURE_LTF_SEQ_PTR_E = 485 , - WIFI_EXT_MLO_PDG_BKOFF_TRUNC_NOTIFY_E = 487 , - WIFI_EXT_PHYTX_LOCATION_E = 489 , - WIFI_EXT_MPDU_LENGTH_STRUCTS_START_E = 491 , - WIFI_EXT_MACTX_EHT_SIG_USR_MU_MIMO_E = 493 , - WIFI_EXT_PHYRX_EHT_SIG_USR_MU_MIMO_E = 495 , - WIFI_EXT_PHYRX_GENERIC_EHT_OR_UHR_SIG_E = 497 , - WIFI_EXT_OVERWRITE_RESP_PREAMBLE_INFO_E = 499 , - WIFI_EXT_OVERWRITE_RESP_END_E = 501 , - WIFI_EXT_MON_DROP_E = 503 , - WIFI_EXT_MACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 505 , - WIFI_EXT_MACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 507 , - WIFI_EXT_MACTX_PREFETCH_CV_PER_USER_E = 509 , - WIFI_EXT_MACTX_BF_PARAMS_UPDATE_COMMON_E = 511 , - WIFI_EXT_RANGING_USER_DETAILS_E = 513 , - WIFI_EXT_PHYTX_CV_CORR_COMMON_E = 515 , - WIFI_EXT_MACTX_CV_CORR_COMMON_E = 517 , - WIFI_EXT_BW_PUNCTURE_EVAL_WRAPPER_E = 519 , - WIFI_EXT_MACTX_TX_NOTIFICATION_FOR_PHY_E = 521 , - WIFI_EXT_MACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 523 , - WIFI_EXT_FW2SW_MON_E = 525 , - WIFI_EXT_MACTX_EMLSR_PRE_SWITCH_E = 527 , - WIFI_EXT_MACTX_EMLSR_SWITCH_BACK_E = 529 , - WIFI_EXT_PHYTX_EMLSR_SWITCH_BACK_ACK_E = 531 , - WIFI_EXT_EAD_LEGACY_STATUS_CONTROL_E = 533 , - WIFI_EXT_TPI_TX_INITIALIZATION_CONFIG_E = 535 , - WIFI_EXT_TPI_LEGACY_STATUS_CONTROL_E = 537 , - WIFI_EXT_TPI_MPDU_START_E = 539 , - WIFI_EXT_TPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E = 541 , - WIFI_EXT_TPI_TX_START_TIME_ARRIVED_E = 543 , - WIFI_EXT_TPI_ERROR_STATUS_E = 545 , - WIFI_EXT_RPI_SEND_TLV_TO_PHYRX_E = 547 , - WIFI_EXT_RPI_LEGACY_INTERRUPT_CONTROL_E = 549 , - WIFI_EXT_RPI_ERROR_STATUS_E = 551 , - WIFI_EXT_RPI_RX_FRAME_UPDATE_STATUS_E = 553 , - WIFI_EXT_TCC_TLV_FETCH_E = 555 , - WIFI_EXT_TCC_LEGACY_INTERRUPT_CONTROL_E = 557 , - WIFI_EXT_TCC_ERROR_STATUS_E = 559 , - WIFI_EXT_TCC_PRE_BACKOFF_CMD_AVAILABLE_E = 561 , - WIFI_EXT_TCC_BURST_CMD_AVAILABLE_E = 563 , - WIFI_EXT_EAD_RING_AIR_TIME_REFERENCE_E = 565 , - WIFI_EXT_RPI_WRITE_INFO_TO_EXT_MEM_E = 567 , - WIFI_EXT_RPI_INIT_LMR_DATA_RESP_ADDR_E = 569 , - WIFI_EXT_TPI_SEND_CTLV_44_TO_PHYTX_E = 571 , - WIFI_EXT_TPI_TX_FRAME_UPDATE_STATUS_E = 573 , - WIFI_EXT_EAD_MPDU_DATA_FETCH_CONTINUATION_E = 575 , - WIFI_EXT_EAD_MSDU_STATUS_DETAILS_E = 577 , - WIFI_EXT_MACTX_UHR_SIG_USR_MU_MIMO_E = 579 , - WIFI_EXT_MACTX_ELR_SIG_UHR_SU_E = 581 , - WIFI_EXT_PEER_BLACKOUT_DETAILS_E = 583 , - WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_E = 585 , - WIFI_EXT_HDR_CTRL_PROT_DATA_E = 587 , - WIFI_EXT_HDR_CTRL_PROT_MIC_STATUS_E = 589 , - WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_DONE_E = 591 , - WIFI_EXT_MACTX_U_SIG_UHR_COBF_E = 593 , - WIFI_EXT_MACTX_U_SIG_UHR_COSR_E = 595 , - WIFI_EXT_OVERWRITE_CFP_INFO_E = 597 , - WIFI_EXT_SPARE_REUSE_TAG_1_E = 599 , - WIFI_EXT_SPARE_REUSE_TAG_3_E = 601 , - WIFI_EXT_SPARE_REUSE_TAG_5_E = 603 , - WIFI_EXT_SPARE_REUSE_TAG_7_E = 605 , - WIFI_EXT_SPARE_REUSE_TAG_9_E = 607 , - WIFI_EXT_SPARE_REUSE_TAG_11_E = 609 , - WIFI_EXT_SPARE_REUSE_TAG_13_E = 611 , - WIFI_EXT_SPARE_REUSE_TAG_15_E = 613 , - WIFI_EXT_SPARE_REUSE_TAG_17_E = 615 , - WIFI_EXT_SPARE_REUSE_TAG_19_E = 617 , - WIFI_EXT_SPARE_REUSE_TAG_21_E = 619 , - WIFI_EXT_SPARE_REUSE_TAG_23_E = 621 , - WIFI_EXT_SPARE_REUSE_TAG_25_E = 623 , - WIFI_EXT_SPARE_REUSE_TAG_27_E = 625 , - WIFI_EXT_SPARE_REUSE_TAG_29_E = 627 , - WIFI_EXT_SPARE_REUSE_TAG_31_E = 629 , - WIFI_EXT_SPARE_REUSE_TAG_33_E = 631 , - WIFI_EXT_SPARE_REUSE_TAG_35_E = 633 , - WIFI_EXT_SPARE_REUSE_TAG_37_E = 635 , - WIFI_EXT_SPARE_REUSE_TAG_39_E = 637 , - WIFI_EXT_SPARE_REUSE_TAG_41_E = 639 , - WIFI_EXT_SPARE_REUSE_TAG_43_E = 641 , - WIFI_EXT_SPARE_REUSE_TAG_45_E = 643 , - WIFI_EXT_SPARE_REUSE_TAG_47_E = 645 , - WIFI_EXT_SPARE_REUSE_TAG_49_E = 647 , - WIFI_EXT_SPARE_REUSE_TAG_51_E = 649 , - WIFI_EXT_SPARE_REUSE_TAG_53_E = 651 , - WIFI_EXT_SPARE_REUSE_TAG_55_E = 653 , - WIFI_EXT_SPARE_REUSE_TAG_57_E = 655 , - WIFI_EXT_SPARE_REUSE_TAG_59_E = 657 , - WIFI_EXT_SPARE_REUSE_TAG_61_E = 659 , - WIFI_EXT_SPARE_REUSE_TAG_63_E = 661 , - WIFI_EXT_SPARE_REUSE_TAG_65_E = 663 , - WIFI_EXT_SPARE_REUSE_TAG_67_E = 665 , - WIFI_EXT_SPARE_REUSE_TAG_69_E = 667 , - WIFI_EXT_SPARE_REUSE_TAG_71_E = 669 , - WIFI_EXT_SPARE_REUSE_TAG_73_E = 671 , - WIFI_EXT_SPARE_REUSE_TAG_75_E = 673 , - WIFI_EXT_SPARE_REUSE_TAG_77_E = 675 , - WIFI_EXT_SPARE_REUSE_TAG_79_E = 677 , - WIFI_EXT_SPARE_REUSE_TAG_81_E = 679 , - WIFI_EXT_SPARE_REUSE_TAG_83_E = 681 , - WIFI_EXT_SPARE_REUSE_TAG_85_E = 683 , - WIFI_EXT_SPARE_REUSE_TAG_87_E = 685 , - WIFI_EXT_SPARE_REUSE_TAG_89_E = 687 , - WIFI_EXT_SPARE_REUSE_TAG_91_E = 689 , - WIFI_EXT_SPARE_REUSE_TAG_93_E = 691 , - WIFI_EXT_SPARE_REUSE_TAG_95_E = 693 , - WIFI_EXT_SPARE_REUSE_TAG_97_E = 695 , - WIFI_EXT_SPARE_REUSE_TAG_99_E = 697 , - WIFI_EXT_SPARE_REUSE_TAG_101_E = 699 , - WIFI_EXT_SPARE_REUSE_TAG_103_E = 701 , - WIFI_EXT_SPARE_REUSE_TAG_105_E = 703 , - WIFI_EXT_SPARE_REUSE_TAG_107_E = 705 , - WIFI_EXT_SPARE_REUSE_TAG_109_E = 707 , - WIFI_EXT_SPARE_REUSE_TAG_111_E = 709 , - WIFI_EXT_SPARE_REUSE_TAG_113_E = 711 , - WIFI_EXT_SPARE_REUSE_TAG_115_E = 713 , - WIFI_EXT_SPARE_REUSE_TAG_117_E = 715 , - WIFI_EXT_SPARE_REUSE_TAG_119_E = 717 , - WIFI_EXT_SPARE_REUSE_TAG_121_E = 719 , - WIFI_EXT_SPARE_REUSE_TAG_123_E = 721 , - WIFI_EXT_SPARE_REUSE_TAG_125_E = 723 , - WIFI_EXT_SPARE_REUSE_TAG_127_E = 725 , - WIFI_EXT_SPARE_REUSE_TAG_129_E = 727 , - WIFI_EXT_SPARE_REUSE_TAG_131_E = 729 , - WIFI_EXT_SPARE_REUSE_TAG_133_E = 731 , - WIFI_EXT_SPARE_REUSE_TAG_135_E = 733 , - WIFI_EXT_SPARE_REUSE_TAG_137_E = 735 , - WIFI_EXT_SPARE_REUSE_TAG_139_E = 737 , - WIFI_EXT_SPARE_REUSE_TAG_141_E = 739 , - WIFI_EXT_SPARE_REUSE_TAG_143_E = 741 , - WIFI_EXT_SPARE_REUSE_TAG_145_E = 743 , - WIFI_EXT_SPARE_REUSE_TAG_147_E = 745 , - WIFI_EXT_SPARE_REUSE_TAG_149_E = 747 , - WIFI_EXT_SPARE_REUSE_TAG_151_E = 749 , - WIFI_EXT_SPARE_REUSE_TAG_153_E = 751 , - WIFI_EXT_SPARE_REUSE_TAG_155_E = 753 , - WIFI_EXT_SPARE_REUSE_TAG_157_E = 755 , - WIFI_EXT_SPARE_REUSE_TAG_159_E = 757 , - WIFI_EXT_SPARE_REUSE_TAG_161_E = 759 , - WIFI_EXT_SPARE_REUSE_TAG_163_E = 761 , - WIFI_EXT_SPARE_REUSE_TAG_165_E = 763 , - WIFI_EXT_SPARE_REUSE_TAG_167_E = 765 , - WIFI_EXT_SPARE_REUSE_TAG_169_E = 767 , - WIFI_EXT_SPARE_REUSE_TAG_171_E = 769 , - WIFI_EXT_SPARE_REUSE_TAG_173_E = 771 , - WIFI_EXT_SPARE_REUSE_TAG_175_E = 773 , - WIFI_EXT_SPARE_REUSE_TAG_177_E = 775 , - WIFI_EXT_SPARE_REUSE_TAG_179_E = 777 , - WIFI_EXT_SPARE_REUSE_TAG_181_E = 779 , - WIFI_EXT_SPARE_REUSE_TAG_183_E = 781 , - WIFI_EXT_SPARE_REUSE_TAG_185_E = 783 , - WIFI_EXT_SPARE_REUSE_TAG_187_E = 785 , - WIFI_EXT_SPARE_REUSE_TAG_189_E = 787 , - WIFI_EXT_SPARE_REUSE_TAG_191_E = 789 , - WIFI_EXT_SPARE_REUSE_TAG_193_E = 791 , - WIFI_EXT_SPARE_REUSE_TAG_195_E = 793 , - WIFI_EXT_SPARE_REUSE_TAG_197_E = 795 , - WIFI_EXT_SPARE_REUSE_TAG_199_E = 797 , - WIFI_EXT_SPARE_REUSE_TAG_201_E = 799 , - WIFI_EXT_SPARE_REUSE_TAG_203_E = 801 , - WIFI_EXT_SPARE_REUSE_TAG_205_E = 803 , - WIFI_EXT_SPARE_REUSE_TAG_207_E = 805 , - WIFI_EXT_SPARE_REUSE_TAG_209_E = 807 , - WIFI_EXT_SPARE_REUSE_TAG_211_E = 809 , - WIFI_EXT_SPARE_REUSE_TAG_213_E = 811 , - WIFI_EXT_SPARE_REUSE_TAG_215_E = 813 , - WIFI_EXT_SPARE_REUSE_TAG_217_E = 815 , - WIFI_EXT_SPARE_REUSE_TAG_219_E = 817 , - WIFI_EXT_SPARE_REUSE_TAG_221_E = 819 , - WIFI_EXT_SPARE_REUSE_TAG_223_E = 821 , - WIFI_EXT_SPARE_REUSE_TAG_225_E = 823 , - WIFI_EXT_SPARE_REUSE_TAG_227_E = 825 , - WIFI_EXT_SPARE_REUSE_TAG_229_E = 827 , - WIFI_EXT_SPARE_REUSE_TAG_231_E = 829 , - WIFI_EXT_SPARE_REUSE_TAG_233_E = 831 , - WIFI_EXT_SPARE_REUSE_TAG_235_E = 833 , - WIFI_EXT_SPARE_REUSE_TAG_237_E = 835 , - WIFI_EXT_SPARE_REUSE_TAG_239_E = 837 , - WIFI_EXT_SPARE_REUSE_TAG_241_E = 839 , - WIFI_EXT_SPARE_REUSE_TAG_243_E = 841 , - WIFI_EXT_SPARE_REUSE_TAG_245_E = 843 , - WIFI_EXT_SPARE_REUSE_TAG_247_E = 845 , - WIFI_EXT_SPARE_REUSE_TAG_249_E = 847 , - WIFI_EXT_SPARE_REUSE_TAG_251_E = 849 , - WIFI_EXT_SPARE_REUSE_TAG_253_E = 851 , - WIFI_EXT_SPARE_REUSE_TAG_255_E = 853 , - WIFI_EXT_SPARE_REUSE_TAG_257_E = 855 , - WIFI_EXT_SPARE_REUSE_TAG_259_E = 857 , - WIFI_EXT_SPARE_REUSE_TAG_261_E = 859 , - WIFI_EXT_SPARE_REUSE_TAG_263_E = 861 , - WIFI_EXT_SPARE_REUSE_TAG_265_E = 863 , - WIFI_EXT_SPARE_REUSE_TAG_267_E = 865 , - WIFI_EXT_SPARE_REUSE_TAG_269_E = 867 , - WIFI_EXT_SPARE_REUSE_TAG_271_E = 869 , - WIFI_EXT_SPARE_REUSE_TAG_273_E = 871 , - WIFI_EXT_SPARE_REUSE_TAG_275_E = 873 , - WIFI_EXT_SPARE_REUSE_TAG_277_E = 875 , - WIFI_EXT_SPARE_REUSE_TAG_279_E = 877 , - WIFI_EXT_SPARE_REUSE_TAG_281_E = 879 , - WIFI_EXT_SPARE_REUSE_TAG_283_E = 881 , - WIFI_EXT_SPARE_REUSE_TAG_285_E = 883 , - WIFI_EXT_SPARE_REUSE_TAG_287_E = 885 , - WIFI_EXT_SPARE_REUSE_TAG_289_E = 887 , - WIFI_EXT_SPARE_REUSE_TAG_291_E = 889 , - WIFI_EXT_SPARE_REUSE_TAG_293_E = 891 , - WIFI_EXT_SPARE_REUSE_TAG_295_E = 893 , - WIFI_EXT_SPARE_REUSE_TAG_297_E = 895 , - WIFI_EXT_SPARE_REUSE_TAG_299_E = 897 , - WIFI_EXT_SPARE_REUSE_TAG_301_E = 899 , - WIFI_EXT_SPARE_REUSE_TAG_303_E = 901 , - WIFI_EXT_SPARE_REUSE_TAG_305_E = 903 , - WIFI_EXT_SPARE_REUSE_TAG_307_E = 905 , - WIFI_EXT_SPARE_REUSE_TAG_309_E = 907 , - WIFI_EXT_SPARE_REUSE_TAG_311_E = 909 , - WIFI_EXT_SPARE_REUSE_TAG_313_E = 911 , - WIFI_EXT_SPARE_REUSE_TAG_315_E = 913 , - WIFI_EXT_SPARE_REUSE_TAG_317_E = 915 , - WIFI_EXT_SPARE_REUSE_TAG_319_E = 917 , - WIFI_EXT_SPARE_REUSE_TAG_321_E = 919 , - WIFI_EXT_SPARE_REUSE_TAG_323_E = 921 , - WIFI_EXT_SPARE_REUSE_TAG_325_E = 923 , - WIFI_EXT_SPARE_REUSE_TAG_327_E = 925 , - WIFI_EXT_SPARE_REUSE_TAG_329_E = 927 , - WIFI_EXT_SPARE_REUSE_TAG_331_E = 929 , - WIFI_EXT_SPARE_REUSE_TAG_333_E = 931 , - WIFI_EXT_SPARE_REUSE_TAG_335_E = 933 , - WIFI_EXT_SPARE_REUSE_TAG_337_E = 935 , - WIFI_EXT_SPARE_REUSE_TAG_339_E = 937 , - WIFI_EXT_SPARE_REUSE_TAG_341_E = 939 , - WIFI_EXT_SPARE_REUSE_TAG_343_E = 941 , - WIFI_EXT_SPARE_REUSE_TAG_345_E = 943 , - WIFI_EXT_SPARE_REUSE_TAG_347_E = 945 , - WIFI_EXT_SPARE_REUSE_TAG_349_E = 947 , - WIFI_EXT_SPARE_REUSE_TAG_351_E = 949 , - WIFI_EXT_SPARE_REUSE_TAG_353_E = 951 , - WIFI_EXT_SPARE_REUSE_TAG_355_E = 953 , - WIFI_EXT_SPARE_REUSE_TAG_357_E = 955 , - WIFI_EXT_SPARE_REUSE_TAG_359_E = 957 , - WIFI_EXT_SPARE_REUSE_TAG_361_E = 959 , - WIFI_EXT_SPARE_REUSE_TAG_363_E = 961 , - WIFI_EXT_SPARE_REUSE_TAG_365_E = 963 , - WIFI_EXT_SPARE_REUSE_TAG_367_E = 965 , - WIFI_EXT_SPARE_REUSE_TAG_369_E = 967 , - WIFI_EXT_SPARE_REUSE_TAG_371_E = 969 , - WIFI_EXT_SPARE_REUSE_TAG_373_E = 971 , - WIFI_EXT_SPARE_REUSE_TAG_375_E = 973 , - WIFI_EXT_SPARE_REUSE_TAG_377_E = 975 , - WIFI_EXT_SPARE_REUSE_TAG_379_E = 977 , - WIFI_EXT_SPARE_REUSE_TAG_381_E = 979 , - WIFI_EXT_SPARE_REUSE_TAG_383_E = 981 , - WIFI_EXT_SPARE_REUSE_TAG_385_E = 983 , - WIFI_EXT_SPARE_REUSE_TAG_387_E = 985 , - WIFI_EXT_SPARE_REUSE_TAG_389_E = 987 , - WIFI_EXT_SPARE_REUSE_TAG_391_E = 989 , - WIFI_EXT_SPARE_REUSE_TAG_393_E = 991 , - WIFI_EXT_SPARE_REUSE_TAG_395_E = 993 , - WIFI_EXT_SPARE_REUSE_TAG_397_E = 995 , - WIFI_EXT_SPARE_REUSE_TAG_399_E = 997 , - WIFI_EXT_SPARE_REUSE_TAG_401_E = 999 , - WIFI_EXT_SPARE_REUSE_TAG_403_E = 1001 , - WIFI_EXT_SPARE_REUSE_TAG_405_E = 1003 , - WIFI_EXT_SPARE_REUSE_TAG_407_E = 1005 , - WIFI_EXT_SPARE_REUSE_TAG_409_E = 1007 , - WIFI_EXT_SPARE_REUSE_TAG_411_E = 1009 , - WIFI_EXT_SPARE_REUSE_TAG_413_E = 1011 , - WIFI_EXT_SPARE_REUSE_TAG_415_E = 1013 , - WIFI_EXT_SPARE_REUSE_TAG_417_E = 1015 , - WIFI_EXT_SPARE_REUSE_TAG_419_E = 1017 , - WIFI_EXT_SPARE_REUSE_TAG_421_E = 1019 , - WIFI_EXT_SPARE_REUSE_TAG_423_E = 1021 -} ext_tlv_tag_def__e; - -typedef enum { - WIFI_N_EXT_MACTX_CBF_START_E = 0 , - WIFI_N_EXT_PHYRX_CBF_DATA_RESP_E = 2 , - WIFI_N_EXT_PHYRX_USER_ABORT_NOTIFICATION_E = 4 , - WIFI_N_EXT_MACTX_CBF_DATA_E = 6 , - WIFI_N_EXT_PHYRX_LMR_DATA_RESP_E = 8 , - WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , - WIFI_N_EXT_RXPCU_TO_UCODE_FCS_STATUS_E = 12 , - WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , - WIFI_N_EXT_RXPCU_TO_UCODE_END_E = 16 , - WIFI_N_EXT_PHYRX_NC_ABORT_REQUEST_E = 18 , - WIFI_N_EXT_PHYRX_NC_DATA_E = 20 , - WIFI_N_EXT_MACRX_CBF_READ_REQUEST_E = 64 , - WIFI_N_EXT_MACRX_EXPECT_NDP_RECEPTION_E = 66 , - WIFI_N_EXT_MACRX_NDP_TIMEOUT_E = 68 , - WIFI_N_EXT_MACRX_REQ_IMPLICIT_FB_E = 70 , - WIFI_N_EXT_MACRX_NAP_USER_E = 72 , - WIFI_N_EXT_PHYTX_OTHER_TRANSMIT_INFO16_E = 74 , - WIFI_N_EXT_PHYTX_ABORT_REQUEST_E = 76 , - WIFI_N_EXT_PHYTX_PPDU_HEADER_INFO_REQUEST_E = 78 , - WIFI_N_EXT_PHYTX_DATA_REQUEST_E = 80 , - WIFI_N_EXT_PHYTX_NAP_ACK_E = 82 , - WIFI_N_EXT_PHYTX_OFF_ACK_E = 84 , - WIFI_N_EXT_PHYTX_SYNTH_OFF_ACK_E = 86 , - WIFI_N_EXT_MACTX_ABORT_REQUEST_E = 88 , - WIFI_N_EXT_MACTX_PKT_END_E = 90 , - WIFI_N_EXT_MACTX_BF_PARAMS_COMMON_E = 92 , - WIFI_N_EXT_MACTX_PREFETCH_CV_E = 94 , - WIFI_N_EXT_MACTX_USER_DESC_PER_USER_E = 96 , - WIFI_N_EXT_EXAMPLE_TLV_16_E = 98 , - WIFI_N_EXT_MACTX_PHY_ON_E = 100 , - WIFI_N_EXT_MACTX_EXPECT_CBF_COMMON_E = 102 , - WIFI_N_EXT_MACTX_PHY_DESC_E = 104 , - WIFI_N_EXT_MACTX_L_SIG_B_E = 106 , - WIFI_N_EXT_MACTX_VHT_SIG_A_E = 108 , - WIFI_N_EXT_MACTX_VHT_SIG_B_SU40_E = 110 , - WIFI_N_EXT_MACTX_VHT_SIG_B_SU160_E = 112 , - WIFI_N_EXT_MACTX_VHT_SIG_B_MU40_E = 114 , - WIFI_N_EXT_MACTX_VHT_SIG_B_MU160_E = 116 , - WIFI_N_EXT_MACTX_HE_SIG_A_SU_E = 118 , - WIFI_N_EXT_MACTX_HE_SIG_A_MU_UL_E = 120 , - WIFI_N_EXT_MACTX_HE_SIG_B2_MU_E = 122 , - WIFI_N_EXT_MACTX_DELETE_CV_E = 124 , - WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_E = 126 , - WIFI_N_EXT_MACTX_PHY_NAP_E = 128 , - WIFI_N_EXT_PHYRX_ABORT_ACK_E = 130 , - WIFI_N_EXT_PHYRX_RSSI_LEGACY_E = 132 , - WIFI_N_EXT_PHYRX_USER_INFO_E = 134 , - WIFI_N_EXT_PHYRX_DEBUG_E = 136 , - WIFI_N_EXT_PHYRX_CBF_TRANSFER_ABORT_E = 138 , - WIFI_N_EXT_PHYRX_L_SIG_B_E = 140 , - WIFI_N_EXT_PHYRX_VHT_SIG_A_E = 142 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_SU40_E = 144 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_SU160_E = 146 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_MU40_E = 148 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_MU160_E = 150 , - WIFI_N_EXT_PHYRX_HE_SIG_A_MU_DL_E = 152 , - WIFI_N_EXT_PHYRX_HE_SIG_B1_MU_E = 154 , - WIFI_N_EXT_PHYRX_HE_SIG_B2_OFDMA_E = 156 , - WIFI_N_EXT_PHYRX_COMMON_USER_INFO_E = 158 , - WIFI_N_EXT_COEX_TX_REQ_E = 160 , - WIFI_N_EXT_EXAMPLE_TLV_32_NAME_E = 162 , - WIFI_N_EXT_NA_LENGTH_END_E = 164 , - WIFI_N_EXT_PCU_PPDU_SETUP_DONE_E = 166 , - WIFI_N_EXT_PCU_PPDU_SETUP_INIT_E = 168 , - WIFI_N_EXT_PDG_FES_SETUP_E = 170 , - WIFI_N_EXT_PDG_TX_REQ_E = 172 , - WIFI_N_EXT_MACTX_SWITCH_TO_MAIN_E = 174 , - WIFI_N_EXT_AUX_PPDU_END_E = 176 , - WIFI_N_EXT_TQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 178 , - WIFI_N_EXT_TQM_GEN_MPDUS_STATUS_E = 180 , - WIFI_N_EXT_TQM_REMOVE_MPDU_STATUS_E = 182 , - WIFI_N_EXT_TQM_REMOVE_MSDU_STATUS_E = 184 , - WIFI_N_EXT_TQM_WRITE_CMD_E = 186 , - WIFI_N_EXT_TX_DATA_E = 188 , - WIFI_N_EXT_RX_PACKET_E = 190 , - WIFI_N_EXT_TX_MPDU_END_E = 192 , - WIFI_N_EXT_TX_MSDU_END_E = 194 , - WIFI_N_EXT_TX_SW_MODE_SETUP_E = 196 , - WIFI_N_EXT_TXPCU_USER_BUFFER_STATUS_E = 198 , - WIFI_N_EXT_EXAMPLE_USER_TLV_32_E = 200 , - WIFI_N_EXT_PDG_USER_SETUP_E = 202 , - WIFI_N_EXT_TX_RAW_OR_NATIVE_FRAME_SETUP_E = 206 , - WIFI_N_EXT_TX_FLUSH_E = 208 , - WIFI_N_EXT_TQM_WRITE_CMD_STATUS_E = 210 , - WIFI_N_EXT_TQM_GET_MSDU_FLOW_STATS_E = 212 , - WIFI_N_EXT_TX_FES_STATUS_START_E = 214 , - WIFI_N_EXT_TX_FES_STATUS_USER_RESPONSE_E = 216 , - WIFI_N_EXT_RX_TRIG_INFO_E = 218 , - WIFI_N_EXT_RX_FRAME_BITMAP_REQ_E = 220 , - WIFI_N_EXT_COEX_RX_STATUS_E = 222 , - WIFI_N_EXT_RX_PPDU_START_E = 224 , - WIFI_N_EXT_RX_MPDU_START_E = 226 , - WIFI_N_EXT_RX_MSDU_START_E = 228 , - WIFI_N_EXT_RX_ATTENTION_E = 230 , - WIFI_N_EXT_RX_PHY_SLEEP_E = 232 , - WIFI_N_EXT_RX_PEER_ENTRY_E = 234 , - WIFI_N_EXT_RX_RESPONSE_REQUIRED_INFO_E = 236 , - WIFI_N_EXT_TQM_GET_MPDU_QUEUE_STATS_STATUS_E = 238 , - WIFI_N_EXT_TX_CBF_INFO_E = 240 , - WIFI_N_EXT_RX_MPDU_PCU_START_E = 242 , - WIFI_N_EXT_RX_USER_PPDU_END_E = 244 , - WIFI_N_EXT_RX_PREAMBLE_E = 246 , - WIFI_N_EXT_TX_LAST_MPDU_FETCHED_E = 248 , - WIFI_N_EXT_RXPCU_SETUP_E = 250 , - WIFI_N_EXT_TX_FES_STATUS_ACK_OR_BA_E = 252 , - WIFI_N_EXT_COEX_TX_RESP_E = 254 , - WIFI_N_EXT_MACTX_COEX_PHY_CTRL_E = 256 , - WIFI_N_EXT_RESPONSE_START_STATUS_E = 258 , - WIFI_N_EXT_CRYPTO_STATUS_E = 260 , - WIFI_N_EXT_COEX_TX_STOP_CTRL_E = 262 , - WIFI_N_EXT_RX_PPDU_NO_ACK_REPORT_E = 264 , - WIFI_N_EXT_SCHEDULER_COMMAND_STATUS_E = 266 , - WIFI_N_EXT_TX_FES_STATUS_PROT_E = 268 , - WIFI_N_EXT_TX_FES_STATUS_START_PROT_E = 270 , - WIFI_N_EXT_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 272 , - WIFI_N_EXT_WHO_ANCHOR_OFFSET_E = 274 , - WIFI_N_EXT_WHO_CCE_INFO_E = 276 , - WIFI_N_EXT_WHO_COMMIT_DONE_E = 278 , - WIFI_N_EXT_WHO_L2_LLC_E = 280 , - WIFI_N_EXT_WHO_L3_CHECKSUM_E = 282 , - WIFI_N_EXT_WHO_L4_CHECKSUM_E = 284 , - WIFI_N_EXT_WHO_MSDU_E = 286 , - WIFI_N_EXT_WHO_PACKET_DATA_E = 288 , - WIFI_N_EXT_WHO_PPDU_END_E = 290 , - WIFI_N_EXT_WHO_TSO_E = 292 , - WIFI_N_EXT_WHO_WMAC_HEADER_PV1_E = 294 , - WIFI_N_EXT_MPDU_INFO_END_E = 296 , - WIFI_N_EXT_TX_QUEUE_EXTENSION_E = 298 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 300 , - WIFI_N_EXT_TQM_ADD_MSDU_STATUS_E = 302 , - WIFI_N_EXT_WHO_TERMINATE_E = 304 , - WIFI_N_EXT_TX_CV_DATA_E = 306 , - WIFI_N_EXT_PROT_TX_END_E = 308 , - WIFI_N_EXT_TQM_SCH_INSTR_GLOBAL_END_E = 310 , - WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT_E = 312 , - WIFI_N_EXT_TQM_UNBLOCK_CACHE_E = 322 , - WIFI_N_EXT_TQM_UNBLOCK_CACHE_STATUS_E = 324 , - WIFI_N_EXT_RX_STATUS_BUFFER_DONE_E = 326 , - WIFI_N_EXT_SCHEDULER_TXOP_DURATION_TRIGGER_E = 328 , - WIFI_N_EXT_PHYRX_CBF_READ_REQUEST_ACK_E = 330 , - WIFI_N_EXT_TQM_SYNC_CMD_E = 332 , - WIFI_N_EXT_TQM_SYNC_CMD_STATUS_E = 334 , - WIFI_N_EXT_TCC_TQM_WRAPPER_CMD_E = 336 , - WIFI_N_EXT_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 340 , - WIFI_N_EXT_RX_PPDU_START_USER_INFO_E = 342 , - WIFI_N_EXT_COEX_MAC_NAP_E = 344 , - WIFI_N_EXT_WHO_MESH_CONTROL_E = 346 , - WIFI_N_EXT_PDG_SW_MODE_BW_END_E = 348 , - WIFI_N_EXT_PDG_WAIT_FOR_PHY_REQUEST_E = 350 , - WIFI_N_EXT_RX_PPDU_START_DROPPED_E = 352 , - WIFI_N_EXT_RX_PPDU_END_STATUS_DONE_DROPPED_E = 354 , - WIFI_N_EXT_RX_MSDU_START_DROPPED_E = 356 , - WIFI_N_EXT_RX_MPDU_END_DROPPED_E = 358 , - WIFI_N_EXT_TXPCU_USER_SETUP_E = 360 , - WIFI_N_EXT_CMD_PART_0_END_E = 362 , - WIFI_N_EXT_SCH_CRITICAL_TLV_REFERENCE_E = 364 , - WIFI_N_EXT_EXAMPLE_TLV_32_E = 366 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 368 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 370 , - WIFI_N_EXT_TQM_2_SCH_MPDU_AVAILABLE_E = 372 , - WIFI_N_EXT_TRIGGER_RESPONSE_TX_DONE_E = 374 , - WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_E = 376 , - WIFI_N_EXT_RECEIVED_RESPONSE_INFO_PART2_E = 378 , - WIFI_N_EXT_TXPCU_PREAMBLE_DONE_E = 380 , - WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_RBO_DROP_E = 382 , - WIFI_N_EXT_MACTX_CLEAR_PREV_TX_INFO_E = 384 , - WIFI_N_EXT_R2R_STATUS_END_E = 386 , - WIFI_N_EXT_END_OF_FLUSH_MARKER_E = 388 , - WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_PUNC_E = 390 , - WIFI_N_EXT_RECEIVED_RESPONSE_USER_15_8_E = 392 , - WIFI_N_EXT_RECEIVED_RESPONSE_USER_31_24_E = 394 , - WIFI_N_EXT_TX_LOOPBACK_SETUP_E = 396 , - WIFI_N_EXT_SCH_WAIT_INSTR_TX_PATH_E = 398 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 400 , - WIFI_N_EXT_TX_WUR_DATA_E = 402 , - WIFI_N_EXT_RX_PPDU_END_MIDDLE_E = 404 , - WIFI_N_EXT_MACTX_BACKOFF_BASED_TRANSMISSION_E = 406 , - WIFI_N_EXT_SRP_INFO_E = 408 , - WIFI_N_EXT_SCHEDULER_SW_MSG_STATUS_E = 410 , - WIFI_N_EXT_RXPCU_SETUP_COMPLETE_E = 412 , - WIFI_N_EXT_MACTX_MCC_SWITCH_BACK_E = 414 , - WIFI_N_EXT_PHYTX_MCC_SWITCH_BACK_ACK_E = 416 , - WIFI_N_EXT_LMR_TX_END_E = 418 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 420 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 422 , - WIFI_N_EXT_SCHEDULER_STATUS_WRAPPER_E = 424 , - WIFI_N_EXT_MACTX___RESERVED_G_0013 = 426 , - WIFI_N_EXT_MACTX_U_SIG_EHT_TB_E = 428 , - WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG1_CFG_E = 430 , - WIFI_N_EXT_PHYRX_U_SIG_EHT_SU_MU_E = 432 , - WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG3_CFG_E = 434 , - WIFI_N_EXT_TX_PUNCTURE_6PATTERNS_SETUP_E = 436 , - WIFI_N_EXT_MACRX_LMR_DATA_REQUEST_E = 438 , - WIFI_N_EXT_PHYRX_LMR_TRANSFER_ABORT_E = 440 , - WIFI_N_EXT_MACRX_SECURE_LTF_SEQ_PTR_E = 442 , - WIFI_N_EXT_MPDU_QUEUE_OVERVIEW_E = 444 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 446 , - WIFI_N_EXT_LMR_MPDU_START_E = 448 , - WIFI_N_EXT_LMR_MPDU_END_E = 450 , - WIFI_N_EXT_RX_FRAME_1K_BITMAP_ACK_E = 452 , - WIFI_N_EXT_TQM_ACKED_1K_MPDU_E = 454 , - WIFI_N_EXT_PHYRX_LOCATION_E = 456 , - WIFI_N_EXT_MLO_TX_NOTIFICATION_MU_E = 458 , - WIFI_N_EXT_MLO_TX_REQ_MU_E = 460 , - WIFI_N_EXT_MLO_RX_NOTIFICATION_E = 462 , - WIFI_N_EXT_MLO_TBTT_NOTIFICATION_E = 464 , - WIFI_N_EXT_MLO_TS_SYNC_MSG_E = 466 , - WIFI_N_EXT_MLO_PDG_FES_SETUP_SU_E = 468 , - WIFI_N_EXT_MPDU_INFO_1K_BITMAP_E = 470 , - WIFI_N_EXT_TX_FRAG_STATE_E = 472 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 474 , - WIFI_N_EXT_MACTX_U_SIG_UHR_SU_MU_E = 476 , - WIFI_N_EXT_TX_MPDU_COMPRESSED_DETAILS_TLV_E = 478 , - WIFI_N_EXT_TX_MSDU_COMPONENT_DETAILS_TLV_E = 480 , - WIFI_N_EXT_SCHEDULER_IU_TEMPLATE_ID_E = 482 , - WIFI_N_EXT_MACTX_EXPECT_NDP_RECEPTION_E = 484 , - WIFI_N_EXT_TX_MPDU_LENGTH_AND_RESTRICTIONS_E = 486 , - WIFI_N_EXT_PHYRX___RESERVED_G_0014 = 488 , - WIFI_N_EXT_PHYTX___RESERVED_G_0014 = 490 , - WIFI_N_EXT_MACTX_EHT_SIG_USR_SU_E = 492 , - WIFI_N_EXT_PHYRX_EHT_SIG_USR_SU_E = 494 , - WIFI_N_EXT_PHYRX_GENERIC_U_SIG_E = 496 , - WIFI_N_EXT_OVERWRITE_RESP_START_E = 498 , - WIFI_N_EXT_OVERWRITE_RESP_FRAME_INFO_E = 500 , - WIFI_N_EXT_RXPCU_EARLY_RX_INDICATION_E = 502 , - WIFI_N_EXT_MACRX_MU_UPLINK_COMMON_SNIFF_E = 504 , - WIFI_N_EXT_MACRX_MU_UPLINK_USER_SEL_SNIFF_E = 506 , - WIFI_N_EXT_MACTX_PREFETCH_CV_DMA_E = 508 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 510 , - WIFI_N_EXT_MACTX_BF_PARAMS_UPDATE_PER_USER_E = 512 , - WIFI_N_EXT_PHYTX_CV_CORR_STATUS_E = 514 , - WIFI_N_EXT_PHYTX_CV_CORR_USER_E = 516 , - WIFI_N_EXT_MACTX_CV_CORR_MAC_INFO_GROUP_E = 518 , - WIFI_N_EXT_MACTX_RX_NOTIFICATION_FOR_PHY_E = 520 , - WIFI_N_EXT_MACTX_MU_UPLINK_COMMON_PER_BW_E = 522 , - WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT2_E = 524 , - WIFI_N_EXT_WSI_DIRECT_MESSAGE_E = 526 , - WIFI_N_EXT_MACTX_EMLSR_SWITCH_E = 528 , - WIFI_N_EXT_PHYTX_EMLSR_SWITCH_ACK_E = 530 , - WIFI_N_EXT_EAD_COMMAND_E = 532 , - WIFI_N_EXT_EAD_LEGACY_INTERRUPT_CONTROL_E = 534 , - WIFI_N_EXT_TPI_ENABLE_RESPONSE_TIMEOUT_E = 536 , - WIFI_N_EXT_TPI_LEGACY_INTERRUPT_CONTROL_E = 538 , - WIFI_N_EXT_TPI_MPDU_CONTINUATION_E = 540 , - WIFI_N_EXT_TPI_SEND_TLV_TO_PHYTX_E = 542 , - WIFI_N_EXT_TPI_STATUS_E = 544 , - WIFI_N_EXT_TPI_TIMESTAMP_STATUS_E = 546 , - WIFI_N_EXT_RPI_LEGACY_STATUS_CONTROL_E = 548 , - WIFI_N_EXT_RPI_STATUS_E = 550 , - WIFI_N_EXT_RPI_TIMESTAMP_STATUS_E = 552 , - WIFI_N_EXT_TCC_PUSH_TRANSMIT_COMMAND_E = 554 , - WIFI_N_EXT_TCC_LEGACY_STATUS_CONTROL_E = 556 , - WIFI_N_EXT_TCC_STATUS_E = 558 , - WIFI_N_EXT_TCC_TIMESTAMP_STATUS_E = 560 , - WIFI_N_EXT_TCC_SCHEDULER_CMD_E = 562 , - WIFI_N_EXT_RPI_NON_DATA_CTLV_44_FROM_PHYRX_E = 564 , - WIFI_N_EXT_RPI_FETCH_INFO_FROM_EXT_MEM_E = 566 , - WIFI_N_EXT_RPI_INIT_CBF_DATA_RESP_ADDR_E = 568 , - WIFI_N_EXT_TPI_SEND_CBF_DATA_TO_PHYTX_E = 570 , - WIFI_N_EXT_TCC_FES_END_MESSAGE_E = 572 , - WIFI_N_EXT_TPI_DISABLE_RESPONSE_TIMEOUT_E = 574 , - WIFI_N_EXT_EAD_MSDU_STATUS_START_E = 576 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_SU_E = 578 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_OFDMA_E = 580 , - WIFI_N_EXT_COEX_BLACKOUT_DETAILS_E = 582 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E = 584 , - WIFI_N_EXT_HDR_CTRL_PROT_MPDU_START_E = 586 , - WIFI_N_EXT_HDR_CTRL_PROT_MPDU_END_E = 588 , - WIFI_N_EXT_HDR_CTRL_PROT_PEER_INFO_E = 590 , - WIFI_N_EXT_MACTX_U_SIG_UHR_ELR_SU_E = 592 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_COBF_E = 594 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_COSR_E = 596 , - WIFI_N_EXT_SPARE_REUSE_TAG_0_E = 598 , - WIFI_N_EXT_SPARE_REUSE_TAG_2_E = 600 , - WIFI_N_EXT_SPARE_REUSE_TAG_4_E = 602 , - WIFI_N_EXT_SPARE_REUSE_TAG_6_E = 604 , - WIFI_N_EXT_SPARE_REUSE_TAG_8_E = 606 , - WIFI_N_EXT_SPARE_REUSE_TAG_10_E = 608 , - WIFI_N_EXT_SPARE_REUSE_TAG_12_E = 610 , - WIFI_N_EXT_SPARE_REUSE_TAG_14_E = 612 , - WIFI_N_EXT_SPARE_REUSE_TAG_16_E = 614 , - WIFI_N_EXT_SPARE_REUSE_TAG_18_E = 616 , - WIFI_N_EXT_SPARE_REUSE_TAG_20_E = 618 , - WIFI_N_EXT_SPARE_REUSE_TAG_22_E = 620 , - WIFI_N_EXT_SPARE_REUSE_TAG_24_E = 622 , - WIFI_N_EXT_SPARE_REUSE_TAG_26_E = 624 , - WIFI_N_EXT_SPARE_REUSE_TAG_28_E = 626 , - WIFI_N_EXT_SPARE_REUSE_TAG_30_E = 628 , - WIFI_N_EXT_SPARE_REUSE_TAG_32_E = 630 , - WIFI_N_EXT_SPARE_REUSE_TAG_34_E = 632 , - WIFI_N_EXT_SPARE_REUSE_TAG_36_E = 634 , - WIFI_N_EXT_SPARE_REUSE_TAG_38_E = 636 , - WIFI_N_EXT_SPARE_REUSE_TAG_40_E = 638 , - WIFI_N_EXT_SPARE_REUSE_TAG_42_E = 640 , - WIFI_N_EXT_SPARE_REUSE_TAG_44_E = 642 , - WIFI_N_EXT_SPARE_REUSE_TAG_46_E = 644 , - WIFI_N_EXT_SPARE_REUSE_TAG_48_E = 646 , - WIFI_N_EXT_SPARE_REUSE_TAG_50_E = 648 , - WIFI_N_EXT_SPARE_REUSE_TAG_52_E = 650 , - WIFI_N_EXT_SPARE_REUSE_TAG_54_E = 652 , - WIFI_N_EXT_SPARE_REUSE_TAG_56_E = 654 , - WIFI_N_EXT_SPARE_REUSE_TAG_58_E = 656 , - WIFI_N_EXT_SPARE_REUSE_TAG_60_E = 658 , - WIFI_N_EXT_SPARE_REUSE_TAG_62_E = 660 , - WIFI_N_EXT_SPARE_REUSE_TAG_64_E = 662 , - WIFI_N_EXT_SPARE_REUSE_TAG_66_E = 664 , - WIFI_N_EXT_SPARE_REUSE_TAG_68_E = 666 , - WIFI_N_EXT_SPARE_REUSE_TAG_70_E = 668 , - WIFI_N_EXT_SPARE_REUSE_TAG_72_E = 670 , - WIFI_N_EXT_SPARE_REUSE_TAG_74_E = 672 , - WIFI_N_EXT_SPARE_REUSE_TAG_76_E = 674 , - WIFI_N_EXT_SPARE_REUSE_TAG_78_E = 676 , - WIFI_N_EXT_SPARE_REUSE_TAG_80_E = 678 , - WIFI_N_EXT_SPARE_REUSE_TAG_82_E = 680 , - WIFI_N_EXT_SPARE_REUSE_TAG_84_E = 682 , - WIFI_N_EXT_SPARE_REUSE_TAG_86_E = 684 , - WIFI_N_EXT_SPARE_REUSE_TAG_88_E = 686 , - WIFI_N_EXT_SPARE_REUSE_TAG_90_E = 688 , - WIFI_N_EXT_SPARE_REUSE_TAG_92_E = 690 , - WIFI_N_EXT_SPARE_REUSE_TAG_94_E = 692 , - WIFI_N_EXT_SPARE_REUSE_TAG_96_E = 694 , - WIFI_N_EXT_SPARE_REUSE_TAG_98_E = 696 , - WIFI_N_EXT_SPARE_REUSE_TAG_100_E = 698 , - WIFI_N_EXT_SPARE_REUSE_TAG_102_E = 700 , - WIFI_N_EXT_SPARE_REUSE_TAG_104_E = 702 , - WIFI_N_EXT_SPARE_REUSE_TAG_106_E = 704 , - WIFI_N_EXT_SPARE_REUSE_TAG_108_E = 706 , - WIFI_N_EXT_SPARE_REUSE_TAG_110_E = 708 , - WIFI_N_EXT_SPARE_REUSE_TAG_112_E = 710 , - WIFI_N_EXT_SPARE_REUSE_TAG_114_E = 712 , - WIFI_N_EXT_SPARE_REUSE_TAG_116_E = 714 , - WIFI_N_EXT_SPARE_REUSE_TAG_118_E = 716 , - WIFI_N_EXT_SPARE_REUSE_TAG_120_E = 718 , - WIFI_N_EXT_SPARE_REUSE_TAG_122_E = 720 , - WIFI_N_EXT_SPARE_REUSE_TAG_124_E = 722 , - WIFI_N_EXT_SPARE_REUSE_TAG_126_E = 724 , - WIFI_N_EXT_SPARE_REUSE_TAG_128_E = 726 , - WIFI_N_EXT_SPARE_REUSE_TAG_130_E = 728 , - WIFI_N_EXT_SPARE_REUSE_TAG_132_E = 730 , - WIFI_N_EXT_SPARE_REUSE_TAG_134_E = 732 , - WIFI_N_EXT_SPARE_REUSE_TAG_136_E = 734 , - WIFI_N_EXT_SPARE_REUSE_TAG_138_E = 736 , - WIFI_N_EXT_SPARE_REUSE_TAG_140_E = 738 , - WIFI_N_EXT_SPARE_REUSE_TAG_142_E = 740 , - WIFI_N_EXT_SPARE_REUSE_TAG_144_E = 742 , - WIFI_N_EXT_SPARE_REUSE_TAG_146_E = 744 , - WIFI_N_EXT_SPARE_REUSE_TAG_148_E = 746 , - WIFI_N_EXT_SPARE_REUSE_TAG_150_E = 748 , - WIFI_N_EXT_SPARE_REUSE_TAG_152_E = 750 , - WIFI_N_EXT_SPARE_REUSE_TAG_154_E = 752 , - WIFI_N_EXT_SPARE_REUSE_TAG_156_E = 754 , - WIFI_N_EXT_SPARE_REUSE_TAG_158_E = 756 , - WIFI_N_EXT_SPARE_REUSE_TAG_160_E = 758 , - WIFI_N_EXT_SPARE_REUSE_TAG_162_E = 760 , - WIFI_N_EXT_SPARE_REUSE_TAG_164_E = 762 , - WIFI_N_EXT_SPARE_REUSE_TAG_166_E = 764 , - WIFI_N_EXT_SPARE_REUSE_TAG_168_E = 766 , - WIFI_N_EXT_SPARE_REUSE_TAG_170_E = 768 , - WIFI_N_EXT_SPARE_REUSE_TAG_172_E = 770 , - WIFI_N_EXT_SPARE_REUSE_TAG_174_E = 772 , - WIFI_N_EXT_SPARE_REUSE_TAG_176_E = 774 , - WIFI_N_EXT_SPARE_REUSE_TAG_178_E = 776 , - WIFI_N_EXT_SPARE_REUSE_TAG_180_E = 778 , - WIFI_N_EXT_SPARE_REUSE_TAG_182_E = 780 , - WIFI_N_EXT_SPARE_REUSE_TAG_184_E = 782 , - WIFI_N_EXT_SPARE_REUSE_TAG_186_E = 784 , - WIFI_N_EXT_SPARE_REUSE_TAG_188_E = 786 , - WIFI_N_EXT_SPARE_REUSE_TAG_190_E = 788 , - WIFI_N_EXT_SPARE_REUSE_TAG_192_E = 790 , - WIFI_N_EXT_SPARE_REUSE_TAG_194_E = 792 , - WIFI_N_EXT_SPARE_REUSE_TAG_196_E = 794 , - WIFI_N_EXT_SPARE_REUSE_TAG_198_E = 796 , - WIFI_N_EXT_SPARE_REUSE_TAG_200_E = 798 , - WIFI_N_EXT_SPARE_REUSE_TAG_202_E = 800 , - WIFI_N_EXT_SPARE_REUSE_TAG_204_E = 802 , - WIFI_N_EXT_SPARE_REUSE_TAG_206_E = 804 , - WIFI_N_EXT_SPARE_REUSE_TAG_208_E = 806 , - WIFI_N_EXT_SPARE_REUSE_TAG_210_E = 808 , - WIFI_N_EXT_SPARE_REUSE_TAG_212_E = 810 , - WIFI_N_EXT_SPARE_REUSE_TAG_214_E = 812 , - WIFI_N_EXT_SPARE_REUSE_TAG_216_E = 814 , - WIFI_N_EXT_SPARE_REUSE_TAG_218_E = 816 , - WIFI_N_EXT_SPARE_REUSE_TAG_220_E = 818 , - WIFI_N_EXT_SPARE_REUSE_TAG_222_E = 820 , - WIFI_N_EXT_SPARE_REUSE_TAG_224_E = 822 , - WIFI_N_EXT_SPARE_REUSE_TAG_226_E = 824 , - WIFI_N_EXT_SPARE_REUSE_TAG_228_E = 826 , - WIFI_N_EXT_SPARE_REUSE_TAG_230_E = 828 , - WIFI_N_EXT_SPARE_REUSE_TAG_232_E = 830 , - WIFI_N_EXT_SPARE_REUSE_TAG_234_E = 832 , - WIFI_N_EXT_SPARE_REUSE_TAG_236_E = 834 , - WIFI_N_EXT_SPARE_REUSE_TAG_238_E = 836 , - WIFI_N_EXT_SPARE_REUSE_TAG_240_E = 838 , - WIFI_N_EXT_SPARE_REUSE_TAG_242_E = 840 , - WIFI_N_EXT_SPARE_REUSE_TAG_244_E = 842 , - WIFI_N_EXT_SPARE_REUSE_TAG_246_E = 844 , - WIFI_N_EXT_SPARE_REUSE_TAG_248_E = 846 , - WIFI_N_EXT_SPARE_REUSE_TAG_250_E = 848 , - WIFI_N_EXT_SPARE_REUSE_TAG_252_E = 850 , - WIFI_N_EXT_SPARE_REUSE_TAG_254_E = 852 , - WIFI_N_EXT_SPARE_REUSE_TAG_256_E = 854 , - WIFI_N_EXT_SPARE_REUSE_TAG_258_E = 856 , - WIFI_N_EXT_SPARE_REUSE_TAG_260_E = 858 , - WIFI_N_EXT_SPARE_REUSE_TAG_262_E = 860 , - WIFI_N_EXT_SPARE_REUSE_TAG_264_E = 862 , - WIFI_N_EXT_SPARE_REUSE_TAG_266_E = 864 , - WIFI_N_EXT_SPARE_REUSE_TAG_268_E = 866 , - WIFI_N_EXT_SPARE_REUSE_TAG_270_E = 868 , - WIFI_N_EXT_SPARE_REUSE_TAG_272_E = 870 , - WIFI_N_EXT_SPARE_REUSE_TAG_274_E = 872 , - WIFI_N_EXT_SPARE_REUSE_TAG_276_E = 874 , - WIFI_N_EXT_SPARE_REUSE_TAG_278_E = 876 , - WIFI_N_EXT_SPARE_REUSE_TAG_280_E = 878 , - WIFI_N_EXT_SPARE_REUSE_TAG_282_E = 880 , - WIFI_N_EXT_SPARE_REUSE_TAG_284_E = 882 , - WIFI_N_EXT_SPARE_REUSE_TAG_286_E = 884 , - WIFI_N_EXT_SPARE_REUSE_TAG_288_E = 886 , - WIFI_N_EXT_SPARE_REUSE_TAG_290_E = 888 , - WIFI_N_EXT_SPARE_REUSE_TAG_292_E = 890 , - WIFI_N_EXT_SPARE_REUSE_TAG_294_E = 892 , - WIFI_N_EXT_SPARE_REUSE_TAG_296_E = 894 , - WIFI_N_EXT_SPARE_REUSE_TAG_298_E = 896 , - WIFI_N_EXT_SPARE_REUSE_TAG_300_E = 898 , - WIFI_N_EXT_SPARE_REUSE_TAG_302_E = 900 , - WIFI_N_EXT_SPARE_REUSE_TAG_304_E = 902 , - WIFI_N_EXT_SPARE_REUSE_TAG_306_E = 904 , - WIFI_N_EXT_SPARE_REUSE_TAG_308_E = 906 , - WIFI_N_EXT_SPARE_REUSE_TAG_310_E = 908 , - WIFI_N_EXT_SPARE_REUSE_TAG_312_E = 910 , - WIFI_N_EXT_SPARE_REUSE_TAG_314_E = 912 , - WIFI_N_EXT_SPARE_REUSE_TAG_316_E = 914 , - WIFI_N_EXT_SPARE_REUSE_TAG_318_E = 916 , - WIFI_N_EXT_SPARE_REUSE_TAG_320_E = 918 , - WIFI_N_EXT_SPARE_REUSE_TAG_322_E = 920 , - WIFI_N_EXT_SPARE_REUSE_TAG_324_E = 922 , - WIFI_N_EXT_SPARE_REUSE_TAG_326_E = 924 , - WIFI_N_EXT_SPARE_REUSE_TAG_328_E = 926 , - WIFI_N_EXT_SPARE_REUSE_TAG_330_E = 928 , - WIFI_N_EXT_SPARE_REUSE_TAG_332_E = 930 , - WIFI_N_EXT_SPARE_REUSE_TAG_334_E = 932 , - WIFI_N_EXT_SPARE_REUSE_TAG_336_E = 934 , - WIFI_N_EXT_SPARE_REUSE_TAG_338_E = 936 , - WIFI_N_EXT_SPARE_REUSE_TAG_340_E = 938 , - WIFI_N_EXT_SPARE_REUSE_TAG_342_E = 940 , - WIFI_N_EXT_SPARE_REUSE_TAG_344_E = 942 , - WIFI_N_EXT_SPARE_REUSE_TAG_346_E = 944 , - WIFI_N_EXT_SPARE_REUSE_TAG_348_E = 946 , - WIFI_N_EXT_SPARE_REUSE_TAG_350_E = 948 , - WIFI_N_EXT_SPARE_REUSE_TAG_352_E = 950 , - WIFI_N_EXT_SPARE_REUSE_TAG_354_E = 952 , - WIFI_N_EXT_SPARE_REUSE_TAG_356_E = 954 , - WIFI_N_EXT_SPARE_REUSE_TAG_358_E = 956 , - WIFI_N_EXT_SPARE_REUSE_TAG_360_E = 958 , - WIFI_N_EXT_SPARE_REUSE_TAG_362_E = 960 , - WIFI_N_EXT_SPARE_REUSE_TAG_364_E = 962 , - WIFI_N_EXT_SPARE_REUSE_TAG_366_E = 964 , - WIFI_N_EXT_SPARE_REUSE_TAG_368_E = 966 , - WIFI_N_EXT_SPARE_REUSE_TAG_370_E = 968 , - WIFI_N_EXT_SPARE_REUSE_TAG_372_E = 970 , - WIFI_N_EXT_SPARE_REUSE_TAG_374_E = 972 , - WIFI_N_EXT_SPARE_REUSE_TAG_376_E = 974 , - WIFI_N_EXT_SPARE_REUSE_TAG_378_E = 976 , - WIFI_N_EXT_SPARE_REUSE_TAG_380_E = 978 , - WIFI_N_EXT_SPARE_REUSE_TAG_382_E = 980 , - WIFI_N_EXT_SPARE_REUSE_TAG_384_E = 982 , - WIFI_N_EXT_SPARE_REUSE_TAG_386_E = 984 , - WIFI_N_EXT_SPARE_REUSE_TAG_388_E = 986 , - WIFI_N_EXT_SPARE_REUSE_TAG_390_E = 988 , - WIFI_N_EXT_SPARE_REUSE_TAG_392_E = 990 , - WIFI_N_EXT_SPARE_REUSE_TAG_394_E = 992 , - WIFI_N_EXT_SPARE_REUSE_TAG_396_E = 994 , - WIFI_N_EXT_SPARE_REUSE_TAG_398_E = 996 , - WIFI_N_EXT_SPARE_REUSE_TAG_400_E = 998 , - WIFI_N_EXT_SPARE_REUSE_TAG_402_E = 1000 , - WIFI_N_EXT_SPARE_REUSE_TAG_404_E = 1002 , - WIFI_N_EXT_SPARE_REUSE_TAG_406_E = 1004 , - WIFI_N_EXT_SPARE_REUSE_TAG_408_E = 1006 , - WIFI_N_EXT_SPARE_REUSE_TAG_410_E = 1008 , - WIFI_N_EXT_SPARE_REUSE_TAG_412_E = 1010 , - WIFI_N_EXT_SPARE_REUSE_TAG_414_E = 1012 , - WIFI_N_EXT_SPARE_REUSE_TAG_416_E = 1014 , - WIFI_N_EXT_SPARE_REUSE_TAG_418_E = 1016 , - WIFI_N_EXT_SPARE_REUSE_TAG_420_E = 1018 , - WIFI_N_EXT_SPARE_REUSE_TAG_422_E = 1020 -} non_ext_tlv_tag_def__e; - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tqm2sw_completion_ring.h b/drivers/staging/fw-api/hw/fig/v2/tqm2sw_completion_ring.h deleted file mode 100644 index f67deea1f6a1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tqm2sw_completion_ring.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TQM2SW_COMPLETION_RING_H_ -#define _TQM2SW_COMPLETION_RING_H_ - -#include "tx_rate_stats_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_TQM2SW_COMPLETION_RING 8 - -struct tqm2sw_completion_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_desc_virt_addr_or_addr_info; - uint32_t release_source_module : 3, - cache_id : 1, - reserved_2a : 2, - buffer_or_desc_type : 3, - return_buffer_manager : 4, - tqm_release_reason : 4, - rbm_override_valid : 1, - sw_buffer_cookie_11_0 : 12, - cookie_conversion_status : 1, - tqm_completion_error : 1; - uint32_t tqm_status_number : 24, - transmit_count : 7, - sw_release_details_valid : 1; - uint32_t ack_frame_rssi : 8, - first_msdu : 1, - last_msdu : 1, - fw_tx_notify_frame : 3, - buffer_timestamp : 19; - struct tx_rate_stats_info tx_rate_stats; - uint32_t sw_peer_id : 16, - tid : 4, - sw_buffer_cookie_19_12 : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_desc_virt_addr_or_addr_info; - uint32_t tqm_completion_error : 1, - cookie_conversion_status : 1, - sw_buffer_cookie_11_0 : 12, - rbm_override_valid : 1, - tqm_release_reason : 4, - return_buffer_manager : 4, - buffer_or_desc_type : 3, - reserved_2a : 2, - cache_id : 1, - release_source_module : 3; - uint32_t sw_release_details_valid : 1, - transmit_count : 7, - tqm_status_number : 24; - uint32_t buffer_timestamp : 19, - fw_tx_notify_frame : 3, - last_msdu : 1, - first_msdu : 1, - ack_frame_rssi : 8; - struct tx_rate_stats_info tx_rate_stats; - uint32_t looping_count : 4, - sw_buffer_cookie_19_12 : 8, - tid : 4, - sw_peer_id : 16; -#endif -}; - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define TQM2SW_COMPLETION_RING_CACHE_ID_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_CACHE_ID_LSB 3 -#define TQM2SW_COMPLETION_RING_CACHE_ID_MSB 3 -#define TQM2SW_COMPLETION_RING_CACHE_ID_MASK 0x00000008 - -#define TQM2SW_COMPLETION_RING_RESERVED_2A_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_LSB 4 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_MSB 5 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_MASK 0x00000030 - -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_LSB 6 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MSB 8 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_LSB 9 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MSB 12 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MASK 0x00001e00 - -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_LSB 13 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MSB 16 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MASK 0x0001e000 - -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_LSB 17 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MSB 17 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MASK 0x00020000 - -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_LSB 18 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MSB 29 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 - -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_LSB 30 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MSB 30 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MASK 0x40000000 - -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_LSB 31 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MSB 31 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MASK 0x80000000 - -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_LSB 0 -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MSB 23 -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MASK 0x00ffffff - -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_LSB 24 -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MSB 30 -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MASK 0x7f000000 - -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_LSB 31 -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MSB 31 -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 - -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_LSB 0 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MSB 7 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MASK 0x000000ff - -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_LSB 8 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MSB 8 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MASK 0x00000100 - -#define TQM2SW_COMPLETION_RING_LAST_MSDU_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_LSB 9 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_MSB 9 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_MASK 0x00000200 - -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_LSB 10 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MSB 12 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 - -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_LSB 13 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MSB 31 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MASK 0xffffe000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_LSB 1 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MSB 3 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MSB 16 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0001f000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_LSB 17 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MSB 19 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MASK 0x000e0000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 20 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 20 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00100000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_LSB 21 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MSB 24 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MASK 0x01e00000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_LSB 25 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MSB 28 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MASK 0x1e000000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff - -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_LSB 0 -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MSB 15 -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MASK 0x0000ffff - -#define TQM2SW_COMPLETION_RING_TID_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_TID_LSB 16 -#define TQM2SW_COMPLETION_RING_TID_MSB 19 -#define TQM2SW_COMPLETION_RING_TID_MASK 0x000f0000 - -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_LSB 20 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MSB 27 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 - -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_LSB 28 -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MSB 31 -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_cbf_info.h b/drivers/staging/fw-api/hw/fig/v2/tx_cbf_info.h deleted file mode 100644 index fed064ce95a8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_cbf_info.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_CBF_INFO_H_ -#define _TX_CBF_INFO_H_ - -#define NUM_OF_DWORDS_TX_CBF_INFO 16 - -#define NUM_OF_QWORDS_TX_CBF_INFO 8 - -struct tx_cbf_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sw_peer_id : 16, - pre_cbf_duration : 16; - uint32_t brpoll_info_valid : 1, - trigger_brpoll_info_valid : 1, - npda_info_11ac_valid : 1, - npda_info_11ax_valid : 1, - dot11ax_su_extended : 1, - bandwidth : 3, - brpoll_info : 8, - cbf_response_table_base_index : 8, - peer_index : 3, - pkt_type : 4, - txop_duration_all_ones : 1; - uint32_t trigger_brpoll_common_info_15_0 : 16, - trigger_brpoll_common_info_31_16 : 16; - uint32_t trigger_brpoll_user_info_15_0 : 16, - trigger_brpoll_user_info_31_16 : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t addr3_47_32 : 16, - sta_partial_aid : 11, - __reserved_g_0035 : 1, - reserved_8a : 3, - cbf_resp_pwr_mgmt : 1; - uint32_t group_id : 6, - rssi_comb : 8, - reserved_9a : 2, - vht_ndpa_sta_info : 16; - uint32_t he_eht_sta_info_15_0 : 16, - he_eht_sta_info_31_16 : 16; - uint32_t dot11ax_received_format_indication : 1, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_bss_color_id : 6, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_cp_size : 2, - dot11ax_received_ltf_size : 2, - dot11ax_received_coding : 1, - dot11ax_received_dcm : 1, - dot11ax_received_doppler_indication : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_dl_ul_flag : 1, - reserved_11a : 8; - uint32_t sw_response_frame_length : 16, - sw_response_tlv_from_crypto : 1, - wait_sifs_config_valid : 1, - wait_sifs : 2, - __reserved_g_0022 : 1, - secure : 1, - tb___reserved_g_0022_response_required : 2, - emlsr_main_tlv_if : 1, - reserved_12a : 1, - u_sig_puncture_pattern_encoding : 6; - uint32_t dot11be_puncture_bitmap : 16, - dot11be_response : 1, - punctured_response : 1, - npda_info_11be_valid : 1, - eht_duplicate_mode : 2, - reserved_13a : 11; - uint32_t eht_sta_info_39_32 : 8, - unassociated___reserved_g_0022_peer : 1, - reserved_14a : 23; - uint32_t tlv64_padding : 32; -#else - uint32_t pre_cbf_duration : 16, - sw_peer_id : 16; - uint32_t txop_duration_all_ones : 1, - pkt_type : 4, - peer_index : 3, - cbf_response_table_base_index : 8, - brpoll_info : 8, - bandwidth : 3, - dot11ax_su_extended : 1, - npda_info_11ax_valid : 1, - npda_info_11ac_valid : 1, - trigger_brpoll_info_valid : 1, - brpoll_info_valid : 1; - uint32_t trigger_brpoll_common_info_31_16 : 16, - trigger_brpoll_common_info_15_0 : 16; - uint32_t trigger_brpoll_user_info_31_16 : 16, - trigger_brpoll_user_info_15_0 : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t cbf_resp_pwr_mgmt : 1, - reserved_8a : 3, - __reserved_g_0035 : 1, - sta_partial_aid : 11, - addr3_47_32 : 16; - uint32_t vht_ndpa_sta_info : 16, - reserved_9a : 2, - rssi_comb : 8, - group_id : 6; - uint32_t he_eht_sta_info_31_16 : 16, - he_eht_sta_info_15_0 : 16; - uint32_t reserved_11a : 8, - dot11ax_dl_ul_flag : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_received_doppler_indication : 1, - dot11ax_received_dcm : 1, - dot11ax_received_coding : 1, - dot11ax_received_ltf_size : 2, - dot11ax_received_cp_size : 2, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_bss_color_id : 6, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_format_indication : 1; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_12a : 1, - emlsr_main_tlv_if : 1, - tb___reserved_g_0022_response_required : 2, - secure : 1, - __reserved_g_0022 : 1, - wait_sifs : 2, - wait_sifs_config_valid : 1, - sw_response_tlv_from_crypto : 1, - sw_response_frame_length : 16; - uint32_t reserved_13a : 11, - eht_duplicate_mode : 2, - npda_info_11be_valid : 1, - punctured_response : 1, - dot11be_response : 1, - dot11be_puncture_bitmap : 16; - uint32_t reserved_14a : 23, - unassociated___reserved_g_0022_peer : 1, - eht_sta_info_39_32 : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_SW_PEER_ID_LSB 0 -#define TX_CBF_INFO_SW_PEER_ID_MSB 15 -#define TX_CBF_INFO_SW_PEER_ID_MASK 0x000000000000ffff - -#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 -#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 -#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 32 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 32 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x0000000100000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 33 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 33 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x0000000200000000 - -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 34 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 34 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x0000000400000000 - -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 35 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 35 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x0000000800000000 - -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 36 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 36 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000001000000000 - -#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BANDWIDTH_LSB 37 -#define TX_CBF_INFO_BANDWIDTH_MSB 39 -#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e000000000 - -#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BRPOLL_INFO_LSB 40 -#define TX_CBF_INFO_BRPOLL_INFO_MSB 47 -#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff0000000000 - -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 48 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 55 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff000000000000 - -#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PEER_INDEX_LSB 56 -#define TX_CBF_INFO_PEER_INDEX_MSB 58 -#define TX_CBF_INFO_PEER_INDEX_MASK 0x0700000000000000 - -#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PKT_TYPE_LSB 59 -#define TX_CBF_INFO_PKT_TYPE_MSB 62 -#define TX_CBF_INFO_PKT_TYPE_MASK 0x7800000000000000 - -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 63 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 63 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x000000000000ffff - -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 32 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 47 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 48 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 63 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff000000000000 - -#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR1_31_0_LSB 0 -#define TX_CBF_INFO_ADDR1_31_0_MSB 31 -#define TX_CBF_INFO_ADDR1_31_0_MASK 0x00000000ffffffff - -#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR1_47_32_LSB 32 -#define TX_CBF_INFO_ADDR1_47_32_MSB 47 -#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR2_15_0_LSB 48 -#define TX_CBF_INFO_ADDR2_15_0_MSB 63 -#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff000000000000 - -#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x0000000000000018 -#define TX_CBF_INFO_ADDR2_47_16_LSB 0 -#define TX_CBF_INFO_ADDR2_47_16_MSB 31 -#define TX_CBF_INFO_ADDR2_47_16_MASK 0x00000000ffffffff - -#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000000000000018 -#define TX_CBF_INFO_ADDR3_31_0_LSB 32 -#define TX_CBF_INFO_ADDR3_31_0_MSB 63 -#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff00000000 - -#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_ADDR3_47_32_LSB 0 -#define TX_CBF_INFO_ADDR3_47_32_MSB 15 -#define TX_CBF_INFO_ADDR3_47_32_MASK 0x000000000000ffff - -#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 -#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 -#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x0000000007ff0000 - -#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RESERVED_8A_LSB 28 -#define TX_CBF_INFO_RESERVED_8A_MSB 30 -#define TX_CBF_INFO_RESERVED_8A_MASK 0x0000000070000000 - -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x0000000080000000 - -#define TX_CBF_INFO_GROUP_ID_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_GROUP_ID_LSB 32 -#define TX_CBF_INFO_GROUP_ID_MSB 37 -#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f00000000 - -#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RSSI_COMB_LSB 38 -#define TX_CBF_INFO_RSSI_COMB_MSB 45 -#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc000000000 - -#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RESERVED_9A_LSB 46 -#define TX_CBF_INFO_RESERVED_9A_MSB 47 -#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c00000000000 - -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 48 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 63 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff000000000000 - -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x000000000000ffff - -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 48 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 48 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 49 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 49 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 - -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 55 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 55 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0080000000000000 - -#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_RESERVED_11A_LSB 56 -#define TX_CBF_INFO_RESERVED_11A_MSB 63 -#define TX_CBF_INFO_RESERVED_11A_MASK 0xff00000000000000 - -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x000000000000ffff - -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000000010000 - -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000000020000 - -#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_WAIT_SIFS_LSB 18 -#define TX_CBF_INFO_WAIT_SIFS_MSB 19 -#define TX_CBF_INFO_WAIT_SIFS_MASK 0x00000000000c0000 - -#define TX_CBF_INFO_SECURE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SECURE_LSB 21 -#define TX_CBF_INFO_SECURE_MSB 21 -#define TX_CBF_INFO_SECURE_MASK 0x0000000000200000 - -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB 24 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB 24 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK 0x0000000001000000 - -#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_RESERVED_12A_LSB 25 -#define TX_CBF_INFO_RESERVED_12A_MSB 25 -#define TX_CBF_INFO_RESERVED_12A_MASK 0x0000000002000000 - -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 48 -#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 48 -#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 - -#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 49 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 49 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 - -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 50 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 50 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x0004000000000000 - -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 51 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 52 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x0018000000000000 - -#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_RESERVED_13A_LSB 53 -#define TX_CBF_INFO_RESERVED_13A_MSB 63 -#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe0000000000000 - -#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x00000000000000ff - -#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_RESERVED_14A_LSB 9 -#define TX_CBF_INFO_RESERVED_14A_MSB 31 -#define TX_CBF_INFO_RESERVED_14A_MASK 0x00000000fffffe00 - -#define TX_CBF_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_TLV64_PADDING_LSB 32 -#define TX_CBF_INFO_TLV64_PADDING_MSB 63 -#define TX_CBF_INFO_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_setup.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_setup.h deleted file mode 100644 index 143ee87f4a5f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_setup.h +++ /dev/null @@ -1,585 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_SETUP_H_ -#define _TX_FES_SETUP_H_ - -#define NUM_OF_DWORDS_TX_FES_SETUP 10 - -#define NUM_OF_QWORDS_TX_FES_SETUP 5 - -struct tx_fes_setup { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t schedule_id : 32; - uint32_t fes_in_11ax_trigger_response_config : 1, - bo_based_tid_aggregation_limit : 4, - __reserved_g_0022 : 1, - expect_i2r_lmr : 1, - transmit_start_reason : 3, - use_alt_power_sr : 1, - static_2_pwr_mode_status : 1, - obss_srg_opport_transmit_status : 1, - srp_based_transmit_status : 1, - obss_pd_based_transmit_status : 1, - puncture_from_all_allowed_modes : 1, - schedule_cmd_ring_id : 5, - fes_control_mode : 2, - number_of_users : 6, - mu_type : 1, - ofdma_triggered_response : 1, - response_to_response_cmd : 1; - uint32_t schedule_try : 4, - reserved_2a : 1, - subband_antenna_selection_en : 1, - txbf : 1, - allow_txop_exceed_in_1st_pkt : 1, - ignore_bw_available : 1, - ignore_tbtt : 1, - static_bandwidth : 3, - set_txop_duration_all_ones : 1, - transmission_contains_mu_rts : 1, - bw_restricted_frames_embedded : 1, - ast_index : 16; - uint32_t cv_id : 8, - trigger_resp_txpdu_ppdu_boundary : 2, - rxpcu_setup_complete_present : 1, - rbo_must_have_data_user_limit : 4, - mu_ndp : 1, - bf_type : 2, - cbf_nc_index_mask : 1, - cbf_nc_index : 3, - cbf_nr_index_mask : 1, - cbf_nr_index : 3, - secure___reserved_g_0022_ista : 1, - ndpa : 1, - wait_sifs : 2, - cbf_feedback_type_mask : 1, - cbf_feedback_type : 1; - uint32_t cbf_sounding_token : 6, - cbf_sounding_token_mask : 1, - cbf_bw_mask : 1, - cbf_bw : 3, - use_static_bw : 1, - coex_nack_count : 5, - sch_tx_burst_ongoing : 1, - gen_tqm_update_mpdu_count_tlv : 1, - rts_tx_over___reserved_g_0016 : 1, - ndp_frame : 3, - optimal_bw_retry_count : 4, - fes_continuation_ratio_threshold : 5; - uint32_t transmit_cca_bitmap : 32; - uint32_t tb___reserved_g_0022 : 1, - __reserved_g_0022_trigger_subtype : 4, - min_cts2self_count : 4, - max_cts2self_count : 4, - wifi_radar_enable : 1, - reserved_6a : 1, - wait_for_chksum_done : 1, - txrx_self_test_enable : 1, - rtt_self_cal_enable : 1, - secure___reserved_g_0022_rsta : 1, - hip_edca_prot_enable : 1, - hip_edca_prot_required : 1, - hip_edca_mini_contention_gap : 8, - last_command_in_burst : 1, - retain_peer_blackout_details : 1, - enable_hw_qos_null : 1; - uint32_t monitor_override_sta_31_0 : 32; - uint32_t monitor_override_sta_36_32 : 5, - enable_qos_null_switch_for_eosp : 1, - __reserved_g_0035 : 1, - secure___reserved_g_0035_smr : 1, - __reserved_g_0035_type : 2, - __reserved_g_0035_trigger_subtype : 4, - cfp_protected_fes : 1, - dot11ax_trigger_frame_embedded : 1, - multiple_triggers_indication : 1, - cmf_uif_length : 4, - npca_switching_cts2self_duration : 8, - reserved_8a : 3; - uint32_t fw2sw_info : 32; -#else - uint32_t schedule_id : 32; - uint32_t response_to_response_cmd : 1, - ofdma_triggered_response : 1, - mu_type : 1, - number_of_users : 6, - fes_control_mode : 2, - schedule_cmd_ring_id : 5, - puncture_from_all_allowed_modes : 1, - obss_pd_based_transmit_status : 1, - srp_based_transmit_status : 1, - obss_srg_opport_transmit_status : 1, - static_2_pwr_mode_status : 1, - use_alt_power_sr : 1, - transmit_start_reason : 3, - expect_i2r_lmr : 1, - __reserved_g_0022 : 1, - bo_based_tid_aggregation_limit : 4, - fes_in_11ax_trigger_response_config : 1; - uint32_t ast_index : 16, - bw_restricted_frames_embedded : 1, - transmission_contains_mu_rts : 1, - set_txop_duration_all_ones : 1, - static_bandwidth : 3, - ignore_tbtt : 1, - ignore_bw_available : 1, - allow_txop_exceed_in_1st_pkt : 1, - txbf : 1, - subband_antenna_selection_en : 1, - reserved_2a : 1, - schedule_try : 4; - uint32_t cbf_feedback_type : 1, - cbf_feedback_type_mask : 1, - wait_sifs : 2, - ndpa : 1, - secure___reserved_g_0022_ista : 1, - cbf_nr_index : 3, - cbf_nr_index_mask : 1, - cbf_nc_index : 3, - cbf_nc_index_mask : 1, - bf_type : 2, - mu_ndp : 1, - rbo_must_have_data_user_limit : 4, - rxpcu_setup_complete_present : 1, - trigger_resp_txpdu_ppdu_boundary : 2, - cv_id : 8; - uint32_t fes_continuation_ratio_threshold : 5, - optimal_bw_retry_count : 4, - ndp_frame : 3, - rts_tx_over___reserved_g_0016 : 1, - gen_tqm_update_mpdu_count_tlv : 1, - sch_tx_burst_ongoing : 1, - coex_nack_count : 5, - use_static_bw : 1, - cbf_bw : 3, - cbf_bw_mask : 1, - cbf_sounding_token_mask : 1, - cbf_sounding_token : 6; - uint32_t transmit_cca_bitmap : 32; - uint32_t enable_hw_qos_null : 1, - retain_peer_blackout_details : 1, - last_command_in_burst : 1, - hip_edca_mini_contention_gap : 8, - hip_edca_prot_required : 1, - hip_edca_prot_enable : 1, - secure___reserved_g_0022_rsta : 1, - rtt_self_cal_enable : 1, - txrx_self_test_enable : 1, - wait_for_chksum_done : 1, - reserved_6a : 1, - wifi_radar_enable : 1, - max_cts2self_count : 4, - min_cts2self_count : 4, - __reserved_g_0022_trigger_subtype : 4, - tb___reserved_g_0022 : 1; - uint32_t monitor_override_sta_31_0 : 32; - uint32_t reserved_8a : 3, - npca_switching_cts2self_duration : 8, - cmf_uif_length : 4, - multiple_triggers_indication : 1, - dot11ax_trigger_frame_embedded : 1, - cfp_protected_fes : 1, - __reserved_g_0035_trigger_subtype : 4, - __reserved_g_0035_type : 2, - secure___reserved_g_0035_smr : 1, - __reserved_g_0035 : 1, - enable_qos_null_switch_for_eosp : 1, - monitor_override_sta_36_32 : 5; - uint32_t fw2sw_info : 32; -#endif -}; - -#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 -#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 -#define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff - -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 - -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 - -#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 -#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 -#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 - -#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 -#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 -#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 - -#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 -#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 -#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 - -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 - -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 - -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 - -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 - -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 - -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 - -#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 -#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 -#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 - -#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 -#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 -#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 - -#define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_MU_TYPE_LSB 61 -#define TX_FES_SETUP_MU_TYPE_MSB 61 -#define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 - -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 - -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 - -#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 -#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 -#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f - -#define TX_FES_SETUP_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RESERVED_2A_LSB 4 -#define TX_FES_SETUP_RESERVED_2A_MSB 4 -#define TX_FES_SETUP_RESERVED_2A_MASK 0x0000000000000010 - -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_LSB 5 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MSB 5 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MASK 0x0000000000000020 - -#define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TXBF_LSB 6 -#define TX_FES_SETUP_TXBF_MSB 6 -#define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 - -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 - -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 - -#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 -#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 -#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 - -#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 -#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 -#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 - -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 - -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 - -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 - -#define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_AST_INDEX_LSB 16 -#define TX_FES_SETUP_AST_INDEX_MSB 31 -#define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 - -#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CV_ID_LSB 32 -#define TX_FES_SETUP_CV_ID_MSB 39 -#define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 - -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 - -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 - -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 - -#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_MU_NDP_LSB 47 -#define TX_FES_SETUP_MU_NDP_MSB 47 -#define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 - -#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_BF_TYPE_LSB 48 -#define TX_FES_SETUP_BF_TYPE_MSB 49 -#define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 - -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 - -#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 -#define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 - -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 - -#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 -#define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 - -#define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_NDPA_LSB 59 -#define TX_FES_SETUP_NDPA_MSB 59 -#define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 - -#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_WAIT_SIFS_LSB 60 -#define TX_FES_SETUP_WAIT_SIFS_MSB 61 -#define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 - -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 - -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 - -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f - -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 - -#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 -#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 -#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 - -#define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_BW_LSB 8 -#define TX_FES_SETUP_CBF_BW_MSB 10 -#define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 - -#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 -#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 -#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 - -#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 -#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 -#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 - -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 - -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 - -#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_NDP_FRAME_LSB 20 -#define TX_FES_SETUP_NDP_FRAME_MSB 22 -#define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000700000 - -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 - -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 - -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 - -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 - -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 - -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 - -#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RESERVED_6A_LSB 14 -#define TX_FES_SETUP_RESERVED_6A_MSB 14 -#define TX_FES_SETUP_RESERVED_6A_MASK 0x0000000000004000 - -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB 15 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB 15 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK 0x0000000000008000 - -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_LSB 16 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MSB 16 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MASK 0x0000000000010000 - -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_LSB 17 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MSB 17 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MASK 0x0000000000020000 - -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_LSB 19 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MSB 19 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MASK 0x0000000000080000 - -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_LSB 20 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MSB 20 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MASK 0x0000000000100000 - -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_LSB 21 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MSB 28 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MASK 0x000000001fe00000 - -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_LSB 29 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MSB 29 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MASK 0x0000000020000000 - -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_LSB 30 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MSB 30 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MASK 0x0000000040000000 - -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB 31 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB 31 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK 0x0000000080000000 - -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 - -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f - -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB 5 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB 5 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK 0x0000000000000020 - -#define TX_FES_SETUP_CFP_PROTECTED_FES_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_CFP_PROTECTED_FES_LSB 14 -#define TX_FES_SETUP_CFP_PROTECTED_FES_MSB 14 -#define TX_FES_SETUP_CFP_PROTECTED_FES_MASK 0x0000000000004000 - -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 15 -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 15 -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000000000008000 - -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_LSB 16 -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_MSB 16 -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_MASK 0x0000000000010000 - -#define TX_FES_SETUP_CMF_UIF_LENGTH_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_CMF_UIF_LENGTH_LSB 17 -#define TX_FES_SETUP_CMF_UIF_LENGTH_MSB 20 -#define TX_FES_SETUP_CMF_UIF_LENGTH_MASK 0x00000000001e0000 - -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_LSB 21 -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_MSB 28 -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_MASK 0x000000001fe00000 - -#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_RESERVED_8A_LSB 29 -#define TX_FES_SETUP_RESERVED_8A_MSB 31 -#define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000e0000000 - -#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_FW2SW_INFO_LSB 32 -#define TX_FES_SETUP_FW2SW_INFO_MSB 63 -#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_1k_ba.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_1k_ba.h deleted file mode 100644 index 4409dc03ac03..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_1k_ba.h +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_1K_BA_H_ -#define _TX_FES_STATUS_1K_BA_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 - -#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 - -struct tx_fes_status_1k_ba { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ack_ba_status_type : 1, - ba_type : 1, - ba_tid : 4, - unexpected_ack_or_ba : 1, - response_timeout : 1, - ack_frame_rssi : 8, - ssn : 12, - reserved_0b : 4; - uint32_t sw_peer_id : 16, - reserved_1a : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; - uint32_t ba_bitmap_287_256 : 32; - uint32_t ba_bitmap_319_288 : 32; - uint32_t ba_bitmap_351_320 : 32; - uint32_t ba_bitmap_383_352 : 32; - uint32_t ba_bitmap_415_384 : 32; - uint32_t ba_bitmap_447_416 : 32; - uint32_t ba_bitmap_479_448 : 32; - uint32_t ba_bitmap_511_480 : 32; - uint32_t ba_bitmap_543_512 : 32; - uint32_t ba_bitmap_575_544 : 32; - uint32_t ba_bitmap_607_576 : 32; - uint32_t ba_bitmap_639_608 : 32; - uint32_t ba_bitmap_671_640 : 32; - uint32_t ba_bitmap_703_672 : 32; - uint32_t ba_bitmap_735_704 : 32; - uint32_t ba_bitmap_767_736 : 32; - uint32_t ba_bitmap_799_768 : 32; - uint32_t ba_bitmap_831_800 : 32; - uint32_t ba_bitmap_863_832 : 32; - uint32_t ba_bitmap_895_864 : 32; - uint32_t ba_bitmap_927_896 : 32; - uint32_t ba_bitmap_959_928 : 32; - uint32_t ba_bitmap_991_960 : 32; - uint32_t ba_bitmap_1023_992 : 32; -#else - uint32_t reserved_0b : 4, - ssn : 12, - ack_frame_rssi : 8, - response_timeout : 1, - unexpected_ack_or_ba : 1, - ba_tid : 4, - ba_type : 1, - ack_ba_status_type : 1; - uint32_t reserved_1a : 16, - sw_peer_id : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; - uint32_t ba_bitmap_287_256 : 32; - uint32_t ba_bitmap_319_288 : 32; - uint32_t ba_bitmap_351_320 : 32; - uint32_t ba_bitmap_383_352 : 32; - uint32_t ba_bitmap_415_384 : 32; - uint32_t ba_bitmap_447_416 : 32; - uint32_t ba_bitmap_479_448 : 32; - uint32_t ba_bitmap_511_480 : 32; - uint32_t ba_bitmap_543_512 : 32; - uint32_t ba_bitmap_575_544 : 32; - uint32_t ba_bitmap_607_576 : 32; - uint32_t ba_bitmap_639_608 : 32; - uint32_t ba_bitmap_671_640 : 32; - uint32_t ba_bitmap_703_672 : 32; - uint32_t ba_bitmap_735_704 : 32; - uint32_t ba_bitmap_767_736 : 32; - uint32_t ba_bitmap_799_768 : 32; - uint32_t ba_bitmap_831_800 : 32; - uint32_t ba_bitmap_863_832 : 32; - uint32_t ba_bitmap_895_864 : 32; - uint32_t ba_bitmap_927_896 : 32; - uint32_t ba_bitmap_959_928 : 32; - uint32_t ba_bitmap_991_960 : 32; - uint32_t ba_bitmap_1023_992 : 32; -#endif -}; - -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 - -#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 -#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 -#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 - -#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 -#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 -#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c - -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 - -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 - -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_SSN_LSB 16 -#define TX_FES_STATUS_1K_BA_SSN_MSB 27 -#define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 - -#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 - -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_ack_or_ba.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_ack_or_ba.h deleted file mode 100644 index 678c639141ba..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_ack_or_ba.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ -#define _TX_FES_STATUS_ACK_OR_BA_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 - -#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5 - -struct tx_fes_status_ack_or_ba { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ack_ba_status_type : 1, - ba_type : 1, - ba_tid : 4, - unexpected_ack_or_ba : 1, - response_timeout : 1, - ack_frame_rssi : 8, - ssn : 12, - reserved_0b : 4; - uint32_t sw_peer_id : 16, - reserved_1a : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; -#else - uint32_t reserved_0b : 4, - ssn : 12, - ack_frame_rssi : 8, - response_timeout : 1, - unexpected_ack_or_ba : 1, - ba_tid : 4, - ba_type : 1, - ack_ba_status_type : 1; - uint32_t reserved_1a : 16, - sw_peer_id : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; -#endif -}; - -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 - -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x0000000000000002 - -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x000000000000003c - -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 - -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 - -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 -#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 -#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x000000000fff0000 - -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0x00000000f0000000 - -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 47 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 48 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff000000000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_end.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_end.h deleted file mode 100644 index 450b9227f8b2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_end.h +++ /dev/null @@ -1,602 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_END_H_ -#define _TX_FES_STATUS_END_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_END 12 - -#define NUM_OF_QWORDS_TX_FES_STATUS_END 6 - -struct tx_fes_status_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0052 : 1, - __reserved_g_0053 : 1, - __reserved_g_0035 : 1, - __reserved_g_0036 : 1, - __reserved_g_0032 : 1, - __reserved_g_0033 : 1, - __reserved_g_0072 : 1, - __reserved_g_0073 : 1, - __reserved_g_0065 : 1, - __reserved_g_0066 : 1, - __reserved_g_0062 : 1, - __reserved_g_0063 : 1, - global_data_underflow_warning : 1, - global_fes_transmit_result : 4, - cbf_bw_received_valid : 1, - cbf_bw_received : 3, - actual_received_ack_type : 4, - sta_response_count : 6, - more_data_received : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t reserved_after_struct16 : 4, - brp_info_valid : 1, - qos_null_switch_done_for_eosp : 1, - reserved_1a : 5, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - fes_in_11ax_trigger_response_config : 1, - null_delim_inserted_before_mpdus : 1, - only_null_delim_sent : 1; - uint32_t terminate___reserved_g_0022_sequence : 1, - unsolicited_erts_tx : 1, - ects_response_type : 2, - eba_response_type : 2, - response_type : 5, - r2r_end_status_to_follow : 1, - service_cbw : 3, - __reserved_g_0039 : 1, - __reserved_g_0040 : 1, - __reserved_g_0017 : 1, - __reserved_g_0018 : 1, - __reserved_g_0030 : 1, - __reserved_g_0031 : 1, - reserved_2c : 11; - uint32_t beamform_masked_user_bitmap_15_0 : 16, - beamform_masked_user_bitmap_31_16 : 16; - uint32_t cbf_segment_request_mask : 8, - cbf_segment_sent_mask : 8, - highest_achieved_data_null_ratio : 5, - use_alt_power_sr : 1, - static_2_pwr_mode_status : 1, - obss_srg_opport_transmit_status : 1, - srp_based_transmit_status : 1, - obss_pd_based_transmit_status : 1, - beamform_masked_user_bitmap_36_32 : 5, - pdg_mpdu_ready : 1; - uint32_t pdg_mpdu_count : 16, - pdg_est_mpdu_tx_count : 16; - uint32_t pdg_overview_length : 24, - txop_duration : 7, - pdg_dropped_mpdu_warning : 1; - uint32_t packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - packet_extension : 3, - fec_type : 1, - stbc : 1, - num_data_symbols : 16, - ru_size : 4, - reserved_17a : 4; - uint32_t num_ltf_symbols : 3, - ltf_size : 2, - cp_setting : 2, - reserved_18a : 5, - dcm : 1, - ldpc_extra_symbol : 1, - force_extra_symbol : 1, - reserved_18b : 1, - tx_pwr_shared : 8, - tx_pwr_unshared : 8; - uint32_t __reserved_g_0022_active_user_map : 16, - __reserved_g_0022_sent_dummy_tx : 1, - __reserved_g_0022_ftm_frame_sent : 1, - __reserved_g_0067 : 1, - __reserved_g_0068 : 1, - __reserved_g_0037 : 1, - __reserved_g_0038 : 1, - __reserved_g_0069 : 1, - __reserved_g_0070 : 1, - cv_corr_status : 8; - uint32_t current_tx_duration : 16, - reserved_21a : 4, - hw_qos_null_bitmap : 8, - hw_qos_null_setup_missing : 1, - interference : 1, - reserved_21b : 2; - uint32_t reserved_22b : 4, - __reserved_g_0027 : 1, - __reserved_g_0028 : 1, - __reserved_g_0049 : 1, - __reserved_g_0050 : 1, - __reserved_g_0025 : 1, - __reserved_g_0026 : 1, - __reserved_g_0047 : 1, - __reserved_g_0048 : 1, - __reserved_g_0023 : 1, - __reserved_g_0024 : 1, - __reserved_g_0045 : 1, - __reserved_g_0046 : 1, - __reserved_g_0021 : 1, - __reserved_g_0022 : 1, - __reserved_g_0043 : 1, - __reserved_g_0044 : 1, - __reserved_g_0019 : 1, - __reserved_g_0020 : 1, - __reserved_g_0041 : 1, - __reserved_g_0042 : 1, - coex_signaling_status : 8; -#else - uint32_t more_data_received : 1, - sta_response_count : 6, - actual_received_ack_type : 4, - cbf_bw_received : 3, - cbf_bw_received_valid : 1, - global_fes_transmit_result : 4, - global_data_underflow_warning : 1, - __reserved_g_0063 : 1, - __reserved_g_0062 : 1, - __reserved_g_0066 : 1, - __reserved_g_0065 : 1, - __reserved_g_0073 : 1, - __reserved_g_0072 : 1, - __reserved_g_0033 : 1, - __reserved_g_0032 : 1, - __reserved_g_0036 : 1, - __reserved_g_0035 : 1, - __reserved_g_0053 : 1, - __reserved_g_0052 : 1; - uint32_t only_null_delim_sent : 1, - null_delim_inserted_before_mpdus : 1, - fes_in_11ax_trigger_response_config : 1, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - reserved_1a : 5, - qos_null_switch_done_for_eosp : 1, - brp_info_valid : 1, - reserved_after_struct16 : 4; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t reserved_2c : 11, - __reserved_g_0031 : 1, - __reserved_g_0030 : 1, - __reserved_g_0018 : 1, - __reserved_g_0017 : 1, - __reserved_g_0040 : 1, - __reserved_g_0039 : 1, - service_cbw : 3, - r2r_end_status_to_follow : 1, - response_type : 5, - eba_response_type : 2, - ects_response_type : 2, - unsolicited_erts_tx : 1, - terminate___reserved_g_0022_sequence : 1; - uint32_t beamform_masked_user_bitmap_31_16 : 16, - beamform_masked_user_bitmap_15_0 : 16; - uint32_t pdg_mpdu_ready : 1, - beamform_masked_user_bitmap_36_32 : 5, - obss_pd_based_transmit_status : 1, - srp_based_transmit_status : 1, - obss_srg_opport_transmit_status : 1, - static_2_pwr_mode_status : 1, - use_alt_power_sr : 1, - highest_achieved_data_null_ratio : 5, - cbf_segment_sent_mask : 8, - cbf_segment_request_mask : 8; - uint32_t pdg_est_mpdu_tx_count : 16, - pdg_mpdu_count : 16; - uint32_t pdg_dropped_mpdu_warning : 1, - txop_duration : 7, - pdg_overview_length : 24; - uint32_t reserved_17a : 4, - ru_size : 4, - num_data_symbols : 16, - stbc : 1, - fec_type : 1, - packet_extension : 3, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2; - uint32_t tx_pwr_unshared : 8, - tx_pwr_shared : 8, - reserved_18b : 1, - force_extra_symbol : 1, - ldpc_extra_symbol : 1, - dcm : 1, - reserved_18a : 5, - cp_setting : 2, - ltf_size : 2, - num_ltf_symbols : 3; - uint32_t cv_corr_status : 8, - __reserved_g_0070 : 1, - __reserved_g_0069 : 1, - __reserved_g_0038 : 1, - __reserved_g_0037 : 1, - __reserved_g_0068 : 1, - __reserved_g_0067 : 1, - __reserved_g_0022_ftm_frame_sent : 1, - __reserved_g_0022_sent_dummy_tx : 1, - __reserved_g_0022_active_user_map : 16; - uint32_t reserved_21b : 2, - interference : 1, - hw_qos_null_setup_missing : 1, - hw_qos_null_bitmap : 8, - reserved_21a : 4, - current_tx_duration : 16; - uint32_t coex_signaling_status : 8, - __reserved_g_0042 : 1, - __reserved_g_0041 : 1, - __reserved_g_0020 : 1, - __reserved_g_0019 : 1, - __reserved_g_0044 : 1, - __reserved_g_0043 : 1, - __reserved_g_0022 : 1, - __reserved_g_0021 : 1, - __reserved_g_0046 : 1, - __reserved_g_0045 : 1, - __reserved_g_0024 : 1, - __reserved_g_0023 : 1, - __reserved_g_0048 : 1, - __reserved_g_0047 : 1, - __reserved_g_0026 : 1, - __reserved_g_0025 : 1, - __reserved_g_0050 : 1, - __reserved_g_0049 : 1, - __reserved_g_0028 : 1, - __reserved_g_0027 : 1, - reserved_22b : 4; -#endif -}; - -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 - -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 - -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 - -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 - -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 - -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 - -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB 31 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB 31 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 - -#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 -#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 -#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 - -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB 53 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB 53 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK 0x0020000000000000 - -#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_RESERVED_1A_LSB 54 -#define TX_FES_STATUS_END_RESERVED_1A_MSB 58 -#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07c0000000000000 - -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 - -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 - -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 - -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 - -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_LSB 1 -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_MSB 1 -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_MASK 0x0000000000000002 - -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_LSB 2 -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_MSB 3 -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_MASK 0x000000000000000c - -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_LSB 4 -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_MSB 5 -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_MASK 0x0000000000000030 - -#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 6 -#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 10 -#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x00000000000007c0 - -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 11 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 11 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000000800 - -#define TX_FES_STATUS_END_SERVICE_CBW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_SERVICE_CBW_LSB 12 -#define TX_FES_STATUS_END_SERVICE_CBW_MSB 14 -#define TX_FES_STATUS_END_SERVICE_CBW_MASK 0x0000000000007000 - -#define TX_FES_STATUS_END_RESERVED_2C_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESERVED_2C_LSB 21 -#define TX_FES_STATUS_END_RESERVED_2C_MSB 31 -#define TX_FES_STATUS_END_RESERVED_2C_MASK 0x00000000ffe00000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 32 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 47 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 48 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 63 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0xffff000000000000 - -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 0 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 7 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x00000000000000ff - -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 8 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 15 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 16 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 20 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x00000000001f0000 - -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 21 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 21 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0000000000200000 - -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 22 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 22 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0000000000400000 - -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 23 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 23 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000000000800000 - -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 24 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 24 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000000001000000 - -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 25 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 25 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000000002000000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 26 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 30 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x000000007c000000 - -#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 31 -#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 31 -#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 32 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 47 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 48 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 63 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0xffff000000000000 - -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 0 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 23 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x0000000000ffffff - -#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_TXOP_DURATION_LSB 24 -#define TX_FES_STATUS_END_TXOP_DURATION_MSB 30 -#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x000000007f000000 - -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 31 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 31 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 32 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 33 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000300000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 34 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 34 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000400000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 35 -#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 37 -#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000003800000000 - -#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_FEC_TYPE_LSB 38 -#define TX_FES_STATUS_END_FEC_TYPE_MSB 38 -#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000004000000000 - -#define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_STBC_LSB 39 -#define TX_FES_STATUS_END_STBC_MSB 39 -#define TX_FES_STATUS_END_STBC_MASK 0x0000008000000000 - -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 40 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 55 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x00ffff0000000000 - -#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_RU_SIZE_LSB 56 -#define TX_FES_STATUS_END_RU_SIZE_MSB 59 -#define TX_FES_STATUS_END_RU_SIZE_MASK 0x0f00000000000000 - -#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_RESERVED_17A_LSB 60 -#define TX_FES_STATUS_END_RESERVED_17A_MSB 63 -#define TX_FES_STATUS_END_RESERVED_17A_MASK 0xf000000000000000 - -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 0 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 2 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000000000007 - -#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_LTF_SIZE_LSB 3 -#define TX_FES_STATUS_END_LTF_SIZE_MSB 4 -#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000000000000018 - -#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_CP_SETTING_LSB 5 -#define TX_FES_STATUS_END_CP_SETTING_MSB 6 -#define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000000000000060 - -#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_RESERVED_18A_LSB 7 -#define TX_FES_STATUS_END_RESERVED_18A_MSB 11 -#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x0000000000000f80 - -#define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_DCM_LSB 12 -#define TX_FES_STATUS_END_DCM_MSB 12 -#define TX_FES_STATUS_END_DCM_MASK 0x0000000000001000 - -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 13 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 13 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000000000002000 - -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 14 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 14 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000000000004000 - -#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_RESERVED_18B_LSB 15 -#define TX_FES_STATUS_END_RESERVED_18B_MSB 15 -#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000000000008000 - -#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 16 -#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 23 -#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x0000000000ff0000 - -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 24 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 31 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0x00000000ff000000 - -#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 56 -#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 63 -#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0xff00000000000000 - -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 0 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 15 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x000000000000ffff - -#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_21A_LSB 16 -#define TX_FES_STATUS_END_RESERVED_21A_MSB 19 -#define TX_FES_STATUS_END_RESERVED_21A_MASK 0x00000000000f0000 - -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB 20 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB 27 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK 0x000000000ff00000 - -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB 28 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB 28 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK 0x0000000010000000 - -#define TX_FES_STATUS_END_INTERFERENCE_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_INTERFERENCE_LSB 29 -#define TX_FES_STATUS_END_INTERFERENCE_MSB 29 -#define TX_FES_STATUS_END_INTERFERENCE_MASK 0x0000000020000000 - -#define TX_FES_STATUS_END_RESERVED_21B_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_21B_LSB 30 -#define TX_FES_STATUS_END_RESERVED_21B_MSB 31 -#define TX_FES_STATUS_END_RESERVED_21B_MASK 0x00000000c0000000 - -#define TX_FES_STATUS_END_RESERVED_22B_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_22B_LSB 32 -#define TX_FES_STATUS_END_RESERVED_22B_MSB 35 -#define TX_FES_STATUS_END_RESERVED_22B_MASK 0x0000000f00000000 - -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_LSB 56 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MSB 63 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_prot.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_prot.h deleted file mode 100644 index 702cc1add940..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_prot.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_PROT_H_ -#define _TX_FES_STATUS_PROT_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 4 - -#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 2 - -struct tx_fes_status_prot { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t success : 1, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - reserved_0 : 19, - pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5; - uint32_t frame_type : 2, - frame_subtype : 4, - rx_pwr_mgmt : 1, - status : 1, - duration_field : 16, - reserved_1a : 2, - agc_cbw : 3, - service_cbw : 3; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t reserved_2a : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4, - reserved_0 : 19, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - success : 1; - uint32_t service_cbw : 3, - agc_cbw : 3, - reserved_1a : 2, - duration_field : 16, - status : 1, - rx_pwr_mgmt : 1, - frame_subtype : 4, - frame_type : 2; - uint32_t reserved_2a : 16; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 -#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 -#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 - -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 - -#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 -#define TX_FES_STATUS_PROT_RESERVED_0_MSB 21 -#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000003ffff8 - -#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 22 -#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 25 -#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000003c00000 - -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 26 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 26 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000004000000 - -#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RATE_MCS_LSB 27 -#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 -#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f8000000 - -#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 -#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 -#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 - -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 - -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 - -#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_STATUS_LSB 39 -#define TX_FES_STATUS_PROT_STATUS_MSB 39 -#define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 - -#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 -#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 -#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 - -#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 -#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 -#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 - -#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 -#define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 -#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 - -#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 -#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 -#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00000000000000ff - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x0000000000003f00 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x000000000000c000 - -#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_RESERVED_2A_LSB 16 -#define TX_FES_STATUS_PROT_RESERVED_2A_MSB 31 -#define TX_FES_STATUS_PROT_RESERVED_2A_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_PROT_TLV64_PADDING_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_PROT_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_PROT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start.h deleted file mode 100644 index bc8e06ec59fb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_H_ -#define _TX_FES_STATUS_START_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START 2 - -struct tx_fes_status_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t schedule_id : 32; - uint32_t reserved_1a : 8, - transmit_start_reason : 3, - disabled_user_bitmap_36_32 : 5, - schedule_cmd_ring_id : 5, - fes_control_mode : 2, - schedule_try : 4, - medium_prot_type : 3, - reserved_1b : 2; - uint32_t optimal_bw_try_count : 4, - number_of_users : 7, - coex_nack_count : 5, - cca_ed0 : 16; - uint32_t disabled_user_bitmap_31_0 : 32; -#else - uint32_t schedule_id : 32; - uint32_t reserved_1b : 2, - medium_prot_type : 3, - schedule_try : 4, - fes_control_mode : 2, - schedule_cmd_ring_id : 5, - disabled_user_bitmap_36_32 : 5, - transmit_start_reason : 3, - reserved_1a : 8; - uint32_t cca_ed0 : 16, - coex_nack_count : 5, - number_of_users : 7, - optimal_bw_try_count : 4; - uint32_t disabled_user_bitmap_31_0 : 32; -#endif -}; - -#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 -#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 -#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_RESERVED_1A_LSB 32 -#define TX_FES_STATUS_START_RESERVED_1A_MSB 39 -#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 40 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 42 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x0000070000000000 - -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 43 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 47 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f80000000000 - -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 48 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 52 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 - -#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 53 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 54 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x0060000000000000 - -#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 55 -#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 58 -#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x0780000000000000 - -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 59 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 61 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x3800000000000000 - -#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_RESERVED_1B_LSB 62 -#define TX_FES_STATUS_START_RESERVED_1B_MSB 63 -#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc000000000000000 - -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x000000000000000f - -#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x00000000000007f0 - -#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x000000000000f800 - -#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_CCA_ED0_LSB 16 -#define TX_FES_STATUS_START_CCA_ED0_MSB 31 -#define TX_FES_STATUS_START_CCA_ED0_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 32 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 63 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_ppdu.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_ppdu.h deleted file mode 100644 index a87b3b0a0ccc..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_ppdu.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_PPDU_H_ -#define _TX_FES_STATUS_START_PPDU_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 3 - -struct tx_fes_status_start_ppdu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ppdu_timestamp_lower_32 : 32; - uint32_t ppdu_timestamp_upper_32 : 32; - uint32_t subband_mask : 16, - ndp_frame : 3, - reserved_2b : 1, - coex_based_tx_bw : 3, - coex_based_ant_mask : 8, - reserved_2c : 1; - uint32_t coex_based_tx_pwr_shared_ant : 8, - coex_based_tx_pwr_ant : 8, - concurrent_bt_tx : 1, - concurrent_wlan_tx : 1, - concurrent_wan_tx : 1, - concurrent_wan_rx : 1, - coex_pwr_reduction_bt : 1, - coex_pwr_reduction_wlan : 1, - coex_pwr_reduction_wan : 1, - coex_result_alt_based : 1, - request_packet_bw : 3, - response_type : 5; - uint32_t concurrent_rx_activity_tracker1 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - coex_pwr_reduction_wan_ratid1 : 1, - reserved_4a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t ppdu_timestamp_lower_32 : 32; - uint32_t ppdu_timestamp_upper_32 : 32; - uint32_t reserved_2c : 1, - coex_based_ant_mask : 8, - coex_based_tx_bw : 3, - reserved_2b : 1, - ndp_frame : 3, - subband_mask : 16; - uint32_t response_type : 5, - request_packet_bw : 3, - coex_result_alt_based : 1, - coex_pwr_reduction_wan : 1, - coex_pwr_reduction_wlan : 1, - coex_pwr_reduction_bt : 1, - concurrent_wan_rx : 1, - concurrent_wan_tx : 1, - concurrent_wlan_tx : 1, - concurrent_bt_tx : 1, - coex_based_tx_pwr_ant : 8, - coex_based_tx_pwr_shared_ant : 8; - uint32_t reserved_4a : 18, - coex_pwr_reduction_wan_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker1 : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 32 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 63 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x000000000000ffff - -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 18 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x0000000000070000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 19 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x0000000000080000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x0000000000700000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x0000000080000000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 32 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 39 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 40 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 47 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff0000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 48 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 48 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x0001000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 49 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 49 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 50 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 50 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x0004000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 51 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 51 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x0008000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 52 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 52 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 53 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 53 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 54 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 54 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 55 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 55 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x0080000000000000 - -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 56 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 58 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x0700000000000000 - -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 59 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 63 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf800000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB 0 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB 0 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK 0x0000000000000001 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB 1 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB 1 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK 0x0000000000000002 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB 2 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB 2 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK 0x0000000000000004 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB 3 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB 3 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK 0x0000000000000008 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB 4 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB 4 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK 0x0000000000000010 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB 5 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB 5 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK 0x0000000000000020 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB 6 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB 6 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK 0x0000000000000040 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB 7 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB 7 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK 0x0000000000000080 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB 8 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB 8 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK 0x0000000000000100 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB 9 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB 9 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK 0x0000000000000200 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB 10 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB 10 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK 0x0000000000000400 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_LSB 11 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MSB 11 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MASK 0x0000000000000800 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_LSB 12 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MSB 12 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MASK 0x0000000000001000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_LSB 13 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MSB 13 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MASK 0x0000000000002000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_LSB 14 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MASK 0x00000000ffffc000 - -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_prot.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_prot.h deleted file mode 100644 index aca9ac5eb28b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_prot.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_PROT_H_ -#define _TX_FES_STATUS_START_PROT_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 3 - -struct tx_fes_status_start_prot { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t prot_timestamp_lower_32 : 32; - uint32_t prot_timestamp_upper_32 : 32; - uint32_t subband_mask : 16, - reserved_2b : 4, - prot_coex_based_tx_bw : 3, - prot_coex_based_ant_mask : 8, - prot_coex_result_alt_based : 1; - uint32_t prot_coex_tx_pwr_shared_ant : 8, - prot_coex_tx_pwr_ant : 8, - prot_concurrent_bt_tx : 1, - prot_concurrent_wlan_tx : 1, - prot_concurrent_wan_tx : 1, - prot_concurrent_wan_rx : 1, - prot_coex_pwr_reduction_bt : 1, - prot_coex_pwr_reduction_wlan : 1, - prot_coex_pwr_reduction_wan : 1, - prot_request_packet_bw : 3, - response_type : 5, - reserved_3a : 1; - uint32_t concurrent_rx_activity_tracker1 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - coex_pwr_reduction_wan_ratid1 : 1, - reserved_4a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t prot_timestamp_lower_32 : 32; - uint32_t prot_timestamp_upper_32 : 32; - uint32_t prot_coex_result_alt_based : 1, - prot_coex_based_ant_mask : 8, - prot_coex_based_tx_bw : 3, - reserved_2b : 4, - subband_mask : 16; - uint32_t reserved_3a : 1, - response_type : 5, - prot_request_packet_bw : 3, - prot_coex_pwr_reduction_wan : 1, - prot_coex_pwr_reduction_wlan : 1, - prot_coex_pwr_reduction_bt : 1, - prot_concurrent_wan_rx : 1, - prot_concurrent_wan_tx : 1, - prot_concurrent_wlan_tx : 1, - prot_concurrent_bt_tx : 1, - prot_coex_tx_pwr_ant : 8, - prot_coex_tx_pwr_shared_ant : 8; - uint32_t reserved_4a : 18, - coex_pwr_reduction_wan_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker1 : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 32 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 63 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x000000000000ffff - -#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x00000000000f0000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x0000000000700000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x0000000080000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 32 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 39 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 40 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 47 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff0000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 48 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 48 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x0001000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 49 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 49 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 50 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 50 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x0004000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 51 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 51 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x0008000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 52 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 52 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 53 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 53 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 54 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 54 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 55 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 57 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x0380000000000000 - -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 58 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 62 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c00000000000000 - -#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 63 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 63 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x8000000000000000 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB 0 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB 0 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK 0x0000000000000001 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB 1 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB 1 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK 0x0000000000000002 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB 2 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB 2 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK 0x0000000000000004 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB 3 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB 3 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK 0x0000000000000008 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB 4 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB 4 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK 0x0000000000000010 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB 5 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB 5 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK 0x0000000000000020 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB 6 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB 6 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK 0x0000000000000040 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB 7 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB 7 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK 0x0000000000000080 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB 8 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB 8 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK 0x0000000000000100 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB 9 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB 9 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK 0x0000000000000200 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB 10 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB 10 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK 0x0000000000000400 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_LSB 11 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MSB 11 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MASK 0x0000000000000800 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_LSB 12 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MSB 12 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MASK 0x0000000000001000 - -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_LSB 13 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MSB 13 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MASK 0x0000000000002000 - -#define TX_FES_STATUS_START_PROT_RESERVED_4A_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_LSB 14 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_MSB 31 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_MASK 0x00000000ffffc000 - -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_ppdu.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_ppdu.h deleted file mode 100644 index dad9a040ff46..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_ppdu.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_USER_PPDU_H_ -#define _TX_FES_STATUS_USER_PPDU_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 - -struct tx_fes_status_user_ppdu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t underflow_mpdu_count : 9, - data_underflow_warning : 2, - bw_drop_underflow_warning : 1, - qc_eosp_setting : 1, - mpdu_tx_count : 11, - user_blocked : 1, - pre_trig_response_delim_count : 7; - uint32_t underflow_byte_count : 16, - coex_abort_mpdu_count_valid : 1, - coex_abort_mpdu_count : 9, - transmitted_tid : 4, - txdma_dropped_mpdu_warning : 1, - cv_corr_user_valid_in_phy : 1; - uint32_t duration : 16, - num_eof_delim_added : 16; - uint32_t psdu_octet : 24, - qos_buf_state : 8; - uint32_t num_null_delim_added : 22, - fc_more_data_setting : 1, - fc_pwr_mgt_setting : 1, - nss : 3, - mcs : 5; - uint32_t ht_control : 32; -#else - uint32_t pre_trig_response_delim_count : 7, - user_blocked : 1, - mpdu_tx_count : 11, - qc_eosp_setting : 1, - bw_drop_underflow_warning : 1, - data_underflow_warning : 2, - underflow_mpdu_count : 9; - uint32_t cv_corr_user_valid_in_phy : 1, - txdma_dropped_mpdu_warning : 1, - transmitted_tid : 4, - coex_abort_mpdu_count : 9, - coex_abort_mpdu_count_valid : 1, - underflow_byte_count : 16; - uint32_t num_eof_delim_added : 16, - duration : 16; - uint32_t qos_buf_state : 8, - psdu_octet : 24; - uint32_t mcs : 5, - nss : 3, - fc_pwr_mgt_setting : 1, - fc_more_data_setting : 1, - num_null_delim_added : 22; - uint32_t ht_control : 32; -#endif -}; - -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff - -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 - -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 - -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 - -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 13 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ffe000 - -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 - -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 - -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 - -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 - -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 - -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 - -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 63 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 63 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x8000000000000000 - -#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 -#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 -#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff - -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 - -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 - -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff - -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 22 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 22 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000400000 - -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 23 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 23 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000800000 - -#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_NSS_LSB 24 -#define TX_FES_STATUS_USER_PPDU_NSS_MSB 26 -#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x0000000007000000 - -#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_MCS_LSB 27 -#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 -#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f8000000 - -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_response.h deleted file mode 100644 index dea7df35887f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_response.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ -#define _TX_FES_STATUS_USER_RESPONSE_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 - -#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1 - -struct tx_fes_status_user_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t fes_transmit_result : 4, - reserved_0 : 23, - overwritten_blackout_window_bitmap : 4, - mic_overwritten : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t pre_padding_fcs_overwritten : 1, - reserved_after_struct16 : 15; -#else - uint32_t mic_overwritten : 1, - overwritten_blackout_window_bitmap : 4, - reserved_0 : 23, - fes_transmit_result : 4; - uint32_t reserved_after_struct16 : 15, - pre_padding_fcs_overwritten : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; -#endif -}; - -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x000000000000000f - -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 26 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0x0000000007fffff0 - -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_LSB 27 -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MSB 30 -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MASK 0x0000000078000000 - -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_LSB 31 -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_MSB 31 -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_MASK 0x0000000080000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_LSB 48 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MSB 48 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MASK 0x0001000000000000 - -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 49 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 63 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xfffe000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_flush_req.h b/drivers/staging/fw-api/hw/fig/v2/tx_flush_req.h deleted file mode 100644 index af502ec619eb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_flush_req.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FLUSH_REQ_H_ -#define _TX_FLUSH_REQ_H_ - -#define NUM_OF_DWORDS_TX_FLUSH_REQ 2 - -#define NUM_OF_QWORDS_TX_FLUSH_REQ 1 - -struct tx_flush_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t flush_req_reason : 8, - phytx_abort_reason : 8, - flush_req_user_number_or_link_id : 6, - mlo_abort_reason : 5, - reserved_0a : 5; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 5, - mlo_abort_reason : 5, - flush_req_user_number_or_link_id : 6, - phytx_abort_reason : 8, - flush_req_reason : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff - -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00 - -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000 - -#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000 - -#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 -#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 -#define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000 - -#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_TLV64_PADDING_LSB 32 -#define TX_FLUSH_REQ_TLV64_PADDING_MSB 63 -#define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_mpdu_start.h b/drivers/staging/fw-api/hw/fig/v2/tx_mpdu_start.h deleted file mode 100644 index 1a0c370d2963..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_mpdu_start.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MPDU_START_H_ -#define _TX_MPDU_START_H_ - -#define NUM_OF_DWORDS_TX_MPDU_START 10 - -#define NUM_OF_QWORDS_TX_MPDU_START 5 - -struct tx_mpdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mpdu_length : 14, - frame_not_from_tqm : 1, - vht_control_present : 1, - mpdu_header_length : 8, - retry_count : 7, - wds : 1; - uint32_t pn_31_0 : 32; - uint32_t pn_47_32 : 16, - mpdu_sequence_number : 12, - raw_already_encrypted : 1, - frame_type : 2, - txdma_dropped_mpdu_warning : 1; - uint32_t iv_byte_0 : 8, - iv_byte_1 : 8, - iv_byte_2 : 8, - iv_byte_3 : 8; - uint32_t iv_byte_4 : 8, - iv_byte_5 : 8, - iv_byte_6 : 8, - iv_byte_7 : 8; - uint32_t iv_byte_8 : 8, - iv_byte_9 : 8, - iv_byte_10 : 8, - iv_byte_11 : 8; - uint32_t iv_byte_12 : 8, - iv_byte_13 : 8, - iv_byte_14 : 8, - iv_byte_15 : 8; - uint32_t iv_byte_16 : 8, - iv_byte_17 : 8, - iv_len : 5, - icv_len : 5, - vht_control_offset : 6; - uint32_t mpdu_type : 1, - transmit_bw_restriction : 1, - allowed_transmit_bw : 4, - tx_notify_frame : 3, - frame_subtype : 4, - reserved_8a : 19; - uint32_t tlv64_padding : 32; -#else - uint32_t wds : 1, - retry_count : 7, - mpdu_header_length : 8, - vht_control_present : 1, - frame_not_from_tqm : 1, - mpdu_length : 14; - uint32_t pn_31_0 : 32; - uint32_t txdma_dropped_mpdu_warning : 1, - frame_type : 2, - raw_already_encrypted : 1, - mpdu_sequence_number : 12, - pn_47_32 : 16; - uint32_t iv_byte_3 : 8, - iv_byte_2 : 8, - iv_byte_1 : 8, - iv_byte_0 : 8; - uint32_t iv_byte_7 : 8, - iv_byte_6 : 8, - iv_byte_5 : 8, - iv_byte_4 : 8; - uint32_t iv_byte_11 : 8, - iv_byte_10 : 8, - iv_byte_9 : 8, - iv_byte_8 : 8; - uint32_t iv_byte_15 : 8, - iv_byte_14 : 8, - iv_byte_13 : 8, - iv_byte_12 : 8; - uint32_t vht_control_offset : 6, - icv_len : 5, - iv_len : 5, - iv_byte_17 : 8, - iv_byte_16 : 8; - uint32_t reserved_8a : 19, - frame_subtype : 4, - tx_notify_frame : 3, - allowed_transmit_bw : 4, - transmit_bw_restriction : 1, - mpdu_type : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 -#define TX_MPDU_START_MPDU_LENGTH_LSB 0 -#define TX_MPDU_START_MPDU_LENGTH_MSB 13 -#define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff - -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 - -#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 - -#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 -#define TX_MPDU_START_RETRY_COUNT_LSB 24 -#define TX_MPDU_START_RETRY_COUNT_MSB 30 -#define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 - -#define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 -#define TX_MPDU_START_WDS_LSB 31 -#define TX_MPDU_START_WDS_MSB 31 -#define TX_MPDU_START_WDS_MASK 0x0000000080000000 - -#define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 -#define TX_MPDU_START_PN_31_0_LSB 32 -#define TX_MPDU_START_PN_31_0_MSB 63 -#define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 - -#define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 -#define TX_MPDU_START_PN_47_32_LSB 0 -#define TX_MPDU_START_PN_47_32_MSB 15 -#define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff - -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 - -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 - -#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 -#define TX_MPDU_START_FRAME_TYPE_LSB 29 -#define TX_MPDU_START_FRAME_TYPE_MSB 30 -#define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 - -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 - -#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_0_LSB 32 -#define TX_MPDU_START_IV_BYTE_0_MSB 39 -#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_1_LSB 40 -#define TX_MPDU_START_IV_BYTE_1_MSB 47 -#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_2_LSB 48 -#define TX_MPDU_START_IV_BYTE_2_MSB 55 -#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 - -#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_3_LSB 56 -#define TX_MPDU_START_IV_BYTE_3_MSB 63 -#define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 - -#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_4_LSB 0 -#define TX_MPDU_START_IV_BYTE_4_MSB 7 -#define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff - -#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_5_LSB 8 -#define TX_MPDU_START_IV_BYTE_5_MSB 15 -#define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 - -#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_6_LSB 16 -#define TX_MPDU_START_IV_BYTE_6_MSB 23 -#define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_7_LSB 24 -#define TX_MPDU_START_IV_BYTE_7_MSB 31 -#define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 - -#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_8_LSB 32 -#define TX_MPDU_START_IV_BYTE_8_MSB 39 -#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_9_LSB 40 -#define TX_MPDU_START_IV_BYTE_9_MSB 47 -#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_10_LSB 48 -#define TX_MPDU_START_IV_BYTE_10_MSB 55 -#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 - -#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_11_LSB 56 -#define TX_MPDU_START_IV_BYTE_11_MSB 63 -#define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 - -#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_12_LSB 0 -#define TX_MPDU_START_IV_BYTE_12_MSB 7 -#define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff - -#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_13_LSB 8 -#define TX_MPDU_START_IV_BYTE_13_MSB 15 -#define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 - -#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_14_LSB 16 -#define TX_MPDU_START_IV_BYTE_14_MSB 23 -#define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_15_LSB 24 -#define TX_MPDU_START_IV_BYTE_15_MSB 31 -#define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 - -#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_16_LSB 32 -#define TX_MPDU_START_IV_BYTE_16_MSB 39 -#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_17_LSB 40 -#define TX_MPDU_START_IV_BYTE_17_MSB 47 -#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_LEN_LSB 48 -#define TX_MPDU_START_IV_LEN_MSB 52 -#define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 - -#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 -#define TX_MPDU_START_ICV_LEN_LSB 53 -#define TX_MPDU_START_ICV_LEN_MSB 57 -#define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 - -#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 - -#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 -#define TX_MPDU_START_MPDU_TYPE_LSB 0 -#define TX_MPDU_START_MPDU_TYPE_MSB 0 -#define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 - -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 - -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c - -#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 -#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 -#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 - -#define TX_MPDU_START_FRAME_SUBTYPE_OFFSET 0x0000000000000020 -#define TX_MPDU_START_FRAME_SUBTYPE_LSB 9 -#define TX_MPDU_START_FRAME_SUBTYPE_MSB 12 -#define TX_MPDU_START_FRAME_SUBTYPE_MASK 0x0000000000001e00 - -#define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_MPDU_START_RESERVED_8A_LSB 13 -#define TX_MPDU_START_RESERVED_8A_MSB 31 -#define TX_MPDU_START_RESERVED_8A_MASK 0x00000000ffffe000 - -#define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TLV64_PADDING_LSB 32 -#define TX_MPDU_START_TLV64_PADDING_MSB 63 -#define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_msdu_extension.h b/drivers/staging/fw-api/hw/fig/v2/tx_msdu_extension.h deleted file mode 100644 index f8da5593497b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_msdu_extension.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MSDU_EXTENSION_H_ -#define _TX_MSDU_EXTENSION_H_ - -#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 - -struct tx_msdu_extension { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tso_enable : 1, - reserved_0a : 6, - tcp_flag : 9, - tcp_flag_mask : 9, - reserved_0b : 7; - uint32_t l2_length : 16, - ip_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t ip_identification : 16, - udp_length : 16; - uint32_t checksum_offset : 14, - partial_checksum_en : 1, - reserved_4a : 1, - payload_start_offset : 14, - reserved_4b : 2; - uint32_t payload_end_offset : 14, - reserved_5a : 2, - wds : 1, - reserved_5b : 15; - uint32_t buf0_ptr_31_0 : 32; - uint32_t buf0_ptr_39_32 : 8, - reserved_7a : 8, - buf0_len : 16; - uint32_t buf1_ptr_31_0 : 32; - uint32_t buf1_ptr_39_32 : 8, - reserved_9a : 8, - buf1_len : 16; - uint32_t buf2_ptr_31_0 : 32; - uint32_t buf2_ptr_39_32 : 8, - reserved_11a : 8, - buf2_len : 16; - uint32_t buf3_ptr_31_0 : 32; - uint32_t buf3_ptr_39_32 : 8, - reserved_13a : 8, - buf3_len : 16; - uint32_t buf4_ptr_31_0 : 32; - uint32_t buf4_ptr_39_32 : 8, - reserved_15a : 8, - buf4_len : 16; - uint32_t buf5_ptr_31_0 : 32; - uint32_t buf5_ptr_39_32 : 8, - reserved_17a : 8, - buf5_len : 16; -#else - uint32_t reserved_0b : 7, - tcp_flag_mask : 9, - tcp_flag : 9, - reserved_0a : 6, - tso_enable : 1; - uint32_t ip_length : 16, - l2_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t udp_length : 16, - ip_identification : 16; - uint32_t reserved_4b : 2, - payload_start_offset : 14, - reserved_4a : 1, - partial_checksum_en : 1, - checksum_offset : 14; - uint32_t reserved_5b : 15, - wds : 1, - reserved_5a : 2, - payload_end_offset : 14; - uint32_t buf0_ptr_31_0 : 32; - uint32_t buf0_len : 16, - reserved_7a : 8, - buf0_ptr_39_32 : 8; - uint32_t buf1_ptr_31_0 : 32; - uint32_t buf1_len : 16, - reserved_9a : 8, - buf1_ptr_39_32 : 8; - uint32_t buf2_ptr_31_0 : 32; - uint32_t buf2_len : 16, - reserved_11a : 8, - buf2_ptr_39_32 : 8; - uint32_t buf3_ptr_31_0 : 32; - uint32_t buf3_len : 16, - reserved_13a : 8, - buf3_ptr_39_32 : 8; - uint32_t buf4_ptr_31_0 : 32; - uint32_t buf4_len : 16, - reserved_15a : 8, - buf4_ptr_39_32 : 8; - uint32_t buf5_ptr_31_0 : 32; - uint32_t buf5_len : 16, - reserved_17a : 8, - buf5_ptr_39_32 : 8; -#endif -}; - -#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 -#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 -#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 - -#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 -#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 -#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e - -#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 -#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 - -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 - -#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 -#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 - -#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 -#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 -#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 -#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff - -#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 -#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 -#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 -#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff - -#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c -#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 -#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 -#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff - -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 - -#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 -#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 - -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 - -#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 -#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 - -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff - -#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 -#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 - -#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_WDS_LSB 16 -#define TX_MSDU_EXTENSION_WDS_MSB 16 -#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 - -#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 -#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 - -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_7A_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_RESERVED_7A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_7A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_7A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_msdu_start.h b/drivers/staging/fw-api/hw/fig/v2/tx_msdu_start.h deleted file mode 100644 index e62a76009f3a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_msdu_start.h +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MSDU_START_H_ -#define _TX_MSDU_START_H_ - -#define NUM_OF_DWORDS_TX_MSDU_START 8 - -#define NUM_OF_QWORDS_TX_MSDU_START 4 - -struct tx_msdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t msdu_len : 14, - first_msdu : 1, - last_msdu : 1, - encap_type : 2, - epd_en : 1, - da_sa_present : 2, - ipv4_checksum_en : 1, - udp_over_ipv4_checksum_en : 1, - udp_over_ipv6_checksum_en : 1, - tcp_over_ipv4_checksum_en : 1, - tcp_over_ipv6_checksum_en : 1, - dummy_msdu_delimitation : 1, - reserved_0a : 5; - uint32_t tso_enable : 1, - reserved_1a : 6, - tcp_flag : 9, - tcp_flag_mask : 9, - mesh_enable : 1, - reserved_1b : 6; - uint32_t l2_length : 16, - ip_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t ip_identification : 16, - checksum_offset : 13, - partial_checksum_en : 1, - reserved_4 : 2; - uint32_t payload_start_offset : 14, - reserved_5a : 2, - payload_end_offset : 14, - reserved_5b : 2; - uint32_t udp_length : 16, - reserved_6 : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 5, - dummy_msdu_delimitation : 1, - tcp_over_ipv6_checksum_en : 1, - tcp_over_ipv4_checksum_en : 1, - udp_over_ipv6_checksum_en : 1, - udp_over_ipv4_checksum_en : 1, - ipv4_checksum_en : 1, - da_sa_present : 2, - epd_en : 1, - encap_type : 2, - last_msdu : 1, - first_msdu : 1, - msdu_len : 14; - uint32_t reserved_1b : 6, - mesh_enable : 1, - tcp_flag_mask : 9, - tcp_flag : 9, - reserved_1a : 6, - tso_enable : 1; - uint32_t ip_length : 16, - l2_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t reserved_4 : 2, - partial_checksum_en : 1, - checksum_offset : 13, - ip_identification : 16; - uint32_t reserved_5b : 2, - payload_end_offset : 14, - reserved_5a : 2, - payload_start_offset : 14; - uint32_t reserved_6 : 16, - udp_length : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_MSDU_LEN_LSB 0 -#define TX_MSDU_START_MSDU_LEN_MSB 13 -#define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff - -#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000 -#define TX_MSDU_START_FIRST_MSDU_LSB 14 -#define TX_MSDU_START_FIRST_MSDU_MSB 14 -#define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000 - -#define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000 -#define TX_MSDU_START_LAST_MSDU_LSB 15 -#define TX_MSDU_START_LAST_MSDU_MSB 15 -#define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000 - -#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_ENCAP_TYPE_LSB 16 -#define TX_MSDU_START_ENCAP_TYPE_MSB 17 -#define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000 - -#define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_EPD_EN_LSB 18 -#define TX_MSDU_START_EPD_EN_MSB 18 -#define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000 - -#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000 -#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 -#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 -#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000 - -#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000 - -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000 - -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000 - -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000 - -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000 - -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000 - -#define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_0A_LSB 27 -#define TX_MSDU_START_RESERVED_0A_MSB 31 -#define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000 - -#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TSO_ENABLE_LSB 32 -#define TX_MSDU_START_TSO_ENABLE_MSB 32 -#define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000 - -#define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_1A_LSB 33 -#define TX_MSDU_START_RESERVED_1A_MSB 38 -#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000 - -#define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_FLAG_LSB 39 -#define TX_MSDU_START_TCP_FLAG_MSB 47 -#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000 - -#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_FLAG_MASK_LSB 48 -#define TX_MSDU_START_TCP_FLAG_MASK_MSB 56 -#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000 - -#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_MESH_ENABLE_LSB 57 -#define TX_MSDU_START_MESH_ENABLE_MSB 57 -#define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000 - -#define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_1B_LSB 58 -#define TX_MSDU_START_RESERVED_1B_MSB 63 -#define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000 - -#define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008 -#define TX_MSDU_START_L2_LENGTH_LSB 0 -#define TX_MSDU_START_L2_LENGTH_MSB 15 -#define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff - -#define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008 -#define TX_MSDU_START_IP_LENGTH_LSB 16 -#define TX_MSDU_START_IP_LENGTH_MSB 31 -#define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000 - -#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008 -#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32 -#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63 -#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 - -#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010 -#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 -#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 -#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff - -#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 -#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 -#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000 - -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000 - -#define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_4_LSB 30 -#define TX_MSDU_START_RESERVED_4_MSB 31 -#define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000 - -#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000 - -#define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_5A_LSB 46 -#define TX_MSDU_START_RESERVED_5A_MSB 47 -#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000 - -#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000 - -#define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_5B_LSB 62 -#define TX_MSDU_START_RESERVED_5B_MSB 63 -#define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000 - -#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018 -#define TX_MSDU_START_UDP_LENGTH_LSB 0 -#define TX_MSDU_START_UDP_LENGTH_MSB 15 -#define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff - -#define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018 -#define TX_MSDU_START_RESERVED_6_LSB 16 -#define TX_MSDU_START_RESERVED_6_MSB 31 -#define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000 - -#define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018 -#define TX_MSDU_START_TLV64_PADDING_LSB 32 -#define TX_MSDU_START_TLV64_PADDING_MSB 63 -#define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_peer_entry.h b/drivers/staging/fw-api/hw/fig/v2/tx_peer_entry.h deleted file mode 100644 index c26c7f6a3e05..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_peer_entry.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_PEER_ENTRY_H_ -#define _TX_PEER_ENTRY_H_ - -#define NUM_OF_DWORDS_TX_PEER_ENTRY 22 - -#define NUM_OF_QWORDS_TX_PEER_ENTRY 11 - -struct tx_peer_entry { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mac_addr_a_31_0 : 32; - uint32_t mac_addr_a_47_32 : 16, - mac_addr_b_15_0 : 16; - uint32_t mac_addr_b_47_16 : 32; - uint32_t use_ad_b : 1, - strip_insert_vlan_inner : 1, - strip_insert_vlan_outer : 1, - vlan_llc_mode : 1, - key_type : 4, - a_msdu_wds_ad3_ad4 : 3, - ignore_hard_filters : 1, - ignore_soft_filters : 1, - epd_output : 1, - wds : 1, - insert_or_strip : 1, - sw_filter_id : 16; - uint32_t temporal_key_31_0 : 32; - uint32_t temporal_key_63_32 : 32; - uint32_t temporal_key_95_64 : 32; - uint32_t temporal_key_127_96 : 32; - uint32_t temporal_key_159_128 : 32; - uint32_t temporal_key_191_160 : 32; - uint32_t temporal_key_223_192 : 32; - uint32_t temporal_key_255_224 : 32; - uint32_t sta_partial_aid : 11, - transmit_vif : 4, - block_this_user : 1, - mesh_amsdu_mode : 2, - use_qos_alt_mute_mask : 1, - dl_ul_direction : 1, - use_ad_c : 1, - a_msdu_11s_fromtods_10_ad3 : 2, - multi_link_addr_ad3_valid : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_ad1_trans_dis : 1, - data_fromtods_00_ad3 : 2, - mgmt_fromtods_00_ad3 : 2, - reserved_12 : 1; - uint32_t insert_vlan_outer_tci : 16, - insert_vlan_inner_tci : 16; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0008 : 16, - __reserved_g_0009 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t multi_link_addr_crypto_enable : 1, - a_msdu_fromtods_10_ad3 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_11_ad4 : 2, - reserved_17a : 9, - sw_peer_id : 16; - uint32_t mac_addr_c_31_0 : 32; - uint32_t mac_addr_c_47_32 : 16, - multi_link_addr_ad3_47_32 : 16; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t mac_addr_a_31_0 : 32; - uint32_t mac_addr_b_15_0 : 16, - mac_addr_a_47_32 : 16; - uint32_t mac_addr_b_47_16 : 32; - uint32_t sw_filter_id : 16, - insert_or_strip : 1, - wds : 1, - epd_output : 1, - ignore_soft_filters : 1, - ignore_hard_filters : 1, - a_msdu_wds_ad3_ad4 : 3, - key_type : 4, - vlan_llc_mode : 1, - strip_insert_vlan_outer : 1, - strip_insert_vlan_inner : 1, - use_ad_b : 1; - uint32_t temporal_key_31_0 : 32; - uint32_t temporal_key_63_32 : 32; - uint32_t temporal_key_95_64 : 32; - uint32_t temporal_key_127_96 : 32; - uint32_t temporal_key_159_128 : 32; - uint32_t temporal_key_191_160 : 32; - uint32_t temporal_key_223_192 : 32; - uint32_t temporal_key_255_224 : 32; - uint32_t reserved_12 : 1, - mgmt_fromtods_00_ad3 : 2, - data_fromtods_00_ad3 : 2, - multi_link_addr_ad1_trans_dis : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_ad3_valid : 1, - a_msdu_11s_fromtods_10_ad3 : 2, - use_ad_c : 1, - dl_ul_direction : 1, - use_qos_alt_mute_mask : 1, - mesh_amsdu_mode : 2, - block_this_user : 1, - transmit_vif : 4, - sta_partial_aid : 11; - uint32_t insert_vlan_inner_tci : 16, - insert_vlan_outer_tci : 16; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0009 : 16, - __reserved_g_0008 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t sw_peer_id : 16, - reserved_17a : 9, - a_msdu_fromtods_11_ad4 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_10_ad3 : 2, - multi_link_addr_crypto_enable : 1; - uint32_t mac_addr_c_31_0 : 32; - uint32_t multi_link_addr_ad3_47_32 : 16, - mac_addr_c_47_32 : 16; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_USE_AD_B_LSB 32 -#define TX_PEER_ENTRY_USE_AD_B_MSB 32 -#define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 - -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 - -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 - -#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 - -#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_KEY_TYPE_LSB 36 -#define TX_PEER_ENTRY_KEY_TYPE_MSB 39 -#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 - -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 - -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 - -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 - -#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 -#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 -#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 - -#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_WDS_LSB 46 -#define TX_PEER_ENTRY_WDS_MSB 46 -#define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 - -#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 - -#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 -#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 -#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff - -#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 -#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 -#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 - -#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 - -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 - -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 - -#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 - -#define TX_PEER_ENTRY_USE_AD_C_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_USE_AD_C_LSB 20 -#define TX_PEER_ENTRY_USE_AD_C_MSB 20 -#define TX_PEER_ENTRY_USE_AD_C_MASK 0x0000000000100000 - -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_LSB 21 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MSB 22 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MASK 0x0000000000600000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_LSB 23 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MSB 23 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MASK 0x0000000000800000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 24 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 24 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0000000001000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 25 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 25 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x0000000002000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 26 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 26 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x0000000004000000 - -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_LSB 27 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MSB 28 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MASK 0x0000000018000000 - -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_LSB 29 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MSB 30 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MASK 0x0000000060000000 - -#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_RESERVED_12_LSB 31 -#define TX_PEER_ENTRY_RESERVED_12_MSB 31 -#define TX_PEER_ENTRY_RESERVED_12_MASK 0x0000000080000000 - -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_LSB 33 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MSB 34 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MASK 0x0000000600000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_LSB 35 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MSB 36 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MASK 0x0000001800000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_LSB 37 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MSB 38 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MASK 0x0000006000000000 - -#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_RESERVED_17A_LSB 39 -#define TX_PEER_ENTRY_RESERVED_17A_MSB 47 -#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000ff8000000000 - -#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 -#define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 -#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_LSB 32 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MSB 47 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_LSB 48 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MSB 63 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_OFFSET 0x0000000000000050 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_LSB 0 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MSB 31 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TLV64_PADDING_OFFSET 0x0000000000000050 -#define TX_PEER_ENTRY_TLV64_PADDING_LSB 32 -#define TX_PEER_ENTRY_TLV64_PADDING_MSB 63 -#define TX_PEER_ENTRY_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_queue_extension.h b/drivers/staging/fw-api/hw/fig/v2/tx_queue_extension.h deleted file mode 100644 index e46bae7cff4c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_queue_extension.h +++ /dev/null @@ -1,432 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_QUEUE_EXTENSION_H_ -#define _TX_QUEUE_EXTENSION_H_ - -#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 18 - -#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 9 - -struct tx_queue_extension { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t frame_ctl : 16, - qos_ctl : 16; - uint32_t ampdu_flag : 1, - tx_notify_no_htc_override : 1, - reserved_1a : 7, - checksum_tso_disable_for_frag : 1, - key_id : 8, - qos_buf_state_overwrite : 1, - buf_state_sta_id : 1, - buf_state_source : 1, - ht_control_overwrite_enable : 1, - ht_control_overwrite_source : 4, - reserved_1b : 6; - uint32_t ul_headroom_insertion_enable : 1, - ul_headroom_offset : 5, - bqrp_insertion_enable : 1, - bqrp_offset : 5, - ul_headroom_rsvd_7_6 : 2, - bqr_rsvd_9_8 : 2, - base_pn_63_48 : 16; - uint32_t base_pn_95_64 : 32; - uint32_t base_pn_127_96 : 32; - uint32_t ht_control_default_tb_ppdu : 32; - uint32_t ht_control_default_non_tb_ppdu : 32; - uint32_t ht_control_overwrite_tb_ppdu_enable : 1, - ht_control_overwrite_non_tb_ppdu_enable : 1, - reserved_7a : 30; - uint32_t reserved_8a : 32; - uint32_t ht_control_overwrite_mask : 32; - uint32_t cas_control_info : 8, - cas_offset : 5, - cas_insertion_enable : 1, - reserved_10a : 2, - ht_control_overwrite_source_for_srp : 4, - ht_control_overwrite_source_for_bsrp : 4, - pre_padding_fcs_overwrite_enable : 1, - reserved_10b : 5, - mpdu_hdr_len_override_en : 1, - bar_ssn_overwrite_enable : 1; - uint32_t bar_ssn_offset : 12, - mpdu_hdr_len_override_val : 9, - reserved_11a : 11; - uint32_t fw2sw_info : 32; - uint32_t pre_padding_fcs_overwrite_offset : 16, - icf_blackout_info_offset : 16; - uint32_t trigger_common_info_length : 6, - cmf_overwrite_offset : 14, - reserved_15a : 12; - uint32_t hdr_ctrl_prot_key_id_byte_offset : 14, - hdr_ctrl_prot_key_id_bit_offset : 3, - ctrl_pkt_protect : 1, - mac_hdr_protect : 1, - hdr_ctrl_prot_tx_peer_idx : 11, - reserved_16a : 2; - uint32_t pad_byte_offset : 16, - pad_byte_offset_valid : 1, - txop_duration_overwrite_enable : 1, - txop_duration_offset : 14; - uint32_t tlv64_padding : 32; -#else - uint32_t qos_ctl : 16, - frame_ctl : 16; - uint32_t reserved_1b : 6, - ht_control_overwrite_source : 4, - ht_control_overwrite_enable : 1, - buf_state_source : 1, - buf_state_sta_id : 1, - qos_buf_state_overwrite : 1, - key_id : 8, - checksum_tso_disable_for_frag : 1, - reserved_1a : 7, - tx_notify_no_htc_override : 1, - ampdu_flag : 1; - uint32_t base_pn_63_48 : 16, - bqr_rsvd_9_8 : 2, - ul_headroom_rsvd_7_6 : 2, - bqrp_offset : 5, - bqrp_insertion_enable : 1, - ul_headroom_offset : 5, - ul_headroom_insertion_enable : 1; - uint32_t base_pn_95_64 : 32; - uint32_t base_pn_127_96 : 32; - uint32_t ht_control_default_tb_ppdu : 32; - uint32_t ht_control_default_non_tb_ppdu : 32; - uint32_t reserved_7a : 30, - ht_control_overwrite_non_tb_ppdu_enable : 1, - ht_control_overwrite_tb_ppdu_enable : 1; - uint32_t reserved_8a : 32; - uint32_t ht_control_overwrite_mask : 32; - uint32_t bar_ssn_overwrite_enable : 1, - mpdu_hdr_len_override_en : 1, - reserved_10b : 5, - pre_padding_fcs_overwrite_enable : 1, - ht_control_overwrite_source_for_bsrp : 4, - ht_control_overwrite_source_for_srp : 4, - reserved_10a : 2, - cas_insertion_enable : 1, - cas_offset : 5, - cas_control_info : 8; - uint32_t reserved_11a : 11, - mpdu_hdr_len_override_val : 9, - bar_ssn_offset : 12; - uint32_t fw2sw_info : 32; - uint32_t icf_blackout_info_offset : 16, - pre_padding_fcs_overwrite_offset : 16; - uint32_t reserved_15a : 12, - cmf_overwrite_offset : 14, - trigger_common_info_length : 6; - uint32_t reserved_16a : 2, - hdr_ctrl_prot_tx_peer_idx : 11, - mac_hdr_protect : 1, - ctrl_pkt_protect : 1, - hdr_ctrl_prot_key_id_bit_offset : 3, - hdr_ctrl_prot_key_id_byte_offset : 14; - uint32_t txop_duration_offset : 14, - txop_duration_overwrite_enable : 1, - pad_byte_offset_valid : 1, - pad_byte_offset : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 -#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 -#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff - -#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 -#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 -#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 - -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 - -#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 -#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 -#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 - -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 - -#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 -#define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 -#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 - -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 - -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 - -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 -#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e - -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 - -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 - -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 - -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_OFFSET 0x0000000000000010 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_LSB 0 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_MSB 31 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_MSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_MASK 0x0000000100000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_LSB 33 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_MSB 33 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_MASK 0x0000000200000000 - -#define TX_QUEUE_EXTENSION_RESERVED_7A_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_RESERVED_7A_LSB 34 -#define TX_QUEUE_EXTENSION_RESERVED_7A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_7A_MASK 0xfffffffc00000000 - -#define TX_QUEUE_EXTENSION_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_QUEUE_EXTENSION_RESERVED_8A_LSB 0 -#define TX_QUEUE_EXTENSION_RESERVED_8A_MSB 31 -#define TX_QUEUE_EXTENSION_RESERVED_8A_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff - -#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 - -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 - -#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 -#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 -#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 - -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_LSB 24 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MSB 24 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MASK 0x0000000001000000 - -#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 25 -#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 -#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003e000000 - -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 - -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 - -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 - -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 -#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 - -#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 0 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 31 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MSB 47 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MASK 0x0000ffff00000000 - -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_LSB 48 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MSB 63 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MASK 0xffff000000000000 - -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_LSB 0 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MSB 5 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MASK 0x000000000000003f - -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_LSB 6 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MSB 19 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MASK 0x00000000000fffc0 - -#define TX_QUEUE_EXTENSION_RESERVED_15A_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_RESERVED_15A_LSB 20 -#define TX_QUEUE_EXTENSION_RESERVED_15A_MSB 31 -#define TX_QUEUE_EXTENSION_RESERVED_15A_MASK 0x00000000fff00000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MSB 45 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MASK 0x00003fff00000000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_LSB 46 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MSB 48 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MASK 0x0001c00000000000 - -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_LSB 49 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MSB 49 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MASK 0x0002000000000000 - -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_LSB 50 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MSB 50 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MASK 0x0004000000000000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_LSB 51 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MSB 61 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MASK 0x3ff8000000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_16A_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_RESERVED_16A_LSB 62 -#define TX_QUEUE_EXTENSION_RESERVED_16A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_16A_MASK 0xc000000000000000 - -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_LSB 0 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MSB 15 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MASK 0x000000000000ffff - -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_LSB 16 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MSB 16 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MASK 0x0000000000010000 - -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_LSB 17 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_MSB 17 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_MASK 0x0000000000020000 - -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_LSB 18 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_MSB 31 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_MASK 0x00000000fffc0000 - -#define TX_QUEUE_EXTENSION_TLV64_PADDING_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_TLV64_PADDING_LSB 32 -#define TX_QUEUE_EXTENSION_TLV64_PADDING_MSB 63 -#define TX_QUEUE_EXTENSION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/fig/v2/tx_rate_stats_info.h deleted file mode 100644 index ce84032dd353..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_rate_stats_info.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_RATE_STATS_INFO_H_ -#define _TX_RATE_STATS_INFO_H_ - -#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 - -struct tx_rate_stats_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_rate_stats_info_valid : 1, - transmit_bw : 3, - transmit_pkt_type : 4, - transmit_stbc : 1, - transmit_ldpc : 1, - transmit_sgi : 2, - transmit_mcs : 5, - unequal_modulation_info : 3, - ofdma_transmission : 1, - reserved_0a : 4, - tones_in_ru : 4, - transmit_nss : 3; - uint32_t ppdu_transmission_tsf : 32; -#else - uint32_t transmit_nss : 3, - tones_in_ru : 4, - reserved_0a : 4, - ofdma_transmission : 1, - unequal_modulation_info : 3, - transmit_mcs : 5, - transmit_sgi : 2, - transmit_ldpc : 1, - transmit_stbc : 1, - transmit_pkt_type : 4, - transmit_bw : 3, - tx_rate_stats_info_valid : 1; - uint32_t ppdu_transmission_tsf : 32; -#endif -}; - -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 - -#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e - -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0 - -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100 - -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200 - -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00 - -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 16 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0001f000 - -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_LSB 17 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MSB 19 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MASK 0x000e0000 - -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 20 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 20 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00100000 - -#define TX_RATE_STATS_INFO_RESERVED_0A_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_RESERVED_0A_LSB 21 -#define TX_RATE_STATS_INFO_RESERVED_0A_MSB 24 -#define TX_RATE_STATS_INFO_RESERVED_0A_MASK 0x01e00000 - -#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 25 -#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28 -#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1e000000 - -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB 29 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB 31 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK 0xe0000000 - -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/fig/v2/tx_raw_or_native_frame_setup.h deleted file mode 100644 index 220a82edf96d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_raw_or_native_frame_setup.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ -#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ - -#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 4 - -#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 - -struct tx_raw_or_native_frame_setup { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t fc_to_ds_mask : 1, - fc_from_ds_mask : 1, - fc_more_frag_mask : 1, - fc_retry_mask : 1, - fc_pwr_mgt_mask : 1, - fc_more_data_mask : 1, - fc_prot_frame_mask : 1, - fc_order_mask : 1, - duration_field_mask : 1, - sequence_control_mask : 1, - qc_tid_mask : 1, - qc_eosp_mask : 1, - qc_ack_policy_mask : 1, - qc_amsdu_mask : 1, - reserved_0a : 1, - qc_15to8_mask : 1, - iv_mask : 1, - fc_to_ds_setting : 1, - fc_from_ds_setting : 1, - fc_more_frag_setting : 1, - fc_retry_setting : 2, - fc_pwr_mgt_setting : 1, - fc_more_data_setting : 2, - fc_prot_frame_setting : 2, - fc_order_setting : 1, - qc_tid_setting : 4; - uint32_t qc_eosp_setting : 2, - qc_ack_policy_setting : 2, - qc_amsdu_setting : 1, - qc_15to8_setting : 8, - mlo_addr_override : 1, - mlo_ignore_addr3_override : 1, - sequence_control_source : 1, - fragment_number : 4, - sequence_number : 12; - uint32_t mlo_addr_override_for_ctrl : 1, - reserved_2a : 31; - uint32_t tlv64_padding : 32; -#else - uint32_t qc_tid_setting : 4, - fc_order_setting : 1, - fc_prot_frame_setting : 2, - fc_more_data_setting : 2, - fc_pwr_mgt_setting : 1, - fc_retry_setting : 2, - fc_more_frag_setting : 1, - fc_from_ds_setting : 1, - fc_to_ds_setting : 1, - iv_mask : 1, - qc_15to8_mask : 1, - reserved_0a : 1, - qc_amsdu_mask : 1, - qc_ack_policy_mask : 1, - qc_eosp_mask : 1, - qc_tid_mask : 1, - sequence_control_mask : 1, - duration_field_mask : 1, - fc_order_mask : 1, - fc_prot_frame_mask : 1, - fc_more_data_mask : 1, - fc_pwr_mgt_mask : 1, - fc_retry_mask : 1, - fc_more_frag_mask : 1, - fc_from_ds_mask : 1, - fc_to_ds_mask : 1; - uint32_t sequence_number : 12, - fragment_number : 4, - sequence_control_source : 1, - mlo_ignore_addr3_override : 1, - mlo_addr_override : 1, - qc_15to8_setting : 8, - qc_amsdu_setting : 1, - qc_ack_policy_setting : 2, - qc_eosp_setting : 2; - uint32_t reserved_2a : 31, - mlo_addr_override_for_ctrl : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x0000000000000001 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x0000000000000002 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x0000000000000004 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x0000000000000008 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x0000000000000010 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x0000000000000020 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x0000000000000040 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x0000000000000080 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x0000000000000100 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x0000000000000200 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x0000000000000400 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x0000000000000800 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x0000000000001000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x0000000000002000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x0000000000004000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x0000000000008000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x0000000000010000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x0000000000020000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x0000000000040000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x0000000000080000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x0000000000300000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x0000000000400000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x0000000001800000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x0000000006000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x0000000008000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0x00000000f0000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 32 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 33 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x0000000300000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 34 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 35 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c00000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 36 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 36 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x0000001000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 37 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 44 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 45 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 45 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x0000200000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 46 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 46 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x0000400000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 47 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 47 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x0000800000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 48 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 51 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f000000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 52 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 63 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff0000000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_LSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MASK 0x0000000000000001 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_LSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MSB 31 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MASK 0x00000000fffffffe - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_LSB 32 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MSB 63 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_basics.h deleted file mode 100644 index 4032a78ad617..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_basics.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_BUFFER_BASICS_H_ -#define _TXPCU_BUFFER_BASICS_H_ - -#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 - -struct txpcu_buffer_basics { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t available_memory : 8, - partial_tx_data_tlv_count : 8, - tx_data_tlv_count : 16; -#else - uint32_t tx_data_tlv_count : 16, - partial_tx_data_tlv_count : 8, - available_memory : 8; -#endif -}; - -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff - -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 - -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_status.h deleted file mode 100644 index 847ca277267d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_status.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_BUFFER_STATUS_H_ -#define _TXPCU_BUFFER_STATUS_H_ - -#include "txpcu_buffer_basics.h" -#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 - -#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1 - -struct txpcu_buffer_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct txpcu_buffer_basics txpcu_basix_buffer_info; - uint32_t reserved : 15, - msdu_end : 1, - tx_data_sync_value : 16; -#else - struct txpcu_buffer_basics txpcu_basix_buffer_info; - uint32_t tx_data_sync_value : 16, - msdu_end : 1, - reserved : 15; -#endif -}; - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 - -#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_RESERVED_LSB 32 -#define TXPCU_BUFFER_STATUS_RESERVED_MSB 46 -#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000 - -#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47 -#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47 -#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 - -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/fig/v2/txpcu_user_buffer_status.h deleted file mode 100644 index f6ad0fd73721..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/txpcu_user_buffer_status.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_USER_BUFFER_STATUS_H_ -#define _TXPCU_USER_BUFFER_STATUS_H_ - -#include "txpcu_buffer_basics.h" -#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 - -#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1 - -struct txpcu_user_buffer_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct txpcu_buffer_basics txpcu_basic_buffer_info; - uint32_t stored_word_count_user : 14, - reserved_1a : 1, - msdu_end : 1, - tx_data_sync_value : 16; -#else - struct txpcu_buffer_basics txpcu_basic_buffer_info; - uint32_t tx_data_sync_value : 16, - msdu_end : 1, - reserved_1a : 1, - stored_word_count_user : 14; -#endif -}; - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 - -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 32 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 45 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff00000000 - -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 46 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 46 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x0000400000000000 - -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 47 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 47 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 - -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_su_mu_info.h deleted file mode 100644 index 1a08f3ab39b2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_su_mu_info.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _U_SIG_EHT_SU_MU_INFO_H_ -#define _U_SIG_EHT_SU_MU_INFO_H_ - -#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 - -struct u_sig_eht_su_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_version : 3, - transmit_bw : 3, - dl_ul_flag : 1, - bss_color_id : 6, - txop_duration : 7, - disregard_0a : 5, - validate_0b : 1, - reserved_0c : 6; - uint32_t eht_ppdu_sig_cmn_type : 2, - validate_1a : 1, - punctured_channel_information : 5, - validate_1b : 1, - mcs_of_eht_sig : 2, - num_eht_sig_symbols : 5, - crc : 4, - tail : 6, - dot11ax_su_extended : 1, - reserved_1d : 3, - rx_ndp : 1, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0c : 6, - validate_0b : 1, - disregard_0a : 5, - txop_duration : 7, - bss_color_id : 6, - dl_ul_flag : 1, - transmit_bw : 3, - phy_version : 3; - uint32_t rx_integrity_check_passed : 1, - rx_ndp : 1, - reserved_1d : 3, - dot11ax_su_extended : 1, - tail : 6, - crc : 4, - num_eht_sig_symbols : 5, - mcs_of_eht_sig : 2, - validate_1b : 1, - punctured_channel_information : 5, - validate_1a : 1, - eht_ppdu_sig_cmn_type : 2; -#endif -}; - -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 - -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 - -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 - -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 - -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 - -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 - -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 - -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 - -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 - -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 - -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 - -#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 -#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 -#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 - -#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 -#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 -#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 - -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 - -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 - -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 - -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_tb_info.h deleted file mode 100644 index 8e417b38d233..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_tb_info.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _U_SIG_EHT_TB_INFO_H_ -#define _U_SIG_EHT_TB_INFO_H_ - -#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 - -struct u_sig_eht_tb_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_version : 3, - transmit_bw : 3, - dl_ul_flag : 1, - bss_color_id : 6, - txop_duration : 7, - disregard_0a : 6, - reserved_0c : 6; - uint32_t eht_ppdu_sig_cmn_type : 2, - validate_1a : 1, - spatial_reuse : 8, - disregard_1b : 5, - crc : 4, - tail : 6, - reserved_1c : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0c : 6, - disregard_0a : 6, - txop_duration : 7, - bss_color_id : 6, - dl_ul_flag : 1, - transmit_bw : 3, - phy_version : 3; - uint32_t rx_integrity_check_passed : 1, - reserved_1c : 5, - tail : 6, - crc : 4, - disregard_1b : 5, - spatial_reuse : 8, - validate_1a : 1, - eht_ppdu_sig_cmn_type : 2; -#endif -}; - -#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 - -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 - -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 - -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 - -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 - -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 - -#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 - -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 - -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 - -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 - -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 - -#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_CRC_LSB 16 -#define U_SIG_EHT_TB_INFO_CRC_MSB 19 -#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 - -#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 -#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 -#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 - -#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 - -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/fig/v2/unallocated_ru_160_info.h deleted file mode 100644 index ccd4a7bab9ad..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/unallocated_ru_160_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _UNALLOCATED_RU_160_INFO_H_ -#define _UNALLOCATED_RU_160_INFO_H_ - -#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 - -struct unallocated_ru_160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t subband80_0_cc0 : 8, - subband80_0_cc1 : 8, - subband80_1_cc0 : 8, - subband80_1_cc1 : 8; -#else - uint32_t subband80_1_cc1 : 8, - subband80_1_cc0 : 8, - subband80_0_cc1 : 8, - subband80_0_cc0 : 8; -#endif -}; - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/fig/v2/uniform_descriptor_header.h deleted file mode 100644 index 7a2de6ccd8df..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/uniform_descriptor_header.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ -#define _UNIFORM_DESCRIPTOR_HEADER_H_ - -#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 - -struct uniform_descriptor_header { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t owner : 4, - buffer_type : 4, - tx_mpdu_queue_number : 20, - reserved_0a : 4; -#else - uint32_t reserved_0a : 4, - tx_mpdu_queue_number : 20, - buffer_type : 4, - owner : 4; -#endif -}; - -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f - -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 - -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 - -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_a_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_a_info.h deleted file mode 100644 index acd20f43949e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_a_info.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_A_INFO_H_ -#define _VHT_SIG_A_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 - -struct vht_sig_a_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t bandwidth : 2, - vhta_reserved_0 : 1, - stbc : 1, - group_id : 6, - n_sts : 12, - txop_ps_not_allowed : 1, - vhta_reserved_0b : 1, - reserved_0 : 8; - uint32_t gi_setting : 2, - su_mu_coding : 1, - ldpc_extra_symbol : 1, - mcs : 4, - beamformed : 1, - vhta_reserved_1 : 1, - crc : 8, - tail : 6, - reserved_1 : 7, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0 : 8, - vhta_reserved_0b : 1, - txop_ps_not_allowed : 1, - n_sts : 12, - group_id : 6, - stbc : 1, - vhta_reserved_0 : 1, - bandwidth : 2; - uint32_t rx_integrity_check_passed : 1, - reserved_1 : 7, - tail : 6, - crc : 8, - vhta_reserved_1 : 1, - beamformed : 1, - mcs : 4, - ldpc_extra_symbol : 1, - su_mu_coding : 1, - gi_setting : 2; -#endif -}; - -#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0 -#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1 -#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004 - -#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_STBC_LSB 3 -#define VHT_SIG_A_INFO_STBC_MSB 3 -#define VHT_SIG_A_INFO_STBC_MASK 0x00000008 - -#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_GROUP_ID_LSB 4 -#define VHT_SIG_A_INFO_GROUP_ID_MSB 9 -#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0 - -#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_N_STS_LSB 10 -#define VHT_SIG_A_INFO_N_STS_MSB 21 -#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00 - -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000 - -#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_RESERVED_0_LSB 24 -#define VHT_SIG_A_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000 - -#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_GI_SETTING_LSB 0 -#define VHT_SIG_A_INFO_GI_SETTING_MSB 1 -#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003 - -#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2 -#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2 -#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004 - -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008 - -#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_MCS_LSB 4 -#define VHT_SIG_A_INFO_MCS_MSB 7 -#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0 - -#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8 -#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8 -#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200 - -#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_CRC_LSB 10 -#define VHT_SIG_A_INFO_CRC_MSB 17 -#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00 - -#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_TAIL_LSB 18 -#define VHT_SIG_A_INFO_TAIL_MSB 23 -#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000 - -#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_RESERVED_1_LSB 24 -#define VHT_SIG_A_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000 - -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu160_info.h deleted file mode 100644 index 13931c5c3556..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu160_info.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU160_INFO_H_ -#define _VHT_SIG_B_MU160_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 - -struct vht_sig_b_mu160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - mcs : 4, - tail : 6, - reserved_0 : 3; - uint32_t length_copy_a : 19, - mcs_copy_a : 4, - tail_copy_a : 6, - reserved_1 : 3; - uint32_t length_copy_b : 19, - mcs_copy_b : 4, - tail_copy_b : 6, - reserved_2 : 3; - uint32_t length_copy_c : 19, - mcs_copy_c : 4, - tail_copy_c : 6, - reserved_3 : 3; - uint32_t length_copy_d : 19, - mcs_copy_d : 4, - tail_copy_d : 6, - reserved_4 : 3; - uint32_t length_copy_e : 19, - mcs_copy_e : 4, - tail_copy_e : 6, - reserved_5 : 3; - uint32_t length_copy_f : 19, - mcs_copy_f : 4, - tail_copy_f : 6, - mu_user_number : 3; - uint32_t length_copy_g : 19, - mcs_copy_g : 4, - tail_copy_g : 6, - reserved_7 : 3; -#else - uint32_t reserved_0 : 3, - tail : 6, - mcs : 4, - length : 19; - uint32_t reserved_1 : 3, - tail_copy_a : 6, - mcs_copy_a : 4, - length_copy_a : 19; - uint32_t reserved_2 : 3, - tail_copy_b : 6, - mcs_copy_b : 4, - length_copy_b : 19; - uint32_t reserved_3 : 3, - tail_copy_c : 6, - mcs_copy_c : 4, - length_copy_c : 19; - uint32_t reserved_4 : 3, - tail_copy_d : 6, - mcs_copy_d : 4, - length_copy_d : 19; - uint32_t reserved_5 : 3, - tail_copy_e : 6, - mcs_copy_e : 4, - length_copy_e : 19; - uint32_t mu_user_number : 3, - tail_copy_f : 6, - mcs_copy_f : 4, - length_copy_f : 19; - uint32_t reserved_7 : 3, - tail_copy_g : 6, - mcs_copy_g : 4, - length_copy_g : 19; -#endif -}; - -#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu20_info.h deleted file mode 100644 index c51ac839a757..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu20_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU20_INFO_H_ -#define _VHT_SIG_B_MU20_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 - -struct vht_sig_b_mu20_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 16, - mcs : 4, - tail : 6, - mu_user_number : 3, - reserved_0 : 3; -#else - uint32_t reserved_0 : 3, - mu_user_number : 3, - tail : 6, - mcs : 4, - length : 16; -#endif -}; - -#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 -#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff - -#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 -#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 -#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 - -#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 -#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 -#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 - -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 - -#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu40_info.h deleted file mode 100644 index 0eb4c164cca1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu40_info.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU40_INFO_H_ -#define _VHT_SIG_B_MU40_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 - -struct vht_sig_b_mu40_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 17, - mcs : 4, - tail : 6, - reserved_0 : 2, - mu_user_number : 3; - uint32_t length_copy : 17, - mcs_copy : 4, - tail_copy : 6, - reserved_1 : 5; -#else - uint32_t mu_user_number : 3, - reserved_0 : 2, - tail : 6, - mcs : 4, - length : 17; - uint32_t reserved_1 : 5, - tail_copy : 6, - mcs_copy : 4, - length_copy : 17; -#endif -}; - -#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 -#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff - -#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 -#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 -#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 - -#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 -#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 -#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 - -#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 - -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff - -#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 - -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 - -#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu80_info.h deleted file mode 100644 index 33d0f1bc08fc..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu80_info.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU80_INFO_H_ -#define _VHT_SIG_B_MU80_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 - -struct vht_sig_b_mu80_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - mcs : 4, - tail : 6, - reserved_0 : 3; - uint32_t length_copy_a : 19, - mcs_copy_a : 4, - tail_copy_a : 6, - reserved_1 : 3; - uint32_t length_copy_b : 19, - mcs_copy_b : 4, - tail_copy_b : 6, - mu_user_number : 3; - uint32_t length_copy_c : 19, - mcs_copy_c : 4, - tail_copy_c : 6, - reserved_3 : 3; -#else - uint32_t reserved_0 : 3, - tail : 6, - mcs : 4, - length : 19; - uint32_t reserved_1 : 3, - tail_copy_a : 6, - mcs_copy_a : 4, - length_copy_a : 19; - uint32_t mu_user_number : 3, - tail_copy_b : 6, - mcs_copy_b : 4, - length_copy_b : 19; - uint32_t reserved_3 : 3, - tail_copy_c : 6, - mcs_copy_c : 4, - length_copy_c : 19; -#endif -}; - -#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su160_info.h deleted file mode 100644 index 7ba503724b56..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su160_info.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU160_INFO_H_ -#define _VHT_SIG_B_SU160_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 - -struct vht_sig_b_su160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 21, - vhtb_reserved : 2, - tail : 6, - reserved_0 : 2, - rx_ndp : 1; - uint32_t length_copy_a : 21, - vhtb_reserved_copy_a : 2, - tail_copy_a : 6, - reserved_1 : 2, - rx_ndp_copy_a : 1; - uint32_t length_copy_b : 21, - vhtb_reserved_copy_b : 2, - tail_copy_b : 6, - reserved_2 : 2, - rx_ndp_copy_b : 1; - uint32_t length_copy_c : 21, - vhtb_reserved_copy_c : 2, - tail_copy_c : 6, - reserved_3 : 2, - rx_ndp_copy_c : 1; - uint32_t length_copy_d : 21, - vhtb_reserved_copy_d : 2, - tail_copy_d : 6, - reserved_4 : 2, - rx_ndp_copy_d : 1; - uint32_t length_copy_e : 21, - vhtb_reserved_copy_e : 2, - tail_copy_e : 6, - reserved_5 : 2, - rx_ndp_copy_e : 1; - uint32_t length_copy_f : 21, - vhtb_reserved_copy_f : 2, - tail_copy_f : 6, - reserved_6 : 2, - rx_ndp_copy_f : 1; - uint32_t length_copy_g : 21, - vhtb_reserved_copy_g : 2, - tail_copy_g : 6, - reserved_7 : 2, - rx_ndp_copy_g : 1; -#else - uint32_t rx_ndp : 1, - reserved_0 : 2, - tail : 6, - vhtb_reserved : 2, - length : 21; - uint32_t rx_ndp_copy_a : 1, - reserved_1 : 2, - tail_copy_a : 6, - vhtb_reserved_copy_a : 2, - length_copy_a : 21; - uint32_t rx_ndp_copy_b : 1, - reserved_2 : 2, - tail_copy_b : 6, - vhtb_reserved_copy_b : 2, - length_copy_b : 21; - uint32_t rx_ndp_copy_c : 1, - reserved_3 : 2, - tail_copy_c : 6, - vhtb_reserved_copy_c : 2, - length_copy_c : 21; - uint32_t rx_ndp_copy_d : 1, - reserved_4 : 2, - tail_copy_d : 6, - vhtb_reserved_copy_d : 2, - length_copy_d : 21; - uint32_t rx_ndp_copy_e : 1, - reserved_5 : 2, - tail_copy_e : 6, - vhtb_reserved_copy_e : 2, - length_copy_e : 21; - uint32_t rx_ndp_copy_f : 1, - reserved_6 : 2, - tail_copy_f : 6, - vhtb_reserved_copy_f : 2, - length_copy_f : 21; - uint32_t rx_ndp_copy_g : 1, - reserved_7 : 2, - tail_copy_g : 6, - vhtb_reserved_copy_g : 2, - length_copy_g : 21; -#endif -}; - -#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su20_info.h deleted file mode 100644 index 2c7f11ba3c21..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su20_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU20_INFO_H_ -#define _VHT_SIG_B_SU20_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 - -struct vht_sig_b_su20_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 17, - vhtb_reserved : 3, - tail : 6, - reserved : 5, - rx_ndp : 1; -#else - uint32_t rx_ndp : 1, - reserved : 5, - tail : 6, - vhtb_reserved : 3, - length : 17; -#endif -}; - -#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 -#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff - -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 - -#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 -#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 -#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 - -#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 -#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 -#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 - -#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su40_info.h deleted file mode 100644 index 467259003e8d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su40_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU40_INFO_H_ -#define _VHT_SIG_B_SU40_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 - -struct vht_sig_b_su40_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - vhtb_reserved : 2, - tail : 6, - reserved : 4, - rx_ndp : 1; - uint32_t length_copy : 19, - vhtb_reserved_copy : 2, - tail_copy : 6, - reserved_copy : 4, - rx_ndp_copy : 1; -#else - uint32_t rx_ndp : 1, - reserved : 4, - tail : 6, - vhtb_reserved : 2, - length : 19; - uint32_t rx_ndp_copy : 1, - reserved_copy : 4, - tail_copy : 6, - vhtb_reserved_copy : 2, - length_copy : 19; -#endif -}; - -#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 - -#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 -#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 -#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 - -#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 -#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 -#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 - -#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff - -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 - -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 - -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 - -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su80_info.h deleted file mode 100644 index 92ceeab9b476..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su80_info.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU80_INFO_H_ -#define _VHT_SIG_B_SU80_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 - -struct vht_sig_b_su80_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 21, - vhtb_reserved : 2, - tail : 6, - reserved_0 : 2, - rx_ndp : 1; - uint32_t length_copy_a : 21, - vhtb_reserved_copy_a : 2, - tail_copy_a : 6, - reserved_1 : 2, - rx_ndp_copy_a : 1; - uint32_t length_copy_b : 21, - vhtb_reserved_copy_b : 2, - tail_copy_b : 6, - reserved_2 : 2, - rx_ndp_copy_b : 1; - uint32_t length_copy_c : 21, - vhtb_reserved_copy_c : 2, - tail_copy_c : 6, - reserved_3 : 2, - rx_ndp_copy_c : 1; -#else - uint32_t rx_ndp : 1, - reserved_0 : 2, - tail : 6, - vhtb_reserved : 2, - length : 21; - uint32_t rx_ndp_copy_a : 1, - reserved_1 : 2, - tail_copy_a : 6, - vhtb_reserved_copy_a : 2, - length_copy_a : 21; - uint32_t rx_ndp_copy_b : 1, - reserved_2 : 2, - tail_copy_b : 6, - vhtb_reserved_copy_b : 2, - length_copy_b : 21; - uint32_t rx_ndp_copy_c : 1, - reserved_3 : 2, - tail_copy_c : 6, - vhtb_reserved_copy_c : 2, - length_copy_c : 21; -#endif -}; - -#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wbm2sw_completion_ring_rx.h b/drivers/staging/fw-api/hw/fig/v2/wbm2sw_completion_ring_rx.h deleted file mode 100644 index e40a7e796a87..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wbm2sw_completion_ring_rx.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM2SW_COMPLETION_RING_RX_H_ -#define _WBM2SW_COMPLETION_RING_RX_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_mpdu_desc_info.h" -#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 - -struct wbm2sw_completion_ring_rx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t release_source_module : 3, - bm_action : 3, - buffer_or_desc_type : 3, - return_buffer_manager : 4, - reserved_2a : 2, - cache_id : 1, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_push_reason : 2, - reo_error_code : 5, - wbm_internal_error : 1; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t buffer_phys_addr_31_0 : 32; - uint32_t buffer_phys_addr_39_32 : 8, - sw_buffer_cookie : 20, - looping_count : 4; -#else - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t wbm_internal_error : 1, - reo_error_code : 5, - reo_push_reason : 2, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - cache_id : 1, - reserved_2a : 2, - return_buffer_manager : 4, - buffer_or_desc_type : 3, - bm_action : 3, - release_source_module : 3; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t buffer_phys_addr_31_0 : 32; - uint32_t looping_count : 4, - sw_buffer_cookie : 20, - buffer_phys_addr_39_32 : 8; -#endif -}; - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 - -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 - -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 - -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 - -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 - -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 - -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 - -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 - -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff - -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 - -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/fig/v2/wbm_buffer_ring.h deleted file mode 100644 index b1532e15595b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wbm_buffer_ring.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_BUFFER_RING_H_ -#define _WBM_BUFFER_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 - -struct wbm_buffer_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_addr_info; -#else - struct buffer_addr_info buf_addr_info; -#endif -}; - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/fig/v2/wbm_link_descriptor_ring.h deleted file mode 100644 index 851807aa4c1c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wbm_link_descriptor_ring.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ -#define _WBM_LINK_DESCRIPTOR_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 - -struct wbm_link_descriptor_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info desc_addr_info; -#else - struct buffer_addr_info desc_addr_info; -#endif -}; - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring.h b/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring.h deleted file mode 100644 index e86d52753912..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_H_ -#define _WBM_RELEASE_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 - -struct wbm_release_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - reserved_2a : 3, - buffer_or_desc_type : 3, - reserved_2b : 22, - wbm_internal_error : 1; - uint32_t reserved_3a : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_5a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 28, - looping_count : 4; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t wbm_internal_error : 1, - reserved_2b : 22, - buffer_or_desc_type : 3, - reserved_2a : 3, - release_source_module : 3; - uint32_t reserved_3a : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_5a : 32; - uint32_t reserved_6a : 32; - uint32_t looping_count : 4, - reserved_7a : 28; -#endif -}; - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RESERVED_2A_LSB 3 -#define WBM_RELEASE_RING_RESERVED_2A_MSB 5 -#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 - -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RESERVED_2B_LSB 9 -#define WBM_RELEASE_RING_RESERVED_2B_MSB 30 -#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 - -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 - -#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c -#define WBM_RELEASE_RING_RESERVED_3A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_3A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 -#define WBM_RELEASE_RING_RESERVED_4A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_4A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 -#define WBM_RELEASE_RING_RESERVED_5A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_5A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 -#define WBM_RELEASE_RING_RESERVED_6A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_6A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c -#define WBM_RELEASE_RING_RESERVED_7A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_7A_MSB 27 -#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff - -#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 -#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 -#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_rx.h b/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_rx.h deleted file mode 100644 index a68bc8115a82..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_rx.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_RX_H_ -#define _WBM_RELEASE_RING_RX_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 4 - -struct wbm_release_ring_rx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - buffer_or_desc_type : 3, - reserved_2a : 14, - mpdu_sequence_number : 12; - uint32_t reserved_3a : 32; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t mpdu_sequence_number : 12, - reserved_2a : 14, - buffer_or_desc_type : 3, - release_source_module : 3; - uint32_t reserved_3a : 32; -#endif -}; - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 3 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 5 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x00000038 - -#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 6 -#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 19 -#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x000fffc0 - -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_LSB 20 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MSB 31 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 - -#define WBM_RELEASE_RING_RX_RESERVED_3A_OFFSET 0x0000000c -#define WBM_RELEASE_RING_RX_RESERVED_3A_LSB 0 -#define WBM_RELEASE_RING_RX_RESERVED_3A_MSB 31 -#define WBM_RELEASE_RING_RX_RESERVED_3A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_tx.h b/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_tx.h deleted file mode 100644 index d1412153c6ae..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_tx.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_TX_H_ -#define _WBM_RELEASE_RING_TX_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 4 - -struct wbm_release_ring_tx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - buffer_or_desc_type : 3, - reserved_2a : 26; - uint32_t tqm_status_number : 32; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t reserved_2a : 26, - buffer_or_desc_type : 3, - release_source_module : 3; - uint32_t tqm_status_number : 32; -#endif -}; - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 3 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 5 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x00000038 - -#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 6 -#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 31 -#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0xffffffc0 - -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 31 -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwiobase.h deleted file mode 100644 index 4e455f399300..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwiobase.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOBASE_H -#define WCSS_SEQ_HWIOBASE_H - -#define UMAC_NOC_BASE 0x140000 -#define UMAC_NOC_BASE_SIZE 0x00004480 -#define UMAC_NOC_BASE_PHYS 0x00140000 - -#define PHYA0_BASE 0x300000 -#define PHYA0_BASE_SIZE 0x00300000 -#define PHYA0_BASE_PHYS 0x00300000 - -#define PHYA1_BASE 0x600000 -#define PHYA1_BASE_SIZE 0x00300000 -#define PHYA1_BASE_PHYS 0x00600000 - -#define DMAC_BASE 0x900000 -#define DMAC_BASE_SIZE 0x00080000 -#define DMAC_BASE_PHYS 0x00900000 - -#define UMAC_BASE 0xa00000 -#define UMAC_BASE_SIZE 0x0004d000 -#define UMAC_BASE_PHYS 0x00a00000 - -#define PMAC0_BASE 0xa80000 -#define PMAC0_BASE_SIZE 0x00040000 -#define PMAC0_BASE_PHYS 0x00a80000 - -#define PMAC1_BASE 0xac0000 -#define PMAC1_BASE_SIZE 0x00040000 -#define PMAC1_BASE_PHYS 0x00ac0000 - -#define WFSS_AMCSS_BASE 0xb00000 -#define WFSS_AMCSS_BASE_SIZE 0x00040000 -#define WFSS_AMCSS_BASE_PHYS 0x00b00000 - -#define CXC_BASE 0xb40000 -#define CXC_BASE_SIZE 0x00010000 -#define CXC_BASE_PHYS 0x00b40000 - -#define WFSS_PMM_BASE 0xb50000 -#define WFSS_PMM_BASE_SIZE 0x00002401 -#define WFSS_PMM_BASE_PHYS 0x00b50000 - -#define WFSS_CC_BASE 0xb60000 -#define WFSS_CC_BASE_SIZE 0x00008000 -#define WFSS_CC_BASE_PHYS 0x00b60000 - -#define WCMN_CORE_BASE 0xb68000 -#define WCMN_CORE_BASE_SIZE 0x000008a9 -#define WCMN_CORE_BASE_PHYS 0x00b68000 - -#define WIFI_CFGBUS_APB_TSLV_BASE 0xb6b000 -#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000 -#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000 - -#define WFSS_CFGBUS_BASE 0xb6c000 -#define WFSS_CFGBUS_BASE_SIZE 0x000000a0 -#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000 - -#define WIFI_CFGBUS_AHB_TSLV_BASE 0xb6d000 -#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000 -#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000 - -#define UMAC_ACMT_BASE 0xb6e000 -#define UMAC_ACMT_BASE_SIZE 0x00001000 -#define UMAC_ACMT_BASE_PHYS 0x00b6e000 - -#define WCSS_CC_BASE 0xb80000 -#define WCSS_CC_BASE_SIZE 0x00010000 -#define WCSS_CC_BASE_PHYS 0x00b80000 - -#define PMM_TOP_BASE 0xb90000 -#define PMM_TOP_BASE_SIZE 0x00010000 -#define PMM_TOP_BASE_PHYS 0x00b90000 - -#define WCSS_TOP_CMN_BASE 0xba0000 -#define WCSS_TOP_CMN_BASE_SIZE 0x00004000 -#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000 - -#define WCSS_CFGBUS_BASE 0xba4000 -#define WCSS_CFGBUS_BASE_SIZE 0x00008000 -#define WCSS_CFGBUS_BASE_PHYS 0x00ba4000 - -#define MSIP_BASE 0xbb0000 -#define MSIP_BASE_SIZE 0x00010000 -#define MSIP_BASE_PHYS 0x00bb0000 - -#define RFA_BASE 0xbc0000 -#define RFA_BASE_SIZE 0x00040000 -#define RFA_BASE_PHYS 0x00bc0000 - -#define DBG_BASE 0x1000000 -#define DBG_BASE_SIZE 0x00100000 -#define DBG_BASE_PHYS 0x01000000 - -#define Q6SS_WLAN_BASE 0x1100000 -#define Q6SS_WLAN_BASE_SIZE 0x00100000 -#define Q6SS_WLAN_BASE_PHYS 0x01100000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_umac.h deleted file mode 100644 index 2f111c881406..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_umac.h +++ /dev/null @@ -1,2481 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef WCSS_SEQ_HWIOREG_UMAC_H - -#include "seq_hwio.h" -#include "wcss_seq_hwiobase.h" -#ifdef SCALE_INCLUDES -#include "HALhwio.h" -#else -#include "msmhwio.h" -#endif - -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x) ((x) + 0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x) ((x) + 0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS (0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK 0xf8000007 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK 0x7 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x) ((x) + 0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x) ((x) + 0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS (0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR 0x00001ffe -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK 0x1ffe000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT 13 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK 0x1ffe -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT 1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK 0x1000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT 12 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK 0x800 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT 11 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK 0x400 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT 10 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK 0x200 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT 9 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x) ((x) + 0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x) ((x) + 0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS (0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK 0xff000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT 24 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK 0xff0000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT 16 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK 0xff00 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT 8 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK 0xff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n) ((base) + 0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n) ((base) + 0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n) (0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK 0xfff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn 31 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK 0xfff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT 0 - -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x) ((x) + 0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x) ((x) + 0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS (0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK 0x3 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x)) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK 0x2 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT 1 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT 0 - -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n) (0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn 63 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) - -#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x40) - -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x130) -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 - -#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x134) -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x138) - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x13c) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x140) - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x144) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x148) - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x14c) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x150) - -#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x24c) - -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0x51c) - -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0x52c) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS (0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK 0x3f -#define HWIO_WBM_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK 0x20 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT 5 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK 0x10 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT 4 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x) ((x) + 0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x) ((x) + 0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS (0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK 0xffffffff -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR 0x00000000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR 0x3 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x) \ - in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x)) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v) \ - out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x)) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK 0xffe00000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT 21 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK 0x1f0000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT 16 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK 0xf800 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT 11 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK 0x7c0 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT 6 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK 0x3e -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT 1 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK 0x1 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT 0 - -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x3ff -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000020 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK 0x200 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT 9 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK 0x100 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT 8 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn 255 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010) - -#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x3040) - -#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) - -#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x) ((x) + 0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x) ((x) + 0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS (0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR 0x76043210 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x) ((x) + 0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x) ((x) + 0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS (0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x6666ba98 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x) ((x) + 0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x) ((x) + 0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS (0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR 0x66666666 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x) ((x) + 0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x) ((x) + 0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS (0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR 0x66666666 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x38) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x3c) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x) ((x) + 0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x) ((x) + 0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS (0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR 0x00000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR 0x3 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x) ((x) + 0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x) ((x) + 0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS (0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR 0x00000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR 0x3 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT 0 - -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x) ((x) + 0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x) ((x) + 0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS (0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK 0x1ffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR 0x00000000 -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR 0x3 -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x) \ - in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v) \ - out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK 0x1ffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT 0 - -#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x6c) - -#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x70) -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 -#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 -#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff -#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 - -#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x344) - -#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x7d0) - -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x7d4) -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x7d8) - -#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) ((x) + 0x7dc) -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x7e0) -#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x7e4) - -#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x7e8) - -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7f4) - -#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x818) - -#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x81c) - -#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x820) - -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x824) - -#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x828) - -#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x82c) - -#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x830) - -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x844) -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x848) - -#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0xc08) - -#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_MISC_CFG_ADDR(x) ((x) + 0x1458) -#define HWIO_REO_R0_MISC_CFG_PHYS(x) ((x) + 0x1458) -#define HWIO_REO_R0_MISC_CFG_OFFS (0x1458) -#define HWIO_REO_R0_MISC_CFG_RMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_POR 0x00000000 -#define HWIO_REO_R0_MISC_CFG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MISC_CFG_ATTR 0x3 -#define HWIO_REO_R0_MISC_CFG_IN(x) \ - in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x)) -#define HWIO_REO_R0_MISC_CFG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m) -#define HWIO_REO_R0_MISC_CFG_OUT(x, v) \ - out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v) -#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x)) -#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT 0 - -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x) ((x) + 0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_PHYS(x) ((x) + 0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OFFS (0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_RMSK 0x7ff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR 0x000003ff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR_RMSK 0xffffffff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ATTR 0x3 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x) \ - in_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x)) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x), m) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUT(x, v) \ - out_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),v) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),m,v,HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x)) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_BMSK 0x400 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_SHFT 10 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_BMSK 0x200 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_SHFT 9 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_BMSK 0x100 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_SHFT 8 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_BMSK 0x80 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_SHFT 7 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_BMSK 0x40 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_SHFT 6 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_BMSK 0x20 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_SHFT 5 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_BMSK 0x10 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_SHFT 4 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_BMSK 0x8 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_SHFT 3 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_BMSK 0x4 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_SHFT 2 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_BMSK 0x2 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_SHFT 1 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_BMSK 0x1 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_SHFT 0 - -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x) ((x) + 0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x) ((x) + 0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS (0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK 0x1ff -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR 0x0000002d -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR 0x3 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x) \ - in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v) \ - out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK 0x1fe -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT 1 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK 0x1 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT 0 - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0x1468) - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0x146c) - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0x1470) - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0x1474) - -#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0x14dc) -#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 -#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 -#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 -#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 - -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_REO_R0_CREDIT_ADDR(x) ((x) + 0x16d0) -#define HWIO_REO_R0_CREDIT_PHYS(x) ((x) + 0x16d0) -#define HWIO_REO_R0_CREDIT_OFFS (0x16d0) -#define HWIO_REO_R0_CREDIT_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_POR 0x00000000 -#define HWIO_REO_R0_CREDIT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_ATTR 0x3 -#define HWIO_REO_R0_CREDIT_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_ADDR(x)) -#define HWIO_REO_R0_CREDIT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_OUT(x, v) \ - out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v) -#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x)) -#define HWIO_REO_R0_CREDIT_VAL_BMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_VAL_SHFT 0 - -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x) ((x) + 0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x) ((x) + 0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS (0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK 0x7 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR 0x00000002 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR 0x3 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x)) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v) \ - out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x)) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK 0x7 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT 0 - -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x) ((x) + 0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x) ((x) + 0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS (0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR 0x00000000 -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR 0x1 -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x)) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT 0 - -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK 0x2000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT 13 - -#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_OFFS (0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_RMSK 0x7 -#define HWIO_REO_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_REO_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_REO_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_PHYS(x) ((x) + 0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OFFS (0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR 0x00060000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ATTR 0x3 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x), m) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),v) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_BMSK 0xf0000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_SHFT 28 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_BMSK 0xf000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_SHFT 24 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_BMSK 0xf00000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_SHFT 20 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_BMSK 0xf0000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_SHFT 16 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_BMSK 0xf000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_SHFT 12 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_BMSK 0xf00 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_SHFT 8 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_BMSK 0xf0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_SHFT 4 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_BMSK 0xf -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_SHFT 0 - -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_PHYS(x) ((x) + 0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OFFS (0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR 0x00060000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ATTR 0x3 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x), m) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),v) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_BMSK 0xf0000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_SHFT 28 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_BMSK 0xf000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_SHFT 24 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_BMSK 0xf00000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_SHFT 20 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_BMSK 0xf0000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_SHFT 16 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_BMSK 0xf000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_SHFT 12 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_BMSK 0xf00 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_SHFT 8 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_BMSK 0xf0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_SHFT 4 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_BMSK 0xf -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_SHFT 0 - -#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x) ((x) + 0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x) ((x) + 0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS (0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK 0x3f -#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR 0x00000000 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR 0x1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x) \ - in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK 0x20 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT 5 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK 0x10 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT 4 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK 0x8 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT 3 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK 0x4 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT 2 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK 0x2 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT 1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK 0x1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT 0 - -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x) ((x) + 0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x) ((x) + 0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS (0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR 0x00000000 -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR 0x3 -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x) \ - in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v) \ - out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT 0 - -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn 255 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028) - -#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3070) - -#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x3074) - -#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3078) - -#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x30b8) - -#define TQM_REG_REG_BASE (UMAC_BASE + 0x0003c000) -#define TQM_REG_REG_BASE_SIZE 0x4000 - -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK 0x80 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT 7 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK 0x40 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT 6 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK 0x20 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT 5 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK 0x10 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT 4 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK 0x8 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT 3 - -#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OFFS (0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OFFS (0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK 0x80000000 -#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT 31 - -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK 0x8000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT 15 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK 0x4000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT 14 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK 0x2000 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT 13 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK 0x1000 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT 12 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK 0x800 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT 11 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK 0x400 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT 10 - -#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS (0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK 0xf -#define HWIO_TQM_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x) ((x) + 0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x) ((x) + 0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS (0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK 0x1ffff -#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR 0x00000000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR 0x3 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x) \ - in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x)) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v) \ - out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x)) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK 0x2 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT 1 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK 0x1 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT 0 - -#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK 0x20000000 -#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT 29 - -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x) ((x) + 0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x) ((x) + 0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS (0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT 0 - -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x) ((x) + 0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x) ((x) + 0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS (0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT 0 - -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x) ((x) + 0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x) ((x) + 0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS (0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT 0 - -#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x) ((x) + 0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x) ((x) + 0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS (0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK 0xfff -#define HWIO_TQM_R0_WATCHDOG_SRNG_POR 0x00000710 -#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR 0x3 -#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x) \ - in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)) -#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)) -#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK 0xfff -#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_PHYS(x) ((x) + 0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OFFS (0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_RMSK 0x1ff -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR 0x000001fe -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_SHFT 7 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_SHFT 6 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_SHFT 5 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_SHFT 4 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_SHFT 3 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_SHFT 2 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_SHFT 1 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_SHFT 0 - -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x) ((x) + 0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PHYS(x) ((x) + 0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OFFS (0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RMSK 0x3fefff -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR 0x00080170 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ATTR 0x3 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x) \ - in_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x)) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x), m) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),v) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),m,v,HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x)) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_BMSK 0x200000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_SHFT 21 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_BMSK 0x100000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_SHFT 20 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x80000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT 19 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_BMSK 0x40000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_SHFT 18 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_BMSK 0x20000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_SHFT 17 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_BMSK 0x10000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_SHFT 16 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_BMSK 0x8000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_SHFT 15 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_BMSK 0x4000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_SHFT 14 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_BMSK 0x2000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_SHFT 13 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_BMSK 0x800 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_SHFT 11 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_BMSK 0x400 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_SHFT 10 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_BMSK 0x200 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_SHFT 9 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_BMSK 0x80 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_SHFT 7 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_BMSK 0x40 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_SHFT 6 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_BMSK 0x20 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_SHFT 5 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_BMSK 0x10 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_SHFT 4 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_BMSK 0x8 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_SHFT 3 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_BMSK 0x4 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_SHFT 2 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_SHFT 1 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_PHYS(x) ((x) + 0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OFFS (0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR 0x00000000 -#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PHYS(x) ((x) + 0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OFFS (0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_RMSK 0x7ffff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR 0x00011100 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0 - -#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x) ((x) + 0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x) ((x) + 0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS (0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x) ((x) + 0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x) ((x) + 0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS (0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x) ((x) + 0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x) ((x) + 0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS (0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x) ((x) + 0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x) ((x) + 0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS (0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK 0xf -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR 0x00000000 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR 0x1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x)) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK 0x8 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT 3 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK 0x4 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT 2 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK 0x2 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT 1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK 0x1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT 0 - -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x) ((x) + 0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x) ((x) + 0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS (0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR 0x00000000 -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR 0x1 -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x) \ - in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x)) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT 0 - -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x) ((x) + 0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x) ((x) + 0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS (0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR 0x00000000 -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR 0x1 -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x) \ - in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x)) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT 0 - -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0xff -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn 127 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_PHYS(x) ((x) + 0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OFFS (0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_PHYS(x) ((x) + 0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OFFS (0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK 0x80 -#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT 7 - -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 28 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 27 - -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 - -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 - -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 - -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 - -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 28 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 27 - -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 - -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 - -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 - -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 - -#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK 0x40 -#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT 6 - -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x) ((x) + 0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x) ((x) + 0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS (0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK 0xf -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR 0x0000000a -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR 0x3 -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x) \ - in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK 0xf -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT 0 - -#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS (0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK 0x1f -#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK 0x10 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT 4 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK 0x8 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT 3 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK 0x4 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT 2 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK 0x2 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT 1 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_UMCMN_R0_LINK_ID_ADDR(x) ((x) + 0x170) -#define HWIO_UMCMN_R0_LINK_ID_PHYS(x) ((x) + 0x170) -#define HWIO_UMCMN_R0_LINK_ID_OFFS (0x170) -#define HWIO_UMCMN_R0_LINK_ID_RMSK 0xffff -#define HWIO_UMCMN_R0_LINK_ID_POR 0x000052c8 -#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_LINK_ID_ATTR 0x3 -#define HWIO_UMCMN_R0_LINK_ID_IN(x) \ - in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x)) -#define HWIO_UMCMN_R0_LINK_ID_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m) -#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v) -#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x)) -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK 0x80 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT 7 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK 0x40 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT 6 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK 0x38 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT 3 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK 0x7 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT 0 - -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK 0x4000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT 14 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK 0x2000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT 13 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK 0x1000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT 12 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK 0x800 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT 11 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK 0x400 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT 10 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK 0x200 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT 9 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK 0x100 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT 8 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK 0x80 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT 7 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK 0x40 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT 6 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK 0x20 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT 5 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK 0x10 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT 4 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK 0x8 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT 3 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK 0x4 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT 2 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK 0x2 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT 1 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK 0x1 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT 0 - -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x) ((x) + 0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x) ((x) + 0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS (0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK 0x1 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR 0x00000000 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR 0x3 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x) \ - in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x)) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x)) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK 0x1 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT 0 - -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x) ((x) + 0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x) ((x) + 0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS (0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK 0x1ffff -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR 0x00000000 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR 0x3 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x) \ - in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x)) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x)) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK 0x1fe00 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT 9 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK 0x1fe -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT 1 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK 0x1 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT 0 - -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x1ff -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK 0x100 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT 8 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK 0x80 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT 7 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK 0x40 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT 6 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK 0x20 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT 5 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n) ((base) + 0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n) ((base) + 0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n) (0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn 7 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR 0x00000000 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR 0x3 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n) \ - in_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n)) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val) \ - out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n)) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT 0 - -#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) - -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 - -#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK 0x200000 -#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT 21 - -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X74 + (0x4*(n))) -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 - -#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X174 + (0x4*(n))) -#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff - -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK 0x800000 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT 23 - -#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK 0x40 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT 6 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK 0x20 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT 5 - -#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x) ((x) + 0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x) ((x) + 0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS (0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK 0x3 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR 0x00000000 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR 0x3 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x) \ - in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x)) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v) \ - out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x)) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK 0x2 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT 1 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK 0x1 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT 0 - -#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS (0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK 0x7 -#define HWIO_TCL_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x8c8) - -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x8cc) -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x8d0) -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x8d8) -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x8e4) - -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x8e8) - -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x8f8) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x8fc) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x910) - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x914) -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x918) - -#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x940) - -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x10000 -#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 16 - -#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x10000 -#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 16 - -#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS (0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK 0x1ff -#define HWIO_TCL_R1_TESTBUS_CTRL_POR 0x00000000 -#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR 0x3 -#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x) \ - in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)) -#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m) -#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v) -#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x)) -#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x100 -#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 8 -#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK 0xc0 -#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT 6 -#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK 0x3f -#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT 0 - -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn 511 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) - -#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) - -#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) - -#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_wifi_top.h b/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_wifi_top.h deleted file mode 100644 index 072ec2ed4af7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_wifi_top.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOREG_WIFI_TOP_H -#define WCSS_SEQ_HWIOREG_WIFI_TOP_H - -#include "wcss_seq_hwiobase.h" - -#define WFSS_PMM_REG_BASE (WFSS_PMM_BASE + 0x00000000) - -#define HWIO_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_26_ADDR(x) ((x) + 0x164) - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wcss_version.h b/drivers/staging/fw-api/hw/fig/v2/wcss_version.h deleted file mode 100644 index a543f80cca7c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wcss_version.h +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#define WCSS_VERSION 3181 diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/HALcomdef.h b/drivers/staging/fw-api/hw/wcn8750/v1/HALcomdef.h deleted file mode 100644 index 60ee92e6cd2e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/HALcomdef.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef HAL_COMDEF_H -#define HAL_COMDEF_H - -#ifndef _ARM_ASM_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "com_dtypes.h" - -#ifndef _BOOL32_DEFINED -typedef unsigned long int bool32; -#define _BOOL32_DEFINED -#endif - -#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF - - #define inp(port) (*((volatile byte *) (port))) - #define inpw(port) (*((volatile word *) (port))) - #define inpdw(port) (*((volatile dword *)(port))) - - #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) - #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) - #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) - -#ifdef __cplusplus -} -#endif - -#endif - -#endif - diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/HALhwio.h b/drivers/staging/fw-api/hw/wcn8750/v1/HALhwio.h deleted file mode 100644 index 059d69b1be87..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/HALhwio.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef HAL_HWIO_H -#define HAL_HWIO_H - -#include "HALcomdef.h" - -#define HWIO_BASE_PTR(base) base##_BASE_PTR - -#ifdef __ARMCC_VERSION - #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) -#else - #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) -#endif - -#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) -#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) -#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) -#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) - -#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) -#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) -#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) -#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) -#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) -#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) -#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) - -#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) -#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) -#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) -#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) -#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) -#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) -#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) - -#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) -#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) -#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) -#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) - -#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) -#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) -#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) -#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) - -#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) - -#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) -#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) -#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) -#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) -#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) -#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) -#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) - -#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) - -#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) -#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) -#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) -#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) - -#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) -#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) -#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) -#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) - -#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) - -#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) - -#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) -#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) -#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) -#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) - -#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) -#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) -#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) -#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) -#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) -#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) -#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) - -#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) -#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) -#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) - -#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) - -#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) - -#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) -#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) -#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) -#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) -#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) -#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) -#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) -#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) - -#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) -#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) - -#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN -#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) -#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) -#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) -#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) -#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) -#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) -#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) -#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) -#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) -#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) -#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) -#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) -#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) -#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) -#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) -#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR -#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) -#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) -#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) -#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS -#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) -#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) -#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) -#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS -#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) -#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) -#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) -#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK -#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) -#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK -#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT -#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT -#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow -#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) -#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL - -#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) -#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) -#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) -#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) -#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) -#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) -#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) -#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) -#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) -#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) -#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) -#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) -#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) -#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ - static uint32 Readdata, Val_temp, Val; \ - Readdata = HWIO_INX(base, hwiosym); \ - Val_temp = Readdata & ~mask1 & ~mask2; \ - Val = Val_temp | val1 | val2; \ - HWIO_##hwiosym##_OUT(base, Val); \ - } - -#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ - static uint32 Readdata, Val_temp, Val; \ - Readdata = HWIO_INX(base, hwiosym); \ - Val_temp = Readdata & ~mask1 & ~mask2 & ~mask3; \ - Val = Val_temp | val1 | val2 | val3; \ - HWIO_##hwiosym##_OUT(base, Val); \ - } - -#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ - static uint32 Readdata, Val_temp, Val; \ - Readdata = HWIO_INX(base, hwiosym); \ - Val_temp = Readdata & ~mask1 & ~mask2 & ~mask3 & ~mask4; \ - Val = Val_temp | val1 | val2 | val3 | val4; \ - HWIO_##hwiosym##_OUT(base, Val); \ - } - -#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) -#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) -#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) -#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) -#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) -#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) -#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) -#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) -#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) -#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) -#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) - -#define HWIO_INTLOCK() -#define HWIO_INTFREE() - -#define __inp(port) (*((volatile uint8 *) (port))) -#define __inpw(port) (*((volatile uint16 *) (port))) -#define __inpdw(port) (*((volatile uint32 *) (port))) -#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) -#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) -#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) - -#ifdef HAL_HWIO_EXTERNAL - -#undef __inp -#undef __inpw -#undef __inpdw -#undef __outp -#undef __outpw -#undef __outpdw - -#define __inp(port) __inp_extern(port) -#define __inpw(port) __inpw_extern(port) -#define __inpdw(port) __inpdw_extern(port) -#define __outp(port, val) __outp_extern(port, val) -#define __outpw(port, val) __outpw_extern(port, val) -#define __outpdw(port, val) __outpdw_extern(port, val) - -extern uint8 __inp_extern ( uint32 nAddr ); -extern uint16 __inpw_extern ( uint32 nAddr ); -extern uint32 __inpdw_extern ( uint32 nAddr ); -extern void __outp_extern ( uint32 nAddr, uint8 nData ); -extern void __outpw_extern ( uint32 nAddr, uint16 nData ); -extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); - -#endif - -#define in_byte(addr) (__inp(addr)) -#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) -#define out_byte(addr, val) __outp(addr,val) -#define out_byte_masked(io, mask, val, shadow) \ - HWIO_INTLOCK(); \ - out_byte( io, shadow); \ - shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ - HWIO_INTFREE() -#define out_byte_masked_ns(io, mask, val, current_reg_content) \ - out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ - ((uint16)((val) & (mask)))) ) - -#define in_word(addr) (__inpw(addr)) -#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) -#define out_word(addr, val) __outpw(addr,val) -#define out_word_masked(io, mask, val, shadow) \ - HWIO_INTLOCK( ); \ - shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ - out_word( io, shadow); \ - HWIO_INTFREE( ) -#define out_word_masked_ns(io, mask, val, current_reg_content) \ - out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ - ((uint16)((val) & (mask)))) ) - -#define in_dword(addr) (__inpdw(addr)) -#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) -#define out_dword(addr, val) __outpdw(addr,val) -#define out_dword_masked(io, mask, val, shadow) \ - HWIO_INTLOCK(); \ - shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ - out_dword( io, shadow); \ - HWIO_INTFREE() -#define out_dword_masked_ns(io, mask, val, current_reg_content) \ - out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ - ((uint32)((val) & (mask)))) ) - -#endif - diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/ack_report.h b/drivers/staging/fw-api/hw/wcn8750/v1/ack_report.h deleted file mode 100644 index e78921b308fd..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/ack_report.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _ACK_REPORT_H_ -#define _ACK_REPORT_H_ - -#define NUM_OF_DWORDS_ACK_REPORT 1 - -struct ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t selfgen_response_reason : 4, - ax_trigger_type : 4, - sr_ppdu : 1, - reserved : 7, - frame_control : 16; -#else - uint32_t frame_control : 16, - reserved : 7, - sr_ppdu : 1, - ax_trigger_type : 4, - selfgen_response_reason : 4; -#endif -}; - -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f - -#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 -#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 -#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 -#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 - -#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 -#define ACK_REPORT_SR_PPDU_LSB 8 -#define ACK_REPORT_SR_PPDU_MSB 8 -#define ACK_REPORT_SR_PPDU_MASK 0x00000100 - -#define ACK_REPORT_RESERVED_OFFSET 0x00000000 -#define ACK_REPORT_RESERVED_LSB 9 -#define ACK_REPORT_RESERVED_MSB 15 -#define ACK_REPORT_RESERVED_MASK 0x0000fe00 - -#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 -#define ACK_REPORT_FRAME_CONTROL_LSB 16 -#define ACK_REPORT_FRAME_CONTROL_MSB 31 -#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/boron_top_reg.h b/drivers/staging/fw-api/hw/wcn8750/v1/boron_top_reg.h deleted file mode 100644 index 306398284fe3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/boron_top_reg.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef BORON_TOP_REG_H -#define BORON_TOP_REG_H - -#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C) -#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050) - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/buffer_addr_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/buffer_addr_info.h deleted file mode 100644 index d65375b54715..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/buffer_addr_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _BUFFER_ADDR_INFO_H_ -#define _BUFFER_ADDR_INFO_H_ - -#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 - -struct buffer_addr_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_addr_31_0 : 32; - uint32_t buffer_addr_39_32 : 8, - return_buffer_manager : 4, - sw_buffer_cookie : 20; -#else - uint32_t buffer_addr_31_0 : 32; - uint32_t sw_buffer_cookie : 20, - return_buffer_manager : 4, - buffer_addr_39_32 : 8; -#endif -}; - -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/ce_src_desc.h b/drivers/staging/fw-api/hw/wcn8750/v1/ce_src_desc.h deleted file mode 100644 index 4ecaedcab2a7..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/ce_src_desc.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _CE_SRC_DESC_H_ -#define _CE_SRC_DESC_H_ - -#define NUM_OF_DWORDS_CE_SRC_DESC 4 - -struct ce_src_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t src_buffer_low : 32; - uint32_t src_buffer_high : 8, - toeplitz_en : 1, - src_swap : 1, - dest_swap : 1, - gather : 1, - ce_res_0 : 1, - barrier_read : 1, - ce_res_1 : 2, - length : 16; - uint32_t fw_metadata : 16, - ce_res_2 : 16; - uint32_t ce_res_3 : 20, - ring_id : 8, - looping_count : 4; -#else - uint32_t src_buffer_low : 32; - uint32_t length : 16, - ce_res_1 : 2, - barrier_read : 1, - ce_res_0 : 1, - gather : 1, - dest_swap : 1, - src_swap : 1, - toeplitz_en : 1, - src_buffer_high : 8; - uint32_t ce_res_2 : 16, - fw_metadata : 16; - uint32_t looping_count : 4, - ring_id : 8, - ce_res_3 : 20; -#endif -}; - -#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000 -#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0 -#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31 -#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff - -#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff - -#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004 -#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8 -#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8 -#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100 - -#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004 -#define CE_SRC_DESC_SRC_SWAP_LSB 9 -#define CE_SRC_DESC_SRC_SWAP_MSB 9 -#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200 - -#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004 -#define CE_SRC_DESC_DEST_SWAP_LSB 10 -#define CE_SRC_DESC_DEST_SWAP_MSB 10 -#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400 - -#define CE_SRC_DESC_GATHER_OFFSET 0x00000004 -#define CE_SRC_DESC_GATHER_LSB 11 -#define CE_SRC_DESC_GATHER_MSB 11 -#define CE_SRC_DESC_GATHER_MASK 0x00000800 - -#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004 -#define CE_SRC_DESC_CE_RES_0_LSB 12 -#define CE_SRC_DESC_CE_RES_0_MSB 12 -#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000 - -#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004 -#define CE_SRC_DESC_BARRIER_READ_LSB 13 -#define CE_SRC_DESC_BARRIER_READ_MSB 13 -#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000 - -#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004 -#define CE_SRC_DESC_CE_RES_1_LSB 14 -#define CE_SRC_DESC_CE_RES_1_MSB 15 -#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000 - -#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004 -#define CE_SRC_DESC_LENGTH_LSB 16 -#define CE_SRC_DESC_LENGTH_MSB 31 -#define CE_SRC_DESC_LENGTH_MASK 0xffff0000 - -#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008 -#define CE_SRC_DESC_FW_METADATA_LSB 0 -#define CE_SRC_DESC_FW_METADATA_MSB 15 -#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff - -#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008 -#define CE_SRC_DESC_CE_RES_2_LSB 16 -#define CE_SRC_DESC_CE_RES_2_MSB 31 -#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000 - -#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c -#define CE_SRC_DESC_CE_RES_3_LSB 0 -#define CE_SRC_DESC_CE_RES_3_MSB 19 -#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff - -#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c -#define CE_SRC_DESC_RING_ID_LSB 20 -#define CE_SRC_DESC_RING_ID_MSB 27 -#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000 - -#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c -#define CE_SRC_DESC_LOOPING_COUNT_LSB 28 -#define CE_SRC_DESC_LOOPING_COUNT_MSB 31 -#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/ce_stat_desc.h b/drivers/staging/fw-api/hw/wcn8750/v1/ce_stat_desc.h deleted file mode 100644 index 0b9f9a221215..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/ce_stat_desc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _CE_STAT_DESC_H_ -#define _CE_STAT_DESC_H_ - -#define NUM_OF_DWORDS_CE_STAT_DESC 4 - -struct ce_stat_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ce_res_5 : 8, - toeplitz_en : 1, - src_swap : 1, - dest_swap : 1, - gather : 1, - barrier_read : 1, - ce_res_6 : 3, - length : 16; - uint32_t toeplitz_hash_0 : 32; - uint32_t toeplitz_hash_1 : 32; - uint32_t fw_metadata : 16, - ce_res_7 : 4, - ring_id : 8, - looping_count : 4; -#else - uint32_t length : 16, - ce_res_6 : 3, - barrier_read : 1, - gather : 1, - dest_swap : 1, - src_swap : 1, - toeplitz_en : 1, - ce_res_5 : 8; - uint32_t toeplitz_hash_0 : 32; - uint32_t toeplitz_hash_1 : 32; - uint32_t looping_count : 4, - ring_id : 8, - ce_res_7 : 4, - fw_metadata : 16; -#endif -}; - -#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000 -#define CE_STAT_DESC_CE_RES_5_LSB 0 -#define CE_STAT_DESC_CE_RES_5_MSB 7 -#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff - -#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000 -#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8 -#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8 -#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100 - -#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000 -#define CE_STAT_DESC_SRC_SWAP_LSB 9 -#define CE_STAT_DESC_SRC_SWAP_MSB 9 -#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200 - -#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000 -#define CE_STAT_DESC_DEST_SWAP_LSB 10 -#define CE_STAT_DESC_DEST_SWAP_MSB 10 -#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400 - -#define CE_STAT_DESC_GATHER_OFFSET 0x00000000 -#define CE_STAT_DESC_GATHER_LSB 11 -#define CE_STAT_DESC_GATHER_MSB 11 -#define CE_STAT_DESC_GATHER_MASK 0x00000800 - -#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000 -#define CE_STAT_DESC_BARRIER_READ_LSB 12 -#define CE_STAT_DESC_BARRIER_READ_MSB 12 -#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000 - -#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000 -#define CE_STAT_DESC_CE_RES_6_LSB 13 -#define CE_STAT_DESC_CE_RES_6_MSB 15 -#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000 - -#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000 -#define CE_STAT_DESC_LENGTH_LSB 16 -#define CE_STAT_DESC_LENGTH_MSB 31 -#define CE_STAT_DESC_LENGTH_MASK 0xffff0000 - -#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff - -#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff - -#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c -#define CE_STAT_DESC_FW_METADATA_LSB 0 -#define CE_STAT_DESC_FW_METADATA_MSB 15 -#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff - -#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c -#define CE_STAT_DESC_CE_RES_7_LSB 16 -#define CE_STAT_DESC_CE_RES_7_MSB 19 -#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000 - -#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c -#define CE_STAT_DESC_RING_ID_LSB 20 -#define CE_STAT_DESC_RING_ID_MSB 27 -#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000 - -#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c -#define CE_STAT_DESC_LOOPING_COUNT_LSB 28 -#define CE_STAT_DESC_LOOPING_COUNT_MSB 31 -#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/coex_rx_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/coex_rx_status.h deleted file mode 100644 index 7d9c6b4d2057..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/coex_rx_status.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_RX_STATUS_H_ -#define _COEX_RX_STATUS_H_ - -#define NUM_OF_DWORDS_COEX_RX_STATUS 2 - -#define NUM_OF_QWORDS_COEX_RX_STATUS 1 - -struct coex_rx_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_mac_frame_status : 2, - rx_with_tx_response : 1, - rx_rate : 5, - rx_bw : 3, - single_mpdu : 1, - filter_status : 1, - ampdu : 1, - directed : 1, - reserved_0 : 1, - rx_nss : 3, - rx_rssi : 8, - rx_type : 3, - retry_bit_setting : 1, - more_data_bit_setting : 1; - uint32_t remain_rx_packet_time : 16, - rx_remaining_fes_time : 16; -#else - uint32_t more_data_bit_setting : 1, - retry_bit_setting : 1, - rx_type : 3, - rx_rssi : 8, - rx_nss : 3, - reserved_0 : 1, - directed : 1, - ampdu : 1, - filter_status : 1, - single_mpdu : 1, - rx_bw : 3, - rx_rate : 5, - rx_with_tx_response : 1, - rx_mac_frame_status : 2; - uint32_t rx_remaining_fes_time : 16, - remain_rx_packet_time : 16; -#endif -}; - -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 - -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 - -#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_RATE_LSB 3 -#define COEX_RX_STATUS_RX_RATE_MSB 7 -#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 - -#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_BW_LSB 8 -#define COEX_RX_STATUS_RX_BW_MSB 10 -#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 - -#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 -#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 -#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 - -#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 -#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 -#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 - -#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_AMPDU_LSB 13 -#define COEX_RX_STATUS_AMPDU_MSB 13 -#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 - -#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_DIRECTED_LSB 14 -#define COEX_RX_STATUS_DIRECTED_MSB 14 -#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 - -#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RESERVED_0_LSB 15 -#define COEX_RX_STATUS_RESERVED_0_MSB 15 -#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 - -#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_NSS_LSB 16 -#define COEX_RX_STATUS_RX_NSS_MSB 18 -#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 - -#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_RSSI_LSB 19 -#define COEX_RX_STATUS_RX_RSSI_MSB 26 -#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 - -#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_TYPE_LSB 27 -#define COEX_RX_STATUS_RX_TYPE_MSB 29 -#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 - -#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 - -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 - -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 - -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_req.h b/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_req.h deleted file mode 100644 index ed5b4c57bfd8..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_req.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_TX_REQ_H_ -#define _COEX_TX_REQ_H_ - -#define NUM_OF_DWORDS_COEX_TX_REQ 6 - -#define NUM_OF_QWORDS_COEX_TX_REQ 3 - -struct coex_tx_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_pwr : 8, - min_tx_pwr : 8, - nss : 3, - tx_chain_mask : 8, - bw : 3, - reserved_0 : 2; - uint32_t alt_tx_pwr : 8, - alt_min_tx_pwr : 8, - alt_nss : 3, - alt_tx_chain_mask : 8, - alt_bw : 3, - reserved_1 : 2; - uint32_t tx_pwr_1 : 8, - alt_tx_pwr_1 : 8, - wlan_request_duration : 16; - uint32_t wlan_pkt_type : 4, - coex_tx_reason : 2, - response_frame_type : 5, - wlan_low_priority_slicing_allowed : 1, - wlan_high_priority_slicing_allowed : 1, - sch_tx_burst_ongoing : 1, - coex_tx_priority : 4, - blackout_details_en : 1, - blackout_peek_duration : 8, - reserved_3a : 5; - uint32_t frequency_channel_bonding_mask : 16, - num_blackout_windows : 8, - reserved_4a : 8; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0 : 2, - bw : 3, - tx_chain_mask : 8, - nss : 3, - min_tx_pwr : 8, - tx_pwr : 8; - uint32_t reserved_1 : 2, - alt_bw : 3, - alt_tx_chain_mask : 8, - alt_nss : 3, - alt_min_tx_pwr : 8, - alt_tx_pwr : 8; - uint32_t wlan_request_duration : 16, - alt_tx_pwr_1 : 8, - tx_pwr_1 : 8; - uint32_t reserved_3a : 5, - blackout_peek_duration : 8, - blackout_details_en : 1, - coex_tx_priority : 4, - sch_tx_burst_ongoing : 1, - wlan_high_priority_slicing_allowed : 1, - wlan_low_priority_slicing_allowed : 1, - response_frame_type : 5, - coex_tx_reason : 2, - wlan_pkt_type : 4; - uint32_t reserved_4a : 8, - num_blackout_windows : 8, - frequency_channel_bonding_mask : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_TX_PWR_LSB 0 -#define COEX_TX_REQ_TX_PWR_MSB 7 -#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff - -#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 -#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 -#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_NSS_LSB 16 -#define COEX_TX_REQ_NSS_MSB 18 -#define COEX_TX_REQ_NSS_MASK 0x0000000000070000 - -#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 -#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 -#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_BW_LSB 27 -#define COEX_TX_REQ_BW_MSB 29 -#define COEX_TX_REQ_BW_MASK 0x0000000038000000 - -#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_RESERVED_0_LSB 30 -#define COEX_TX_REQ_RESERVED_0_MSB 31 -#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000 - -#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_TX_PWR_LSB 32 -#define COEX_TX_REQ_ALT_TX_PWR_MSB 39 -#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_NSS_LSB 48 -#define COEX_TX_REQ_ALT_NSS_MSB 50 -#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000 - -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_BW_LSB 59 -#define COEX_TX_REQ_ALT_BW_MSB 61 -#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000 - -#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_RESERVED_1_LSB 62 -#define COEX_TX_REQ_RESERVED_1_MSB 63 -#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000 - -#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_TX_PWR_1_LSB 0 -#define COEX_TX_REQ_TX_PWR_1_MSB 7 -#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff - -#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 -#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 -#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00 - -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000 - -#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32 -#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35 -#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000 - -#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_COEX_TX_REASON_LSB 36 -#define COEX_TX_REQ_COEX_TX_REASON_MSB 37 -#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000 - -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000 - -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000 - -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000 - -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000 - -#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46 -#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49 -#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000 - -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_LSB 50 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MSB 50 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MASK 0x0004000000000000 - -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_LSB 51 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MSB 58 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MASK 0x07f8000000000000 - -#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_RESERVED_3A_LSB 59 -#define COEX_TX_REQ_RESERVED_3A_MSB 63 -#define COEX_TX_REQ_RESERVED_3A_MASK 0xf800000000000000 - -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_LSB 0 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MSB 15 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MASK 0x000000000000ffff - -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_LSB 16 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MSB 23 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MASK 0x0000000000ff0000 - -#define COEX_TX_REQ_RESERVED_4A_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_RESERVED_4A_LSB 24 -#define COEX_TX_REQ_RESERVED_4A_MSB 31 -#define COEX_TX_REQ_RESERVED_4A_MASK 0x00000000ff000000 - -#define COEX_TX_REQ_TLV64_PADDING_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_TLV64_PADDING_LSB 32 -#define COEX_TX_REQ_TLV64_PADDING_MSB 63 -#define COEX_TX_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_status.h deleted file mode 100644 index c47c29c2a5ba..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_status.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_TX_STATUS_H_ -#define _COEX_TX_STATUS_H_ - -#define NUM_OF_DWORDS_COEX_TX_STATUS 4 - -#define NUM_OF_QWORDS_COEX_TX_STATUS 2 - -struct coex_tx_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 7, - tx_bw : 3, - tx_status_reason : 3, - tx_wait_ack : 1, - fes_tx_is_gen_frame : 1, - sch_tx_burst_ongoing : 1, - current_tx_duration : 16; - uint32_t next_rx_active_time : 16, - remaining_fes_time : 16; - uint32_t tx_antenna_mask : 8, - shared_ant_tx_pwr : 8, - other_ant_tx_pwr : 8, - reserved_2 : 8; - uint32_t tlv64_padding : 32; -#else - uint32_t current_tx_duration : 16, - sch_tx_burst_ongoing : 1, - fes_tx_is_gen_frame : 1, - tx_wait_ack : 1, - tx_status_reason : 3, - tx_bw : 3, - reserved_0a : 7; - uint32_t remaining_fes_time : 16, - next_rx_active_time : 16; - uint32_t reserved_2 : 8, - other_ant_tx_pwr : 8, - shared_ant_tx_pwr : 8, - tx_antenna_mask : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_RESERVED_0A_LSB 0 -#define COEX_TX_STATUS_RESERVED_0A_MSB 6 -#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f - -#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_BW_LSB 7 -#define COEX_TX_STATUS_TX_BW_MSB 9 -#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 - -#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 -#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 -#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 - -#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 -#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 -#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 - -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 - -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 - -#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 - -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 - -#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 -#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 -#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 - -#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff - -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 - -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 - -#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_RESERVED_2_LSB 24 -#define COEX_TX_STATUS_RESERVED_2_MSB 31 -#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 - -#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_TLV64_PADDING_LSB 32 -#define COEX_TX_STATUS_TLV64_PADDING_MSB 63 -#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/com_dtypes.h b/drivers/staging/fw-api/hw/wcn8750/v1/com_dtypes.h deleted file mode 100644 index aa7bf7a51845..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/com_dtypes.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef COM_DTYPES_H -#define COM_DTYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef T_WINNT - #ifndef WIN32 - #define WIN32 - #endif - #include -#endif - -#ifdef TRUE -#undef TRUE -#endif - -#ifdef FALSE -#undef FALSE -#endif - -#define TRUE 1 -#define FALSE 0 - -#define ON 1 -#define OFF 0 - -#ifndef NULL - #define NULL 0 -#endif - -#ifndef _ARM_ASM_ -#ifndef _BOOLEAN_DEFINED - -typedef unsigned char boolean; -#define _BOOLEAN_DEFINED -#endif - -#if defined(DALSTDDEF_H) -#define _BOOLEAN_DEFINED -#define _UINT32_DEFINED -#define _UINT16_DEFINED -#define _UINT8_DEFINED -#define _INT32_DEFINED -#define _INT16_DEFINED -#define _INT8_DEFINED -#define _UINT64_DEFINED -#define _INT64_DEFINED -#define _BYTE_DEFINED -#endif - -#ifndef _UINT32_DEFINED - -typedef unsigned int uint32; -#define _UINT32_DEFINED -#endif - -#ifndef _UINT16_DEFINED - -typedef unsigned short uint16; -#define _UINT16_DEFINED -#endif - -#ifndef _UINT8_DEFINED - -typedef unsigned char uint8; -#define _UINT8_DEFINED -#endif - -#ifndef _INT32_DEFINED - -typedef signed int int32; -#define _INT32_DEFINED -#endif - -#ifndef _INT16_DEFINED - -typedef signed short int16; -#define _INT16_DEFINED -#endif - -#ifndef _INT8_DEFINED - -typedef signed char int8; -#define _INT8_DEFINED -#endif - -#ifndef _BYTE_DEFINED - -typedef unsigned char byte; -#define _BYTE_DEFINED -#endif - -typedef unsigned short word; - -typedef unsigned long dword; - -typedef unsigned char uint1; - -typedef unsigned short uint2; - -typedef unsigned long uint4; - -typedef signed char int1; - -typedef signed short int2; - -typedef long int int4; - -typedef signed long sint31; - -typedef signed short sint15; - -typedef signed char sint7; - -typedef uint16 UWord16 ; -typedef uint32 UWord32 ; -typedef int32 Word32 ; -typedef int16 Word16 ; -typedef uint8 UWord8 ; -typedef int8 Word8 ; -typedef int32 Vect32 ; - -#if (! defined T_WINNT) && (! defined __GNUC__) - - #ifndef _INT64_DEFINED - - typedef long long int64; - #define _INT64_DEFINED - #endif - #ifndef _UINT64_DEFINED - - typedef unsigned long long uint64; - #define _UINT64_DEFINED - #endif -#else - - #if (defined __GNUC__) - #ifndef _INT64_DEFINED - typedef long long int64; - #define _INT64_DEFINED - #endif - #ifndef _UINT64_DEFINED - typedef unsigned long long uint64; - #define _UINT64_DEFINED - #endif - #else - typedef __int64 int64; - #ifndef _UINT64_DEFINED - typedef unsigned __int64 uint64; - #define _UINT64_DEFINED - #endif - #endif -#endif - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h deleted file mode 100644 index c9e20d75e648..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ -#define _EHT_SIG_USR_MU_MIMO_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 - -struct eht_sig_usr_mu_mimo_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - sta_coding : 1, - sta_spatial_config : 6, - reserved_0a : 1, - rx_integrity_check_passed : 1, - subband80_cc_mask : 8; - uint32_t user_order_subband80_0 : 8, - user_order_subband80_1 : 8, - user_order_subband80_2 : 8, - user_order_subband80_3 : 8; -#else - uint32_t subband80_cc_mask : 8, - rx_integrity_check_passed : 1, - reserved_0a : 1, - sta_spatial_config : 6, - sta_coding : 1, - sta_mcs : 4, - sta_id : 11; - uint32_t user_order_subband80_3 : 8, - user_order_subband80_2 : 8, - user_order_subband80_1 : 8, - user_order_subband80_0 : 8; -#endif -}; - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 - -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 - -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 - -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_ofdma_info.h deleted file mode 100644 index f2520cccfde9..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_ofdma_info.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ -#define _EHT_SIG_USR_OFDMA_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 - -struct eht_sig_usr_ofdma_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - validate_0a : 1, - nss : 4, - txbf : 1, - sta_coding : 1, - reserved_0b : 1, - rx_integrity_check_passed : 1, - subband80_cc_mask : 8; - uint32_t user_order_subband80_0 : 8, - user_order_subband80_1 : 8, - user_order_subband80_2 : 8, - user_order_subband80_3 : 8; -#else - uint32_t subband80_cc_mask : 8, - rx_integrity_check_passed : 1, - reserved_0b : 1, - sta_coding : 1, - txbf : 1, - nss : 4, - validate_0a : 1, - sta_mcs : 4, - sta_id : 11; - uint32_t user_order_subband80_3 : 8, - user_order_subband80_2 : 8, - user_order_subband80_1 : 8, - user_order_subband80_0 : 8; -#endif -}; - -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 - -#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 -#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 -#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 - -#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 - -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 - -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 - -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 - -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_su_info.h deleted file mode 100644 index 208cb4de0539..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_su_info.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_SU_INFO_H_ -#define _EHT_SIG_USR_SU_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 - -struct eht_sig_usr_su_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - validate_0a : 1, - nss : 4, - txbf : 1, - sta_coding : 1, - reserved_0b : 9, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0b : 9, - sta_coding : 1, - txbf : 1, - nss : 4, - validate_0a : 1, - sta_mcs : 4, - sta_id : 11; -#endif -}; - -#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 - -#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 -#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 -#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 - -#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 -#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 -#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 - -#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 -#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 -#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 - -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 - -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/expected_response.h b/drivers/staging/fw-api/hw/wcn8750/v1/expected_response.h deleted file mode 100644 index 0ef831133865..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/expected_response.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EXPECTED_RESPONSE_H_ -#define _EXPECTED_RESPONSE_H_ - -#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 - -#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 - -struct expected_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_ad2_31_0 : 32; - uint32_t tx_ad2_47_32 : 16, - expected_response_type : 5, - response_to_response : 3, - su_ba_user_number : 1, - response_info_part2_required : 1, - transmitted_bssid_check_en : 1, - eht___reserved_g_0005_ndp_expected : 1, - reserved_1 : 4; - uint32_t ndp_sta_partial_aid_2_8_0 : 11, - reserved_2 : 10, - ndp_sta_partial_aid1_8_0 : 11; - uint32_t ast_index : 16, - capture_ack_ba_sounding : 1, - capture_sounding_1str_20mhz : 1, - capture_sounding_1str_40mhz : 1, - capture_sounding_1str_80mhz : 1, - capture_sounding_1str_160mhz : 1, - capture_sounding_1str_240mhz : 1, - capture_sounding_1str_320mhz : 1, - reserved_3a : 9; - uint32_t fcs : 9, - expect_rx_with_blackout_details : 1, - crc : 4, - scrambler_seed : 7, - reserved_4b : 11; - uint32_t tlv64_padding : 32; -#else - uint32_t tx_ad2_31_0 : 32; - uint32_t reserved_1 : 4, - eht___reserved_g_0005_ndp_expected : 1, - transmitted_bssid_check_en : 1, - response_info_part2_required : 1, - su_ba_user_number : 1, - response_to_response : 3, - expected_response_type : 5, - tx_ad2_47_32 : 16; - uint32_t ndp_sta_partial_aid1_8_0 : 11, - reserved_2 : 10, - ndp_sta_partial_aid_2_8_0 : 11; - uint32_t reserved_3a : 9, - capture_sounding_1str_320mhz : 1, - capture_sounding_1str_240mhz : 1, - capture_sounding_1str_160mhz : 1, - capture_sounding_1str_80mhz : 1, - capture_sounding_1str_40mhz : 1, - capture_sounding_1str_20mhz : 1, - capture_ack_ba_sounding : 1, - ast_index : 16; - uint32_t reserved_4b : 11, - scrambler_seed : 7, - crc : 4, - expect_rx_with_blackout_details : 1, - fcs : 9; - uint32_t tlv64_padding : 32; -#endif -}; - -#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 -#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 -#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff - -#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 -#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 -#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 - -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 - -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 - -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 - -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 - -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 - -#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESERVED_1_LSB 60 -#define EXPECTED_RESPONSE_RESERVED_1_MSB 63 -#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf000000000000000 - -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff - -#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 -#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 -#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 - -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 - -#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_AST_INDEX_LSB 32 -#define EXPECTED_RESPONSE_AST_INDEX_MSB 47 -#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 - -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 - -#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 -#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 -#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 - -#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_FCS_LSB 0 -#define EXPECTED_RESPONSE_FCS_MSB 8 -#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff - -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB 9 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB 9 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK 0x0000000000000200 - -#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_CRC_LSB 10 -#define EXPECTED_RESPONSE_CRC_MSB 13 -#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 - -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 - -#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 -#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 -#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 - -#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 -#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 -#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_dl_info.h deleted file mode 100644 index 84571eb65d3b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_dl_info.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_MU_DL_INFO_H_ -#define _HE_SIG_A_MU_DL_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 - -struct he_sig_a_mu_dl_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dl_ul_flag : 1, - mcs_of_sig_b : 3, - dcm_of_sig_b : 1, - bss_color_id : 6, - spatial_reuse : 4, - transmit_bw : 3, - num_sig_b_symbols : 4, - comp_mode_sig_b : 1, - cp_ltf_size : 2, - doppler_indication : 1, - reserved_0a : 6; - uint32_t txop_duration : 7, - reserved_1a : 1, - num_ltf_symbols : 3, - ldpc_extra_symbol : 1, - stbc : 1, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - crc : 4, - tail : 6, - reserved_1b : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0a : 6, - doppler_indication : 1, - cp_ltf_size : 2, - comp_mode_sig_b : 1, - num_sig_b_symbols : 4, - transmit_bw : 3, - spatial_reuse : 4, - bss_color_id : 6, - dcm_of_sig_b : 1, - mcs_of_sig_b : 3, - dl_ul_flag : 1; - uint32_t rx_integrity_check_passed : 1, - reserved_1b : 5, - tail : 6, - crc : 4, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - stbc : 1, - ldpc_extra_symbol : 1, - num_ltf_symbols : 3, - reserved_1a : 1, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 - -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e - -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 - -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 - -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 - -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 - -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 - -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 - -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 - -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 - -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 - -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 - -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 - -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 - -#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 -#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 -#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 - -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 - -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 - -#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 -#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 -#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 -#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 -#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 - -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_ul_info.h deleted file mode 100644 index e2d0ad73a66c..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_ul_info.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_MU_UL_INFO_H_ -#define _HE_SIG_A_MU_UL_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 - -struct he_sig_a_mu_ul_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t format_indication : 1, - bss_color_id : 6, - spatial_reuse : 16, - reserved_0a : 1, - transmit_bw : 2, - reserved_0b : 6; - uint32_t txop_duration : 7, - reserved_1a : 9, - crc : 4, - tail : 6, - reserved_1b : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0b : 6, - transmit_bw : 2, - reserved_0a : 1, - spatial_reuse : 16, - bss_color_id : 6, - format_indication : 1; - uint32_t rx_integrity_check_passed : 1, - reserved_1b : 5, - tail : 6, - crc : 4, - reserved_1a : 9, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 - -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e - -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 - -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 - -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 - -#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 -#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 -#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 -#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 -#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 - -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_su_info.h deleted file mode 100644 index e4be3671016e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_su_info.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_SU_INFO_H_ -#define _HE_SIG_A_SU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 - -struct he_sig_a_su_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t format_indication : 1, - beam_change : 1, - dl_ul_flag : 1, - transmit_mcs : 4, - dcm : 1, - bss_color_id : 6, - reserved_0a : 1, - spatial_reuse : 4, - transmit_bw : 2, - cp_ltf_size : 2, - nsts : 3, - reserved_0b : 6; - uint32_t txop_duration : 7, - coding : 1, - ldpc_extra_symbol : 1, - stbc : 1, - txbf : 1, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - reserved_1a : 1, - doppler_indication : 1, - crc : 4, - tail : 6, - dot11ax_su_extended : 1, - dot11ax_ext_ru_size : 3, - rx_ndp : 1, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0b : 6, - nsts : 3, - cp_ltf_size : 2, - transmit_bw : 2, - spatial_reuse : 4, - reserved_0a : 1, - bss_color_id : 6, - dcm : 1, - transmit_mcs : 4, - dl_ul_flag : 1, - beam_change : 1, - format_indication : 1; - uint32_t rx_integrity_check_passed : 1, - rx_ndp : 1, - dot11ax_ext_ru_size : 3, - dot11ax_su_extended : 1, - tail : 6, - crc : 4, - doppler_indication : 1, - reserved_1a : 1, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - txbf : 1, - stbc : 1, - ldpc_extra_symbol : 1, - coding : 1, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001 - -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002 - -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004 - -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078 - -#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_DCM_LSB 7 -#define HE_SIG_A_SU_INFO_DCM_MSB 7 -#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080 - -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00 - -#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000 - -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000 - -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000 - -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000 - -#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_NSTS_LSB 23 -#define HE_SIG_A_SU_INFO_NSTS_MSB 25 -#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000 - -#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26 -#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31 -#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000 - -#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_CODING_LSB 7 -#define HE_SIG_A_SU_INFO_CODING_MSB 7 -#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080 - -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100 - -#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_STBC_LSB 9 -#define HE_SIG_A_SU_INFO_STBC_MSB 9 -#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200 - -#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TXBF_LSB 10 -#define HE_SIG_A_SU_INFO_TXBF_MSB 10 -#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400 - -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 - -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 - -#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000 - -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000 - -#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_CRC_LSB 16 -#define HE_SIG_A_SU_INFO_CRC_MSB 19 -#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TAIL_LSB 20 -#define HE_SIG_A_SU_INFO_TAIL_MSB 25 -#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 - -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 - -#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30 -#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30 -#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000 - -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b1_mu_info.h deleted file mode 100644 index a248c3dc67b3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b1_mu_info.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B1_MU_INFO_H_ -#define _HE_SIG_B1_MU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 - -struct he_sig_b1_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_allocation : 8, - reserved_0 : 23, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0 : 23, - ru_allocation : 8; -#endif -}; - -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff - -#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 -#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 -#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 - -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_mu_info.h deleted file mode 100644 index 83d6f3bc843f..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_mu_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B2_MU_INFO_H_ -#define _HE_SIG_B2_MU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2 - -struct he_sig_b2_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_spatial_config : 4, - sta_mcs : 4, - reserved_set_to_1 : 1, - sta_coding : 1, - reserved_0a : 7, - nsts : 3, - rx_integrity_check_passed : 1; - uint32_t user_order : 8, - cc_mask : 8, - reserved_1a : 16; -#else - uint32_t rx_integrity_check_passed : 1, - nsts : 3, - reserved_0a : 7, - sta_coding : 1, - reserved_set_to_1 : 1, - sta_mcs : 4, - sta_spatial_config : 4, - sta_id : 11; - uint32_t reserved_1a : 16, - cc_mask : 8, - user_order : 8; -#endif -}; - -#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0 -#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10 -#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff - -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800 - -#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15 -#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18 -#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000 - -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000 - -#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20 -#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20 -#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000 - -#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000 - -#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_NSTS_LSB 28 -#define HE_SIG_B2_MU_INFO_NSTS_MSB 30 -#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000 - -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0 -#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7 -#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff - -#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8 -#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15 -#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00 - -#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_ofdma_info.h deleted file mode 100644 index 6357d216eb3a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_ofdma_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B2_OFDMA_INFO_H_ -#define _HE_SIG_B2_OFDMA_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 - -struct he_sig_b2_ofdma_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - nsts : 3, - txbf : 1, - sta_mcs : 4, - sta_dcm : 1, - sta_coding : 1, - reserved_0 : 10, - rx_integrity_check_passed : 1; - uint32_t user_order : 8, - cc_mask : 8, - reserved_1a : 16; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0 : 10, - sta_coding : 1, - sta_dcm : 1, - sta_mcs : 4, - txbf : 1, - nsts : 3, - sta_id : 11; - uint32_t reserved_1a : 16, - cc_mask : 8, - user_order : 8; -#endif -}; - -#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff - -#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 -#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 -#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 - -#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 -#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 -#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 - -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 - -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 - -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 - -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 - -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff - -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 - -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/ht_sig_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/ht_sig_info.h deleted file mode 100644 index d6a4a719e6e2..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/ht_sig_info.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HT_SIG_INFO_H_ -#define _HT_SIG_INFO_H_ - -#define NUM_OF_DWORDS_HT_SIG_INFO 2 - -struct ht_sig_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mcs : 7, - cbw : 1, - length : 16, - reserved_0 : 8; - uint32_t smoothing : 1, - not_sounding : 1, - ht_reserved : 1, - aggregation : 1, - stbc : 2, - fec_coding : 1, - short_gi : 1, - num_ext_sp_str : 2, - crc : 8, - signal_tail : 6, - reserved_1 : 7, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0 : 8, - length : 16, - cbw : 1, - mcs : 7; - uint32_t rx_integrity_check_passed : 1, - reserved_1 : 7, - signal_tail : 6, - crc : 8, - num_ext_sp_str : 2, - short_gi : 1, - fec_coding : 1, - stbc : 2, - aggregation : 1, - ht_reserved : 1, - not_sounding : 1, - smoothing : 1; -#endif -}; - -#define HT_SIG_INFO_MCS_OFFSET 0x00000000 -#define HT_SIG_INFO_MCS_LSB 0 -#define HT_SIG_INFO_MCS_MSB 6 -#define HT_SIG_INFO_MCS_MASK 0x0000007f - -#define HT_SIG_INFO_CBW_OFFSET 0x00000000 -#define HT_SIG_INFO_CBW_LSB 7 -#define HT_SIG_INFO_CBW_MSB 7 -#define HT_SIG_INFO_CBW_MASK 0x00000080 - -#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000 -#define HT_SIG_INFO_LENGTH_LSB 8 -#define HT_SIG_INFO_LENGTH_MSB 23 -#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00 - -#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000 -#define HT_SIG_INFO_RESERVED_0_LSB 24 -#define HT_SIG_INFO_RESERVED_0_MSB 31 -#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000 - -#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004 -#define HT_SIG_INFO_SMOOTHING_LSB 0 -#define HT_SIG_INFO_SMOOTHING_MSB 0 -#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001 - -#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004 -#define HT_SIG_INFO_NOT_SOUNDING_LSB 1 -#define HT_SIG_INFO_NOT_SOUNDING_MSB 1 -#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002 - -#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004 -#define HT_SIG_INFO_HT_RESERVED_LSB 2 -#define HT_SIG_INFO_HT_RESERVED_MSB 2 -#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004 - -#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004 -#define HT_SIG_INFO_AGGREGATION_LSB 3 -#define HT_SIG_INFO_AGGREGATION_MSB 3 -#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008 - -#define HT_SIG_INFO_STBC_OFFSET 0x00000004 -#define HT_SIG_INFO_STBC_LSB 4 -#define HT_SIG_INFO_STBC_MSB 5 -#define HT_SIG_INFO_STBC_MASK 0x00000030 - -#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004 -#define HT_SIG_INFO_FEC_CODING_LSB 6 -#define HT_SIG_INFO_FEC_CODING_MSB 6 -#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040 - -#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004 -#define HT_SIG_INFO_SHORT_GI_LSB 7 -#define HT_SIG_INFO_SHORT_GI_MSB 7 -#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080 - -#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004 -#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8 -#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9 -#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300 - -#define HT_SIG_INFO_CRC_OFFSET 0x00000004 -#define HT_SIG_INFO_CRC_LSB 10 -#define HT_SIG_INFO_CRC_MSB 17 -#define HT_SIG_INFO_CRC_MASK 0x0003fc00 - -#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004 -#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18 -#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23 -#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000 - -#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004 -#define HT_SIG_INFO_RESERVED_1_LSB 24 -#define HT_SIG_INFO_RESERVED_1_MSB 30 -#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000 - -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_a_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_a_info.h deleted file mode 100644 index 6da0725dfee7..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_a_info.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _L_SIG_A_INFO_H_ -#define _L_SIG_A_INFO_H_ - -#define NUM_OF_DWORDS_L_SIG_A_INFO 1 - -struct l_sig_a_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rate : 4, - lsig_reserved : 1, - length : 12, - parity : 1, - tail : 6, - pkt_type : 4, - captured_implicit_sounding : 1, - reserved : 2, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved : 2, - captured_implicit_sounding : 1, - pkt_type : 4, - tail : 6, - parity : 1, - length : 12, - lsig_reserved : 1, - rate : 4; -#endif -}; - -#define L_SIG_A_INFO_RATE_OFFSET 0x00000000 -#define L_SIG_A_INFO_RATE_LSB 0 -#define L_SIG_A_INFO_RATE_MSB 3 -#define L_SIG_A_INFO_RATE_MASK 0x0000000f - -#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000 -#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4 -#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4 -#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010 - -#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000 -#define L_SIG_A_INFO_LENGTH_LSB 5 -#define L_SIG_A_INFO_LENGTH_MSB 16 -#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0 - -#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000 -#define L_SIG_A_INFO_PARITY_LSB 17 -#define L_SIG_A_INFO_PARITY_MSB 17 -#define L_SIG_A_INFO_PARITY_MASK 0x00020000 - -#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000 -#define L_SIG_A_INFO_TAIL_LSB 18 -#define L_SIG_A_INFO_TAIL_MSB 23 -#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000 - -#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000 -#define L_SIG_A_INFO_PKT_TYPE_LSB 24 -#define L_SIG_A_INFO_PKT_TYPE_MSB 27 -#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000 - -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 - -#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000 -#define L_SIG_A_INFO_RESERVED_LSB 29 -#define L_SIG_A_INFO_RESERVED_MSB 30 -#define L_SIG_A_INFO_RESERVED_MASK 0x60000000 - -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_b_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_b_info.h deleted file mode 100644 index f2052702e2de..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_b_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _L_SIG_B_INFO_H_ -#define _L_SIG_B_INFO_H_ - -#define NUM_OF_DWORDS_L_SIG_B_INFO 1 - -struct l_sig_b_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rate : 4, - length : 12, - reserved : 15, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved : 15, - length : 12, - rate : 4; -#endif -}; - -#define L_SIG_B_INFO_RATE_OFFSET 0x00000000 -#define L_SIG_B_INFO_RATE_LSB 0 -#define L_SIG_B_INFO_RATE_MSB 3 -#define L_SIG_B_INFO_RATE_MASK 0x0000000f - -#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000 -#define L_SIG_B_INFO_LENGTH_LSB 4 -#define L_SIG_B_INFO_LENGTH_MSB 15 -#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0 - -#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000 -#define L_SIG_B_INFO_RESERVED_LSB 16 -#define L_SIG_B_INFO_RESERVED_MSB 30 -#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000 - -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/macrx_abort_request_info.h deleted file mode 100644 index 038f4038fa59..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/macrx_abort_request_info.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACRX_ABORT_REQUEST_INFO_H_ -#define _MACRX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 - -struct macrx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t macrx_abort_reason : 8, - reserved_0 : 8; -#else - uint16_t reserved_0 : 8, - macrx_abort_reason : 8; -#endif -}; - -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff - -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h deleted file mode 100644 index f29ca356a223..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ -#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ - -#include "eht_sig_usr_mu_mimo_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 - -struct mactx_eht_sig_usr_mu_mimo { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; -#else - struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; -#endif -}; - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h deleted file mode 100644 index 24bf6691978d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ -#define _MACTX_EHT_SIG_USR_OFDMA_H_ - -#include "eht_sig_usr_ofdma_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1 - -struct mactx_eht_sig_usr_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; -#else - struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; -#endif -}; - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_su.h deleted file mode 100644 index 1fb82723c1ff..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_su.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_SU_H_ -#define _MACTX_EHT_SIG_USR_SU_H_ - -#include "eht_sig_usr_su_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1 - -struct mactx_eht_sig_usr_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; - uint32_t tlv64_padding : 32; -#else - struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h deleted file mode 100644 index 438f3af6f9e7..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_MU_DL_H_ -#define _MACTX_HE_SIG_A_MU_DL_H_ - -#include "he_sig_a_mu_dl_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1 - -struct mactx_he_sig_a_mu_dl { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; -#else - struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h deleted file mode 100644 index 96d2b912665a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_MU_UL_H_ -#define _MACTX_HE_SIG_A_MU_UL_H_ - -#include "he_sig_a_mu_ul_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1 - -struct mactx_he_sig_a_mu_ul { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; -#else - struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_su.h deleted file mode 100644 index e51241d26559..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_su.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_SU_H_ -#define _MACTX_HE_SIG_A_SU_H_ - -#include "he_sig_a_su_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1 - -struct mactx_he_sig_a_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_su_info mactx_he_sig_a_su_info_details; -#else - struct he_sig_a_su_info mactx_he_sig_a_su_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b1_mu.h deleted file mode 100644 index 700528af2048..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b1_mu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B1_MU_H_ -#define _MACTX_HE_SIG_B1_MU_H_ - -#include "he_sig_b1_mu_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 - -struct mactx_he_sig_b1_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#else - struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_mu.h deleted file mode 100644 index ccc1c593fed6..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_mu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B2_MU_H_ -#define _MACTX_HE_SIG_B2_MU_H_ - -#include "he_sig_b2_mu_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1 - -struct mactx_he_sig_b2_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; -#else - struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; -#endif -}; - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h deleted file mode 100644 index afc3c4b22841..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ -#define _MACTX_HE_SIG_B2_OFDMA_H_ - -#include "he_sig_b2_ofdma_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1 - -struct mactx_he_sig_b2_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; -#else - struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; -#endif -}; - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_ht_sig.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_ht_sig.h deleted file mode 100644 index ec28824c590f..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_ht_sig.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HT_SIG_H_ -#define _MACTX_HT_SIG_H_ - -#include "ht_sig_info.h" -#define NUM_OF_DWORDS_MACTX_HT_SIG 2 - -#define NUM_OF_QWORDS_MACTX_HT_SIG 1 - -struct mactx_ht_sig { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ht_sig_info mactx_ht_sig_info_details; -#else - struct ht_sig_info mactx_ht_sig_info_details; -#endif -}; - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_a.h deleted file mode 100644 index 061e46e28a2c..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_a.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_L_SIG_A_H_ -#define _MACTX_L_SIG_A_H_ - -#include "l_sig_a_info.h" -#define NUM_OF_DWORDS_MACTX_L_SIG_A 2 - -#define NUM_OF_QWORDS_MACTX_L_SIG_A 1 - -struct mactx_l_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_a_info mactx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_a_info mactx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32 -#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63 -#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_b.h deleted file mode 100644 index 6d533acef675..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_b.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_L_SIG_B_H_ -#define _MACTX_L_SIG_B_H_ - -#include "l_sig_b_info.h" -#define NUM_OF_DWORDS_MACTX_L_SIG_B 2 - -#define NUM_OF_QWORDS_MACTX_L_SIG_B 1 - -struct mactx_l_sig_b { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_b_info mactx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_b_info mactx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32 -#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63 -#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_phy_desc.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_phy_desc.h deleted file mode 100644 index ee4ccdf65c28..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_phy_desc.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_PHY_DESC_H_ -#define _MACTX_PHY_DESC_H_ - -#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 - -#define NUM_OF_QWORDS_MACTX_PHY_DESC 2 - -struct mactx_phy_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 16, - bf_type : 2, - wait_sifs : 2, - dot11b_preamble_type : 1, - pkt_type : 4, - su_or_mu : 2, - mu_type : 1, - bandwidth : 3, - channel_capture : 1; - uint32_t mcs : 5, - global_ofdma_mimo_enable : 1, - stbc : 1, - dot11ax_su_extended : 1, - dot11ax_trigger_frame_embedded : 1, - tx_pwr_shared : 8, - tx_pwr_unshared : 8, - measure_power : 1, - tpc_glut_self_cal : 1, - back_to_back_transmission_expected : 1, - heavy_clip_nss : 3, - txbf_per_packet_no_csd_no_walsh : 1; - uint32_t ndp : 3, - ul_flag : 1, - triggered : 1, - ap_pkt_bw : 3, - ru_position_start : 8, - pcu_ppdu_setup_start_reason : 3, - tlv_source : 1, - reserved_2a : 1, - nss : 3, - stream_offset : 3, - reserved_2b : 2, - clpc_enable : 1, - mu_ndp : 1, - response_expected : 1; - uint32_t rx_chain_mask : 8, - rx_chain_mask_valid : 1, - ant_sel_valid : 1, - ant_sel : 1, - cp_setting : 2, - he_ppdu_subtype : 2, - active_channel : 3, - generate_phyrx_tx_start_timing : 1, - ltf_size : 2, - ru_size_updated_v2 : 4, - reserved_3c : 1, - u_sig_puncture_pattern_encoding : 6; -#else - uint32_t channel_capture : 1, - bandwidth : 3, - mu_type : 1, - su_or_mu : 2, - pkt_type : 4, - dot11b_preamble_type : 1, - wait_sifs : 2, - bf_type : 2, - reserved_0a : 16; - uint32_t txbf_per_packet_no_csd_no_walsh : 1, - heavy_clip_nss : 3, - back_to_back_transmission_expected : 1, - tpc_glut_self_cal : 1, - measure_power : 1, - tx_pwr_unshared : 8, - tx_pwr_shared : 8, - dot11ax_trigger_frame_embedded : 1, - dot11ax_su_extended : 1, - stbc : 1, - global_ofdma_mimo_enable : 1, - mcs : 5; - uint32_t response_expected : 1, - mu_ndp : 1, - clpc_enable : 1, - reserved_2b : 2, - stream_offset : 3, - nss : 3, - reserved_2a : 1, - tlv_source : 1, - pcu_ppdu_setup_start_reason : 3, - ru_position_start : 8, - ap_pkt_bw : 3, - triggered : 1, - ul_flag : 1, - ndp : 3; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_3c : 1, - ru_size_updated_v2 : 4, - ltf_size : 2, - generate_phyrx_tx_start_timing : 1, - active_channel : 3, - he_ppdu_subtype : 2, - cp_setting : 2, - ant_sel : 1, - ant_sel_valid : 1, - rx_chain_mask_valid : 1, - rx_chain_mask : 8; -#endif -}; - -#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 -#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 -#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff - -#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BF_TYPE_LSB 16 -#define MACTX_PHY_DESC_BF_TYPE_MSB 17 -#define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 - -#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 -#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 -#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 - -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 - -#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 -#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 -#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 - -#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 -#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 -#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 - -#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MU_TYPE_LSB 27 -#define MACTX_PHY_DESC_MU_TYPE_MSB 27 -#define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 - -#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 -#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 -#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 - -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 - -#define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MCS_LSB 32 -#define MACTX_PHY_DESC_MCS_MSB 36 -#define MACTX_PHY_DESC_MCS_MASK 0x0000001f00000000 - -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 37 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 37 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000002000000000 - -#define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_STBC_LSB 38 -#define MACTX_PHY_DESC_STBC_MSB 38 -#define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 - -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 - -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 - -#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 -#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 -#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 - -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 - -#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 -#define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 -#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 - -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 - -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 - -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 - -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 - -#define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_NDP_LSB 0 -#define MACTX_PHY_DESC_NDP_MSB 2 -#define MACTX_PHY_DESC_NDP_MASK 0x0000000000000007 - -#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_UL_FLAG_LSB 3 -#define MACTX_PHY_DESC_UL_FLAG_MSB 3 -#define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000008 - -#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_TRIGGERED_LSB 4 -#define MACTX_PHY_DESC_TRIGGERED_MSB 4 -#define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000010 - -#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_AP_PKT_BW_LSB 5 -#define MACTX_PHY_DESC_AP_PKT_BW_MSB 7 -#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000000000000e0 - -#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RU_POSITION_START_LSB 8 -#define MACTX_PHY_DESC_RU_POSITION_START_MSB 15 -#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x000000000000ff00 - -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 16 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 18 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000070000 - -#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_TLV_SOURCE_LSB 19 -#define MACTX_PHY_DESC_TLV_SOURCE_MSB 19 -#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000080000 - -#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_2A_LSB 20 -#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 -#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000100000 - -#define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_NSS_LSB 21 -#define MACTX_PHY_DESC_NSS_MSB 23 -#define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 - -#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 -#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 -#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 - -#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 -#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 -#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 - -#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 -#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 -#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 - -#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_MU_NDP_LSB 30 -#define MACTX_PHY_DESC_MU_NDP_MSB 30 -#define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 - -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 - -#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 - -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 - -#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 -#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 -#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 - -#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ANT_SEL_LSB 42 -#define MACTX_PHY_DESC_ANT_SEL_MSB 42 -#define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 - -#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_CP_SETTING_LSB 43 -#define MACTX_PHY_DESC_CP_SETTING_MSB 44 -#define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 - -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 - -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 - -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 - -#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_LTF_SIZE_LSB 51 -#define MACTX_PHY_DESC_LTF_SIZE_MSB 52 -#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 - -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 - -#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_3C_LSB 57 -#define MACTX_PHY_DESC_RESERVED_3C_MSB 57 -#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 - -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h deleted file mode 100644 index f46583e4c7ee..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ -#define _MACTX_U_SIG_EHT_SU_MU_H_ - -#include "u_sig_eht_su_mu_info.h" -#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 - -#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1 - -struct mactx_u_sig_eht_su_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; -#else - struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; -#endif -}; - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_tb.h deleted file mode 100644 index 5e57312a9da2..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_tb.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_U_SIG_EHT_TB_H_ -#define _MACTX_U_SIG_EHT_TB_H_ - -#include "u_sig_eht_tb_info.h" -#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 - -#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1 - -struct mactx_u_sig_eht_tb { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; -#else - struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; -#endif -}; - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_common.h deleted file mode 100644 index 04124271bbc9..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_common.h +++ /dev/null @@ -1,482 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_USER_DESC_COMMON_H_ -#define _MACTX_USER_DESC_COMMON_H_ - -#include "unallocated_ru_160_info.h" -#include "ru_allocation_160_info.h" -#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 - -#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 - -struct mactx_user_desc_common { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t num_users : 6, - reserved_0b : 5, - ltf_size : 2, - reserved_0c : 3, - he_stf_long : 1, - reserved_0d : 7, - num_users_he_sigb_band0 : 8; - uint32_t num_ltf_symbols : 3, - reserved_1a : 5, - num_users_he_sigb_band1 : 8, - reserved_1b : 16; - uint32_t packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - packet_extension : 3, - reserved : 2, - he_sigb_dcm : 1, - reserved_2b : 7, - he_sigb_compression : 1, - reserved_2c : 15; - uint32_t he_sigb_0_mcs : 3, - reserved_3a : 13, - num_he_sigb_sym : 5, - center_ru_0 : 1, - center_ru_1 : 1, - reserved_3b : 1, - ftm_en : 1, - pe_nss : 3, - pe_ltf_size : 2, - pe_content : 1, - pe_chain_csd_en : 1; - struct ru_allocation_160_info ru_allocation_0123_details; - struct ru_allocation_160_info ru_allocation_4567_details; - struct unallocated_ru_160_info ru_allocation_160_0_details; - struct unallocated_ru_160_info ru_allocation_160_1_details; - uint32_t num_data_symbols : 16, - ndp_ru_tone_set_index : 7, - ndp_feedback_status : 1, - doppler_indication : 1, - reserved_14a : 7; - uint32_t spatial_reuse : 16, - distributed_ru : 1, - dru_spreading_bw : 2, - reserved_15a : 13; -#else - uint32_t num_users_he_sigb_band0 : 8, - reserved_0d : 7, - he_stf_long : 1, - reserved_0c : 3, - ltf_size : 2, - reserved_0b : 5, - num_users : 6; - uint32_t reserved_1b : 16, - num_users_he_sigb_band1 : 8, - reserved_1a : 5, - num_ltf_symbols : 3; - uint32_t reserved_2c : 15, - he_sigb_compression : 1, - reserved_2b : 7, - he_sigb_dcm : 1, - reserved : 2, - packet_extension : 3, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2; - uint32_t pe_chain_csd_en : 1, - pe_content : 1, - pe_ltf_size : 2, - pe_nss : 3, - ftm_en : 1, - reserved_3b : 1, - center_ru_1 : 1, - center_ru_0 : 1, - num_he_sigb_sym : 5, - reserved_3a : 13, - he_sigb_0_mcs : 3; - struct ru_allocation_160_info ru_allocation_0123_details; - struct ru_allocation_160_info ru_allocation_4567_details; - struct unallocated_ru_160_info ru_allocation_160_0_details; - struct unallocated_ru_160_info ru_allocation_160_1_details; - uint32_t reserved_14a : 7, - doppler_indication : 1, - ndp_feedback_status : 1, - ndp_ru_tone_set_index : 7, - num_data_symbols : 16; - uint32_t reserved_15a : 13, - dru_spreading_bw : 2, - distributed_ru : 1, - spatial_reuse : 16; -#endif -}; - -#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 -#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 -#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f - -#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 - -#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 - -#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 - -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 - -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 - -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 - -#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 -#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 -#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 - -#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 - -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 - -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 - -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 - -#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 -#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 -#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 - -#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 -#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 -#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 - -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 - -#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 - -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 - -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff - -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 - -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 - -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 - -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_LSB 48 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MSB 48 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MASK 0x0001000000000000 - -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_LSB 49 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MSB 50 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MASK 0x0006000000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 51 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xfff8000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_per_user.h deleted file mode 100644 index a68b50d9d639..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_per_user.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_USER_DESC_PER_USER_H_ -#define _MACTX_USER_DESC_PER_USER_H_ - -#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 6 - -#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 3 - -struct mactx_user_desc_per_user { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t psdu_length : 24, - reserved_0a : 8; - uint32_t ru_start_index : 8, - ru_size : 4, - reserved_1b : 4, - ofdma_mu_mimo_enabled : 1, - nss : 3, - stream_offset : 3, - reserved_1c : 1, - mcs : 5, - dcm : 1, - reserved_1d : 2; - uint32_t fec_type : 1, - reserved_2a : 1, - qam_diff1 : 2, - qam_diff2 : 2, - qam_diff3 : 2, - user_bf_type : 2, - a_factor_ldpc2x : 2, - extra_sym_ldpc2x : 1, - cw_len_2x : 2, - reserved_2b : 1, - drop_user_cbf : 1, - a_factor_ldpc1x : 2, - extra_sym_ldpc1x : 1, - cw_len_1x : 2, - ldpc1x_used : 1, - ldpc2x_used : 1, - ldpc_extra_symbol : 1, - force_extra_symbol : 1, - ldpc_2x_codeword : 1, - reserved_2d : 5; - uint32_t sw_peer_id : 16, - per_user_subband_mask : 16; - uint32_t ldpc_num_avbits : 27, - reserved_4a : 5; - uint32_t num_cw_1x : 16, - num_cw_2x : 16; -#else - uint32_t reserved_0a : 8, - psdu_length : 24; - uint32_t reserved_1d : 2, - dcm : 1, - mcs : 5, - reserved_1c : 1, - stream_offset : 3, - nss : 3, - ofdma_mu_mimo_enabled : 1, - reserved_1b : 4, - ru_size : 4, - ru_start_index : 8; - uint32_t reserved_2d : 5, - ldpc_2x_codeword : 1, - force_extra_symbol : 1, - ldpc_extra_symbol : 1, - ldpc2x_used : 1, - ldpc1x_used : 1, - cw_len_1x : 2, - extra_sym_ldpc1x : 1, - a_factor_ldpc1x : 2, - drop_user_cbf : 1, - reserved_2b : 1, - cw_len_2x : 2, - extra_sym_ldpc2x : 1, - a_factor_ldpc2x : 2, - user_bf_type : 2, - qam_diff3 : 2, - qam_diff2 : 2, - qam_diff1 : 2, - reserved_2a : 1, - fec_type : 1; - uint32_t per_user_subband_mask : 16, - sw_peer_id : 16; - uint32_t reserved_4a : 5, - ldpc_num_avbits : 27; - uint32_t num_cw_2x : 16, - num_cw_1x : 16; -#endif -}; - -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff - -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000 - -#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000 - -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000 - -#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_NSS_LSB 49 -#define MACTX_USER_DESC_PER_USER_NSS_MSB 51 -#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000 - -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000 - -#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_MCS_LSB 56 -#define MACTX_USER_DESC_PER_USER_MCS_MSB 60 -#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x1f00000000000000 - -#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_DCM_LSB 61 -#define MACTX_USER_DESC_PER_USER_DCM_MSB 61 -#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x2000000000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 62 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xc000000000000000 - -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 1 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x0000000000000002 - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_LSB 2 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MSB 3 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MASK 0x000000000000000c - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_LSB 4 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MSB 5 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MASK 0x0000000000000030 - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_LSB 6 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MSB 7 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MASK 0x00000000000000c0 - -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300 - -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_LSB 10 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MSB 11 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MASK 0x0000000000000c00 - -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_LSB 12 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MSB 12 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MASK 0x0000000000001000 - -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_LSB 13 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MSB 14 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MASK 0x0000000000006000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 15 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x0000000000008000 - -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_LSB 17 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MSB 18 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MASK 0x0000000000060000 - -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_LSB 19 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MSB 19 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MASK 0x0000000000080000 - -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_LSB 20 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MSB 21 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MASK 0x0000000000300000 - -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_LSB 22 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MSB 22 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MASK 0x0000000000400000 - -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_LSB 23 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MSB 23 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MASK 0x0000000000800000 - -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000 - -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000 - -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_LSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MASK 0x0000000004000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 27 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000f8000000 - -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000 - -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_LSB 0 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MASK 0x0000000007ffffff - -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_LSB 27 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MASK 0x00000000f8000000 - -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_LSB 32 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MSB 47 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_LSB 48 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MSB 63 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_a.h deleted file mode 100644 index 6dec145785d6..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_a.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_A_H_ -#define _MACTX_VHT_SIG_A_H_ - -#include "vht_sig_a_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1 - -struct mactx_vht_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_a_info mactx_vht_sig_a_info_details; -#else - struct vht_sig_a_info mactx_vht_sig_a_info_details; -#endif -}; - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu160.h deleted file mode 100644 index b66278da930b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu160.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU160_H_ -#define _MACTX_VHT_SIG_B_MU160_H_ - -#include "vht_sig_b_mu160_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4 - -struct mactx_vht_sig_b_mu160 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; -#else - struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu20.h deleted file mode 100644 index 95feca30eaa3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu20.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU20_H_ -#define _MACTX_VHT_SIG_B_MU20_H_ - -#include "vht_sig_b_mu20_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1 - -struct mactx_vht_sig_b_mu20 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; - uint32_t tlv64_padding : 32; -#else - struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu40.h deleted file mode 100644 index c770db089203..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu40.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU40_H_ -#define _MACTX_VHT_SIG_B_MU40_H_ - -#include "vht_sig_b_mu40_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1 - -struct mactx_vht_sig_b_mu40 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; -#else - struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu80.h deleted file mode 100644 index 9e39d240b618..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu80.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU80_H_ -#define _MACTX_VHT_SIG_B_MU80_H_ - -#include "vht_sig_b_mu80_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2 - -struct mactx_vht_sig_b_mu80 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; -#else - struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su160.h deleted file mode 100644 index 01bc54e5ab89..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su160.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU160_H_ -#define _MACTX_VHT_SIG_B_SU160_H_ - -#include "vht_sig_b_su160_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4 - -struct mactx_vht_sig_b_su160 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; -#else - struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su20.h deleted file mode 100644 index c297cc0785e3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su20.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU20_H_ -#define _MACTX_VHT_SIG_B_SU20_H_ - -#include "vht_sig_b_su20_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1 - -struct mactx_vht_sig_b_su20 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; - uint32_t tlv64_padding : 32; -#else - struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su40.h deleted file mode 100644 index 002d72c430ca..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su40.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU40_H_ -#define _MACTX_VHT_SIG_B_SU40_H_ - -#include "vht_sig_b_su40_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1 - -struct mactx_vht_sig_b_su40 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; -#else - struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su80.h deleted file mode 100644 index b15646f03f4a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su80.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU80_H_ -#define _MACTX_VHT_SIG_B_SU80_H_ - -#include "vht_sig_b_su80_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2 - -struct mactx_vht_sig_b_su80 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; -#else - struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/mlo_sta_id_details.h deleted file mode 100644 index 952056890206..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mlo_sta_id_details.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MLO_STA_ID_DETAILS_H_ -#define _MLO_STA_ID_DETAILS_H_ - -#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 - -struct mlo_sta_id_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t nstr_mlo_sta_id : 10, - block_self_ml_sync : 1, - block_partner_ml_sync : 1, - nstr_mlo_sta_id_valid : 1, - reserved_0a : 3; -#else - uint16_t reserved_0a : 3, - nstr_mlo_sta_id_valid : 1, - block_partner_ml_sync : 1, - block_self_ml_sync : 1, - nstr_mlo_sta_id : 10; -#endif -}; - -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff - -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 - -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 - -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 - -#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 -#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 -#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mon_buffer_addr.h b/drivers/staging/fw-api/hw/wcn8750/v1/mon_buffer_addr.h deleted file mode 100644 index 8cb6f5fd57b9..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mon_buffer_addr.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_BUFFER_ADDR_H_ -#define _MON_BUFFER_ADDR_H_ - -#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 - -#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 - -struct mon_buffer_addr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t dma_length : 12, - reserved_2a : 4, - msdu_continuation : 1, - truncated : 1, - reserved_2b : 14; - uint32_t tlv64_padding : 32; -#else - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t reserved_2b : 14, - truncated : 1, - msdu_continuation : 1, - reserved_2a : 4, - dma_length : 12; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff - -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 - -#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 -#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 -#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff - -#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 -#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 -#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 - -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 - -#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 -#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 -#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 - -#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 -#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 -#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 - -#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 -#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 -#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mon_destination_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/mon_destination_ring.h deleted file mode 100644 index 1f373b585fd5..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mon_destination_ring.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_DESTINATION_RING_H_ -#define _MON_DESTINATION_RING_H_ - -#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 - -struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t stat_buf_virt_addr_31_0 : 32; - uint32_t stat_buf_virt_addr_63_32 : 32; - uint32_t ppdu_id : 32; - uint32_t end_offset : 12, - reserved_3a : 2, - link_info : 2, - end_reason : 2, - initiator : 1, - empty_descriptor : 1, - pkt_buffer_cnt : 8, - looping_count : 4; -#else - uint32_t stat_buf_virt_addr_31_0 : 32; - uint32_t stat_buf_virt_addr_63_32 : 32; - uint32_t ppdu_id : 32; - uint32_t looping_count : 4, - pkt_buffer_cnt : 8, - empty_descriptor : 1, - initiator : 1, - end_reason : 2, - link_info : 2, - reserved_3a : 2, - end_offset : 12; -#endif -}; - -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff - -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff - -#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 -#define MON_DESTINATION_RING_PPDU_ID_LSB 0 -#define MON_DESTINATION_RING_PPDU_ID_MSB 31 -#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff - -#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c -#define MON_DESTINATION_RING_END_OFFSET_LSB 0 -#define MON_DESTINATION_RING_END_OFFSET_MSB 11 -#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff - -#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c -#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 -#define MON_DESTINATION_RING_RESERVED_3A_MSB 13 -#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x00003000 - -#define MON_DESTINATION_RING_LINK_INFO_OFFSET 0x0000000c -#define MON_DESTINATION_RING_LINK_INFO_LSB 14 -#define MON_DESTINATION_RING_LINK_INFO_MSB 15 -#define MON_DESTINATION_RING_LINK_INFO_MASK 0x0000c000 - -#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c -#define MON_DESTINATION_RING_END_REASON_LSB 16 -#define MON_DESTINATION_RING_END_REASON_MSB 17 -#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 - -#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c -#define MON_DESTINATION_RING_INITIATOR_LSB 18 -#define MON_DESTINATION_RING_INITIATOR_MSB 18 -#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 - -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 - -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_OFFSET 0x0000000c -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_LSB 20 -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MSB 27 -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MASK 0x0ff00000 - -#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c -#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 -#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 -#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mon_drop.h b/drivers/staging/fw-api/hw/wcn8750/v1/mon_drop.h deleted file mode 100644 index d1135ecd0dc2..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mon_drop.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_DROP_H_ -#define _MON_DROP_H_ - -#define NUM_OF_DWORDS_MON_DROP 2 - -#define NUM_OF_QWORDS_MON_DROP 1 - -struct mon_drop { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ppdu_id : 32; - uint32_t ppdu_drop_cnt : 10, - mpdu_drop_cnt : 10, - tlv_drop_cnt : 10, - end_of_ppdu_seen : 1, - reserved_1a : 1; -#else - uint32_t ppdu_id : 32; - uint32_t reserved_1a : 1, - end_of_ppdu_seen : 1, - tlv_drop_cnt : 10, - mpdu_drop_cnt : 10, - ppdu_drop_cnt : 10; -#endif -}; - -#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000 -#define MON_DROP_PPDU_ID_LSB 0 -#define MON_DROP_PPDU_ID_MSB 31 -#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff - -#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_PPDU_DROP_CNT_LSB 32 -#define MON_DROP_PPDU_DROP_CNT_MSB 41 -#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000 - -#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_MPDU_DROP_CNT_LSB 42 -#define MON_DROP_MPDU_DROP_CNT_MSB 51 -#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000 - -#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_TLV_DROP_CNT_LSB 52 -#define MON_DROP_TLV_DROP_CNT_MSB 61 -#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000 - -#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000 -#define MON_DROP_END_OF_PPDU_SEEN_LSB 62 -#define MON_DROP_END_OF_PPDU_SEEN_MSB 62 -#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000 - -#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000 -#define MON_DROP_RESERVED_1A_LSB 63 -#define MON_DROP_RESERVED_1A_MSB 63 -#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mon_ingress_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/mon_ingress_ring.h deleted file mode 100644 index 76f4e80417e0..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mon_ingress_ring.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_INGRESS_RING_H_ -#define _MON_INGRESS_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_MON_INGRESS_RING 4 - -struct mon_ingress_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buffer_addr_info_details; - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; -#else - struct buffer_addr_info buffer_addr_info_details; - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; -#endif -}; - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff - -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/msmhwiobase.h b/drivers/staging/fw-api/hw/wcn8750/v1/msmhwiobase.h deleted file mode 100644 index 613be3cf2136..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/msmhwiobase.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef MSMHWIOBASE_H -#define MSMHWIOBASE_H - -#define HOST_WCSS_WCSS_BASE 0x0 -#define HOST_WCSS_WCSS_BASE_SIZE 0x00d00000 -#define HOST_WCSS_WCSS_BASE_PHYS 0x00000000 - -#define HOST_HZ_AUXSSAUXSS_SWI_BASE 0x1900000 -#define HOST_HZ_AUXSSAUXSS_SWI_BASE_SIZE 0x00007000 -#define HOST_HZ_AUXSSAUXSS_SWI_BASE_PHYS 0x01900000 - -#define HOST_WLAN_HZ_ZEALIS_AON_BASE 0x1907000 -#define HOST_WLAN_HZ_ZEALIS_AON_BASE_SIZE 0x00019000 -#define HOST_WLAN_HZ_ZEALIS_AON_BASE_PHYS 0x01907000 - -#define HOST_TLMM_BASE 0x1a00000 -#define HOST_TLMM_BASE_SIZE 0x00100000 -#define HOST_TLMM_BASE_PHYS 0x01a00000 - -#define HOST_CORE_TOP_CSR_BASE 0x1b00000 -#define HOST_CORE_TOP_CSR_BASE_SIZE 0x0003f000 -#define HOST_CORE_TOP_CSR_BASE_PHYS 0x01b00000 - -#define QUPV3_QUPV3_ID_3_BASE 0x1b40000 -#define QUPV3_QUPV3_ID_3_BASE_SIZE 0x00040000 -#define QUPV3_QUPV3_ID_3_BASE_PHYS 0x01b40000 - -#define HOST_SOC_WFSS_CE_REG_BASE 0x1b80000 -#define HOST_SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 -#define HOST_SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 - -#define HOST_WL_TLMM_BASE 0x1bc0000 -#define HOST_WL_TLMM_BASE_SIZE 0x00020000 -#define HOST_WL_TLMM_BASE_PHYS 0x01bc0000 - -#define HOST_TSENS_SROT_BASE 0x1bf0000 -#define HOST_TSENS_SROT_BASE_SIZE 0x00001000 -#define HOST_TSENS_SROT_BASE_PHYS 0x01bf0000 - -#define HOST_TSENS_TM_BASE 0x1bf1000 -#define HOST_TSENS_TM_BASE_SIZE 0x00001000 -#define HOST_TSENS_TM_BASE_PHYS 0x01bf1000 - -#define HOST_QDSS_LITE_QDSS_LITE_APB_BASE 0x1c00000 -#define HOST_QDSS_LITE_QDSS_LITE_APB_BASE_SIZE 0x00080000 -#define HOST_QDSS_LITE_QDSS_LITE_APB_BASE_PHYS 0x01c00000 - -#define HOST_SOC_DBG_WRAPPER_TOPHOST__BASE 0x1c80000 -#define HOST_SOC_DBG_WRAPPER_TOPHOST__BASE_SIZE 0x0007fffd -#define HOST_SOC_DBG_WRAPPER_TOPHOST__BASE_PHYS 0x01c80000 - -#define HOST_QDSS_APB_WCSS_DBG_DEC_SOC_APB_WCSSDBG_BASE 0x1d00000 -#define HOST_QDSS_APB_WCSS_DBG_DEC_SOC_APB_WCSSDBG_BASE_SIZE 0x00100000 -#define HOST_QDSS_APB_WCSS_DBG_DEC_SOC_APB_WCSSDBG_BASE_PHYS 0x01d00000 - -#define HOST_PCIE_PCIE_TOP_WRAPPER_BASE 0x1e00000 -#define HOST_PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000 -#define HOST_PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000 - -#define HOST_SECURITY_CONTROL_WLAN_BASE 0x1e20000 -#define HOST_SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000 -#define HOST_SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000 - -#define HOST_EDPD_CAL_ACC_BASE 0x1e28000 -#define HOST_EDPD_CAL_ACC_BASE_SIZE 0x00003000 -#define HOST_EDPD_CAL_ACC_BASE_PHYS 0x01e28000 - -#define HOST_CPR_CX_CPR3_BASE 0x1e30000 -#define HOST_CPR_CX_CPR3_BASE_SIZE 0x00004000 -#define HOST_CPR_CX_CPR3_BASE_PHYS 0x01e30000 - -#define HOST_CPR_MX_CPR3_BASE 0x1e34000 -#define HOST_CPR_MX_CPR3_BASE_SIZE 0x00004000 -#define HOST_CPR_MX_CPR3_BASE_PHYS 0x01e34000 - -#define HOST_WCSS_IE_BASE 0x1e38000 -#define HOST_WCSS_IE_BASE_SIZE 0x00001000 -#define HOST_WCSS_IE_BASE_PHYS 0x01e38000 - -#define HOST_GCC_GCC_BASE 0x1e40000 -#define HOST_GCC_GCC_BASE_SIZE 0x0000048c -#define HOST_GCC_GCC_BASE_PHYS 0x01e40000 - -#define HOST_PCNOC_0_BUS_TIMEOUT_BASE 0x1e60000 -#define HOST_PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000 -#define HOST_PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000 - -#define HOST_PCNOC_1_BUS_TIMEOUT_BASE 0x1e61000 -#define HOST_PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000 -#define HOST_PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000 - -#define HOST_PCNOC_2_BUS_TIMEOUT_BASE 0x1e62000 -#define HOST_PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000 -#define HOST_PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000 - -#define HOST_PCNOC_3_BUS_TIMEOUT_BASE 0x1e63000 -#define HOST_PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000 -#define HOST_PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000 - -#define HOST_PCNOC_4_BUS_TIMEOUT_BASE 0x1e64000 -#define HOST_PCNOC_4_BUS_TIMEOUT_BASE_SIZE 0x00001000 -#define HOST_PCNOC_4_BUS_TIMEOUT_BASE_PHYS 0x01e64000 - -#define HOST_PCNOC_5_BUS_TIMEOUT_BASE 0x1e65000 -#define HOST_PCNOC_5_BUS_TIMEOUT_BASE_SIZE 0x00001000 -#define HOST_PCNOC_5_BUS_TIMEOUT_BASE_PHYS 0x01e65000 - -#define HOST_RRI_PREFETCH_REG_BASE 0x1e70000 -#define HOST_RRI_PREFETCH_REG_BASE_SIZE 0x00010000 -#define HOST_RRI_PREFETCH_REG_BASE_PHYS 0x01e70000 - -#define HOST_SYSTEM_NOC_BASE 0x1e80000 -#define HOST_SYSTEM_NOC_BASE_SIZE 0x0000a000 -#define HOST_SYSTEM_NOC_BASE_PHYS 0x01e80000 - -#define HOST_PC_NOC_BASE 0x1f00000 -#define HOST_PC_NOC_BASE_SIZE 0x00003880 -#define HOST_PC_NOC_BASE_PHYS 0x01f00000 - -#define HOST_WLAON_WL_AON_REG_BASE 0x1f80000 -#define HOST_WLAON_WL_AON_REG_BASE_SIZE 0x000007f0 -#define HOST_WLAON_WL_AON_REG_BASE_PHYS 0x01f80000 - -#define HOST_SYSPM_SYSPM_REG_BASE 0x1f82000 -#define HOST_SYSPM_SYSPM_REG_BASE_SIZE 0x00001000 -#define HOST_SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000 - -#define HOST_PMU_WLAN_PMU_TOP_BASE 0x1f88000 -#define HOST_PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000400 -#define HOST_PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000 - -#define HOST_PMU_NOC_BASE 0x1f8a000 -#define HOST_PMU_NOC_BASE_SIZE 0x00000180 -#define HOST_PMU_NOC_BASE_PHYS 0x01f8a000 - -#define HOST_BOOT_ROM 0x1200000 -#define HOST_BOOT_ROM_SIZE 0x00004800 -#define HOST_BOOT_ROM_PHYS 0x01200000 - -#define HOST_SYSTEM_IRAM 0x1400000 -#define HOST_SYSTEM_IRAM_SIZE 0x00020000 -#define HOST_SYSTEM_IRAM_PHYS 0x01400000 - -#define HOST_ZEALIS_SRAM 0x28c0000 -#define HOST_ZEALIS_SRAM_SIZE 0x00040000 -#define HOST_ZEALIS_SRAM_PHYS 0x028c0000 - -#define HOST_PCIE_ATU_REGION 0x4000000 -#define HOST_PCIE_ATU_REGION_SIZE 0x40000000 -#define HOST_PCIE_ATU_REGION_PHYS 0x04000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/msmhwioreg.h b/drivers/staging/fw-api/hw/wcn8750/v1/msmhwioreg.h deleted file mode 100644 index 2d9c5ac5a7db..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/msmhwioreg.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef __MSMHWIOREG_H__ -#define __MSMHWIOREG_H__ - -#include "msmhwiobase.h" - -#define HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00001000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x408) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ - in_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x4) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ - in_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00003000) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ - in_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x4) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ - in_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x400) -#define HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00002000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ - in_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x4) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ - in_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x400) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x58) - - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/no_ack_report.h b/drivers/staging/fw-api/hw/wcn8750/v1/no_ack_report.h deleted file mode 100644 index 5f9660801de6..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/no_ack_report.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _NO_ACK_REPORT_H_ -#define _NO_ACK_REPORT_H_ - -#define NUM_OF_DWORDS_NO_ACK_REPORT 4 - -struct no_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t no_ack_transmit_reason : 4, - macrx_abort_reason : 4, - phyrx_abort_reason : 8, - frame_control : 16; - uint32_t rx_ppdu_duration : 24, - sr_ppdu_during_obss : 1, - selfgen_response_reason_to_sr_ppdu : 4, - reserved_1 : 3; - uint32_t pre_bt_broadcast_status_details : 12, - first_bt_broadcast_status_details : 12, - reserved_2 : 8; - uint32_t second_bt_broadcast_status_details : 12, - reserved_3 : 20; -#else - uint32_t frame_control : 16, - phyrx_abort_reason : 8, - macrx_abort_reason : 4, - no_ack_transmit_reason : 4; - uint32_t reserved_1 : 3, - selfgen_response_reason_to_sr_ppdu : 4, - sr_ppdu_during_obss : 1, - rx_ppdu_duration : 24; - uint32_t reserved_2 : 8, - first_bt_broadcast_status_details : 12, - pre_bt_broadcast_status_details : 12; - uint32_t reserved_3 : 20, - second_bt_broadcast_status_details : 12; -#endif -}; - -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f - -#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 - -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 - -#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 -#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 -#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 -#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 - -#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 -#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 -#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 -#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff - -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 - -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 - -#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 -#define NO_ACK_REPORT_RESERVED_1_LSB 29 -#define NO_ACK_REPORT_RESERVED_1_MSB 31 -#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 - -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff - -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 - -#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 -#define NO_ACK_REPORT_RESERVED_2_LSB 24 -#define NO_ACK_REPORT_RESERVED_2_MSB 31 -#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 - -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff - -#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c -#define NO_ACK_REPORT_RESERVED_3_LSB 12 -#define NO_ACK_REPORT_RESERVED_3_MSB 31 -#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/ofdma_trigger_details.h deleted file mode 100644 index 8ad80d76b0ee..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/ofdma_trigger_details.h +++ /dev/null @@ -1,944 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _OFDMA_TRIGGER_DETAILS_H_ -#define _OFDMA_TRIGGER_DETAILS_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 26 - -#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 13 - -struct ofdma_trigger_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ax_trigger_source : 1, - rx_trigger_frame_user_source : 2, - received_bandwidth : 3, - txop_duration_all_ones : 1, - eht_trigger_response : 1, - pre_rssi_comb : 8, - rssi_comb : 8, - rxpcu_pcie_l0_req_duration : 8; - uint32_t he_trigger_ul_ppdu_length : 5, - he_trigger_ru_allocation : 8, - he_trigger_dl_tx_power : 5, - he_trigger_ul_target_rssi : 5, - he_trigger_ul_mcs : 2, - he_trigger_reserved : 1, - bss_color : 6; - uint32_t trigger_type : 4, - lsig_response_length : 12, - cascade_indication : 1, - carrier_sense : 1, - bandwidth : 2, - cp_ltf_size : 2, - mu_mimo_ltf_mode : 1, - number_of_ltfs : 3, - stbc : 1, - ldpc_extra_symbol : 1, - ap_tx_power_lsb_part : 4; - uint32_t ap_tx_power_msb_part : 2, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - spatial_reuse : 16, - doppler : 1, - he_siga_reserved : 9, - reserved_3b : 1; - uint32_t aid12 : 12, - ru_allocation : 9, - mcs : 4, - dcm : 1, - start_spatial_stream : 3, - number_of_spatial_stream : 3; - uint32_t target_rssi : 7, - coding_type : 1, - mpdu_mu_spacing_factor : 2, - tid_aggregation_limit : 3, - reserved_5b : 1, - prefered_ac : 2, - bar_control_ack_policy : 1, - bar_control_multi_tid : 1, - bar_control_compressed_bitmap : 1, - bar_control_reserved : 9, - bar_control_tid_info : 4; - uint32_t nr0_per_tid_info_reserved : 12, - nr0_per_tid_info_tid_value : 4, - nr0_start_seq_ctrl_frag_number : 4, - nr0_start_seq_ctrl_start_seq_number : 12; - uint32_t nr1_per_tid_info_reserved : 12, - nr1_per_tid_info_tid_value : 4, - nr1_start_seq_ctrl_frag_number : 4, - nr1_start_seq_ctrl_start_seq_number : 12; - uint32_t nr2_per_tid_info_reserved : 12, - nr2_per_tid_info_tid_value : 4, - nr2_start_seq_ctrl_frag_number : 4, - nr2_start_seq_ctrl_start_seq_number : 12; - uint32_t nr3_per_tid_info_reserved : 12, - nr3_per_tid_info_tid_value : 4, - nr3_start_seq_ctrl_frag_number : 4, - nr3_start_seq_ctrl_start_seq_number : 12; - uint32_t nr4_per_tid_info_reserved : 12, - nr4_per_tid_info_tid_value : 4, - nr4_start_seq_ctrl_frag_number : 4, - nr4_start_seq_ctrl_start_seq_number : 12; - uint32_t nr5_per_tid_info_reserved : 12, - nr5_per_tid_info_tid_value : 4, - nr5_start_seq_ctrl_frag_number : 4, - nr5_start_seq_ctrl_start_seq_number : 12; - uint32_t nr6_per_tid_info_reserved : 12, - nr6_per_tid_info_tid_value : 4, - nr6_start_seq_ctrl_frag_number : 4, - nr6_start_seq_ctrl_start_seq_number : 12; - uint32_t nr7_per_tid_info_reserved : 12, - nr7_per_tid_info_tid_value : 4, - nr7_start_seq_ctrl_frag_number : 4, - nr7_start_seq_ctrl_start_seq_number : 12; - uint32_t fb_segment_retransmission_bitmap : 8, - reserved_14a : 2, - u_sig_puncture_pattern_encoding : 6, - dot11be_puncture_bitmap : 16; - uint32_t rx_chain_mask : 8, - rx_duration_field : 16, - scrambler_seed : 7, - rx_chain_mask_type : 1; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t normalized_pre_rssi_comb : 8, - normalized_rssi_comb : 8; - uint32_t sw_peer_id : 16, - response_tx_duration : 16; - uint32_t __reserved_g_0005_trigger_subtype : 4, - tbr_trigger_common_info_79_68 : 12, - tbr_trigger_sound_reserved_20_12 : 9, - i2r_rep : 3, - tbr_trigger_sound_reserved_25_24 : 2, - reserved_18a : 1, - qos_null_only_response_tx : 1; - uint32_t tbr_trigger_sound_sac : 16, - reserved_19a : 8, - u_sig_reserved2 : 5, - reserved_19b : 3; - uint32_t eht_special_aid12 : 12, - phy_version : 3, - bandwidth_ext : 2, - eht_spatial_reuse : 8, - u_sig_reserved1 : 7; - uint32_t eht_trigger_special_user_info_71_40 : 32; - uint32_t __reserved_g_0086 : 1, - __reserved_g_0074 : 4, - blackout_details_en : 1, - uhr_trig_response : 1, - mcs_ext : 1, - dso_primary20_index_select : 4, - dso_icf_reception : 1, - dru_spreading_bw : 2, - dru_indication_per_80mhz : 4, - coding_type_ext : 1, - pad_duration : 5, - ects_as_tb_ppdu : 1, - reserved_22a : 6; - uint32_t dso_cca_puncture_pattern : 16, - dso_freq_subband_channel_bonding_mask : 16; - uint32_t __reserved_g_0034 : 1, - enable_steering : 1, - q2q_mba : 1, - reserved_24a : 29; - uint32_t reserved_25a : 32; -#else - uint32_t rxpcu_pcie_l0_req_duration : 8, - rssi_comb : 8, - pre_rssi_comb : 8, - eht_trigger_response : 1, - txop_duration_all_ones : 1, - received_bandwidth : 3, - rx_trigger_frame_user_source : 2, - ax_trigger_source : 1; - uint32_t bss_color : 6, - he_trigger_reserved : 1, - he_trigger_ul_mcs : 2, - he_trigger_ul_target_rssi : 5, - he_trigger_dl_tx_power : 5, - he_trigger_ru_allocation : 8, - he_trigger_ul_ppdu_length : 5; - uint32_t ap_tx_power_lsb_part : 4, - ldpc_extra_symbol : 1, - stbc : 1, - number_of_ltfs : 3, - mu_mimo_ltf_mode : 1, - cp_ltf_size : 2, - bandwidth : 2, - carrier_sense : 1, - cascade_indication : 1, - lsig_response_length : 12, - trigger_type : 4; - uint32_t reserved_3b : 1, - he_siga_reserved : 9, - doppler : 1, - spatial_reuse : 16, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - ap_tx_power_msb_part : 2; - uint32_t number_of_spatial_stream : 3, - start_spatial_stream : 3, - dcm : 1, - mcs : 4, - ru_allocation : 9, - aid12 : 12; - uint32_t bar_control_tid_info : 4, - bar_control_reserved : 9, - bar_control_compressed_bitmap : 1, - bar_control_multi_tid : 1, - bar_control_ack_policy : 1, - prefered_ac : 2, - reserved_5b : 1, - tid_aggregation_limit : 3, - mpdu_mu_spacing_factor : 2, - coding_type : 1, - target_rssi : 7; - uint32_t nr0_start_seq_ctrl_start_seq_number : 12, - nr0_start_seq_ctrl_frag_number : 4, - nr0_per_tid_info_tid_value : 4, - nr0_per_tid_info_reserved : 12; - uint32_t nr1_start_seq_ctrl_start_seq_number : 12, - nr1_start_seq_ctrl_frag_number : 4, - nr1_per_tid_info_tid_value : 4, - nr1_per_tid_info_reserved : 12; - uint32_t nr2_start_seq_ctrl_start_seq_number : 12, - nr2_start_seq_ctrl_frag_number : 4, - nr2_per_tid_info_tid_value : 4, - nr2_per_tid_info_reserved : 12; - uint32_t nr3_start_seq_ctrl_start_seq_number : 12, - nr3_start_seq_ctrl_frag_number : 4, - nr3_per_tid_info_tid_value : 4, - nr3_per_tid_info_reserved : 12; - uint32_t nr4_start_seq_ctrl_start_seq_number : 12, - nr4_start_seq_ctrl_frag_number : 4, - nr4_per_tid_info_tid_value : 4, - nr4_per_tid_info_reserved : 12; - uint32_t nr5_start_seq_ctrl_start_seq_number : 12, - nr5_start_seq_ctrl_frag_number : 4, - nr5_per_tid_info_tid_value : 4, - nr5_per_tid_info_reserved : 12; - uint32_t nr6_start_seq_ctrl_start_seq_number : 12, - nr6_start_seq_ctrl_frag_number : 4, - nr6_per_tid_info_tid_value : 4, - nr6_per_tid_info_reserved : 12; - uint32_t nr7_start_seq_ctrl_start_seq_number : 12, - nr7_start_seq_ctrl_frag_number : 4, - nr7_per_tid_info_tid_value : 4, - nr7_per_tid_info_reserved : 12; - uint32_t dot11be_puncture_bitmap : 16, - u_sig_puncture_pattern_encoding : 6, - reserved_14a : 2, - fb_segment_retransmission_bitmap : 8; - uint32_t rx_chain_mask_type : 1, - scrambler_seed : 7, - rx_duration_field : 16, - rx_chain_mask : 8; - uint32_t normalized_rssi_comb : 8, - normalized_pre_rssi_comb : 8; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint32_t response_tx_duration : 16, - sw_peer_id : 16; - uint32_t qos_null_only_response_tx : 1, - reserved_18a : 1, - tbr_trigger_sound_reserved_25_24 : 2, - i2r_rep : 3, - tbr_trigger_sound_reserved_20_12 : 9, - tbr_trigger_common_info_79_68 : 12, - __reserved_g_0005_trigger_subtype : 4; - uint32_t reserved_19b : 3, - u_sig_reserved2 : 5, - reserved_19a : 8, - tbr_trigger_sound_sac : 16; - uint32_t u_sig_reserved1 : 7, - eht_spatial_reuse : 8, - bandwidth_ext : 2, - phy_version : 3, - eht_special_aid12 : 12; - uint32_t eht_trigger_special_user_info_71_40 : 32; - uint32_t reserved_22a : 6, - ects_as_tb_ppdu : 1, - pad_duration : 5, - coding_type_ext : 1, - dru_indication_per_80mhz : 4, - dru_spreading_bw : 2, - dso_icf_reception : 1, - dso_primary20_index_select : 4, - mcs_ext : 1, - uhr_trig_response : 1, - blackout_details_en : 1, - __reserved_g_0074 : 4, - __reserved_g_0086 : 1; - uint32_t dso_freq_subband_channel_bonding_mask : 16, - dso_cca_puncture_pattern : 16; - uint32_t reserved_24a : 29, - q2q_mba : 1, - enable_steering : 1, - __reserved_g_0034 : 1; - uint32_t reserved_25a : 32; -#endif -}; - -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001 - -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006 - -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038 - -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040 - -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080 - -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00 - -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000 - -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000 - -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000 - -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f - -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0 - -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000 - -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000 - -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000 - -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000 - -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000 - -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000 - -#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 -#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 -#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000 - -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000 - -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000 - -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000 - -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000 - -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000 - -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000 - -#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000 - -#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 -#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 -#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000 - -#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 -#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 -#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000 - -#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 -#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 -#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000 - -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000 - -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000 - -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000 - -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000 - -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000 - -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000 - -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff - -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00 - -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000 - -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000 - -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000 - -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000 - -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 - -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 - -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000 - -#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000 - -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000 - -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000 - -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000 - -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000 - -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000 - -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_LSB 5 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MSB 5 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MASK 0x0000000000000020 - -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_LSB 6 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MSB 6 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MASK 0x0000000000000040 - -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_LSB 7 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MSB 7 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MASK 0x0000000000000080 - -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_LSB 8 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MSB 11 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MASK 0x0000000000000f00 - -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MSB 12 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MASK 0x0000000000001000 - -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_LSB 13 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MSB 14 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MASK 0x0000000000006000 - -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_LSB 15 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MSB 18 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MASK 0x0000000000078000 - -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_LSB 19 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MSB 19 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MASK 0x0000000000080000 - -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_LSB 20 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MSB 24 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MASK 0x0000000001f00000 - -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 25 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 25 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x0000000002000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_LSB 26 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MASK 0x00000000fc000000 - -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_LSB 32 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MSB 47 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 48 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 63 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0xffff000000000000 - -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_LSB 1 -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MSB 1 -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MASK 0x0000000000000002 - -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_LSB 2 -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MSB 2 -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MASK 0x0000000000000004 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_LSB 3 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MASK 0x00000000fffffff8 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_LSB 32 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/wcn8750/v1/pcu_ppdu_setup_init.h deleted file mode 100644 index f623a25ba4d4..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/pcu_ppdu_setup_init.h +++ /dev/null @@ -1,2316 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PCU_PPDU_SETUP_INIT_H_ -#define _PCU_PPDU_SETUP_INIT_H_ - -#include "pdg_response_rate_setting.h" -#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 - -#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29 - -struct pcu_ppdu_setup_init { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t medium_prot_type : 3, - response_type : 5, - response_info_part2_required : 1, - response_to_response : 3, - mba_user_order : 2, - expected_mba_size : 11, - required_ul_mu_resp_user_count : 6, - transmitted_bssid_check_en : 1; - uint32_t mprot_required_bw1 : 1, - mprot_required_bw20 : 1, - mprot_required_bw40 : 1, - mprot_required_bw80 : 1, - mprot_required_bw160 : 1, - mprot_required_bw240 : 1, - mprot_required_bw320 : 1, - ppdu_allowed_bw1 : 1, - ppdu_allowed_bw20 : 1, - ppdu_allowed_bw40 : 1, - ppdu_allowed_bw80 : 1, - ppdu_allowed_bw160 : 1, - ppdu_allowed_bw240 : 1, - ppdu_allowed_bw320 : 1, - set_fc_pwr_mgt : 1, - use_cts_duration_for_data_tx : 1, - update_timestamp_64 : 1, - update_timestamp_32_lower : 1, - update_timestamp_32_upper : 1, - reserved_1a : 13; - uint32_t insert_timestamp_offset_0 : 16, - insert_timestamp_offset_1 : 16; - uint32_t max_bw40_try_count : 4, - max_bw80_try_count : 4, - max_bw160_try_count : 4, - max_bw240_try_count : 4, - max_bw320_try_count : 4, - insert_wur_timestamp_offset : 6, - update_wur_timestamp : 1, - wur_embedded_bssid_present : 1, - insert_wur_fcs : 1, - q2q_trigger : 1, - reserved_3b : 2; - struct pdg_response_rate_setting response_to_response_rate_info_bw20; - struct pdg_response_rate_setting response_to_response_rate_info_bw40; - struct pdg_response_rate_setting response_to_response_rate_info_bw80; - struct pdg_response_rate_setting response_to_response_rate_info_bw160; - struct pdg_response_rate_setting response_to_response_rate_info_bw240; - struct pdg_response_rate_setting response_to_response_rate_info_bw320; - uint32_t r2r_hw_response_tx_duration : 16, - r2r_rx_duration_field : 16; - uint32_t r2r_group_id : 6, - r2r_response_frame_type : 4, - r2r_sta_partial_aid : 11, - use_address_fields_for_protection : 1, - r2r_set_required_response_time : 1, - reserved_29a : 3, - r2r_bw20_active_channel : 3, - r2r_bw40_active_channel : 3; - uint32_t r2r_bw80_active_channel : 3, - r2r_bw160_active_channel : 3, - r2r_bw240_active_channel : 3, - r2r_bw320_active_channel : 3, - r2r_bw20 : 3, - r2r_bw40 : 3, - r2r_bw80 : 3, - r2r_bw160 : 3, - r2r_bw240 : 3, - r2r_bw320 : 3, - tx_with_blackout_details : 1, - expect_rx_with_blackout_details : 1; - uint32_t mu_response_expected_bitmap_31_0 : 32; - uint32_t mu_response_expected_bitmap_36_32 : 5, - mu_expected_response_cbf_count : 6, - mu_expected_response_sta_count : 6, - transmit_includes_multidestination : 1, - insert_prev_tx_start_timing_info : 1, - insert_current_tx_start_timing_info : 1, - tx_start_transmit_time_byte_offset : 12; - uint32_t protection_frame_ad1_31_0 : 32; - uint32_t protection_frame_ad1_47_32 : 16, - protection_frame_ad2_15_0 : 16; - uint32_t protection_frame_ad2_47_16 : 32; - uint32_t dynamic_medium_prot_threshold : 24, - dynamic_medium_prot_type : 1, - reserved_54a : 7; - uint32_t protection_frame_ad3_31_0 : 32; - uint32_t protection_frame_ad3_47_32 : 16, - protection_frame_ad4_15_0 : 16; - uint32_t protection_frame_ad4_47_16 : 32; -#else - uint32_t transmitted_bssid_check_en : 1, - required_ul_mu_resp_user_count : 6, - expected_mba_size : 11, - mba_user_order : 2, - response_to_response : 3, - response_info_part2_required : 1, - response_type : 5, - medium_prot_type : 3; - uint32_t reserved_1a : 13, - update_timestamp_32_upper : 1, - update_timestamp_32_lower : 1, - update_timestamp_64 : 1, - use_cts_duration_for_data_tx : 1, - set_fc_pwr_mgt : 1, - ppdu_allowed_bw320 : 1, - ppdu_allowed_bw240 : 1, - ppdu_allowed_bw160 : 1, - ppdu_allowed_bw80 : 1, - ppdu_allowed_bw40 : 1, - ppdu_allowed_bw20 : 1, - ppdu_allowed_bw1 : 1, - mprot_required_bw320 : 1, - mprot_required_bw240 : 1, - mprot_required_bw160 : 1, - mprot_required_bw80 : 1, - mprot_required_bw40 : 1, - mprot_required_bw20 : 1, - mprot_required_bw1 : 1; - uint32_t insert_timestamp_offset_1 : 16, - insert_timestamp_offset_0 : 16; - uint32_t reserved_3b : 2, - q2q_trigger : 1, - insert_wur_fcs : 1, - wur_embedded_bssid_present : 1, - update_wur_timestamp : 1, - insert_wur_timestamp_offset : 6, - max_bw320_try_count : 4, - max_bw240_try_count : 4, - max_bw160_try_count : 4, - max_bw80_try_count : 4, - max_bw40_try_count : 4; - struct pdg_response_rate_setting response_to_response_rate_info_bw20; - struct pdg_response_rate_setting response_to_response_rate_info_bw40; - struct pdg_response_rate_setting response_to_response_rate_info_bw80; - struct pdg_response_rate_setting response_to_response_rate_info_bw160; - struct pdg_response_rate_setting response_to_response_rate_info_bw240; - struct pdg_response_rate_setting response_to_response_rate_info_bw320; - uint32_t r2r_rx_duration_field : 16, - r2r_hw_response_tx_duration : 16; - uint32_t r2r_bw40_active_channel : 3, - r2r_bw20_active_channel : 3, - reserved_29a : 3, - r2r_set_required_response_time : 1, - use_address_fields_for_protection : 1, - r2r_sta_partial_aid : 11, - r2r_response_frame_type : 4, - r2r_group_id : 6; - uint32_t expect_rx_with_blackout_details : 1, - tx_with_blackout_details : 1, - r2r_bw320 : 3, - r2r_bw240 : 3, - r2r_bw160 : 3, - r2r_bw80 : 3, - r2r_bw40 : 3, - r2r_bw20 : 3, - r2r_bw320_active_channel : 3, - r2r_bw240_active_channel : 3, - r2r_bw160_active_channel : 3, - r2r_bw80_active_channel : 3; - uint32_t mu_response_expected_bitmap_31_0 : 32; - uint32_t tx_start_transmit_time_byte_offset : 12, - insert_current_tx_start_timing_info : 1, - insert_prev_tx_start_timing_info : 1, - transmit_includes_multidestination : 1, - mu_expected_response_sta_count : 6, - mu_expected_response_cbf_count : 6, - mu_response_expected_bitmap_36_32 : 5; - uint32_t protection_frame_ad1_31_0 : 32; - uint32_t protection_frame_ad2_15_0 : 16, - protection_frame_ad1_47_32 : 16; - uint32_t protection_frame_ad2_47_16 : 32; - uint32_t reserved_54a : 7, - dynamic_medium_prot_type : 1, - dynamic_medium_prot_threshold : 24; - uint32_t protection_frame_ad3_31_0 : 32; - uint32_t protection_frame_ad4_15_0 : 16, - protection_frame_ad3_47_32 : 16; - uint32_t protection_frame_ad4_47_16 : 32; -#endif -}; - -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x0000000000000007 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x00000000000000f8 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0000000000000100 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x0000000000000e00 - -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x0000000000003000 - -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x0000000001ffc000 - -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x000000007e000000 - -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 32 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 32 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 33 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 33 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x0000000200000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 34 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 34 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x0000000400000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 35 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 35 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x0000000800000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 36 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 36 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x0000001000000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 37 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 37 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x0000002000000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 38 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 38 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x0000004000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 39 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 39 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 40 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 40 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x0000010000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 41 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 41 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x0000020000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 42 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 42 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 43 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 43 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 44 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 44 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 45 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 45 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 46 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 46 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 47 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 47 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 48 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 48 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x0001000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 49 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 49 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x0002000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 50 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 50 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x0004000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff8000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 32 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 35 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 36 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 39 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 40 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 43 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f0000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 44 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 47 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f00000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 48 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 51 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 52 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 57 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 58 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 58 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 59 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 59 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x0800000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 60 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 60 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x1000000000000000 - -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_LSB 61 -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_MSB 61 -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xc000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 37 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f00000000 - -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 38 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 41 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 42 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 52 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc0000000000 - -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 53 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 53 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 54 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 54 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x0040000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 55 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x0380000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 58 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 60 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c00000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 61 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 63 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe000000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x0000000000000007 - -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x0000000000000038 - -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x00000000000001c0 - -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x0000000000000e00 - -#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x0000000000007000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x0000000000038000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x0000000000e00000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x0000000007000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_LSB 30 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MSB 30 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB 31 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB 31 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x00000000000007e0 - -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x000000000001f800 - -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x0000000000020000 - -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x0000000000040000 - -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0x00000000fff00000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x0000000000ffffff - -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0x00000000fe000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response.h b/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response.h deleted file mode 100644 index d94c69ff2645..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response.h +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_RESPONSE_H_ -#define _PDG_RESPONSE_H_ - -#include "pdg_response_rate_setting.h" -#define NUM_OF_DWORDS_PDG_RESPONSE 14 - -#define NUM_OF_QWORDS_PDG_RESPONSE 7 - -struct pdg_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct pdg_response_rate_setting hw_response_rate_info; - uint32_t hw_response_tx_duration : 16, - rx_duration_field : 16; - uint32_t punctured_response_transmission : 1, - cca_subband_channel_bonding_mask : 16, - scrambler_seed_override : 2, - response_density_valid : 1, - response_density : 5, - more_data : 1, - duration_indication : 1, - blackout_details_en : 1, - cfp_protected_resp : 1, - bandwidth : 3; - uint32_t ack_id : 16, - block_ack_bitmap : 16; - uint32_t response_frame_type : 4, - ack_id_ext : 10, - ftm_en : 1, - group_id : 6, - sta_partial_aid : 11; - uint32_t ndp_ba_start_seq_ctrl : 12, - active_channel : 3, - txop_duration_all_ones : 1, - frame_length : 16; - uint32_t dso_primary20_index_select : 4, - dso_freq_subband_channel_bonding_mask : 16, - pad_duration : 5, - q2q_mba : 1, - reserved_12a : 6; - uint32_t tlv64_padding : 32; -#else - struct pdg_response_rate_setting hw_response_rate_info; - uint32_t rx_duration_field : 16, - hw_response_tx_duration : 16; - uint32_t bandwidth : 3, - cfp_protected_resp : 1, - blackout_details_en : 1, - duration_indication : 1, - more_data : 1, - response_density : 5, - response_density_valid : 1, - scrambler_seed_override : 2, - cca_subband_channel_bonding_mask : 16, - punctured_response_transmission : 1; - uint32_t block_ack_bitmap : 16, - ack_id : 16; - uint32_t sta_partial_aid : 11, - group_id : 6, - ftm_en : 1, - ack_id_ext : 10, - response_frame_type : 4; - uint32_t frame_length : 16, - txop_duration_all_ones : 1, - active_channel : 3, - ndp_ba_start_seq_ctrl : 12; - uint32_t reserved_12a : 6, - q2q_mba : 1, - pad_duration : 5, - dso_freq_subband_channel_bonding_mask : 16, - dso_primary20_index_select : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MSB 3 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MASK 0x000000000000000f - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 36 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 37 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000e000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 46 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00007c0000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_LSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000 - -#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48 -#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63 -#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000 - -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001 - -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe - -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000 - -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000 - -#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 -#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 -#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000 - -#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_MORE_DATA_LSB 25 -#define PDG_RESPONSE_MORE_DATA_MSB 25 -#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000 - -#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 -#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 -#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000 - -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_LSB 27 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MSB 27 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MASK 0x0000000008000000 - -#define PDG_RESPONSE_CFP_PROTECTED_RESP_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_CFP_PROTECTED_RESP_LSB 28 -#define PDG_RESPONSE_CFP_PROTECTED_RESP_MSB 28 -#define PDG_RESPONSE_CFP_PROTECTED_RESP_MASK 0x0000000010000000 - -#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BANDWIDTH_LSB 29 -#define PDG_RESPONSE_BANDWIDTH_MSB 31 -#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000 - -#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_ACK_ID_LSB 32 -#define PDG_RESPONSE_ACK_ID_MSB 47 -#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000 - -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000 - -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f - -#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 -#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 -#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0 - -#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_FTM_EN_LSB 14 -#define PDG_RESPONSE_FTM_EN_MSB 14 -#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000 - -#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_GROUP_ID_LSB 15 -#define PDG_RESPONSE_GROUP_ID_MSB 20 -#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000 - -#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 -#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 -#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000 - -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000 - -#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44 -#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46 -#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000 - -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000 - -#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_FRAME_LENGTH_LSB 48 -#define PDG_RESPONSE_FRAME_LENGTH_MSB 63 -#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000 - -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_LSB 0 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MSB 3 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MASK 0x000000000000000f - -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 4 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 19 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x00000000000ffff0 - -#define PDG_RESPONSE_PAD_DURATION_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_PAD_DURATION_LSB 20 -#define PDG_RESPONSE_PAD_DURATION_MSB 24 -#define PDG_RESPONSE_PAD_DURATION_MASK 0x0000000001f00000 - -#define PDG_RESPONSE_Q2Q_MBA_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_Q2Q_MBA_LSB 25 -#define PDG_RESPONSE_Q2Q_MBA_MSB 25 -#define PDG_RESPONSE_Q2Q_MBA_MASK 0x0000000002000000 - -#define PDG_RESPONSE_RESERVED_12A_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_RESERVED_12A_LSB 26 -#define PDG_RESPONSE_RESERVED_12A_MSB 31 -#define PDG_RESPONSE_RESERVED_12A_MASK 0x00000000fc000000 - -#define PDG_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_TLV64_PADDING_LSB 32 -#define PDG_RESPONSE_TLV64_PADDING_MSB 63 -#define PDG_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response_rate_setting.h b/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response_rate_setting.h deleted file mode 100644 index eb123386f2bf..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response_rate_setting.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_RESPONSE_RATE_SETTING_H_ -#define _PDG_RESPONSE_RATE_SETTING_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 - -struct pdg_response_rate_setting { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 1, - tx_antenna_sector_ctrl : 24, - pkt_type : 4, - smoothing : 1, - ldpc : 1, - stbc : 1; - uint32_t alt_tx_pwr : 8, - alt_min_tx_pwr : 8, - alt_nss : 3, - alt_tx_chain_mask : 8, - alt_bw : 3, - stf_ltf_3db_boost : 1, - force_extra_symbol : 1; - uint32_t reserved_2a : 4, - nss : 3, - dpd_enable : 1, - tx_pwr : 8, - min_tx_pwr : 8, - tx_chain_mask : 8; - uint32_t alt_rate_mcs : 5, - reserved_3a : 3, - sgi : 2, - rate_mcs : 5, - ldpc_2x_codeword : 1, - tx_pwr_1 : 8, - alt_tx_pwr_1 : 8; - uint32_t aggregation : 1, - dot11ax_bss_color_id : 6, - dot11ax_spatial_reuse : 4, - dot11ax_cp_ltf_size : 2, - dot11ax_dcm : 1, - dot11ax_doppler_indication : 1, - dot11ax_su_extended : 1, - dot11ax_min_packet_extension : 2, - dot11ax_pe_nss : 3, - dot11ax_pe_content : 1, - dot11ax_pe_ltf_size : 2, - dot11ax_chain_csd_en : 1, - dot11ax_pe_chain_csd_en : 1, - dot11ax_dl_ul_flag : 1, - reserved_4a : 5; - uint32_t dot11ax_ext_ru_start_index : 4, - dot11ax_ext_ru_size : 4, - eht_duplicate_mode : 2, - he_sigb_dcm : 1, - he_sigb_0_mcs : 3, - num_he_sigb_sym : 5, - required_response_time_source : 1, - reserved_5a : 6, - u_sig_puncture_pattern_encoding : 6; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t required_response_time : 12, - dot11be_params_placeholder : 4; -#else - uint32_t stbc : 1, - ldpc : 1, - smoothing : 1, - pkt_type : 4, - tx_antenna_sector_ctrl : 24, - reserved_0a : 1; - uint32_t force_extra_symbol : 1, - stf_ltf_3db_boost : 1, - alt_bw : 3, - alt_tx_chain_mask : 8, - alt_nss : 3, - alt_min_tx_pwr : 8, - alt_tx_pwr : 8; - uint32_t tx_chain_mask : 8, - min_tx_pwr : 8, - tx_pwr : 8, - dpd_enable : 1, - nss : 3, - reserved_2a : 4; - uint32_t alt_tx_pwr_1 : 8, - tx_pwr_1 : 8, - ldpc_2x_codeword : 1, - rate_mcs : 5, - sgi : 2, - reserved_3a : 3, - alt_rate_mcs : 5; - uint32_t reserved_4a : 5, - dot11ax_dl_ul_flag : 1, - dot11ax_pe_chain_csd_en : 1, - dot11ax_chain_csd_en : 1, - dot11ax_pe_ltf_size : 2, - dot11ax_pe_content : 1, - dot11ax_pe_nss : 3, - dot11ax_min_packet_extension : 2, - dot11ax_su_extended : 1, - dot11ax_doppler_indication : 1, - dot11ax_dcm : 1, - dot11ax_cp_ltf_size : 2, - dot11ax_spatial_reuse : 4, - dot11ax_bss_color_id : 6, - aggregation : 1; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_5a : 6, - required_response_time_source : 1, - num_he_sigb_sym : 5, - he_sigb_0_mcs : 3, - he_sigb_dcm : 1, - eht_duplicate_mode : 2, - dot11ax_ext_ru_size : 4, - dot11ax_ext_ru_start_index : 4; - uint32_t dot11be_params_placeholder : 4, - required_response_time : 12; - struct mlo_sta_id_details mlo_sta_id_details_rx; -#endif -}; - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 - -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe - -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 - -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 - -#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 -#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 -#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 - -#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 -#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff - -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 - -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 - -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 - -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MSB 3 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MASK 0x0000000f - -#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 -#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 -#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 - -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 - -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 - -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 - -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 4 -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000001f - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 5 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000e0 - -#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 - -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 14 -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00007c00 - -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_LSB 15 -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MASK 0x00008000 - -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 - -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 - -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 - -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 - -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 - -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 - -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 - -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 - -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/pdg_tx_req.h b/drivers/staging/fw-api/hw/wcn8750/v1/pdg_tx_req.h deleted file mode 100644 index 6baf640807da..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/pdg_tx_req.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_TX_REQ_H_ -#define _PDG_TX_REQ_H_ - -#define NUM_OF_DWORDS_PDG_TX_REQ 2 - -#define NUM_OF_QWORDS_PDG_TX_REQ 1 - -struct pdg_tx_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_reason : 2, - use_puncture_pattern : 2, - req_bw : 3, - puncture_pattern_number : 6, - reserved_0b : 1, - req_paprd : 1, - duration_field_boundary_valid : 1, - duration_field_boundary : 16; - uint32_t puncture_subband_mask : 16, - reserved_0c : 16; -#else - uint32_t duration_field_boundary : 16, - duration_field_boundary_valid : 1, - req_paprd : 1, - reserved_0b : 1, - puncture_pattern_number : 6, - req_bw : 3, - use_puncture_pattern : 2, - tx_reason : 2; - uint32_t reserved_0c : 16, - puncture_subband_mask : 16; -#endif -}; - -#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_TX_REASON_LSB 0 -#define PDG_TX_REQ_TX_REASON_MSB 1 -#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003 - -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c - -#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_REQ_BW_LSB 4 -#define PDG_TX_REQ_REQ_BW_MSB 6 -#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070 - -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80 - -#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_RESERVED_0B_LSB 13 -#define PDG_TX_REQ_RESERVED_0B_MSB 13 -#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000 - -#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_REQ_PAPRD_LSB 14 -#define PDG_TX_REQ_REQ_PAPRD_MSB 14 -#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000 - -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000 - -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000 - -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000 - -#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_RESERVED_0C_LSB 48 -#define PDG_TX_REQ_RESERVED_0C_MSB 63 -#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_abort_request_info.h deleted file mode 100644 index 1f3bf4b817b9..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_abort_request_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ -#define _PHYRX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 - -struct phyrx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phyrx_abort_reason : 8, - phy_enters_nap_state : 1, - phy_enters_defer_state : 1, - gain_change_by_main : 1, - gain_change_by_bt : 1, - main_tx_indication : 1, - bt_tx_indication : 1, - concurrent_mode : 1, - reserved_0 : 1, - receive_duration : 16; -#else - uint32_t receive_duration : 16, - reserved_0 : 1, - concurrent_mode : 1, - bt_tx_indication : 1, - main_tx_indication : 1, - gain_change_by_bt : 1, - gain_change_by_main : 1, - phy_enters_defer_state : 1, - phy_enters_nap_state : 1, - phyrx_abort_reason : 8; -#endif -}; - -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff - -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 - -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 - -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB 10 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB 10 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK 0x00000400 - -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB 11 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB 11 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK 0x00000800 - -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB 12 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB 12 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK 0x00001000 - -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB 13 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB 13 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK 0x00002000 - -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB 14 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB 14 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK 0x00004000 - -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 15 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x00008000 - -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_common_user_info.h deleted file mode 100644 index e73d1ab47ee7..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_common_user_info.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_COMMON_USER_INFO_H_ -#define _PHYRX_COMMON_USER_INFO_H_ - -#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4 - -#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2 - -struct phyrx_common_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t receive_duration : 16, - reserved_0a : 16; - uint32_t u_sig_puncture_pattern_encoding : 6, - eht___reserved_g_0005_ndp : 1, - reserved_1a : 8, - obss_nav_update_enable : 1, - obss_nav_value : 16; - uint32_t eht_or_uhr_ppdu_type : 2, - bss_color_id : 6, - dl_ul_flag : 1, - txop_duration : 7, - cp_setting : 2, - ltf_size : 2, - spatial_reuse : 4, - rx_ndp : 1, - dot11bn_su_elr : 1, - reserved_2a : 6; - uint32_t eht_duplicate : 2, - eht_or_uhr_sig_cmn_field_type : 2, - doppler_indication : 1, - sta_id : 11, - puncture_bitmap : 16; -#else - uint32_t reserved_0a : 16, - receive_duration : 16; - uint32_t obss_nav_value : 16, - obss_nav_update_enable : 1, - reserved_1a : 8, - eht___reserved_g_0005_ndp : 1, - u_sig_puncture_pattern_encoding : 6; - uint32_t reserved_2a : 6, - dot11bn_su_elr : 1, - rx_ndp : 1, - spatial_reuse : 4, - ltf_size : 2, - cp_setting : 2, - txop_duration : 7, - dl_ul_flag : 1, - bss_color_id : 6, - eht_or_uhr_ppdu_type : 2; - uint32_t puncture_bitmap : 16, - sta_id : 11, - doppler_indication : 1, - eht_or_uhr_sig_cmn_field_type : 2, - eht_duplicate : 2; -#endif -}; - -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x000000000000ffff - -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0x00000000ffff0000 - -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 32 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 37 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f00000000 - -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 39 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 46 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0x00007f8000000000 - -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB 47 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB 47 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK 0x0000800000000000 - -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB 48 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB 63 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK 0xffff000000000000 - -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_LSB 0 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MSB 1 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MASK 0x0000000000000003 - -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x00000000000000fc - -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x0000000000000100 - -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x000000000000fe00 - -#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x0000000000030000 - -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x00000000000c0000 - -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x0000000000f00000 - -#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24 -#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24 -#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x0000000001000000 - -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_LSB 25 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MSB 25 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MASK 0x0000000002000000 - -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26 -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31 -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0x00000000fc000000 - -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 32 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 33 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x0000000300000000 - -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_LSB 34 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MSB 35 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MASK 0x0000000c00000000 - -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 36 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 36 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x0000001000000000 - -#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 37 -#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 47 -#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe000000000 - -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 48 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 63 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h deleted file mode 100644 index da4f1691b9f7..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ -#define _PHYRX_HE_SIG_A_MU_DL_H_ - -#include "he_sig_a_mu_dl_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1 - -struct phyrx_he_sig_a_mu_dl { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; -#else - struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h deleted file mode 100644 index ff9cf72a7237..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ -#define _PHYRX_HE_SIG_A_MU_UL_H_ - -#include "he_sig_a_mu_ul_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1 - -struct phyrx_he_sig_a_mu_ul { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; -#else - struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_su.h deleted file mode 100644 index abca58673a90..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_su.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_SU_H_ -#define _PHYRX_HE_SIG_A_SU_H_ - -#include "he_sig_a_su_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1 - -struct phyrx_he_sig_a_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; -#else - struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b1_mu.h deleted file mode 100644 index ae784469331b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b1_mu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B1_MU_H_ -#define _PHYRX_HE_SIG_B1_MU_H_ - -#include "he_sig_b1_mu_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1 - -struct phyrx_he_sig_b1_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#else - struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_mu.h deleted file mode 100644 index 6035ecffde5d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_mu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B2_MU_H_ -#define _PHYRX_HE_SIG_B2_MU_H_ - -#include "he_sig_b2_mu_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1 - -struct phyrx_he_sig_b2_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; -#else - struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; -#endif -}; - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h deleted file mode 100644 index 126a9559e155..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ -#define _PHYRX_HE_SIG_B2_OFDMA_H_ - -#include "he_sig_b2_ofdma_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1 - -struct phyrx_he_sig_b2_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; -#else - struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; -#endif -}; - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_ht_sig.h deleted file mode 100644 index 4dd90653d431..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_ht_sig.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HT_SIG_H_ -#define _PHYRX_HT_SIG_H_ - -#include "ht_sig_info.h" -#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 - -#define NUM_OF_QWORDS_PHYRX_HT_SIG 1 - -struct phyrx_ht_sig { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ht_sig_info phyrx_ht_sig_info_details; -#else - struct ht_sig_info phyrx_ht_sig_info_details; -#endif -}; - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_a.h deleted file mode 100644 index 2e70822f5d06..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_a.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_L_SIG_A_H_ -#define _PHYRX_L_SIG_A_H_ - -#include "l_sig_a_info.h" -#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2 - -#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1 - -struct phyrx_l_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_a_info phyrx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_a_info phyrx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32 -#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63 -#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_b.h deleted file mode 100644 index 461edd24dd4e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_b.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_L_SIG_B_H_ -#define _PHYRX_L_SIG_B_H_ - -#include "l_sig_b_info.h" -#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2 - -#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1 - -struct phyrx_l_sig_b { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_b_info phyrx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_b_info phyrx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32 -#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63 -#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_location.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_location.h deleted file mode 100644 index 15a8413e304a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_location.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_LOCATION_H_ -#define _PHYRX_LOCATION_H_ - -#include "rx_location_info.h" -#define NUM_OF_DWORDS_PHYRX_LOCATION 28 - -#define NUM_OF_QWORDS_PHYRX_LOCATION 14 - -struct phyrx_location { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_location_info rx_location_info_details; -#else - struct rx_location_info rx_location_info_details; -#endif -}; - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h deleted file mode 100644 index a6090f721e1d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ -#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ - -#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4 - -#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2 - -struct phyrx_other_receive_info_ru_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_details_channel_0 : 32; - uint32_t ru_details_channel_1 : 32; - uint32_t spare : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t ru_details_channel_0 : 32; - uint32_t ru_details_channel_1 : 32; - uint32_t spare : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000 - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end.h deleted file mode 100644 index 1d1675edc0e1..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end.h +++ /dev/null @@ -1,427 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_PKT_END_H_ -#define _PHYRX_PKT_END_H_ - -#include "phyrx_pkt_end_info.h" -#define NUM_OF_DWORDS_PHYRX_PKT_END 24 - -#define NUM_OF_QWORDS_PHYRX_PKT_END 12 - -struct phyrx_pkt_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct phyrx_pkt_end_info rx_pkt_end_details; -#else - struct phyrx_pkt_end_info rx_pkt_end_details; -#endif -}; - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 44 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 53 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff00000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB 54 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc0000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end_info.h deleted file mode 100644 index a21edc94d24e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end_info.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_PKT_END_INFO_H_ -#define _PHYRX_PKT_END_INFO_H_ - -#include "receive_rssi_info.h" -#include "rx_timing_info.h" -#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 - -struct phyrx_pkt_end_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0001 : 1, - location_info_valid : 1, - timing_info_valid : 1, - rssi_info_valid : 1, - reserved_0a : 1, - frameless_frame_received : 1, - reserved_0b : 2, - rssi_comb : 8, - reserved_0c : 16; - struct rx_timing_info rx_timing_info_details; - struct receive_rssi_info post_rssi_info_details; - uint32_t phy_sw_status_31_0 : 32; - uint32_t phy_sw_status_63_32 : 32; -#else - uint32_t reserved_0c : 16, - rssi_comb : 8, - reserved_0b : 2, - frameless_frame_received : 1, - reserved_0a : 1, - rssi_info_valid : 1, - timing_info_valid : 1, - location_info_valid : 1, - __reserved_g_0001 : 1; - struct rx_timing_info rx_timing_info_details; - struct receive_rssi_info post_rssi_info_details; - uint32_t phy_sw_status_31_0 : 32; - uint32_t phy_sw_status_63_32 : 32; -#endif -}; - -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 - -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 - -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 - -#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 -#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 -#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 - -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 - -#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 -#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 -#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 - -#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 -#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 -#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 -#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 -#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 12 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 21 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff000 - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB 22 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc00000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_rssi_legacy.h deleted file mode 100644 index 820ced6212ca..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_rssi_legacy.h +++ /dev/null @@ -1,806 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_RSSI_LEGACY_H_ -#define _PHYRX_RSSI_LEGACY_H_ - -#include "receive_rssi_info.h" -#include "receive_pkt_start_info.h" -#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 - -#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21 - -struct phyrx_rssi_legacy { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_pkt_start_info rx_pkt_start_details; - uint32_t sw_phy_meta_data : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 32; - struct receive_rssi_info pre_rssi_info_details; - struct receive_rssi_info preamble_rssi_info_details; - uint32_t pre_rssi_comb : 8, - rssi_comb : 8, - normalized_pre_rssi_comb : 8, - normalized_rssi_comb : 8; - uint32_t rssi_comb_ppdu : 8, - rssi_db_to_dbm_offset : 8, - rssi_for_spatial_reuse : 8, - rssi_for_trigger_resp : 8; -#else - struct receive_pkt_start_info rx_pkt_start_details; - uint32_t sw_phy_meta_data : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 32; - struct receive_rssi_info pre_rssi_info_details; - struct receive_rssi_info preamble_rssi_info_details; - uint32_t normalized_rssi_comb : 8, - normalized_pre_rssi_comb : 8, - rssi_comb : 8, - pre_rssi_comb : 8; - uint32_t rssi_for_trigger_resp : 8, - rssi_for_spatial_reuse : 8, - rssi_db_to_dbm_offset : 8, - rssi_comb_ppdu : 8; -#endif -}; - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB 3 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK 0x000000000000000f - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x0000000000000010 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB 5 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB 7 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00000000000000e0 - -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB 8 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB 15 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB 16 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB 32 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB 63 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB 32 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB 39 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB 40 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB 40 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK 0x0000010000000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB 41 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB 63 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK 0xfffffe0000000000 - -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x0000000000000010 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 31 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x0000000000000010 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 32 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 63 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x0000000000000018 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000000000000018 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 32 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 63 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 32 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 39 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 40 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 47 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 48 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 55 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 56 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 63 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_user_info.h deleted file mode 100644 index d3dc8b6b2414..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_user_info.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_USER_INFO_H_ -#define _PHYRX_USER_INFO_H_ - -#include "receive_user_info.h" -#define NUM_OF_DWORDS_PHYRX_USER_INFO 8 - -#define NUM_OF_QWORDS_PHYRX_USER_INFO 4 - -struct phyrx_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_user_info receive_user_info_details; -#else - struct receive_user_info receive_user_info_details; -#endif -}; - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 36 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000001f00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 37 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 38 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000006000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 1 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x0000000000000002 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB 2 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB 3 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK 0x000000000000000c - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB 4 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB 5 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK 0x0000000000000030 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB 6 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB 7 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK 0x00000000000000c0 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_vht_sig_a.h deleted file mode 100644 index e47f0e35adeb..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_vht_sig_a.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_VHT_SIG_A_H_ -#define _PHYRX_VHT_SIG_A_H_ - -#include "vht_sig_a_info.h" -#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 - -#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1 - -struct phyrx_vht_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_a_info phyrx_vht_sig_a_info_details; -#else - struct vht_sig_a_info phyrx_vht_sig_a_info_details; -#endif -}; - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phytx_abort_request_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phytx_abort_request_info.h deleted file mode 100644 index e4800f6a2d97..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phytx_abort_request_info.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ -#define _PHYTX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 - -struct phytx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t phytx_abort_reason : 8, - user_number : 6, - reserved : 2; -#else - uint16_t reserved : 2, - user_number : 6, - phytx_abort_reason : 8; -#endif -}; - -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff - -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 - -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phytx_pkt_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/phytx_pkt_end.h deleted file mode 100644 index 55911ea9edb3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phytx_pkt_end.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_PKT_END_H_ -#define _PHYTX_PKT_END_H_ - -#define NUM_OF_WORDS_PHYTX_PKT_END 28 - -#define NUM_OF_DWORDS_PHYTX_PKT_END 14 - -struct phytx_pkt_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t start_of_frame_timestamp_15_0 : 16; - uint16_t start_of_frame_timestamp_31_16 : 16; - uint16_t end_of_frame_timestamp_15_0 : 16; - uint16_t end_of_frame_timestamp_31_16 : 16; - uint16_t tx_group_delay : 12, - timing_status : 2, - phyrx_entered_nap_state : 1, - dpdtrain_done : 1; - uint16_t transmit_delay : 16; - uint16_t tpc_dbg_info_cmn_15_0 : 16; - uint16_t tpc_dbg_info_cmn_31_16 : 16; - uint16_t tpc_dbg_info_cmn_47_32 : 16; - uint16_t tpc_dbg_info_chn1_15_0 : 16; - uint16_t tpc_dbg_info_chn1_31_16 : 16; - uint16_t tpc_dbg_info_chn1_47_32 : 16; - uint16_t tpc_dbg_info_chn1_63_48 : 16; - uint16_t tpc_dbg_info_chn1_79_64 : 16; - uint16_t tpc_dbg_info_chn2_15_0 : 16; - uint16_t tpc_dbg_info_chn2_31_16 : 16; - uint16_t tpc_dbg_info_chn2_47_32 : 16; - uint16_t tpc_dbg_info_chn2_63_48 : 16; - uint16_t tpc_dbg_info_chn2_79_64 : 16; - uint16_t phytx_tx_end_sw_info_15_0 : 16; - uint16_t phytx_tx_end_sw_info_31_16 : 16; - uint16_t phytx_tx_end_sw_info_47_32 : 16; - uint16_t phytx_tx_end_sw_info_63_48 : 16; - uint16_t beamform_masked_user_bitmap_15_0 : 16; - uint16_t beamform_masked_user_bitmap_31_16 : 16; - uint16_t beamform_masked_user_bitmap_36_32 : 5, - reserved_23 : 11; - uint16_t reserved_26 : 16; - uint16_t reserved_27 : 16; -#else - uint16_t start_of_frame_timestamp_15_0 : 16; - uint16_t start_of_frame_timestamp_31_16 : 16; - uint16_t end_of_frame_timestamp_15_0 : 16; - uint16_t end_of_frame_timestamp_31_16 : 16; - uint16_t dpdtrain_done : 1, - phyrx_entered_nap_state : 1, - timing_status : 2, - tx_group_delay : 12; - uint16_t transmit_delay : 16; - uint16_t tpc_dbg_info_cmn_15_0 : 16; - uint16_t tpc_dbg_info_cmn_31_16 : 16; - uint16_t tpc_dbg_info_cmn_47_32 : 16; - uint16_t tpc_dbg_info_chn1_15_0 : 16; - uint16_t tpc_dbg_info_chn1_31_16 : 16; - uint16_t tpc_dbg_info_chn1_47_32 : 16; - uint16_t tpc_dbg_info_chn1_63_48 : 16; - uint16_t tpc_dbg_info_chn1_79_64 : 16; - uint16_t tpc_dbg_info_chn2_15_0 : 16; - uint16_t tpc_dbg_info_chn2_31_16 : 16; - uint16_t tpc_dbg_info_chn2_47_32 : 16; - uint16_t tpc_dbg_info_chn2_63_48 : 16; - uint16_t tpc_dbg_info_chn2_79_64 : 16; - uint16_t phytx_tx_end_sw_info_15_0 : 16; - uint16_t phytx_tx_end_sw_info_31_16 : 16; - uint16_t phytx_tx_end_sw_info_47_32 : 16; - uint16_t phytx_tx_end_sw_info_63_48 : 16; - uint16_t beamform_masked_user_bitmap_15_0 : 16; - uint16_t beamform_masked_user_bitmap_31_16 : 16; - uint16_t reserved_23 : 11, - beamform_masked_user_bitmap_36_32 : 5; - uint16_t reserved_26 : 16; - uint16_t reserved_27 : 16; -#endif -}; - -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000000 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000002 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 0 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 15 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000004 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000006 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 0 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 15 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET 0x00000008 -#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB 0 -#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB 11 -#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK 0x00000fff - -#define PHYTX_PKT_END_TIMING_STATUS_OFFSET 0x00000008 -#define PHYTX_PKT_END_TIMING_STATUS_LSB 12 -#define PHYTX_PKT_END_TIMING_STATUS_MSB 13 -#define PHYTX_PKT_END_TIMING_STATUS_MASK 0x00003000 - -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET 0x00000008 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB 14 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB 14 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK 0x00004000 - -#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET 0x00000008 -#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB 15 -#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB 15 -#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK 0x00008000 - -#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET 0x0000000a -#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB 0 -#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB 15 -#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000c -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000e -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET 0x00000010 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x00000012 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x00000014 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x00000016 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x00000018 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000001a -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000001c -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000001e -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x00000020 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x00000022 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x00000024 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x00000026 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x00000028 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000002a -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000002c -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000002e -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x00000030 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 15 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000032 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 4 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x0000001f - -#define PHYTX_PKT_END_RESERVED_23_OFFSET 0x00000032 -#define PHYTX_PKT_END_RESERVED_23_LSB 5 -#define PHYTX_PKT_END_RESERVED_23_MSB 15 -#define PHYTX_PKT_END_RESERVED_23_MASK 0x0000ffe0 - -#define PHYTX_PKT_END_RESERVED_26_OFFSET 0x00000034 -#define PHYTX_PKT_END_RESERVED_26_LSB 0 -#define PHYTX_PKT_END_RESERVED_26_MSB 15 -#define PHYTX_PKT_END_RESERVED_26_MASK 0x0000ffff - -#define PHYTX_PKT_END_RESERVED_27_OFFSET 0x00000036 -#define PHYTX_PKT_END_RESERVED_27_LSB 0 -#define PHYTX_PKT_END_RESERVED_27_MSB 15 -#define PHYTX_PKT_END_RESERVED_27_MASK 0x0000ffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phytx_ppdu_header_info_request.h b/drivers/staging/fw-api/hw/wcn8750/v1/phytx_ppdu_header_info_request.h deleted file mode 100644 index 7fbecae41236..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phytx_ppdu_header_info_request.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ -#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ - -#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 - -#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 - -struct phytx_ppdu_header_info_request { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t request_type : 5, - reserved : 11; - uint16_t tlv32_padding : 16; -#else - uint16_t reserved : 11, - request_type : 5; - uint16_t tlv32_padding : 16; -#endif -}; - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/receive_pkt_start_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/receive_pkt_start_info.h deleted file mode 100644 index 7f7c81449a15..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/receive_pkt_start_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_PKT_START_INFO_H_ -#define _RECEIVE_PKT_START_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4 - -struct receive_pkt_start_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reception_type : 4, - rx_chain_mask_type : 1, - receive_bandwidth : 3, - rx_chain_mask : 8, - phy_ppdu_id : 16; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t preamble_time_to_rxframe : 8, - standalone_sniffer_mode : 1, - reserved_3a : 23; -#else - uint32_t phy_ppdu_id : 16, - rx_chain_mask : 8, - receive_bandwidth : 3, - rx_chain_mask_type : 1, - reception_type : 4; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t reserved_3a : 23, - standalone_sniffer_mode : 1, - preamble_time_to_rxframe : 8; -#endif -}; - -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB 0 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB 3 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK 0x0000000f - -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB 4 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB 4 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK 0x00000010 - -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB 5 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB 7 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK 0x000000e0 - -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB 8 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB 15 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK 0x0000ff00 - -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB 16 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB 31 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK 0xffff0000 - -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff - -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff - -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB 0 -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB 7 -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff - -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB 8 -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB 8 -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK 0x00000100 - -#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB 9 -#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB 31 -#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK 0xfffffe00 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/receive_rssi_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/receive_rssi_info.h deleted file mode 100644 index 9aaa98217d99..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/receive_rssi_info.h +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_RSSI_INFO_H_ -#define _RECEIVE_RSSI_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 - -struct receive_rssi_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rssi_pri20_chain0 : 8, - rssi_ext20_chain0 : 8, - rssi_ext40_low20_chain0 : 8, - rssi_ext40_high20_chain0 : 8; - uint32_t rssi_ext80_low20_chain0 : 8, - rssi_ext80_low_high20_chain0 : 8, - rssi_ext80_high_low20_chain0 : 8, - rssi_ext80_high20_chain0 : 8; - uint32_t rssi_ext160_0_chain0 : 8, - rssi_ext160_1_chain0 : 8, - rssi_ext160_2_chain0 : 8, - rssi_ext160_3_chain0 : 8; - uint32_t rssi_ext160_4_chain0 : 8, - rssi_ext160_5_chain0 : 8, - rssi_ext160_6_chain0 : 8, - rssi_ext160_7_chain0 : 8; - uint32_t rssi_pri20_chain1 : 8, - rssi_ext20_chain1 : 8, - rssi_ext40_low20_chain1 : 8, - rssi_ext40_high20_chain1 : 8; - uint32_t rssi_ext80_low20_chain1 : 8, - rssi_ext80_low_high20_chain1 : 8, - rssi_ext80_high_low20_chain1 : 8, - rssi_ext80_high20_chain1 : 8; - uint32_t rssi_ext160_0_chain1 : 8, - rssi_ext160_1_chain1 : 8, - rssi_ext160_2_chain1 : 8, - rssi_ext160_3_chain1 : 8; - uint32_t rssi_ext160_4_chain1 : 8, - rssi_ext160_5_chain1 : 8, - rssi_ext160_6_chain1 : 8, - rssi_ext160_7_chain1 : 8; - uint32_t rssi_pri20_chain2 : 8, - rssi_ext20_chain2 : 8, - rssi_ext40_low20_chain2 : 8, - rssi_ext40_high20_chain2 : 8; - uint32_t rssi_ext80_low20_chain2 : 8, - rssi_ext80_low_high20_chain2 : 8, - rssi_ext80_high_low20_chain2 : 8, - rssi_ext80_high20_chain2 : 8; - uint32_t rssi_ext160_0_chain2 : 8, - rssi_ext160_1_chain2 : 8, - rssi_ext160_2_chain2 : 8, - rssi_ext160_3_chain2 : 8; - uint32_t rssi_ext160_4_chain2 : 8, - rssi_ext160_5_chain2 : 8, - rssi_ext160_6_chain2 : 8, - rssi_ext160_7_chain2 : 8; - uint32_t rssi_pri20_chain3 : 8, - rssi_ext20_chain3 : 8, - rssi_ext40_low20_chain3 : 8, - rssi_ext40_high20_chain3 : 8; - uint32_t rssi_ext80_low20_chain3 : 8, - rssi_ext80_low_high20_chain3 : 8, - rssi_ext80_high_low20_chain3 : 8, - rssi_ext80_high20_chain3 : 8; - uint32_t rssi_ext160_0_chain3 : 8, - rssi_ext160_1_chain3 : 8, - rssi_ext160_2_chain3 : 8, - rssi_ext160_3_chain3 : 8; - uint32_t rssi_ext160_4_chain3 : 8, - rssi_ext160_5_chain3 : 8, - rssi_ext160_6_chain3 : 8, - rssi_ext160_7_chain3 : 8; -#else - uint32_t rssi_ext40_high20_chain0 : 8, - rssi_ext40_low20_chain0 : 8, - rssi_ext20_chain0 : 8, - rssi_pri20_chain0 : 8; - uint32_t rssi_ext80_high20_chain0 : 8, - rssi_ext80_high_low20_chain0 : 8, - rssi_ext80_low_high20_chain0 : 8, - rssi_ext80_low20_chain0 : 8; - uint32_t rssi_ext160_3_chain0 : 8, - rssi_ext160_2_chain0 : 8, - rssi_ext160_1_chain0 : 8, - rssi_ext160_0_chain0 : 8; - uint32_t rssi_ext160_7_chain0 : 8, - rssi_ext160_6_chain0 : 8, - rssi_ext160_5_chain0 : 8, - rssi_ext160_4_chain0 : 8; - uint32_t rssi_ext40_high20_chain1 : 8, - rssi_ext40_low20_chain1 : 8, - rssi_ext20_chain1 : 8, - rssi_pri20_chain1 : 8; - uint32_t rssi_ext80_high20_chain1 : 8, - rssi_ext80_high_low20_chain1 : 8, - rssi_ext80_low_high20_chain1 : 8, - rssi_ext80_low20_chain1 : 8; - uint32_t rssi_ext160_3_chain1 : 8, - rssi_ext160_2_chain1 : 8, - rssi_ext160_1_chain1 : 8, - rssi_ext160_0_chain1 : 8; - uint32_t rssi_ext160_7_chain1 : 8, - rssi_ext160_6_chain1 : 8, - rssi_ext160_5_chain1 : 8, - rssi_ext160_4_chain1 : 8; - uint32_t rssi_ext40_high20_chain2 : 8, - rssi_ext40_low20_chain2 : 8, - rssi_ext20_chain2 : 8, - rssi_pri20_chain2 : 8; - uint32_t rssi_ext80_high20_chain2 : 8, - rssi_ext80_high_low20_chain2 : 8, - rssi_ext80_low_high20_chain2 : 8, - rssi_ext80_low20_chain2 : 8; - uint32_t rssi_ext160_3_chain2 : 8, - rssi_ext160_2_chain2 : 8, - rssi_ext160_1_chain2 : 8, - rssi_ext160_0_chain2 : 8; - uint32_t rssi_ext160_7_chain2 : 8, - rssi_ext160_6_chain2 : 8, - rssi_ext160_5_chain2 : 8, - rssi_ext160_4_chain2 : 8; - uint32_t rssi_ext40_high20_chain3 : 8, - rssi_ext40_low20_chain3 : 8, - rssi_ext20_chain3 : 8, - rssi_pri20_chain3 : 8; - uint32_t rssi_ext80_high20_chain3 : 8, - rssi_ext80_high_low20_chain3 : 8, - rssi_ext80_low_high20_chain3 : 8, - rssi_ext80_low20_chain3 : 8; - uint32_t rssi_ext160_3_chain3 : 8, - rssi_ext160_2_chain3 : 8, - rssi_ext160_1_chain3 : 8, - rssi_ext160_0_chain3 : 8; - uint32_t rssi_ext160_7_chain3 : 8, - rssi_ext160_6_chain3 : 8, - rssi_ext160_5_chain3 : 8, - rssi_ext160_4_chain3 : 8; -#endif -}; - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/receive_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/receive_user_info.h deleted file mode 100644 index 23daabab5dc8..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/receive_user_info.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_USER_INFO_H_ -#define _RECEIVE_USER_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8 - -struct receive_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - user_rssi : 8, - pkt_type : 4, - stbc : 1, - reception_type : 3; - uint32_t rate_mcs : 5, - sgi : 2, - __reserved_g_0004 : 1, - mimo_ss_bitmap : 8, - receive_bandwidth : 3, - reserved_1b : 5, - dl_ofdma_user_index : 8; - uint32_t dl_ofdma_content_channel : 1, - reserved_2a : 1, - qam_diff1 : 2, - qam_diff2 : 2, - qam_diff3 : 2, - nss : 3, - stream_offset : 3, - sta_dcm : 1, - ldpc : 1, - ru_type_80_0 : 4, - ru_type_80_1 : 4, - ru_type_80_2 : 4, - ru_type_80_3 : 4; - uint32_t ru_start_index_80_0 : 6, - reserved_3a : 2, - ru_start_index_80_1 : 6, - reserved_3b : 2, - ru_start_index_80_2 : 6, - reserved_3c : 2, - ru_start_index_80_3 : 6, - reserved_3d : 2; - uint32_t user_fd_rssi_seg0 : 32; - uint32_t user_fd_rssi_seg1 : 32; - uint32_t user_fd_rssi_seg2 : 32; - uint32_t user_fd_rssi_seg3 : 32; -#else - uint32_t reception_type : 3, - stbc : 1, - pkt_type : 4, - user_rssi : 8, - phy_ppdu_id : 16; - uint32_t dl_ofdma_user_index : 8, - reserved_1b : 5, - receive_bandwidth : 3, - mimo_ss_bitmap : 8, - __reserved_g_0004 : 1, - sgi : 2, - rate_mcs : 5; - uint32_t ru_type_80_3 : 4, - ru_type_80_2 : 4, - ru_type_80_1 : 4, - ru_type_80_0 : 4, - ldpc : 1, - sta_dcm : 1, - stream_offset : 3, - nss : 3, - qam_diff3 : 2, - qam_diff2 : 2, - qam_diff1 : 2, - reserved_2a : 1, - dl_ofdma_content_channel : 1; - uint32_t reserved_3d : 2, - ru_start_index_80_3 : 6, - reserved_3c : 2, - ru_start_index_80_2 : 6, - reserved_3b : 2, - ru_start_index_80_1 : 6, - reserved_3a : 2, - ru_start_index_80_0 : 6; - uint32_t user_fd_rssi_seg0 : 32; - uint32_t user_fd_rssi_seg1 : 32; - uint32_t user_fd_rssi_seg2 : 32; - uint32_t user_fd_rssi_seg3 : 32; -#endif -}; - -#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff - -#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_USER_RSSI_LSB 16 -#define RECEIVE_USER_INFO_USER_RSSI_MSB 23 -#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 - -#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 -#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 -#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 - -#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_STBC_LSB 28 -#define RECEIVE_USER_INFO_STBC_MSB 28 -#define RECEIVE_USER_INFO_STBC_MASK 0x10000000 - -#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 - -#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RATE_MCS_LSB 0 -#define RECEIVE_USER_INFO_RATE_MCS_MSB 4 -#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000001f - -#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_SGI_LSB 5 -#define RECEIVE_USER_INFO_SGI_MSB 6 -#define RECEIVE_USER_INFO_SGI_MASK 0x00000060 - -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 - -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 - -#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 -#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 -#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 - -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 - -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 - -#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 -#define RECEIVE_USER_INFO_RESERVED_2A_MSB 1 -#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x00000002 - -#define RECEIVE_USER_INFO_QAM_DIFF1_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF1_LSB 2 -#define RECEIVE_USER_INFO_QAM_DIFF1_MSB 3 -#define RECEIVE_USER_INFO_QAM_DIFF1_MASK 0x0000000c - -#define RECEIVE_USER_INFO_QAM_DIFF2_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF2_LSB 4 -#define RECEIVE_USER_INFO_QAM_DIFF2_MSB 5 -#define RECEIVE_USER_INFO_QAM_DIFF2_MASK 0x00000030 - -#define RECEIVE_USER_INFO_QAM_DIFF3_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF3_LSB 6 -#define RECEIVE_USER_INFO_QAM_DIFF3_MSB 7 -#define RECEIVE_USER_INFO_QAM_DIFF3_MASK 0x000000c0 - -#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_NSS_LSB 8 -#define RECEIVE_USER_INFO_NSS_MSB 10 -#define RECEIVE_USER_INFO_NSS_MASK 0x00000700 - -#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 -#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 -#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 - -#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_STA_DCM_LSB 14 -#define RECEIVE_USER_INFO_STA_DCM_MSB 14 -#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 - -#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_LDPC_LSB 15 -#define RECEIVE_USER_INFO_LDPC_MSB 15 -#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f - -#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 -#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 -#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 - -#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 -#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 -#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 - -#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 -#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 -#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 - -#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30 -#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 -#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000 - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_15_8.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_15_8.h deleted file mode 100644 index 6cf8117ff02f..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_15_8.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ -#define _RECEIVED_RESPONSE_USER_15_8_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32 - -struct received_response_user_15_8 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user8; - struct received_response_user_info received_response_details_user9; - struct received_response_user_info received_response_details_user10; - struct received_response_user_info received_response_details_user11; - struct received_response_user_info received_response_details_user12; - struct received_response_user_info received_response_details_user13; - struct received_response_user_info received_response_details_user14; - struct received_response_user_info received_response_details_user15; -#else - struct received_response_user_info received_response_details_user8; - struct received_response_user_info received_response_details_user9; - struct received_response_user_info received_response_details_user10; - struct received_response_user_info received_response_details_user11; - struct received_response_user_info received_response_details_user12; - struct received_response_user_info received_response_details_user13; - struct received_response_user_info received_response_details_user14; - struct received_response_user_info received_response_details_user15; -#endif -}; - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_23_16.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_23_16.h deleted file mode 100644 index ff56f4d96472..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_23_16.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ -#define _RECEIVED_RESPONSE_USER_23_16_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32 - -struct received_response_user_23_16 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user16; - struct received_response_user_info received_response_details_user17; - struct received_response_user_info received_response_details_user18; - struct received_response_user_info received_response_details_user19; - struct received_response_user_info received_response_details_user20; - struct received_response_user_info received_response_details_user21; - struct received_response_user_info received_response_details_user22; - struct received_response_user_info received_response_details_user23; -#else - struct received_response_user_info received_response_details_user16; - struct received_response_user_info received_response_details_user17; - struct received_response_user_info received_response_details_user18; - struct received_response_user_info received_response_details_user19; - struct received_response_user_info received_response_details_user20; - struct received_response_user_info received_response_details_user21; - struct received_response_user_info received_response_details_user22; - struct received_response_user_info received_response_details_user23; -#endif -}; - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_31_24.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_31_24.h deleted file mode 100644 index aaa90838daa9..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_31_24.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ -#define _RECEIVED_RESPONSE_USER_31_24_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32 - -struct received_response_user_31_24 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user24; - struct received_response_user_info received_response_details_user25; - struct received_response_user_info received_response_details_user26; - struct received_response_user_info received_response_details_user27; - struct received_response_user_info received_response_details_user28; - struct received_response_user_info received_response_details_user29; - struct received_response_user_info received_response_details_user30; - struct received_response_user_info received_response_details_user31; -#else - struct received_response_user_info received_response_details_user24; - struct received_response_user_info received_response_details_user25; - struct received_response_user_info received_response_details_user26; - struct received_response_user_info received_response_details_user27; - struct received_response_user_info received_response_details_user28; - struct received_response_user_info received_response_details_user29; - struct received_response_user_info received_response_details_user30; - struct received_response_user_info received_response_details_user31; -#endif -}; - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_36_32.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_36_32.h deleted file mode 100644 index 3f33fdab635e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_36_32.h +++ /dev/null @@ -1,705 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ -#define _RECEIVED_RESPONSE_USER_36_32_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20 - -struct received_response_user_36_32 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user32; - struct received_response_user_info received_response_details_user33; - struct received_response_user_info received_response_details_user34; - struct received_response_user_info received_response_details_user35; - struct received_response_user_info received_response_details_user36; -#else - struct received_response_user_info received_response_details_user32; - struct received_response_user_info received_response_details_user33; - struct received_response_user_info received_response_details_user34; - struct received_response_user_info received_response_details_user35; - struct received_response_user_info received_response_details_user36; -#endif -}; - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_7_0.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_7_0.h deleted file mode 100644 index f785aca46840..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_7_0.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ -#define _RECEIVED_RESPONSE_USER_7_0_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32 - -struct received_response_user_7_0 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user0; - struct received_response_user_info received_response_details_user1; - struct received_response_user_info received_response_details_user2; - struct received_response_user_info received_response_details_user3; - struct received_response_user_info received_response_details_user4; - struct received_response_user_info received_response_details_user5; - struct received_response_user_info received_response_details_user6; - struct received_response_user_info received_response_details_user7; -#else - struct received_response_user_info received_response_details_user0; - struct received_response_user_info received_response_details_user1; - struct received_response_user_info received_response_details_user2; - struct received_response_user_info received_response_details_user3; - struct received_response_user_info received_response_details_user4; - struct received_response_user_info received_response_details_user5; - struct received_response_user_info received_response_details_user6; - struct received_response_user_info received_response_details_user7; -#endif -}; - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_info.h deleted file mode 100644 index 3c3faf119635..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_info.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ -#define _RECEIVED_RESPONSE_USER_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 - -struct received_response_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mpdu_fcs_pass_count : 12, - mpdu_fcs_fail_count : 12, - qosnull_frame_count : 4, - reserved_0a : 3, - user_info_valid : 1; - uint32_t null_delimiter_count : 22, - reserved_1a : 9, - ht_control_valid : 1; - uint32_t ht_control : 32; - uint32_t qos_control_valid : 16, - eosp : 16; - uint32_t qos_control_15_8_tid_0 : 8, - qos_control_15_8_tid_1 : 8, - qos_control_15_8_tid_2 : 8, - qos_control_15_8_tid_3 : 8; - uint32_t qos_control_15_8_tid_4 : 8, - qos_control_15_8_tid_5 : 8, - qos_control_15_8_tid_6 : 8, - qos_control_15_8_tid_7 : 8; - uint32_t qos_control_15_8_tid_8 : 8, - qos_control_15_8_tid_9 : 8, - qos_control_15_8_tid_10 : 8, - qos_control_15_8_tid_11 : 8; - uint32_t qos_control_15_8_tid_12 : 8, - qos_control_15_8_tid_13 : 8, - qos_control_15_8_tid_14 : 8, - qos_control_15_8_tid_15 : 8; -#else - uint32_t user_info_valid : 1, - reserved_0a : 3, - qosnull_frame_count : 4, - mpdu_fcs_fail_count : 12, - mpdu_fcs_pass_count : 12; - uint32_t ht_control_valid : 1, - reserved_1a : 9, - null_delimiter_count : 22; - uint32_t ht_control : 32; - uint32_t eosp : 16, - qos_control_valid : 16; - uint32_t qos_control_15_8_tid_3 : 8, - qos_control_15_8_tid_2 : 8, - qos_control_15_8_tid_1 : 8, - qos_control_15_8_tid_0 : 8; - uint32_t qos_control_15_8_tid_7 : 8, - qos_control_15_8_tid_6 : 8, - qos_control_15_8_tid_5 : 8, - qos_control_15_8_tid_4 : 8; - uint32_t qos_control_15_8_tid_11 : 8, - qos_control_15_8_tid_10 : 8, - qos_control_15_8_tid_9 : 8, - qos_control_15_8_tid_8 : 8; - uint32_t qos_control_15_8_tid_15 : 8, - qos_control_15_8_tid_14 : 8, - qos_control_15_8_tid_13 : 8, - qos_control_15_8_tid_12 : 8; -#endif -}; - -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff - -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 - -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 - -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 - -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 - -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff - -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 - -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 - -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff - -#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c -#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info.h deleted file mode 100644 index ff464f4e3bb5..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_TRIGGER_INFO_H_ -#define _RECEIVED_TRIGGER_INFO_H_ - -#include "received_trigger_info_details.h" -#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6 - -#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3 - -struct received_trigger_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_trigger_info_details received_trigger_details; -#else - struct received_trigger_info_details received_trigger_details; -#endif -}; - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB 29 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB 30 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK 0x0000000060000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x0000000080000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_LSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MASK 0x2000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x4000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0x8000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 48 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 56 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xc000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x0000000100000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 33 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 36 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 37 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 39 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_LSB 40 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MASK 0xffffff0000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info_details.h deleted file mode 100644 index ae169bca026b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info_details.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ -#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ - -#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 6 - -struct received_trigger_info_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t trigger_type : 4, - ax_trigger_source : 1, - ax_trigger_type : 4, - trigger_source_sta_full_aid : 13, - frame_control_valid : 1, - qos_control_valid : 1, - he_control_info_valid : 1, - __reserved_g_0005_trigger_subtype : 4, - txop_sharing_mode : 2, - tid_aggregation_limit_is_zero : 1; - uint32_t phy_ppdu_id : 16, - lsig_response_length : 12, - __reserved_g_0086 : 1, - scsid_valid : 1, - ects_as_tb_ppdu : 1, - reserved_1a : 1; - uint32_t frame_control : 16, - qos_control : 16; - uint32_t sw_peer_id : 16, - txop_sharing_allocation_duration : 9, - __reserved_g_0074 : 4, - __reserved_g_0034 : 1, - reserved_3a : 2; - uint32_t he_control : 32; - uint32_t txop_sharing_duration_from_durid : 1, - frame_durationid_lower_4 : 4, - frame_durationid_upper_3 : 3, - reserved_5a : 24; -#else - uint32_t tid_aggregation_limit_is_zero : 1, - txop_sharing_mode : 2, - __reserved_g_0005_trigger_subtype : 4, - he_control_info_valid : 1, - qos_control_valid : 1, - frame_control_valid : 1, - trigger_source_sta_full_aid : 13, - ax_trigger_type : 4, - ax_trigger_source : 1, - trigger_type : 4; - uint32_t reserved_1a : 1, - ects_as_tb_ppdu : 1, - scsid_valid : 1, - __reserved_g_0086 : 1, - lsig_response_length : 12, - phy_ppdu_id : 16; - uint32_t qos_control : 16, - frame_control : 16; - uint32_t reserved_3a : 2, - __reserved_g_0034 : 1, - __reserved_g_0074 : 4, - txop_sharing_allocation_duration : 9, - sw_peer_id : 16; - uint32_t he_control : 32; - uint32_t reserved_5a : 24, - frame_durationid_upper_3 : 3, - frame_durationid_lower_4 : 4, - txop_sharing_duration_from_durid : 1; -#endif -}; - -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f - -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 - -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MASK 0x20000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_LSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MASK 0x40000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0x80000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xc0000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x00000001 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 1 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 5 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 7 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e0 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_LSB 8 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MASK 0xffffff00 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring.h deleted file mode 100644 index 5147635121c1..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_DESTINATION_RING_H_ -#define _REO_DESTINATION_RING_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_mpdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_REO_DESTINATION_RING 8 - -struct reo_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t release_source_module : 3, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_delink_error : 1, - sw_buffer_cookie : 20; - uint32_t msdu_link_desc_index : 4, - reserved_6a : 28; - uint32_t reo_dest_buffer_type : 1, - reo_push_reason : 2, - reo_error_code : 5, - captured_msdu_data_size : 4, - sw_exception : 1, - src_link_id : 3, - reo_destination_struct_signature : 4, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t sw_buffer_cookie : 20, - reo_delink_error : 1, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - release_source_module : 3; - uint32_t reserved_6a : 28, - msdu_link_desc_index : 4; - uint32_t looping_count : 4, - ring_id : 8, - reo_destination_struct_signature : 4, - src_link_id : 3, - sw_exception : 1, - captured_msdu_data_size : 4, - reo_error_code : 5, - reo_push_reason : 2, - reo_dest_buffer_type : 1; -#endif -}; - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_LSB 3 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MSB 3 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MASK 0x00000008 - -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_LSB 4 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MSB 5 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MASK 0x00000030 - -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_LSB 6 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MSB 10 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MASK 0x000007c0 - -#define REO_DESTINATION_RING_REO_DELINK_ERROR_OFFSET 0x00000014 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_LSB 11 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_MSB 11 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_MASK 0x00000800 - -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_LSB 0 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MSB 3 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MASK 0x0000000f - -#define REO_DESTINATION_RING_RESERVED_6A_OFFSET 0x00000018 -#define REO_DESTINATION_RING_RESERVED_6A_LSB 4 -#define REO_DESTINATION_RING_RESERVED_6A_MSB 31 -#define REO_DESTINATION_RING_RESERVED_6A_MASK 0xfffffff0 - -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 - -#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 -#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 -#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 - -#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 -#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 -#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 - -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 - -#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c -#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 -#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 -#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 - -#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 -#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 -#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 - -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 - -#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_RING_ID_LSB 20 -#define REO_DESTINATION_RING_RING_ID_MSB 27 -#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 - -#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 -#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 -#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring_with_pn.h b/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring_with_pn.h deleted file mode 100644 index b486a8658388..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring_with_pn.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_DESTINATION_RING_WITH_PN_H_ -#define _REO_DESTINATION_RING_WITH_PN_H_ - -#include "rx_msdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8 - -struct reo_destination_ring_with_pn { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - uint32_t msdu_count : 8, - prev_pn_23_0 : 24; - uint32_t prev_pn_47_24 : 24, - prev_pn_127_48_info : 2, - reserved_3a : 6; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t release_source_module : 3, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_delink_error : 1, - sw_buffer_cookie : 20; - uint32_t msdu_link_desc_index : 4, - reserved_6a : 28; - uint32_t reo_dest_buffer_type : 1, - reo_push_reason : 2, - reo_error_code : 5, - captured_msdu_data_size : 4, - sw_exception : 1, - src_link_id : 3, - reo_destination_struct_signature : 4, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - uint32_t prev_pn_23_0 : 24, - msdu_count : 8; - uint32_t reserved_3a : 6, - prev_pn_127_48_info : 2, - prev_pn_47_24 : 24; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t sw_buffer_cookie : 20, - reo_delink_error : 1, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - release_source_module : 3; - uint32_t reserved_6a : 28, - msdu_link_desc_index : 4; - uint32_t looping_count : 4, - ring_id : 8, - reo_destination_struct_signature : 4, - src_link_id : 3, - sw_exception : 1, - captured_msdu_data_size : 4, - reo_error_code : 5, - reo_push_reason : 2, - reo_dest_buffer_type : 1; -#endif -}; - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00 - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MSB 23 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MASK 0x00ffffff - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_LSB 24 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MSB 25 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MASK 0x03000000 - -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_LSB 26 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MASK 0xfc000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MSB 3 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MASK 0x00000008 - -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_LSB 4 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MSB 5 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MASK 0x00000030 - -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_LSB 6 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MSB 10 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MASK 0x000007c0 - -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_LSB 11 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MASK 0x00000800 - -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MSB 3 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MASK 0x0000000f - -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_OFFSET 0x00000018 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_LSB 4 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MASK 0xfffffff0 - -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0 -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001 - -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1 -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006 - -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8 - -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 - -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000 - -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13 -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15 -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000 - -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 - -#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20 -#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27 -#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000 - -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28 -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/reo_entrance_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/reo_entrance_ring.h deleted file mode 100644 index 17a68d08ce25..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/reo_entrance_ring.h +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_ENTRANCE_RING_H_ -#define _REO_ENTRANCE_RING_H_ - -#include "rx_mpdu_details.h" -#define NUM_OF_DWORDS_REO_ENTRANCE_RING 12 - -struct reo_entrance_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_mpdu_details reo_level_mpdu_frame_info; - uint32_t rx_preamble_timestamp : 32; - uint32_t reserved_7a : 8, - rounded_mpdu_byte_count : 14, - reo_destination_indication : 5, - frameless_bar : 1, - reserved_7b : 4; - uint32_t rxdma_push_reason : 2, - rxdma_error_code : 5, - mpdu_fragment_number : 4, - sw_exception : 1, - sw_exception_mpdu_delink : 1, - sw_exception_destination_ring_valid : 1, - sw_exception_destination_ring : 5, - mpdu_sequence_number : 12, - no_ack : 1; - uint32_t phy_ppdu_id : 16, - src_link_id : 3, - reserved_9a : 5, - rx_reo_queue_desc_addr_39_32 : 8; - uint32_t receive_queue_number : 16, - fw_reorder_push_reason : 2, - fw_reorder_error_code : 5, - reo_bypass : 1, - reserved_10a : 8; - uint32_t phy_lmac_latency : 16, - reserved_15a : 4, - ring_id : 8, - looping_count : 4; -#else - struct rx_mpdu_details reo_level_mpdu_frame_info; - uint32_t rx_preamble_timestamp : 32; - uint32_t reserved_7b : 4, - frameless_bar : 1, - reo_destination_indication : 5, - rounded_mpdu_byte_count : 14, - reserved_7a : 8; - uint32_t no_ack : 1, - mpdu_sequence_number : 12, - sw_exception_destination_ring : 5, - sw_exception_destination_ring_valid : 1, - sw_exception_mpdu_delink : 1, - sw_exception : 1, - mpdu_fragment_number : 4, - rxdma_error_code : 5, - rxdma_push_reason : 2; - uint32_t rx_reo_queue_desc_addr_39_32 : 8, - reserved_9a : 5, - src_link_id : 3, - phy_ppdu_id : 16; - uint32_t reserved_10a : 8, - reo_bypass : 1, - fw_reorder_error_code : 5, - fw_reorder_push_reason : 2, - receive_queue_number : 16; - uint32_t looping_count : 4, - ring_id : 8, - reserved_15a : 4, - phy_lmac_latency : 16; -#endif -}; - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000 - -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_OFFSET 0x00000018 -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_LSB 0 -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MSB 31 -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_RESERVED_7A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_7A_MSB 7 -#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x000000ff - -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 - -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 - -#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 -#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 -#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 - -#define REO_ENTRANCE_RING_RESERVED_7B_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_RESERVED_7B_LSB 28 -#define REO_ENTRANCE_RING_RESERVED_7B_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_7B_MASK 0xf0000000 - -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 - -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c - -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 - -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 - -#define REO_ENTRANCE_RING_NO_ACK_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_NO_ACK_LSB 31 -#define REO_ENTRANCE_RING_NO_ACK_MSB 31 -#define REO_ENTRANCE_RING_NO_ACK_MASK 0x80000000 - -#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 -#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 -#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 - -#define REO_ENTRANCE_RING_RESERVED_9A_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_RESERVED_9A_LSB 19 -#define REO_ENTRANCE_RING_RESERVED_9A_MSB 23 -#define REO_ENTRANCE_RING_RESERVED_9A_MASK 0x00f80000 - -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 24 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 31 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0xff000000 - -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_LSB 0 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MSB 15 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_LSB 16 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MSB 17 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MASK 0x00030000 - -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_LSB 18 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MSB 22 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MASK 0x007c0000 - -#define REO_ENTRANCE_RING_REO_BYPASS_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_REO_BYPASS_LSB 23 -#define REO_ENTRANCE_RING_REO_BYPASS_MSB 23 -#define REO_ENTRANCE_RING_REO_BYPASS_MASK 0x00800000 - -#define REO_ENTRANCE_RING_RESERVED_10A_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_RESERVED_10A_LSB 24 -#define REO_ENTRANCE_RING_RESERVED_10A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_10A_MASK 0xff000000 - -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_LSB 0 -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MSB 15 -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_RESERVED_15A_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_RESERVED_15A_LSB 16 -#define REO_ENTRANCE_RING_RESERVED_15A_MSB 19 -#define REO_ENTRANCE_RING_RESERVED_15A_MASK 0x000f0000 - -#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_RING_ID_LSB 20 -#define REO_ENTRANCE_RING_RING_ID_MSB 27 -#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 - -#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 -#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 -#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/response_end_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/response_end_status.h deleted file mode 100644 index 20f72c890ffe..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/response_end_status.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RESPONSE_END_STATUS_H_ -#define _RESPONSE_END_STATUS_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10 - -#define NUM_OF_QWORDS_RESPONSE_END_STATUS 5 - -struct response_end_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0072 : 1, - __reserved_g_0065 : 1, - __reserved_g_0062 : 1, - global_data_underflow_warning : 1, - response_transmit_status : 4, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - generated_response : 3, - mba_user_count : 7, - mba_fake_bitmap_count : 7, - coex_based_tx_bw : 3, - trig_response_related : 1, - __reserved_g_0086 : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t cbf_segment_request_mask : 8, - cbf_segment_sent_mask : 8; - uint32_t underflow_mpdu_count : 9, - data_underflow_warning : 2, - reserved_2b : 10, - only_null_delim_sent : 1, - brp_info_valid : 1, - __reserved_g_0067 : 1, - __reserved_g_0069 : 1, - __reserved_g_0051 : 1, - __reserved_g_0049 : 1, - __reserved_g_0047 : 1, - __reserved_g_0045 : 1, - __reserved_g_0043 : 1, - __reserved_g_0041 : 1, - __reserved_g_0030 : 1; - uint32_t mu_response_bitmap_31_0 : 32; - uint32_t mu_response_bitmap_36_32 : 5, - overwritten_blackout_window_bitmap : 4, - mic_overwritten : 1, - trig_resp_cmd_found : 1, - reserved_4a : 21; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t addr3_47_32 : 16, - __reserved_g_0005 : 1, - secure : 1, - __reserved_g_0005_ftm_frame_sent : 1, - reserved_20a : 13; -#else - uint32_t __reserved_g_0086 : 1, - trig_response_related : 1, - coex_based_tx_bw : 3, - mba_fake_bitmap_count : 7, - mba_user_count : 7, - generated_response : 3, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - response_transmit_status : 4, - global_data_underflow_warning : 1, - __reserved_g_0062 : 1, - __reserved_g_0065 : 1, - __reserved_g_0072 : 1; - uint32_t cbf_segment_sent_mask : 8, - cbf_segment_request_mask : 8; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t __reserved_g_0030 : 1, - __reserved_g_0041 : 1, - __reserved_g_0043 : 1, - __reserved_g_0045 : 1, - __reserved_g_0047 : 1, - __reserved_g_0049 : 1, - __reserved_g_0051 : 1, - __reserved_g_0069 : 1, - __reserved_g_0067 : 1, - brp_info_valid : 1, - only_null_delim_sent : 1, - reserved_2b : 10, - data_underflow_warning : 2, - underflow_mpdu_count : 9; - uint32_t mu_response_bitmap_31_0 : 32; - uint32_t reserved_4a : 21, - trig_resp_cmd_found : 1, - mic_overwritten : 1, - overwritten_blackout_window_bitmap : 4, - mu_response_bitmap_36_32 : 5; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t reserved_20a : 13, - __reserved_g_0005_ftm_frame_sent : 1, - secure : 1, - __reserved_g_0005 : 1, - addr3_47_32 : 16; -#endif -}; - -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 - -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 - -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 - -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 - -#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 - -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 - -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 - -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 - -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 - -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff - -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 - -#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_RESERVED_2B_LSB 11 -#define RESPONSE_END_STATUS_RESERVED_2B_MSB 20 -#define RESPONSE_END_STATUS_RESERVED_2B_MASK 0x00000000001ff800 - -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 - -#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 - -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f - -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_LSB 5 -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MSB 8 -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MASK 0x00000000000001e0 - -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_LSB 9 -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MSB 9 -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MASK 0x0000000000000200 - -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_LSB 10 -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MSB 10 -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MASK 0x0000000000000400 - -#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_RESERVED_4A_LSB 11 -#define RESPONSE_END_STATUS_RESERVED_4A_MSB 31 -#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x00000000fffff800 - -#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 32 -#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 63 -#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 0 -#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 15 -#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x000000000000ffff - -#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 16 -#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 31 -#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0x00000000ffff0000 - -#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 32 -#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 63 -#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 0 -#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 31 -#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0x00000000ffffffff - -#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 32 -#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 47 -#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x0000ffff00000000 - -#define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_SECURE_LSB 49 -#define RESPONSE_END_STATUS_SECURE_MSB 49 -#define RESPONSE_END_STATUS_SECURE_MASK 0x0002000000000000 - -#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_RESERVED_20A_LSB 51 -#define RESPONSE_END_STATUS_RESERVED_20A_MSB 63 -#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0xfff8000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/response_start_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/response_start_status.h deleted file mode 100644 index 0a3090f219fe..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/response_start_status.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RESPONSE_START_STATUS_H_ -#define _RESPONSE_START_STATUS_H_ - -#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 - -#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 - -struct response_start_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t generated_response : 3, - __reserved_g_0012 : 2, - trig_response_related : 1, - response_sta_count : 7, - mba_for_cfp_ba : 1, - mba_for_cfp_ack : 1, - ects_response_type : 2, - eba_response_type : 2, - cfp_mba : 1, - mba_for_ll_ack : 1, - mba_for_ll_ba : 1, - reserved : 10; - uint32_t phy_ppdu_id : 16, - sw_peer_id : 16; -#else - uint32_t reserved : 10, - mba_for_ll_ba : 1, - mba_for_ll_ack : 1, - cfp_mba : 1, - eba_response_type : 2, - ects_response_type : 2, - mba_for_cfp_ack : 1, - mba_for_cfp_ba : 1, - response_sta_count : 7, - trig_response_related : 1, - __reserved_g_0012 : 2, - generated_response : 3; - uint32_t sw_peer_id : 16, - phy_ppdu_id : 16; -#endif -}; - -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 - -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 - -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 - -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_LSB 13 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_MSB 13 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_MASK 0x0000000000002000 - -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_LSB 14 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_MSB 14 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_MASK 0x0000000000004000 - -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_LSB 15 -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_MSB 16 -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_MASK 0x0000000000018000 - -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_LSB 17 -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_MSB 18 -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_MASK 0x0000000000060000 - -#define RESPONSE_START_STATUS_CFP_MBA_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_CFP_MBA_LSB 19 -#define RESPONSE_START_STATUS_CFP_MBA_MSB 19 -#define RESPONSE_START_STATUS_CFP_MBA_MASK 0x0000000000080000 - -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_LSB 20 -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_MSB 20 -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_MASK 0x0000000000100000 - -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_LSB 21 -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_MSB 21 -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_MASK 0x0000000000200000 - -#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_RESERVED_LSB 22 -#define RESPONSE_START_STATUS_RESERVED_MSB 31 -#define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffc00000 - -#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 - -#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 -#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 -#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/ru_allocation_160_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/ru_allocation_160_info.h deleted file mode 100644 index 57d51dc44f8a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/ru_allocation_160_info.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RU_ALLOCATION_160_INFO_H_ -#define _RU_ALLOCATION_160_INFO_H_ - -#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 - -struct ru_allocation_160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_allocation_band0_0 : 9, - ru_allocation_band0_1 : 9, - reserved_0a : 6, - ru_allocations_01_subband80_mask : 4, - ru_allocations_23_subband80_mask : 4; - uint32_t ru_allocation_band0_2 : 9, - ru_allocation_band0_3 : 9, - reserved_1a : 14; - uint32_t ru_allocation_band1_0 : 9, - ru_allocation_band1_1 : 9, - reserved_2a : 14; - uint32_t ru_allocation_band1_2 : 9, - ru_allocation_band1_3 : 9, - reserved_3a : 14; -#else - uint32_t ru_allocations_23_subband80_mask : 4, - ru_allocations_01_subband80_mask : 4, - reserved_0a : 6, - ru_allocation_band0_1 : 9, - ru_allocation_band0_0 : 9; - uint32_t reserved_1a : 14, - ru_allocation_band0_3 : 9, - ru_allocation_band0_2 : 9; - uint32_t reserved_2a : 14, - ru_allocation_band1_1 : 9, - ru_allocation_band1_0 : 9; - uint32_t reserved_3a : 14, - ru_allocation_band1_3 : 9, - ru_allocation_band1_2 : 9; -#endif -}; - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_attention.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_attention.h deleted file mode 100644 index cac7c2fb52c3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_attention.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_ATTENTION_H_ -#define _RX_ATTENTION_H_ - -#define NUM_OF_DWORDS_RX_ATTENTION 4 - -#define NUM_OF_QWORDS_RX_ATTENTION 2 - -struct rx_attention { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t first_mpdu : 1, - reserved_1a : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - a_msdu_error : 1, - fragment_flag : 1, - order : 1, - cce_match : 1, - overflow_err : 1, - msdu_length_err : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - sa_idx_invalid : 1, - da_idx_invalid : 1, - reserved_1b : 1, - rx_in_tx_decrypt_byp : 1, - encrypt_required : 1, - directed : 1, - buffer_fragment : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - fcs_err : 1; - uint32_t flow_idx_timeout : 1, - flow_idx_invalid : 1, - wifi_parser_error : 1, - amsdu_parser_error : 1, - sa_idx_timeout : 1, - da_idx_timeout : 1, - msdu_limit_error : 1, - da_is_valid : 1, - da_is_mcbc : 1, - sa_is_valid : 1, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - reserved_2 : 17, - msdu_done : 1; - uint32_t tlv64_padding : 32; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t fcs_err : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - buffer_fragment : 1, - directed : 1, - encrypt_required : 1, - rx_in_tx_decrypt_byp : 1, - reserved_1b : 1, - da_idx_invalid : 1, - sa_idx_invalid : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - msdu_length_err : 1, - overflow_err : 1, - cce_match : 1, - order : 1, - fragment_flag : 1, - a_msdu_error : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - reserved_1a : 1, - first_mpdu : 1; - uint32_t msdu_done : 1, - reserved_2 : 17, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - sa_is_valid : 1, - da_is_mcbc : 1, - da_is_valid : 1, - msdu_limit_error : 1, - da_idx_timeout : 1, - sa_idx_timeout : 1, - amsdu_parser_error : 1, - wifi_parser_error : 1, - flow_idx_invalid : 1, - flow_idx_timeout : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_0_LSB 9 -#define RX_ATTENTION_RESERVED_0_MSB 15 -#define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_PHY_PPDU_ID_LSB 16 -#define RX_ATTENTION_PHY_PPDU_ID_MSB 31 -#define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FIRST_MPDU_LSB 32 -#define RX_ATTENTION_FIRST_MPDU_MSB 32 -#define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 - -#define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_1A_LSB 33 -#define RX_ATTENTION_RESERVED_1A_MSB 33 -#define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 - -#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MCAST_BCAST_LSB 34 -#define RX_ATTENTION_MCAST_BCAST_MSB 34 -#define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 - -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 - -#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 - -#define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_POWER_MGMT_LSB 37 -#define RX_ATTENTION_POWER_MGMT_MSB 37 -#define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 - -#define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 -#define RX_ATTENTION_NON_QOS_LSB 38 -#define RX_ATTENTION_NON_QOS_MSB 38 -#define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 - -#define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 -#define RX_ATTENTION_NULL_DATA_LSB 39 -#define RX_ATTENTION_NULL_DATA_MSB 39 -#define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 - -#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MGMT_TYPE_LSB 40 -#define RX_ATTENTION_MGMT_TYPE_MSB 40 -#define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 - -#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 -#define RX_ATTENTION_CTRL_TYPE_LSB 41 -#define RX_ATTENTION_CTRL_TYPE_MSB 41 -#define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 - -#define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MORE_DATA_LSB 42 -#define RX_ATTENTION_MORE_DATA_MSB 42 -#define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 - -#define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 -#define RX_ATTENTION_EOSP_LSB 43 -#define RX_ATTENTION_EOSP_MSB 43 -#define RX_ATTENTION_EOSP_MASK 0x0000080000000000 - -#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_A_MSDU_ERROR_LSB 44 -#define RX_ATTENTION_A_MSDU_ERROR_MSB 44 -#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 - -#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 -#define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 -#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 - -#define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 -#define RX_ATTENTION_ORDER_LSB 46 -#define RX_ATTENTION_ORDER_MSB 46 -#define RX_ATTENTION_ORDER_MASK 0x0000400000000000 - -#define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 -#define RX_ATTENTION_CCE_MATCH_LSB 47 -#define RX_ATTENTION_CCE_MATCH_MSB 47 -#define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 - -#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_OVERFLOW_ERR_LSB 48 -#define RX_ATTENTION_OVERFLOW_ERR_MSB 48 -#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 - -#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 -#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 -#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 - -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 - -#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 -#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 -#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 -#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 - -#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_SA_IDX_INVALID_LSB 52 -#define RX_ATTENTION_SA_IDX_INVALID_MSB 52 -#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 - -#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DA_IDX_INVALID_LSB 53 -#define RX_ATTENTION_DA_IDX_INVALID_MSB 53 -#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 - -#define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_1B_LSB 54 -#define RX_ATTENTION_RESERVED_1B_MSB 54 -#define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 - -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 - -#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 -#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 -#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 -#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 - -#define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DIRECTED_LSB 57 -#define RX_ATTENTION_DIRECTED_MSB 57 -#define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 - -#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 -#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 -#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 - -#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 -#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 -#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 - -#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 -#define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 -#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 - -#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DECRYPT_ERR_LSB 61 -#define RX_ATTENTION_DECRYPT_ERR_MSB 61 -#define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 - -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 - -#define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FCS_ERR_LSB 63 -#define RX_ATTENTION_FCS_ERR_MSB 63 -#define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 - -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 - -#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 -#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 -#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 - -#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 -#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 -#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 - -#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 - -#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 -#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 -#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 - -#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 -#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 -#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 - -#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 - -#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IS_VALID_LSB 7 -#define RX_ATTENTION_DA_IS_VALID_MSB 7 -#define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 - -#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IS_MCBC_LSB 8 -#define RX_ATTENTION_DA_IS_MCBC_MSB 8 -#define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 - -#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_SA_IS_VALID_LSB 9 -#define RX_ATTENTION_SA_IS_VALID_MSB 9 -#define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 - -#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 - -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 - -#define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 -#define RX_ATTENTION_RESERVED_2_LSB 14 -#define RX_ATTENTION_RESERVED_2_MSB 30 -#define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 - -#define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 -#define RX_ATTENTION_MSDU_DONE_LSB 31 -#define RX_ATTENTION_MSDU_DONE_MSB 31 -#define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 - -#define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 -#define RX_ATTENTION_TLV64_PADDING_LSB 32 -#define RX_ATTENTION_TLV64_PADDING_MSB 63 -#define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_flow_search_entry.h deleted file mode 100644 index 25f1f81c439f..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_flow_search_entry.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FLOW_SEARCH_ENTRY_H_ -#define _RX_FLOW_SEARCH_ENTRY_H_ - -#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 - -struct rx_flow_search_entry { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t src_ip_127_96 : 32; - uint32_t src_ip_95_64 : 32; - uint32_t src_ip_63_32 : 32; - uint32_t src_ip_31_0 : 32; - uint32_t dest_ip_127_96 : 32; - uint32_t dest_ip_95_64 : 32; - uint32_t dest_ip_63_32 : 32; - uint32_t dest_ip_31_0 : 32; - uint32_t src_port : 16, - dest_port : 16; - uint32_t l4_protocol : 8, - valid : 1, - reserved_9 : 4, - service_code : 9, - priority_valid : 1, - use_ppe : 1, - reo_destination_indication : 5, - msdu_drop : 1, - reo_destination_handler : 2; - uint32_t metadata : 32; - uint32_t aggregation_count : 7, - lro_eligible : 1, - msdu_count : 24; - uint32_t msdu_byte_count : 32; - uint32_t timestamp : 32; - uint32_t cumulative_ip_length_pmac1 : 16, - cumulative_ip_length : 16; - uint32_t tcp_sequence_number : 32; -#else - uint32_t src_ip_127_96 : 32; - uint32_t src_ip_95_64 : 32; - uint32_t src_ip_63_32 : 32; - uint32_t src_ip_31_0 : 32; - uint32_t dest_ip_127_96 : 32; - uint32_t dest_ip_95_64 : 32; - uint32_t dest_ip_63_32 : 32; - uint32_t dest_ip_31_0 : 32; - uint32_t dest_port : 16, - src_port : 16; - uint32_t reo_destination_handler : 2, - msdu_drop : 1, - reo_destination_indication : 5, - use_ppe : 1, - priority_valid : 1, - service_code : 9, - reserved_9 : 4, - valid : 1, - l4_protocol : 8; - uint32_t metadata : 32; - uint32_t msdu_count : 24, - lro_eligible : 1, - aggregation_count : 7; - uint32_t msdu_byte_count : 32; - uint32_t timestamp : 32; - uint32_t cumulative_ip_length : 16, - cumulative_ip_length_pmac1 : 16; - uint32_t tcp_sequence_number : 32; -#endif -}; - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 - -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff - -#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 -#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 -#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 - -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 - -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 - -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 - -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 - -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 - -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 - -#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 -#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f - -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff - -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 - -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h deleted file mode 100644 index a43548b14a07..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ -#define _RX_FRAME_1K_BITMAP_ACK_H_ - -#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 - -#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 - -struct rx_frame_1k_bitmap_ack { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 5, - ba_bitmap_size : 2, - gen_mlo_notification : 1, - reserved_0b : 2, - ba_tid : 4, - sta_full_aid : 13, - reserved_0c : 5; - uint32_t mlo_sta_id : 10, - ba_size_1024_allowed : 1, - ba_size_512_allowed : 1, - reserved_1a : 20; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_ctrl : 16, - ba_ts_seq : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; - uint32_t ba_ts_bitmap_287_256 : 32; - uint32_t ba_ts_bitmap_319_288 : 32; - uint32_t ba_ts_bitmap_351_320 : 32; - uint32_t ba_ts_bitmap_383_352 : 32; - uint32_t ba_ts_bitmap_415_384 : 32; - uint32_t ba_ts_bitmap_447_416 : 32; - uint32_t ba_ts_bitmap_479_448 : 32; - uint32_t ba_ts_bitmap_511_480 : 32; - uint32_t ba_ts_bitmap_543_512 : 32; - uint32_t ba_ts_bitmap_575_544 : 32; - uint32_t ba_ts_bitmap_607_576 : 32; - uint32_t ba_ts_bitmap_639_608 : 32; - uint32_t ba_ts_bitmap_671_640 : 32; - uint32_t ba_ts_bitmap_703_672 : 32; - uint32_t ba_ts_bitmap_735_704 : 32; - uint32_t ba_ts_bitmap_767_736 : 32; - uint32_t ba_ts_bitmap_799_768 : 32; - uint32_t ba_ts_bitmap_831_800 : 32; - uint32_t ba_ts_bitmap_863_832 : 32; - uint32_t ba_ts_bitmap_895_864 : 32; - uint32_t ba_ts_bitmap_927_896 : 32; - uint32_t ba_ts_bitmap_959_928 : 32; - uint32_t ba_ts_bitmap_991_960 : 32; - uint32_t ba_ts_bitmap_1023_992 : 32; -#else - uint32_t reserved_0c : 5, - sta_full_aid : 13, - ba_tid : 4, - reserved_0b : 2, - gen_mlo_notification : 1, - ba_bitmap_size : 2, - reserved_0a : 5; - uint32_t reserved_1a : 20, - ba_size_512_allowed : 1, - ba_size_1024_allowed : 1, - mlo_sta_id : 10; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_seq : 16, - ba_ts_ctrl : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; - uint32_t ba_ts_bitmap_287_256 : 32; - uint32_t ba_ts_bitmap_319_288 : 32; - uint32_t ba_ts_bitmap_351_320 : 32; - uint32_t ba_ts_bitmap_383_352 : 32; - uint32_t ba_ts_bitmap_415_384 : 32; - uint32_t ba_ts_bitmap_447_416 : 32; - uint32_t ba_ts_bitmap_479_448 : 32; - uint32_t ba_ts_bitmap_511_480 : 32; - uint32_t ba_ts_bitmap_543_512 : 32; - uint32_t ba_ts_bitmap_575_544 : 32; - uint32_t ba_ts_bitmap_607_576 : 32; - uint32_t ba_ts_bitmap_639_608 : 32; - uint32_t ba_ts_bitmap_671_640 : 32; - uint32_t ba_ts_bitmap_703_672 : 32; - uint32_t ba_ts_bitmap_735_704 : 32; - uint32_t ba_ts_bitmap_767_736 : 32; - uint32_t ba_ts_bitmap_799_768 : 32; - uint32_t ba_ts_bitmap_831_800 : 32; - uint32_t ba_ts_bitmap_863_832 : 32; - uint32_t ba_ts_bitmap_895_864 : 32; - uint32_t ba_ts_bitmap_927_896 : 32; - uint32_t ba_ts_bitmap_959_928 : 32; - uint32_t ba_ts_bitmap_991_960 : 32; - uint32_t ba_ts_bitmap_1023_992 : 32; -#endif -}; - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f - -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 - -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB 7 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB 7 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK 0x0000000000000080 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 8 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000300 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 - -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 - -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MSB 41 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MASK 0x000003ff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB 42 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB 42 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK 0x0000040000000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB 43 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB 43 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK 0x0000080000000000 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_LSB 44 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MASK 0xfffff00000000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 47 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 48 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 47 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 48 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff000000000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000020 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000028 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000030 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000038 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000040 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000048 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000050 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000058 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000060 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000068 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000070 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000078 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000080 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000088 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000090 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_ack.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_ack.h deleted file mode 100644 index 0b68486b038e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_ack.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_BITMAP_ACK_H_ -#define _RX_FRAME_BITMAP_ACK_H_ - -#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 - -#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 - -struct rx_frame_bitmap_ack { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t no_bitmap_available : 1, - explicit_ack : 1, - explict_ack_type : 3, - ba_bitmap_size : 2, - gen_mlo_notification : 1, - reserved_0a : 2, - ba_tid : 4, - sta_full_aid : 13, - reserved_0b : 5; - uint32_t mlo_sta_id : 10, - ba_size_1024_allowed : 1, - ba_size_512_allowed : 1, - ba_size_256_allowed : 1, - ba_size_128_allowed : 1, - ba_size_64_allowed : 1, - ba_size_32_allowed : 1, - reserved_1a : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_ctrl : 16, - ba_ts_seq : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; -#else - uint32_t reserved_0b : 5, - sta_full_aid : 13, - ba_tid : 4, - reserved_0a : 2, - gen_mlo_notification : 1, - ba_bitmap_size : 2, - explict_ack_type : 3, - explicit_ack : 1, - no_bitmap_available : 1; - uint32_t reserved_1a : 16, - ba_size_32_allowed : 1, - ba_size_64_allowed : 1, - ba_size_128_allowed : 1, - ba_size_256_allowed : 1, - ba_size_512_allowed : 1, - ba_size_1024_allowed : 1, - mlo_sta_id : 10; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_seq : 16, - ba_ts_ctrl : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; -#endif -}; - -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 - -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 - -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c - -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 - -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB 7 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB 7 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK 0x0000000000000080 - -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 8 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000300 - -#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 -#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 -#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 - -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 - -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 - -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_LSB 32 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MSB 41 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MASK 0x000003ff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB 42 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB 42 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK 0x0000040000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB 43 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB 43 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK 0x0000080000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_LSB 44 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MSB 44 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MASK 0x0000100000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_LSB 45 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MSB 45 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MASK 0x0000200000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_LSB 46 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MSB 46 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MASK 0x0000400000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_LSB 47 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MSB 47 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MASK 0x0000800000000000 - -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_LSB 48 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MSB 63 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 0 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 31 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 32 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 47 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 48 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 63 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 0 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 31 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 47 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 48 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000020 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000028 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000030 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_req.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_req.h deleted file mode 100644 index 24f8ddd1c57c..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_req.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_BITMAP_REQ_H_ -#define _RX_FRAME_BITMAP_REQ_H_ - -#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2 - -#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1 - -struct rx_frame_bitmap_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t explicit_user_request : 1, - user_request_type : 1, - user_number : 6, - sw_peer_id : 16, - tid_specific_request : 1, - requested_tid : 4, - reserved_0 : 3; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0 : 3, - requested_tid : 4, - tid_specific_request : 1, - sw_peer_id : 16, - user_number : 6, - user_request_type : 1, - explicit_user_request : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x0000000000000001 - -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x0000000000000002 - -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x00000000000000fc - -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x0000000000ffff00 - -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x0000000001000000 - -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x000000001e000000 - -#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0x00000000e0000000 - -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB 32 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB 63 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_location_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_location_info.h deleted file mode 100644 index cfd6a734f511..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_location_info.h +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_LOCATION_INFO_H_ -#define _RX_LOCATION_INFO_H_ - -#define NUM_OF_DWORDS_RX_LOCATION_INFO 28 - -struct rx_location_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_location_info_valid : 1, - rtt_hw_ifft_mode : 1, - __reserved_g_0083 : 2, - reserved_0 : 4, - rtt_num_fac : 8, - rtt_rx_chain_mask : 8, - rtt_num_streams : 8; - uint32_t rtt_first_selected_chain : 8, - rtt_second_selected_chain : 8, - rtt_cfr_status : 8, - rtt_cir_status : 8; - uint32_t rtt_che_buffer_pointer_low32 : 32; - uint32_t rtt_che_buffer_pointer_high8 : 8, - reserved_3 : 8, - rtt_pkt_bw_vht : 4, - rtt_pkt_bw_leg : 4, - rtt_mcs_rate : 8; - uint32_t rtt_cfo_measurement : 16, - rtt_preamble_type : 8, - rtt_gi_type : 8; - uint32_t rx_start_ts : 32; - uint32_t rx_start_ts_upper : 32; - uint32_t rx_end_ts : 32; - uint32_t gain_chain0 : 16, - gain_chain1 : 16; - uint32_t gain_chain2 : 16, - gain_chain3 : 16; - uint32_t gain_report_status : 8, - rtt_timing_backoff_sel : 8, - rtt_fac_combined : 16; - uint32_t rtt_fac_0 : 16, - rtt_fac_1 : 16; - uint32_t rtt_fac_2 : 16, - rtt_fac_3 : 16; - uint32_t rtt_fac_4 : 16, - rtt_fac_5 : 16; - uint32_t rtt_fac_6 : 16, - rtt_fac_7 : 16; - uint32_t rtt_fac_8 : 16, - rtt_fac_9 : 16; - uint32_t rtt_fac_10 : 16, - rtt_fac_11 : 16; - uint32_t rtt_fac_12 : 16, - rtt_fac_13 : 16; - uint32_t rtt_fac_14 : 16, - rtt_fac_15 : 16; - uint32_t rtt_fac_16 : 16, - rtt_fac_17 : 16; - uint32_t rtt_fac_18 : 16, - rtt_fac_19 : 16; - uint32_t rtt_fac_20 : 16, - rtt_fac_21 : 16; - uint32_t rtt_fac_22 : 16, - rtt_fac_23 : 16; - uint32_t rtt_fac_24 : 16, - rtt_fac_25 : 16; - uint32_t rtt_fac_26 : 16, - rtt_fac_27 : 16; - uint32_t rtt_fac_28 : 16, - rtt_fac_29 : 16; - uint32_t rtt_fac_30 : 16, - rtt_fac_31 : 16; - uint32_t reserved_27a : 32; -#else - uint32_t rtt_num_streams : 8, - rtt_rx_chain_mask : 8, - rtt_num_fac : 8, - reserved_0 : 4, - __reserved_g_0083 : 2, - rtt_hw_ifft_mode : 1, - rx_location_info_valid : 1; - uint32_t rtt_cir_status : 8, - rtt_cfr_status : 8, - rtt_second_selected_chain : 8, - rtt_first_selected_chain : 8; - uint32_t rtt_che_buffer_pointer_low32 : 32; - uint32_t rtt_mcs_rate : 8, - rtt_pkt_bw_leg : 4, - rtt_pkt_bw_vht : 4, - reserved_3 : 8, - rtt_che_buffer_pointer_high8 : 8; - uint32_t rtt_gi_type : 8, - rtt_preamble_type : 8, - rtt_cfo_measurement : 16; - uint32_t rx_start_ts : 32; - uint32_t rx_start_ts_upper : 32; - uint32_t rx_end_ts : 32; - uint32_t gain_chain1 : 16, - gain_chain0 : 16; - uint32_t gain_chain3 : 16, - gain_chain2 : 16; - uint32_t rtt_fac_combined : 16, - rtt_timing_backoff_sel : 8, - gain_report_status : 8; - uint32_t rtt_fac_1 : 16, - rtt_fac_0 : 16; - uint32_t rtt_fac_3 : 16, - rtt_fac_2 : 16; - uint32_t rtt_fac_5 : 16, - rtt_fac_4 : 16; - uint32_t rtt_fac_7 : 16, - rtt_fac_6 : 16; - uint32_t rtt_fac_9 : 16, - rtt_fac_8 : 16; - uint32_t rtt_fac_11 : 16, - rtt_fac_10 : 16; - uint32_t rtt_fac_13 : 16, - rtt_fac_12 : 16; - uint32_t rtt_fac_15 : 16, - rtt_fac_14 : 16; - uint32_t rtt_fac_17 : 16, - rtt_fac_16 : 16; - uint32_t rtt_fac_19 : 16, - rtt_fac_18 : 16; - uint32_t rtt_fac_21 : 16, - rtt_fac_20 : 16; - uint32_t rtt_fac_23 : 16, - rtt_fac_22 : 16; - uint32_t rtt_fac_25 : 16, - rtt_fac_24 : 16; - uint32_t rtt_fac_27 : 16, - rtt_fac_26 : 16; - uint32_t rtt_fac_29 : 16, - rtt_fac_28 : 16; - uint32_t rtt_fac_31 : 16, - rtt_fac_30 : 16; - uint32_t reserved_27a : 32; -#endif -}; - -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001 - -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002 - -#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RESERVED_0_LSB 4 -#define RX_LOCATION_INFO_RESERVED_0_MSB 7 -#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0 - -#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8 -#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15 -#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff - -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff - -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff - -#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RESERVED_3_LSB 8 -#define RX_LOCATION_INFO_RESERVED_3_MSB 15 -#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16 -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19 -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000 - -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20 -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23 -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000 - -#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24 -#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31 -#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24 -#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31 -#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000 - -#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014 -#define RX_LOCATION_INFO_RX_START_TS_LSB 0 -#define RX_LOCATION_INFO_RX_START_TS_MSB 31 -#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff - -#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff - -#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c -#define RX_LOCATION_INFO_RX_END_TS_LSB 0 -#define RX_LOCATION_INFO_RX_END_TS_MSB 31 -#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff - -#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020 -#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0 -#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15 -#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff - -#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020 -#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16 -#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31 -#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000 - -#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024 -#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0 -#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15 -#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff - -#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024 -#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16 -#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31 -#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000 - -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff - -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c -#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c -#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030 -#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030 -#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034 -#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034 -#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038 -#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038 -#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c -#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c -#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040 -#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040 -#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044 -#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044 -#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048 -#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048 -#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c -#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c -#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050 -#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050 -#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054 -#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054 -#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058 -#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058 -#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c -#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c -#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060 -#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060 -#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064 -#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064 -#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068 -#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068 -#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c -#define RX_LOCATION_INFO_RESERVED_27A_LSB 0 -#define RX_LOCATION_INFO_RESERVED_27A_MSB 31 -#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_desc_info.h deleted file mode 100644 index 30f538fb1228..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_desc_info.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_DESC_INFO_H_ -#define _RX_MPDU_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 - -struct rx_mpdu_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t msdu_count : 8, - fragment_flag : 1, - mpdu_retry_bit : 1, - ampdu_flag : 1, - bar_frame : 1, - pn_fields_contain_valid_info : 1, - raw_mpdu : 1, - more_fragment_flag : 1, - src_info : 12, - mpdu_qos_control_valid : 1, - tid : 4; - uint32_t peer_meta_data : 32; -#else - uint32_t tid : 4, - mpdu_qos_control_valid : 1, - src_info : 12, - more_fragment_flag : 1, - raw_mpdu : 1, - pn_fields_contain_valid_info : 1, - bar_frame : 1, - ampdu_flag : 1, - mpdu_retry_bit : 1, - fragment_flag : 1, - msdu_count : 8; - uint32_t peer_meta_data : 32; -#endif -}; - -#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff - -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 - -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 - -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 - -#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 -#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 -#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 - -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 -#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 -#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 - -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 -#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 -#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 - -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_TID_LSB 28 -#define RX_MPDU_DESC_INFO_TID_MSB 31 -#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 - -#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_details.h deleted file mode 100644 index d2d96a0a9996..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_details.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_DETAILS_H_ -#define _RX_MPDU_DETAILS_H_ - -#include "rx_mpdu_ext_desc_info.h" -#include "rx_mpdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MPDU_DETAILS 6 - -struct rx_mpdu_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info msdu_link_desc_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_mpdu_ext_desc_info rx_mpdu_ext_desc_info_details; -#else - struct buffer_addr_info msdu_link_desc_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_mpdu_ext_desc_info rx_mpdu_ext_desc_info_details; -#endif -}; - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000 - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_end.h deleted file mode 100644 index dc54ea129fdd..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_end.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_END_H_ -#define _RX_MPDU_END_H_ - -#define NUM_OF_DWORDS_RX_MPDU_END 4 - -#define NUM_OF_QWORDS_RX_MPDU_END 2 - -struct rx_mpdu_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t reserved_1a : 9, - cfp_mic_err : 1, - cfp_pn_chk_err : 1, - unsup_ktype_short_frame : 1, - rx_in_tx_decrypt_byp : 1, - overflow_err : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - pn_fields_contain_valid_info : 1, - fcs_err : 1, - msdu_length_err : 1, - reserved1c : 6, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - ifcs_present : 1; - uint32_t mpdu_crc_ok_intermediate_fcs : 1, - mpdu_length_intermediate_fcs : 14, - rxpcu_mgmt_sequence_nr_valid : 1, - rxpcu_mgmt_sequence_nr : 16; - uint32_t __reserved_g_0002 : 32; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t ifcs_present : 1, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - reserved1c : 6, - msdu_length_err : 1, - fcs_err : 1, - pn_fields_contain_valid_info : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - overflow_err : 1, - rx_in_tx_decrypt_byp : 1, - unsup_ktype_short_frame : 1, - cfp_pn_chk_err : 1, - cfp_mic_err : 1, - reserved_1a : 9; - uint32_t rxpcu_mgmt_sequence_nr : 16, - rxpcu_mgmt_sequence_nr_valid : 1, - mpdu_length_intermediate_fcs : 14, - mpdu_crc_ok_intermediate_fcs : 1; - uint32_t __reserved_g_0002 : 32; -#endif -}; - -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_0_LSB 9 -#define RX_MPDU_END_RESERVED_0_MSB 15 -#define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MPDU_END_PHY_PPDU_ID_LSB 16 -#define RX_MPDU_END_PHY_PPDU_ID_MSB 31 -#define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_1A_LSB 32 -#define RX_MPDU_END_RESERVED_1A_MSB 40 -#define RX_MPDU_END_RESERVED_1A_MASK 0x000001ff00000000 - -#define RX_MPDU_END_CFP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_CFP_MIC_ERR_LSB 41 -#define RX_MPDU_END_CFP_MIC_ERR_MSB 41 -#define RX_MPDU_END_CFP_MIC_ERR_MASK 0x0000020000000000 - -#define RX_MPDU_END_CFP_PN_CHK_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_CFP_PN_CHK_ERR_LSB 42 -#define RX_MPDU_END_CFP_PN_CHK_ERR_MSB 42 -#define RX_MPDU_END_CFP_PN_CHK_ERR_MASK 0x0000040000000000 - -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 - -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 - -#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_OVERFLOW_ERR_LSB 45 -#define RX_MPDU_END_OVERFLOW_ERR_MSB 45 -#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 - -#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 -#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 -#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 - -#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 -#define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 -#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 - -#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_DECRYPT_ERR_LSB 48 -#define RX_MPDU_END_DECRYPT_ERR_MSB 48 -#define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 - -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 - -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 - -#define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_FCS_ERR_LSB 51 -#define RX_MPDU_END_FCS_ERR_MSB 51 -#define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 - -#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 -#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 -#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 - -#define RX_MPDU_END_RESERVED1C_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED1C_LSB 53 -#define RX_MPDU_END_RESERVED1C_MSB 58 -#define RX_MPDU_END_RESERVED1C_MASK 0x07e0000000000000 - -#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 - -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 - -#define RX_MPDU_END_IFCS_PRESENT_OFFSET 0x0000000000000000 -#define RX_MPDU_END_IFCS_PRESENT_LSB 63 -#define RX_MPDU_END_IFCS_PRESENT_MSB 63 -#define RX_MPDU_END_IFCS_PRESENT_MASK 0x8000000000000000 - -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_OFFSET 0x0000000000000008 -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_LSB 0 -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_MSB 0 -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_MASK 0x0000000000000001 - -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_OFFSET 0x0000000000000008 -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_LSB 1 -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_MSB 14 -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_MASK 0x0000000000007ffe - -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 - -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_ext_desc_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_ext_desc_info.h deleted file mode 100644 index 83f4df333c88..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_ext_desc_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_EXT_DESC_INFO_H_ -#define _RX_MPDU_EXT_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MPDU_EXT_DESC_INFO 2 - -struct rx_mpdu_ext_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pn_31_0 : 32; - uint32_t pn_47_32 : 16, - pn_127_48_info : 2, - msdu_link_desc_index : 4, - reserved_1a : 10; -#else - uint32_t pn_31_0 : 32; - uint32_t reserved_1a : 10, - msdu_link_desc_index : 4, - pn_127_48_info : 2, - pn_47_32 : 16; -#endif -}; - -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_OFFSET 0x00000000 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_LSB 0 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MSB 31 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_LSB 0 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MSB 15 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MASK 0x0000ffff - -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_LSB 16 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MSB 17 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MASK 0x00030000 - -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_LSB 18 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MSB 21 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_LSB 22 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MSB 31 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_info.h deleted file mode 100644 index d76b47b7a712..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_info.h +++ /dev/null @@ -1,972 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_INFO_H_ -#define _RX_MPDU_INFO_H_ - -#include "rxpt_classify_info.h" -#define NUM_OF_DWORDS_RX_MPDU_INFO 30 - -struct rx_mpdu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rxpt_classify_info rxpt_classify_info_details; - uint32_t epd_en : 1, - all_frames_shall_be_encrypted : 1, - encrypt_type : 4, - wep_key_width_for_variable_key : 2, - __reserved_g_0003 : 2, - bssid_hit : 1, - bssid_number : 4, - tid : 4, - reserved_7a : 13; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t rx_reo_queue_desc_addr_39_32 : 8, - receive_queue_number : 16, - pre_delim_err_warning : 1, - first_delim_err : 1, - reserved_2a : 6; - uint32_t pn_31_0 : 32; - uint32_t pn_63_32 : 32; - uint32_t pn_95_64 : 32; - uint32_t pn_127_96 : 32; - uint32_t mpdu_frame_control_valid : 1, - mpdu_duration_valid : 1, - mac_addr_ad1_valid : 1, - mac_addr_ad2_valid : 1, - mac_addr_ad3_valid : 1, - mac_addr_ad4_valid : 1, - mpdu_sequence_control_valid : 1, - mpdu_qos_control_valid : 1, - mpdu_ht_control_valid : 1, - frame_encryption_info_valid : 1, - mpdu_fragment_number : 4, - more_fragment_flag : 1, - protected_cbf_cqi : 1, - fr_ds : 1, - to_ds : 1, - encrypted : 1, - mpdu_retry : 1, - mpdu_sequence_number : 12; - uint32_t peer_meta_data : 32; - uint32_t ast_index : 16, - sw_peer_id : 16; - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - ndp_frame : 1, - phy_err : 1, - phy_err_during_mpdu_header : 1, - protocol_version_err : 1, - ast_based_lookup_valid : 1, - __reserved_g_0005 : 1, - __reserved_g_0086 : 1, - phy_ppdu_id : 16; - uint32_t key_id_octet : 8, - new_peer_entry : 1, - decrypt_needed : 1, - decap_type : 2, - rx_insert_vlan_c_tag_padding : 1, - rx_insert_vlan_s_tag_padding : 1, - strip_vlan_c_tag_decap : 1, - strip_vlan_s_tag_decap : 1, - pre_delim_count : 12, - ampdu_flag : 1, - bar_frame : 1, - raw_mpdu : 1, - reserved_12 : 1; - uint32_t mpdu_length : 14, - first_mpdu : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - fragment_flag : 1, - order : 1, - u_apsd_trigger : 1, - encrypt_required : 1, - directed : 1, - amsdu_present : 1, - reserved_13 : 1; - uint32_t mpdu_frame_control_field : 16, - mpdu_duration_field : 16; - uint32_t mac_addr_ad1_31_0 : 32; - uint32_t mac_addr_ad1_47_32 : 16, - mac_addr_ad2_15_0 : 16; - uint32_t mac_addr_ad2_47_16 : 32; - uint32_t mac_addr_ad3_31_0 : 32; - uint32_t mac_addr_ad3_47_32 : 16, - mpdu_sequence_control_field : 16; - uint32_t mac_addr_ad4_31_0 : 32; - uint32_t mac_addr_ad4_47_32 : 16, - mpdu_qos_control_field : 16; - uint32_t mpdu_ht_control_field : 32; - uint32_t vdev_id : 8, - service_code : 9, - priority_valid : 1, - src_info : 12, - smr_frame : 1, - __reserved_g_0029 : 1; - uint32_t __reserved_g_0060 : 32; - uint32_t __reserved_g_0057 : 16, - __reserved_g_0059 : 16; - uint32_t __reserved_g_0056 : 32; - uint32_t authorized_to_send_wds : 1, - disallow_mcbc_da_in_unicast_mpdu : 1, - fromtods_00_fnf_check_dis : 1, - fromtods_01_fnf_check_dis : 1, - fromtods_10_fnf_check_dis : 1, - fromtods_11_fnf_check_dis : 1, - rx_misc_config : 3, - a_msdu_fromtods_10_ad3 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_11_ad4 : 2, - multi_link_ds_addr_fromtods_00_raw_en : 1, - multi_link_ds_addr_fromtods_non00_raw_en : 1, - multi_link_ds_addr_ad3_valid : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_ad1_trans_dis : 1, - data_fromtods_00_ad3 : 2, - mgmt_fromtods_00_ad3 : 2, - multi_link_ds_addr_mgmt_en : 1, - multi_link_ds_addr_ctrl_en : 1, - reserved_27a : 5; - uint32_t multi_link_ds_addr_ad3_31_0 : 32; - uint32_t multi_link_ds_addr_ad3_47_32 : 16, - cfp_mic_err : 1, - cfp_pn_chk_err : 1, - reserved_29a : 14; -#else - struct rxpt_classify_info rxpt_classify_info_details; - uint32_t reserved_7a : 13, - tid : 4, - bssid_number : 4, - bssid_hit : 1, - __reserved_g_0003 : 2, - wep_key_width_for_variable_key : 2, - encrypt_type : 4, - all_frames_shall_be_encrypted : 1, - epd_en : 1; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t reserved_2a : 6, - first_delim_err : 1, - pre_delim_err_warning : 1, - receive_queue_number : 16, - rx_reo_queue_desc_addr_39_32 : 8; - uint32_t pn_31_0 : 32; - uint32_t pn_63_32 : 32; - uint32_t pn_95_64 : 32; - uint32_t pn_127_96 : 32; - uint32_t mpdu_sequence_number : 12, - mpdu_retry : 1, - encrypted : 1, - to_ds : 1, - fr_ds : 1, - protected_cbf_cqi : 1, - more_fragment_flag : 1, - mpdu_fragment_number : 4, - frame_encryption_info_valid : 1, - mpdu_ht_control_valid : 1, - mpdu_qos_control_valid : 1, - mpdu_sequence_control_valid : 1, - mac_addr_ad4_valid : 1, - mac_addr_ad3_valid : 1, - mac_addr_ad2_valid : 1, - mac_addr_ad1_valid : 1, - mpdu_duration_valid : 1, - mpdu_frame_control_valid : 1; - uint32_t peer_meta_data : 32; - uint32_t sw_peer_id : 16, - ast_index : 16; - uint32_t phy_ppdu_id : 16, - __reserved_g_0086 : 1, - __reserved_g_0005 : 1, - ast_based_lookup_valid : 1, - protocol_version_err : 1, - phy_err_during_mpdu_header : 1, - phy_err : 1, - ndp_frame : 1, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_12 : 1, - raw_mpdu : 1, - bar_frame : 1, - ampdu_flag : 1, - pre_delim_count : 12, - strip_vlan_s_tag_decap : 1, - strip_vlan_c_tag_decap : 1, - rx_insert_vlan_s_tag_padding : 1, - rx_insert_vlan_c_tag_padding : 1, - decap_type : 2, - decrypt_needed : 1, - new_peer_entry : 1, - key_id_octet : 8; - uint32_t reserved_13 : 1, - amsdu_present : 1, - directed : 1, - encrypt_required : 1, - u_apsd_trigger : 1, - order : 1, - fragment_flag : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - first_mpdu : 1, - mpdu_length : 14; - uint32_t mpdu_duration_field : 16, - mpdu_frame_control_field : 16; - uint32_t mac_addr_ad1_31_0 : 32; - uint32_t mac_addr_ad2_15_0 : 16, - mac_addr_ad1_47_32 : 16; - uint32_t mac_addr_ad2_47_16 : 32; - uint32_t mac_addr_ad3_31_0 : 32; - uint32_t mpdu_sequence_control_field : 16, - mac_addr_ad3_47_32 : 16; - uint32_t mac_addr_ad4_31_0 : 32; - uint32_t mpdu_qos_control_field : 16, - mac_addr_ad4_47_32 : 16; - uint32_t mpdu_ht_control_field : 32; - uint32_t __reserved_g_0029 : 1, - smr_frame : 1, - src_info : 12, - priority_valid : 1, - service_code : 9, - vdev_id : 8; - uint32_t __reserved_g_0060 : 32; - uint32_t __reserved_g_0059 : 16, - __reserved_g_0057 : 16; - uint32_t __reserved_g_0056 : 32; - uint32_t reserved_27a : 5, - multi_link_ds_addr_ctrl_en : 1, - multi_link_ds_addr_mgmt_en : 1, - mgmt_fromtods_00_ad3 : 2, - data_fromtods_00_ad3 : 2, - multi_link_addr_ad1_trans_dis : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_ds_addr_ad3_valid : 1, - multi_link_ds_addr_fromtods_non00_raw_en : 1, - multi_link_ds_addr_fromtods_00_raw_en : 1, - a_msdu_fromtods_11_ad4 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_10_ad3 : 2, - rx_misc_config : 3, - fromtods_11_fnf_check_dis : 1, - fromtods_10_fnf_check_dis : 1, - fromtods_01_fnf_check_dis : 1, - fromtods_00_fnf_check_dis : 1, - disallow_mcbc_da_in_unicast_mpdu : 1, - authorized_to_send_wds : 1; - uint32_t multi_link_ds_addr_ad3_31_0 : 32; - uint32_t reserved_29a : 14, - cfp_pn_chk_err : 1, - cfp_mic_err : 1, - multi_link_ds_addr_ad3_47_32 : 16; -#endif -}; - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000 - -#define RX_MPDU_INFO_EPD_EN_OFFSET 0x00000004 -#define RX_MPDU_INFO_EPD_EN_LSB 0 -#define RX_MPDU_INFO_EPD_EN_MSB 0 -#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 - -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 - -#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x00000004 -#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 -#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 -#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c - -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 - -#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x00000004 -#define RX_MPDU_INFO_BSSID_HIT_LSB 10 -#define RX_MPDU_INFO_BSSID_HIT_MSB 10 -#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 - -#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x00000004 -#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 -#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 -#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 - -#define RX_MPDU_INFO_TID_OFFSET 0x00000004 -#define RX_MPDU_INFO_TID_LSB 15 -#define RX_MPDU_INFO_TID_MSB 18 -#define RX_MPDU_INFO_TID_MASK 0x00078000 - -#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x00000004 -#define RX_MPDU_INFO_RESERVED_7A_LSB 19 -#define RX_MPDU_INFO_RESERVED_7A_MSB 31 -#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 - -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 - -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 - -#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x0000000c -#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 -#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 -#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 - -#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x0000000c -#define RX_MPDU_INFO_RESERVED_2A_LSB 26 -#define RX_MPDU_INFO_RESERVED_2A_MSB 31 -#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 - -#define RX_MPDU_INFO_PN_31_0_OFFSET 0x00000010 -#define RX_MPDU_INFO_PN_31_0_LSB 0 -#define RX_MPDU_INFO_PN_31_0_MSB 31 -#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000014 -#define RX_MPDU_INFO_PN_63_32_LSB 0 -#define RX_MPDU_INFO_PN_63_32_MSB 31 -#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000018 -#define RX_MPDU_INFO_PN_95_64_LSB 0 -#define RX_MPDU_INFO_PN_95_64_MSB 31 -#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_127_96_OFFSET 0x0000001c -#define RX_MPDU_INFO_PN_127_96_LSB 0 -#define RX_MPDU_INFO_PN_127_96_MSB 31 -#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff - -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 - -#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 - -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 - -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 - -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 - -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 - -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 - -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 - -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 - -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 - -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 - -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000020 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_OFFSET 0x00000020 -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_LSB 15 -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_MSB 15 -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_MASK 0x00008000 - -#define RX_MPDU_INFO_FR_DS_OFFSET 0x00000020 -#define RX_MPDU_INFO_FR_DS_LSB 16 -#define RX_MPDU_INFO_FR_DS_MSB 16 -#define RX_MPDU_INFO_FR_DS_MASK 0x00010000 - -#define RX_MPDU_INFO_TO_DS_OFFSET 0x00000020 -#define RX_MPDU_INFO_TO_DS_LSB 17 -#define RX_MPDU_INFO_TO_DS_MSB 17 -#define RX_MPDU_INFO_TO_DS_MASK 0x00020000 - -#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x00000020 -#define RX_MPDU_INFO_ENCRYPTED_LSB 18 -#define RX_MPDU_INFO_ENCRYPTED_MSB 18 -#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 - -#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_RETRY_LSB 19 -#define RX_MPDU_INFO_MPDU_RETRY_MSB 19 -#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 - -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 - -#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000024 -#define RX_MPDU_INFO_PEER_META_DATA_LSB 0 -#define RX_MPDU_INFO_PEER_META_DATA_MSB 31 -#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff - -#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 -#define RX_MPDU_INFO_AST_INDEX_LSB 0 -#define RX_MPDU_INFO_AST_INDEX_MSB 15 -#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff - -#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 -#define RX_MPDU_INFO_SW_PEER_ID_LSB 16 -#define RX_MPDU_INFO_SW_PEER_ID_MSB 31 -#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 - -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 - -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x0000002c -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc - -#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x0000002c -#define RX_MPDU_INFO_NDP_FRAME_LSB 9 -#define RX_MPDU_INFO_NDP_FRAME_MSB 9 -#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 - -#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_ERR_LSB 10 -#define RX_MPDU_INFO_PHY_ERR_MSB 10 -#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 - -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 - -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 - -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 - -#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 -#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 -#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 - -#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 -#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 -#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 -#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff - -#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 - -#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 -#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 -#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 -#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 - -#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 -#define RX_MPDU_INFO_DECAP_TYPE_LSB 10 -#define RX_MPDU_INFO_DECAP_TYPE_MSB 11 -#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 - -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 - -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 - -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 - -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 - -#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 - -#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 -#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 -#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 -#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 - -#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 -#define RX_MPDU_INFO_BAR_FRAME_LSB 29 -#define RX_MPDU_INFO_BAR_FRAME_MSB 29 -#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 - -#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 -#define RX_MPDU_INFO_RAW_MPDU_LSB 30 -#define RX_MPDU_INFO_RAW_MPDU_MSB 30 -#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 - -#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 -#define RX_MPDU_INFO_RESERVED_12_LSB 31 -#define RX_MPDU_INFO_RESERVED_12_MSB 31 -#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 - -#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 -#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 -#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 -#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff - -#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 -#define RX_MPDU_INFO_FIRST_MPDU_LSB 14 -#define RX_MPDU_INFO_FIRST_MPDU_MSB 14 -#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 - -#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 -#define RX_MPDU_INFO_MCAST_BCAST_LSB 15 -#define RX_MPDU_INFO_MCAST_BCAST_MSB 15 -#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 - -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 - -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 - -#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 -#define RX_MPDU_INFO_POWER_MGMT_LSB 18 -#define RX_MPDU_INFO_POWER_MGMT_MSB 18 -#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 - -#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 -#define RX_MPDU_INFO_NON_QOS_LSB 19 -#define RX_MPDU_INFO_NON_QOS_MSB 19 -#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 - -#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 -#define RX_MPDU_INFO_NULL_DATA_LSB 20 -#define RX_MPDU_INFO_NULL_DATA_MSB 20 -#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 - -#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 -#define RX_MPDU_INFO_MGMT_TYPE_LSB 21 -#define RX_MPDU_INFO_MGMT_TYPE_MSB 21 -#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 - -#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 -#define RX_MPDU_INFO_CTRL_TYPE_LSB 22 -#define RX_MPDU_INFO_CTRL_TYPE_MSB 22 -#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 - -#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 -#define RX_MPDU_INFO_MORE_DATA_LSB 23 -#define RX_MPDU_INFO_MORE_DATA_MSB 23 -#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 - -#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 -#define RX_MPDU_INFO_EOSP_LSB 24 -#define RX_MPDU_INFO_EOSP_MSB 24 -#define RX_MPDU_INFO_EOSP_MASK 0x01000000 - -#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 -#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 -#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 -#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 - -#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 -#define RX_MPDU_INFO_ORDER_LSB 26 -#define RX_MPDU_INFO_ORDER_MSB 26 -#define RX_MPDU_INFO_ORDER_MASK 0x04000000 - -#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 -#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 -#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 -#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 - -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 - -#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 -#define RX_MPDU_INFO_DIRECTED_LSB 29 -#define RX_MPDU_INFO_DIRECTED_MSB 29 -#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 - -#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 -#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 -#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 -#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 - -#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 -#define RX_MPDU_INFO_RESERVED_13_LSB 31 -#define RX_MPDU_INFO_RESERVED_13_MSB 31 -#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 - -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff - -#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c -#define RX_MPDU_INFO_VDEV_ID_LSB 0 -#define RX_MPDU_INFO_VDEV_ID_MSB 7 -#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff - -#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c -#define RX_MPDU_INFO_SERVICE_CODE_LSB 8 -#define RX_MPDU_INFO_SERVICE_CODE_MSB 16 -#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 - -#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c -#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 -#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 -#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 - -#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c -#define RX_MPDU_INFO_SRC_INFO_LSB 18 -#define RX_MPDU_INFO_SRC_INFO_MSB 29 -#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 - -#define RX_MPDU_INFO_SMR_FRAME_OFFSET 0x0000005c -#define RX_MPDU_INFO_SMR_FRAME_LSB 30 -#define RX_MPDU_INFO_SMR_FRAME_MSB 30 -#define RX_MPDU_INFO_SMR_FRAME_MASK 0x40000000 - -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 - -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET 0x0000006c -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB 1 -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB 1 -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK 0x00000002 - -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_LSB 2 -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MSB 2 -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MASK 0x00000004 - -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_LSB 3 -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MSB 3 -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MASK 0x00000008 - -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_LSB 4 -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MSB 4 -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MASK 0x00000010 - -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_LSB 5 -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MSB 5 -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MASK 0x00000020 - -#define RX_MPDU_INFO_RX_MISC_CONFIG_OFFSET 0x0000006c -#define RX_MPDU_INFO_RX_MISC_CONFIG_LSB 6 -#define RX_MPDU_INFO_RX_MISC_CONFIG_MSB 8 -#define RX_MPDU_INFO_RX_MISC_CONFIG_MASK 0x000001c0 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_LSB 9 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MSB 10 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MASK 0x00000600 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_LSB 11 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MSB 12 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MASK 0x00001800 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_LSB 13 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MSB 14 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MASK 0x00006000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_LSB 15 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MSB 15 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MASK 0x00008000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_LSB 16 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MSB 16 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x00010000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_LSB 17 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_MSB 17 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_MASK 0x00020000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 18 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 18 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x00040000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 19 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 19 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x00080000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 20 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 20 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x00100000 - -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_LSB 21 -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MSB 22 -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MASK 0x00600000 - -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_LSB 23 -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MSB 24 -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MASK 0x01800000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_LSB 25 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_MSB 25 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_MASK 0x02000000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_LSB 26 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_MSB 26 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_MASK 0x04000000 - -#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c -#define RX_MPDU_INFO_RESERVED_27A_LSB 27 -#define RX_MPDU_INFO_RESERVED_27A_MSB 31 -#define RX_MPDU_INFO_RESERVED_27A_MASK 0xf8000000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_OFFSET 0x00000070 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_OFFSET 0x00000074 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_LSB 0 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_MSB 15 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_CFP_MIC_ERR_OFFSET 0x00000074 -#define RX_MPDU_INFO_CFP_MIC_ERR_LSB 16 -#define RX_MPDU_INFO_CFP_MIC_ERR_MSB 16 -#define RX_MPDU_INFO_CFP_MIC_ERR_MASK 0x00010000 - -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_OFFSET 0x00000074 -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_LSB 17 -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_MSB 17 -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_MASK 0x00020000 - -#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 -#define RX_MPDU_INFO_RESERVED_29A_LSB 18 -#define RX_MPDU_INFO_RESERVED_29A_MSB 31 -#define RX_MPDU_INFO_RESERVED_29A_MASK 0xfffc0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_link_ptr.h deleted file mode 100644 index e9d7e83a92cc..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_link_ptr.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_LINK_PTR_H_ -#define _RX_MPDU_LINK_PTR_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 - -struct rx_mpdu_link_ptr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info mpdu_link_desc_addr_info; -#else - struct buffer_addr_info mpdu_link_desc_addr_info; -#endif -}; - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_start.h deleted file mode 100644 index fc5029dc2da3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_start.h +++ /dev/null @@ -1,712 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_START_H_ -#define _RX_MPDU_START_H_ - -#include "rx_mpdu_info.h" -#define NUM_OF_DWORDS_RX_MPDU_START 30 - -#define NUM_OF_QWORDS_RX_MPDU_START 15 - -struct rx_mpdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_mpdu_info rx_mpdu_info_details; -#else - struct rx_mpdu_info rx_mpdu_info_details; -#endif -}; - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x0000000000100000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x0000000000400000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ff800000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x0000000100000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x0000000200000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 38 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x0000040000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x0000780000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x0007800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff8000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff0000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x0100000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc00000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000000000010 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x0000000000000010 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x0000000000000018 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000000000000018 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x0000000000000001 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 1 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x0000000000000002 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 2 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x0000000000000004 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 3 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x0000000000000008 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x0000000000000010 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x0000000000000020 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x0000000000000040 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x0000000000000080 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x0000000000003c00 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x0000000000004000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_LSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_MASK 0x0000000000008000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x0000000000010000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x0000000000020000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x0000000000040000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x0000000000080000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x00000000fff00000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000300000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x0000020000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x0000040000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x0000080000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x0000100000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x0000200000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x00000000000000ff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x0000000000000c00 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x0000000000001000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x0000000000002000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x0000000000004000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x0000000000008000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x000000000fff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x0000000010000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x0000000020000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x0000000040000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x0000000080000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x0000400000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x0000800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x0004000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x0008000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x0010000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x0020000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x0040000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x0080000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x0100000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x0400000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x0800000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 60 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 60 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x1000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x2000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x4000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x8000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff0000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_LSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_MSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_MASK 0x4000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x0000000100000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK 0x0000000200000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MASK 0x0000000400000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_LSB 35 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MSB 35 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MASK 0x0000000800000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_LSB 36 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MSB 36 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MASK 0x0000001000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_LSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MASK 0x0000002000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_LSB 38 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MASK 0x000001c000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_LSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MASK 0x0000060000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MASK 0x0000180000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_LSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MASK 0x0000600000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MASK 0x0000800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0004000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x0008000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x0010000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_LSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MASK 0x0060000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_LSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MASK 0x0180000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_MSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_MASK 0x0400000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xf800000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xfffc000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_desc_info.h deleted file mode 100644 index 88569b653b64..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_desc_info.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_DESC_INFO_H_ -#define _RX_MSDU_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 - -struct rx_msdu_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t first_msdu_in_mpdu_flag : 1, - last_msdu_in_mpdu_flag : 1, - msdu_continuation : 1, - msdu_length : 14, - msdu_drop : 1, - sa_is_valid : 1, - da_is_valid : 1, - da_is_mcbc : 1, - l3_header_padding_msb : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - fr_ds : 1, - to_ds : 1, - intra_bss : 1, - dest_chip_id : 2, - decap_format : 2, - __reserved_g_0015 : 1; -#else - uint32_t __reserved_g_0015 : 1, - decap_format : 2, - dest_chip_id : 2, - intra_bss : 1, - to_ds : 1, - fr_ds : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - l3_header_padding_msb : 1, - da_is_mcbc : 1, - da_is_valid : 1, - sa_is_valid : 1, - msdu_drop : 1, - msdu_length : 14, - msdu_continuation : 1, - last_msdu_in_mpdu_flag : 1, - first_msdu_in_mpdu_flag : 1; -#endif -}; - -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 -#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 -#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_FR_DS_LSB 24 -#define RX_MSDU_DESC_INFO_FR_DS_MSB 24 -#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 - -#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_TO_DS_LSB 25 -#define RX_MSDU_DESC_INFO_TO_DS_MSB 25 -#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 - -#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 -#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 -#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_details.h deleted file mode 100644 index 0b763a473ce6..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_details.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_DETAILS_H_ -#define _RX_MSDU_DETAILS_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_msdu_ext_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 - -struct rx_msdu_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buffer_addr_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; -#else - struct buffer_addr_info buffer_addr_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; -#endif -}; - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xe0000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_end.h deleted file mode 100644 index b05c9896b09a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_end.h +++ /dev/null @@ -1,1094 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_END_H_ -#define _RX_MSDU_END_H_ - -#define NUM_OF_DWORDS_RX_MSDU_END 32 - -#define NUM_OF_QWORDS_RX_MSDU_END 16 - -struct rx_msdu_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t ip_hdr_chksum : 16, - reported_mpdu_length : 14, - reserved_1a : 2; - uint32_t reserved_2a : 8, - cce_super_rule : 6, - cce_classify_not_done_truncate : 1, - cce_classify_not_done_cce_dis : 1, - cumulative_l3_checksum : 16; - uint32_t rule_indication_31_0 : 32; - uint32_t ipv6_options_crc : 32; - uint32_t da_offset : 6, - sa_offset : 6, - da_offset_valid : 1, - sa_offset_valid : 1, - reserved_5a : 2, - l3_type : 16; - uint32_t rule_indication_63_32 : 32; - uint32_t tcp_seq_number : 32; - uint32_t tcp_ack_number : 32; - uint32_t tcp_flag : 9, - lro_eligible : 1, - reserved_9a : 6, - window_size : 16; - uint32_t sa_sw_peer_id : 16, - sa_idx_timeout : 1, - da_idx_timeout : 1, - to_ds : 1, - tid : 4, - sa_is_valid : 1, - da_is_valid : 1, - da_is_mcbc : 1, - l3_header_padding : 2, - first_msdu : 1, - last_msdu : 1, - fr_ds : 1, - ip_chksum_fail_copy : 1; - uint32_t sa_idx : 16, - da_idx_or_sw_peer_id : 16; - uint32_t msdu_drop : 1, - reo_destination_indication : 5, - flow_idx : 20, - use_ppe : 1, - __reserved_g_0003 : 2, - vlan_ctag_stripped : 1, - vlan_stag_stripped : 1, - fragment_flag : 1; - uint32_t fse_metadata : 32; - uint32_t cce_metadata : 16, - tcp_udp_chksum : 16; - uint32_t aggregation_count : 8, - flow_aggregation_continuation : 1, - fisa_timeout : 1, - tcp_udp_chksum_fail_copy : 1, - msdu_limit_error : 1, - flow_idx_timeout : 1, - flow_idx_invalid : 1, - cce_match : 1, - amsdu_parser_error : 1, - cumulative_ip_length : 16; - uint32_t key_id_octet : 8, - reserved_16a : 24; - uint32_t reserved_17a : 6, - service_code : 9, - priority_valid : 1, - intra_bss : 1, - dest_chip_id : 2, - multicast_echo : 1, - wds_learning_event : 1, - wds_roaming_event : 1, - wds_keep_alive_event : 1, - __reserved_g_0015 : 1, - reserved_17b : 8; - uint32_t msdu_length : 14, - stbc : 1, - ipsec_esp : 1, - l3_offset : 7, - ipsec_ah : 1, - l4_offset : 8; - uint32_t msdu_number : 8, - decap_format : 2, - ipv4_proto : 1, - ipv6_proto : 1, - tcp_proto : 1, - udp_proto : 1, - ip_frag : 1, - tcp_only_ack : 1, - da_is_bcast_mcast : 1, - toeplitz_hash_sel : 2, - ip_fixed_header_valid : 1, - ip_extn_header_valid : 1, - tcp_udp_header_valid : 1, - mesh_control_present : 1, - ldpc : 1, - ip4_protocol_ip6_next_header : 8; - uint32_t vlan_ctag_ci : 16, - vlan_stag_ci : 16; - uint32_t peer_meta_data : 32; - uint32_t user_rssi : 8, - pkt_type : 4, - sgi : 2, - rate_mcs : 5, - receive_bandwidth : 3, - reception_type : 3, - mimo_ss_bitmap : 6, - msdu_done_copy : 1; - uint32_t flow_id_toeplitz : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t reserved_28a : 16, - sa_15_0 : 16; - uint32_t sa_47_16 : 32; - uint32_t first_mpdu : 1, - reserved_30a : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - a_msdu_error : 1, - reserved_30b : 1, - order : 1, - wifi_parser_error : 1, - overflow_err : 1, - msdu_length_err : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - sa_idx_invalid : 1, - da_idx_invalid : 1, - amsdu_addr_mismatch : 1, - rx_in_tx_decrypt_byp : 1, - encrypt_required : 1, - directed : 1, - buffer_fragment : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - fcs_err : 1; - uint32_t reserved_31a : 10, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - ifcs_present : 1, - reserved_31b : 16, - msdu_done : 1; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_1a : 2, - reported_mpdu_length : 14, - ip_hdr_chksum : 16; - uint32_t cumulative_l3_checksum : 16, - cce_classify_not_done_cce_dis : 1, - cce_classify_not_done_truncate : 1, - cce_super_rule : 6, - reserved_2a : 8; - uint32_t rule_indication_31_0 : 32; - uint32_t ipv6_options_crc : 32; - uint32_t l3_type : 16, - reserved_5a : 2, - sa_offset_valid : 1, - da_offset_valid : 1, - sa_offset : 6, - da_offset : 6; - uint32_t rule_indication_63_32 : 32; - uint32_t tcp_seq_number : 32; - uint32_t tcp_ack_number : 32; - uint32_t window_size : 16, - reserved_9a : 6, - lro_eligible : 1, - tcp_flag : 9; - uint32_t ip_chksum_fail_copy : 1, - fr_ds : 1, - last_msdu : 1, - first_msdu : 1, - l3_header_padding : 2, - da_is_mcbc : 1, - da_is_valid : 1, - sa_is_valid : 1, - tid : 4, - to_ds : 1, - da_idx_timeout : 1, - sa_idx_timeout : 1, - sa_sw_peer_id : 16; - uint32_t da_idx_or_sw_peer_id : 16, - sa_idx : 16; - uint32_t fragment_flag : 1, - vlan_stag_stripped : 1, - vlan_ctag_stripped : 1, - __reserved_g_0003 : 2, - use_ppe : 1, - flow_idx : 20, - reo_destination_indication : 5, - msdu_drop : 1; - uint32_t fse_metadata : 32; - uint32_t tcp_udp_chksum : 16, - cce_metadata : 16; - uint32_t cumulative_ip_length : 16, - amsdu_parser_error : 1, - cce_match : 1, - flow_idx_invalid : 1, - flow_idx_timeout : 1, - msdu_limit_error : 1, - tcp_udp_chksum_fail_copy : 1, - fisa_timeout : 1, - flow_aggregation_continuation : 1, - aggregation_count : 8; - uint32_t reserved_16a : 24, - key_id_octet : 8; - uint32_t reserved_17b : 8, - __reserved_g_0015 : 1, - wds_keep_alive_event : 1, - wds_roaming_event : 1, - wds_learning_event : 1, - multicast_echo : 1, - dest_chip_id : 2, - intra_bss : 1, - priority_valid : 1, - service_code : 9, - reserved_17a : 6; - uint32_t l4_offset : 8, - ipsec_ah : 1, - l3_offset : 7, - ipsec_esp : 1, - stbc : 1, - msdu_length : 14; - uint32_t ip4_protocol_ip6_next_header : 8, - ldpc : 1, - mesh_control_present : 1, - tcp_udp_header_valid : 1, - ip_extn_header_valid : 1, - ip_fixed_header_valid : 1, - toeplitz_hash_sel : 2, - da_is_bcast_mcast : 1, - tcp_only_ack : 1, - ip_frag : 1, - udp_proto : 1, - tcp_proto : 1, - ipv6_proto : 1, - ipv4_proto : 1, - decap_format : 2, - msdu_number : 8; - uint32_t vlan_stag_ci : 16, - vlan_ctag_ci : 16; - uint32_t peer_meta_data : 32; - uint32_t msdu_done_copy : 1, - mimo_ss_bitmap : 6, - reception_type : 3, - receive_bandwidth : 3, - rate_mcs : 5, - sgi : 2, - pkt_type : 4, - user_rssi : 8; - uint32_t flow_id_toeplitz : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t sa_15_0 : 16, - reserved_28a : 16; - uint32_t sa_47_16 : 32; - uint32_t fcs_err : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - buffer_fragment : 1, - directed : 1, - encrypt_required : 1, - rx_in_tx_decrypt_byp : 1, - amsdu_addr_mismatch : 1, - da_idx_invalid : 1, - sa_idx_invalid : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - msdu_length_err : 1, - overflow_err : 1, - wifi_parser_error : 1, - order : 1, - reserved_30b : 1, - a_msdu_error : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - reserved_30a : 1, - first_mpdu : 1; - uint32_t msdu_done : 1, - reserved_31b : 16, - ifcs_present : 1, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - reserved_31a : 10; -#endif -}; - -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RESERVED_0_LSB 9 -#define RX_MSDU_END_RESERVED_0_MSB 15 -#define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_END_PHY_PPDU_ID_LSB 16 -#define RX_MSDU_END_PHY_PPDU_ID_MSB 31 -#define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 -#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 -#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 -#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 - -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 - -#define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RESERVED_1A_LSB 62 -#define RX_MSDU_END_RESERVED_1A_MSB 63 -#define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 - -#define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MSDU_END_RESERVED_2A_LSB 0 -#define RX_MSDU_END_RESERVED_2A_MSB 7 -#define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff - -#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 -#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 -#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 - -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 - -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 - -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 -#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 -#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 -#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 - -#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff - -#define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 -#define RX_MSDU_END_DA_OFFSET_LSB 32 -#define RX_MSDU_END_DA_OFFSET_MSB 37 -#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 - -#define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 -#define RX_MSDU_END_SA_OFFSET_LSB 38 -#define RX_MSDU_END_SA_OFFSET_MSB 43 -#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 - -#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 -#define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 -#define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 -#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 - -#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 -#define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 -#define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 -#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 - -#define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 -#define RX_MSDU_END_RESERVED_5A_LSB 46 -#define RX_MSDU_END_RESERVED_5A_MSB 47 -#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 - -#define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_END_L3_TYPE_LSB 48 -#define RX_MSDU_END_L3_TYPE_MSB 63 -#define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 - -#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 -#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 -#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 -#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 -#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 -#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 - -#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 -#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 -#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 -#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 -#define RX_MSDU_END_TCP_FLAG_LSB 32 -#define RX_MSDU_END_TCP_FLAG_MSB 40 -#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 - -#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 -#define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 -#define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 -#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 - -#define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 -#define RX_MSDU_END_RESERVED_9A_LSB 42 -#define RX_MSDU_END_RESERVED_9A_MSB 47 -#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 - -#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 -#define RX_MSDU_END_WINDOW_SIZE_LSB 48 -#define RX_MSDU_END_WINDOW_SIZE_MSB 63 -#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 - -#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 -#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 -#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff - -#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 -#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 -#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 - -#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 -#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 -#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 - -#define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 -#define RX_MSDU_END_TO_DS_LSB 18 -#define RX_MSDU_END_TO_DS_MSB 18 -#define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 - -#define RX_MSDU_END_TID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_TID_LSB 19 -#define RX_MSDU_END_TID_MSB 22 -#define RX_MSDU_END_TID_MASK 0x0000000000780000 - -#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IS_VALID_LSB 23 -#define RX_MSDU_END_SA_IS_VALID_MSB 23 -#define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 - -#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IS_VALID_LSB 24 -#define RX_MSDU_END_DA_IS_VALID_MSB 24 -#define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 - -#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IS_MCBC_LSB 25 -#define RX_MSDU_END_DA_IS_MCBC_MSB 25 -#define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 - -#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 -#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 -#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 -#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 - -#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 -#define RX_MSDU_END_FIRST_MSDU_LSB 28 -#define RX_MSDU_END_FIRST_MSDU_MSB 28 -#define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 - -#define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 -#define RX_MSDU_END_LAST_MSDU_LSB 29 -#define RX_MSDU_END_LAST_MSDU_MSB 29 -#define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 - -#define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 -#define RX_MSDU_END_FR_DS_LSB 30 -#define RX_MSDU_END_FR_DS_MSB 30 -#define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 - -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 - -#define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IDX_LSB 32 -#define RX_MSDU_END_SA_IDX_MSB 47 -#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 - -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 - -#define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 -#define RX_MSDU_END_MSDU_DROP_LSB 0 -#define RX_MSDU_END_MSDU_DROP_MSB 0 -#define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 - -#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e - -#define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FLOW_IDX_LSB 6 -#define RX_MSDU_END_FLOW_IDX_MSB 25 -#define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 - -#define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 -#define RX_MSDU_END_USE_PPE_LSB 26 -#define RX_MSDU_END_USE_PPE_MSB 26 -#define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 - -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 - -#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 - -#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 -#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 -#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 - -#define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FSE_METADATA_LSB 32 -#define RX_MSDU_END_FSE_METADATA_MSB 63 -#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CCE_METADATA_LSB 0 -#define RX_MSDU_END_CCE_METADATA_MSB 15 -#define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff - -#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 -#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 -#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 -#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 -#define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 -#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 - -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 - -#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FISA_TIMEOUT_LSB 41 -#define RX_MSDU_END_FISA_TIMEOUT_MSB 41 -#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 - -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 - -#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 - -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 - -#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 -#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 -#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 - -#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CCE_MATCH_LSB 46 -#define RX_MSDU_END_CCE_MATCH_MSB 46 -#define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 - -#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 - -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 - -#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 -#define RX_MSDU_END_KEY_ID_OCTET_LSB 0 -#define RX_MSDU_END_KEY_ID_OCTET_MSB 7 -#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff - -#define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_16A_LSB 8 -#define RX_MSDU_END_RESERVED_16A_MSB 31 -#define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 - -#define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_17A_LSB 32 -#define RX_MSDU_END_RESERVED_17A_MSB 37 -#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 - -#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 -#define RX_MSDU_END_SERVICE_CODE_LSB 38 -#define RX_MSDU_END_SERVICE_CODE_MSB 46 -#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 - -#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 -#define RX_MSDU_END_PRIORITY_VALID_LSB 47 -#define RX_MSDU_END_PRIORITY_VALID_MSB 47 -#define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 - -#define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 -#define RX_MSDU_END_INTRA_BSS_LSB 48 -#define RX_MSDU_END_INTRA_BSS_MSB 48 -#define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 - -#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 -#define RX_MSDU_END_DEST_CHIP_ID_LSB 49 -#define RX_MSDU_END_DEST_CHIP_ID_MSB 50 -#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 - -#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 -#define RX_MSDU_END_MULTICAST_ECHO_LSB 51 -#define RX_MSDU_END_MULTICAST_ECHO_MSB 51 -#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 - -#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 -#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 -#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 - -#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 -#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 -#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 - -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 - -#define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_17B_LSB 56 -#define RX_MSDU_END_RESERVED_17B_MSB 63 -#define RX_MSDU_END_RESERVED_17B_MASK 0xff00000000000000 - -#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MSDU_LENGTH_LSB 0 -#define RX_MSDU_END_MSDU_LENGTH_MSB 13 -#define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff - -#define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 -#define RX_MSDU_END_STBC_LSB 14 -#define RX_MSDU_END_STBC_MSB 14 -#define RX_MSDU_END_STBC_MASK 0x0000000000004000 - -#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPSEC_ESP_LSB 15 -#define RX_MSDU_END_IPSEC_ESP_MSB 15 -#define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 - -#define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 -#define RX_MSDU_END_L3_OFFSET_LSB 16 -#define RX_MSDU_END_L3_OFFSET_MSB 22 -#define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 - -#define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPSEC_AH_LSB 23 -#define RX_MSDU_END_IPSEC_AH_MSB 23 -#define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 - -#define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 -#define RX_MSDU_END_L4_OFFSET_LSB 24 -#define RX_MSDU_END_L4_OFFSET_MSB 31 -#define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 - -#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MSDU_NUMBER_LSB 32 -#define RX_MSDU_END_MSDU_NUMBER_MSB 39 -#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 - -#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 -#define RX_MSDU_END_DECAP_FORMAT_LSB 40 -#define RX_MSDU_END_DECAP_FORMAT_MSB 41 -#define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 - -#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPV4_PROTO_LSB 42 -#define RX_MSDU_END_IPV4_PROTO_MSB 42 -#define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 - -#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPV6_PROTO_LSB 43 -#define RX_MSDU_END_IPV6_PROTO_MSB 43 -#define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 - -#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_PROTO_LSB 44 -#define RX_MSDU_END_TCP_PROTO_MSB 44 -#define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 - -#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_UDP_PROTO_LSB 45 -#define RX_MSDU_END_UDP_PROTO_MSB 45 -#define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 - -#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_FRAG_LSB 46 -#define RX_MSDU_END_IP_FRAG_MSB 46 -#define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 - -#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 -#define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 -#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 - -#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 - -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 - -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 - -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 - -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 - -#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 - -#define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 -#define RX_MSDU_END_LDPC_LSB 55 -#define RX_MSDU_END_LDPC_MSB 55 -#define RX_MSDU_END_LDPC_MASK 0x0080000000000000 - -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 - -#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 -#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 -#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 -#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff - -#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 -#define RX_MSDU_END_VLAN_STAG_CI_LSB 16 -#define RX_MSDU_END_VLAN_STAG_CI_MSB 31 -#define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 -#define RX_MSDU_END_PEER_META_DATA_LSB 32 -#define RX_MSDU_END_PEER_META_DATA_MSB 63 -#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 -#define RX_MSDU_END_USER_RSSI_LSB 0 -#define RX_MSDU_END_USER_RSSI_MSB 7 -#define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff - -#define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 -#define RX_MSDU_END_PKT_TYPE_LSB 8 -#define RX_MSDU_END_PKT_TYPE_MSB 11 -#define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 - -#define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 -#define RX_MSDU_END_SGI_LSB 12 -#define RX_MSDU_END_SGI_MSB 13 -#define RX_MSDU_END_SGI_MASK 0x0000000000003000 - -#define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RATE_MCS_LSB 14 -#define RX_MSDU_END_RATE_MCS_MSB 18 -#define RX_MSDU_END_RATE_MCS_MASK 0x000000000007c000 - -#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 19 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 21 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x0000000000380000 - -#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RECEPTION_TYPE_LSB 22 -#define RX_MSDU_END_RECEPTION_TYPE_MSB 24 -#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000001c00000 - -#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 -#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 25 -#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 -#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007e000000 - -#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 -#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 -#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 -#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 - -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 - -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff - -#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 -#define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 -#define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 -#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 - -#define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 -#define RX_MSDU_END_RESERVED_28A_LSB 0 -#define RX_MSDU_END_RESERVED_28A_MSB 15 -#define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff - -#define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 -#define RX_MSDU_END_SA_15_0_LSB 16 -#define RX_MSDU_END_SA_15_0_MSB 31 -#define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 -#define RX_MSDU_END_SA_47_16_LSB 32 -#define RX_MSDU_END_SA_47_16_MSB 63 -#define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 - -#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 -#define RX_MSDU_END_FIRST_MPDU_LSB 0 -#define RX_MSDU_END_FIRST_MPDU_MSB 0 -#define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 - -#define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_30A_LSB 1 -#define RX_MSDU_END_RESERVED_30A_MSB 1 -#define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 - -#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MCAST_BCAST_LSB 2 -#define RX_MSDU_END_MCAST_BCAST_MSB 2 -#define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 - -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 - -#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 - -#define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_POWER_MGMT_LSB 5 -#define RX_MSDU_END_POWER_MGMT_MSB 5 -#define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 - -#define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 -#define RX_MSDU_END_NON_QOS_LSB 6 -#define RX_MSDU_END_NON_QOS_MSB 6 -#define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 - -#define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 -#define RX_MSDU_END_NULL_DATA_LSB 7 -#define RX_MSDU_END_NULL_DATA_MSB 7 -#define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 - -#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MGMT_TYPE_LSB 8 -#define RX_MSDU_END_MGMT_TYPE_MSB 8 -#define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 - -#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_CTRL_TYPE_LSB 9 -#define RX_MSDU_END_CTRL_TYPE_MSB 9 -#define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 - -#define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MORE_DATA_LSB 10 -#define RX_MSDU_END_MORE_DATA_MSB 10 -#define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 - -#define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 -#define RX_MSDU_END_EOSP_LSB 11 -#define RX_MSDU_END_EOSP_MSB 11 -#define RX_MSDU_END_EOSP_MASK 0x0000000000000800 - -#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_A_MSDU_ERROR_LSB 12 -#define RX_MSDU_END_A_MSDU_ERROR_MSB 12 -#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 - -#define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_30B_LSB 13 -#define RX_MSDU_END_RESERVED_30B_MSB 13 -#define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 - -#define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 -#define RX_MSDU_END_ORDER_LSB 14 -#define RX_MSDU_END_ORDER_MSB 14 -#define RX_MSDU_END_ORDER_MASK 0x0000000000004000 - -#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 -#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 -#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 - -#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_OVERFLOW_ERR_LSB 16 -#define RX_MSDU_END_OVERFLOW_ERR_MSB 16 -#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 - -#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 -#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 -#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 - -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 - -#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 -#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 -#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 -#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 - -#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 -#define RX_MSDU_END_SA_IDX_INVALID_LSB 20 -#define RX_MSDU_END_SA_IDX_INVALID_MSB 20 -#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 - -#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DA_IDX_INVALID_LSB 21 -#define RX_MSDU_END_DA_IDX_INVALID_MSB 21 -#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 - -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 - -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 - -#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 -#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 -#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 - -#define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DIRECTED_LSB 25 -#define RX_MSDU_END_DIRECTED_MSB 25 -#define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 - -#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 -#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 -#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 - -#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 -#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 -#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 - -#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 -#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 -#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 - -#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DECRYPT_ERR_LSB 29 -#define RX_MSDU_END_DECRYPT_ERR_MSB 29 -#define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 - -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 - -#define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_FCS_ERR_LSB 31 -#define RX_MSDU_END_FCS_ERR_MSB 31 -#define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 - -#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_31A_LSB 32 -#define RX_MSDU_END_RESERVED_31A_MSB 41 -#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 - -#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 - -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 - -#define RX_MSDU_END_IFCS_PRESENT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_IFCS_PRESENT_LSB 46 -#define RX_MSDU_END_IFCS_PRESENT_MSB 46 -#define RX_MSDU_END_IFCS_PRESENT_MASK 0x0000400000000000 - -#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_31B_LSB 47 -#define RX_MSDU_END_RESERVED_31B_MSB 62 -#define RX_MSDU_END_RESERVED_31B_MASK 0x7fff800000000000 - -#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MSDU_DONE_LSB 63 -#define RX_MSDU_END_MSDU_DONE_MSB 63 -#define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_ext_desc_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_ext_desc_info.h deleted file mode 100644 index 70bda69ddfec..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_ext_desc_info.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_EXT_DESC_INFO_H_ -#define _RX_MSDU_EXT_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 - -struct rx_msdu_ext_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reo_destination_indication : 5, - service_code : 9, - priority_valid : 1, - data_offset : 12, - src_link_id : 3, - reserved_0a : 2; -#else - uint32_t reserved_0a : 2, - src_link_id : 3, - data_offset : 12, - priority_valid : 1, - service_code : 9, - reo_destination_indication : 5; -#endif -}; - -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_link.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_link.h deleted file mode 100644 index c54357dae2ef..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_link.h +++ /dev/null @@ -1,2051 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_LINK_H_ -#define _RX_MSDU_LINK_H_ - -#include "uniform_descriptor_header.h" -#include "buffer_addr_info.h" -#include "rx_msdu_details.h" -#define NUM_OF_DWORDS_RX_MSDU_LINK 64 - -struct rx_msdu_link { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct uniform_descriptor_header descriptor_header; - struct buffer_addr_info next_msdu_link_desc_addr_info; - uint32_t reserved_3a : 32; - struct rx_msdu_details msdu_0; - struct rx_msdu_details msdu_1; - struct rx_msdu_details msdu_2; - struct rx_msdu_details msdu_3; - struct rx_msdu_details msdu_4; - struct rx_msdu_details msdu_5; - struct rx_msdu_details msdu_6; - struct rx_msdu_details msdu_7; - struct rx_msdu_details msdu_8; - struct rx_msdu_details msdu_9; - struct rx_msdu_details msdu_10; - struct rx_msdu_details msdu_11; - struct rx_msdu_details msdu_12; - struct rx_msdu_details msdu_13; - struct rx_msdu_details msdu_14; -#else - struct uniform_descriptor_header descriptor_header; - struct buffer_addr_info next_msdu_link_desc_addr_info; - uint32_t reserved_3a : 32; - struct rx_msdu_details msdu_0; - struct rx_msdu_details msdu_1; - struct rx_msdu_details msdu_2; - struct rx_msdu_details msdu_3; - struct rx_msdu_details msdu_4; - struct rx_msdu_details msdu_5; - struct rx_msdu_details msdu_6; - struct rx_msdu_details msdu_7; - struct rx_msdu_details msdu_8; - struct rx_msdu_details msdu_9; - struct rx_msdu_details msdu_10; - struct rx_msdu_details msdu_11; - struct rx_msdu_details msdu_12; - struct rx_msdu_details msdu_13; - struct rx_msdu_details msdu_14; -#endif -}; - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c -#define RX_MSDU_LINK_RESERVED_3A_LSB 0 -#define RX_MSDU_LINK_RESERVED_3A_MSB 31 -#define RX_MSDU_LINK_RESERVED_3A_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000010 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000080 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000090 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000a0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000b0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000c0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000d0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000e0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000f0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_start.h deleted file mode 100644 index e1e99c027c85..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_start.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_START_H_ -#define _RX_MSDU_START_H_ - -#define NUM_OF_DWORDS_RX_MSDU_START 10 - -#define NUM_OF_QWORDS_RX_MSDU_START 5 - -struct rx_msdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - rate_mcs : 5, - reserved_0 : 2, - phy_ppdu_id : 16; - uint32_t msdu_length : 14, - stbc : 1, - ipsec_esp : 1, - l3_offset : 7, - ipsec_ah : 1, - l4_offset : 8; - uint32_t msdu_number : 8, - decap_format : 2, - ipv4_proto : 1, - ipv6_proto : 1, - tcp_proto : 1, - udp_proto : 1, - ip_frag : 1, - tcp_only_ack : 1, - da_is_bcast_mcast : 1, - toeplitz_hash_sel : 2, - ip_fixed_header_valid : 1, - ip_extn_header_valid : 1, - tcp_udp_header_valid : 1, - mesh_control_present : 1, - ldpc : 1, - ip4_protocol_ip6_next_header : 8; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t flow_id_toeplitz : 32; - uint32_t user_rssi : 8, - pkt_type : 4, - sgi : 2, - reserved_5a : 4, - receive_bandwidth : 3, - reception_type : 3, - mimo_ss_bitmap : 8; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t vlan_ctag_ci : 16, - vlan_stag_ci : 16; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 2, - rate_mcs : 5, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t l4_offset : 8, - ipsec_ah : 1, - l3_offset : 7, - ipsec_esp : 1, - stbc : 1, - msdu_length : 14; - uint32_t ip4_protocol_ip6_next_header : 8, - ldpc : 1, - mesh_control_present : 1, - tcp_udp_header_valid : 1, - ip_extn_header_valid : 1, - ip_fixed_header_valid : 1, - toeplitz_hash_sel : 2, - da_is_bcast_mcast : 1, - tcp_only_ack : 1, - ip_frag : 1, - udp_proto : 1, - tcp_proto : 1, - ipv6_proto : 1, - ipv4_proto : 1, - decap_format : 2, - msdu_number : 8; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t flow_id_toeplitz : 32; - uint32_t mimo_ss_bitmap : 8, - reception_type : 3, - receive_bandwidth : 3, - reserved_5a : 4, - sgi : 2, - pkt_type : 4, - user_rssi : 8; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t vlan_stag_ci : 16, - vlan_ctag_ci : 16; -#endif -}; - -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MSDU_START_RATE_MCS_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RATE_MCS_LSB 9 -#define RX_MSDU_START_RATE_MCS_MSB 13 -#define RX_MSDU_START_RATE_MCS_MASK 0x0000000000003e00 - -#define RX_MSDU_START_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RESERVED_0_LSB 14 -#define RX_MSDU_START_RESERVED_0_MSB 15 -#define RX_MSDU_START_RESERVED_0_MASK 0x000000000000c000 - -#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_START_PHY_PPDU_ID_LSB 16 -#define RX_MSDU_START_PHY_PPDU_ID_MSB 31 -#define RX_MSDU_START_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x0000000000000000 -#define RX_MSDU_START_MSDU_LENGTH_LSB 32 -#define RX_MSDU_START_MSDU_LENGTH_MSB 45 -#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff00000000 - -#define RX_MSDU_START_STBC_OFFSET 0x0000000000000000 -#define RX_MSDU_START_STBC_LSB 46 -#define RX_MSDU_START_STBC_MSB 46 -#define RX_MSDU_START_STBC_MASK 0x0000400000000000 - -#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x0000000000000000 -#define RX_MSDU_START_IPSEC_ESP_LSB 47 -#define RX_MSDU_START_IPSEC_ESP_MSB 47 -#define RX_MSDU_START_IPSEC_ESP_MASK 0x0000800000000000 - -#define RX_MSDU_START_L3_OFFSET_OFFSET 0x0000000000000000 -#define RX_MSDU_START_L3_OFFSET_LSB 48 -#define RX_MSDU_START_L3_OFFSET_MSB 54 -#define RX_MSDU_START_L3_OFFSET_MASK 0x007f000000000000 - -#define RX_MSDU_START_IPSEC_AH_OFFSET 0x0000000000000000 -#define RX_MSDU_START_IPSEC_AH_LSB 55 -#define RX_MSDU_START_IPSEC_AH_MSB 55 -#define RX_MSDU_START_IPSEC_AH_MASK 0x0080000000000000 - -#define RX_MSDU_START_L4_OFFSET_OFFSET 0x0000000000000000 -#define RX_MSDU_START_L4_OFFSET_LSB 56 -#define RX_MSDU_START_L4_OFFSET_MSB 63 -#define RX_MSDU_START_L4_OFFSET_MASK 0xff00000000000000 - -#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x0000000000000008 -#define RX_MSDU_START_MSDU_NUMBER_LSB 0 -#define RX_MSDU_START_MSDU_NUMBER_MSB 7 -#define RX_MSDU_START_MSDU_NUMBER_MASK 0x00000000000000ff - -#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x0000000000000008 -#define RX_MSDU_START_DECAP_FORMAT_LSB 8 -#define RX_MSDU_START_DECAP_FORMAT_MSB 9 -#define RX_MSDU_START_DECAP_FORMAT_MASK 0x0000000000000300 - -#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IPV4_PROTO_LSB 10 -#define RX_MSDU_START_IPV4_PROTO_MSB 10 -#define RX_MSDU_START_IPV4_PROTO_MASK 0x0000000000000400 - -#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IPV6_PROTO_LSB 11 -#define RX_MSDU_START_IPV6_PROTO_MSB 11 -#define RX_MSDU_START_IPV6_PROTO_MASK 0x0000000000000800 - -#define RX_MSDU_START_TCP_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_PROTO_LSB 12 -#define RX_MSDU_START_TCP_PROTO_MSB 12 -#define RX_MSDU_START_TCP_PROTO_MASK 0x0000000000001000 - -#define RX_MSDU_START_UDP_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_UDP_PROTO_LSB 13 -#define RX_MSDU_START_UDP_PROTO_MSB 13 -#define RX_MSDU_START_UDP_PROTO_MASK 0x0000000000002000 - -#define RX_MSDU_START_IP_FRAG_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_FRAG_LSB 14 -#define RX_MSDU_START_IP_FRAG_MSB 14 -#define RX_MSDU_START_IP_FRAG_MASK 0x0000000000004000 - -#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 -#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 -#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x0000000000008000 - -#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000008 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x0000000000010000 - -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x0000000000060000 - -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x0000000000080000 - -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x0000000000100000 - -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x0000000000200000 - -#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000008 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x0000000000400000 - -#define RX_MSDU_START_LDPC_OFFSET 0x0000000000000008 -#define RX_MSDU_START_LDPC_LSB 23 -#define RX_MSDU_START_LDPC_MSB 23 -#define RX_MSDU_START_LDPC_MASK 0x0000000000800000 - -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00000000ff000000 - -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 32 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 63 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 - -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000010 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0x00000000ffffffff - -#define RX_MSDU_START_USER_RSSI_OFFSET 0x0000000000000010 -#define RX_MSDU_START_USER_RSSI_LSB 32 -#define RX_MSDU_START_USER_RSSI_MSB 39 -#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff00000000 - -#define RX_MSDU_START_PKT_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_START_PKT_TYPE_LSB 40 -#define RX_MSDU_START_PKT_TYPE_MSB 43 -#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f0000000000 - -#define RX_MSDU_START_SGI_OFFSET 0x0000000000000010 -#define RX_MSDU_START_SGI_LSB 44 -#define RX_MSDU_START_SGI_MSB 45 -#define RX_MSDU_START_SGI_MASK 0x0000300000000000 - -#define RX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RESERVED_5A_LSB 46 -#define RX_MSDU_START_RESERVED_5A_MSB 49 -#define RX_MSDU_START_RESERVED_5A_MASK 0x0003c00000000000 - -#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 50 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 52 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c000000000000 - -#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RECEPTION_TYPE_LSB 53 -#define RX_MSDU_START_RECEPTION_TYPE_MSB 55 -#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e0000000000000 - -#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x0000000000000010 -#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 56 -#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 63 -#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff00000000000000 - -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000018 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000018 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 - -#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000020 -#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 -#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 -#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0x00000000ffffffff - -#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x0000000000000020 -#define RX_MSDU_START_VLAN_CTAG_CI_LSB 32 -#define RX_MSDU_START_VLAN_CTAG_CI_MSB 47 -#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff00000000 - -#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x0000000000000020 -#define RX_MSDU_START_VLAN_STAG_CI_LSB 48 -#define RX_MSDU_START_VLAN_STAG_CI_MSB 63 -#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_ack_report.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_ack_report.h deleted file mode 100644 index 345b14ea4255..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_ack_report.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_ACK_REPORT_H_ -#define _RX_PPDU_ACK_REPORT_H_ - -#include "ack_report.h" -#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2 - -#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1 - -struct rx_ppdu_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ack_report ack_report_details; - uint32_t tlv64_padding : 32; -#else - struct ack_report ack_report_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x000000000000000f - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000000f0 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x0000000000000100 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x000000000000fe00 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 - -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB 32 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB 63 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats.h deleted file mode 100644 index 51db8f35a6ab..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats.h +++ /dev/null @@ -1,679 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_END_USER_STATS_H_ -#define _RX_PPDU_END_USER_STATS_H_ - -#include "rx_rxpcu_classification_overview.h" -#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 - -#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15 - -struct rx_ppdu_end_user_stats { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t sta_full_aid : 13, - mcs : 5, - nss : 3, - expected_response_ack_or_ba : 1, - reserved_1a : 10; - uint32_t sw_peer_id : 16, - mpdu_cnt_fcs_err : 11, - sw2rxdma0_buf_source_used : 1, - fw2rxdma0_buf_source_used : 1, - sw2rxdma1_buf_source_used : 1, - sw2rxdma2_buf_source_used : 1, - fw2rxdma1_buf_source_used : 1; - uint32_t mpdu_cnt_fcs_ok : 11, - frame_control_info_valid : 1, - qos_control_info_valid : 1, - ht_control_info_valid : 1, - data_sequence_control_info_valid : 1, - ht_control_info_null_valid : 1, - rxdma2fw0_ring_used : 1, - rxdma2fw1_ring_used : 1, - rxdma2fwreo_0_ring_used : 1, - rxdma2fwreo_1_ring_used : 1, - reserved_3a : 1, - ht_control_field_pkt_type : 4, - reserved_3b : 7; - uint32_t ast_index : 16, - frame_control_field : 16; - uint32_t first_data_seq_ctrl : 16, - qos_control_field : 16; - uint32_t ht_control_field : 32; - uint32_t fcs_ok_bitmap_31_0 : 32; - uint32_t fcs_ok_bitmap_63_32 : 32; - uint32_t udp_msdu_count : 16, - tcp_msdu_count : 16; - uint32_t other_msdu_count : 16, - tcp_ack_msdu_count : 16; - uint32_t sw_response_reference_ptr : 32; - uint32_t received_qos_data_tid_bitmap : 16, - received_qos_data_tid_eosp_bitmap : 16; - uint32_t qosctrl_15_8_tid0 : 8, - qosctrl_15_8_tid1 : 8, - qosctrl_15_8_tid2 : 8, - qosctrl_15_8_tid3 : 8; - uint32_t qosctrl_15_8_tid4 : 8, - qosctrl_15_8_tid5 : 8, - qosctrl_15_8_tid6 : 8, - qosctrl_15_8_tid7 : 8; - uint32_t qosctrl_15_8_tid8 : 8, - qosctrl_15_8_tid9 : 8, - qosctrl_15_8_tid10 : 8, - qosctrl_15_8_tid11 : 8; - uint32_t qosctrl_15_8_tid12 : 8, - qosctrl_15_8_tid13 : 8, - qosctrl_15_8_tid14 : 8, - qosctrl_15_8_tid15 : 8; - uint32_t mpdu_ok_byte_count : 25, - ampdu_delim_ok_count_6_0 : 7; - uint32_t ampdu_delim_err_count : 25, - ampdu_delim_ok_count_13_7 : 7; - uint32_t mpdu_err_byte_count : 25, - ampdu_delim_ok_count_20_14 : 7; - uint32_t non_consecutive_delimiter_err : 16, - retried_msdu_count : 16; - uint32_t ht_control_null_field : 32; - uint32_t sw_response_reference_ptr_ext : 32; - uint32_t corrupted_due_to_fifo_delay : 1, - frame_control_info_null_valid : 1, - frame_control_field_null : 16, - retried_mpdu_count : 11, - reserved_23a : 3; - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_24a : 4, - frame_control_info_mgmt_ctrl_valid : 1, - mac_addr_ad2_valid : 1, - mcast_bcast : 1, - frame_control_field_mgmt_ctrl : 16; - uint32_t user_ppdu_len : 24, - reserved_25a : 8; - uint32_t mac_addr_ad2_31_0 : 32; - uint32_t mac_addr_ad2_47_32 : 16, - amsdu_msdu_count : 16; - uint32_t non_amsdu_msdu_count : 16, - ucast_msdu_count : 16; - uint32_t bcast_msdu_count : 16, - mcast_bcast_msdu_count : 16; -#else - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t reserved_1a : 10, - expected_response_ack_or_ba : 1, - nss : 3, - mcs : 5, - sta_full_aid : 13; - uint32_t fw2rxdma1_buf_source_used : 1, - sw2rxdma2_buf_source_used : 1, - sw2rxdma1_buf_source_used : 1, - fw2rxdma0_buf_source_used : 1, - sw2rxdma0_buf_source_used : 1, - mpdu_cnt_fcs_err : 11, - sw_peer_id : 16; - uint32_t reserved_3b : 7, - ht_control_field_pkt_type : 4, - reserved_3a : 1, - rxdma2fwreo_1_ring_used : 1, - rxdma2fwreo_0_ring_used : 1, - rxdma2fw1_ring_used : 1, - rxdma2fw0_ring_used : 1, - ht_control_info_null_valid : 1, - data_sequence_control_info_valid : 1, - ht_control_info_valid : 1, - qos_control_info_valid : 1, - frame_control_info_valid : 1, - mpdu_cnt_fcs_ok : 11; - uint32_t frame_control_field : 16, - ast_index : 16; - uint32_t qos_control_field : 16, - first_data_seq_ctrl : 16; - uint32_t ht_control_field : 32; - uint32_t fcs_ok_bitmap_31_0 : 32; - uint32_t fcs_ok_bitmap_63_32 : 32; - uint32_t tcp_msdu_count : 16, - udp_msdu_count : 16; - uint32_t tcp_ack_msdu_count : 16, - other_msdu_count : 16; - uint32_t sw_response_reference_ptr : 32; - uint32_t received_qos_data_tid_eosp_bitmap : 16, - received_qos_data_tid_bitmap : 16; - uint32_t qosctrl_15_8_tid3 : 8, - qosctrl_15_8_tid2 : 8, - qosctrl_15_8_tid1 : 8, - qosctrl_15_8_tid0 : 8; - uint32_t qosctrl_15_8_tid7 : 8, - qosctrl_15_8_tid6 : 8, - qosctrl_15_8_tid5 : 8, - qosctrl_15_8_tid4 : 8; - uint32_t qosctrl_15_8_tid11 : 8, - qosctrl_15_8_tid10 : 8, - qosctrl_15_8_tid9 : 8, - qosctrl_15_8_tid8 : 8; - uint32_t qosctrl_15_8_tid15 : 8, - qosctrl_15_8_tid14 : 8, - qosctrl_15_8_tid13 : 8, - qosctrl_15_8_tid12 : 8; - uint32_t ampdu_delim_ok_count_6_0 : 7, - mpdu_ok_byte_count : 25; - uint32_t ampdu_delim_ok_count_13_7 : 7, - ampdu_delim_err_count : 25; - uint32_t ampdu_delim_ok_count_20_14 : 7, - mpdu_err_byte_count : 25; - uint32_t retried_msdu_count : 16, - non_consecutive_delimiter_err : 16; - uint32_t ht_control_null_field : 32; - uint32_t sw_response_reference_ptr_ext : 32; - uint32_t reserved_23a : 3, - retried_mpdu_count : 11, - frame_control_field_null : 16, - frame_control_info_null_valid : 1, - corrupted_due_to_fifo_delay : 1; - uint32_t frame_control_field_mgmt_ctrl : 16, - mcast_bcast : 1, - mac_addr_ad2_valid : 1, - frame_control_info_mgmt_ctrl_valid : 1, - reserved_24a : 4, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_25a : 8, - user_ppdu_len : 24; - uint32_t mac_addr_ad2_31_0 : 32; - uint32_t amsdu_msdu_count : 16, - mac_addr_ad2_47_32 : 16; - uint32_t ucast_msdu_count : 16, - non_amsdu_msdu_count : 16; - uint32_t mcast_bcast_msdu_count : 16, - bcast_msdu_count : 16; -#endif -}; - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 - -#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_MCS_LSB 45 -#define RX_PPDU_END_USER_STATS_MCS_MSB 49 -#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0003e00000000000 - -#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_NSS_LSB 50 -#define RX_PPDU_END_USER_STATS_NSS_MSB 52 -#define RX_PPDU_END_USER_STATS_NSS_MASK 0x001c000000000000 - -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 53 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 53 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0020000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 54 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffc0000000000000 - -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 - -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_LSB 28 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MSB 28 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000010000000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_LSB 30 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MSB 30 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MASK 0x0000000040000000 - -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_LSB 31 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MSB 31 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000080000000 - -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 - -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 - -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_LSB 48 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MSB 48 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MASK 0x0001000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_LSB 49 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MSB 49 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MASK 0x0002000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_LSB 50 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MSB 50 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MASK 0x0004000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_LSB 51 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MSB 51 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MASK 0x0008000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_LSB 52 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_MSB 52 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_MASK 0x0010000000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 57 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 -#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 -#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 - -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 - -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 - -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 - -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x0000000000001e00 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x0000000000002000 - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x0000000000004000 - -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x0000000000008000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 32 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 55 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff00000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 56 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 32 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 47 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 47 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h deleted file mode 100644 index 0a11202db481..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ -#define _RX_PPDU_END_USER_STATS_EXT_H_ - -#include "rx_rxpcu_classification_overview.h" -#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 - -#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4 - -struct rx_ppdu_end_user_stats_ext { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t fcs_ok_bitmap_95_64 : 32; - uint32_t fcs_ok_bitmap_127_96 : 32; - uint32_t fcs_ok_bitmap_159_128 : 32; - uint32_t fcs_ok_bitmap_191_160 : 32; - uint32_t fcs_ok_bitmap_223_192 : 32; - uint32_t fcs_ok_bitmap_255_224 : 32; - uint32_t corrupted_due_to_fifo_delay : 1, - reserved_7a : 31; -#else - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t fcs_ok_bitmap_95_64 : 32; - uint32_t fcs_ok_bitmap_127_96 : 32; - uint32_t fcs_ok_bitmap_159_128 : 32; - uint32_t fcs_ok_bitmap_191_160 : 32; - uint32_t fcs_ok_bitmap_223_192 : 32; - uint32_t fcs_ok_bitmap_255_224 : 32; - uint32_t reserved_7a : 31, - corrupted_due_to_fifo_delay : 1; -#endif -}; - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 - -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 33 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_no_ack_report.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_no_ack_report.h deleted file mode 100644 index d9c54c04df32..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_no_ack_report.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_NO_ACK_REPORT_H_ -#define _RX_PPDU_NO_ACK_REPORT_H_ - -#include "no_ack_report.h" -#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 - -#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2 - -struct rx_ppdu_no_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct no_ack_report no_ack_report_details; -#else - struct no_ack_report no_ack_report_details; -#endif -}; - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x000000000000000f - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000f0 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000000000ff00 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 32 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 55 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff00000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 56 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 56 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x0100000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 61 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 63 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0x00000000ff000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 44 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 63 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff00000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start.h deleted file mode 100644 index 19765eb4409b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_START_H_ -#define _RX_PPDU_START_H_ - -#define NUM_OF_DWORDS_RX_PPDU_START 6 - -#define NUM_OF_QWORDS_RX_PPDU_START 3 - -struct rx_ppdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - preamble_time_to_rxframe : 8, - reserved_0a : 8; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t rxframe_assert_timestamp : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 8, - preamble_time_to_rxframe : 8, - phy_ppdu_id : 16; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t rxframe_assert_timestamp : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_START_PHY_PPDU_ID_LSB 0 -#define RX_PPDU_START_PHY_PPDU_ID_MSB 15 -#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 - -#define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_PPDU_START_RESERVED_0A_LSB 24 -#define RX_PPDU_START_RESERVED_0A_MSB 31 -#define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 - -#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 -#define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 -#define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 -#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 - -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 - -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff - -#define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 -#define RX_PPDU_START_TLV64_PADDING_LSB 32 -#define RX_PPDU_START_TLV64_PADDING_MSB 63 -#define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start_user_info.h deleted file mode 100644 index 16d3bb33edb4..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start_user_info.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_START_USER_INFO_H_ -#define _RX_PPDU_START_USER_INFO_H_ - -#include "receive_user_info.h" -#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8 - -#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 4 - -struct rx_ppdu_start_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_user_info receive_user_info_details; -#else - struct receive_user_info receive_user_info_details; -#endif -}; - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 36 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000001f00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 37 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 38 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000006000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 1 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x0000000000000002 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB 2 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB 3 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK 0x000000000000000c - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB 4 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB 5 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK 0x0000000000000030 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB 6 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB 7 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK 0x00000000000000c0 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_LSB 62 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MSB 62 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MASK 0x4000000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0x8000000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_preamble.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_preamble.h deleted file mode 100644 index 807463753865..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_preamble.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PREAMBLE_H_ -#define _RX_PREAMBLE_H_ - -#define NUM_OF_DWORDS_RX_PREAMBLE 2 - -#define NUM_OF_QWORDS_RX_PREAMBLE 1 - -struct rx_preamble { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t num_users : 6, - pkt_type : 4, - direction : 1, - reserved_0a : 21; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 21, - direction : 1, - pkt_type : 4, - num_users : 6; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PREAMBLE_NUM_USERS_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_NUM_USERS_LSB 0 -#define RX_PREAMBLE_NUM_USERS_MSB 5 -#define RX_PREAMBLE_NUM_USERS_MASK 0x000000000000003f - -#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_PKT_TYPE_LSB 6 -#define RX_PREAMBLE_PKT_TYPE_MSB 9 -#define RX_PREAMBLE_PKT_TYPE_MASK 0x00000000000003c0 - -#define RX_PREAMBLE_DIRECTION_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_DIRECTION_LSB 10 -#define RX_PREAMBLE_DIRECTION_MSB 10 -#define RX_PREAMBLE_DIRECTION_MASK 0x0000000000000400 - -#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_RESERVED_0A_LSB 11 -#define RX_PREAMBLE_RESERVED_0A_MSB 31 -#define RX_PREAMBLE_RESERVED_0A_MASK 0x00000000fffff800 - -#define RX_PREAMBLE_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_TLV64_PADDING_LSB 32 -#define RX_PREAMBLE_TLV64_PADDING_MSB 63 -#define RX_PREAMBLE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_response_required_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_response_required_info.h deleted file mode 100644 index e6ee112bb1ac..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_response_required_info.h +++ /dev/null @@ -1,764 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ -#define _RX_RESPONSE_REQUIRED_INFO_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 - -#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 - -struct rx_response_required_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - su_or_uplink_mu_reception : 1, - trigger_frame_received : 1, - __reserved_g_0012 : 2, - tb___reserved_g_0005_response_required : 2, - mac_security : 1, - filter_pass_monitor_ovrd : 1, - ast_search_incomplete : 1, - r2r_end_status_to_follow : 1, - __reserved_g_0016_listen_cca_check_at_phy_desc : 1, - __reserved_g_0016_listen_indication : 1, - three_or_more_type_subtypes : 1, - wait_sifs_config_valid : 1, - wait_sifs : 2; - uint32_t general_frame_control : 16, - second_frame_control : 16; - uint32_t duration : 16, - pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5, - sgi : 2, - stbc : 1, - ldpc : 1, - ampdu : 1, - rts_ta_grp_bit : 1; - uint32_t ctrl_frame_soliciting_resp : 1, - ast_fail_for_dot11ax_su_ext : 1, - service_dynamic : 1, - m_pkt : 1, - sta_partial_aid : 12, - group_id : 6, - ctrl_resp_pwr_mgmt : 1, - response_indication : 2, - ndp_indication : 1, - ndp_frame_type : 3, - second_frame_control_valid : 1, - ack_ba_resp_more_data : 1, - vht_ack : 1; - uint32_t sta_aid : 11, - interference : 1, - ects_as_tb_ppdu : 1, - ll_traffic_indication : 1, - reserved_4a : 2, - ack_id_ext : 10, - agc_cbw : 3, - service_cbw : 3; - uint32_t response_sta_count : 7, - __reserved_g_0086 : 1, - blackout_details_en : 1, - reserved : 2, - ht_vht_sig_cbw : 3, - cts_cbw : 3, - response_ack_count : 7, - response_assoc_ack_count : 7, - txop_duration_all_ones : 1; - uint32_t response_ba32_count : 7, - response_ba64_count : 7, - response_ba128_count : 7, - response_ba256_count : 7, - multi_tid : 1, - sw_response_tlv_from_crypto : 1, - dot11ax_dl_ul_flag : 1, - emlsr_main_tlv_if : 1; - uint32_t sw_response_frame_length : 16, - response_ba512_count : 7, - response_ba1024_count : 7, - reserved_7a : 2; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t dot11ax_received_format_indication : 1, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_bss_color_id : 6, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_cp_size : 2, - dot11ax_received_ltf_size : 2, - dot11ax_received_coding : 1, - dot11ax_received_dcm : 1, - dot11ax_received_doppler_indication : 1, - dot11ax_received_ext_ru_size : 4, - ftm_fields_valid : 1, - ftm_pe_nss : 3, - ftm_pe_ltf_size : 2, - ftm_pe_content : 1, - ftm_chain_csd_en : 1, - ftm_pe_chain_csd_en : 1; - uint32_t dot11ax_response_rate_source : 8, - dot11ax_ext_response_rate_source : 8, - sw_peer_id : 16; - uint32_t dot11be_puncture_bitmap : 16, - dot11be_response : 1, - punctured_response : 1, - eht_duplicate_mode : 2, - force_extra_symbol : 1, - ctrl_pkt_protect : 1, - mac_hdr_protect : 1, - reserved_13a : 3, - u_sig_puncture_pattern_encoding : 6; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t he_a_control_response_time : 12, - reserved_after_struct16 : 4; - uint32_t dso_primary20_index_select : 4, - dso_freq_subband_channel_bonding_mask : 16, - pad_duration : 5, - q2q_mba : 1, - reserved_15a : 6; -#else - uint32_t wait_sifs : 2, - wait_sifs_config_valid : 1, - three_or_more_type_subtypes : 1, - __reserved_g_0016_listen_indication : 1, - __reserved_g_0016_listen_cca_check_at_phy_desc : 1, - r2r_end_status_to_follow : 1, - ast_search_incomplete : 1, - filter_pass_monitor_ovrd : 1, - mac_security : 1, - tb___reserved_g_0005_response_required : 2, - __reserved_g_0012 : 2, - trigger_frame_received : 1, - su_or_uplink_mu_reception : 1, - phy_ppdu_id : 16; - uint32_t second_frame_control : 16, - general_frame_control : 16; - uint32_t rts_ta_grp_bit : 1, - ampdu : 1, - ldpc : 1, - stbc : 1, - sgi : 2, - rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4, - duration : 16; - uint32_t vht_ack : 1, - ack_ba_resp_more_data : 1, - second_frame_control_valid : 1, - ndp_frame_type : 3, - ndp_indication : 1, - response_indication : 2, - ctrl_resp_pwr_mgmt : 1, - group_id : 6, - sta_partial_aid : 12, - m_pkt : 1, - service_dynamic : 1, - ast_fail_for_dot11ax_su_ext : 1, - ctrl_frame_soliciting_resp : 1; - uint32_t service_cbw : 3, - agc_cbw : 3, - ack_id_ext : 10, - reserved_4a : 2, - ll_traffic_indication : 1, - ects_as_tb_ppdu : 1, - interference : 1, - sta_aid : 11; - uint32_t txop_duration_all_ones : 1, - response_assoc_ack_count : 7, - response_ack_count : 7, - cts_cbw : 3, - ht_vht_sig_cbw : 3, - reserved : 2, - blackout_details_en : 1, - __reserved_g_0086 : 1, - response_sta_count : 7; - uint32_t emlsr_main_tlv_if : 1, - dot11ax_dl_ul_flag : 1, - sw_response_tlv_from_crypto : 1, - multi_tid : 1, - response_ba256_count : 7, - response_ba128_count : 7, - response_ba64_count : 7, - response_ba32_count : 7; - uint32_t reserved_7a : 2, - response_ba1024_count : 7, - response_ba512_count : 7, - sw_response_frame_length : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ftm_pe_chain_csd_en : 1, - ftm_chain_csd_en : 1, - ftm_pe_content : 1, - ftm_pe_ltf_size : 2, - ftm_pe_nss : 3, - ftm_fields_valid : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_received_doppler_indication : 1, - dot11ax_received_dcm : 1, - dot11ax_received_coding : 1, - dot11ax_received_ltf_size : 2, - dot11ax_received_cp_size : 2, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_bss_color_id : 6, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_format_indication : 1; - uint32_t sw_peer_id : 16, - dot11ax_ext_response_rate_source : 8, - dot11ax_response_rate_source : 8; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_13a : 3, - mac_hdr_protect : 1, - ctrl_pkt_protect : 1, - force_extra_symbol : 1, - eht_duplicate_mode : 2, - punctured_response : 1, - dot11be_response : 1, - dot11be_puncture_bitmap : 16; - uint32_t reserved_after_struct16 : 4, - he_a_control_response_time : 12; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint32_t reserved_15a : 6, - q2q_mba : 1, - pad_duration : 5, - dso_freq_subband_channel_bonding_mask : 16, - dso_primary20_index_select : 4; -#endif -}; - -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 - -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 - -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 - -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 - -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 - -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 - -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 - -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff - -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 - -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000003e00000 - -#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 26 -#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x000000000c000000 - -#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 30 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000040000000 - -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 - -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 - -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 - -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 - -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 - -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK 0x4000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MSB 10 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MASK 0x00000000000007ff - -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_LSB 11 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MSB 11 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MASK 0x0000000000000800 - -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_LSB 12 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MSB 12 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MASK 0x0000000000001000 - -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_LSB 13 -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_MSB 13 -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_MASK 0x0000000000002000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_LSB 14 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MASK 0x000000000000c000 - -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 - -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 - -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 - -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_LSB 40 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MSB 40 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MASK 0x0000010000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 41 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000060000000000 - -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 - -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 - -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB 31 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK 0x0000000080000000 - -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 - -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_LSB 53 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MSB 53 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MASK 0x0020000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_LSB 54 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MASK 0x0040000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x0380000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 - -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MSB 35 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MASK 0x0000000f00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 36 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 51 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000ffff000000000 - -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_LSB 52 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MSB 56 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MASK 0x01f0000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_LSB 57 -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_MASK 0x0200000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MASK 0xfc00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_rxpcu_classification_overview.h deleted file mode 100644 index 92489a5f5b2d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_rxpcu_classification_overview.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ -#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ - -#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 - -struct rx_rxpcu_classification_overview { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t filter_pass_mpdus : 1, - filter_pass_mpdus_fcs_ok : 1, - monitor_direct_mpdus : 1, - monitor_direct_mpdus_fcs_ok : 1, - monitor_other_mpdus : 1, - monitor_other_mpdus_fcs_ok : 1, - phyrx_abort_received : 1, - filter_pass_monitor_ovrd_mpdus : 1, - filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, - reserved_0 : 7, - phy_ppdu_id : 16; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, - filter_pass_monitor_ovrd_mpdus : 1, - phyrx_abort_received : 1, - monitor_other_mpdus_fcs_ok : 1, - monitor_other_mpdus : 1, - monitor_direct_mpdus_fcs_ok : 1, - monitor_direct_mpdus : 1, - filter_pass_mpdus_fcs_ok : 1, - filter_pass_mpdus : 1; -#endif -}; - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_start_param.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_start_param.h deleted file mode 100644 index bb2b87e3cc97..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_start_param.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_START_PARAM_H_ -#define _RX_START_PARAM_H_ - -#define NUM_OF_DWORDS_RX_START_PARAM 2 - -#define NUM_OF_QWORDS_RX_START_PARAM 1 - -struct rx_start_param { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pkt_type : 4, - reserved_0a : 12, - remaining_rx_time : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t remaining_rx_time : 16, - reserved_0a : 12, - pkt_type : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_START_PARAM_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_START_PARAM_PKT_TYPE_LSB 0 -#define RX_START_PARAM_PKT_TYPE_MSB 3 -#define RX_START_PARAM_PKT_TYPE_MASK 0x000000000000000f - -#define RX_START_PARAM_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_START_PARAM_RESERVED_0A_LSB 4 -#define RX_START_PARAM_RESERVED_0A_MSB 15 -#define RX_START_PARAM_RESERVED_0A_MASK 0x000000000000fff0 - -#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x0000000000000000 -#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 -#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 -#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0x00000000ffff0000 - -#define RX_START_PARAM_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_START_PARAM_TLV64_PADDING_LSB 32 -#define RX_START_PARAM_TLV64_PADDING_MSB 63 -#define RX_START_PARAM_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_timing_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_timing_info.h deleted file mode 100644 index ea6780e25c55..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_timing_info.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_TIMING_INFO_H_ -#define _RX_TIMING_INFO_H_ - -#define NUM_OF_DWORDS_RX_TIMING_INFO 5 - -struct rx_timing_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_timestamp_1_lower_32 : 32; - uint32_t phy_timestamp_1_upper_32 : 32; - uint32_t phy_timestamp_2_lower_32 : 32; - uint32_t phy_timestamp_2_upper_32 : 32; - uint32_t residual_phase_offset : 12, - sub_usec_ts_rx_end : 10, - reserved : 10; -#else - uint32_t phy_timestamp_1_lower_32 : 32; - uint32_t phy_timestamp_1_upper_32 : 32; - uint32_t phy_timestamp_2_lower_32 : 32; - uint32_t phy_timestamp_2_upper_32 : 32; - uint32_t reserved : 10, - sub_usec_ts_rx_end : 10, - residual_phase_offset : 12; -#endif -}; - -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000000 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000004 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x00000008 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000c -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000010 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB 0 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB 11 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff - -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_OFFSET 0x00000010 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_LSB 12 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MSB 21 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MASK 0x003ff000 - -#define RX_TIMING_INFO_RESERVED_OFFSET 0x00000010 -#define RX_TIMING_INFO_RESERVED_LSB 22 -#define RX_TIMING_INFO_RESERVED_MSB 31 -#define RX_TIMING_INFO_RESERVED_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_trig_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_trig_info.h deleted file mode 100644 index b6b074118bea..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_trig_info.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_TRIG_INFO_H_ -#define _RX_TRIG_INFO_H_ - -#define NUM_OF_DWORDS_RX_TRIG_INFO 2 - -#define NUM_OF_QWORDS_RX_TRIG_INFO 1 - -struct rx_trig_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_trigger_frame_type : 2, - trigger_resp_type : 3, - reserved_0 : 27; - uint32_t ppdu_duration : 16, - unique_destination_id : 16; -#else - uint32_t reserved_0 : 27, - trigger_resp_type : 3, - rx_trigger_frame_type : 2; - uint32_t unique_destination_id : 16, - ppdu_duration : 16; -#endif -}; - -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003 - -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c - -#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_RESERVED_0_LSB 5 -#define RX_TRIG_INFO_RESERVED_0_MSB 31 -#define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0 - -#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_PPDU_DURATION_LSB 32 -#define RX_TRIG_INFO_PPDU_DURATION_MSB 47 -#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000 - -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_early_rx_indication.h b/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_early_rx_indication.h deleted file mode 100644 index d2dc464cf1cf..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_early_rx_indication.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_EARLY_RX_INDICATION_H_ -#define _RXPCU_EARLY_RX_INDICATION_H_ - -#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2 - -#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1 - -struct rxpcu_early_rx_indication { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5, - dot11ax_received_ext_ru_size : 4, - reserved_0a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 18, - dot11ax_received_ext_ru_size : 4, - rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x000000000000000f - -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x0000000000000010 - -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 9 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x00000000000003e0 - -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 10 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 13 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0000000000003c00 - -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 14 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0x00000000ffffc000 - -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB 32 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB 63 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_info.h deleted file mode 100644 index c97ad08c26a4..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_info.h +++ /dev/null @@ -1,925 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_PPDU_END_INFO_H_ -#define _RXPCU_PPDU_END_INFO_H_ - -#include "phyrx_abort_request_info.h" -#include "macrx_abort_request_info.h" -#include "rxpcu_ppdu_end_layout_info.h" -#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 32 - -#define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 16 - -struct rxpcu_ppdu_end_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t wb_timestamp_lower_32 : 32; - uint32_t wb_timestamp_upper_32 : 32; - uint32_t rx_antenna : 24, - tx_ht_vht_ack : 1, - unsupported_mu_nc : 1, - otp_txbf_disable : 1, - previous_tlv_corrupted : 1, - phyrx_abort_request_info_valid : 1, - macrx_abort_request_info_valid : 1, - coex_wan_tx_from_start_of_rx_ratid1 : 1, - coex_wan_tx_after_start_of_rx_ratid1 : 1; - uint32_t coex_bt_tx_from_start_of_rx : 1, - coex_bt_tx_after_start_of_rx : 1, - coex_wan_tx_from_start_of_rx : 1, - coex_wan_tx_after_start_of_rx : 1, - coex_wlan_tx_from_start_of_rx : 1, - coex_wlan_tx_after_start_of_rx : 1, - mpdu_delimiter_errors_seen : 1, - __reserved_g_0012 : 2, - dialog_token : 8, - follow_up_dialog_token : 8, - bb_captured_channel : 1, - bb_captured_reason : 3, - bb_captured_timeout : 1, - __reserved_g_0054 : 1, - __reserved_g_0058 : 1; - uint32_t before_mpdu_count_passing_fcs : 10, - before_mpdu_count_failing_fcs : 10, - after_mpdu_count_passing_fcs : 10, - reserved_4 : 2; - uint32_t after_mpdu_count_failing_fcs : 10, - reserved_5 : 22; - uint32_t phy_timestamp_tx_lower_32 : 32; - uint32_t phy_timestamp_tx_upper_32 : 32; - uint32_t bb_length : 16, - bb_data : 1, - reserved_8 : 3, - first_bt_broadcast_status_details : 12; - uint32_t rx_ppdu_duration : 24, - reserved_9 : 8; - uint32_t ast_index : 16, - ast_index_valid : 1, - reserved_10 : 3, - second_bt_broadcast_status_details : 12; - struct phyrx_abort_request_info phyrx_abort_request_info_details; - struct macrx_abort_request_info macrx_abort_request_info_details; - uint16_t pre_bt_broadcast_status_details : 12, - reserved_12a : 4; - uint32_t non_qos_sn_info_valid : 1, - rts_or_trig_protected_ppdu : 1, - rts_or_trig_prot_type : 2, - reserved_13a : 2, - non_qos_sn_highest : 12, - non_qos_sn_highest_retry_setting : 1, - non_qos_sn_lowest : 12, - non_qos_sn_lowest_retry_setting : 1; - uint32_t qos_sn_1_info_valid : 1, - reserved_14a : 1, - qos_sn_1_tid : 4, - qos_sn_1_highest : 12, - qos_sn_1_highest_retry_setting : 1, - qos_sn_1_lowest : 12, - qos_sn_1_lowest_retry_setting : 1; - uint32_t qos_sn_2_info_valid : 1, - reserved_15a : 1, - qos_sn_2_tid : 4, - qos_sn_2_highest : 12, - qos_sn_2_highest_retry_setting : 1, - qos_sn_2_lowest : 12, - qos_sn_2_lowest_retry_setting : 1; - struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; - uint32_t corrupted_due_to_fifo_delay : 1, - qos_sn_1_more_frag_state : 1, - qos_sn_1_frag_num_state : 4, - qos_sn_2_more_frag_state : 1, - qos_sn_2_frag_num_state : 4, - rts_or_trig_prot_non_11a : 1, - rts_or_trig_prot_rate_mcs : 4, - rts_or_trig_prot_peer_addr_15_0 : 16; - uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; - uint32_t rts_or_trig_rx_count : 32; - uint32_t cts_or_null_tx_count : 32; - uint32_t coex_tracker2_tx_from_start_of_rx : 1, - coex_tracker2_tx_after_start_of_rx : 1, - coex_tracker3_tx_from_start_of_rx : 1, - coex_tracker3_tx_after_start_of_rx : 1, - coex_tracker4_tx_from_start_of_rx : 1, - coex_tracker4_tx_after_start_of_rx : 1, - coex_tracker5_tx_from_start_of_rx : 1, - coex_tracker5_tx_after_start_of_rx : 1, - coex_tracker6_tx_from_start_of_rx : 1, - coex_tracker6_tx_after_start_of_rx : 1, - reserved_30a : 22; - uint32_t rx_ppdu_end_marker : 32; -#else - uint32_t wb_timestamp_lower_32 : 32; - uint32_t wb_timestamp_upper_32 : 32; - uint32_t coex_wan_tx_after_start_of_rx_ratid1 : 1, - coex_wan_tx_from_start_of_rx_ratid1 : 1, - macrx_abort_request_info_valid : 1, - phyrx_abort_request_info_valid : 1, - previous_tlv_corrupted : 1, - otp_txbf_disable : 1, - unsupported_mu_nc : 1, - tx_ht_vht_ack : 1, - rx_antenna : 24; - uint32_t __reserved_g_0058 : 1, - __reserved_g_0054 : 1, - bb_captured_timeout : 1, - bb_captured_reason : 3, - bb_captured_channel : 1, - follow_up_dialog_token : 8, - dialog_token : 8, - __reserved_g_0012 : 2, - mpdu_delimiter_errors_seen : 1, - coex_wlan_tx_after_start_of_rx : 1, - coex_wlan_tx_from_start_of_rx : 1, - coex_wan_tx_after_start_of_rx : 1, - coex_wan_tx_from_start_of_rx : 1, - coex_bt_tx_after_start_of_rx : 1, - coex_bt_tx_from_start_of_rx : 1; - uint32_t reserved_4 : 2, - after_mpdu_count_passing_fcs : 10, - before_mpdu_count_failing_fcs : 10, - before_mpdu_count_passing_fcs : 10; - uint32_t reserved_5 : 22, - after_mpdu_count_failing_fcs : 10; - uint32_t phy_timestamp_tx_lower_32 : 32; - uint32_t phy_timestamp_tx_upper_32 : 32; - uint32_t first_bt_broadcast_status_details : 12, - reserved_8 : 3, - bb_data : 1, - bb_length : 16; - uint32_t reserved_9 : 8, - rx_ppdu_duration : 24; - uint32_t second_bt_broadcast_status_details : 12, - reserved_10 : 3, - ast_index_valid : 1, - ast_index : 16; - struct phyrx_abort_request_info phyrx_abort_request_info_details; - uint32_t reserved_12a : 4, - pre_bt_broadcast_status_details : 12; - struct macrx_abort_request_info macrx_abort_request_info_details; - uint32_t non_qos_sn_lowest_retry_setting : 1, - non_qos_sn_lowest : 12, - non_qos_sn_highest_retry_setting : 1, - non_qos_sn_highest : 12, - reserved_13a : 2, - rts_or_trig_prot_type : 2, - rts_or_trig_protected_ppdu : 1, - non_qos_sn_info_valid : 1; - uint32_t qos_sn_1_lowest_retry_setting : 1, - qos_sn_1_lowest : 12, - qos_sn_1_highest_retry_setting : 1, - qos_sn_1_highest : 12, - qos_sn_1_tid : 4, - reserved_14a : 1, - qos_sn_1_info_valid : 1; - uint32_t qos_sn_2_lowest_retry_setting : 1, - qos_sn_2_lowest : 12, - qos_sn_2_highest_retry_setting : 1, - qos_sn_2_highest : 12, - qos_sn_2_tid : 4, - reserved_15a : 1, - qos_sn_2_info_valid : 1; - struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; - uint32_t rts_or_trig_prot_peer_addr_15_0 : 16, - rts_or_trig_prot_rate_mcs : 4, - rts_or_trig_prot_non_11a : 1, - qos_sn_2_frag_num_state : 4, - qos_sn_2_more_frag_state : 1, - qos_sn_1_frag_num_state : 4, - qos_sn_1_more_frag_state : 1, - corrupted_due_to_fifo_delay : 1; - uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; - uint32_t rts_or_trig_rx_count : 32; - uint32_t cts_or_null_tx_count : 32; - uint32_t reserved_30a : 22, - coex_tracker6_tx_after_start_of_rx : 1, - coex_tracker6_tx_from_start_of_rx : 1, - coex_tracker5_tx_after_start_of_rx : 1, - coex_tracker5_tx_from_start_of_rx : 1, - coex_tracker4_tx_after_start_of_rx : 1, - coex_tracker4_tx_from_start_of_rx : 1, - coex_tracker3_tx_after_start_of_rx : 1, - coex_tracker3_tx_from_start_of_rx : 1, - coex_tracker2_tx_after_start_of_rx : 1, - coex_tracker2_tx_from_start_of_rx : 1; - uint32_t rx_ppdu_end_marker : 32; -#endif -}; - -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff - -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 - -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 - -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 - -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_LSB 30 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MSB 30 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MASK 0x0000000040000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_LSB 31 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MSB 31 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MASK 0x0000000080000000 - -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 - -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 - -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 - -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 - -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 - -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 - -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff - -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 - -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 - -#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 -#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 - -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 -#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 -#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 - -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff - -#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 -#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 -#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 - -#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 -#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 -#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 - -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 - -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 -#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 -#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 - -#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 -#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 -#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff - -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 - -#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 -#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 -#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 - -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 42 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 42 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x0000040000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB 43 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB 43 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x0000080000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 44 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 44 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x0000100000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB 45 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB 45 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK 0x0000200000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB 46 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB 46 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK 0x0000400000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 47 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000800000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 - -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 - -#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB 33 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB 33 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB 34 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB 35 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK 0x0000000c00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 36 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB 11 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB 11 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK 0x0000000000000800 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB 12 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB 15 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK 0x000000000000f000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB 16 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB 31 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK 0x00000000ffff0000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB 32 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB 63 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET 0x0000000000000070 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB 0 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB 31 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET 0x0000000000000070 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB 32 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB 63 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_LSB 0 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MSB 0 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_LSB 1 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MSB 1 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_LSB 2 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MSB 2 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MASK 0x0000000000000004 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_LSB 3 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MSB 3 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MASK 0x0000000000000008 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_LSB 4 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MSB 4 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MASK 0x0000000000000010 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_LSB 5 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MSB 5 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MASK 0x0000000000000020 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_LSB 6 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MSB 6 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MASK 0x0000000000000040 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_LSB 7 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MSB 7 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MASK 0x0000000000000080 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_LSB 8 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MSB 8 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MASK 0x0000000000000100 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_LSB 9 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MSB 9 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MASK 0x0000000000000200 - -#define RXPCU_PPDU_END_INFO_RESERVED_30A_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_LSB 10 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_MASK 0x00000000fffffc00 - -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h deleted file mode 100644 index 9d54e91522ec..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ -#define _RXPCU_PPDU_END_LAYOUT_INFO_H_ - -#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 - -struct rxpcu_ppdu_end_layout_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rssi_legacy_offset : 2, - l_sig_a_offset : 6, - l_sig_b_offset : 6, - ht_sig_offset : 6, - vht_sig_a_offset : 6, - repeat_l_sig_a_offset : 6; - uint32_t he_sig_a_su_offset : 6, - he_sig_a_mu_dl_offset : 6, - he_sig_a_mu_ul_offset : 6, - generic_u_sig_offset : 6, - rssi_ht_offset : 7, - reserved_1a : 1; - uint32_t vht_sig_b_su20_offset : 7, - vht_sig_b_su40_offset : 7, - vht_sig_b_su80_offset : 7, - vht_sig_b_su160_offset : 7, - reserved_2a : 4; - uint32_t vht_sig_b_mu20_offset : 7, - vht_sig_b_mu40_offset : 7, - vht_sig_b_mu80_offset : 7, - vht_sig_b_mu160_offset : 7, - reserved_3a : 4; - uint32_t he_sig_b1_mu_offset : 7, - he_sig_b2_mu_offset : 7, - he_sig_b2_ofdma_offset : 7, - first_generic_eht_sig_offset : 7, - multiple_generic_eht_sig_included : 1, - reserved_4a : 3; - uint32_t common_user_info_offset : 7, - first_debug_info_offset : 8, - multiple_debug_info_included : 1, - first_other_receive_info_offset : 8, - multiple_other_receive_info_included : 1, - reserved_5a : 7; - uint32_t data_done_offset : 8, - generated_cbf_details_offset : 8, - pkt_end_part1_offset : 8, - location_offset : 8; - uint32_t __reserved_g_0011 : 8, - pkt_end_offset : 8, - abort_request_ack_offset : 8, - reserved_7a : 8; - uint32_t reserved_8a : 32; - uint32_t reserved_9a : 32; -#else - uint32_t repeat_l_sig_a_offset : 6, - vht_sig_a_offset : 6, - ht_sig_offset : 6, - l_sig_b_offset : 6, - l_sig_a_offset : 6, - rssi_legacy_offset : 2; - uint32_t reserved_1a : 1, - rssi_ht_offset : 7, - generic_u_sig_offset : 6, - he_sig_a_mu_ul_offset : 6, - he_sig_a_mu_dl_offset : 6, - he_sig_a_su_offset : 6; - uint32_t reserved_2a : 4, - vht_sig_b_su160_offset : 7, - vht_sig_b_su80_offset : 7, - vht_sig_b_su40_offset : 7, - vht_sig_b_su20_offset : 7; - uint32_t reserved_3a : 4, - vht_sig_b_mu160_offset : 7, - vht_sig_b_mu80_offset : 7, - vht_sig_b_mu40_offset : 7, - vht_sig_b_mu20_offset : 7; - uint32_t reserved_4a : 3, - multiple_generic_eht_sig_included : 1, - first_generic_eht_sig_offset : 7, - he_sig_b2_ofdma_offset : 7, - he_sig_b2_mu_offset : 7, - he_sig_b1_mu_offset : 7; - uint32_t reserved_5a : 7, - multiple_other_receive_info_included : 1, - first_other_receive_info_offset : 8, - multiple_debug_info_included : 1, - first_debug_info_offset : 8, - common_user_info_offset : 7; - uint32_t location_offset : 8, - pkt_end_part1_offset : 8, - generated_cbf_details_offset : 8, - data_done_offset : 8; - uint32_t reserved_7a : 8, - abort_request_ack_offset : 8, - pkt_end_offset : 8, - __reserved_g_0011 : 8; - uint32_t reserved_8a : 32; - uint32_t reserved_9a : 32; -#endif -}; - -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 - -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc - -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff - -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rxpt_classify_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rxpt_classify_info.h deleted file mode 100644 index 7fc572ae2474..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rxpt_classify_info.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPT_CLASSIFY_INFO_H_ -#define _RXPT_CLASSIFY_INFO_H_ - -#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 - -struct rxpt_classify_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reo_destination_indication : 5, - lmac_peer_id_msb : 2, - use_flow_id_toeplitz_clfy : 1, - pkt_selection_fp_ucast_data : 1, - pkt_selection_fp_mcast_data : 1, - pkt_selection_fp_1000 : 1, - rxdma0_source_ring_selection : 3, - rxdma0_destination_ring_selection : 3, - mcast_echo_drop_enable : 1, - wds_learning_detect_en : 1, - intrabss_check_en : 1, - use_ppe : 1, - ppe_routing_enable : 1, - cce_source_sel_en : 1, - reserved_0b : 9; -#else - uint32_t reserved_0b : 9, - cce_source_sel_en : 1, - ppe_routing_enable : 1, - use_ppe : 1, - intrabss_check_en : 1, - wds_learning_detect_en : 1, - mcast_echo_drop_enable : 1, - rxdma0_destination_ring_selection : 3, - rxdma0_source_ring_selection : 3, - pkt_selection_fp_1000 : 1, - pkt_selection_fp_mcast_data : 1, - pkt_selection_fp_ucast_data : 1, - use_flow_id_toeplitz_clfy : 1, - lmac_peer_id_msb : 2, - reo_destination_indication : 5; -#endif -}; - -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060 - -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400 - -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 - -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 - -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 - -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000 - -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000 - -#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20 -#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20 -#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000 - -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000 - -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB 22 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB 22 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK 0x00400000 - -#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 23 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xff800000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/seq_hwio.h b/drivers/staging/fw-api/hw/wcn8750/v1/seq_hwio.h deleted file mode 100644 index 69111d08d535..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/seq_hwio.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef __SEQ_H__ -#define __SEQ_H__ - -#include "HALhwio.h" - -#define SEQ_INH(base, regtype, reg) \ - SEQ_##regtype##_INH(base, reg) - -#define SEQ_INMH(base, regtype, reg, mask) \ - SEQ_##regtype##_INMH(base, reg, mask) - -#define SEQ_INFH(base, regtype, reg, fld) \ - (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) - -#define SEQ_OUTH(base, regtype, reg, val) \ - SEQ_##regtype##_OUTH(base, reg, val) - -#define SEQ_OUTMH(base, regtype, reg, mask, val) \ - SEQ_##regtype##_OUTMH(base, reg, mask, val) - -#define SEQ_OUTFH(base, regtype, reg, fld, val) \ - SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) - -typedef enum { - SEC, - MS, - US, - NS -} SEQ_TimeUnit; - -extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); - -extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); - -#endif - diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tcl_assist_cmd.h b/drivers/staging/fw-api/hw/wcn8750/v1/tcl_assist_cmd.h deleted file mode 100644 index f7a5bd5287cb..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tcl_assist_cmd.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TCL_ASSIST_CMD_H_ -#define _TCL_ASSIST_CMD_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_TCL_ASSIST_CMD 16 - -struct tcl_assist_cmd { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_addr_info; - uint32_t buf_or_ext_desc_type : 1, - bank_id : 6, - vdev_id : 8, - data_length : 14, - to_fw_tqm : 2, - reserved_2a : 1; - uint32_t reserved_3a : 25, - metadata_length : 7; - uint32_t txpt_classify_info_index : 8, - txpt_classify_info_sel : 5, - txpt_classify_info_override : 1, - flow_override_enable : 1, - flow_select : 1, - hlos_tid : 4, - hlos_tid_overwrite : 1, - tos_tc_value : 8, - reserved_4a : 3; - uint32_t reserved_5a : 16, - l3_type : 16; - uint32_t l4_protocol : 8, - l4_port : 16, - l4_port_type : 1, - da_is_bcast_mcast : 1, - da_is_bcast : 1, - reserved_6a : 5; - uint32_t ip_address_31_0 : 32; - uint32_t ip_address_63_32 : 32; - uint32_t ip_address_95_64 : 32; - uint32_t ip_address_127_96 : 32; - uint32_t ip_da_or_sa : 1, - encap_length_change : 6, - encap_length_decrease : 1, - encap_length_override : 1, - type_or_length : 1, - snap_oui_zero_or_f8 : 1, - snap_oui_not_zero_and_not_f8 : 1, - msdu_color : 2, - tx_notify_frame : 3, - tqm_no_drop : 1, - reserved_11a : 12, - l3_checksum_enable : 1, - l4_checksum_enable : 1; - uint32_t buffer_timestamp : 19, - buffer_timestamp_valid : 1, - s_vlan_tag_present : 1, - c_vlan_tag_present : 1, - wmac_hdr_len : 7, - reserved_12a : 3; - uint32_t tcl_cmd_number : 32; - uint32_t reserved_14a : 32; - uint32_t reserved_15a : 20, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_addr_info; - uint32_t reserved_2a : 1, - to_fw_tqm : 2, - data_length : 14, - vdev_id : 8, - bank_id : 6, - buf_or_ext_desc_type : 1; - uint32_t metadata_length : 7, - reserved_3a : 25; - uint32_t reserved_4a : 3, - tos_tc_value : 8, - hlos_tid_overwrite : 1, - hlos_tid : 4, - flow_select : 1, - flow_override_enable : 1, - txpt_classify_info_override : 1, - txpt_classify_info_sel : 5, - txpt_classify_info_index : 8; - uint32_t l3_type : 16, - reserved_5a : 16; - uint32_t reserved_6a : 5, - da_is_bcast : 1, - da_is_bcast_mcast : 1, - l4_port_type : 1, - l4_port : 16, - l4_protocol : 8; - uint32_t ip_address_31_0 : 32; - uint32_t ip_address_63_32 : 32; - uint32_t ip_address_95_64 : 32; - uint32_t ip_address_127_96 : 32; - uint32_t l4_checksum_enable : 1, - l3_checksum_enable : 1, - reserved_11a : 12, - tqm_no_drop : 1, - tx_notify_frame : 3, - msdu_color : 2, - snap_oui_not_zero_and_not_f8 : 1, - snap_oui_zero_or_f8 : 1, - type_or_length : 1, - encap_length_override : 1, - encap_length_decrease : 1, - encap_length_change : 6, - ip_da_or_sa : 1; - uint32_t reserved_12a : 3, - wmac_hdr_len : 7, - c_vlan_tag_present : 1, - s_vlan_tag_present : 1, - buffer_timestamp_valid : 1, - buffer_timestamp : 19; - uint32_t tcl_cmd_number : 32; - uint32_t reserved_14a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_15a : 20; -#endif -}; - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_LSB 0 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MSB 0 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001 - -#define TCL_ASSIST_CMD_BANK_ID_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_BANK_ID_LSB 1 -#define TCL_ASSIST_CMD_BANK_ID_MSB 6 -#define TCL_ASSIST_CMD_BANK_ID_MASK 0x0000007e - -#define TCL_ASSIST_CMD_VDEV_ID_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_VDEV_ID_LSB 7 -#define TCL_ASSIST_CMD_VDEV_ID_MSB 14 -#define TCL_ASSIST_CMD_VDEV_ID_MASK 0x00007f80 - -#define TCL_ASSIST_CMD_DATA_LENGTH_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_DATA_LENGTH_LSB 15 -#define TCL_ASSIST_CMD_DATA_LENGTH_MSB 28 -#define TCL_ASSIST_CMD_DATA_LENGTH_MASK 0x1fff8000 - -#define TCL_ASSIST_CMD_TO_FW_TQM_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_TO_FW_TQM_LSB 29 -#define TCL_ASSIST_CMD_TO_FW_TQM_MSB 30 -#define TCL_ASSIST_CMD_TO_FW_TQM_MASK 0x60000000 - -#define TCL_ASSIST_CMD_RESERVED_2A_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_RESERVED_2A_LSB 31 -#define TCL_ASSIST_CMD_RESERVED_2A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_2A_MASK 0x80000000 - -#define TCL_ASSIST_CMD_RESERVED_3A_OFFSET 0x0000000c -#define TCL_ASSIST_CMD_RESERVED_3A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_3A_MSB 24 -#define TCL_ASSIST_CMD_RESERVED_3A_MASK 0x01ffffff - -#define TCL_ASSIST_CMD_METADATA_LENGTH_OFFSET 0x0000000c -#define TCL_ASSIST_CMD_METADATA_LENGTH_LSB 25 -#define TCL_ASSIST_CMD_METADATA_LENGTH_MSB 31 -#define TCL_ASSIST_CMD_METADATA_LENGTH_MASK 0xfe000000 - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_LSB 0 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MSB 7 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MASK 0x000000ff - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_LSB 8 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MSB 12 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MASK 0x00001f00 - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_LSB 13 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MSB 13 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MASK 0x00002000 - -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_LSB 14 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MSB 14 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00004000 - -#define TCL_ASSIST_CMD_FLOW_SELECT_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_FLOW_SELECT_LSB 15 -#define TCL_ASSIST_CMD_FLOW_SELECT_MSB 15 -#define TCL_ASSIST_CMD_FLOW_SELECT_MASK 0x00008000 - -#define TCL_ASSIST_CMD_HLOS_TID_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_HLOS_TID_LSB 16 -#define TCL_ASSIST_CMD_HLOS_TID_MSB 19 -#define TCL_ASSIST_CMD_HLOS_TID_MASK 0x000f0000 - -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_LSB 20 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MSB 20 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MASK 0x00100000 - -#define TCL_ASSIST_CMD_TOS_TC_VALUE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_LSB 21 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_MSB 28 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_MASK 0x1fe00000 - -#define TCL_ASSIST_CMD_RESERVED_4A_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_RESERVED_4A_LSB 29 -#define TCL_ASSIST_CMD_RESERVED_4A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_4A_MASK 0xe0000000 - -#define TCL_ASSIST_CMD_RESERVED_5A_OFFSET 0x00000014 -#define TCL_ASSIST_CMD_RESERVED_5A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_5A_MSB 15 -#define TCL_ASSIST_CMD_RESERVED_5A_MASK 0x0000ffff - -#define TCL_ASSIST_CMD_L3_TYPE_OFFSET 0x00000014 -#define TCL_ASSIST_CMD_L3_TYPE_LSB 16 -#define TCL_ASSIST_CMD_L3_TYPE_MSB 31 -#define TCL_ASSIST_CMD_L3_TYPE_MASK 0xffff0000 - -#define TCL_ASSIST_CMD_L4_PROTOCOL_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PROTOCOL_LSB 0 -#define TCL_ASSIST_CMD_L4_PROTOCOL_MSB 7 -#define TCL_ASSIST_CMD_L4_PROTOCOL_MASK 0x000000ff - -#define TCL_ASSIST_CMD_L4_PORT_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PORT_LSB 8 -#define TCL_ASSIST_CMD_L4_PORT_MSB 23 -#define TCL_ASSIST_CMD_L4_PORT_MASK 0x00ffff00 - -#define TCL_ASSIST_CMD_L4_PORT_TYPE_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_LSB 24 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_MSB 24 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_MASK 0x01000000 - -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_LSB 25 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MSB 25 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MASK 0x02000000 - -#define TCL_ASSIST_CMD_DA_IS_BCAST_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_DA_IS_BCAST_LSB 26 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MSB 26 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MASK 0x04000000 - -#define TCL_ASSIST_CMD_RESERVED_6A_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_RESERVED_6A_LSB 27 -#define TCL_ASSIST_CMD_RESERVED_6A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_6A_MASK 0xf8000000 - -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_OFFSET 0x0000001c -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_OFFSET 0x00000020 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_OFFSET 0x00000024 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_OFFSET 0x00000028 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_DA_OR_SA_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_IP_DA_OR_SA_LSB 0 -#define TCL_ASSIST_CMD_IP_DA_OR_SA_MSB 0 -#define TCL_ASSIST_CMD_IP_DA_OR_SA_MASK 0x00000001 - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_LSB 1 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MSB 6 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MASK 0x0000007e - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_LSB 7 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MSB 7 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MASK 0x00000080 - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_LSB 8 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MSB 8 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MASK 0x00000100 - -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_LSB 9 -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MSB 9 -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MASK 0x00000200 - -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_LSB 10 -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MSB 10 -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MASK 0x00000400 - -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_LSB 11 -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MSB 11 -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MASK 0x00000800 - -#define TCL_ASSIST_CMD_MSDU_COLOR_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_MSDU_COLOR_LSB 12 -#define TCL_ASSIST_CMD_MSDU_COLOR_MSB 13 -#define TCL_ASSIST_CMD_MSDU_COLOR_MASK 0x00003000 - -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_LSB 14 -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MSB 16 -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MASK 0x0001c000 - -#define TCL_ASSIST_CMD_TQM_NO_DROP_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TQM_NO_DROP_LSB 17 -#define TCL_ASSIST_CMD_TQM_NO_DROP_MSB 17 -#define TCL_ASSIST_CMD_TQM_NO_DROP_MASK 0x00020000 - -#define TCL_ASSIST_CMD_RESERVED_11A_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_RESERVED_11A_LSB 18 -#define TCL_ASSIST_CMD_RESERVED_11A_MSB 29 -#define TCL_ASSIST_CMD_RESERVED_11A_MASK 0x3ffc0000 - -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_LSB 30 -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MSB 30 -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MASK 0x40000000 - -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_LSB 31 -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MSB 31 -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MASK 0x80000000 - -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_LSB 0 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MSB 18 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MASK 0x0007ffff - -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_LSB 19 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MSB 19 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x00080000 - -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_LSB 20 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MSB 20 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MASK 0x00100000 - -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_LSB 21 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MSB 21 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MASK 0x00200000 - -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_LSB 22 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MSB 28 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MASK 0x1fc00000 - -#define TCL_ASSIST_CMD_RESERVED_12A_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_RESERVED_12A_LSB 29 -#define TCL_ASSIST_CMD_RESERVED_12A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_12A_MASK 0xe0000000 - -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_OFFSET 0x00000034 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_LSB 0 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MSB 31 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MASK 0xffffffff - -#define TCL_ASSIST_CMD_RESERVED_14A_OFFSET 0x00000038 -#define TCL_ASSIST_CMD_RESERVED_14A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_14A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_14A_MASK 0xffffffff - -#define TCL_ASSIST_CMD_RESERVED_15A_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_RESERVED_15A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_15A_MSB 19 -#define TCL_ASSIST_CMD_RESERVED_15A_MASK 0x000fffff - -#define TCL_ASSIST_CMD_RING_ID_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_RING_ID_LSB 20 -#define TCL_ASSIST_CMD_RING_ID_MSB 27 -#define TCL_ASSIST_CMD_RING_ID_MASK 0x0ff00000 - -#define TCL_ASSIST_CMD_LOOPING_COUNT_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_LOOPING_COUNT_LSB 28 -#define TCL_ASSIST_CMD_LOOPING_COUNT_MSB 31 -#define TCL_ASSIST_CMD_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tcl_status_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/tcl_status_ring.h deleted file mode 100644 index 5a24217c95d5..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tcl_status_ring.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TCL_STATUS_RING_H_ -#define _TCL_STATUS_RING_H_ - -#define NUM_OF_DWORDS_TCL_STATUS_RING 8 - -struct tcl_status_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t gse_ctrl : 4, - ase_fse_sel : 1, - cache_op_res : 2, - index_search_en : 1, - msdu_cnt_n : 24; - uint32_t msdu_byte_cnt_n : 32; - uint32_t msdu_timestmp_n : 32; - uint32_t cmd_meta_data_31_0 : 32; - uint32_t cmd_meta_data_63_32 : 32; - uint32_t hash_indx_val : 20, - cache_set_num : 4, - reserved_5a : 8; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 20, - ring_id : 8, - looping_count : 4; -#else - uint32_t msdu_cnt_n : 24, - index_search_en : 1, - cache_op_res : 2, - ase_fse_sel : 1, - gse_ctrl : 4; - uint32_t msdu_byte_cnt_n : 32; - uint32_t msdu_timestmp_n : 32; - uint32_t cmd_meta_data_31_0 : 32; - uint32_t cmd_meta_data_63_32 : 32; - uint32_t reserved_5a : 8, - cache_set_num : 4, - hash_indx_val : 20; - uint32_t reserved_6a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_7a : 20; -#endif -}; - -#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 -#define TCL_STATUS_RING_GSE_CTRL_LSB 0 -#define TCL_STATUS_RING_GSE_CTRL_MSB 3 -#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f - -#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 -#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 -#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 -#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 - -#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 -#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 -#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 -#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 - -#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 - -#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 -#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 -#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 -#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 - -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff - -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff - -#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c -#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 -#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 -#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff - -#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff - -#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 -#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 -#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 -#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff - -#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 -#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 -#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 -#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 - -#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 -#define TCL_STATUS_RING_RESERVED_5A_LSB 24 -#define TCL_STATUS_RING_RESERVED_5A_MSB 31 -#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 - -#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 -#define TCL_STATUS_RING_RESERVED_6A_LSB 0 -#define TCL_STATUS_RING_RESERVED_6A_MSB 31 -#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff - -#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c -#define TCL_STATUS_RING_RESERVED_7A_LSB 0 -#define TCL_STATUS_RING_RESERVED_7A_MSB 19 -#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff - -#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c -#define TCL_STATUS_RING_RING_ID_LSB 20 -#define TCL_STATUS_RING_RING_ID_MSB 27 -#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 - -#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 -#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 -#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tlv_hdr.h b/drivers/staging/fw-api/hw/wcn8750/v1/tlv_hdr.h deleted file mode 100644 index a2defe7be508..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tlv_hdr.h +++ /dev/null @@ -1,634 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TLV_HDR_H_ -#define _TLV_HDR_H_ - -#define _TLV_USERID_WIDTH_ 6 - -#define _TLV_MRV_EN_LEN_WIDTH_ 9 -#define _TLV_MRV_DIS_LEN_WIDTH_ 12 - -#define _TLV_DATA_WIDTH_ 32 -#define _TLV_64_DATA_WIDTH_ 64 -#define _TLV_CDATA_WIDTH_ 32 -#define _TLV_77_DATA_WIDTH_ 77 -#define _TLV_CDATA_77_WIDTH_ 64 - -#define _TLV_TAG_WIDTH_ 10 -#define _TLV_CTAG_WIDTH_ 6 - -struct tlv_mlo_usr_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mlo_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_32_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_32_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : 6; -#else - uint32_t tlv_reserved : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_64_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_64_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_c_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata_lower_52 : 52; - uint64_t tlv_cdata_upper_12 : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - tlv_cdata_upper_12 : 12; - uint64_t tlv_cdata_lower_52 : 52, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_; -#endif -}; - -struct tlv_mlo_usr_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mlo_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_reserved : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mac_usr_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mac_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_reserved : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_usr_c_77_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata_lower_20 : 20; - uint32_t tlv_cdata_middle_32 : 32; - uint32_t tlv_cdata_upper_12 : 12, - tlv_compression : 1, - pad_77to96_bit : 19; - uint32_t pad_96to128_bit : 32; -#else - uint32_t tlv_cdata_lower_20 : 20, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_; - uint32_t tlv_cdata_middle_32 : 32; - uint32_t pad_77to96_bit : 20, - tlv_compression : 1, - tlv_cdata_upper_12 : 12; - uint32_t pad_96to128_bit : 32; -#endif -}; - -struct tlv_usr_32_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_reserved : 32; -#else - uint64_t tlv_reserved : 32, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_32_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : 6, - pad_32to64_bit : 32; -#else - uint64_t pad_32to64_bit : 32, - tlv_reserved : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_77_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint32_t pad_64to75_bit : 12, - tlv_compression : 1, - pad_77to95_bit : 19; -#else - uint32_t pad_77to95_bit : 19, - tlv_compression : 1, - pad_64to75_bit : 12; - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_77_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint32_t pad_64to75_bit : 12, - tlv_compression : 1, - pad_77to96_bit : 19; -#else - uint32_t pad_77to96_bit : 19, - tlv_compression : 1, - pad_64to75_bit : 12; - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_c_44_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata : _TLV_CDATA_WIDTH_, - pad_44to64_bit : 20; -#else - uint64_t tlv_cdata_lower_20 : 20, - pad_44to64_bit : 20, - tlv_cdata_upper_12 : 12; - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_, -#endif -}; - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tlv_tag_def.h b/drivers/staging/fw-api/hw/wcn8750/v1/tlv_tag_def.h deleted file mode 100644 index 8189c6ec5601..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tlv_tag_def.h +++ /dev/null @@ -1,1976 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TLV_TAG_DEF_ -#define _TLV_TAG_DEF_ - -typedef enum tlv_tag_def { - WIFIMACTX_CBF_START_E = 0 , - WIFIPHYRX_DATA_E = 1 , - WIFIPHYRX_CBF_DATA_RESP_E = 2 , - WIFIPHYRX_ABORT_REQUEST_E = 3 , - WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , - WIFIMACTX_DATA_RESP_E = 5 , - WIFIMACTX_CBF_DATA_E = 6 , - WIFIMACTX_CBF_DONE_E = 7 , - WIFIPHYRX_LMR_DATA_RESP_E = 8 , - WIFIRXPCU_TO_UCODE_START_E = 9 , - WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , - WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , - WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 , - WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , - WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , - WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , - WIFIRXPCU_TO_UCODE_END_E = 16 , - WIFIPHYRX_RSSI_LEGACY_20MHZ_E = 17 , - WIFIPHYRX_NC_ABORT_REQUEST_E = 18 , - WIFIPHYRX_PKT_END_20MHZ_E = 19 , - WIFIPHYRX_NC_DATA_E = 20 , - WIFIMACRX_CBF_READ_REQUEST_E = 64 , - WIFIMACRX_CBF_DATA_REQUEST_E = 65 , - WIFIMACRX_EXPECT_NDP_RECEPTION_E = 66 , - WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 67 , - WIFIMACRX_NDP_TIMEOUT_E = 68 , - WIFIMACRX_ABORT_ACK_E = 69 , - WIFIMACRX_REQ_IMPLICIT_FB_E = 70 , - WIFIMACRX_CHAIN_MASK_E = 71 , - WIFIMACRX_NAP_USER_E = 72 , - WIFIMACRX_ABORT_REQUEST_E = 73 , - WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 74 , - WIFIPHYTX_ABORT_ACK_E = 75 , - WIFIPHYTX_ABORT_REQUEST_E = 76 , - WIFIPHYTX_PKT_END_E = 77 , - WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 78 , - WIFIPHYTX_REQUEST_CTRL_INFO_E = 79 , - WIFIPHYTX_DATA_REQUEST_E = 80 , - WIFIPHYTX_BF_CV_LOADING_DONE_E = 81 , - WIFIPHYTX_NAP_ACK_E = 82 , - WIFIPHYTX_NAP_DONE_E = 83 , - WIFIPHYTX_OFF_ACK_E = 84 , - WIFIPHYTX_ON_ACK_E = 85 , - WIFIPHYTX_SYNTH_OFF_ACK_E = 86 , - WIFIPHYTX_DEBUG16_E = 87 , - WIFIMACTX_ABORT_REQUEST_E = 88 , - WIFIMACTX_ABORT_ACK_E = 89 , - WIFIMACTX_PKT_END_E = 90 , - WIFIMACTX_PRE_PHY_DESC_E = 91 , - WIFIMACTX_BF_PARAMS_COMMON_E = 92 , - WIFIMACTX_BF_PARAMS_PER_USER_E = 93 , - WIFIMACTX_PREFETCH_CV_E = 94 , - WIFIMACTX_USER_DESC_COMMON_E = 95 , - WIFIMACTX_USER_DESC_PER_USER_E = 96 , - WIFIEXAMPLE_USER_TLV_16_E = 97 , - WIFIEXAMPLE_TLV_16_E = 98 , - WIFIMACTX_PHY_OFF_E = 99 , - WIFIMACTX_PHY_ON_E = 100 , - WIFIMACTX_SYNTH_OFF_E = 101 , - WIFIMACTX_EXPECT_CBF_COMMON_E = 102 , - WIFIMACTX_EXPECT_CBF_PER_USER_E = 103 , - WIFIMACTX_PHY_DESC_E = 104 , - WIFIMACTX_L_SIG_A_E = 105 , - WIFIMACTX_L_SIG_B_E = 106 , - WIFIMACTX_HT_SIG_E = 107 , - WIFIMACTX_VHT_SIG_A_E = 108 , - WIFIMACTX_VHT_SIG_B_SU20_E = 109 , - WIFIMACTX_VHT_SIG_B_SU40_E = 110 , - WIFIMACTX_VHT_SIG_B_SU80_E = 111 , - WIFIMACTX_VHT_SIG_B_SU160_E = 112 , - WIFIMACTX_VHT_SIG_B_MU20_E = 113 , - WIFIMACTX_VHT_SIG_B_MU40_E = 114 , - WIFIMACTX_VHT_SIG_B_MU80_E = 115 , - WIFIMACTX_VHT_SIG_B_MU160_E = 116 , - WIFIMACTX_SERVICE_E = 117 , - WIFIMACTX_HE_SIG_A_SU_E = 118 , - WIFIMACTX_HE_SIG_A_MU_DL_E = 119 , - WIFIMACTX_HE_SIG_A_MU_UL_E = 120 , - WIFIMACTX_HE_SIG_B1_MU_E = 121 , - WIFIMACTX_HE_SIG_B2_MU_E = 122 , - WIFIMACTX_HE_SIG_B2_OFDMA_E = 123 , - WIFIMACTX_DELETE_CV_E = 124 , - WIFIMACTX_MU_UPLINK_COMMON_E = 125 , - WIFIMACTX_MU_UPLINK_USER_SETUP_E = 126 , - WIFIMACTX_OTHER_TRANSMIT_INFO_E = 127 , - WIFIMACTX_PHY_NAP_E = 128 , - WIFIMACTX_DEBUG_E = 129 , - WIFIPHYRX_ABORT_ACK_E = 130 , - WIFIPHYRX_GENERATED_CBF_DETAILS_E = 131 , - WIFIPHYRX_RSSI_LEGACY_E = 132 , - WIFIPHYRX_RSSI_HT_E = 133 , - WIFIPHYRX_USER_INFO_E = 134 , - WIFIPHYRX_PKT_END_E = 135 , - WIFIPHYRX_DEBUG_E = 136 , - WIFIPHYRX_CBF_TRANSFER_DONE_E = 137 , - WIFIPHYRX_CBF_TRANSFER_ABORT_E = 138 , - WIFIPHYRX_L_SIG_A_E = 139 , - WIFIPHYRX_L_SIG_B_E = 140 , - WIFIPHYRX_HT_SIG_E = 141 , - WIFIPHYRX_VHT_SIG_A_E = 142 , - WIFIPHYRX_VHT_SIG_B_SU20_E = 143 , - WIFIPHYRX_VHT_SIG_B_SU40_E = 144 , - WIFIPHYRX_VHT_SIG_B_SU80_E = 145 , - WIFIPHYRX_VHT_SIG_B_SU160_E = 146 , - WIFIPHYRX_VHT_SIG_B_MU20_E = 147 , - WIFIPHYRX_VHT_SIG_B_MU40_E = 148 , - WIFIPHYRX_VHT_SIG_B_MU80_E = 149 , - WIFIPHYRX_VHT_SIG_B_MU160_E = 150 , - WIFIPHYRX_HE_SIG_A_SU_E = 151 , - WIFIPHYRX_HE_SIG_A_MU_DL_E = 152 , - WIFIPHYRX_HE_SIG_A_MU_UL_E = 153 , - WIFIPHYRX_HE_SIG_B1_MU_E = 154 , - WIFIPHYRX_HE_SIG_B2_MU_E = 155 , - WIFIPHYRX_HE_SIG_B2_OFDMA_E = 156 , - WIFIPHYRX_OTHER_RECEIVE_INFO_E = 157 , - WIFIPHYRX_COMMON_USER_INFO_E = 158 , - WIFIPHYRX_DATA_DONE_E = 159 , - WIFICOEX_TX_REQ_E = 160 , - WIFIDUMMY_E = 161 , - WIFIEXAMPLE_TLV_32_NAME_E = 162 , - WIFIMPDU_LIMIT_E = 163 , - WIFINA_LENGTH_END_E = 164 , - WIFIOLE_BUF_STATUS_E = 165 , - WIFIPCU_PPDU_SETUP_DONE_E = 166 , - WIFIPCU_PPDU_SETUP_END_E = 167 , - WIFIPCU_PPDU_SETUP_INIT_E = 168 , - WIFIPCU_PPDU_SETUP_START_E = 169 , - WIFIPDG_FES_SETUP_E = 170 , - WIFIPDG_RESPONSE_E = 171 , - WIFIPDG_TX_REQ_E = 172 , - WIFISCH_WAIT_INSTR_E = 173 , - WIFIMACTX_SWITCH_TO_MAIN_E = 174 , - WIFIPHYTX_LINK_STATE_E = 175 , - WIFIAUX_PPDU_END_E = 176 , - WIFITQM_GEN_MPDU_LENGTH_LIST_E = 177 , - WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 178 , - WIFITQM_GEN_MPDUS_E = 179 , - WIFITQM_GEN_MPDUS_STATUS_E = 180 , - WIFITQM_REMOVE_MPDU_E = 181 , - WIFITQM_REMOVE_MPDU_STATUS_E = 182 , - WIFITQM_REMOVE_MSDU_E = 183 , - WIFITQM_REMOVE_MSDU_STATUS_E = 184 , - WIFITQM_UPDATE_TX_MPDU_COUNT_E = 185 , - WIFITQM_WRITE_CMD_E = 186 , - WIFIOFDMA_TRIGGER_DETAILS_E = 187 , - WIFITX_DATA_E = 188 , - WIFITX_FES_SETUP_E = 189 , - WIFIRX_PACKET_E = 190 , - WIFIEXPECTED_RESPONSE_E = 191 , - WIFITX_MPDU_END_E = 192 , - WIFITX_MPDU_START_E = 193 , - WIFITX_MSDU_END_E = 194 , - WIFITX_MSDU_START_E = 195 , - WIFITX_SW_MODE_SETUP_E = 196 , - WIFITXPCU_BUFFER_STATUS_E = 197 , - WIFITXPCU_USER_BUFFER_STATUS_E = 198 , - WIFIDATA_TO_TIME_CONFIG_E = 199 , - WIFIEXAMPLE_USER_TLV_32_E = 200 , - WIFIMPDU_INFO_E = 201 , - WIFIPDG_USER_SETUP_E = 202 , - WIFITX_11AH_SETUP_E = 203 , - WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 204 , - WIFITX_PEER_ENTRY_E = 205 , - WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 206 , - WIFIEXAMPLE_USER_TLV_44_E = 207 , - WIFITX_FLUSH_E = 208 , - WIFITX_FLUSH_REQ_E = 209 , - WIFITQM_WRITE_CMD_STATUS_E = 210 , - WIFITQM_GET_MPDU_QUEUE_STATS_E = 211 , - WIFITQM_GET_MSDU_FLOW_STATS_E = 212 , - WIFIEXAMPLE_USER_CTLV_44_E = 213 , - WIFITX_FES_STATUS_START_E = 214 , - WIFITX_FES_STATUS_USER_PPDU_E = 215 , - WIFITX_FES_STATUS_USER_RESPONSE_E = 216 , - WIFITX_FES_STATUS_END_E = 217 , - WIFIRX_TRIG_INFO_E = 218 , - WIFIRXPCU_TX_SETUP_CLEAR_E = 219 , - WIFIRX_FRAME_BITMAP_REQ_E = 220 , - WIFIRX_FRAME_BITMAP_ACK_E = 221 , - WIFICOEX_RX_STATUS_E = 222 , - WIFIRX_START_PARAM_E = 223 , - WIFIRX_PPDU_START_E = 224 , - WIFIRX_PPDU_END_E = 225 , - WIFIRX_MPDU_START_E = 226 , - WIFIRX_MPDU_END_E = 227 , - WIFIRX_MSDU_START_E = 228 , - WIFIRX_MSDU_END_E = 229 , - WIFIRX_ATTENTION_E = 230 , - WIFIRECEIVED_RESPONSE_INFO_E = 231 , - WIFIRX_PHY_SLEEP_E = 232 , - WIFIRX_HEADER_E = 233 , - WIFIRX_PEER_ENTRY_E = 234 , - WIFIRX_FLUSH_E = 235 , - WIFIRX_RESPONSE_REQUIRED_INFO_E = 236 , - WIFIRX_FRAMELESS_BAR_DETAILS_E = 237 , - WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 238 , - WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 239 , - WIFITX_CBF_INFO_E = 240 , - WIFIPCU_PPDU_SETUP_USER_E = 241 , - WIFIRX_MPDU_PCU_START_E = 242 , - WIFIRX_PM_INFO_E = 243 , - WIFIRX_USER_PPDU_END_E = 244 , - WIFIRX_PRE_PPDU_START_E = 245 , - WIFIRX_PREAMBLE_E = 246 , - WIFITX_FES_SETUP_COMPLETE_E = 247 , - WIFITX_LAST_MPDU_FETCHED_E = 248 , - WIFITXDMA_STOP_REQUEST_E = 249 , - WIFIRXPCU_SETUP_E = 250 , - WIFIRXPCU_USER_SETUP_E = 251 , - WIFITX_FES_STATUS_ACK_OR_BA_E = 252 , - WIFITQM_ACKED_MPDU_E = 253 , - WIFICOEX_TX_RESP_E = 254 , - WIFICOEX_TX_STATUS_E = 255 , - WIFIMACTX_COEX_PHY_CTRL_E = 256 , - WIFICOEX_STATUS_BROADCAST_E = 257 , - WIFIRESPONSE_START_STATUS_E = 258 , - WIFIRESPONSE_END_STATUS_E = 259 , - WIFICRYPTO_STATUS_E = 260 , - WIFIRECEIVED_TRIGGER_INFO_E = 261 , - WIFICOEX_TX_STOP_CTRL_E = 262 , - WIFIRX_PPDU_ACK_REPORT_E = 263 , - WIFIRX_PPDU_NO_ACK_REPORT_E = 264 , - WIFISCH_COEX_STATUS_E = 265 , - WIFISCHEDULER_COMMAND_STATUS_E = 266 , - WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 267 , - WIFITX_FES_STATUS_PROT_E = 268 , - WIFITX_FES_STATUS_START_PPDU_E = 269 , - WIFITX_FES_STATUS_START_PROT_E = 270 , - WIFITXPCU_PHYTX_DEBUG32_E = 271 , - WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 272 , - WIFITX_MPDU_COUNT_TRANSFER_END_E = 273 , - WIFIWHO_ANCHOR_OFFSET_E = 274 , - WIFIWHO_ANCHOR_VALUE_E = 275 , - WIFIWHO_CCE_INFO_E = 276 , - WIFIWHO_COMMIT_E = 277 , - WIFIWHO_COMMIT_DONE_E = 278 , - WIFIWHO_FLUSH_E = 279 , - WIFIWHO_L2_LLC_E = 280 , - WIFIWHO_L2_PAYLOAD_E = 281 , - WIFIWHO_L3_CHECKSUM_E = 282 , - WIFIWHO_L3_INFO_E = 283 , - WIFIWHO_L4_CHECKSUM_E = 284 , - WIFIWHO_L4_INFO_E = 285 , - WIFIWHO_MSDU_E = 286 , - WIFIWHO_MSDU_MISC_E = 287 , - WIFIWHO_PACKET_DATA_E = 288 , - WIFIWHO_PACKET_HDR_E = 289 , - WIFIWHO_PPDU_END_E = 290 , - WIFIWHO_PPDU_START_E = 291 , - WIFIWHO_TSO_E = 292 , - WIFIWHO_WMAC_HEADER_PV0_E = 293 , - WIFIWHO_WMAC_HEADER_PV1_E = 294 , - WIFIWHO_WMAC_IV_E = 295 , - WIFIMPDU_INFO_END_E = 296 , - WIFIMPDU_INFO_BITMAP_E = 297 , - WIFITX_QUEUE_EXTENSION_E = 298 , - WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 299 , - WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 300 , - WIFITQM_ACKED_MPDU_STATUS_E = 301 , - WIFITQM_ADD_MSDU_STATUS_E = 302 , - WIFITQM_LIST_GEN_DONE_E = 303 , - WIFIWHO_TERMINATE_E = 304 , - WIFITX_LAST_MPDU_END_E = 305 , - WIFITX_CV_DATA_E = 306 , - WIFIPPDU_TX_END_E = 307 , - WIFIPROT_TX_END_E = 308 , - WIFIMPDU_INFO_GLOBAL_END_E = 309 , - WIFITQM_SCH_INSTR_GLOBAL_END_E = 310 , - WIFIRX_PPDU_END_USER_STATS_E = 311 , - WIFIRX_PPDU_END_USER_STATS_EXT_E = 312 , - WIFIREO_GET_QUEUE_STATS_E = 313 , - WIFIREO_FLUSH_QUEUE_E = 314 , - WIFIREO_FLUSH_CACHE_E = 315 , - WIFIREO_UNBLOCK_CACHE_E = 316 , - WIFIREO_GET_QUEUE_STATS_STATUS_E = 317 , - WIFIREO_FLUSH_QUEUE_STATUS_E = 318 , - WIFIREO_FLUSH_CACHE_STATUS_E = 319 , - WIFIREO_UNBLOCK_CACHE_STATUS_E = 320 , - WIFITQM_FLUSH_CACHE_E = 321 , - WIFITQM_UNBLOCK_CACHE_E = 322 , - WIFITQM_FLUSH_CACHE_STATUS_E = 323 , - WIFITQM_UNBLOCK_CACHE_STATUS_E = 324 , - WIFIRX_PPDU_END_STATUS_DONE_E = 325 , - WIFIRX_STATUS_BUFFER_DONE_E = 326 , - WIFISCHEDULER_MLO_SW_MSG_STATUS_E = 327 , - WIFISCHEDULER_TXOP_DURATION_TRIGGER_E = 328 , - WIFITX_DATA_SYNC_E = 329 , - WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 330 , - WIFITQM_GET_MPDU_HEAD_INFO_E = 331 , - WIFITQM_SYNC_CMD_E = 332 , - WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 333 , - WIFITQM_SYNC_CMD_STATUS_E = 334 , - WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 335 , - WIFITCC_TQM_WRAPPER_CMD_E = 336 , - WIFIREO_FLUSH_TIMEOUT_LIST_E = 337 , - WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 338 , - WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 339 , - WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 340 , - WIFIEXAMPLE_USER_TLV_32_NAME_E = 341 , - WIFIRX_PPDU_START_USER_INFO_E = 342 , - WIFIRX_RING_MASK_E = 343 , - WIFICOEX_MAC_NAP_E = 344 , - WIFIRXPCU_PPDU_END_INFO_E = 345 , - WIFIWHO_MESH_CONTROL_E = 346 , - WIFIPDG_SW_MODE_BW_START_E = 347 , - WIFIPDG_SW_MODE_BW_END_E = 348 , - WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 349 , - WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 350 , - WIFISCHEDULER_END_E = 351 , - WIFIRX_PPDU_START_DROPPED_E = 352 , - WIFIRX_PPDU_END_DROPPED_E = 353 , - WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 354 , - WIFIRX_MPDU_START_DROPPED_E = 355 , - WIFIRX_MSDU_START_DROPPED_E = 356 , - WIFIRX_MSDU_END_DROPPED_E = 357 , - WIFIRX_MPDU_END_DROPPED_E = 358 , - WIFIRX_ATTENTION_DROPPED_E = 359 , - WIFITXPCU_USER_SETUP_E = 360 , - WIFIRXPCU_USER_SETUP_EXT_E = 361 , - WIFICMD_PART_0_END_E = 362 , - WIFIMACTX_SYNTH_ON_E = 363 , - WIFISCH_CRITICAL_TLV_REFERENCE_E = 364 , - WIFITQM_MPDU_GLOBAL_START_E = 365 , - WIFIEXAMPLE_TLV_32_E = 366 , - WIFITQM_UPDATE_TX_MSDU_FLOW_E = 367 , - WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 368 , - WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 369 , - WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 370 , - WIFIREO_UPDATE_RX_REO_QUEUE_E = 371 , - WIFITQM_2_SCH_MPDU_AVAILABLE_E = 372 , - WIFIPDG_TRIG_RESPONSE_E = 373 , - WIFITRIGGER_RESPONSE_TX_DONE_E = 374 , - WIFIABORT_FROM_PHYRX_DETAILS_E = 375 , - WIFISCH_TQM_CMD_WRAPPER_E = 376 , - WIFIMPDUS_AVAILABLE_E = 377 , - WIFIRECEIVED_RESPONSE_INFO_PART2_E = 378 , - WIFIPHYRX_TX_START_TIMING_E = 379 , - WIFITXPCU_PREAMBLE_DONE_E = 380 , - WIFINDP_PREAMBLE_DONE_E = 381 , - WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 382 , - WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 383 , - WIFIMACTX_CLEAR_PREV_TX_INFO_E = 384 , - WIFITX_PUNCTURE_SETUP_E = 385 , - WIFIR2R_STATUS_END_E = 386 , - WIFIMACTX_PREFETCH_CV_COMMON_E = 387 , - WIFIEND_OF_FLUSH_MARKER_E = 388 , - WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 389 , - WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 390 , - WIFIRECEIVED_RESPONSE_USER_7_0_E = 391 , - WIFIRECEIVED_RESPONSE_USER_15_8_E = 392 , - WIFIRECEIVED_RESPONSE_USER_23_16_E = 393 , - WIFIRECEIVED_RESPONSE_USER_31_24_E = 394 , - WIFIRECEIVED_RESPONSE_USER_36_32_E = 395 , - WIFITX_LOOPBACK_SETUP_E = 396 , - WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 397 , - WIFISCH_WAIT_INSTR_TX_PATH_E = 398 , - WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 399 , - WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 400 , - WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 401 , - WIFITX_WUR_DATA_E = 402 , - WIFIRX_PPDU_END_START_E = 403 , - WIFIRX_PPDU_END_MIDDLE_E = 404 , - WIFIRX_PPDU_END_LAST_E = 405 , - WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 406 , - WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 407 , - WIFISRP_INFO_E = 408 , - WIFIOBSS_SR_INFO_E = 409 , - WIFISCHEDULER_SW_MSG_STATUS_E = 410 , - WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 411 , - WIFIRXPCU_SETUP_COMPLETE_E = 412 , - WIFIMACTX_MCC_SWITCH_E = 413 , - WIFIMACTX_MCC_SWITCH_BACK_E = 414 , - WIFIPHYTX_MCC_SWITCH_ACK_E = 415 , - WIFIPHYTX_MCC_SWITCH_BACK_ACK_E = 416 , - WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E = 417 , - WIFILMR_TX_END_E = 418 , - WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 419 , - WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 420 , - WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 421 , - WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 422 , - WIFISCH_TLV_WRAPPER_E = 423 , - WIFISCHEDULER_STATUS_WRAPPER_E = 424 , - WIFIMPDU_INFO_6X_E = 425 , - WIFIMACTX___RESERVED_G_0013 = 426 , - WIFIMACTX_U_SIG_EHT_SU_MU_E = 427 , - WIFIMACTX_U_SIG_EHT_TB_E = 428 , - WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E = 429 , - WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E = 430 , - WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E = 431 , - WIFIPHYRX_U_SIG_EHT_SU_MU_E = 432 , - WIFIPHYRX_U_SIG_EHT_TB_E = 433 , - WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E = 434 , - WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 435 , - WIFITX_PUNCTURE_6PATTERNS_SETUP_E = 436 , - WIFIMACRX_LMR_READ_REQUEST_E = 437 , - WIFIMACRX_LMR_DATA_REQUEST_E = 438 , - WIFIPHYRX_LMR_TRANSFER_DONE_E = 439 , - WIFIPHYRX_LMR_TRANSFER_ABORT_E = 440 , - WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 441 , - WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 442 , - WIFIPHYRX_USER_INFO_MU_UL_E = 443 , - WIFIMPDU_QUEUE_OVERVIEW_E = 444 , - WIFISCHEDULER_NAV_INFO_E = 445 , - WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 446 , - WIFILMR_PEER_ENTRY_E = 447 , - WIFILMR_MPDU_START_E = 448 , - WIFILMR_DATA_E = 449 , - WIFILMR_MPDU_END_E = 450 , - WIFIREO_GET_QUEUE_1K_STATS_STATUS_E = 451 , - WIFIRX_FRAME_1K_BITMAP_ACK_E = 452 , - WIFITX_FES_STATUS_1K_BA_E = 453 , - WIFITQM_ACKED_1K_MPDU_E = 454 , - WIFIMACRX_INBSS_OBSS_IND_E = 455 , - WIFIPHYRX_LOCATION_E = 456 , - WIFIMLO_TX_NOTIFICATION_SU_E = 457 , - WIFIMLO_TX_NOTIFICATION_MU_E = 458 , - WIFIMLO_TX_REQ_SU_E = 459 , - WIFIMLO_TX_REQ_MU_E = 460 , - WIFIMLO_TX_RESP_E = 461 , - WIFIMLO_RX_NOTIFICATION_E = 462 , - WIFIMLO_BKOFF_TRUNC_REQ_E = 463 , - WIFIMLO_TBTT_NOTIFICATION_E = 464 , - WIFIMLO_MESSAGE_E = 465 , - WIFIMLO_TS_SYNC_MSG_E = 466 , - WIFIMLO_FES_SETUP_E = 467 , - WIFIMLO_PDG_FES_SETUP_SU_E = 468 , - WIFIMLO_PDG_FES_SETUP_MU_E = 469 , - WIFIMPDU_INFO_1K_BITMAP_E = 470 , - WIFIMON_BUFFER_ADDR_E = 471 , - WIFITX_FRAG_STATE_E = 472 , - WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 473 , - WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 474 , - WIFIMACTX_EHT_SIG_USR_OFDMA_E = 475 , - WIFIMACTX_U_SIG_UHR_SU_MU_E = 476 , - WIFIMACTX_U_SIG_UHR_TB_E = 477 , - WIFITX_MPDU_COMPRESSED_DETAILS_TLV_E = 478 , - WIFITX_MSDU_COMPRESSED_DETAILS_TLV_E = 479 , - WIFITX_MSDU_COMPONENT_DETAILS_TLV_E = 480 , - WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 481 , - WIFISCHEDULER_IU_TEMPLATE_ID_E = 482 , - WIFIPHYRX_PKT_END_PART1_E = 483 , - WIFIMACTX_EXPECT_NDP_RECEPTION_E = 484 , - WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 485 , - WIFITX_MPDU_LENGTH_AND_RESTRICTIONS_E = 486 , - WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 487 , - WIFIPHYRX___RESERVED_G_0014 = 488 , - WIFIPHYTX_LOCATION_E = 489 , - WIFIPHYTX___RESERVED_G_0014 = 490 , - WIFIMPDU_LENGTH_STRUCTS_START_E = 491 , - WIFIMACTX_EHT_SIG_USR_SU_E = 492 , - WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 493 , - WIFIPHYRX_EHT_SIG_USR_SU_E = 494 , - WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 495 , - WIFIPHYRX_GENERIC_U_SIG_E = 496 , - WIFIPHYRX_GENERIC_EHT_OR_UHR_SIG_E = 497 , - WIFIOVERWRITE_RESP_START_E = 498 , - WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 499 , - WIFIOVERWRITE_RESP_FRAME_INFO_E = 500 , - WIFIOVERWRITE_RESP_END_E = 501 , - WIFIRXPCU_EARLY_RX_INDICATION_E = 502 , - WIFIMON_DROP_E = 503 , - WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 504 , - WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 505 , - WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 506 , - WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 507 , - WIFIMACTX_PREFETCH_CV_DMA_E = 508 , - WIFIMACTX_PREFETCH_CV_PER_USER_E = 509 , - WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 510 , - WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 511 , - WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 512 , - WIFIRANGING_USER_DETAILS_E = 513 , - WIFIPHYTX_CV_CORR_STATUS_E = 514 , - WIFIPHYTX_CV_CORR_COMMON_E = 515 , - WIFIPHYTX_CV_CORR_USER_E = 516 , - WIFIMACTX_CV_CORR_COMMON_E = 517 , - WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 518 , - WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 519 , - WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 520 , - WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 521 , - WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 522 , - WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 523 , - WIFIRX_PPDU_END_USER_STATS_EXT2_E = 524 , - WIFIFW2SW_MON_E = 525 , - WIFIWSI_DIRECT_MESSAGE_E = 526 , - WIFIMACTX_EMLSR_PRE_SWITCH_E = 527 , - WIFIMACTX_EMLSR_SWITCH_E = 528 , - WIFIMACTX_EMLSR_SWITCH_BACK_E = 529 , - WIFIPHYTX_EMLSR_SWITCH_ACK_E = 530 , - WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 531 , - WIFIEAD_COMMAND_E = 532 , - WIFIEAD_LEGACY_STATUS_CONTROL_E = 533 , - WIFIEAD_LEGACY_INTERRUPT_CONTROL_E = 534 , - WIFITPI_TX_INITIALIZATION_CONFIG_E = 535 , - WIFITPI_ENABLE_RESPONSE_TIMEOUT_E = 536 , - WIFITPI_LEGACY_STATUS_CONTROL_E = 537 , - WIFITPI_LEGACY_INTERRUPT_CONTROL_E = 538 , - WIFITPI_MPDU_START_E = 539 , - WIFITPI_MPDU_CONTINUATION_E = 540 , - WIFITPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E = 541 , - WIFITPI_SEND_TLV_TO_PHYTX_E = 542 , - WIFITPI_TX_START_TIME_ARRIVED_E = 543 , - WIFITPI_STATUS_E = 544 , - WIFITPI_ERROR_STATUS_E = 545 , - WIFITPI_TIMESTAMP_STATUS_E = 546 , - WIFIRPI_SEND_TLV_TO_PHYRX_E = 547 , - WIFIRPI_LEGACY_STATUS_CONTROL_E = 548 , - WIFIRPI_LEGACY_INTERRUPT_CONTROL_E = 549 , - WIFIRPI_STATUS_E = 550 , - WIFIRPI_ERROR_STATUS_E = 551 , - WIFIRPI_TIMESTAMP_STATUS_E = 552 , - WIFIRPI_RX_FRAME_UPDATE_STATUS_E = 553 , - WIFITCC_PUSH_TRANSMIT_COMMAND_E = 554 , - WIFITCC_TLV_FETCH_E = 555 , - WIFITCC_LEGACY_STATUS_CONTROL_E = 556 , - WIFITCC_LEGACY_INTERRUPT_CONTROL_E = 557 , - WIFITCC_STATUS_E = 558 , - WIFITCC_ERROR_STATUS_E = 559 , - WIFITCC_TIMESTAMP_STATUS_E = 560 , - WIFITCC_PRE_BACKOFF_CMD_AVAILABLE_E = 561 , - WIFITCC_SCHEDULER_CMD_E = 562 , - WIFITCC_BURST_CMD_AVAILABLE_E = 563 , - WIFIRPI_NON_DATA_CTLV_44_FROM_PHYRX_E = 564 , - WIFIEAD_RING_AIR_TIME_REFERENCE_E = 565 , - WIFIRPI_FETCH_INFO_FROM_EXT_MEM_E = 566 , - WIFIRPI_WRITE_INFO_TO_EXT_MEM_E = 567 , - WIFIRPI_INIT_CBF_DATA_RESP_ADDR_E = 568 , - WIFIRPI_INIT_LMR_DATA_RESP_ADDR_E = 569 , - WIFITPI_SEND_CBF_DATA_TO_PHYTX_E = 570 , - WIFITPI_SEND_CTLV_44_TO_PHYTX_E = 571 , - WIFITCC_FES_END_MESSAGE_E = 572 , - WIFITPI_TX_FRAME_UPDATE_STATUS_E = 573 , - WIFITPI_DISABLE_RESPONSE_TIMEOUT_E = 574 , - WIFIEAD_MPDU_DATA_FETCH_CONTINUATION_E = 575 , - WIFIEAD_MSDU_STATUS_START_E = 576 , - WIFIEAD_MSDU_STATUS_DETAILS_E = 577 , - WIFIMACTX_UHR_SIG_USR_SU_E = 578 , - WIFIMACTX_UHR_SIG_USR_MU_MIMO_E = 579 , - WIFIMACTX_UHR_SIG_USR_OFDMA_E = 580 , - WIFIMACTX_ELR_SIG_UHR_SU_E = 581 , - WIFICOEX_BLACKOUT_DETAILS_E = 582 , - WIFIPEER_BLACKOUT_DETAILS_E = 583 , - WIFIMACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E = 584 , - WIFIHDR_CTRL_PROT_PEER_ENTRY_E = 585 , - WIFIHDR_CTRL_PROT_MPDU_START_E = 586 , - WIFIHDR_CTRL_PROT_DATA_E = 587 , - WIFIHDR_CTRL_PROT_MPDU_END_E = 588 , - WIFIHDR_CTRL_PROT_MIC_STATUS_E = 589 , - WIFIHDR_CTRL_PROT_PEER_INFO_E = 590 , - WIFIHDR_CTRL_PROT_PEER_ENTRY_DONE_E = 591 , - WIFIMACTX_U_SIG_UHR_ELR_SU_E = 592 , - WIFIMACTX_U_SIG_UHR_COBF_E = 593 , - WIFIMACTX_UHR_SIG_USR_COBF_E = 594 , - WIFISPARE_REUSE_TAG_0_E = 595 , - WIFISPARE_REUSE_TAG_1_E = 596 , - WIFISPARE_REUSE_TAG_2_E = 597 , - WIFISPARE_REUSE_TAG_3_E = 598 , - WIFISPARE_REUSE_TAG_4_E = 599 , - WIFISPARE_REUSE_TAG_5_E = 600 , - WIFISPARE_REUSE_TAG_6_E = 601 , - WIFISPARE_REUSE_TAG_7_E = 602 , - WIFISPARE_REUSE_TAG_8_E = 603 , - WIFISPARE_REUSE_TAG_9_E = 604 , - WIFISPARE_REUSE_TAG_10_E = 605 , - WIFISPARE_REUSE_TAG_11_E = 606 , - WIFISPARE_REUSE_TAG_12_E = 607 , - WIFISPARE_REUSE_TAG_13_E = 608 , - WIFISPARE_REUSE_TAG_14_E = 609 , - WIFISPARE_REUSE_TAG_15_E = 610 , - WIFISPARE_REUSE_TAG_16_E = 611 , - WIFISPARE_REUSE_TAG_17_E = 612 , - WIFISPARE_REUSE_TAG_18_E = 613 , - WIFISPARE_REUSE_TAG_19_E = 614 , - WIFISPARE_REUSE_TAG_20_E = 615 , - WIFISPARE_REUSE_TAG_21_E = 616 , - WIFISPARE_REUSE_TAG_22_E = 617 , - WIFISPARE_REUSE_TAG_23_E = 618 , - WIFISPARE_REUSE_TAG_24_E = 619 , - WIFISPARE_REUSE_TAG_25_E = 620 , - WIFISPARE_REUSE_TAG_26_E = 621 , - WIFISPARE_REUSE_TAG_27_E = 622 , - WIFISPARE_REUSE_TAG_28_E = 623 , - WIFISPARE_REUSE_TAG_29_E = 624 , - WIFISPARE_REUSE_TAG_30_E = 625 , - WIFISPARE_REUSE_TAG_31_E = 626 , - WIFISPARE_REUSE_TAG_32_E = 627 , - WIFISPARE_REUSE_TAG_33_E = 628 , - WIFISPARE_REUSE_TAG_34_E = 629 , - WIFISPARE_REUSE_TAG_35_E = 630 , - WIFISPARE_REUSE_TAG_36_E = 631 , - WIFISPARE_REUSE_TAG_37_E = 632 , - WIFISPARE_REUSE_TAG_38_E = 633 , - WIFISPARE_REUSE_TAG_39_E = 634 , - WIFISPARE_REUSE_TAG_40_E = 635 , - WIFISPARE_REUSE_TAG_41_E = 636 , - WIFISPARE_REUSE_TAG_42_E = 637 , - WIFISPARE_REUSE_TAG_43_E = 638 , - WIFISPARE_REUSE_TAG_44_E = 639 , - WIFISPARE_REUSE_TAG_45_E = 640 , - WIFISPARE_REUSE_TAG_46_E = 641 , - WIFISPARE_REUSE_TAG_47_E = 642 , - WIFISPARE_REUSE_TAG_48_E = 643 , - WIFISPARE_REUSE_TAG_49_E = 644 , - WIFISPARE_REUSE_TAG_50_E = 645 , - WIFISPARE_REUSE_TAG_51_E = 646 , - WIFISPARE_REUSE_TAG_52_E = 647 , - WIFISPARE_REUSE_TAG_53_E = 648 , - WIFISPARE_REUSE_TAG_54_E = 649 , - WIFISPARE_REUSE_TAG_55_E = 650 , - WIFISPARE_REUSE_TAG_56_E = 651 , - WIFISPARE_REUSE_TAG_57_E = 652 , - WIFISPARE_REUSE_TAG_58_E = 653 , - WIFISPARE_REUSE_TAG_59_E = 654 , - WIFISPARE_REUSE_TAG_60_E = 655 , - WIFISPARE_REUSE_TAG_61_E = 656 , - WIFISPARE_REUSE_TAG_62_E = 657 , - WIFISPARE_REUSE_TAG_63_E = 658 , - WIFISPARE_REUSE_TAG_64_E = 659 , - WIFISPARE_REUSE_TAG_65_E = 660 , - WIFISPARE_REUSE_TAG_66_E = 661 , - WIFISPARE_REUSE_TAG_67_E = 662 , - WIFISPARE_REUSE_TAG_68_E = 663 , - WIFISPARE_REUSE_TAG_69_E = 664 , - WIFISPARE_REUSE_TAG_70_E = 665 , - WIFISPARE_REUSE_TAG_71_E = 666 , - WIFISPARE_REUSE_TAG_72_E = 667 , - WIFISPARE_REUSE_TAG_73_E = 668 , - WIFISPARE_REUSE_TAG_74_E = 669 , - WIFISPARE_REUSE_TAG_75_E = 670 , - WIFISPARE_REUSE_TAG_76_E = 671 , - WIFISPARE_REUSE_TAG_77_E = 672 , - WIFISPARE_REUSE_TAG_78_E = 673 , - WIFISPARE_REUSE_TAG_79_E = 674 , - WIFISPARE_REUSE_TAG_80_E = 675 , - WIFISPARE_REUSE_TAG_81_E = 676 , - WIFISPARE_REUSE_TAG_82_E = 677 , - WIFISPARE_REUSE_TAG_83_E = 678 , - WIFISPARE_REUSE_TAG_84_E = 679 , - WIFISPARE_REUSE_TAG_85_E = 680 , - WIFISPARE_REUSE_TAG_86_E = 681 , - WIFISPARE_REUSE_TAG_87_E = 682 , - WIFISPARE_REUSE_TAG_88_E = 683 , - WIFISPARE_REUSE_TAG_89_E = 684 , - WIFISPARE_REUSE_TAG_90_E = 685 , - WIFISPARE_REUSE_TAG_91_E = 686 , - WIFISPARE_REUSE_TAG_92_E = 687 , - WIFISPARE_REUSE_TAG_93_E = 688 , - WIFISPARE_REUSE_TAG_94_E = 689 , - WIFISPARE_REUSE_TAG_95_E = 690 , - WIFISPARE_REUSE_TAG_96_E = 691 , - WIFISPARE_REUSE_TAG_97_E = 692 , - WIFISPARE_REUSE_TAG_98_E = 693 , - WIFISPARE_REUSE_TAG_99_E = 694 , - WIFISPARE_REUSE_TAG_100_E = 695 , - WIFISPARE_REUSE_TAG_101_E = 696 , - WIFISPARE_REUSE_TAG_102_E = 697 , - WIFISPARE_REUSE_TAG_103_E = 698 , - WIFISPARE_REUSE_TAG_104_E = 699 , - WIFISPARE_REUSE_TAG_105_E = 700 , - WIFISPARE_REUSE_TAG_106_E = 701 , - WIFISPARE_REUSE_TAG_107_E = 702 , - WIFISPARE_REUSE_TAG_108_E = 703 , - WIFISPARE_REUSE_TAG_109_E = 704 , - WIFISPARE_REUSE_TAG_110_E = 705 , - WIFISPARE_REUSE_TAG_111_E = 706 , - WIFISPARE_REUSE_TAG_112_E = 707 , - WIFISPARE_REUSE_TAG_113_E = 708 , - WIFISPARE_REUSE_TAG_114_E = 709 , - WIFISPARE_REUSE_TAG_115_E = 710 , - WIFISPARE_REUSE_TAG_116_E = 711 , - WIFISPARE_REUSE_TAG_117_E = 712 , - WIFISPARE_REUSE_TAG_118_E = 713 , - WIFISPARE_REUSE_TAG_119_E = 714 , - WIFISPARE_REUSE_TAG_120_E = 715 , - WIFISPARE_REUSE_TAG_121_E = 716 , - WIFISPARE_REUSE_TAG_122_E = 717 , - WIFISPARE_REUSE_TAG_123_E = 718 , - WIFISPARE_REUSE_TAG_124_E = 719 , - WIFISPARE_REUSE_TAG_125_E = 720 , - WIFISPARE_REUSE_TAG_126_E = 721 , - WIFISPARE_REUSE_TAG_127_E = 722 , - WIFISPARE_REUSE_TAG_128_E = 723 , - WIFISPARE_REUSE_TAG_129_E = 724 , - WIFISPARE_REUSE_TAG_130_E = 725 , - WIFISPARE_REUSE_TAG_131_E = 726 , - WIFISPARE_REUSE_TAG_132_E = 727 , - WIFISPARE_REUSE_TAG_133_E = 728 , - WIFISPARE_REUSE_TAG_134_E = 729 , - WIFISPARE_REUSE_TAG_135_E = 730 , - WIFISPARE_REUSE_TAG_136_E = 731 , - WIFISPARE_REUSE_TAG_137_E = 732 , - WIFISPARE_REUSE_TAG_138_E = 733 , - WIFISPARE_REUSE_TAG_139_E = 734 , - WIFISPARE_REUSE_TAG_140_E = 735 , - WIFISPARE_REUSE_TAG_141_E = 736 , - WIFISPARE_REUSE_TAG_142_E = 737 , - WIFISPARE_REUSE_TAG_143_E = 738 , - WIFISPARE_REUSE_TAG_144_E = 739 , - WIFISPARE_REUSE_TAG_145_E = 740 , - WIFISPARE_REUSE_TAG_146_E = 741 , - WIFISPARE_REUSE_TAG_147_E = 742 , - WIFISPARE_REUSE_TAG_148_E = 743 , - WIFISPARE_REUSE_TAG_149_E = 744 , - WIFISPARE_REUSE_TAG_150_E = 745 , - WIFISPARE_REUSE_TAG_151_E = 746 , - WIFISPARE_REUSE_TAG_152_E = 747 , - WIFISPARE_REUSE_TAG_153_E = 748 , - WIFISPARE_REUSE_TAG_154_E = 749 , - WIFISPARE_REUSE_TAG_155_E = 750 , - WIFISPARE_REUSE_TAG_156_E = 751 , - WIFISPARE_REUSE_TAG_157_E = 752 , - WIFISPARE_REUSE_TAG_158_E = 753 , - WIFISPARE_REUSE_TAG_159_E = 754 , - WIFISPARE_REUSE_TAG_160_E = 755 , - WIFISPARE_REUSE_TAG_161_E = 756 , - WIFISPARE_REUSE_TAG_162_E = 757 , - WIFISPARE_REUSE_TAG_163_E = 758 , - WIFISPARE_REUSE_TAG_164_E = 759 , - WIFISPARE_REUSE_TAG_165_E = 760 , - WIFISPARE_REUSE_TAG_166_E = 761 , - WIFISPARE_REUSE_TAG_167_E = 762 , - WIFISPARE_REUSE_TAG_168_E = 763 , - WIFISPARE_REUSE_TAG_169_E = 764 , - WIFISPARE_REUSE_TAG_170_E = 765 , - WIFISPARE_REUSE_TAG_171_E = 766 , - WIFISPARE_REUSE_TAG_172_E = 767 , - WIFISPARE_REUSE_TAG_173_E = 768 , - WIFISPARE_REUSE_TAG_174_E = 769 , - WIFISPARE_REUSE_TAG_175_E = 770 , - WIFISPARE_REUSE_TAG_176_E = 771 , - WIFISPARE_REUSE_TAG_177_E = 772 , - WIFISPARE_REUSE_TAG_178_E = 773 , - WIFISPARE_REUSE_TAG_179_E = 774 , - WIFISPARE_REUSE_TAG_180_E = 775 , - WIFISPARE_REUSE_TAG_181_E = 776 , - WIFISPARE_REUSE_TAG_182_E = 777 , - WIFISPARE_REUSE_TAG_183_E = 778 , - WIFISPARE_REUSE_TAG_184_E = 779 , - WIFISPARE_REUSE_TAG_185_E = 780 , - WIFISPARE_REUSE_TAG_186_E = 781 , - WIFISPARE_REUSE_TAG_187_E = 782 , - WIFISPARE_REUSE_TAG_188_E = 783 , - WIFISPARE_REUSE_TAG_189_E = 784 , - WIFISPARE_REUSE_TAG_190_E = 785 , - WIFISPARE_REUSE_TAG_191_E = 786 , - WIFISPARE_REUSE_TAG_192_E = 787 , - WIFISPARE_REUSE_TAG_193_E = 788 , - WIFISPARE_REUSE_TAG_194_E = 789 , - WIFISPARE_REUSE_TAG_195_E = 790 , - WIFISPARE_REUSE_TAG_196_E = 791 , - WIFISPARE_REUSE_TAG_197_E = 792 , - WIFISPARE_REUSE_TAG_198_E = 793 , - WIFISPARE_REUSE_TAG_199_E = 794 , - WIFISPARE_REUSE_TAG_200_E = 795 , - WIFISPARE_REUSE_TAG_201_E = 796 , - WIFISPARE_REUSE_TAG_202_E = 797 , - WIFISPARE_REUSE_TAG_203_E = 798 , - WIFISPARE_REUSE_TAG_204_E = 799 , - WIFISPARE_REUSE_TAG_205_E = 800 , - WIFISPARE_REUSE_TAG_206_E = 801 , - WIFISPARE_REUSE_TAG_207_E = 802 , - WIFISPARE_REUSE_TAG_208_E = 803 , - WIFISPARE_REUSE_TAG_209_E = 804 , - WIFISPARE_REUSE_TAG_210_E = 805 , - WIFISPARE_REUSE_TAG_211_E = 806 , - WIFISPARE_REUSE_TAG_212_E = 807 , - WIFISPARE_REUSE_TAG_213_E = 808 , - WIFISPARE_REUSE_TAG_214_E = 809 , - WIFISPARE_REUSE_TAG_215_E = 810 , - WIFISPARE_REUSE_TAG_216_E = 811 , - WIFISPARE_REUSE_TAG_217_E = 812 , - WIFISPARE_REUSE_TAG_218_E = 813 , - WIFISPARE_REUSE_TAG_219_E = 814 , - WIFISPARE_REUSE_TAG_220_E = 815 , - WIFISPARE_REUSE_TAG_221_E = 816 , - WIFISPARE_REUSE_TAG_222_E = 817 , - WIFISPARE_REUSE_TAG_223_E = 818 , - WIFISPARE_REUSE_TAG_224_E = 819 , - WIFISPARE_REUSE_TAG_225_E = 820 , - WIFISPARE_REUSE_TAG_226_E = 821 , - WIFISPARE_REUSE_TAG_227_E = 822 , - WIFISPARE_REUSE_TAG_228_E = 823 , - WIFISPARE_REUSE_TAG_229_E = 824 , - WIFISPARE_REUSE_TAG_230_E = 825 , - WIFISPARE_REUSE_TAG_231_E = 826 , - WIFISPARE_REUSE_TAG_232_E = 827 , - WIFISPARE_REUSE_TAG_233_E = 828 , - WIFISPARE_REUSE_TAG_234_E = 829 , - WIFISPARE_REUSE_TAG_235_E = 830 , - WIFISPARE_REUSE_TAG_236_E = 831 , - WIFISPARE_REUSE_TAG_237_E = 832 , - WIFISPARE_REUSE_TAG_238_E = 833 , - WIFISPARE_REUSE_TAG_239_E = 834 , - WIFISPARE_REUSE_TAG_240_E = 835 , - WIFISPARE_REUSE_TAG_241_E = 836 , - WIFISPARE_REUSE_TAG_242_E = 837 , - WIFISPARE_REUSE_TAG_243_E = 838 , - WIFISPARE_REUSE_TAG_244_E = 839 , - WIFISPARE_REUSE_TAG_245_E = 840 , - WIFISPARE_REUSE_TAG_246_E = 841 , - WIFISPARE_REUSE_TAG_247_E = 842 , - WIFISPARE_REUSE_TAG_248_E = 843 , - WIFISPARE_REUSE_TAG_249_E = 844 , - WIFISPARE_REUSE_TAG_250_E = 845 , - WIFISPARE_REUSE_TAG_251_E = 846 , - WIFISPARE_REUSE_TAG_252_E = 847 , - WIFISPARE_REUSE_TAG_253_E = 848 , - WIFISPARE_REUSE_TAG_254_E = 849 , - WIFISPARE_REUSE_TAG_255_E = 850 , - WIFISPARE_REUSE_TAG_256_E = 851 , - WIFISPARE_REUSE_TAG_257_E = 852 , - WIFISPARE_REUSE_TAG_258_E = 853 , - WIFISPARE_REUSE_TAG_259_E = 854 , - WIFISPARE_REUSE_TAG_260_E = 855 , - WIFISPARE_REUSE_TAG_261_E = 856 , - WIFISPARE_REUSE_TAG_262_E = 857 , - WIFISPARE_REUSE_TAG_263_E = 858 , - WIFISPARE_REUSE_TAG_264_E = 859 , - WIFISPARE_REUSE_TAG_265_E = 860 , - WIFISPARE_REUSE_TAG_266_E = 861 , - WIFISPARE_REUSE_TAG_267_E = 862 , - WIFISPARE_REUSE_TAG_268_E = 863 , - WIFISPARE_REUSE_TAG_269_E = 864 , - WIFISPARE_REUSE_TAG_270_E = 865 , - WIFISPARE_REUSE_TAG_271_E = 866 , - WIFISPARE_REUSE_TAG_272_E = 867 , - WIFISPARE_REUSE_TAG_273_E = 868 , - WIFISPARE_REUSE_TAG_274_E = 869 , - WIFISPARE_REUSE_TAG_275_E = 870 , - WIFISPARE_REUSE_TAG_276_E = 871 , - WIFISPARE_REUSE_TAG_277_E = 872 , - WIFISPARE_REUSE_TAG_278_E = 873 , - WIFISPARE_REUSE_TAG_279_E = 874 , - WIFISPARE_REUSE_TAG_280_E = 875 , - WIFISPARE_REUSE_TAG_281_E = 876 , - WIFISPARE_REUSE_TAG_282_E = 877 , - WIFISPARE_REUSE_TAG_283_E = 878 , - WIFISPARE_REUSE_TAG_284_E = 879 , - WIFISPARE_REUSE_TAG_285_E = 880 , - WIFISPARE_REUSE_TAG_286_E = 881 , - WIFISPARE_REUSE_TAG_287_E = 882 , - WIFISPARE_REUSE_TAG_288_E = 883 , - WIFISPARE_REUSE_TAG_289_E = 884 , - WIFISPARE_REUSE_TAG_290_E = 885 , - WIFISPARE_REUSE_TAG_291_E = 886 , - WIFISPARE_REUSE_TAG_292_E = 887 , - WIFISPARE_REUSE_TAG_293_E = 888 , - WIFISPARE_REUSE_TAG_294_E = 889 , - WIFISPARE_REUSE_TAG_295_E = 890 , - WIFISPARE_REUSE_TAG_296_E = 891 , - WIFISPARE_REUSE_TAG_297_E = 892 , - WIFISPARE_REUSE_TAG_298_E = 893 , - WIFISPARE_REUSE_TAG_299_E = 894 , - WIFISPARE_REUSE_TAG_300_E = 895 , - WIFISPARE_REUSE_TAG_301_E = 896 , - WIFISPARE_REUSE_TAG_302_E = 897 , - WIFISPARE_REUSE_TAG_303_E = 898 , - WIFISPARE_REUSE_TAG_304_E = 899 , - WIFISPARE_REUSE_TAG_305_E = 900 , - WIFISPARE_REUSE_TAG_306_E = 901 , - WIFISPARE_REUSE_TAG_307_E = 902 , - WIFISPARE_REUSE_TAG_308_E = 903 , - WIFISPARE_REUSE_TAG_309_E = 904 , - WIFISPARE_REUSE_TAG_310_E = 905 , - WIFISPARE_REUSE_TAG_311_E = 906 , - WIFISPARE_REUSE_TAG_312_E = 907 , - WIFISPARE_REUSE_TAG_313_E = 908 , - WIFISPARE_REUSE_TAG_314_E = 909 , - WIFISPARE_REUSE_TAG_315_E = 910 , - WIFISPARE_REUSE_TAG_316_E = 911 , - WIFISPARE_REUSE_TAG_317_E = 912 , - WIFISPARE_REUSE_TAG_318_E = 913 , - WIFISPARE_REUSE_TAG_319_E = 914 , - WIFISPARE_REUSE_TAG_320_E = 915 , - WIFISPARE_REUSE_TAG_321_E = 916 , - WIFISPARE_REUSE_TAG_322_E = 917 , - WIFISPARE_REUSE_TAG_323_E = 918 , - WIFISPARE_REUSE_TAG_324_E = 919 , - WIFISPARE_REUSE_TAG_325_E = 920 , - WIFISPARE_REUSE_TAG_326_E = 921 , - WIFISPARE_REUSE_TAG_327_E = 922 , - WIFISPARE_REUSE_TAG_328_E = 923 , - WIFISPARE_REUSE_TAG_329_E = 924 , - WIFISPARE_REUSE_TAG_330_E = 925 , - WIFISPARE_REUSE_TAG_331_E = 926 , - WIFISPARE_REUSE_TAG_332_E = 927 , - WIFISPARE_REUSE_TAG_333_E = 928 , - WIFISPARE_REUSE_TAG_334_E = 929 , - WIFISPARE_REUSE_TAG_335_E = 930 , - WIFISPARE_REUSE_TAG_336_E = 931 , - WIFISPARE_REUSE_TAG_337_E = 932 , - WIFISPARE_REUSE_TAG_338_E = 933 , - WIFISPARE_REUSE_TAG_339_E = 934 , - WIFISPARE_REUSE_TAG_340_E = 935 , - WIFISPARE_REUSE_TAG_341_E = 936 , - WIFISPARE_REUSE_TAG_342_E = 937 , - WIFISPARE_REUSE_TAG_343_E = 938 , - WIFISPARE_REUSE_TAG_344_E = 939 , - WIFISPARE_REUSE_TAG_345_E = 940 , - WIFISPARE_REUSE_TAG_346_E = 941 , - WIFISPARE_REUSE_TAG_347_E = 942 , - WIFISPARE_REUSE_TAG_348_E = 943 , - WIFISPARE_REUSE_TAG_349_E = 944 , - WIFISPARE_REUSE_TAG_350_E = 945 , - WIFISPARE_REUSE_TAG_351_E = 946 , - WIFISPARE_REUSE_TAG_352_E = 947 , - WIFISPARE_REUSE_TAG_353_E = 948 , - WIFISPARE_REUSE_TAG_354_E = 949 , - WIFISPARE_REUSE_TAG_355_E = 950 , - WIFISPARE_REUSE_TAG_356_E = 951 , - WIFISPARE_REUSE_TAG_357_E = 952 , - WIFISPARE_REUSE_TAG_358_E = 953 , - WIFISPARE_REUSE_TAG_359_E = 954 , - WIFISPARE_REUSE_TAG_360_E = 955 , - WIFISPARE_REUSE_TAG_361_E = 956 , - WIFISPARE_REUSE_TAG_362_E = 957 , - WIFISPARE_REUSE_TAG_363_E = 958 , - WIFISPARE_REUSE_TAG_364_E = 959 , - WIFISPARE_REUSE_TAG_365_E = 960 , - WIFISPARE_REUSE_TAG_366_E = 961 , - WIFISPARE_REUSE_TAG_367_E = 962 , - WIFISPARE_REUSE_TAG_368_E = 963 , - WIFISPARE_REUSE_TAG_369_E = 964 , - WIFISPARE_REUSE_TAG_370_E = 965 , - WIFISPARE_REUSE_TAG_371_E = 966 , - WIFISPARE_REUSE_TAG_372_E = 967 , - WIFISPARE_REUSE_TAG_373_E = 968 , - WIFISPARE_REUSE_TAG_374_E = 969 , - WIFISPARE_REUSE_TAG_375_E = 970 , - WIFISPARE_REUSE_TAG_376_E = 971 , - WIFISPARE_REUSE_TAG_377_E = 972 , - WIFISPARE_REUSE_TAG_378_E = 973 , - WIFISPARE_REUSE_TAG_379_E = 974 , - WIFISPARE_REUSE_TAG_380_E = 975 , - WIFISPARE_REUSE_TAG_381_E = 976 , - WIFISPARE_REUSE_TAG_382_E = 977 , - WIFISPARE_REUSE_TAG_383_E = 978 , - WIFISPARE_REUSE_TAG_384_E = 979 , - WIFISPARE_REUSE_TAG_385_E = 980 , - WIFISPARE_REUSE_TAG_386_E = 981 , - WIFISPARE_REUSE_TAG_387_E = 982 , - WIFISPARE_REUSE_TAG_388_E = 983 , - WIFISPARE_REUSE_TAG_389_E = 984 , - WIFISPARE_REUSE_TAG_390_E = 985 , - WIFISPARE_REUSE_TAG_391_E = 986 , - WIFISPARE_REUSE_TAG_392_E = 987 , - WIFISPARE_REUSE_TAG_393_E = 988 , - WIFISPARE_REUSE_TAG_394_E = 989 , - WIFISPARE_REUSE_TAG_395_E = 990 , - WIFISPARE_REUSE_TAG_396_E = 991 , - WIFISPARE_REUSE_TAG_397_E = 992 , - WIFISPARE_REUSE_TAG_398_E = 993 , - WIFISPARE_REUSE_TAG_399_E = 994 , - WIFISPARE_REUSE_TAG_400_E = 995 , - WIFISPARE_REUSE_TAG_401_E = 996 , - WIFISPARE_REUSE_TAG_402_E = 997 , - WIFISPARE_REUSE_TAG_403_E = 998 , - WIFISPARE_REUSE_TAG_404_E = 999 , - WIFISPARE_REUSE_TAG_405_E = 1000 , - WIFISPARE_REUSE_TAG_406_E = 1001 , - WIFISPARE_REUSE_TAG_407_E = 1002 , - WIFISPARE_REUSE_TAG_408_E = 1003 , - WIFISPARE_REUSE_TAG_409_E = 1004 , - WIFISPARE_REUSE_TAG_410_E = 1005 , - WIFISPARE_REUSE_TAG_411_E = 1006 , - WIFISPARE_REUSE_TAG_412_E = 1007 , - WIFISPARE_REUSE_TAG_413_E = 1008 , - WIFISPARE_REUSE_TAG_414_E = 1009 , - WIFISPARE_REUSE_TAG_415_E = 1010 , - WIFISPARE_REUSE_TAG_416_E = 1011 , - WIFISPARE_REUSE_TAG_417_E = 1012 , - WIFISPARE_REUSE_TAG_418_E = 1013 , - WIFISPARE_REUSE_TAG_419_E = 1014 , - WIFISPARE_REUSE_TAG_420_E = 1015 , - WIFISPARE_REUSE_TAG_421_E = 1016 , - WIFISPARE_REUSE_TAG_422_E = 1017 , - WIFISPARE_REUSE_TAG_423_E = 1018 , - WIFISPARE_REUSE_TAG_424_E = 1019 , - WIFISPARE_REUSE_TAG_425_E = 1020 , - WIFISPARE_REUSE_TAG_426_E = 1021 -} tlv_tag_def__e; - -typedef enum { - WIFI_EXT_PHYRX_DATA_E = 1 , - WIFI_EXT_PHYRX_ABORT_REQUEST_E = 3 , - WIFI_EXT_MACTX_DATA_RESP_E = 5 , - WIFI_EXT_MACTX_CBF_DONE_E = 7 , - WIFI_EXT_RXPCU_TO_UCODE_START_E = 9 , - WIFI_EXT_RXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , - WIFI_EXT_RXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , - WIFI_EXT_RXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , - WIFI_EXT_PHYRX_RSSI_LEGACY_20MHZ_E = 17 , - WIFI_EXT_PHYRX_PKT_END_20MHZ_E = 19 , - WIFI_EXT_MACRX_CBF_DATA_REQUEST_E = 65 , - WIFI_EXT_MACRX_FREEZE_CAPTURE_CHANNEL_E = 67 , - WIFI_EXT_MACRX_ABORT_ACK_E = 69 , - WIFI_EXT_MACRX_CHAIN_MASK_E = 71 , - WIFI_EXT_MACRX_ABORT_REQUEST_E = 73 , - WIFI_EXT_PHYTX_ABORT_ACK_E = 75 , - WIFI_EXT_PHYTX_PKT_END_E = 77 , - WIFI_EXT_PHYTX_REQUEST_CTRL_INFO_E = 79 , - WIFI_EXT_PHYTX_BF_CV_LOADING_DONE_E = 81 , - WIFI_EXT_PHYTX_NAP_DONE_E = 83 , - WIFI_EXT_PHYTX_ON_ACK_E = 85 , - WIFI_EXT_PHYTX_DEBUG16_E = 87 , - WIFI_EXT_MACTX_ABORT_ACK_E = 89 , - WIFI_EXT_MACTX_PRE_PHY_DESC_E = 91 , - WIFI_EXT_MACTX_BF_PARAMS_PER_USER_E = 93 , - WIFI_EXT_MACTX_USER_DESC_COMMON_E = 95 , - WIFI_EXT_EXAMPLE_USER_TLV_16_E = 97 , - WIFI_EXT_MACTX_PHY_OFF_E = 99 , - WIFI_EXT_MACTX_SYNTH_OFF_E = 101 , - WIFI_EXT_MACTX_EXPECT_CBF_PER_USER_E = 103 , - WIFI_EXT_MACTX_L_SIG_A_E = 105 , - WIFI_EXT_MACTX_HT_SIG_E = 107 , - WIFI_EXT_MACTX_VHT_SIG_B_SU20_E = 109 , - WIFI_EXT_MACTX_VHT_SIG_B_SU80_E = 111 , - WIFI_EXT_MACTX_VHT_SIG_B_MU20_E = 113 , - WIFI_EXT_MACTX_VHT_SIG_B_MU80_E = 115 , - WIFI_EXT_MACTX_SERVICE_E = 117 , - WIFI_EXT_MACTX_HE_SIG_A_MU_DL_E = 119 , - WIFI_EXT_MACTX_HE_SIG_B1_MU_E = 121 , - WIFI_EXT_MACTX_HE_SIG_B2_OFDMA_E = 123 , - WIFI_EXT_MACTX_MU_UPLINK_COMMON_E = 125 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_E = 127 , - WIFI_EXT_MACTX_DEBUG_E = 129 , - WIFI_EXT_PHYRX_GENERATED_CBF_DETAILS_E = 131 , - WIFI_EXT_PHYRX_RSSI_HT_E = 133 , - WIFI_EXT_PHYRX_PKT_END_E = 135 , - WIFI_EXT_PHYRX_CBF_TRANSFER_DONE_E = 137 , - WIFI_EXT_PHYRX_L_SIG_A_E = 139 , - WIFI_EXT_PHYRX_HT_SIG_E = 141 , - WIFI_EXT_PHYRX_VHT_SIG_B_SU20_E = 143 , - WIFI_EXT_PHYRX_VHT_SIG_B_SU80_E = 145 , - WIFI_EXT_PHYRX_VHT_SIG_B_MU20_E = 147 , - WIFI_EXT_PHYRX_VHT_SIG_B_MU80_E = 149 , - WIFI_EXT_PHYRX_HE_SIG_A_SU_E = 151 , - WIFI_EXT_PHYRX_HE_SIG_A_MU_UL_E = 153 , - WIFI_EXT_PHYRX_HE_SIG_B2_MU_E = 155 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_E = 157 , - WIFI_EXT_PHYRX_DATA_DONE_E = 159 , - WIFI_EXT_DUMMY_E = 161 , - WIFI_EXT_MPDU_LIMIT_E = 163 , - WIFI_EXT_OLE_BUF_STATUS_E = 165 , - WIFI_EXT_PCU_PPDU_SETUP_END_E = 167 , - WIFI_EXT_PCU_PPDU_SETUP_START_E = 169 , - WIFI_EXT_PDG_RESPONSE_E = 171 , - WIFI_EXT_SCH_WAIT_INSTR_E = 173 , - WIFI_EXT_PHYTX_LINK_STATE_E = 175 , - WIFI_EXT_TQM_GEN_MPDU_LENGTH_LIST_E = 177 , - WIFI_EXT_TQM_GEN_MPDUS_E = 179 , - WIFI_EXT_TQM_REMOVE_MPDU_E = 181 , - WIFI_EXT_TQM_REMOVE_MSDU_E = 183 , - WIFI_EXT_TQM_UPDATE_TX_MPDU_COUNT_E = 185 , - WIFI_EXT_OFDMA_TRIGGER_DETAILS_E = 187 , - WIFI_EXT_TX_FES_SETUP_E = 189 , - WIFI_EXT_EXPECTED_RESPONSE_E = 191 , - WIFI_EXT_TX_MPDU_START_E = 193 , - WIFI_EXT_TX_MSDU_START_E = 195 , - WIFI_EXT_TXPCU_BUFFER_STATUS_E = 197 , - WIFI_EXT_DATA_TO_TIME_CONFIG_E = 199 , - WIFI_EXT_MPDU_INFO_E = 201 , - WIFI_EXT_TX_11AH_SETUP_E = 203 , - WIFI_EXT_TX_PEER_ENTRY_E = 205 , - WIFI_EXT_EXAMPLE_USER_TLV_44_E = 207 , - WIFI_EXT_TX_FLUSH_REQ_E = 209 , - WIFI_EXT_TQM_GET_MPDU_QUEUE_STATS_E = 211 , - WIFI_EXT_EXAMPLE_USER_CTLV_44_E = 213 , - WIFI_EXT_TX_FES_STATUS_USER_PPDU_E = 215 , - WIFI_EXT_TX_FES_STATUS_END_E = 217 , - WIFI_EXT_RXPCU_TX_SETUP_CLEAR_E = 219 , - WIFI_EXT_RX_FRAME_BITMAP_ACK_E = 221 , - WIFI_EXT_RX_START_PARAM_E = 223 , - WIFI_EXT_RX_PPDU_END_E = 225 , - WIFI_EXT_RX_MPDU_END_E = 227 , - WIFI_EXT_RX_MSDU_END_E = 229 , - WIFI_EXT_RECEIVED_RESPONSE_INFO_E = 231 , - WIFI_EXT_RX_HEADER_E = 233 , - WIFI_EXT_RX_FLUSH_E = 235 , - WIFI_EXT_RX_FRAMELESS_BAR_DETAILS_E = 237 , - WIFI_EXT_TQM_GET_MSDU_FLOW_STATS_STATUS_E = 239 , - WIFI_EXT_PCU_PPDU_SETUP_USER_E = 241 , - WIFI_EXT_RX_PM_INFO_E = 243 , - WIFI_EXT_RX_PRE_PPDU_START_E = 245 , - WIFI_EXT_TX_FES_SETUP_COMPLETE_E = 247 , - WIFI_EXT_TXDMA_STOP_REQUEST_E = 249 , - WIFI_EXT_RXPCU_USER_SETUP_E = 251 , - WIFI_EXT_TQM_ACKED_MPDU_E = 253 , - WIFI_EXT_COEX_TX_STATUS_E = 255 , - WIFI_EXT_COEX_STATUS_BROADCAST_E = 257 , - WIFI_EXT_RESPONSE_END_STATUS_E = 259 , - WIFI_EXT_RECEIVED_TRIGGER_INFO_E = 261 , - WIFI_EXT_RX_PPDU_ACK_REPORT_E = 263 , - WIFI_EXT_SCH_COEX_STATUS_E = 265 , - WIFI_EXT_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 267 , - WIFI_EXT_TX_FES_STATUS_START_PPDU_E = 269 , - WIFI_EXT_TXPCU_PHYTX_DEBUG32_E = 271 , - WIFI_EXT_TX_MPDU_COUNT_TRANSFER_END_E = 273 , - WIFI_EXT_WHO_ANCHOR_VALUE_E = 275 , - WIFI_EXT_WHO_COMMIT_E = 277 , - WIFI_EXT_WHO_FLUSH_E = 279 , - WIFI_EXT_WHO_L2_PAYLOAD_E = 281 , - WIFI_EXT_WHO_L3_INFO_E = 283 , - WIFI_EXT_WHO_L4_INFO_E = 285 , - WIFI_EXT_WHO_MSDU_MISC_E = 287 , - WIFI_EXT_WHO_PACKET_HDR_E = 289 , - WIFI_EXT_WHO_PPDU_START_E = 291 , - WIFI_EXT_WHO_WMAC_HEADER_PV0_E = 293 , - WIFI_EXT_WHO_WMAC_IV_E = 295 , - WIFI_EXT_MPDU_INFO_BITMAP_E = 297 , - WIFI_EXT_SCHEDULER_SELFGEN_RESPONSE_STATUS_E = 299 , - WIFI_EXT_TQM_ACKED_MPDU_STATUS_E = 301 , - WIFI_EXT_TQM_LIST_GEN_DONE_E = 303 , - WIFI_EXT_TX_LAST_MPDU_END_E = 305 , - WIFI_EXT_PPDU_TX_END_E = 307 , - WIFI_EXT_MPDU_INFO_GLOBAL_END_E = 309 , - WIFI_EXT_RX_PPDU_END_USER_STATS_E = 311 , - WIFI_EXT_REO_GET_QUEUE_STATS_E = 313 , - WIFI_EXT_REO_FLUSH_CACHE_E = 315 , - WIFI_EXT_REO_GET_QUEUE_STATS_STATUS_E = 317 , - WIFI_EXT_REO_FLUSH_CACHE_STATUS_E = 319 , - WIFI_EXT_TQM_FLUSH_CACHE_E = 321 , - WIFI_EXT_TQM_FLUSH_CACHE_STATUS_E = 323 , - WIFI_EXT_RX_PPDU_END_STATUS_DONE_E = 325 , - WIFI_EXT_SCHEDULER_MLO_SW_MSG_STATUS_E = 327 , - WIFI_EXT_TX_DATA_SYNC_E = 329 , - WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_E = 331 , - WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_STATUS_E = 333 , - WIFI_EXT_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 335 , - WIFI_EXT_REO_FLUSH_TIMEOUT_LIST_E = 337 , - WIFI_EXT_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 339 , - WIFI_EXT_EXAMPLE_USER_TLV_32_NAME_E = 341 , - WIFI_EXT_RX_RING_MASK_E = 343 , - WIFI_EXT_RXPCU_PPDU_END_INFO_E = 345 , - WIFI_EXT_PDG_SW_MODE_BW_START_E = 347 , - WIFI_EXT_PDG_WAIT_FOR_MAC_REQUEST_E = 349 , - WIFI_EXT_SCHEDULER_END_E = 351 , - WIFI_EXT_RX_PPDU_END_DROPPED_E = 353 , - WIFI_EXT_RX_MPDU_START_DROPPED_E = 355 , - WIFI_EXT_RX_MSDU_END_DROPPED_E = 357 , - WIFI_EXT_RX_ATTENTION_DROPPED_E = 359 , - WIFI_EXT_RXPCU_USER_SETUP_EXT_E = 361 , - WIFI_EXT_MACTX_SYNTH_ON_E = 363 , - WIFI_EXT_TQM_MPDU_GLOBAL_START_E = 365 , - WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_E = 367 , - WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 369 , - WIFI_EXT_REO_UPDATE_RX_REO_QUEUE_E = 371 , - WIFI_EXT_PDG_TRIG_RESPONSE_E = 373 , - WIFI_EXT_ABORT_FROM_PHYRX_DETAILS_E = 375 , - WIFI_EXT_MPDUS_AVAILABLE_E = 377 , - WIFI_EXT_PHYRX_TX_START_TIMING_E = 379 , - WIFI_EXT_NDP_PREAMBLE_DONE_E = 381 , - WIFI_EXT_SCH_TQM_CMD_WRAPPER_CONT_DROP_E = 383 , - WIFI_EXT_TX_PUNCTURE_SETUP_E = 385 , - WIFI_EXT_MACTX_PREFETCH_CV_COMMON_E = 387 , - WIFI_EXT_MACTX_MU_UPLINK_COMMON_PUNC_E = 389 , - WIFI_EXT_RECEIVED_RESPONSE_USER_7_0_E = 391 , - WIFI_EXT_RECEIVED_RESPONSE_USER_23_16_E = 393 , - WIFI_EXT_RECEIVED_RESPONSE_USER_36_32_E = 395 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 397 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 399 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 401 , - WIFI_EXT_RX_PPDU_END_START_E = 403 , - WIFI_EXT_RX_PPDU_END_LAST_E = 405 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 407 , - WIFI_EXT_OBSS_SR_INFO_E = 409 , - WIFI_EXT_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 411 , - WIFI_EXT_MACTX_MCC_SWITCH_E = 413 , - WIFI_EXT_PHYTX_MCC_SWITCH_ACK_E = 415 , - WIFI_EXT_PHYTX_EMLSR_PRE_SWITCH_ACK_E = 417 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 419 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 421 , - WIFI_EXT_SCH_TLV_WRAPPER_E = 423 , - WIFI_EXT_MPDU_INFO_6X_E = 425 , - WIFI_EXT_MACTX_U_SIG_EHT_SU_MU_E = 427 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG0_CFG_E = 429 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG2_CFG_E = 431 , - WIFI_EXT_PHYRX_U_SIG_EHT_TB_E = 433 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 435 , - WIFI_EXT_MACRX_LMR_READ_REQUEST_E = 437 , - WIFI_EXT_PHYRX_LMR_TRANSFER_DONE_E = 439 , - WIFI_EXT_PHYRX_LMR_READ_REQUEST_ACK_E = 441 , - WIFI_EXT_PHYRX_USER_INFO_MU_UL_E = 443 , - WIFI_EXT_SCHEDULER_NAV_INFO_E = 445 , - WIFI_EXT_LMR_PEER_ENTRY_E = 447 , - WIFI_EXT_LMR_DATA_E = 449 , - WIFI_EXT_REO_GET_QUEUE_1K_STATS_STATUS_E = 451 , - WIFI_EXT_TX_FES_STATUS_1K_BA_E = 453 , - WIFI_EXT_MACRX_INBSS_OBSS_IND_E = 455 , - WIFI_EXT_MLO_TX_NOTIFICATION_SU_E = 457 , - WIFI_EXT_MLO_TX_REQ_SU_E = 459 , - WIFI_EXT_MLO_TX_RESP_E = 461 , - WIFI_EXT_MLO_BKOFF_TRUNC_REQ_E = 463 , - WIFI_EXT_MLO_MESSAGE_E = 465 , - WIFI_EXT_MLO_FES_SETUP_E = 467 , - WIFI_EXT_MLO_PDG_FES_SETUP_MU_E = 469 , - WIFI_EXT_MON_BUFFER_ADDR_E = 471 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 473 , - WIFI_EXT_MACTX_EHT_SIG_USR_OFDMA_E = 475 , - WIFI_EXT_MACTX_U_SIG_UHR_TB_E = 477 , - WIFI_EXT_TX_MSDU_COMPRESSED_DETAILS_TLV_E = 479 , - WIFI_EXT_PHYRX_EHT_SIG_USR_OFDMA_E = 481 , - WIFI_EXT_PHYRX_PKT_END_PART1_E = 483 , - WIFI_EXT_MACTX_SECURE_LTF_SEQ_PTR_E = 485 , - WIFI_EXT_MLO_PDG_BKOFF_TRUNC_NOTIFY_E = 487 , - WIFI_EXT_PHYTX_LOCATION_E = 489 , - WIFI_EXT_MPDU_LENGTH_STRUCTS_START_E = 491 , - WIFI_EXT_MACTX_EHT_SIG_USR_MU_MIMO_E = 493 , - WIFI_EXT_PHYRX_EHT_SIG_USR_MU_MIMO_E = 495 , - WIFI_EXT_PHYRX_GENERIC_EHT_OR_UHR_SIG_E = 497 , - WIFI_EXT_OVERWRITE_RESP_PREAMBLE_INFO_E = 499 , - WIFI_EXT_OVERWRITE_RESP_END_E = 501 , - WIFI_EXT_MON_DROP_E = 503 , - WIFI_EXT_MACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 505 , - WIFI_EXT_MACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 507 , - WIFI_EXT_MACTX_PREFETCH_CV_PER_USER_E = 509 , - WIFI_EXT_MACTX_BF_PARAMS_UPDATE_COMMON_E = 511 , - WIFI_EXT_RANGING_USER_DETAILS_E = 513 , - WIFI_EXT_PHYTX_CV_CORR_COMMON_E = 515 , - WIFI_EXT_MACTX_CV_CORR_COMMON_E = 517 , - WIFI_EXT_BW_PUNCTURE_EVAL_WRAPPER_E = 519 , - WIFI_EXT_MACTX_TX_NOTIFICATION_FOR_PHY_E = 521 , - WIFI_EXT_MACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 523 , - WIFI_EXT_FW2SW_MON_E = 525 , - WIFI_EXT_MACTX_EMLSR_PRE_SWITCH_E = 527 , - WIFI_EXT_MACTX_EMLSR_SWITCH_BACK_E = 529 , - WIFI_EXT_PHYTX_EMLSR_SWITCH_BACK_ACK_E = 531 , - WIFI_EXT_EAD_LEGACY_STATUS_CONTROL_E = 533 , - WIFI_EXT_TPI_TX_INITIALIZATION_CONFIG_E = 535 , - WIFI_EXT_TPI_LEGACY_STATUS_CONTROL_E = 537 , - WIFI_EXT_TPI_MPDU_START_E = 539 , - WIFI_EXT_TPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E = 541 , - WIFI_EXT_TPI_TX_START_TIME_ARRIVED_E = 543 , - WIFI_EXT_TPI_ERROR_STATUS_E = 545 , - WIFI_EXT_RPI_SEND_TLV_TO_PHYRX_E = 547 , - WIFI_EXT_RPI_LEGACY_INTERRUPT_CONTROL_E = 549 , - WIFI_EXT_RPI_ERROR_STATUS_E = 551 , - WIFI_EXT_RPI_RX_FRAME_UPDATE_STATUS_E = 553 , - WIFI_EXT_TCC_TLV_FETCH_E = 555 , - WIFI_EXT_TCC_LEGACY_INTERRUPT_CONTROL_E = 557 , - WIFI_EXT_TCC_ERROR_STATUS_E = 559 , - WIFI_EXT_TCC_PRE_BACKOFF_CMD_AVAILABLE_E = 561 , - WIFI_EXT_TCC_BURST_CMD_AVAILABLE_E = 563 , - WIFI_EXT_EAD_RING_AIR_TIME_REFERENCE_E = 565 , - WIFI_EXT_RPI_WRITE_INFO_TO_EXT_MEM_E = 567 , - WIFI_EXT_RPI_INIT_LMR_DATA_RESP_ADDR_E = 569 , - WIFI_EXT_TPI_SEND_CTLV_44_TO_PHYTX_E = 571 , - WIFI_EXT_TPI_TX_FRAME_UPDATE_STATUS_E = 573 , - WIFI_EXT_EAD_MPDU_DATA_FETCH_CONTINUATION_E = 575 , - WIFI_EXT_EAD_MSDU_STATUS_DETAILS_E = 577 , - WIFI_EXT_MACTX_UHR_SIG_USR_MU_MIMO_E = 579 , - WIFI_EXT_MACTX_ELR_SIG_UHR_SU_E = 581 , - WIFI_EXT_PEER_BLACKOUT_DETAILS_E = 583 , - WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_E = 585 , - WIFI_EXT_HDR_CTRL_PROT_DATA_E = 587 , - WIFI_EXT_HDR_CTRL_PROT_MIC_STATUS_E = 589 , - WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_DONE_E = 591 , - WIFI_EXT_MACTX_U_SIG_UHR_COBF_E = 593 , - WIFI_EXT_SPARE_REUSE_TAG_0_E = 595 , - WIFI_EXT_SPARE_REUSE_TAG_2_E = 597 , - WIFI_EXT_SPARE_REUSE_TAG_4_E = 599 , - WIFI_EXT_SPARE_REUSE_TAG_6_E = 601 , - WIFI_EXT_SPARE_REUSE_TAG_8_E = 603 , - WIFI_EXT_SPARE_REUSE_TAG_10_E = 605 , - WIFI_EXT_SPARE_REUSE_TAG_12_E = 607 , - WIFI_EXT_SPARE_REUSE_TAG_14_E = 609 , - WIFI_EXT_SPARE_REUSE_TAG_16_E = 611 , - WIFI_EXT_SPARE_REUSE_TAG_18_E = 613 , - WIFI_EXT_SPARE_REUSE_TAG_20_E = 615 , - WIFI_EXT_SPARE_REUSE_TAG_22_E = 617 , - WIFI_EXT_SPARE_REUSE_TAG_24_E = 619 , - WIFI_EXT_SPARE_REUSE_TAG_26_E = 621 , - WIFI_EXT_SPARE_REUSE_TAG_28_E = 623 , - WIFI_EXT_SPARE_REUSE_TAG_30_E = 625 , - WIFI_EXT_SPARE_REUSE_TAG_32_E = 627 , - WIFI_EXT_SPARE_REUSE_TAG_34_E = 629 , - WIFI_EXT_SPARE_REUSE_TAG_36_E = 631 , - WIFI_EXT_SPARE_REUSE_TAG_38_E = 633 , - WIFI_EXT_SPARE_REUSE_TAG_40_E = 635 , - WIFI_EXT_SPARE_REUSE_TAG_42_E = 637 , - WIFI_EXT_SPARE_REUSE_TAG_44_E = 639 , - WIFI_EXT_SPARE_REUSE_TAG_46_E = 641 , - WIFI_EXT_SPARE_REUSE_TAG_48_E = 643 , - WIFI_EXT_SPARE_REUSE_TAG_50_E = 645 , - WIFI_EXT_SPARE_REUSE_TAG_52_E = 647 , - WIFI_EXT_SPARE_REUSE_TAG_54_E = 649 , - WIFI_EXT_SPARE_REUSE_TAG_56_E = 651 , - WIFI_EXT_SPARE_REUSE_TAG_58_E = 653 , - WIFI_EXT_SPARE_REUSE_TAG_60_E = 655 , - WIFI_EXT_SPARE_REUSE_TAG_62_E = 657 , - WIFI_EXT_SPARE_REUSE_TAG_64_E = 659 , - WIFI_EXT_SPARE_REUSE_TAG_66_E = 661 , - WIFI_EXT_SPARE_REUSE_TAG_68_E = 663 , - WIFI_EXT_SPARE_REUSE_TAG_70_E = 665 , - WIFI_EXT_SPARE_REUSE_TAG_72_E = 667 , - WIFI_EXT_SPARE_REUSE_TAG_74_E = 669 , - WIFI_EXT_SPARE_REUSE_TAG_76_E = 671 , - WIFI_EXT_SPARE_REUSE_TAG_78_E = 673 , - WIFI_EXT_SPARE_REUSE_TAG_80_E = 675 , - WIFI_EXT_SPARE_REUSE_TAG_82_E = 677 , - WIFI_EXT_SPARE_REUSE_TAG_84_E = 679 , - WIFI_EXT_SPARE_REUSE_TAG_86_E = 681 , - WIFI_EXT_SPARE_REUSE_TAG_88_E = 683 , - WIFI_EXT_SPARE_REUSE_TAG_90_E = 685 , - WIFI_EXT_SPARE_REUSE_TAG_92_E = 687 , - WIFI_EXT_SPARE_REUSE_TAG_94_E = 689 , - WIFI_EXT_SPARE_REUSE_TAG_96_E = 691 , - WIFI_EXT_SPARE_REUSE_TAG_98_E = 693 , - WIFI_EXT_SPARE_REUSE_TAG_100_E = 695 , - WIFI_EXT_SPARE_REUSE_TAG_102_E = 697 , - WIFI_EXT_SPARE_REUSE_TAG_104_E = 699 , - WIFI_EXT_SPARE_REUSE_TAG_106_E = 701 , - WIFI_EXT_SPARE_REUSE_TAG_108_E = 703 , - WIFI_EXT_SPARE_REUSE_TAG_110_E = 705 , - WIFI_EXT_SPARE_REUSE_TAG_112_E = 707 , - WIFI_EXT_SPARE_REUSE_TAG_114_E = 709 , - WIFI_EXT_SPARE_REUSE_TAG_116_E = 711 , - WIFI_EXT_SPARE_REUSE_TAG_118_E = 713 , - WIFI_EXT_SPARE_REUSE_TAG_120_E = 715 , - WIFI_EXT_SPARE_REUSE_TAG_122_E = 717 , - WIFI_EXT_SPARE_REUSE_TAG_124_E = 719 , - WIFI_EXT_SPARE_REUSE_TAG_126_E = 721 , - WIFI_EXT_SPARE_REUSE_TAG_128_E = 723 , - WIFI_EXT_SPARE_REUSE_TAG_130_E = 725 , - WIFI_EXT_SPARE_REUSE_TAG_132_E = 727 , - WIFI_EXT_SPARE_REUSE_TAG_134_E = 729 , - WIFI_EXT_SPARE_REUSE_TAG_136_E = 731 , - WIFI_EXT_SPARE_REUSE_TAG_138_E = 733 , - WIFI_EXT_SPARE_REUSE_TAG_140_E = 735 , - WIFI_EXT_SPARE_REUSE_TAG_142_E = 737 , - WIFI_EXT_SPARE_REUSE_TAG_144_E = 739 , - WIFI_EXT_SPARE_REUSE_TAG_146_E = 741 , - WIFI_EXT_SPARE_REUSE_TAG_148_E = 743 , - WIFI_EXT_SPARE_REUSE_TAG_150_E = 745 , - WIFI_EXT_SPARE_REUSE_TAG_152_E = 747 , - WIFI_EXT_SPARE_REUSE_TAG_154_E = 749 , - WIFI_EXT_SPARE_REUSE_TAG_156_E = 751 , - WIFI_EXT_SPARE_REUSE_TAG_158_E = 753 , - WIFI_EXT_SPARE_REUSE_TAG_160_E = 755 , - WIFI_EXT_SPARE_REUSE_TAG_162_E = 757 , - WIFI_EXT_SPARE_REUSE_TAG_164_E = 759 , - WIFI_EXT_SPARE_REUSE_TAG_166_E = 761 , - WIFI_EXT_SPARE_REUSE_TAG_168_E = 763 , - WIFI_EXT_SPARE_REUSE_TAG_170_E = 765 , - WIFI_EXT_SPARE_REUSE_TAG_172_E = 767 , - WIFI_EXT_SPARE_REUSE_TAG_174_E = 769 , - WIFI_EXT_SPARE_REUSE_TAG_176_E = 771 , - WIFI_EXT_SPARE_REUSE_TAG_178_E = 773 , - WIFI_EXT_SPARE_REUSE_TAG_180_E = 775 , - WIFI_EXT_SPARE_REUSE_TAG_182_E = 777 , - WIFI_EXT_SPARE_REUSE_TAG_184_E = 779 , - WIFI_EXT_SPARE_REUSE_TAG_186_E = 781 , - WIFI_EXT_SPARE_REUSE_TAG_188_E = 783 , - WIFI_EXT_SPARE_REUSE_TAG_190_E = 785 , - WIFI_EXT_SPARE_REUSE_TAG_192_E = 787 , - WIFI_EXT_SPARE_REUSE_TAG_194_E = 789 , - WIFI_EXT_SPARE_REUSE_TAG_196_E = 791 , - WIFI_EXT_SPARE_REUSE_TAG_198_E = 793 , - WIFI_EXT_SPARE_REUSE_TAG_200_E = 795 , - WIFI_EXT_SPARE_REUSE_TAG_202_E = 797 , - WIFI_EXT_SPARE_REUSE_TAG_204_E = 799 , - WIFI_EXT_SPARE_REUSE_TAG_206_E = 801 , - WIFI_EXT_SPARE_REUSE_TAG_208_E = 803 , - WIFI_EXT_SPARE_REUSE_TAG_210_E = 805 , - WIFI_EXT_SPARE_REUSE_TAG_212_E = 807 , - WIFI_EXT_SPARE_REUSE_TAG_214_E = 809 , - WIFI_EXT_SPARE_REUSE_TAG_216_E = 811 , - WIFI_EXT_SPARE_REUSE_TAG_218_E = 813 , - WIFI_EXT_SPARE_REUSE_TAG_220_E = 815 , - WIFI_EXT_SPARE_REUSE_TAG_222_E = 817 , - WIFI_EXT_SPARE_REUSE_TAG_224_E = 819 , - WIFI_EXT_SPARE_REUSE_TAG_226_E = 821 , - WIFI_EXT_SPARE_REUSE_TAG_228_E = 823 , - WIFI_EXT_SPARE_REUSE_TAG_230_E = 825 , - WIFI_EXT_SPARE_REUSE_TAG_232_E = 827 , - WIFI_EXT_SPARE_REUSE_TAG_234_E = 829 , - WIFI_EXT_SPARE_REUSE_TAG_236_E = 831 , - WIFI_EXT_SPARE_REUSE_TAG_238_E = 833 , - WIFI_EXT_SPARE_REUSE_TAG_240_E = 835 , - WIFI_EXT_SPARE_REUSE_TAG_242_E = 837 , - WIFI_EXT_SPARE_REUSE_TAG_244_E = 839 , - WIFI_EXT_SPARE_REUSE_TAG_246_E = 841 , - WIFI_EXT_SPARE_REUSE_TAG_248_E = 843 , - WIFI_EXT_SPARE_REUSE_TAG_250_E = 845 , - WIFI_EXT_SPARE_REUSE_TAG_252_E = 847 , - WIFI_EXT_SPARE_REUSE_TAG_254_E = 849 , - WIFI_EXT_SPARE_REUSE_TAG_256_E = 851 , - WIFI_EXT_SPARE_REUSE_TAG_258_E = 853 , - WIFI_EXT_SPARE_REUSE_TAG_260_E = 855 , - WIFI_EXT_SPARE_REUSE_TAG_262_E = 857 , - WIFI_EXT_SPARE_REUSE_TAG_264_E = 859 , - WIFI_EXT_SPARE_REUSE_TAG_266_E = 861 , - WIFI_EXT_SPARE_REUSE_TAG_268_E = 863 , - WIFI_EXT_SPARE_REUSE_TAG_270_E = 865 , - WIFI_EXT_SPARE_REUSE_TAG_272_E = 867 , - WIFI_EXT_SPARE_REUSE_TAG_274_E = 869 , - WIFI_EXT_SPARE_REUSE_TAG_276_E = 871 , - WIFI_EXT_SPARE_REUSE_TAG_278_E = 873 , - WIFI_EXT_SPARE_REUSE_TAG_280_E = 875 , - WIFI_EXT_SPARE_REUSE_TAG_282_E = 877 , - WIFI_EXT_SPARE_REUSE_TAG_284_E = 879 , - WIFI_EXT_SPARE_REUSE_TAG_286_E = 881 , - WIFI_EXT_SPARE_REUSE_TAG_288_E = 883 , - WIFI_EXT_SPARE_REUSE_TAG_290_E = 885 , - WIFI_EXT_SPARE_REUSE_TAG_292_E = 887 , - WIFI_EXT_SPARE_REUSE_TAG_294_E = 889 , - WIFI_EXT_SPARE_REUSE_TAG_296_E = 891 , - WIFI_EXT_SPARE_REUSE_TAG_298_E = 893 , - WIFI_EXT_SPARE_REUSE_TAG_300_E = 895 , - WIFI_EXT_SPARE_REUSE_TAG_302_E = 897 , - WIFI_EXT_SPARE_REUSE_TAG_304_E = 899 , - WIFI_EXT_SPARE_REUSE_TAG_306_E = 901 , - WIFI_EXT_SPARE_REUSE_TAG_308_E = 903 , - WIFI_EXT_SPARE_REUSE_TAG_310_E = 905 , - WIFI_EXT_SPARE_REUSE_TAG_312_E = 907 , - WIFI_EXT_SPARE_REUSE_TAG_314_E = 909 , - WIFI_EXT_SPARE_REUSE_TAG_316_E = 911 , - WIFI_EXT_SPARE_REUSE_TAG_318_E = 913 , - WIFI_EXT_SPARE_REUSE_TAG_320_E = 915 , - WIFI_EXT_SPARE_REUSE_TAG_322_E = 917 , - WIFI_EXT_SPARE_REUSE_TAG_324_E = 919 , - WIFI_EXT_SPARE_REUSE_TAG_326_E = 921 , - WIFI_EXT_SPARE_REUSE_TAG_328_E = 923 , - WIFI_EXT_SPARE_REUSE_TAG_330_E = 925 , - WIFI_EXT_SPARE_REUSE_TAG_332_E = 927 , - WIFI_EXT_SPARE_REUSE_TAG_334_E = 929 , - WIFI_EXT_SPARE_REUSE_TAG_336_E = 931 , - WIFI_EXT_SPARE_REUSE_TAG_338_E = 933 , - WIFI_EXT_SPARE_REUSE_TAG_340_E = 935 , - WIFI_EXT_SPARE_REUSE_TAG_342_E = 937 , - WIFI_EXT_SPARE_REUSE_TAG_344_E = 939 , - WIFI_EXT_SPARE_REUSE_TAG_346_E = 941 , - WIFI_EXT_SPARE_REUSE_TAG_348_E = 943 , - WIFI_EXT_SPARE_REUSE_TAG_350_E = 945 , - WIFI_EXT_SPARE_REUSE_TAG_352_E = 947 , - WIFI_EXT_SPARE_REUSE_TAG_354_E = 949 , - WIFI_EXT_SPARE_REUSE_TAG_356_E = 951 , - WIFI_EXT_SPARE_REUSE_TAG_358_E = 953 , - WIFI_EXT_SPARE_REUSE_TAG_360_E = 955 , - WIFI_EXT_SPARE_REUSE_TAG_362_E = 957 , - WIFI_EXT_SPARE_REUSE_TAG_364_E = 959 , - WIFI_EXT_SPARE_REUSE_TAG_366_E = 961 , - WIFI_EXT_SPARE_REUSE_TAG_368_E = 963 , - WIFI_EXT_SPARE_REUSE_TAG_370_E = 965 , - WIFI_EXT_SPARE_REUSE_TAG_372_E = 967 , - WIFI_EXT_SPARE_REUSE_TAG_374_E = 969 , - WIFI_EXT_SPARE_REUSE_TAG_376_E = 971 , - WIFI_EXT_SPARE_REUSE_TAG_378_E = 973 , - WIFI_EXT_SPARE_REUSE_TAG_380_E = 975 , - WIFI_EXT_SPARE_REUSE_TAG_382_E = 977 , - WIFI_EXT_SPARE_REUSE_TAG_384_E = 979 , - WIFI_EXT_SPARE_REUSE_TAG_386_E = 981 , - WIFI_EXT_SPARE_REUSE_TAG_388_E = 983 , - WIFI_EXT_SPARE_REUSE_TAG_390_E = 985 , - WIFI_EXT_SPARE_REUSE_TAG_392_E = 987 , - WIFI_EXT_SPARE_REUSE_TAG_394_E = 989 , - WIFI_EXT_SPARE_REUSE_TAG_396_E = 991 , - WIFI_EXT_SPARE_REUSE_TAG_398_E = 993 , - WIFI_EXT_SPARE_REUSE_TAG_400_E = 995 , - WIFI_EXT_SPARE_REUSE_TAG_402_E = 997 , - WIFI_EXT_SPARE_REUSE_TAG_404_E = 999 , - WIFI_EXT_SPARE_REUSE_TAG_406_E = 1001 , - WIFI_EXT_SPARE_REUSE_TAG_408_E = 1003 , - WIFI_EXT_SPARE_REUSE_TAG_410_E = 1005 , - WIFI_EXT_SPARE_REUSE_TAG_412_E = 1007 , - WIFI_EXT_SPARE_REUSE_TAG_414_E = 1009 , - WIFI_EXT_SPARE_REUSE_TAG_416_E = 1011 , - WIFI_EXT_SPARE_REUSE_TAG_418_E = 1013 , - WIFI_EXT_SPARE_REUSE_TAG_420_E = 1015 , - WIFI_EXT_SPARE_REUSE_TAG_422_E = 1017 , - WIFI_EXT_SPARE_REUSE_TAG_424_E = 1019 , - WIFI_EXT_SPARE_REUSE_TAG_426_E = 1021 -} ext_tlv_tag_def__e; - -typedef enum { - WIFI_N_EXT_MACTX_CBF_START_E = 0 , - WIFI_N_EXT_PHYRX_CBF_DATA_RESP_E = 2 , - WIFI_N_EXT_PHYRX_USER_ABORT_NOTIFICATION_E = 4 , - WIFI_N_EXT_MACTX_CBF_DATA_E = 6 , - WIFI_N_EXT_PHYRX_LMR_DATA_RESP_E = 8 , - WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , - WIFI_N_EXT_RXPCU_TO_UCODE_FCS_STATUS_E = 12 , - WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , - WIFI_N_EXT_RXPCU_TO_UCODE_END_E = 16 , - WIFI_N_EXT_PHYRX_NC_ABORT_REQUEST_E = 18 , - WIFI_N_EXT_PHYRX_NC_DATA_E = 20 , - WIFI_N_EXT_MACRX_CBF_READ_REQUEST_E = 64 , - WIFI_N_EXT_MACRX_EXPECT_NDP_RECEPTION_E = 66 , - WIFI_N_EXT_MACRX_NDP_TIMEOUT_E = 68 , - WIFI_N_EXT_MACRX_REQ_IMPLICIT_FB_E = 70 , - WIFI_N_EXT_MACRX_NAP_USER_E = 72 , - WIFI_N_EXT_PHYTX_OTHER_TRANSMIT_INFO16_E = 74 , - WIFI_N_EXT_PHYTX_ABORT_REQUEST_E = 76 , - WIFI_N_EXT_PHYTX_PPDU_HEADER_INFO_REQUEST_E = 78 , - WIFI_N_EXT_PHYTX_DATA_REQUEST_E = 80 , - WIFI_N_EXT_PHYTX_NAP_ACK_E = 82 , - WIFI_N_EXT_PHYTX_OFF_ACK_E = 84 , - WIFI_N_EXT_PHYTX_SYNTH_OFF_ACK_E = 86 , - WIFI_N_EXT_MACTX_ABORT_REQUEST_E = 88 , - WIFI_N_EXT_MACTX_PKT_END_E = 90 , - WIFI_N_EXT_MACTX_BF_PARAMS_COMMON_E = 92 , - WIFI_N_EXT_MACTX_PREFETCH_CV_E = 94 , - WIFI_N_EXT_MACTX_USER_DESC_PER_USER_E = 96 , - WIFI_N_EXT_EXAMPLE_TLV_16_E = 98 , - WIFI_N_EXT_MACTX_PHY_ON_E = 100 , - WIFI_N_EXT_MACTX_EXPECT_CBF_COMMON_E = 102 , - WIFI_N_EXT_MACTX_PHY_DESC_E = 104 , - WIFI_N_EXT_MACTX_L_SIG_B_E = 106 , - WIFI_N_EXT_MACTX_VHT_SIG_A_E = 108 , - WIFI_N_EXT_MACTX_VHT_SIG_B_SU40_E = 110 , - WIFI_N_EXT_MACTX_VHT_SIG_B_SU160_E = 112 , - WIFI_N_EXT_MACTX_VHT_SIG_B_MU40_E = 114 , - WIFI_N_EXT_MACTX_VHT_SIG_B_MU160_E = 116 , - WIFI_N_EXT_MACTX_HE_SIG_A_SU_E = 118 , - WIFI_N_EXT_MACTX_HE_SIG_A_MU_UL_E = 120 , - WIFI_N_EXT_MACTX_HE_SIG_B2_MU_E = 122 , - WIFI_N_EXT_MACTX_DELETE_CV_E = 124 , - WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_E = 126 , - WIFI_N_EXT_MACTX_PHY_NAP_E = 128 , - WIFI_N_EXT_PHYRX_ABORT_ACK_E = 130 , - WIFI_N_EXT_PHYRX_RSSI_LEGACY_E = 132 , - WIFI_N_EXT_PHYRX_USER_INFO_E = 134 , - WIFI_N_EXT_PHYRX_DEBUG_E = 136 , - WIFI_N_EXT_PHYRX_CBF_TRANSFER_ABORT_E = 138 , - WIFI_N_EXT_PHYRX_L_SIG_B_E = 140 , - WIFI_N_EXT_PHYRX_VHT_SIG_A_E = 142 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_SU40_E = 144 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_SU160_E = 146 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_MU40_E = 148 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_MU160_E = 150 , - WIFI_N_EXT_PHYRX_HE_SIG_A_MU_DL_E = 152 , - WIFI_N_EXT_PHYRX_HE_SIG_B1_MU_E = 154 , - WIFI_N_EXT_PHYRX_HE_SIG_B2_OFDMA_E = 156 , - WIFI_N_EXT_PHYRX_COMMON_USER_INFO_E = 158 , - WIFI_N_EXT_COEX_TX_REQ_E = 160 , - WIFI_N_EXT_EXAMPLE_TLV_32_NAME_E = 162 , - WIFI_N_EXT_NA_LENGTH_END_E = 164 , - WIFI_N_EXT_PCU_PPDU_SETUP_DONE_E = 166 , - WIFI_N_EXT_PCU_PPDU_SETUP_INIT_E = 168 , - WIFI_N_EXT_PDG_FES_SETUP_E = 170 , - WIFI_N_EXT_PDG_TX_REQ_E = 172 , - WIFI_N_EXT_MACTX_SWITCH_TO_MAIN_E = 174 , - WIFI_N_EXT_AUX_PPDU_END_E = 176 , - WIFI_N_EXT_TQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 178 , - WIFI_N_EXT_TQM_GEN_MPDUS_STATUS_E = 180 , - WIFI_N_EXT_TQM_REMOVE_MPDU_STATUS_E = 182 , - WIFI_N_EXT_TQM_REMOVE_MSDU_STATUS_E = 184 , - WIFI_N_EXT_TQM_WRITE_CMD_E = 186 , - WIFI_N_EXT_TX_DATA_E = 188 , - WIFI_N_EXT_RX_PACKET_E = 190 , - WIFI_N_EXT_TX_MPDU_END_E = 192 , - WIFI_N_EXT_TX_MSDU_END_E = 194 , - WIFI_N_EXT_TX_SW_MODE_SETUP_E = 196 , - WIFI_N_EXT_TXPCU_USER_BUFFER_STATUS_E = 198 , - WIFI_N_EXT_EXAMPLE_USER_TLV_32_E = 200 , - WIFI_N_EXT_PDG_USER_SETUP_E = 202 , - WIFI_N_EXT_REO_UPDATE_RX_REO_QUEUE_STATUS_E = 204 , - WIFI_N_EXT_TX_RAW_OR_NATIVE_FRAME_SETUP_E = 206 , - WIFI_N_EXT_TX_FLUSH_E = 208 , - WIFI_N_EXT_TQM_WRITE_CMD_STATUS_E = 210 , - WIFI_N_EXT_TQM_GET_MSDU_FLOW_STATS_E = 212 , - WIFI_N_EXT_TX_FES_STATUS_START_E = 214 , - WIFI_N_EXT_TX_FES_STATUS_USER_RESPONSE_E = 216 , - WIFI_N_EXT_RX_TRIG_INFO_E = 218 , - WIFI_N_EXT_RX_FRAME_BITMAP_REQ_E = 220 , - WIFI_N_EXT_COEX_RX_STATUS_E = 222 , - WIFI_N_EXT_RX_PPDU_START_E = 224 , - WIFI_N_EXT_RX_MPDU_START_E = 226 , - WIFI_N_EXT_RX_MSDU_START_E = 228 , - WIFI_N_EXT_RX_ATTENTION_E = 230 , - WIFI_N_EXT_RX_PHY_SLEEP_E = 232 , - WIFI_N_EXT_RX_PEER_ENTRY_E = 234 , - WIFI_N_EXT_RX_RESPONSE_REQUIRED_INFO_E = 236 , - WIFI_N_EXT_TQM_GET_MPDU_QUEUE_STATS_STATUS_E = 238 , - WIFI_N_EXT_TX_CBF_INFO_E = 240 , - WIFI_N_EXT_RX_MPDU_PCU_START_E = 242 , - WIFI_N_EXT_RX_USER_PPDU_END_E = 244 , - WIFI_N_EXT_RX_PREAMBLE_E = 246 , - WIFI_N_EXT_TX_LAST_MPDU_FETCHED_E = 248 , - WIFI_N_EXT_RXPCU_SETUP_E = 250 , - WIFI_N_EXT_TX_FES_STATUS_ACK_OR_BA_E = 252 , - WIFI_N_EXT_COEX_TX_RESP_E = 254 , - WIFI_N_EXT_MACTX_COEX_PHY_CTRL_E = 256 , - WIFI_N_EXT_RESPONSE_START_STATUS_E = 258 , - WIFI_N_EXT_CRYPTO_STATUS_E = 260 , - WIFI_N_EXT_COEX_TX_STOP_CTRL_E = 262 , - WIFI_N_EXT_RX_PPDU_NO_ACK_REPORT_E = 264 , - WIFI_N_EXT_SCHEDULER_COMMAND_STATUS_E = 266 , - WIFI_N_EXT_TX_FES_STATUS_PROT_E = 268 , - WIFI_N_EXT_TX_FES_STATUS_START_PROT_E = 270 , - WIFI_N_EXT_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 272 , - WIFI_N_EXT_WHO_ANCHOR_OFFSET_E = 274 , - WIFI_N_EXT_WHO_CCE_INFO_E = 276 , - WIFI_N_EXT_WHO_COMMIT_DONE_E = 278 , - WIFI_N_EXT_WHO_L2_LLC_E = 280 , - WIFI_N_EXT_WHO_L3_CHECKSUM_E = 282 , - WIFI_N_EXT_WHO_L4_CHECKSUM_E = 284 , - WIFI_N_EXT_WHO_MSDU_E = 286 , - WIFI_N_EXT_WHO_PACKET_DATA_E = 288 , - WIFI_N_EXT_WHO_PPDU_END_E = 290 , - WIFI_N_EXT_WHO_TSO_E = 292 , - WIFI_N_EXT_WHO_WMAC_HEADER_PV1_E = 294 , - WIFI_N_EXT_MPDU_INFO_END_E = 296 , - WIFI_N_EXT_TX_QUEUE_EXTENSION_E = 298 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 300 , - WIFI_N_EXT_TQM_ADD_MSDU_STATUS_E = 302 , - WIFI_N_EXT_WHO_TERMINATE_E = 304 , - WIFI_N_EXT_TX_CV_DATA_E = 306 , - WIFI_N_EXT_PROT_TX_END_E = 308 , - WIFI_N_EXT_TQM_SCH_INSTR_GLOBAL_END_E = 310 , - WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT_E = 312 , - WIFI_N_EXT_REO_FLUSH_QUEUE_E = 314 , - WIFI_N_EXT_REO_UNBLOCK_CACHE_E = 316 , - WIFI_N_EXT_REO_FLUSH_QUEUE_STATUS_E = 318 , - WIFI_N_EXT_REO_UNBLOCK_CACHE_STATUS_E = 320 , - WIFI_N_EXT_TQM_UNBLOCK_CACHE_E = 322 , - WIFI_N_EXT_TQM_UNBLOCK_CACHE_STATUS_E = 324 , - WIFI_N_EXT_RX_STATUS_BUFFER_DONE_E = 326 , - WIFI_N_EXT_SCHEDULER_TXOP_DURATION_TRIGGER_E = 328 , - WIFI_N_EXT_PHYRX_CBF_READ_REQUEST_ACK_E = 330 , - WIFI_N_EXT_TQM_SYNC_CMD_E = 332 , - WIFI_N_EXT_TQM_SYNC_CMD_STATUS_E = 334 , - WIFI_N_EXT_TCC_TQM_WRAPPER_CMD_E = 336 , - WIFI_N_EXT_REO_FLUSH_TIMEOUT_LIST_STATUS_E = 338 , - WIFI_N_EXT_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 340 , - WIFI_N_EXT_RX_PPDU_START_USER_INFO_E = 342 , - WIFI_N_EXT_COEX_MAC_NAP_E = 344 , - WIFI_N_EXT_WHO_MESH_CONTROL_E = 346 , - WIFI_N_EXT_PDG_SW_MODE_BW_END_E = 348 , - WIFI_N_EXT_PDG_WAIT_FOR_PHY_REQUEST_E = 350 , - WIFI_N_EXT_RX_PPDU_START_DROPPED_E = 352 , - WIFI_N_EXT_RX_PPDU_END_STATUS_DONE_DROPPED_E = 354 , - WIFI_N_EXT_RX_MSDU_START_DROPPED_E = 356 , - WIFI_N_EXT_RX_MPDU_END_DROPPED_E = 358 , - WIFI_N_EXT_TXPCU_USER_SETUP_E = 360 , - WIFI_N_EXT_CMD_PART_0_END_E = 362 , - WIFI_N_EXT_SCH_CRITICAL_TLV_REFERENCE_E = 364 , - WIFI_N_EXT_EXAMPLE_TLV_32_E = 366 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 368 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 370 , - WIFI_N_EXT_TQM_2_SCH_MPDU_AVAILABLE_E = 372 , - WIFI_N_EXT_TRIGGER_RESPONSE_TX_DONE_E = 374 , - WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_E = 376 , - WIFI_N_EXT_RECEIVED_RESPONSE_INFO_PART2_E = 378 , - WIFI_N_EXT_TXPCU_PREAMBLE_DONE_E = 380 , - WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_RBO_DROP_E = 382 , - WIFI_N_EXT_MACTX_CLEAR_PREV_TX_INFO_E = 384 , - WIFI_N_EXT_R2R_STATUS_END_E = 386 , - WIFI_N_EXT_END_OF_FLUSH_MARKER_E = 388 , - WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_PUNC_E = 390 , - WIFI_N_EXT_RECEIVED_RESPONSE_USER_15_8_E = 392 , - WIFI_N_EXT_RECEIVED_RESPONSE_USER_31_24_E = 394 , - WIFI_N_EXT_TX_LOOPBACK_SETUP_E = 396 , - WIFI_N_EXT_SCH_WAIT_INSTR_TX_PATH_E = 398 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 400 , - WIFI_N_EXT_TX_WUR_DATA_E = 402 , - WIFI_N_EXT_RX_PPDU_END_MIDDLE_E = 404 , - WIFI_N_EXT_MACTX_BACKOFF_BASED_TRANSMISSION_E = 406 , - WIFI_N_EXT_SRP_INFO_E = 408 , - WIFI_N_EXT_SCHEDULER_SW_MSG_STATUS_E = 410 , - WIFI_N_EXT_RXPCU_SETUP_COMPLETE_E = 412 , - WIFI_N_EXT_MACTX_MCC_SWITCH_BACK_E = 414 , - WIFI_N_EXT_PHYTX_MCC_SWITCH_BACK_ACK_E = 416 , - WIFI_N_EXT_LMR_TX_END_E = 418 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 420 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 422 , - WIFI_N_EXT_SCHEDULER_STATUS_WRAPPER_E = 424 , - WIFI_N_EXT_MACTX___RESERVED_G_0013 = 426 , - WIFI_N_EXT_MACTX_U_SIG_EHT_TB_E = 428 , - WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG1_CFG_E = 430 , - WIFI_N_EXT_PHYRX_U_SIG_EHT_SU_MU_E = 432 , - WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG3_CFG_E = 434 , - WIFI_N_EXT_TX_PUNCTURE_6PATTERNS_SETUP_E = 436 , - WIFI_N_EXT_MACRX_LMR_DATA_REQUEST_E = 438 , - WIFI_N_EXT_PHYRX_LMR_TRANSFER_ABORT_E = 440 , - WIFI_N_EXT_MACRX_SECURE_LTF_SEQ_PTR_E = 442 , - WIFI_N_EXT_MPDU_QUEUE_OVERVIEW_E = 444 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 446 , - WIFI_N_EXT_LMR_MPDU_START_E = 448 , - WIFI_N_EXT_LMR_MPDU_END_E = 450 , - WIFI_N_EXT_RX_FRAME_1K_BITMAP_ACK_E = 452 , - WIFI_N_EXT_TQM_ACKED_1K_MPDU_E = 454 , - WIFI_N_EXT_PHYRX_LOCATION_E = 456 , - WIFI_N_EXT_MLO_TX_NOTIFICATION_MU_E = 458 , - WIFI_N_EXT_MLO_TX_REQ_MU_E = 460 , - WIFI_N_EXT_MLO_RX_NOTIFICATION_E = 462 , - WIFI_N_EXT_MLO_TBTT_NOTIFICATION_E = 464 , - WIFI_N_EXT_MLO_TS_SYNC_MSG_E = 466 , - WIFI_N_EXT_MLO_PDG_FES_SETUP_SU_E = 468 , - WIFI_N_EXT_MPDU_INFO_1K_BITMAP_E = 470 , - WIFI_N_EXT_TX_FRAG_STATE_E = 472 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 474 , - WIFI_N_EXT_MACTX_U_SIG_UHR_SU_MU_E = 476 , - WIFI_N_EXT_TX_MPDU_COMPRESSED_DETAILS_TLV_E = 478 , - WIFI_N_EXT_TX_MSDU_COMPONENT_DETAILS_TLV_E = 480 , - WIFI_N_EXT_SCHEDULER_IU_TEMPLATE_ID_E = 482 , - WIFI_N_EXT_MACTX_EXPECT_NDP_RECEPTION_E = 484 , - WIFI_N_EXT_TX_MPDU_LENGTH_AND_RESTRICTIONS_E = 486 , - WIFI_N_EXT_PHYRX___RESERVED_G_0014 = 488 , - WIFI_N_EXT_PHYTX___RESERVED_G_0014 = 490 , - WIFI_N_EXT_MACTX_EHT_SIG_USR_SU_E = 492 , - WIFI_N_EXT_PHYRX_EHT_SIG_USR_SU_E = 494 , - WIFI_N_EXT_PHYRX_GENERIC_U_SIG_E = 496 , - WIFI_N_EXT_OVERWRITE_RESP_START_E = 498 , - WIFI_N_EXT_OVERWRITE_RESP_FRAME_INFO_E = 500 , - WIFI_N_EXT_RXPCU_EARLY_RX_INDICATION_E = 502 , - WIFI_N_EXT_MACRX_MU_UPLINK_COMMON_SNIFF_E = 504 , - WIFI_N_EXT_MACRX_MU_UPLINK_USER_SEL_SNIFF_E = 506 , - WIFI_N_EXT_MACTX_PREFETCH_CV_DMA_E = 508 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 510 , - WIFI_N_EXT_MACTX_BF_PARAMS_UPDATE_PER_USER_E = 512 , - WIFI_N_EXT_PHYTX_CV_CORR_STATUS_E = 514 , - WIFI_N_EXT_PHYTX_CV_CORR_USER_E = 516 , - WIFI_N_EXT_MACTX_CV_CORR_MAC_INFO_GROUP_E = 518 , - WIFI_N_EXT_MACTX_RX_NOTIFICATION_FOR_PHY_E = 520 , - WIFI_N_EXT_MACTX_MU_UPLINK_COMMON_PER_BW_E = 522 , - WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT2_E = 524 , - WIFI_N_EXT_WSI_DIRECT_MESSAGE_E = 526 , - WIFI_N_EXT_MACTX_EMLSR_SWITCH_E = 528 , - WIFI_N_EXT_PHYTX_EMLSR_SWITCH_ACK_E = 530 , - WIFI_N_EXT_EAD_COMMAND_E = 532 , - WIFI_N_EXT_EAD_LEGACY_INTERRUPT_CONTROL_E = 534 , - WIFI_N_EXT_TPI_ENABLE_RESPONSE_TIMEOUT_E = 536 , - WIFI_N_EXT_TPI_LEGACY_INTERRUPT_CONTROL_E = 538 , - WIFI_N_EXT_TPI_MPDU_CONTINUATION_E = 540 , - WIFI_N_EXT_TPI_SEND_TLV_TO_PHYTX_E = 542 , - WIFI_N_EXT_TPI_STATUS_E = 544 , - WIFI_N_EXT_TPI_TIMESTAMP_STATUS_E = 546 , - WIFI_N_EXT_RPI_LEGACY_STATUS_CONTROL_E = 548 , - WIFI_N_EXT_RPI_STATUS_E = 550 , - WIFI_N_EXT_RPI_TIMESTAMP_STATUS_E = 552 , - WIFI_N_EXT_TCC_PUSH_TRANSMIT_COMMAND_E = 554 , - WIFI_N_EXT_TCC_LEGACY_STATUS_CONTROL_E = 556 , - WIFI_N_EXT_TCC_STATUS_E = 558 , - WIFI_N_EXT_TCC_TIMESTAMP_STATUS_E = 560 , - WIFI_N_EXT_TCC_SCHEDULER_CMD_E = 562 , - WIFI_N_EXT_RPI_NON_DATA_CTLV_44_FROM_PHYRX_E = 564 , - WIFI_N_EXT_RPI_FETCH_INFO_FROM_EXT_MEM_E = 566 , - WIFI_N_EXT_RPI_INIT_CBF_DATA_RESP_ADDR_E = 568 , - WIFI_N_EXT_TPI_SEND_CBF_DATA_TO_PHYTX_E = 570 , - WIFI_N_EXT_TCC_FES_END_MESSAGE_E = 572 , - WIFI_N_EXT_TPI_DISABLE_RESPONSE_TIMEOUT_E = 574 , - WIFI_N_EXT_EAD_MSDU_STATUS_START_E = 576 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_SU_E = 578 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_OFDMA_E = 580 , - WIFI_N_EXT_COEX_BLACKOUT_DETAILS_E = 582 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E = 584 , - WIFI_N_EXT_HDR_CTRL_PROT_MPDU_START_E = 586 , - WIFI_N_EXT_HDR_CTRL_PROT_MPDU_END_E = 588 , - WIFI_N_EXT_HDR_CTRL_PROT_PEER_INFO_E = 590 , - WIFI_N_EXT_MACTX_U_SIG_UHR_ELR_SU_E = 592 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_COBF_E = 594 , - WIFI_N_EXT_SPARE_REUSE_TAG_1_E = 596 , - WIFI_N_EXT_SPARE_REUSE_TAG_3_E = 598 , - WIFI_N_EXT_SPARE_REUSE_TAG_5_E = 600 , - WIFI_N_EXT_SPARE_REUSE_TAG_7_E = 602 , - WIFI_N_EXT_SPARE_REUSE_TAG_9_E = 604 , - WIFI_N_EXT_SPARE_REUSE_TAG_11_E = 606 , - WIFI_N_EXT_SPARE_REUSE_TAG_13_E = 608 , - WIFI_N_EXT_SPARE_REUSE_TAG_15_E = 610 , - WIFI_N_EXT_SPARE_REUSE_TAG_17_E = 612 , - WIFI_N_EXT_SPARE_REUSE_TAG_19_E = 614 , - WIFI_N_EXT_SPARE_REUSE_TAG_21_E = 616 , - WIFI_N_EXT_SPARE_REUSE_TAG_23_E = 618 , - WIFI_N_EXT_SPARE_REUSE_TAG_25_E = 620 , - WIFI_N_EXT_SPARE_REUSE_TAG_27_E = 622 , - WIFI_N_EXT_SPARE_REUSE_TAG_29_E = 624 , - WIFI_N_EXT_SPARE_REUSE_TAG_31_E = 626 , - WIFI_N_EXT_SPARE_REUSE_TAG_33_E = 628 , - WIFI_N_EXT_SPARE_REUSE_TAG_35_E = 630 , - WIFI_N_EXT_SPARE_REUSE_TAG_37_E = 632 , - WIFI_N_EXT_SPARE_REUSE_TAG_39_E = 634 , - WIFI_N_EXT_SPARE_REUSE_TAG_41_E = 636 , - WIFI_N_EXT_SPARE_REUSE_TAG_43_E = 638 , - WIFI_N_EXT_SPARE_REUSE_TAG_45_E = 640 , - WIFI_N_EXT_SPARE_REUSE_TAG_47_E = 642 , - WIFI_N_EXT_SPARE_REUSE_TAG_49_E = 644 , - WIFI_N_EXT_SPARE_REUSE_TAG_51_E = 646 , - WIFI_N_EXT_SPARE_REUSE_TAG_53_E = 648 , - WIFI_N_EXT_SPARE_REUSE_TAG_55_E = 650 , - WIFI_N_EXT_SPARE_REUSE_TAG_57_E = 652 , - WIFI_N_EXT_SPARE_REUSE_TAG_59_E = 654 , - WIFI_N_EXT_SPARE_REUSE_TAG_61_E = 656 , - WIFI_N_EXT_SPARE_REUSE_TAG_63_E = 658 , - WIFI_N_EXT_SPARE_REUSE_TAG_65_E = 660 , - WIFI_N_EXT_SPARE_REUSE_TAG_67_E = 662 , - WIFI_N_EXT_SPARE_REUSE_TAG_69_E = 664 , - WIFI_N_EXT_SPARE_REUSE_TAG_71_E = 666 , - WIFI_N_EXT_SPARE_REUSE_TAG_73_E = 668 , - WIFI_N_EXT_SPARE_REUSE_TAG_75_E = 670 , - WIFI_N_EXT_SPARE_REUSE_TAG_77_E = 672 , - WIFI_N_EXT_SPARE_REUSE_TAG_79_E = 674 , - WIFI_N_EXT_SPARE_REUSE_TAG_81_E = 676 , - WIFI_N_EXT_SPARE_REUSE_TAG_83_E = 678 , - WIFI_N_EXT_SPARE_REUSE_TAG_85_E = 680 , - WIFI_N_EXT_SPARE_REUSE_TAG_87_E = 682 , - WIFI_N_EXT_SPARE_REUSE_TAG_89_E = 684 , - WIFI_N_EXT_SPARE_REUSE_TAG_91_E = 686 , - WIFI_N_EXT_SPARE_REUSE_TAG_93_E = 688 , - WIFI_N_EXT_SPARE_REUSE_TAG_95_E = 690 , - WIFI_N_EXT_SPARE_REUSE_TAG_97_E = 692 , - WIFI_N_EXT_SPARE_REUSE_TAG_99_E = 694 , - WIFI_N_EXT_SPARE_REUSE_TAG_101_E = 696 , - WIFI_N_EXT_SPARE_REUSE_TAG_103_E = 698 , - WIFI_N_EXT_SPARE_REUSE_TAG_105_E = 700 , - WIFI_N_EXT_SPARE_REUSE_TAG_107_E = 702 , - WIFI_N_EXT_SPARE_REUSE_TAG_109_E = 704 , - WIFI_N_EXT_SPARE_REUSE_TAG_111_E = 706 , - WIFI_N_EXT_SPARE_REUSE_TAG_113_E = 708 , - WIFI_N_EXT_SPARE_REUSE_TAG_115_E = 710 , - WIFI_N_EXT_SPARE_REUSE_TAG_117_E = 712 , - WIFI_N_EXT_SPARE_REUSE_TAG_119_E = 714 , - WIFI_N_EXT_SPARE_REUSE_TAG_121_E = 716 , - WIFI_N_EXT_SPARE_REUSE_TAG_123_E = 718 , - WIFI_N_EXT_SPARE_REUSE_TAG_125_E = 720 , - WIFI_N_EXT_SPARE_REUSE_TAG_127_E = 722 , - WIFI_N_EXT_SPARE_REUSE_TAG_129_E = 724 , - WIFI_N_EXT_SPARE_REUSE_TAG_131_E = 726 , - WIFI_N_EXT_SPARE_REUSE_TAG_133_E = 728 , - WIFI_N_EXT_SPARE_REUSE_TAG_135_E = 730 , - WIFI_N_EXT_SPARE_REUSE_TAG_137_E = 732 , - WIFI_N_EXT_SPARE_REUSE_TAG_139_E = 734 , - WIFI_N_EXT_SPARE_REUSE_TAG_141_E = 736 , - WIFI_N_EXT_SPARE_REUSE_TAG_143_E = 738 , - WIFI_N_EXT_SPARE_REUSE_TAG_145_E = 740 , - WIFI_N_EXT_SPARE_REUSE_TAG_147_E = 742 , - WIFI_N_EXT_SPARE_REUSE_TAG_149_E = 744 , - WIFI_N_EXT_SPARE_REUSE_TAG_151_E = 746 , - WIFI_N_EXT_SPARE_REUSE_TAG_153_E = 748 , - WIFI_N_EXT_SPARE_REUSE_TAG_155_E = 750 , - WIFI_N_EXT_SPARE_REUSE_TAG_157_E = 752 , - WIFI_N_EXT_SPARE_REUSE_TAG_159_E = 754 , - WIFI_N_EXT_SPARE_REUSE_TAG_161_E = 756 , - WIFI_N_EXT_SPARE_REUSE_TAG_163_E = 758 , - WIFI_N_EXT_SPARE_REUSE_TAG_165_E = 760 , - WIFI_N_EXT_SPARE_REUSE_TAG_167_E = 762 , - WIFI_N_EXT_SPARE_REUSE_TAG_169_E = 764 , - WIFI_N_EXT_SPARE_REUSE_TAG_171_E = 766 , - WIFI_N_EXT_SPARE_REUSE_TAG_173_E = 768 , - WIFI_N_EXT_SPARE_REUSE_TAG_175_E = 770 , - WIFI_N_EXT_SPARE_REUSE_TAG_177_E = 772 , - WIFI_N_EXT_SPARE_REUSE_TAG_179_E = 774 , - WIFI_N_EXT_SPARE_REUSE_TAG_181_E = 776 , - WIFI_N_EXT_SPARE_REUSE_TAG_183_E = 778 , - WIFI_N_EXT_SPARE_REUSE_TAG_185_E = 780 , - WIFI_N_EXT_SPARE_REUSE_TAG_187_E = 782 , - WIFI_N_EXT_SPARE_REUSE_TAG_189_E = 784 , - WIFI_N_EXT_SPARE_REUSE_TAG_191_E = 786 , - WIFI_N_EXT_SPARE_REUSE_TAG_193_E = 788 , - WIFI_N_EXT_SPARE_REUSE_TAG_195_E = 790 , - WIFI_N_EXT_SPARE_REUSE_TAG_197_E = 792 , - WIFI_N_EXT_SPARE_REUSE_TAG_199_E = 794 , - WIFI_N_EXT_SPARE_REUSE_TAG_201_E = 796 , - WIFI_N_EXT_SPARE_REUSE_TAG_203_E = 798 , - WIFI_N_EXT_SPARE_REUSE_TAG_205_E = 800 , - WIFI_N_EXT_SPARE_REUSE_TAG_207_E = 802 , - WIFI_N_EXT_SPARE_REUSE_TAG_209_E = 804 , - WIFI_N_EXT_SPARE_REUSE_TAG_211_E = 806 , - WIFI_N_EXT_SPARE_REUSE_TAG_213_E = 808 , - WIFI_N_EXT_SPARE_REUSE_TAG_215_E = 810 , - WIFI_N_EXT_SPARE_REUSE_TAG_217_E = 812 , - WIFI_N_EXT_SPARE_REUSE_TAG_219_E = 814 , - WIFI_N_EXT_SPARE_REUSE_TAG_221_E = 816 , - WIFI_N_EXT_SPARE_REUSE_TAG_223_E = 818 , - WIFI_N_EXT_SPARE_REUSE_TAG_225_E = 820 , - WIFI_N_EXT_SPARE_REUSE_TAG_227_E = 822 , - WIFI_N_EXT_SPARE_REUSE_TAG_229_E = 824 , - WIFI_N_EXT_SPARE_REUSE_TAG_231_E = 826 , - WIFI_N_EXT_SPARE_REUSE_TAG_233_E = 828 , - WIFI_N_EXT_SPARE_REUSE_TAG_235_E = 830 , - WIFI_N_EXT_SPARE_REUSE_TAG_237_E = 832 , - WIFI_N_EXT_SPARE_REUSE_TAG_239_E = 834 , - WIFI_N_EXT_SPARE_REUSE_TAG_241_E = 836 , - WIFI_N_EXT_SPARE_REUSE_TAG_243_E = 838 , - WIFI_N_EXT_SPARE_REUSE_TAG_245_E = 840 , - WIFI_N_EXT_SPARE_REUSE_TAG_247_E = 842 , - WIFI_N_EXT_SPARE_REUSE_TAG_249_E = 844 , - WIFI_N_EXT_SPARE_REUSE_TAG_251_E = 846 , - WIFI_N_EXT_SPARE_REUSE_TAG_253_E = 848 , - WIFI_N_EXT_SPARE_REUSE_TAG_255_E = 850 , - WIFI_N_EXT_SPARE_REUSE_TAG_257_E = 852 , - WIFI_N_EXT_SPARE_REUSE_TAG_259_E = 854 , - WIFI_N_EXT_SPARE_REUSE_TAG_261_E = 856 , - WIFI_N_EXT_SPARE_REUSE_TAG_263_E = 858 , - WIFI_N_EXT_SPARE_REUSE_TAG_265_E = 860 , - WIFI_N_EXT_SPARE_REUSE_TAG_267_E = 862 , - WIFI_N_EXT_SPARE_REUSE_TAG_269_E = 864 , - WIFI_N_EXT_SPARE_REUSE_TAG_271_E = 866 , - WIFI_N_EXT_SPARE_REUSE_TAG_273_E = 868 , - WIFI_N_EXT_SPARE_REUSE_TAG_275_E = 870 , - WIFI_N_EXT_SPARE_REUSE_TAG_277_E = 872 , - WIFI_N_EXT_SPARE_REUSE_TAG_279_E = 874 , - WIFI_N_EXT_SPARE_REUSE_TAG_281_E = 876 , - WIFI_N_EXT_SPARE_REUSE_TAG_283_E = 878 , - WIFI_N_EXT_SPARE_REUSE_TAG_285_E = 880 , - WIFI_N_EXT_SPARE_REUSE_TAG_287_E = 882 , - WIFI_N_EXT_SPARE_REUSE_TAG_289_E = 884 , - WIFI_N_EXT_SPARE_REUSE_TAG_291_E = 886 , - WIFI_N_EXT_SPARE_REUSE_TAG_293_E = 888 , - WIFI_N_EXT_SPARE_REUSE_TAG_295_E = 890 , - WIFI_N_EXT_SPARE_REUSE_TAG_297_E = 892 , - WIFI_N_EXT_SPARE_REUSE_TAG_299_E = 894 , - WIFI_N_EXT_SPARE_REUSE_TAG_301_E = 896 , - WIFI_N_EXT_SPARE_REUSE_TAG_303_E = 898 , - WIFI_N_EXT_SPARE_REUSE_TAG_305_E = 900 , - WIFI_N_EXT_SPARE_REUSE_TAG_307_E = 902 , - WIFI_N_EXT_SPARE_REUSE_TAG_309_E = 904 , - WIFI_N_EXT_SPARE_REUSE_TAG_311_E = 906 , - WIFI_N_EXT_SPARE_REUSE_TAG_313_E = 908 , - WIFI_N_EXT_SPARE_REUSE_TAG_315_E = 910 , - WIFI_N_EXT_SPARE_REUSE_TAG_317_E = 912 , - WIFI_N_EXT_SPARE_REUSE_TAG_319_E = 914 , - WIFI_N_EXT_SPARE_REUSE_TAG_321_E = 916 , - WIFI_N_EXT_SPARE_REUSE_TAG_323_E = 918 , - WIFI_N_EXT_SPARE_REUSE_TAG_325_E = 920 , - WIFI_N_EXT_SPARE_REUSE_TAG_327_E = 922 , - WIFI_N_EXT_SPARE_REUSE_TAG_329_E = 924 , - WIFI_N_EXT_SPARE_REUSE_TAG_331_E = 926 , - WIFI_N_EXT_SPARE_REUSE_TAG_333_E = 928 , - WIFI_N_EXT_SPARE_REUSE_TAG_335_E = 930 , - WIFI_N_EXT_SPARE_REUSE_TAG_337_E = 932 , - WIFI_N_EXT_SPARE_REUSE_TAG_339_E = 934 , - WIFI_N_EXT_SPARE_REUSE_TAG_341_E = 936 , - WIFI_N_EXT_SPARE_REUSE_TAG_343_E = 938 , - WIFI_N_EXT_SPARE_REUSE_TAG_345_E = 940 , - WIFI_N_EXT_SPARE_REUSE_TAG_347_E = 942 , - WIFI_N_EXT_SPARE_REUSE_TAG_349_E = 944 , - WIFI_N_EXT_SPARE_REUSE_TAG_351_E = 946 , - WIFI_N_EXT_SPARE_REUSE_TAG_353_E = 948 , - WIFI_N_EXT_SPARE_REUSE_TAG_355_E = 950 , - WIFI_N_EXT_SPARE_REUSE_TAG_357_E = 952 , - WIFI_N_EXT_SPARE_REUSE_TAG_359_E = 954 , - WIFI_N_EXT_SPARE_REUSE_TAG_361_E = 956 , - WIFI_N_EXT_SPARE_REUSE_TAG_363_E = 958 , - WIFI_N_EXT_SPARE_REUSE_TAG_365_E = 960 , - WIFI_N_EXT_SPARE_REUSE_TAG_367_E = 962 , - WIFI_N_EXT_SPARE_REUSE_TAG_369_E = 964 , - WIFI_N_EXT_SPARE_REUSE_TAG_371_E = 966 , - WIFI_N_EXT_SPARE_REUSE_TAG_373_E = 968 , - WIFI_N_EXT_SPARE_REUSE_TAG_375_E = 970 , - WIFI_N_EXT_SPARE_REUSE_TAG_377_E = 972 , - WIFI_N_EXT_SPARE_REUSE_TAG_379_E = 974 , - WIFI_N_EXT_SPARE_REUSE_TAG_381_E = 976 , - WIFI_N_EXT_SPARE_REUSE_TAG_383_E = 978 , - WIFI_N_EXT_SPARE_REUSE_TAG_385_E = 980 , - WIFI_N_EXT_SPARE_REUSE_TAG_387_E = 982 , - WIFI_N_EXT_SPARE_REUSE_TAG_389_E = 984 , - WIFI_N_EXT_SPARE_REUSE_TAG_391_E = 986 , - WIFI_N_EXT_SPARE_REUSE_TAG_393_E = 988 , - WIFI_N_EXT_SPARE_REUSE_TAG_395_E = 990 , - WIFI_N_EXT_SPARE_REUSE_TAG_397_E = 992 , - WIFI_N_EXT_SPARE_REUSE_TAG_399_E = 994 , - WIFI_N_EXT_SPARE_REUSE_TAG_401_E = 996 , - WIFI_N_EXT_SPARE_REUSE_TAG_403_E = 998 , - WIFI_N_EXT_SPARE_REUSE_TAG_405_E = 1000 , - WIFI_N_EXT_SPARE_REUSE_TAG_407_E = 1002 , - WIFI_N_EXT_SPARE_REUSE_TAG_409_E = 1004 , - WIFI_N_EXT_SPARE_REUSE_TAG_411_E = 1006 , - WIFI_N_EXT_SPARE_REUSE_TAG_413_E = 1008 , - WIFI_N_EXT_SPARE_REUSE_TAG_415_E = 1010 , - WIFI_N_EXT_SPARE_REUSE_TAG_417_E = 1012 , - WIFI_N_EXT_SPARE_REUSE_TAG_419_E = 1014 , - WIFI_N_EXT_SPARE_REUSE_TAG_421_E = 1016 , - WIFI_N_EXT_SPARE_REUSE_TAG_423_E = 1018 , - WIFI_N_EXT_SPARE_REUSE_TAG_425_E = 1020 -} non_ext_tlv_tag_def__e; - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tqm2sw_completion_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/tqm2sw_completion_ring.h deleted file mode 100644 index f67deea1f6a1..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tqm2sw_completion_ring.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TQM2SW_COMPLETION_RING_H_ -#define _TQM2SW_COMPLETION_RING_H_ - -#include "tx_rate_stats_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_TQM2SW_COMPLETION_RING 8 - -struct tqm2sw_completion_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_desc_virt_addr_or_addr_info; - uint32_t release_source_module : 3, - cache_id : 1, - reserved_2a : 2, - buffer_or_desc_type : 3, - return_buffer_manager : 4, - tqm_release_reason : 4, - rbm_override_valid : 1, - sw_buffer_cookie_11_0 : 12, - cookie_conversion_status : 1, - tqm_completion_error : 1; - uint32_t tqm_status_number : 24, - transmit_count : 7, - sw_release_details_valid : 1; - uint32_t ack_frame_rssi : 8, - first_msdu : 1, - last_msdu : 1, - fw_tx_notify_frame : 3, - buffer_timestamp : 19; - struct tx_rate_stats_info tx_rate_stats; - uint32_t sw_peer_id : 16, - tid : 4, - sw_buffer_cookie_19_12 : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_desc_virt_addr_or_addr_info; - uint32_t tqm_completion_error : 1, - cookie_conversion_status : 1, - sw_buffer_cookie_11_0 : 12, - rbm_override_valid : 1, - tqm_release_reason : 4, - return_buffer_manager : 4, - buffer_or_desc_type : 3, - reserved_2a : 2, - cache_id : 1, - release_source_module : 3; - uint32_t sw_release_details_valid : 1, - transmit_count : 7, - tqm_status_number : 24; - uint32_t buffer_timestamp : 19, - fw_tx_notify_frame : 3, - last_msdu : 1, - first_msdu : 1, - ack_frame_rssi : 8; - struct tx_rate_stats_info tx_rate_stats; - uint32_t looping_count : 4, - sw_buffer_cookie_19_12 : 8, - tid : 4, - sw_peer_id : 16; -#endif -}; - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define TQM2SW_COMPLETION_RING_CACHE_ID_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_CACHE_ID_LSB 3 -#define TQM2SW_COMPLETION_RING_CACHE_ID_MSB 3 -#define TQM2SW_COMPLETION_RING_CACHE_ID_MASK 0x00000008 - -#define TQM2SW_COMPLETION_RING_RESERVED_2A_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_LSB 4 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_MSB 5 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_MASK 0x00000030 - -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_LSB 6 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MSB 8 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_LSB 9 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MSB 12 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MASK 0x00001e00 - -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_LSB 13 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MSB 16 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MASK 0x0001e000 - -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_LSB 17 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MSB 17 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MASK 0x00020000 - -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_LSB 18 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MSB 29 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 - -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_LSB 30 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MSB 30 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MASK 0x40000000 - -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_LSB 31 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MSB 31 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MASK 0x80000000 - -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_LSB 0 -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MSB 23 -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MASK 0x00ffffff - -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_LSB 24 -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MSB 30 -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MASK 0x7f000000 - -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_LSB 31 -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MSB 31 -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 - -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_LSB 0 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MSB 7 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MASK 0x000000ff - -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_LSB 8 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MSB 8 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MASK 0x00000100 - -#define TQM2SW_COMPLETION_RING_LAST_MSDU_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_LSB 9 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_MSB 9 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_MASK 0x00000200 - -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_LSB 10 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MSB 12 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 - -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_LSB 13 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MSB 31 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MASK 0xffffe000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_LSB 1 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MSB 3 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MSB 16 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0001f000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_LSB 17 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MSB 19 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MASK 0x000e0000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 20 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 20 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00100000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_LSB 21 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MSB 24 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MASK 0x01e00000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_LSB 25 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MSB 28 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MASK 0x1e000000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff - -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_LSB 0 -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MSB 15 -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MASK 0x0000ffff - -#define TQM2SW_COMPLETION_RING_TID_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_TID_LSB 16 -#define TQM2SW_COMPLETION_RING_TID_MSB 19 -#define TQM2SW_COMPLETION_RING_TID_MASK 0x000f0000 - -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_LSB 20 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MSB 27 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 - -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_LSB 28 -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MSB 31 -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_cbf_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_cbf_info.h deleted file mode 100644 index 772b09d7b2a1..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_cbf_info.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_CBF_INFO_H_ -#define _TX_CBF_INFO_H_ - -#define NUM_OF_DWORDS_TX_CBF_INFO 16 - -#define NUM_OF_QWORDS_TX_CBF_INFO 8 - -struct tx_cbf_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sw_peer_id : 16, - pre_cbf_duration : 16; - uint32_t brpoll_info_valid : 1, - trigger_brpoll_info_valid : 1, - npda_info_11ac_valid : 1, - npda_info_11ax_valid : 1, - dot11ax_su_extended : 1, - bandwidth : 3, - brpoll_info : 8, - cbf_response_table_base_index : 8, - peer_index : 3, - pkt_type : 4, - txop_duration_all_ones : 1; - uint32_t trigger_brpoll_common_info_15_0 : 16, - trigger_brpoll_common_info_31_16 : 16; - uint32_t trigger_brpoll_user_info_15_0 : 16, - trigger_brpoll_user_info_31_16 : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t addr3_47_32 : 16, - sta_partial_aid : 11, - __reserved_g_0086 : 1, - reserved_8a : 3, - cbf_resp_pwr_mgmt : 1; - uint32_t group_id : 6, - rssi_comb : 8, - reserved_9a : 2, - vht_ndpa_sta_info : 16; - uint32_t he_eht_sta_info_15_0 : 16, - he_eht_sta_info_31_16 : 16; - uint32_t dot11ax_received_format_indication : 1, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_bss_color_id : 6, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_cp_size : 2, - dot11ax_received_ltf_size : 2, - dot11ax_received_coding : 1, - dot11ax_received_dcm : 1, - dot11ax_received_doppler_indication : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_dl_ul_flag : 1, - reserved_11a : 8; - uint32_t sw_response_frame_length : 16, - sw_response_tlv_from_crypto : 1, - wait_sifs_config_valid : 1, - wait_sifs : 2, - __reserved_g_0005 : 1, - secure : 1, - tb___reserved_g_0005_response_required : 2, - emlsr_main_tlv_if : 1, - reserved_12a : 1, - u_sig_puncture_pattern_encoding : 6; - uint32_t dot11be_puncture_bitmap : 16, - dot11be_response : 1, - punctured_response : 1, - npda_info_11be_valid : 1, - eht_duplicate_mode : 2, - reserved_13a : 11; - uint32_t eht_sta_info_39_32 : 8, - unassociated___reserved_g_0005_peer : 1, - reserved_14a : 23; - uint32_t tlv64_padding : 32; -#else - uint32_t pre_cbf_duration : 16, - sw_peer_id : 16; - uint32_t txop_duration_all_ones : 1, - pkt_type : 4, - peer_index : 3, - cbf_response_table_base_index : 8, - brpoll_info : 8, - bandwidth : 3, - dot11ax_su_extended : 1, - npda_info_11ax_valid : 1, - npda_info_11ac_valid : 1, - trigger_brpoll_info_valid : 1, - brpoll_info_valid : 1; - uint32_t trigger_brpoll_common_info_31_16 : 16, - trigger_brpoll_common_info_15_0 : 16; - uint32_t trigger_brpoll_user_info_31_16 : 16, - trigger_brpoll_user_info_15_0 : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t cbf_resp_pwr_mgmt : 1, - reserved_8a : 3, - __reserved_g_0086 : 1, - sta_partial_aid : 11, - addr3_47_32 : 16; - uint32_t vht_ndpa_sta_info : 16, - reserved_9a : 2, - rssi_comb : 8, - group_id : 6; - uint32_t he_eht_sta_info_31_16 : 16, - he_eht_sta_info_15_0 : 16; - uint32_t reserved_11a : 8, - dot11ax_dl_ul_flag : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_received_doppler_indication : 1, - dot11ax_received_dcm : 1, - dot11ax_received_coding : 1, - dot11ax_received_ltf_size : 2, - dot11ax_received_cp_size : 2, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_bss_color_id : 6, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_format_indication : 1; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_12a : 1, - emlsr_main_tlv_if : 1, - tb___reserved_g_0005_response_required : 2, - secure : 1, - __reserved_g_0005 : 1, - wait_sifs : 2, - wait_sifs_config_valid : 1, - sw_response_tlv_from_crypto : 1, - sw_response_frame_length : 16; - uint32_t reserved_13a : 11, - eht_duplicate_mode : 2, - npda_info_11be_valid : 1, - punctured_response : 1, - dot11be_response : 1, - dot11be_puncture_bitmap : 16; - uint32_t reserved_14a : 23, - unassociated___reserved_g_0005_peer : 1, - eht_sta_info_39_32 : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_SW_PEER_ID_LSB 0 -#define TX_CBF_INFO_SW_PEER_ID_MSB 15 -#define TX_CBF_INFO_SW_PEER_ID_MASK 0x000000000000ffff - -#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 -#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 -#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 32 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 32 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x0000000100000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 33 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 33 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x0000000200000000 - -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 34 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 34 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x0000000400000000 - -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 35 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 35 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x0000000800000000 - -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 36 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 36 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000001000000000 - -#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BANDWIDTH_LSB 37 -#define TX_CBF_INFO_BANDWIDTH_MSB 39 -#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e000000000 - -#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BRPOLL_INFO_LSB 40 -#define TX_CBF_INFO_BRPOLL_INFO_MSB 47 -#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff0000000000 - -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 48 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 55 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff000000000000 - -#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PEER_INDEX_LSB 56 -#define TX_CBF_INFO_PEER_INDEX_MSB 58 -#define TX_CBF_INFO_PEER_INDEX_MASK 0x0700000000000000 - -#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PKT_TYPE_LSB 59 -#define TX_CBF_INFO_PKT_TYPE_MSB 62 -#define TX_CBF_INFO_PKT_TYPE_MASK 0x7800000000000000 - -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 63 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 63 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x000000000000ffff - -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 32 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 47 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 48 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 63 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff000000000000 - -#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR1_31_0_LSB 0 -#define TX_CBF_INFO_ADDR1_31_0_MSB 31 -#define TX_CBF_INFO_ADDR1_31_0_MASK 0x00000000ffffffff - -#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR1_47_32_LSB 32 -#define TX_CBF_INFO_ADDR1_47_32_MSB 47 -#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR2_15_0_LSB 48 -#define TX_CBF_INFO_ADDR2_15_0_MSB 63 -#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff000000000000 - -#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x0000000000000018 -#define TX_CBF_INFO_ADDR2_47_16_LSB 0 -#define TX_CBF_INFO_ADDR2_47_16_MSB 31 -#define TX_CBF_INFO_ADDR2_47_16_MASK 0x00000000ffffffff - -#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000000000000018 -#define TX_CBF_INFO_ADDR3_31_0_LSB 32 -#define TX_CBF_INFO_ADDR3_31_0_MSB 63 -#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff00000000 - -#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_ADDR3_47_32_LSB 0 -#define TX_CBF_INFO_ADDR3_47_32_MSB 15 -#define TX_CBF_INFO_ADDR3_47_32_MASK 0x000000000000ffff - -#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 -#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 -#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x0000000007ff0000 - -#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RESERVED_8A_LSB 28 -#define TX_CBF_INFO_RESERVED_8A_MSB 30 -#define TX_CBF_INFO_RESERVED_8A_MASK 0x0000000070000000 - -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x0000000080000000 - -#define TX_CBF_INFO_GROUP_ID_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_GROUP_ID_LSB 32 -#define TX_CBF_INFO_GROUP_ID_MSB 37 -#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f00000000 - -#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RSSI_COMB_LSB 38 -#define TX_CBF_INFO_RSSI_COMB_MSB 45 -#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc000000000 - -#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RESERVED_9A_LSB 46 -#define TX_CBF_INFO_RESERVED_9A_MSB 47 -#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c00000000000 - -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 48 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 63 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff000000000000 - -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x000000000000ffff - -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 48 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 48 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 49 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 49 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 - -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 55 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 55 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0080000000000000 - -#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_RESERVED_11A_LSB 56 -#define TX_CBF_INFO_RESERVED_11A_MSB 63 -#define TX_CBF_INFO_RESERVED_11A_MASK 0xff00000000000000 - -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x000000000000ffff - -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000000010000 - -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000000020000 - -#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_WAIT_SIFS_LSB 18 -#define TX_CBF_INFO_WAIT_SIFS_MSB 19 -#define TX_CBF_INFO_WAIT_SIFS_MASK 0x00000000000c0000 - -#define TX_CBF_INFO_SECURE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SECURE_LSB 21 -#define TX_CBF_INFO_SECURE_MSB 21 -#define TX_CBF_INFO_SECURE_MASK 0x0000000000200000 - -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB 24 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB 24 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK 0x0000000001000000 - -#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_RESERVED_12A_LSB 25 -#define TX_CBF_INFO_RESERVED_12A_MSB 25 -#define TX_CBF_INFO_RESERVED_12A_MASK 0x0000000002000000 - -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 48 -#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 48 -#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 - -#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 49 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 49 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 - -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 50 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 50 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x0004000000000000 - -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 51 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 52 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x0018000000000000 - -#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_RESERVED_13A_LSB 53 -#define TX_CBF_INFO_RESERVED_13A_MSB 63 -#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe0000000000000 - -#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x00000000000000ff - -#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_RESERVED_14A_LSB 9 -#define TX_CBF_INFO_RESERVED_14A_MSB 31 -#define TX_CBF_INFO_RESERVED_14A_MASK 0x00000000fffffe00 - -#define TX_CBF_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_TLV64_PADDING_LSB 32 -#define TX_CBF_INFO_TLV64_PADDING_MSB 63 -#define TX_CBF_INFO_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_setup.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_setup.h deleted file mode 100644 index 360e373b8019..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_setup.h +++ /dev/null @@ -1,585 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_SETUP_H_ -#define _TX_FES_SETUP_H_ - -#define NUM_OF_DWORDS_TX_FES_SETUP 10 - -#define NUM_OF_QWORDS_TX_FES_SETUP 5 - -struct tx_fes_setup { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t schedule_id : 32; - uint32_t fes_in_11ax_trigger_response_config : 1, - bo_based_tid_aggregation_limit : 4, - __reserved_g_0005 : 1, - expect_i2r_lmr : 1, - transmit_start_reason : 3, - use_alt_power_sr : 1, - static_2_pwr_mode_status : 1, - obss_srg_opport_transmit_status : 1, - srp_based_transmit_status : 1, - obss_pd_based_transmit_status : 1, - puncture_from_all_allowed_modes : 1, - schedule_cmd_ring_id : 5, - fes_control_mode : 2, - number_of_users : 6, - mu_type : 1, - ofdma_triggered_response : 1, - response_to_response_cmd : 1; - uint32_t schedule_try : 4, - reserved_2a : 1, - subband_antenna_selection_en : 1, - txbf : 1, - allow_txop_exceed_in_1st_pkt : 1, - ignore_bw_available : 1, - ignore_tbtt : 1, - static_bandwidth : 3, - set_txop_duration_all_ones : 1, - transmission_contains_mu_rts : 1, - bw_restricted_frames_embedded : 1, - ast_index : 16; - uint32_t cv_id : 8, - trigger_resp_txpdu_ppdu_boundary : 2, - rxpcu_setup_complete_present : 1, - rbo_must_have_data_user_limit : 4, - mu_ndp : 1, - bf_type : 2, - cbf_nc_index_mask : 1, - cbf_nc_index : 3, - cbf_nr_index_mask : 1, - cbf_nr_index : 3, - secure___reserved_g_0005_ista : 1, - ndpa : 1, - wait_sifs : 2, - cbf_feedback_type_mask : 1, - cbf_feedback_type : 1; - uint32_t cbf_sounding_token : 6, - cbf_sounding_token_mask : 1, - cbf_bw_mask : 1, - cbf_bw : 3, - use_static_bw : 1, - coex_nack_count : 5, - sch_tx_burst_ongoing : 1, - gen_tqm_update_mpdu_count_tlv : 1, - rts_tx_over___reserved_g_0016 : 1, - ndp_frame : 3, - optimal_bw_retry_count : 4, - fes_continuation_ratio_threshold : 5; - uint32_t transmit_cca_bitmap : 32; - uint32_t tb___reserved_g_0005 : 1, - __reserved_g_0005_trigger_subtype : 4, - min_cts2self_count : 4, - max_cts2self_count : 4, - wifi_radar_enable : 1, - reserved_6a : 1, - wait_for_chksum_done : 1, - txrx_self_test_enable : 1, - rtt_self_cal_enable : 1, - secure___reserved_g_0005_rsta : 1, - hip_edca_prot_enable : 1, - hip_edca_prot_required : 1, - hip_edca_mini_contention_gap : 8, - last_command_in_burst : 1, - retain_peer_blackout_details : 1, - enable_hw_qos_null : 1; - uint32_t monitor_override_sta_31_0 : 32; - uint32_t monitor_override_sta_36_32 : 5, - enable_qos_null_switch_for_eosp : 1, - __reserved_g_0086 : 1, - __reserved_g_0081 : 1, - __reserved_g_0084 : 2, - __reserved_g_0074 : 4, - cfp_protected_fes : 1, - dot11ax_trigger_frame_embedded : 1, - multiple_triggers_indication : 1, - cmf_uif_length : 4, - npca_switching_cts2self_duration : 8, - reserved_8a : 3; - uint32_t fw2sw_info : 32; -#else - uint32_t schedule_id : 32; - uint32_t response_to_response_cmd : 1, - ofdma_triggered_response : 1, - mu_type : 1, - number_of_users : 6, - fes_control_mode : 2, - schedule_cmd_ring_id : 5, - puncture_from_all_allowed_modes : 1, - obss_pd_based_transmit_status : 1, - srp_based_transmit_status : 1, - obss_srg_opport_transmit_status : 1, - static_2_pwr_mode_status : 1, - use_alt_power_sr : 1, - transmit_start_reason : 3, - expect_i2r_lmr : 1, - __reserved_g_0005 : 1, - bo_based_tid_aggregation_limit : 4, - fes_in_11ax_trigger_response_config : 1; - uint32_t ast_index : 16, - bw_restricted_frames_embedded : 1, - transmission_contains_mu_rts : 1, - set_txop_duration_all_ones : 1, - static_bandwidth : 3, - ignore_tbtt : 1, - ignore_bw_available : 1, - allow_txop_exceed_in_1st_pkt : 1, - txbf : 1, - subband_antenna_selection_en : 1, - reserved_2a : 1, - schedule_try : 4; - uint32_t cbf_feedback_type : 1, - cbf_feedback_type_mask : 1, - wait_sifs : 2, - ndpa : 1, - secure___reserved_g_0005_ista : 1, - cbf_nr_index : 3, - cbf_nr_index_mask : 1, - cbf_nc_index : 3, - cbf_nc_index_mask : 1, - bf_type : 2, - mu_ndp : 1, - rbo_must_have_data_user_limit : 4, - rxpcu_setup_complete_present : 1, - trigger_resp_txpdu_ppdu_boundary : 2, - cv_id : 8; - uint32_t fes_continuation_ratio_threshold : 5, - optimal_bw_retry_count : 4, - ndp_frame : 3, - rts_tx_over___reserved_g_0016 : 1, - gen_tqm_update_mpdu_count_tlv : 1, - sch_tx_burst_ongoing : 1, - coex_nack_count : 5, - use_static_bw : 1, - cbf_bw : 3, - cbf_bw_mask : 1, - cbf_sounding_token_mask : 1, - cbf_sounding_token : 6; - uint32_t transmit_cca_bitmap : 32; - uint32_t enable_hw_qos_null : 1, - retain_peer_blackout_details : 1, - last_command_in_burst : 1, - hip_edca_mini_contention_gap : 8, - hip_edca_prot_required : 1, - hip_edca_prot_enable : 1, - secure___reserved_g_0005_rsta : 1, - rtt_self_cal_enable : 1, - txrx_self_test_enable : 1, - wait_for_chksum_done : 1, - reserved_6a : 1, - wifi_radar_enable : 1, - max_cts2self_count : 4, - min_cts2self_count : 4, - __reserved_g_0005_trigger_subtype : 4, - tb___reserved_g_0005 : 1; - uint32_t monitor_override_sta_31_0 : 32; - uint32_t reserved_8a : 3, - npca_switching_cts2self_duration : 8, - cmf_uif_length : 4, - multiple_triggers_indication : 1, - dot11ax_trigger_frame_embedded : 1, - cfp_protected_fes : 1, - __reserved_g_0074 : 4, - __reserved_g_0084 : 2, - __reserved_g_0081 : 1, - __reserved_g_0086 : 1, - enable_qos_null_switch_for_eosp : 1, - monitor_override_sta_36_32 : 5; - uint32_t fw2sw_info : 32; -#endif -}; - -#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 -#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 -#define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff - -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 - -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 - -#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 -#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 -#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 - -#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 -#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 -#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 - -#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 -#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 -#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 - -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 - -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 - -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 - -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 - -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 - -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 - -#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 -#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 -#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 - -#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 -#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 -#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 - -#define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_MU_TYPE_LSB 61 -#define TX_FES_SETUP_MU_TYPE_MSB 61 -#define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 - -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 - -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 - -#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 -#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 -#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f - -#define TX_FES_SETUP_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RESERVED_2A_LSB 4 -#define TX_FES_SETUP_RESERVED_2A_MSB 4 -#define TX_FES_SETUP_RESERVED_2A_MASK 0x0000000000000010 - -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_LSB 5 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MSB 5 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MASK 0x0000000000000020 - -#define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TXBF_LSB 6 -#define TX_FES_SETUP_TXBF_MSB 6 -#define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 - -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 - -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 - -#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 -#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 -#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 - -#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 -#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 -#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 - -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 - -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 - -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 - -#define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_AST_INDEX_LSB 16 -#define TX_FES_SETUP_AST_INDEX_MSB 31 -#define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 - -#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CV_ID_LSB 32 -#define TX_FES_SETUP_CV_ID_MSB 39 -#define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 - -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 - -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 - -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 - -#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_MU_NDP_LSB 47 -#define TX_FES_SETUP_MU_NDP_MSB 47 -#define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 - -#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_BF_TYPE_LSB 48 -#define TX_FES_SETUP_BF_TYPE_MSB 49 -#define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 - -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 - -#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 -#define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 - -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 - -#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 -#define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 - -#define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_NDPA_LSB 59 -#define TX_FES_SETUP_NDPA_MSB 59 -#define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 - -#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_WAIT_SIFS_LSB 60 -#define TX_FES_SETUP_WAIT_SIFS_MSB 61 -#define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 - -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 - -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 - -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f - -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 - -#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 -#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 -#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 - -#define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_BW_LSB 8 -#define TX_FES_SETUP_CBF_BW_MSB 10 -#define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 - -#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 -#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 -#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 - -#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 -#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 -#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 - -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 - -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 - -#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_NDP_FRAME_LSB 20 -#define TX_FES_SETUP_NDP_FRAME_MSB 22 -#define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000700000 - -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 - -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 - -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 - -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 - -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 - -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 - -#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RESERVED_6A_LSB 14 -#define TX_FES_SETUP_RESERVED_6A_MSB 14 -#define TX_FES_SETUP_RESERVED_6A_MASK 0x0000000000004000 - -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB 15 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB 15 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK 0x0000000000008000 - -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_LSB 16 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MSB 16 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MASK 0x0000000000010000 - -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_LSB 17 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MSB 17 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MASK 0x0000000000020000 - -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_LSB 19 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MSB 19 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MASK 0x0000000000080000 - -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_LSB 20 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MSB 20 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MASK 0x0000000000100000 - -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_LSB 21 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MSB 28 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MASK 0x000000001fe00000 - -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_LSB 29 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MSB 29 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MASK 0x0000000020000000 - -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_LSB 30 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MSB 30 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MASK 0x0000000040000000 - -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB 31 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB 31 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK 0x0000000080000000 - -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 - -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f - -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB 5 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB 5 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK 0x0000000000000020 - -#define TX_FES_SETUP_CFP_PROTECTED_FES_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_CFP_PROTECTED_FES_LSB 14 -#define TX_FES_SETUP_CFP_PROTECTED_FES_MSB 14 -#define TX_FES_SETUP_CFP_PROTECTED_FES_MASK 0x0000000000004000 - -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 15 -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 15 -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000000000008000 - -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_LSB 16 -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_MSB 16 -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_MASK 0x0000000000010000 - -#define TX_FES_SETUP_CMF_UIF_LENGTH_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_CMF_UIF_LENGTH_LSB 17 -#define TX_FES_SETUP_CMF_UIF_LENGTH_MSB 20 -#define TX_FES_SETUP_CMF_UIF_LENGTH_MASK 0x00000000001e0000 - -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_LSB 21 -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_MSB 28 -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_MASK 0x000000001fe00000 - -#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_RESERVED_8A_LSB 29 -#define TX_FES_SETUP_RESERVED_8A_MSB 31 -#define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000e0000000 - -#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_FW2SW_INFO_LSB 32 -#define TX_FES_SETUP_FW2SW_INFO_MSB 63 -#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_1k_ba.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_1k_ba.h deleted file mode 100644 index 4409dc03ac03..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_1k_ba.h +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_1K_BA_H_ -#define _TX_FES_STATUS_1K_BA_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 - -#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 - -struct tx_fes_status_1k_ba { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ack_ba_status_type : 1, - ba_type : 1, - ba_tid : 4, - unexpected_ack_or_ba : 1, - response_timeout : 1, - ack_frame_rssi : 8, - ssn : 12, - reserved_0b : 4; - uint32_t sw_peer_id : 16, - reserved_1a : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; - uint32_t ba_bitmap_287_256 : 32; - uint32_t ba_bitmap_319_288 : 32; - uint32_t ba_bitmap_351_320 : 32; - uint32_t ba_bitmap_383_352 : 32; - uint32_t ba_bitmap_415_384 : 32; - uint32_t ba_bitmap_447_416 : 32; - uint32_t ba_bitmap_479_448 : 32; - uint32_t ba_bitmap_511_480 : 32; - uint32_t ba_bitmap_543_512 : 32; - uint32_t ba_bitmap_575_544 : 32; - uint32_t ba_bitmap_607_576 : 32; - uint32_t ba_bitmap_639_608 : 32; - uint32_t ba_bitmap_671_640 : 32; - uint32_t ba_bitmap_703_672 : 32; - uint32_t ba_bitmap_735_704 : 32; - uint32_t ba_bitmap_767_736 : 32; - uint32_t ba_bitmap_799_768 : 32; - uint32_t ba_bitmap_831_800 : 32; - uint32_t ba_bitmap_863_832 : 32; - uint32_t ba_bitmap_895_864 : 32; - uint32_t ba_bitmap_927_896 : 32; - uint32_t ba_bitmap_959_928 : 32; - uint32_t ba_bitmap_991_960 : 32; - uint32_t ba_bitmap_1023_992 : 32; -#else - uint32_t reserved_0b : 4, - ssn : 12, - ack_frame_rssi : 8, - response_timeout : 1, - unexpected_ack_or_ba : 1, - ba_tid : 4, - ba_type : 1, - ack_ba_status_type : 1; - uint32_t reserved_1a : 16, - sw_peer_id : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; - uint32_t ba_bitmap_287_256 : 32; - uint32_t ba_bitmap_319_288 : 32; - uint32_t ba_bitmap_351_320 : 32; - uint32_t ba_bitmap_383_352 : 32; - uint32_t ba_bitmap_415_384 : 32; - uint32_t ba_bitmap_447_416 : 32; - uint32_t ba_bitmap_479_448 : 32; - uint32_t ba_bitmap_511_480 : 32; - uint32_t ba_bitmap_543_512 : 32; - uint32_t ba_bitmap_575_544 : 32; - uint32_t ba_bitmap_607_576 : 32; - uint32_t ba_bitmap_639_608 : 32; - uint32_t ba_bitmap_671_640 : 32; - uint32_t ba_bitmap_703_672 : 32; - uint32_t ba_bitmap_735_704 : 32; - uint32_t ba_bitmap_767_736 : 32; - uint32_t ba_bitmap_799_768 : 32; - uint32_t ba_bitmap_831_800 : 32; - uint32_t ba_bitmap_863_832 : 32; - uint32_t ba_bitmap_895_864 : 32; - uint32_t ba_bitmap_927_896 : 32; - uint32_t ba_bitmap_959_928 : 32; - uint32_t ba_bitmap_991_960 : 32; - uint32_t ba_bitmap_1023_992 : 32; -#endif -}; - -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 - -#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 -#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 -#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 - -#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 -#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 -#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c - -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 - -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 - -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_SSN_LSB 16 -#define TX_FES_STATUS_1K_BA_SSN_MSB 27 -#define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 - -#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 - -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_ack_or_ba.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_ack_or_ba.h deleted file mode 100644 index 678c639141ba..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_ack_or_ba.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ -#define _TX_FES_STATUS_ACK_OR_BA_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 - -#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5 - -struct tx_fes_status_ack_or_ba { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ack_ba_status_type : 1, - ba_type : 1, - ba_tid : 4, - unexpected_ack_or_ba : 1, - response_timeout : 1, - ack_frame_rssi : 8, - ssn : 12, - reserved_0b : 4; - uint32_t sw_peer_id : 16, - reserved_1a : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; -#else - uint32_t reserved_0b : 4, - ssn : 12, - ack_frame_rssi : 8, - response_timeout : 1, - unexpected_ack_or_ba : 1, - ba_tid : 4, - ba_type : 1, - ack_ba_status_type : 1; - uint32_t reserved_1a : 16, - sw_peer_id : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; -#endif -}; - -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 - -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x0000000000000002 - -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x000000000000003c - -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 - -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 - -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 -#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 -#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x000000000fff0000 - -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0x00000000f0000000 - -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 47 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 48 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff000000000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_end.h deleted file mode 100644 index f1ac77424029..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_end.h +++ /dev/null @@ -1,602 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_END_H_ -#define _TX_FES_STATUS_END_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_END 12 - -#define NUM_OF_QWORDS_TX_FES_STATUS_END 6 - -struct tx_fes_status_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0052 : 1, - __reserved_g_0053 : 1, - __reserved_g_0035 : 1, - __reserved_g_0036 : 1, - __reserved_g_0032 : 1, - __reserved_g_0033 : 1, - __reserved_g_0072 : 1, - __reserved_g_0073 : 1, - __reserved_g_0065 : 1, - __reserved_g_0066 : 1, - __reserved_g_0062 : 1, - __reserved_g_0063 : 1, - global_data_underflow_warning : 1, - global_fes_transmit_result : 4, - cbf_bw_received_valid : 1, - cbf_bw_received : 3, - actual_received_ack_type : 4, - sta_response_count : 6, - more_data_received : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t reserved_after_struct16 : 4, - brp_info_valid : 1, - qos_null_switch_done_for_eosp : 1, - reserved_1a : 5, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - fes_in_11ax_trigger_response_config : 1, - null_delim_inserted_before_mpdus : 1, - only_null_delim_sent : 1; - uint32_t terminate___reserved_g_0005_sequence : 1, - unsolicited_erts_tx : 1, - ects_response_type : 2, - eba_response_type : 2, - response_type : 5, - r2r_end_status_to_follow : 1, - service_cbw : 3, - __reserved_g_0039 : 1, - __reserved_g_0040 : 1, - __reserved_g_0017 : 1, - __reserved_g_0018 : 1, - __reserved_g_0030 : 1, - __reserved_g_0031 : 1, - reserved_2c : 11; - uint32_t beamform_masked_user_bitmap_15_0 : 16, - beamform_masked_user_bitmap_31_16 : 16; - uint32_t cbf_segment_request_mask : 8, - cbf_segment_sent_mask : 8, - highest_achieved_data_null_ratio : 5, - use_alt_power_sr : 1, - static_2_pwr_mode_status : 1, - obss_srg_opport_transmit_status : 1, - srp_based_transmit_status : 1, - obss_pd_based_transmit_status : 1, - beamform_masked_user_bitmap_36_32 : 5, - pdg_mpdu_ready : 1; - uint32_t pdg_mpdu_count : 16, - pdg_est_mpdu_tx_count : 16; - uint32_t pdg_overview_length : 24, - txop_duration : 7, - pdg_dropped_mpdu_warning : 1; - uint32_t packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - packet_extension : 3, - fec_type : 1, - stbc : 1, - num_data_symbols : 16, - ru_size : 4, - reserved_17a : 4; - uint32_t num_ltf_symbols : 3, - ltf_size : 2, - cp_setting : 2, - reserved_18a : 5, - dcm : 1, - ldpc_extra_symbol : 1, - force_extra_symbol : 1, - reserved_18b : 1, - tx_pwr_shared : 8, - tx_pwr_unshared : 8; - uint32_t __reserved_g_0005_active_user_map : 16, - __reserved_g_0005_sent_dummy_tx : 1, - __reserved_g_0005_ftm_frame_sent : 1, - __reserved_g_0067 : 1, - __reserved_g_0068 : 1, - __reserved_g_0037 : 1, - __reserved_g_0038 : 1, - __reserved_g_0069 : 1, - __reserved_g_0070 : 1, - cv_corr_status : 8; - uint32_t current_tx_duration : 16, - reserved_21a : 4, - hw_qos_null_bitmap : 8, - hw_qos_null_setup_missing : 1, - interference : 1, - reserved_21b : 2; - uint32_t reserved_22b : 4, - __reserved_g_0027 : 1, - __reserved_g_0028 : 1, - __reserved_g_0049 : 1, - __reserved_g_0050 : 1, - __reserved_g_0025 : 1, - __reserved_g_0026 : 1, - __reserved_g_0047 : 1, - __reserved_g_0048 : 1, - __reserved_g_0023 : 1, - __reserved_g_0024 : 1, - __reserved_g_0045 : 1, - __reserved_g_0046 : 1, - __reserved_g_0021 : 1, - __reserved_g_0022 : 1, - __reserved_g_0043 : 1, - __reserved_g_0044 : 1, - __reserved_g_0019 : 1, - __reserved_g_0020 : 1, - __reserved_g_0041 : 1, - __reserved_g_0042 : 1, - coex_signaling_status : 8; -#else - uint32_t more_data_received : 1, - sta_response_count : 6, - actual_received_ack_type : 4, - cbf_bw_received : 3, - cbf_bw_received_valid : 1, - global_fes_transmit_result : 4, - global_data_underflow_warning : 1, - __reserved_g_0063 : 1, - __reserved_g_0062 : 1, - __reserved_g_0066 : 1, - __reserved_g_0065 : 1, - __reserved_g_0073 : 1, - __reserved_g_0072 : 1, - __reserved_g_0033 : 1, - __reserved_g_0032 : 1, - __reserved_g_0036 : 1, - __reserved_g_0035 : 1, - __reserved_g_0053 : 1, - __reserved_g_0052 : 1; - uint32_t only_null_delim_sent : 1, - null_delim_inserted_before_mpdus : 1, - fes_in_11ax_trigger_response_config : 1, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - reserved_1a : 5, - qos_null_switch_done_for_eosp : 1, - brp_info_valid : 1, - reserved_after_struct16 : 4; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t reserved_2c : 11, - __reserved_g_0031 : 1, - __reserved_g_0030 : 1, - __reserved_g_0018 : 1, - __reserved_g_0017 : 1, - __reserved_g_0040 : 1, - __reserved_g_0039 : 1, - service_cbw : 3, - r2r_end_status_to_follow : 1, - response_type : 5, - eba_response_type : 2, - ects_response_type : 2, - unsolicited_erts_tx : 1, - terminate___reserved_g_0005_sequence : 1; - uint32_t beamform_masked_user_bitmap_31_16 : 16, - beamform_masked_user_bitmap_15_0 : 16; - uint32_t pdg_mpdu_ready : 1, - beamform_masked_user_bitmap_36_32 : 5, - obss_pd_based_transmit_status : 1, - srp_based_transmit_status : 1, - obss_srg_opport_transmit_status : 1, - static_2_pwr_mode_status : 1, - use_alt_power_sr : 1, - highest_achieved_data_null_ratio : 5, - cbf_segment_sent_mask : 8, - cbf_segment_request_mask : 8; - uint32_t pdg_est_mpdu_tx_count : 16, - pdg_mpdu_count : 16; - uint32_t pdg_dropped_mpdu_warning : 1, - txop_duration : 7, - pdg_overview_length : 24; - uint32_t reserved_17a : 4, - ru_size : 4, - num_data_symbols : 16, - stbc : 1, - fec_type : 1, - packet_extension : 3, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2; - uint32_t tx_pwr_unshared : 8, - tx_pwr_shared : 8, - reserved_18b : 1, - force_extra_symbol : 1, - ldpc_extra_symbol : 1, - dcm : 1, - reserved_18a : 5, - cp_setting : 2, - ltf_size : 2, - num_ltf_symbols : 3; - uint32_t cv_corr_status : 8, - __reserved_g_0070 : 1, - __reserved_g_0069 : 1, - __reserved_g_0038 : 1, - __reserved_g_0037 : 1, - __reserved_g_0068 : 1, - __reserved_g_0067 : 1, - __reserved_g_0005_ftm_frame_sent : 1, - __reserved_g_0005_sent_dummy_tx : 1, - __reserved_g_0005_active_user_map : 16; - uint32_t reserved_21b : 2, - interference : 1, - hw_qos_null_setup_missing : 1, - hw_qos_null_bitmap : 8, - reserved_21a : 4, - current_tx_duration : 16; - uint32_t coex_signaling_status : 8, - __reserved_g_0042 : 1, - __reserved_g_0041 : 1, - __reserved_g_0020 : 1, - __reserved_g_0019 : 1, - __reserved_g_0044 : 1, - __reserved_g_0043 : 1, - __reserved_g_0022 : 1, - __reserved_g_0021 : 1, - __reserved_g_0046 : 1, - __reserved_g_0045 : 1, - __reserved_g_0024 : 1, - __reserved_g_0023 : 1, - __reserved_g_0048 : 1, - __reserved_g_0047 : 1, - __reserved_g_0026 : 1, - __reserved_g_0025 : 1, - __reserved_g_0050 : 1, - __reserved_g_0049 : 1, - __reserved_g_0028 : 1, - __reserved_g_0027 : 1, - reserved_22b : 4; -#endif -}; - -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 - -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 - -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 - -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 - -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 - -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 - -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB 31 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB 31 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 - -#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 -#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 -#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 - -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB 53 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB 53 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK 0x0020000000000000 - -#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_RESERVED_1A_LSB 54 -#define TX_FES_STATUS_END_RESERVED_1A_MSB 58 -#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07c0000000000000 - -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 - -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 - -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 - -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 - -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_LSB 1 -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_MSB 1 -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_MASK 0x0000000000000002 - -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_LSB 2 -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_MSB 3 -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_MASK 0x000000000000000c - -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_LSB 4 -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_MSB 5 -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_MASK 0x0000000000000030 - -#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 6 -#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 10 -#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x00000000000007c0 - -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 11 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 11 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000000800 - -#define TX_FES_STATUS_END_SERVICE_CBW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_SERVICE_CBW_LSB 12 -#define TX_FES_STATUS_END_SERVICE_CBW_MSB 14 -#define TX_FES_STATUS_END_SERVICE_CBW_MASK 0x0000000000007000 - -#define TX_FES_STATUS_END_RESERVED_2C_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESERVED_2C_LSB 21 -#define TX_FES_STATUS_END_RESERVED_2C_MSB 31 -#define TX_FES_STATUS_END_RESERVED_2C_MASK 0x00000000ffe00000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 32 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 47 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 48 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 63 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0xffff000000000000 - -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 0 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 7 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x00000000000000ff - -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 8 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 15 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 16 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 20 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x00000000001f0000 - -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 21 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 21 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0000000000200000 - -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 22 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 22 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0000000000400000 - -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 23 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 23 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000000000800000 - -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 24 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 24 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000000001000000 - -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 25 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 25 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000000002000000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 26 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 30 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x000000007c000000 - -#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 31 -#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 31 -#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 32 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 47 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 48 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 63 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0xffff000000000000 - -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 0 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 23 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x0000000000ffffff - -#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_TXOP_DURATION_LSB 24 -#define TX_FES_STATUS_END_TXOP_DURATION_MSB 30 -#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x000000007f000000 - -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 31 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 31 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 32 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 33 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000300000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 34 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 34 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000400000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 35 -#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 37 -#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000003800000000 - -#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_FEC_TYPE_LSB 38 -#define TX_FES_STATUS_END_FEC_TYPE_MSB 38 -#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000004000000000 - -#define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_STBC_LSB 39 -#define TX_FES_STATUS_END_STBC_MSB 39 -#define TX_FES_STATUS_END_STBC_MASK 0x0000008000000000 - -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 40 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 55 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x00ffff0000000000 - -#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_RU_SIZE_LSB 56 -#define TX_FES_STATUS_END_RU_SIZE_MSB 59 -#define TX_FES_STATUS_END_RU_SIZE_MASK 0x0f00000000000000 - -#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_RESERVED_17A_LSB 60 -#define TX_FES_STATUS_END_RESERVED_17A_MSB 63 -#define TX_FES_STATUS_END_RESERVED_17A_MASK 0xf000000000000000 - -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 0 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 2 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000000000007 - -#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_LTF_SIZE_LSB 3 -#define TX_FES_STATUS_END_LTF_SIZE_MSB 4 -#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000000000000018 - -#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_CP_SETTING_LSB 5 -#define TX_FES_STATUS_END_CP_SETTING_MSB 6 -#define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000000000000060 - -#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_RESERVED_18A_LSB 7 -#define TX_FES_STATUS_END_RESERVED_18A_MSB 11 -#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x0000000000000f80 - -#define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_DCM_LSB 12 -#define TX_FES_STATUS_END_DCM_MSB 12 -#define TX_FES_STATUS_END_DCM_MASK 0x0000000000001000 - -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 13 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 13 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000000000002000 - -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 14 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 14 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000000000004000 - -#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_RESERVED_18B_LSB 15 -#define TX_FES_STATUS_END_RESERVED_18B_MSB 15 -#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000000000008000 - -#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 16 -#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 23 -#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x0000000000ff0000 - -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 24 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 31 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0x00000000ff000000 - -#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 56 -#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 63 -#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0xff00000000000000 - -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 0 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 15 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x000000000000ffff - -#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_21A_LSB 16 -#define TX_FES_STATUS_END_RESERVED_21A_MSB 19 -#define TX_FES_STATUS_END_RESERVED_21A_MASK 0x00000000000f0000 - -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB 20 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB 27 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK 0x000000000ff00000 - -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB 28 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB 28 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK 0x0000000010000000 - -#define TX_FES_STATUS_END_INTERFERENCE_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_INTERFERENCE_LSB 29 -#define TX_FES_STATUS_END_INTERFERENCE_MSB 29 -#define TX_FES_STATUS_END_INTERFERENCE_MASK 0x0000000020000000 - -#define TX_FES_STATUS_END_RESERVED_21B_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_21B_LSB 30 -#define TX_FES_STATUS_END_RESERVED_21B_MSB 31 -#define TX_FES_STATUS_END_RESERVED_21B_MASK 0x00000000c0000000 - -#define TX_FES_STATUS_END_RESERVED_22B_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_22B_LSB 32 -#define TX_FES_STATUS_END_RESERVED_22B_MSB 35 -#define TX_FES_STATUS_END_RESERVED_22B_MASK 0x0000000f00000000 - -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_LSB 56 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MSB 63 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_prot.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_prot.h deleted file mode 100644 index 702cc1add940..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_prot.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_PROT_H_ -#define _TX_FES_STATUS_PROT_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 4 - -#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 2 - -struct tx_fes_status_prot { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t success : 1, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - reserved_0 : 19, - pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5; - uint32_t frame_type : 2, - frame_subtype : 4, - rx_pwr_mgmt : 1, - status : 1, - duration_field : 16, - reserved_1a : 2, - agc_cbw : 3, - service_cbw : 3; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t reserved_2a : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4, - reserved_0 : 19, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - success : 1; - uint32_t service_cbw : 3, - agc_cbw : 3, - reserved_1a : 2, - duration_field : 16, - status : 1, - rx_pwr_mgmt : 1, - frame_subtype : 4, - frame_type : 2; - uint32_t reserved_2a : 16; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 -#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 -#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 - -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 - -#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 -#define TX_FES_STATUS_PROT_RESERVED_0_MSB 21 -#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000003ffff8 - -#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 22 -#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 25 -#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000003c00000 - -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 26 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 26 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000004000000 - -#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RATE_MCS_LSB 27 -#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 -#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f8000000 - -#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 -#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 -#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 - -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 - -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 - -#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_STATUS_LSB 39 -#define TX_FES_STATUS_PROT_STATUS_MSB 39 -#define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 - -#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 -#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 -#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 - -#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 -#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 -#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 - -#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 -#define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 -#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 - -#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 -#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 -#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00000000000000ff - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x0000000000003f00 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x000000000000c000 - -#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_RESERVED_2A_LSB 16 -#define TX_FES_STATUS_PROT_RESERVED_2A_MSB 31 -#define TX_FES_STATUS_PROT_RESERVED_2A_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_PROT_TLV64_PADDING_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_PROT_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_PROT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start.h deleted file mode 100644 index bc8e06ec59fb..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_H_ -#define _TX_FES_STATUS_START_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START 2 - -struct tx_fes_status_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t schedule_id : 32; - uint32_t reserved_1a : 8, - transmit_start_reason : 3, - disabled_user_bitmap_36_32 : 5, - schedule_cmd_ring_id : 5, - fes_control_mode : 2, - schedule_try : 4, - medium_prot_type : 3, - reserved_1b : 2; - uint32_t optimal_bw_try_count : 4, - number_of_users : 7, - coex_nack_count : 5, - cca_ed0 : 16; - uint32_t disabled_user_bitmap_31_0 : 32; -#else - uint32_t schedule_id : 32; - uint32_t reserved_1b : 2, - medium_prot_type : 3, - schedule_try : 4, - fes_control_mode : 2, - schedule_cmd_ring_id : 5, - disabled_user_bitmap_36_32 : 5, - transmit_start_reason : 3, - reserved_1a : 8; - uint32_t cca_ed0 : 16, - coex_nack_count : 5, - number_of_users : 7, - optimal_bw_try_count : 4; - uint32_t disabled_user_bitmap_31_0 : 32; -#endif -}; - -#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 -#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 -#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_RESERVED_1A_LSB 32 -#define TX_FES_STATUS_START_RESERVED_1A_MSB 39 -#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 40 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 42 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x0000070000000000 - -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 43 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 47 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f80000000000 - -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 48 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 52 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 - -#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 53 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 54 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x0060000000000000 - -#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 55 -#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 58 -#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x0780000000000000 - -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 59 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 61 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x3800000000000000 - -#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_RESERVED_1B_LSB 62 -#define TX_FES_STATUS_START_RESERVED_1B_MSB 63 -#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc000000000000000 - -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x000000000000000f - -#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x00000000000007f0 - -#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x000000000000f800 - -#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_CCA_ED0_LSB 16 -#define TX_FES_STATUS_START_CCA_ED0_MSB 31 -#define TX_FES_STATUS_START_CCA_ED0_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 32 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 63 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_ppdu.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_ppdu.h deleted file mode 100644 index a87b3b0a0ccc..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_ppdu.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_PPDU_H_ -#define _TX_FES_STATUS_START_PPDU_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 3 - -struct tx_fes_status_start_ppdu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ppdu_timestamp_lower_32 : 32; - uint32_t ppdu_timestamp_upper_32 : 32; - uint32_t subband_mask : 16, - ndp_frame : 3, - reserved_2b : 1, - coex_based_tx_bw : 3, - coex_based_ant_mask : 8, - reserved_2c : 1; - uint32_t coex_based_tx_pwr_shared_ant : 8, - coex_based_tx_pwr_ant : 8, - concurrent_bt_tx : 1, - concurrent_wlan_tx : 1, - concurrent_wan_tx : 1, - concurrent_wan_rx : 1, - coex_pwr_reduction_bt : 1, - coex_pwr_reduction_wlan : 1, - coex_pwr_reduction_wan : 1, - coex_result_alt_based : 1, - request_packet_bw : 3, - response_type : 5; - uint32_t concurrent_rx_activity_tracker1 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - coex_pwr_reduction_wan_ratid1 : 1, - reserved_4a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t ppdu_timestamp_lower_32 : 32; - uint32_t ppdu_timestamp_upper_32 : 32; - uint32_t reserved_2c : 1, - coex_based_ant_mask : 8, - coex_based_tx_bw : 3, - reserved_2b : 1, - ndp_frame : 3, - subband_mask : 16; - uint32_t response_type : 5, - request_packet_bw : 3, - coex_result_alt_based : 1, - coex_pwr_reduction_wan : 1, - coex_pwr_reduction_wlan : 1, - coex_pwr_reduction_bt : 1, - concurrent_wan_rx : 1, - concurrent_wan_tx : 1, - concurrent_wlan_tx : 1, - concurrent_bt_tx : 1, - coex_based_tx_pwr_ant : 8, - coex_based_tx_pwr_shared_ant : 8; - uint32_t reserved_4a : 18, - coex_pwr_reduction_wan_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker1 : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 32 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 63 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x000000000000ffff - -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 18 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x0000000000070000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 19 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x0000000000080000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x0000000000700000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x0000000080000000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 32 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 39 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 40 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 47 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff0000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 48 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 48 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x0001000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 49 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 49 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 50 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 50 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x0004000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 51 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 51 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x0008000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 52 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 52 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 53 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 53 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 54 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 54 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 55 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 55 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x0080000000000000 - -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 56 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 58 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x0700000000000000 - -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 59 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 63 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf800000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB 0 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB 0 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK 0x0000000000000001 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB 1 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB 1 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK 0x0000000000000002 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB 2 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB 2 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK 0x0000000000000004 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB 3 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB 3 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK 0x0000000000000008 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB 4 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB 4 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK 0x0000000000000010 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB 5 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB 5 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK 0x0000000000000020 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB 6 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB 6 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK 0x0000000000000040 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB 7 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB 7 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK 0x0000000000000080 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB 8 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB 8 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK 0x0000000000000100 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB 9 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB 9 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK 0x0000000000000200 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB 10 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB 10 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK 0x0000000000000400 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_LSB 11 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MSB 11 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MASK 0x0000000000000800 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_LSB 12 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MSB 12 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MASK 0x0000000000001000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_LSB 13 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MSB 13 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MASK 0x0000000000002000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_LSB 14 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MASK 0x00000000ffffc000 - -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_prot.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_prot.h deleted file mode 100644 index aca9ac5eb28b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_prot.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_PROT_H_ -#define _TX_FES_STATUS_START_PROT_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 3 - -struct tx_fes_status_start_prot { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t prot_timestamp_lower_32 : 32; - uint32_t prot_timestamp_upper_32 : 32; - uint32_t subband_mask : 16, - reserved_2b : 4, - prot_coex_based_tx_bw : 3, - prot_coex_based_ant_mask : 8, - prot_coex_result_alt_based : 1; - uint32_t prot_coex_tx_pwr_shared_ant : 8, - prot_coex_tx_pwr_ant : 8, - prot_concurrent_bt_tx : 1, - prot_concurrent_wlan_tx : 1, - prot_concurrent_wan_tx : 1, - prot_concurrent_wan_rx : 1, - prot_coex_pwr_reduction_bt : 1, - prot_coex_pwr_reduction_wlan : 1, - prot_coex_pwr_reduction_wan : 1, - prot_request_packet_bw : 3, - response_type : 5, - reserved_3a : 1; - uint32_t concurrent_rx_activity_tracker1 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - coex_pwr_reduction_wan_ratid1 : 1, - reserved_4a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t prot_timestamp_lower_32 : 32; - uint32_t prot_timestamp_upper_32 : 32; - uint32_t prot_coex_result_alt_based : 1, - prot_coex_based_ant_mask : 8, - prot_coex_based_tx_bw : 3, - reserved_2b : 4, - subband_mask : 16; - uint32_t reserved_3a : 1, - response_type : 5, - prot_request_packet_bw : 3, - prot_coex_pwr_reduction_wan : 1, - prot_coex_pwr_reduction_wlan : 1, - prot_coex_pwr_reduction_bt : 1, - prot_concurrent_wan_rx : 1, - prot_concurrent_wan_tx : 1, - prot_concurrent_wlan_tx : 1, - prot_concurrent_bt_tx : 1, - prot_coex_tx_pwr_ant : 8, - prot_coex_tx_pwr_shared_ant : 8; - uint32_t reserved_4a : 18, - coex_pwr_reduction_wan_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker1 : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 32 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 63 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x000000000000ffff - -#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x00000000000f0000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x0000000000700000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x0000000080000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 32 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 39 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 40 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 47 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff0000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 48 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 48 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x0001000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 49 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 49 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 50 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 50 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x0004000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 51 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 51 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x0008000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 52 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 52 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 53 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 53 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 54 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 54 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 55 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 57 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x0380000000000000 - -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 58 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 62 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c00000000000000 - -#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 63 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 63 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x8000000000000000 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB 0 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB 0 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK 0x0000000000000001 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB 1 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB 1 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK 0x0000000000000002 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB 2 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB 2 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK 0x0000000000000004 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB 3 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB 3 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK 0x0000000000000008 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB 4 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB 4 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK 0x0000000000000010 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB 5 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB 5 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK 0x0000000000000020 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB 6 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB 6 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK 0x0000000000000040 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB 7 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB 7 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK 0x0000000000000080 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB 8 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB 8 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK 0x0000000000000100 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB 9 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB 9 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK 0x0000000000000200 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB 10 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB 10 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK 0x0000000000000400 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_LSB 11 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MSB 11 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MASK 0x0000000000000800 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_LSB 12 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MSB 12 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MASK 0x0000000000001000 - -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_LSB 13 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MSB 13 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MASK 0x0000000000002000 - -#define TX_FES_STATUS_START_PROT_RESERVED_4A_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_LSB 14 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_MSB 31 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_MASK 0x00000000ffffc000 - -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_ppdu.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_ppdu.h deleted file mode 100644 index dad9a040ff46..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_ppdu.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_USER_PPDU_H_ -#define _TX_FES_STATUS_USER_PPDU_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 - -struct tx_fes_status_user_ppdu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t underflow_mpdu_count : 9, - data_underflow_warning : 2, - bw_drop_underflow_warning : 1, - qc_eosp_setting : 1, - mpdu_tx_count : 11, - user_blocked : 1, - pre_trig_response_delim_count : 7; - uint32_t underflow_byte_count : 16, - coex_abort_mpdu_count_valid : 1, - coex_abort_mpdu_count : 9, - transmitted_tid : 4, - txdma_dropped_mpdu_warning : 1, - cv_corr_user_valid_in_phy : 1; - uint32_t duration : 16, - num_eof_delim_added : 16; - uint32_t psdu_octet : 24, - qos_buf_state : 8; - uint32_t num_null_delim_added : 22, - fc_more_data_setting : 1, - fc_pwr_mgt_setting : 1, - nss : 3, - mcs : 5; - uint32_t ht_control : 32; -#else - uint32_t pre_trig_response_delim_count : 7, - user_blocked : 1, - mpdu_tx_count : 11, - qc_eosp_setting : 1, - bw_drop_underflow_warning : 1, - data_underflow_warning : 2, - underflow_mpdu_count : 9; - uint32_t cv_corr_user_valid_in_phy : 1, - txdma_dropped_mpdu_warning : 1, - transmitted_tid : 4, - coex_abort_mpdu_count : 9, - coex_abort_mpdu_count_valid : 1, - underflow_byte_count : 16; - uint32_t num_eof_delim_added : 16, - duration : 16; - uint32_t qos_buf_state : 8, - psdu_octet : 24; - uint32_t mcs : 5, - nss : 3, - fc_pwr_mgt_setting : 1, - fc_more_data_setting : 1, - num_null_delim_added : 22; - uint32_t ht_control : 32; -#endif -}; - -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff - -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 - -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 - -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 - -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 13 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ffe000 - -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 - -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 - -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 - -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 - -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 - -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 - -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 63 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 63 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x8000000000000000 - -#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 -#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 -#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff - -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 - -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 - -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff - -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 22 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 22 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000400000 - -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 23 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 23 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000800000 - -#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_NSS_LSB 24 -#define TX_FES_STATUS_USER_PPDU_NSS_MSB 26 -#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x0000000007000000 - -#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_MCS_LSB 27 -#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 -#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f8000000 - -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_response.h deleted file mode 100644 index dea7df35887f..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_response.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ -#define _TX_FES_STATUS_USER_RESPONSE_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 - -#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1 - -struct tx_fes_status_user_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t fes_transmit_result : 4, - reserved_0 : 23, - overwritten_blackout_window_bitmap : 4, - mic_overwritten : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t pre_padding_fcs_overwritten : 1, - reserved_after_struct16 : 15; -#else - uint32_t mic_overwritten : 1, - overwritten_blackout_window_bitmap : 4, - reserved_0 : 23, - fes_transmit_result : 4; - uint32_t reserved_after_struct16 : 15, - pre_padding_fcs_overwritten : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; -#endif -}; - -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x000000000000000f - -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 26 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0x0000000007fffff0 - -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_LSB 27 -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MSB 30 -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MASK 0x0000000078000000 - -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_LSB 31 -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_MSB 31 -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_MASK 0x0000000080000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_LSB 48 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MSB 48 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MASK 0x0001000000000000 - -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 49 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 63 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xfffe000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_flush_req.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_flush_req.h deleted file mode 100644 index af502ec619eb..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_flush_req.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FLUSH_REQ_H_ -#define _TX_FLUSH_REQ_H_ - -#define NUM_OF_DWORDS_TX_FLUSH_REQ 2 - -#define NUM_OF_QWORDS_TX_FLUSH_REQ 1 - -struct tx_flush_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t flush_req_reason : 8, - phytx_abort_reason : 8, - flush_req_user_number_or_link_id : 6, - mlo_abort_reason : 5, - reserved_0a : 5; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 5, - mlo_abort_reason : 5, - flush_req_user_number_or_link_id : 6, - phytx_abort_reason : 8, - flush_req_reason : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff - -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00 - -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000 - -#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000 - -#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 -#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 -#define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000 - -#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_TLV64_PADDING_LSB 32 -#define TX_FLUSH_REQ_TLV64_PADDING_MSB 63 -#define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_mpdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_mpdu_start.h deleted file mode 100644 index 1a0c370d2963..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_mpdu_start.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MPDU_START_H_ -#define _TX_MPDU_START_H_ - -#define NUM_OF_DWORDS_TX_MPDU_START 10 - -#define NUM_OF_QWORDS_TX_MPDU_START 5 - -struct tx_mpdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mpdu_length : 14, - frame_not_from_tqm : 1, - vht_control_present : 1, - mpdu_header_length : 8, - retry_count : 7, - wds : 1; - uint32_t pn_31_0 : 32; - uint32_t pn_47_32 : 16, - mpdu_sequence_number : 12, - raw_already_encrypted : 1, - frame_type : 2, - txdma_dropped_mpdu_warning : 1; - uint32_t iv_byte_0 : 8, - iv_byte_1 : 8, - iv_byte_2 : 8, - iv_byte_3 : 8; - uint32_t iv_byte_4 : 8, - iv_byte_5 : 8, - iv_byte_6 : 8, - iv_byte_7 : 8; - uint32_t iv_byte_8 : 8, - iv_byte_9 : 8, - iv_byte_10 : 8, - iv_byte_11 : 8; - uint32_t iv_byte_12 : 8, - iv_byte_13 : 8, - iv_byte_14 : 8, - iv_byte_15 : 8; - uint32_t iv_byte_16 : 8, - iv_byte_17 : 8, - iv_len : 5, - icv_len : 5, - vht_control_offset : 6; - uint32_t mpdu_type : 1, - transmit_bw_restriction : 1, - allowed_transmit_bw : 4, - tx_notify_frame : 3, - frame_subtype : 4, - reserved_8a : 19; - uint32_t tlv64_padding : 32; -#else - uint32_t wds : 1, - retry_count : 7, - mpdu_header_length : 8, - vht_control_present : 1, - frame_not_from_tqm : 1, - mpdu_length : 14; - uint32_t pn_31_0 : 32; - uint32_t txdma_dropped_mpdu_warning : 1, - frame_type : 2, - raw_already_encrypted : 1, - mpdu_sequence_number : 12, - pn_47_32 : 16; - uint32_t iv_byte_3 : 8, - iv_byte_2 : 8, - iv_byte_1 : 8, - iv_byte_0 : 8; - uint32_t iv_byte_7 : 8, - iv_byte_6 : 8, - iv_byte_5 : 8, - iv_byte_4 : 8; - uint32_t iv_byte_11 : 8, - iv_byte_10 : 8, - iv_byte_9 : 8, - iv_byte_8 : 8; - uint32_t iv_byte_15 : 8, - iv_byte_14 : 8, - iv_byte_13 : 8, - iv_byte_12 : 8; - uint32_t vht_control_offset : 6, - icv_len : 5, - iv_len : 5, - iv_byte_17 : 8, - iv_byte_16 : 8; - uint32_t reserved_8a : 19, - frame_subtype : 4, - tx_notify_frame : 3, - allowed_transmit_bw : 4, - transmit_bw_restriction : 1, - mpdu_type : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 -#define TX_MPDU_START_MPDU_LENGTH_LSB 0 -#define TX_MPDU_START_MPDU_LENGTH_MSB 13 -#define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff - -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 - -#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 - -#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 -#define TX_MPDU_START_RETRY_COUNT_LSB 24 -#define TX_MPDU_START_RETRY_COUNT_MSB 30 -#define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 - -#define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 -#define TX_MPDU_START_WDS_LSB 31 -#define TX_MPDU_START_WDS_MSB 31 -#define TX_MPDU_START_WDS_MASK 0x0000000080000000 - -#define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 -#define TX_MPDU_START_PN_31_0_LSB 32 -#define TX_MPDU_START_PN_31_0_MSB 63 -#define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 - -#define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 -#define TX_MPDU_START_PN_47_32_LSB 0 -#define TX_MPDU_START_PN_47_32_MSB 15 -#define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff - -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 - -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 - -#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 -#define TX_MPDU_START_FRAME_TYPE_LSB 29 -#define TX_MPDU_START_FRAME_TYPE_MSB 30 -#define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 - -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 - -#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_0_LSB 32 -#define TX_MPDU_START_IV_BYTE_0_MSB 39 -#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_1_LSB 40 -#define TX_MPDU_START_IV_BYTE_1_MSB 47 -#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_2_LSB 48 -#define TX_MPDU_START_IV_BYTE_2_MSB 55 -#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 - -#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_3_LSB 56 -#define TX_MPDU_START_IV_BYTE_3_MSB 63 -#define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 - -#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_4_LSB 0 -#define TX_MPDU_START_IV_BYTE_4_MSB 7 -#define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff - -#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_5_LSB 8 -#define TX_MPDU_START_IV_BYTE_5_MSB 15 -#define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 - -#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_6_LSB 16 -#define TX_MPDU_START_IV_BYTE_6_MSB 23 -#define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_7_LSB 24 -#define TX_MPDU_START_IV_BYTE_7_MSB 31 -#define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 - -#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_8_LSB 32 -#define TX_MPDU_START_IV_BYTE_8_MSB 39 -#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_9_LSB 40 -#define TX_MPDU_START_IV_BYTE_9_MSB 47 -#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_10_LSB 48 -#define TX_MPDU_START_IV_BYTE_10_MSB 55 -#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 - -#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_11_LSB 56 -#define TX_MPDU_START_IV_BYTE_11_MSB 63 -#define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 - -#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_12_LSB 0 -#define TX_MPDU_START_IV_BYTE_12_MSB 7 -#define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff - -#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_13_LSB 8 -#define TX_MPDU_START_IV_BYTE_13_MSB 15 -#define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 - -#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_14_LSB 16 -#define TX_MPDU_START_IV_BYTE_14_MSB 23 -#define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_15_LSB 24 -#define TX_MPDU_START_IV_BYTE_15_MSB 31 -#define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 - -#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_16_LSB 32 -#define TX_MPDU_START_IV_BYTE_16_MSB 39 -#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_17_LSB 40 -#define TX_MPDU_START_IV_BYTE_17_MSB 47 -#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_LEN_LSB 48 -#define TX_MPDU_START_IV_LEN_MSB 52 -#define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 - -#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 -#define TX_MPDU_START_ICV_LEN_LSB 53 -#define TX_MPDU_START_ICV_LEN_MSB 57 -#define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 - -#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 - -#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 -#define TX_MPDU_START_MPDU_TYPE_LSB 0 -#define TX_MPDU_START_MPDU_TYPE_MSB 0 -#define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 - -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 - -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c - -#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 -#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 -#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 - -#define TX_MPDU_START_FRAME_SUBTYPE_OFFSET 0x0000000000000020 -#define TX_MPDU_START_FRAME_SUBTYPE_LSB 9 -#define TX_MPDU_START_FRAME_SUBTYPE_MSB 12 -#define TX_MPDU_START_FRAME_SUBTYPE_MASK 0x0000000000001e00 - -#define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_MPDU_START_RESERVED_8A_LSB 13 -#define TX_MPDU_START_RESERVED_8A_MSB 31 -#define TX_MPDU_START_RESERVED_8A_MASK 0x00000000ffffe000 - -#define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TLV64_PADDING_LSB 32 -#define TX_MPDU_START_TLV64_PADDING_MSB 63 -#define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_extension.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_extension.h deleted file mode 100644 index f8da5593497b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_extension.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MSDU_EXTENSION_H_ -#define _TX_MSDU_EXTENSION_H_ - -#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 - -struct tx_msdu_extension { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tso_enable : 1, - reserved_0a : 6, - tcp_flag : 9, - tcp_flag_mask : 9, - reserved_0b : 7; - uint32_t l2_length : 16, - ip_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t ip_identification : 16, - udp_length : 16; - uint32_t checksum_offset : 14, - partial_checksum_en : 1, - reserved_4a : 1, - payload_start_offset : 14, - reserved_4b : 2; - uint32_t payload_end_offset : 14, - reserved_5a : 2, - wds : 1, - reserved_5b : 15; - uint32_t buf0_ptr_31_0 : 32; - uint32_t buf0_ptr_39_32 : 8, - reserved_7a : 8, - buf0_len : 16; - uint32_t buf1_ptr_31_0 : 32; - uint32_t buf1_ptr_39_32 : 8, - reserved_9a : 8, - buf1_len : 16; - uint32_t buf2_ptr_31_0 : 32; - uint32_t buf2_ptr_39_32 : 8, - reserved_11a : 8, - buf2_len : 16; - uint32_t buf3_ptr_31_0 : 32; - uint32_t buf3_ptr_39_32 : 8, - reserved_13a : 8, - buf3_len : 16; - uint32_t buf4_ptr_31_0 : 32; - uint32_t buf4_ptr_39_32 : 8, - reserved_15a : 8, - buf4_len : 16; - uint32_t buf5_ptr_31_0 : 32; - uint32_t buf5_ptr_39_32 : 8, - reserved_17a : 8, - buf5_len : 16; -#else - uint32_t reserved_0b : 7, - tcp_flag_mask : 9, - tcp_flag : 9, - reserved_0a : 6, - tso_enable : 1; - uint32_t ip_length : 16, - l2_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t udp_length : 16, - ip_identification : 16; - uint32_t reserved_4b : 2, - payload_start_offset : 14, - reserved_4a : 1, - partial_checksum_en : 1, - checksum_offset : 14; - uint32_t reserved_5b : 15, - wds : 1, - reserved_5a : 2, - payload_end_offset : 14; - uint32_t buf0_ptr_31_0 : 32; - uint32_t buf0_len : 16, - reserved_7a : 8, - buf0_ptr_39_32 : 8; - uint32_t buf1_ptr_31_0 : 32; - uint32_t buf1_len : 16, - reserved_9a : 8, - buf1_ptr_39_32 : 8; - uint32_t buf2_ptr_31_0 : 32; - uint32_t buf2_len : 16, - reserved_11a : 8, - buf2_ptr_39_32 : 8; - uint32_t buf3_ptr_31_0 : 32; - uint32_t buf3_len : 16, - reserved_13a : 8, - buf3_ptr_39_32 : 8; - uint32_t buf4_ptr_31_0 : 32; - uint32_t buf4_len : 16, - reserved_15a : 8, - buf4_ptr_39_32 : 8; - uint32_t buf5_ptr_31_0 : 32; - uint32_t buf5_len : 16, - reserved_17a : 8, - buf5_ptr_39_32 : 8; -#endif -}; - -#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 -#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 -#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 - -#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 -#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 -#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e - -#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 -#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 - -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 - -#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 -#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 - -#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 -#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 -#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 -#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff - -#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 -#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 -#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 -#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff - -#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c -#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 -#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 -#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff - -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 - -#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 -#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 - -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 - -#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 -#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 - -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff - -#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 -#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 - -#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_WDS_LSB 16 -#define TX_MSDU_EXTENSION_WDS_MSB 16 -#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 - -#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 -#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 - -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_7A_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_RESERVED_7A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_7A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_7A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_start.h deleted file mode 100644 index e62a76009f3a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_start.h +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MSDU_START_H_ -#define _TX_MSDU_START_H_ - -#define NUM_OF_DWORDS_TX_MSDU_START 8 - -#define NUM_OF_QWORDS_TX_MSDU_START 4 - -struct tx_msdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t msdu_len : 14, - first_msdu : 1, - last_msdu : 1, - encap_type : 2, - epd_en : 1, - da_sa_present : 2, - ipv4_checksum_en : 1, - udp_over_ipv4_checksum_en : 1, - udp_over_ipv6_checksum_en : 1, - tcp_over_ipv4_checksum_en : 1, - tcp_over_ipv6_checksum_en : 1, - dummy_msdu_delimitation : 1, - reserved_0a : 5; - uint32_t tso_enable : 1, - reserved_1a : 6, - tcp_flag : 9, - tcp_flag_mask : 9, - mesh_enable : 1, - reserved_1b : 6; - uint32_t l2_length : 16, - ip_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t ip_identification : 16, - checksum_offset : 13, - partial_checksum_en : 1, - reserved_4 : 2; - uint32_t payload_start_offset : 14, - reserved_5a : 2, - payload_end_offset : 14, - reserved_5b : 2; - uint32_t udp_length : 16, - reserved_6 : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 5, - dummy_msdu_delimitation : 1, - tcp_over_ipv6_checksum_en : 1, - tcp_over_ipv4_checksum_en : 1, - udp_over_ipv6_checksum_en : 1, - udp_over_ipv4_checksum_en : 1, - ipv4_checksum_en : 1, - da_sa_present : 2, - epd_en : 1, - encap_type : 2, - last_msdu : 1, - first_msdu : 1, - msdu_len : 14; - uint32_t reserved_1b : 6, - mesh_enable : 1, - tcp_flag_mask : 9, - tcp_flag : 9, - reserved_1a : 6, - tso_enable : 1; - uint32_t ip_length : 16, - l2_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t reserved_4 : 2, - partial_checksum_en : 1, - checksum_offset : 13, - ip_identification : 16; - uint32_t reserved_5b : 2, - payload_end_offset : 14, - reserved_5a : 2, - payload_start_offset : 14; - uint32_t reserved_6 : 16, - udp_length : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_MSDU_LEN_LSB 0 -#define TX_MSDU_START_MSDU_LEN_MSB 13 -#define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff - -#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000 -#define TX_MSDU_START_FIRST_MSDU_LSB 14 -#define TX_MSDU_START_FIRST_MSDU_MSB 14 -#define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000 - -#define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000 -#define TX_MSDU_START_LAST_MSDU_LSB 15 -#define TX_MSDU_START_LAST_MSDU_MSB 15 -#define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000 - -#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_ENCAP_TYPE_LSB 16 -#define TX_MSDU_START_ENCAP_TYPE_MSB 17 -#define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000 - -#define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_EPD_EN_LSB 18 -#define TX_MSDU_START_EPD_EN_MSB 18 -#define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000 - -#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000 -#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 -#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 -#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000 - -#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000 - -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000 - -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000 - -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000 - -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000 - -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000 - -#define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_0A_LSB 27 -#define TX_MSDU_START_RESERVED_0A_MSB 31 -#define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000 - -#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TSO_ENABLE_LSB 32 -#define TX_MSDU_START_TSO_ENABLE_MSB 32 -#define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000 - -#define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_1A_LSB 33 -#define TX_MSDU_START_RESERVED_1A_MSB 38 -#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000 - -#define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_FLAG_LSB 39 -#define TX_MSDU_START_TCP_FLAG_MSB 47 -#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000 - -#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_FLAG_MASK_LSB 48 -#define TX_MSDU_START_TCP_FLAG_MASK_MSB 56 -#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000 - -#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_MESH_ENABLE_LSB 57 -#define TX_MSDU_START_MESH_ENABLE_MSB 57 -#define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000 - -#define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_1B_LSB 58 -#define TX_MSDU_START_RESERVED_1B_MSB 63 -#define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000 - -#define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008 -#define TX_MSDU_START_L2_LENGTH_LSB 0 -#define TX_MSDU_START_L2_LENGTH_MSB 15 -#define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff - -#define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008 -#define TX_MSDU_START_IP_LENGTH_LSB 16 -#define TX_MSDU_START_IP_LENGTH_MSB 31 -#define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000 - -#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008 -#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32 -#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63 -#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 - -#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010 -#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 -#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 -#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff - -#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 -#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 -#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000 - -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000 - -#define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_4_LSB 30 -#define TX_MSDU_START_RESERVED_4_MSB 31 -#define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000 - -#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000 - -#define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_5A_LSB 46 -#define TX_MSDU_START_RESERVED_5A_MSB 47 -#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000 - -#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000 - -#define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_5B_LSB 62 -#define TX_MSDU_START_RESERVED_5B_MSB 63 -#define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000 - -#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018 -#define TX_MSDU_START_UDP_LENGTH_LSB 0 -#define TX_MSDU_START_UDP_LENGTH_MSB 15 -#define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff - -#define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018 -#define TX_MSDU_START_RESERVED_6_LSB 16 -#define TX_MSDU_START_RESERVED_6_MSB 31 -#define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000 - -#define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018 -#define TX_MSDU_START_TLV64_PADDING_LSB 32 -#define TX_MSDU_START_TLV64_PADDING_MSB 63 -#define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_peer_entry.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_peer_entry.h deleted file mode 100644 index c26c7f6a3e05..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_peer_entry.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_PEER_ENTRY_H_ -#define _TX_PEER_ENTRY_H_ - -#define NUM_OF_DWORDS_TX_PEER_ENTRY 22 - -#define NUM_OF_QWORDS_TX_PEER_ENTRY 11 - -struct tx_peer_entry { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mac_addr_a_31_0 : 32; - uint32_t mac_addr_a_47_32 : 16, - mac_addr_b_15_0 : 16; - uint32_t mac_addr_b_47_16 : 32; - uint32_t use_ad_b : 1, - strip_insert_vlan_inner : 1, - strip_insert_vlan_outer : 1, - vlan_llc_mode : 1, - key_type : 4, - a_msdu_wds_ad3_ad4 : 3, - ignore_hard_filters : 1, - ignore_soft_filters : 1, - epd_output : 1, - wds : 1, - insert_or_strip : 1, - sw_filter_id : 16; - uint32_t temporal_key_31_0 : 32; - uint32_t temporal_key_63_32 : 32; - uint32_t temporal_key_95_64 : 32; - uint32_t temporal_key_127_96 : 32; - uint32_t temporal_key_159_128 : 32; - uint32_t temporal_key_191_160 : 32; - uint32_t temporal_key_223_192 : 32; - uint32_t temporal_key_255_224 : 32; - uint32_t sta_partial_aid : 11, - transmit_vif : 4, - block_this_user : 1, - mesh_amsdu_mode : 2, - use_qos_alt_mute_mask : 1, - dl_ul_direction : 1, - use_ad_c : 1, - a_msdu_11s_fromtods_10_ad3 : 2, - multi_link_addr_ad3_valid : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_ad1_trans_dis : 1, - data_fromtods_00_ad3 : 2, - mgmt_fromtods_00_ad3 : 2, - reserved_12 : 1; - uint32_t insert_vlan_outer_tci : 16, - insert_vlan_inner_tci : 16; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0008 : 16, - __reserved_g_0009 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t multi_link_addr_crypto_enable : 1, - a_msdu_fromtods_10_ad3 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_11_ad4 : 2, - reserved_17a : 9, - sw_peer_id : 16; - uint32_t mac_addr_c_31_0 : 32; - uint32_t mac_addr_c_47_32 : 16, - multi_link_addr_ad3_47_32 : 16; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t mac_addr_a_31_0 : 32; - uint32_t mac_addr_b_15_0 : 16, - mac_addr_a_47_32 : 16; - uint32_t mac_addr_b_47_16 : 32; - uint32_t sw_filter_id : 16, - insert_or_strip : 1, - wds : 1, - epd_output : 1, - ignore_soft_filters : 1, - ignore_hard_filters : 1, - a_msdu_wds_ad3_ad4 : 3, - key_type : 4, - vlan_llc_mode : 1, - strip_insert_vlan_outer : 1, - strip_insert_vlan_inner : 1, - use_ad_b : 1; - uint32_t temporal_key_31_0 : 32; - uint32_t temporal_key_63_32 : 32; - uint32_t temporal_key_95_64 : 32; - uint32_t temporal_key_127_96 : 32; - uint32_t temporal_key_159_128 : 32; - uint32_t temporal_key_191_160 : 32; - uint32_t temporal_key_223_192 : 32; - uint32_t temporal_key_255_224 : 32; - uint32_t reserved_12 : 1, - mgmt_fromtods_00_ad3 : 2, - data_fromtods_00_ad3 : 2, - multi_link_addr_ad1_trans_dis : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_ad3_valid : 1, - a_msdu_11s_fromtods_10_ad3 : 2, - use_ad_c : 1, - dl_ul_direction : 1, - use_qos_alt_mute_mask : 1, - mesh_amsdu_mode : 2, - block_this_user : 1, - transmit_vif : 4, - sta_partial_aid : 11; - uint32_t insert_vlan_inner_tci : 16, - insert_vlan_outer_tci : 16; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0009 : 16, - __reserved_g_0008 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t sw_peer_id : 16, - reserved_17a : 9, - a_msdu_fromtods_11_ad4 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_10_ad3 : 2, - multi_link_addr_crypto_enable : 1; - uint32_t mac_addr_c_31_0 : 32; - uint32_t multi_link_addr_ad3_47_32 : 16, - mac_addr_c_47_32 : 16; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_USE_AD_B_LSB 32 -#define TX_PEER_ENTRY_USE_AD_B_MSB 32 -#define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 - -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 - -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 - -#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 - -#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_KEY_TYPE_LSB 36 -#define TX_PEER_ENTRY_KEY_TYPE_MSB 39 -#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 - -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 - -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 - -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 - -#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 -#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 -#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 - -#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_WDS_LSB 46 -#define TX_PEER_ENTRY_WDS_MSB 46 -#define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 - -#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 - -#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 -#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 -#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff - -#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 -#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 -#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 - -#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 - -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 - -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 - -#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 - -#define TX_PEER_ENTRY_USE_AD_C_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_USE_AD_C_LSB 20 -#define TX_PEER_ENTRY_USE_AD_C_MSB 20 -#define TX_PEER_ENTRY_USE_AD_C_MASK 0x0000000000100000 - -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_LSB 21 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MSB 22 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MASK 0x0000000000600000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_LSB 23 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MSB 23 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MASK 0x0000000000800000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 24 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 24 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0000000001000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 25 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 25 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x0000000002000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 26 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 26 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x0000000004000000 - -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_LSB 27 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MSB 28 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MASK 0x0000000018000000 - -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_LSB 29 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MSB 30 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MASK 0x0000000060000000 - -#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_RESERVED_12_LSB 31 -#define TX_PEER_ENTRY_RESERVED_12_MSB 31 -#define TX_PEER_ENTRY_RESERVED_12_MASK 0x0000000080000000 - -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_LSB 33 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MSB 34 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MASK 0x0000000600000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_LSB 35 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MSB 36 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MASK 0x0000001800000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_LSB 37 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MSB 38 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MASK 0x0000006000000000 - -#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_RESERVED_17A_LSB 39 -#define TX_PEER_ENTRY_RESERVED_17A_MSB 47 -#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000ff8000000000 - -#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 -#define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 -#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_LSB 32 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MSB 47 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_LSB 48 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MSB 63 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_OFFSET 0x0000000000000050 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_LSB 0 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MSB 31 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TLV64_PADDING_OFFSET 0x0000000000000050 -#define TX_PEER_ENTRY_TLV64_PADDING_LSB 32 -#define TX_PEER_ENTRY_TLV64_PADDING_MSB 63 -#define TX_PEER_ENTRY_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_queue_extension.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_queue_extension.h deleted file mode 100644 index e46bae7cff4c..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_queue_extension.h +++ /dev/null @@ -1,432 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_QUEUE_EXTENSION_H_ -#define _TX_QUEUE_EXTENSION_H_ - -#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 18 - -#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 9 - -struct tx_queue_extension { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t frame_ctl : 16, - qos_ctl : 16; - uint32_t ampdu_flag : 1, - tx_notify_no_htc_override : 1, - reserved_1a : 7, - checksum_tso_disable_for_frag : 1, - key_id : 8, - qos_buf_state_overwrite : 1, - buf_state_sta_id : 1, - buf_state_source : 1, - ht_control_overwrite_enable : 1, - ht_control_overwrite_source : 4, - reserved_1b : 6; - uint32_t ul_headroom_insertion_enable : 1, - ul_headroom_offset : 5, - bqrp_insertion_enable : 1, - bqrp_offset : 5, - ul_headroom_rsvd_7_6 : 2, - bqr_rsvd_9_8 : 2, - base_pn_63_48 : 16; - uint32_t base_pn_95_64 : 32; - uint32_t base_pn_127_96 : 32; - uint32_t ht_control_default_tb_ppdu : 32; - uint32_t ht_control_default_non_tb_ppdu : 32; - uint32_t ht_control_overwrite_tb_ppdu_enable : 1, - ht_control_overwrite_non_tb_ppdu_enable : 1, - reserved_7a : 30; - uint32_t reserved_8a : 32; - uint32_t ht_control_overwrite_mask : 32; - uint32_t cas_control_info : 8, - cas_offset : 5, - cas_insertion_enable : 1, - reserved_10a : 2, - ht_control_overwrite_source_for_srp : 4, - ht_control_overwrite_source_for_bsrp : 4, - pre_padding_fcs_overwrite_enable : 1, - reserved_10b : 5, - mpdu_hdr_len_override_en : 1, - bar_ssn_overwrite_enable : 1; - uint32_t bar_ssn_offset : 12, - mpdu_hdr_len_override_val : 9, - reserved_11a : 11; - uint32_t fw2sw_info : 32; - uint32_t pre_padding_fcs_overwrite_offset : 16, - icf_blackout_info_offset : 16; - uint32_t trigger_common_info_length : 6, - cmf_overwrite_offset : 14, - reserved_15a : 12; - uint32_t hdr_ctrl_prot_key_id_byte_offset : 14, - hdr_ctrl_prot_key_id_bit_offset : 3, - ctrl_pkt_protect : 1, - mac_hdr_protect : 1, - hdr_ctrl_prot_tx_peer_idx : 11, - reserved_16a : 2; - uint32_t pad_byte_offset : 16, - pad_byte_offset_valid : 1, - txop_duration_overwrite_enable : 1, - txop_duration_offset : 14; - uint32_t tlv64_padding : 32; -#else - uint32_t qos_ctl : 16, - frame_ctl : 16; - uint32_t reserved_1b : 6, - ht_control_overwrite_source : 4, - ht_control_overwrite_enable : 1, - buf_state_source : 1, - buf_state_sta_id : 1, - qos_buf_state_overwrite : 1, - key_id : 8, - checksum_tso_disable_for_frag : 1, - reserved_1a : 7, - tx_notify_no_htc_override : 1, - ampdu_flag : 1; - uint32_t base_pn_63_48 : 16, - bqr_rsvd_9_8 : 2, - ul_headroom_rsvd_7_6 : 2, - bqrp_offset : 5, - bqrp_insertion_enable : 1, - ul_headroom_offset : 5, - ul_headroom_insertion_enable : 1; - uint32_t base_pn_95_64 : 32; - uint32_t base_pn_127_96 : 32; - uint32_t ht_control_default_tb_ppdu : 32; - uint32_t ht_control_default_non_tb_ppdu : 32; - uint32_t reserved_7a : 30, - ht_control_overwrite_non_tb_ppdu_enable : 1, - ht_control_overwrite_tb_ppdu_enable : 1; - uint32_t reserved_8a : 32; - uint32_t ht_control_overwrite_mask : 32; - uint32_t bar_ssn_overwrite_enable : 1, - mpdu_hdr_len_override_en : 1, - reserved_10b : 5, - pre_padding_fcs_overwrite_enable : 1, - ht_control_overwrite_source_for_bsrp : 4, - ht_control_overwrite_source_for_srp : 4, - reserved_10a : 2, - cas_insertion_enable : 1, - cas_offset : 5, - cas_control_info : 8; - uint32_t reserved_11a : 11, - mpdu_hdr_len_override_val : 9, - bar_ssn_offset : 12; - uint32_t fw2sw_info : 32; - uint32_t icf_blackout_info_offset : 16, - pre_padding_fcs_overwrite_offset : 16; - uint32_t reserved_15a : 12, - cmf_overwrite_offset : 14, - trigger_common_info_length : 6; - uint32_t reserved_16a : 2, - hdr_ctrl_prot_tx_peer_idx : 11, - mac_hdr_protect : 1, - ctrl_pkt_protect : 1, - hdr_ctrl_prot_key_id_bit_offset : 3, - hdr_ctrl_prot_key_id_byte_offset : 14; - uint32_t txop_duration_offset : 14, - txop_duration_overwrite_enable : 1, - pad_byte_offset_valid : 1, - pad_byte_offset : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 -#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 -#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff - -#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 -#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 -#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 - -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 - -#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 -#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 -#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 - -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 - -#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 -#define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 -#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 - -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 - -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 - -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 -#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e - -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 - -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 - -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 - -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_OFFSET 0x0000000000000010 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_LSB 0 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_MSB 31 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_MSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_MASK 0x0000000100000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_LSB 33 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_MSB 33 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_MASK 0x0000000200000000 - -#define TX_QUEUE_EXTENSION_RESERVED_7A_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_RESERVED_7A_LSB 34 -#define TX_QUEUE_EXTENSION_RESERVED_7A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_7A_MASK 0xfffffffc00000000 - -#define TX_QUEUE_EXTENSION_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_QUEUE_EXTENSION_RESERVED_8A_LSB 0 -#define TX_QUEUE_EXTENSION_RESERVED_8A_MSB 31 -#define TX_QUEUE_EXTENSION_RESERVED_8A_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff - -#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 - -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 - -#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 -#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 -#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 - -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_LSB 24 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MSB 24 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MASK 0x0000000001000000 - -#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 25 -#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 -#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003e000000 - -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 - -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 - -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 - -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 -#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 - -#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 0 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 31 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MSB 47 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MASK 0x0000ffff00000000 - -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_LSB 48 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MSB 63 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MASK 0xffff000000000000 - -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_LSB 0 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MSB 5 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MASK 0x000000000000003f - -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_LSB 6 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MSB 19 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MASK 0x00000000000fffc0 - -#define TX_QUEUE_EXTENSION_RESERVED_15A_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_RESERVED_15A_LSB 20 -#define TX_QUEUE_EXTENSION_RESERVED_15A_MSB 31 -#define TX_QUEUE_EXTENSION_RESERVED_15A_MASK 0x00000000fff00000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MSB 45 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MASK 0x00003fff00000000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_LSB 46 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MSB 48 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MASK 0x0001c00000000000 - -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_LSB 49 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MSB 49 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MASK 0x0002000000000000 - -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_LSB 50 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MSB 50 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MASK 0x0004000000000000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_LSB 51 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MSB 61 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MASK 0x3ff8000000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_16A_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_RESERVED_16A_LSB 62 -#define TX_QUEUE_EXTENSION_RESERVED_16A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_16A_MASK 0xc000000000000000 - -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_LSB 0 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MSB 15 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MASK 0x000000000000ffff - -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_LSB 16 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MSB 16 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MASK 0x0000000000010000 - -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_LSB 17 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_MSB 17 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_MASK 0x0000000000020000 - -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_LSB 18 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_MSB 31 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_MASK 0x00000000fffc0000 - -#define TX_QUEUE_EXTENSION_TLV64_PADDING_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_TLV64_PADDING_LSB 32 -#define TX_QUEUE_EXTENSION_TLV64_PADDING_MSB 63 -#define TX_QUEUE_EXTENSION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_rate_stats_info.h deleted file mode 100644 index ce84032dd353..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_rate_stats_info.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_RATE_STATS_INFO_H_ -#define _TX_RATE_STATS_INFO_H_ - -#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 - -struct tx_rate_stats_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_rate_stats_info_valid : 1, - transmit_bw : 3, - transmit_pkt_type : 4, - transmit_stbc : 1, - transmit_ldpc : 1, - transmit_sgi : 2, - transmit_mcs : 5, - unequal_modulation_info : 3, - ofdma_transmission : 1, - reserved_0a : 4, - tones_in_ru : 4, - transmit_nss : 3; - uint32_t ppdu_transmission_tsf : 32; -#else - uint32_t transmit_nss : 3, - tones_in_ru : 4, - reserved_0a : 4, - ofdma_transmission : 1, - unequal_modulation_info : 3, - transmit_mcs : 5, - transmit_sgi : 2, - transmit_ldpc : 1, - transmit_stbc : 1, - transmit_pkt_type : 4, - transmit_bw : 3, - tx_rate_stats_info_valid : 1; - uint32_t ppdu_transmission_tsf : 32; -#endif -}; - -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 - -#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e - -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0 - -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100 - -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200 - -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00 - -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 16 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0001f000 - -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_LSB 17 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MSB 19 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MASK 0x000e0000 - -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 20 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 20 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00100000 - -#define TX_RATE_STATS_INFO_RESERVED_0A_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_RESERVED_0A_LSB 21 -#define TX_RATE_STATS_INFO_RESERVED_0A_MSB 24 -#define TX_RATE_STATS_INFO_RESERVED_0A_MASK 0x01e00000 - -#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 25 -#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28 -#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1e000000 - -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB 29 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB 31 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK 0xe0000000 - -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_raw_or_native_frame_setup.h deleted file mode 100644 index 220a82edf96d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_raw_or_native_frame_setup.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ -#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ - -#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 4 - -#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 - -struct tx_raw_or_native_frame_setup { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t fc_to_ds_mask : 1, - fc_from_ds_mask : 1, - fc_more_frag_mask : 1, - fc_retry_mask : 1, - fc_pwr_mgt_mask : 1, - fc_more_data_mask : 1, - fc_prot_frame_mask : 1, - fc_order_mask : 1, - duration_field_mask : 1, - sequence_control_mask : 1, - qc_tid_mask : 1, - qc_eosp_mask : 1, - qc_ack_policy_mask : 1, - qc_amsdu_mask : 1, - reserved_0a : 1, - qc_15to8_mask : 1, - iv_mask : 1, - fc_to_ds_setting : 1, - fc_from_ds_setting : 1, - fc_more_frag_setting : 1, - fc_retry_setting : 2, - fc_pwr_mgt_setting : 1, - fc_more_data_setting : 2, - fc_prot_frame_setting : 2, - fc_order_setting : 1, - qc_tid_setting : 4; - uint32_t qc_eosp_setting : 2, - qc_ack_policy_setting : 2, - qc_amsdu_setting : 1, - qc_15to8_setting : 8, - mlo_addr_override : 1, - mlo_ignore_addr3_override : 1, - sequence_control_source : 1, - fragment_number : 4, - sequence_number : 12; - uint32_t mlo_addr_override_for_ctrl : 1, - reserved_2a : 31; - uint32_t tlv64_padding : 32; -#else - uint32_t qc_tid_setting : 4, - fc_order_setting : 1, - fc_prot_frame_setting : 2, - fc_more_data_setting : 2, - fc_pwr_mgt_setting : 1, - fc_retry_setting : 2, - fc_more_frag_setting : 1, - fc_from_ds_setting : 1, - fc_to_ds_setting : 1, - iv_mask : 1, - qc_15to8_mask : 1, - reserved_0a : 1, - qc_amsdu_mask : 1, - qc_ack_policy_mask : 1, - qc_eosp_mask : 1, - qc_tid_mask : 1, - sequence_control_mask : 1, - duration_field_mask : 1, - fc_order_mask : 1, - fc_prot_frame_mask : 1, - fc_more_data_mask : 1, - fc_pwr_mgt_mask : 1, - fc_retry_mask : 1, - fc_more_frag_mask : 1, - fc_from_ds_mask : 1, - fc_to_ds_mask : 1; - uint32_t sequence_number : 12, - fragment_number : 4, - sequence_control_source : 1, - mlo_ignore_addr3_override : 1, - mlo_addr_override : 1, - qc_15to8_setting : 8, - qc_amsdu_setting : 1, - qc_ack_policy_setting : 2, - qc_eosp_setting : 2; - uint32_t reserved_2a : 31, - mlo_addr_override_for_ctrl : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x0000000000000001 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x0000000000000002 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x0000000000000004 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x0000000000000008 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x0000000000000010 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x0000000000000020 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x0000000000000040 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x0000000000000080 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x0000000000000100 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x0000000000000200 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x0000000000000400 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x0000000000000800 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x0000000000001000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x0000000000002000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x0000000000004000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x0000000000008000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x0000000000010000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x0000000000020000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x0000000000040000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x0000000000080000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x0000000000300000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x0000000000400000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x0000000001800000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x0000000006000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x0000000008000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0x00000000f0000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 32 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 33 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x0000000300000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 34 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 35 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c00000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 36 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 36 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x0000001000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 37 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 44 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 45 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 45 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x0000200000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 46 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 46 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x0000400000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 47 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 47 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x0000800000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 48 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 51 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f000000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 52 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 63 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff0000000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_LSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MASK 0x0000000000000001 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_LSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MSB 31 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MASK 0x00000000fffffffe - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_LSB 32 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MSB 63 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_basics.h deleted file mode 100644 index 4032a78ad617..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_basics.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_BUFFER_BASICS_H_ -#define _TXPCU_BUFFER_BASICS_H_ - -#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 - -struct txpcu_buffer_basics { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t available_memory : 8, - partial_tx_data_tlv_count : 8, - tx_data_tlv_count : 16; -#else - uint32_t tx_data_tlv_count : 16, - partial_tx_data_tlv_count : 8, - available_memory : 8; -#endif -}; - -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff - -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 - -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_status.h deleted file mode 100644 index 847ca277267d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_status.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_BUFFER_STATUS_H_ -#define _TXPCU_BUFFER_STATUS_H_ - -#include "txpcu_buffer_basics.h" -#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 - -#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1 - -struct txpcu_buffer_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct txpcu_buffer_basics txpcu_basix_buffer_info; - uint32_t reserved : 15, - msdu_end : 1, - tx_data_sync_value : 16; -#else - struct txpcu_buffer_basics txpcu_basix_buffer_info; - uint32_t tx_data_sync_value : 16, - msdu_end : 1, - reserved : 15; -#endif -}; - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 - -#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_RESERVED_LSB 32 -#define TXPCU_BUFFER_STATUS_RESERVED_MSB 46 -#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000 - -#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47 -#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47 -#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 - -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_user_buffer_status.h deleted file mode 100644 index f6ad0fd73721..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_user_buffer_status.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_USER_BUFFER_STATUS_H_ -#define _TXPCU_USER_BUFFER_STATUS_H_ - -#include "txpcu_buffer_basics.h" -#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 - -#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1 - -struct txpcu_user_buffer_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct txpcu_buffer_basics txpcu_basic_buffer_info; - uint32_t stored_word_count_user : 14, - reserved_1a : 1, - msdu_end : 1, - tx_data_sync_value : 16; -#else - struct txpcu_buffer_basics txpcu_basic_buffer_info; - uint32_t tx_data_sync_value : 16, - msdu_end : 1, - reserved_1a : 1, - stored_word_count_user : 14; -#endif -}; - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 - -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 32 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 45 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff00000000 - -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 46 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 46 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x0000400000000000 - -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 47 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 47 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 - -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_su_mu_info.h deleted file mode 100644 index 1a08f3ab39b2..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_su_mu_info.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _U_SIG_EHT_SU_MU_INFO_H_ -#define _U_SIG_EHT_SU_MU_INFO_H_ - -#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 - -struct u_sig_eht_su_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_version : 3, - transmit_bw : 3, - dl_ul_flag : 1, - bss_color_id : 6, - txop_duration : 7, - disregard_0a : 5, - validate_0b : 1, - reserved_0c : 6; - uint32_t eht_ppdu_sig_cmn_type : 2, - validate_1a : 1, - punctured_channel_information : 5, - validate_1b : 1, - mcs_of_eht_sig : 2, - num_eht_sig_symbols : 5, - crc : 4, - tail : 6, - dot11ax_su_extended : 1, - reserved_1d : 3, - rx_ndp : 1, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0c : 6, - validate_0b : 1, - disregard_0a : 5, - txop_duration : 7, - bss_color_id : 6, - dl_ul_flag : 1, - transmit_bw : 3, - phy_version : 3; - uint32_t rx_integrity_check_passed : 1, - rx_ndp : 1, - reserved_1d : 3, - dot11ax_su_extended : 1, - tail : 6, - crc : 4, - num_eht_sig_symbols : 5, - mcs_of_eht_sig : 2, - validate_1b : 1, - punctured_channel_information : 5, - validate_1a : 1, - eht_ppdu_sig_cmn_type : 2; -#endif -}; - -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 - -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 - -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 - -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 - -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 - -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 - -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 - -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 - -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 - -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 - -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 - -#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 -#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 -#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 - -#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 -#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 -#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 - -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 - -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 - -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 - -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_tb_info.h deleted file mode 100644 index 8e417b38d233..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_tb_info.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _U_SIG_EHT_TB_INFO_H_ -#define _U_SIG_EHT_TB_INFO_H_ - -#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 - -struct u_sig_eht_tb_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_version : 3, - transmit_bw : 3, - dl_ul_flag : 1, - bss_color_id : 6, - txop_duration : 7, - disregard_0a : 6, - reserved_0c : 6; - uint32_t eht_ppdu_sig_cmn_type : 2, - validate_1a : 1, - spatial_reuse : 8, - disregard_1b : 5, - crc : 4, - tail : 6, - reserved_1c : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0c : 6, - disregard_0a : 6, - txop_duration : 7, - bss_color_id : 6, - dl_ul_flag : 1, - transmit_bw : 3, - phy_version : 3; - uint32_t rx_integrity_check_passed : 1, - reserved_1c : 5, - tail : 6, - crc : 4, - disregard_1b : 5, - spatial_reuse : 8, - validate_1a : 1, - eht_ppdu_sig_cmn_type : 2; -#endif -}; - -#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 - -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 - -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 - -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 - -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 - -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 - -#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 - -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 - -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 - -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 - -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 - -#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_CRC_LSB 16 -#define U_SIG_EHT_TB_INFO_CRC_MSB 19 -#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 - -#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 -#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 -#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 - -#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 - -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/unallocated_ru_160_info.h deleted file mode 100644 index ccd4a7bab9ad..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/unallocated_ru_160_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _UNALLOCATED_RU_160_INFO_H_ -#define _UNALLOCATED_RU_160_INFO_H_ - -#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 - -struct unallocated_ru_160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t subband80_0_cc0 : 8, - subband80_0_cc1 : 8, - subband80_1_cc0 : 8, - subband80_1_cc1 : 8; -#else - uint32_t subband80_1_cc1 : 8, - subband80_1_cc0 : 8, - subband80_0_cc1 : 8, - subband80_0_cc0 : 8; -#endif -}; - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/wcn8750/v1/uniform_descriptor_header.h deleted file mode 100644 index 7a2de6ccd8df..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/uniform_descriptor_header.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ -#define _UNIFORM_DESCRIPTOR_HEADER_H_ - -#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 - -struct uniform_descriptor_header { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t owner : 4, - buffer_type : 4, - tx_mpdu_queue_number : 20, - reserved_0a : 4; -#else - uint32_t reserved_0a : 4, - tx_mpdu_queue_number : 20, - buffer_type : 4, - owner : 4; -#endif -}; - -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f - -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 - -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 - -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_a_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_a_info.h deleted file mode 100644 index acd20f43949e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_a_info.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_A_INFO_H_ -#define _VHT_SIG_A_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 - -struct vht_sig_a_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t bandwidth : 2, - vhta_reserved_0 : 1, - stbc : 1, - group_id : 6, - n_sts : 12, - txop_ps_not_allowed : 1, - vhta_reserved_0b : 1, - reserved_0 : 8; - uint32_t gi_setting : 2, - su_mu_coding : 1, - ldpc_extra_symbol : 1, - mcs : 4, - beamformed : 1, - vhta_reserved_1 : 1, - crc : 8, - tail : 6, - reserved_1 : 7, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0 : 8, - vhta_reserved_0b : 1, - txop_ps_not_allowed : 1, - n_sts : 12, - group_id : 6, - stbc : 1, - vhta_reserved_0 : 1, - bandwidth : 2; - uint32_t rx_integrity_check_passed : 1, - reserved_1 : 7, - tail : 6, - crc : 8, - vhta_reserved_1 : 1, - beamformed : 1, - mcs : 4, - ldpc_extra_symbol : 1, - su_mu_coding : 1, - gi_setting : 2; -#endif -}; - -#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0 -#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1 -#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004 - -#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_STBC_LSB 3 -#define VHT_SIG_A_INFO_STBC_MSB 3 -#define VHT_SIG_A_INFO_STBC_MASK 0x00000008 - -#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_GROUP_ID_LSB 4 -#define VHT_SIG_A_INFO_GROUP_ID_MSB 9 -#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0 - -#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_N_STS_LSB 10 -#define VHT_SIG_A_INFO_N_STS_MSB 21 -#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00 - -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000 - -#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_RESERVED_0_LSB 24 -#define VHT_SIG_A_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000 - -#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_GI_SETTING_LSB 0 -#define VHT_SIG_A_INFO_GI_SETTING_MSB 1 -#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003 - -#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2 -#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2 -#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004 - -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008 - -#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_MCS_LSB 4 -#define VHT_SIG_A_INFO_MCS_MSB 7 -#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0 - -#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8 -#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8 -#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200 - -#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_CRC_LSB 10 -#define VHT_SIG_A_INFO_CRC_MSB 17 -#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00 - -#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_TAIL_LSB 18 -#define VHT_SIG_A_INFO_TAIL_MSB 23 -#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000 - -#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_RESERVED_1_LSB 24 -#define VHT_SIG_A_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000 - -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu160_info.h deleted file mode 100644 index 13931c5c3556..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu160_info.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU160_INFO_H_ -#define _VHT_SIG_B_MU160_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 - -struct vht_sig_b_mu160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - mcs : 4, - tail : 6, - reserved_0 : 3; - uint32_t length_copy_a : 19, - mcs_copy_a : 4, - tail_copy_a : 6, - reserved_1 : 3; - uint32_t length_copy_b : 19, - mcs_copy_b : 4, - tail_copy_b : 6, - reserved_2 : 3; - uint32_t length_copy_c : 19, - mcs_copy_c : 4, - tail_copy_c : 6, - reserved_3 : 3; - uint32_t length_copy_d : 19, - mcs_copy_d : 4, - tail_copy_d : 6, - reserved_4 : 3; - uint32_t length_copy_e : 19, - mcs_copy_e : 4, - tail_copy_e : 6, - reserved_5 : 3; - uint32_t length_copy_f : 19, - mcs_copy_f : 4, - tail_copy_f : 6, - mu_user_number : 3; - uint32_t length_copy_g : 19, - mcs_copy_g : 4, - tail_copy_g : 6, - reserved_7 : 3; -#else - uint32_t reserved_0 : 3, - tail : 6, - mcs : 4, - length : 19; - uint32_t reserved_1 : 3, - tail_copy_a : 6, - mcs_copy_a : 4, - length_copy_a : 19; - uint32_t reserved_2 : 3, - tail_copy_b : 6, - mcs_copy_b : 4, - length_copy_b : 19; - uint32_t reserved_3 : 3, - tail_copy_c : 6, - mcs_copy_c : 4, - length_copy_c : 19; - uint32_t reserved_4 : 3, - tail_copy_d : 6, - mcs_copy_d : 4, - length_copy_d : 19; - uint32_t reserved_5 : 3, - tail_copy_e : 6, - mcs_copy_e : 4, - length_copy_e : 19; - uint32_t mu_user_number : 3, - tail_copy_f : 6, - mcs_copy_f : 4, - length_copy_f : 19; - uint32_t reserved_7 : 3, - tail_copy_g : 6, - mcs_copy_g : 4, - length_copy_g : 19; -#endif -}; - -#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu20_info.h deleted file mode 100644 index c51ac839a757..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu20_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU20_INFO_H_ -#define _VHT_SIG_B_MU20_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 - -struct vht_sig_b_mu20_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 16, - mcs : 4, - tail : 6, - mu_user_number : 3, - reserved_0 : 3; -#else - uint32_t reserved_0 : 3, - mu_user_number : 3, - tail : 6, - mcs : 4, - length : 16; -#endif -}; - -#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 -#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff - -#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 -#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 -#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 - -#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 -#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 -#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 - -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 - -#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu40_info.h deleted file mode 100644 index 0eb4c164cca1..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu40_info.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU40_INFO_H_ -#define _VHT_SIG_B_MU40_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 - -struct vht_sig_b_mu40_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 17, - mcs : 4, - tail : 6, - reserved_0 : 2, - mu_user_number : 3; - uint32_t length_copy : 17, - mcs_copy : 4, - tail_copy : 6, - reserved_1 : 5; -#else - uint32_t mu_user_number : 3, - reserved_0 : 2, - tail : 6, - mcs : 4, - length : 17; - uint32_t reserved_1 : 5, - tail_copy : 6, - mcs_copy : 4, - length_copy : 17; -#endif -}; - -#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 -#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff - -#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 -#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 -#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 - -#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 -#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 -#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 - -#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 - -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff - -#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 - -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 - -#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu80_info.h deleted file mode 100644 index 33d0f1bc08fc..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu80_info.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU80_INFO_H_ -#define _VHT_SIG_B_MU80_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 - -struct vht_sig_b_mu80_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - mcs : 4, - tail : 6, - reserved_0 : 3; - uint32_t length_copy_a : 19, - mcs_copy_a : 4, - tail_copy_a : 6, - reserved_1 : 3; - uint32_t length_copy_b : 19, - mcs_copy_b : 4, - tail_copy_b : 6, - mu_user_number : 3; - uint32_t length_copy_c : 19, - mcs_copy_c : 4, - tail_copy_c : 6, - reserved_3 : 3; -#else - uint32_t reserved_0 : 3, - tail : 6, - mcs : 4, - length : 19; - uint32_t reserved_1 : 3, - tail_copy_a : 6, - mcs_copy_a : 4, - length_copy_a : 19; - uint32_t mu_user_number : 3, - tail_copy_b : 6, - mcs_copy_b : 4, - length_copy_b : 19; - uint32_t reserved_3 : 3, - tail_copy_c : 6, - mcs_copy_c : 4, - length_copy_c : 19; -#endif -}; - -#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su160_info.h deleted file mode 100644 index 7ba503724b56..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su160_info.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU160_INFO_H_ -#define _VHT_SIG_B_SU160_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 - -struct vht_sig_b_su160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 21, - vhtb_reserved : 2, - tail : 6, - reserved_0 : 2, - rx_ndp : 1; - uint32_t length_copy_a : 21, - vhtb_reserved_copy_a : 2, - tail_copy_a : 6, - reserved_1 : 2, - rx_ndp_copy_a : 1; - uint32_t length_copy_b : 21, - vhtb_reserved_copy_b : 2, - tail_copy_b : 6, - reserved_2 : 2, - rx_ndp_copy_b : 1; - uint32_t length_copy_c : 21, - vhtb_reserved_copy_c : 2, - tail_copy_c : 6, - reserved_3 : 2, - rx_ndp_copy_c : 1; - uint32_t length_copy_d : 21, - vhtb_reserved_copy_d : 2, - tail_copy_d : 6, - reserved_4 : 2, - rx_ndp_copy_d : 1; - uint32_t length_copy_e : 21, - vhtb_reserved_copy_e : 2, - tail_copy_e : 6, - reserved_5 : 2, - rx_ndp_copy_e : 1; - uint32_t length_copy_f : 21, - vhtb_reserved_copy_f : 2, - tail_copy_f : 6, - reserved_6 : 2, - rx_ndp_copy_f : 1; - uint32_t length_copy_g : 21, - vhtb_reserved_copy_g : 2, - tail_copy_g : 6, - reserved_7 : 2, - rx_ndp_copy_g : 1; -#else - uint32_t rx_ndp : 1, - reserved_0 : 2, - tail : 6, - vhtb_reserved : 2, - length : 21; - uint32_t rx_ndp_copy_a : 1, - reserved_1 : 2, - tail_copy_a : 6, - vhtb_reserved_copy_a : 2, - length_copy_a : 21; - uint32_t rx_ndp_copy_b : 1, - reserved_2 : 2, - tail_copy_b : 6, - vhtb_reserved_copy_b : 2, - length_copy_b : 21; - uint32_t rx_ndp_copy_c : 1, - reserved_3 : 2, - tail_copy_c : 6, - vhtb_reserved_copy_c : 2, - length_copy_c : 21; - uint32_t rx_ndp_copy_d : 1, - reserved_4 : 2, - tail_copy_d : 6, - vhtb_reserved_copy_d : 2, - length_copy_d : 21; - uint32_t rx_ndp_copy_e : 1, - reserved_5 : 2, - tail_copy_e : 6, - vhtb_reserved_copy_e : 2, - length_copy_e : 21; - uint32_t rx_ndp_copy_f : 1, - reserved_6 : 2, - tail_copy_f : 6, - vhtb_reserved_copy_f : 2, - length_copy_f : 21; - uint32_t rx_ndp_copy_g : 1, - reserved_7 : 2, - tail_copy_g : 6, - vhtb_reserved_copy_g : 2, - length_copy_g : 21; -#endif -}; - -#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su20_info.h deleted file mode 100644 index 2c7f11ba3c21..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su20_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU20_INFO_H_ -#define _VHT_SIG_B_SU20_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 - -struct vht_sig_b_su20_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 17, - vhtb_reserved : 3, - tail : 6, - reserved : 5, - rx_ndp : 1; -#else - uint32_t rx_ndp : 1, - reserved : 5, - tail : 6, - vhtb_reserved : 3, - length : 17; -#endif -}; - -#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 -#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff - -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 - -#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 -#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 -#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 - -#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 -#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 -#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 - -#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su40_info.h deleted file mode 100644 index 467259003e8d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su40_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU40_INFO_H_ -#define _VHT_SIG_B_SU40_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 - -struct vht_sig_b_su40_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - vhtb_reserved : 2, - tail : 6, - reserved : 4, - rx_ndp : 1; - uint32_t length_copy : 19, - vhtb_reserved_copy : 2, - tail_copy : 6, - reserved_copy : 4, - rx_ndp_copy : 1; -#else - uint32_t rx_ndp : 1, - reserved : 4, - tail : 6, - vhtb_reserved : 2, - length : 19; - uint32_t rx_ndp_copy : 1, - reserved_copy : 4, - tail_copy : 6, - vhtb_reserved_copy : 2, - length_copy : 19; -#endif -}; - -#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 - -#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 -#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 -#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 - -#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 -#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 -#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 - -#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff - -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 - -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 - -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 - -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su80_info.h deleted file mode 100644 index 92ceeab9b476..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su80_info.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU80_INFO_H_ -#define _VHT_SIG_B_SU80_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 - -struct vht_sig_b_su80_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 21, - vhtb_reserved : 2, - tail : 6, - reserved_0 : 2, - rx_ndp : 1; - uint32_t length_copy_a : 21, - vhtb_reserved_copy_a : 2, - tail_copy_a : 6, - reserved_1 : 2, - rx_ndp_copy_a : 1; - uint32_t length_copy_b : 21, - vhtb_reserved_copy_b : 2, - tail_copy_b : 6, - reserved_2 : 2, - rx_ndp_copy_b : 1; - uint32_t length_copy_c : 21, - vhtb_reserved_copy_c : 2, - tail_copy_c : 6, - reserved_3 : 2, - rx_ndp_copy_c : 1; -#else - uint32_t rx_ndp : 1, - reserved_0 : 2, - tail : 6, - vhtb_reserved : 2, - length : 21; - uint32_t rx_ndp_copy_a : 1, - reserved_1 : 2, - tail_copy_a : 6, - vhtb_reserved_copy_a : 2, - length_copy_a : 21; - uint32_t rx_ndp_copy_b : 1, - reserved_2 : 2, - tail_copy_b : 6, - vhtb_reserved_copy_b : 2, - length_copy_b : 21; - uint32_t rx_ndp_copy_c : 1, - reserved_3 : 2, - tail_copy_c : 6, - vhtb_reserved_copy_c : 2, - length_copy_c : 21; -#endif -}; - -#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wbm2sw_completion_ring_rx.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm2sw_completion_ring_rx.h deleted file mode 100644 index e40a7e796a87..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wbm2sw_completion_ring_rx.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM2SW_COMPLETION_RING_RX_H_ -#define _WBM2SW_COMPLETION_RING_RX_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_mpdu_desc_info.h" -#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 - -struct wbm2sw_completion_ring_rx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t release_source_module : 3, - bm_action : 3, - buffer_or_desc_type : 3, - return_buffer_manager : 4, - reserved_2a : 2, - cache_id : 1, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_push_reason : 2, - reo_error_code : 5, - wbm_internal_error : 1; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t buffer_phys_addr_31_0 : 32; - uint32_t buffer_phys_addr_39_32 : 8, - sw_buffer_cookie : 20, - looping_count : 4; -#else - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t wbm_internal_error : 1, - reo_error_code : 5, - reo_push_reason : 2, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - cache_id : 1, - reserved_2a : 2, - return_buffer_manager : 4, - buffer_or_desc_type : 3, - bm_action : 3, - release_source_module : 3; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t buffer_phys_addr_31_0 : 32; - uint32_t looping_count : 4, - sw_buffer_cookie : 20, - buffer_phys_addr_39_32 : 8; -#endif -}; - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 - -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 - -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 - -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 - -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 - -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 - -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 - -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 - -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff - -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 - -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_buffer_ring.h deleted file mode 100644 index b1532e15595b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_buffer_ring.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_BUFFER_RING_H_ -#define _WBM_BUFFER_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 - -struct wbm_buffer_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_addr_info; -#else - struct buffer_addr_info buf_addr_info; -#endif -}; - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_link_descriptor_ring.h deleted file mode 100644 index 851807aa4c1c..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_link_descriptor_ring.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ -#define _WBM_LINK_DESCRIPTOR_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 - -struct wbm_link_descriptor_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info desc_addr_info; -#else - struct buffer_addr_info desc_addr_info; -#endif -}; - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring.h deleted file mode 100644 index e86d52753912..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_H_ -#define _WBM_RELEASE_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 - -struct wbm_release_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - reserved_2a : 3, - buffer_or_desc_type : 3, - reserved_2b : 22, - wbm_internal_error : 1; - uint32_t reserved_3a : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_5a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 28, - looping_count : 4; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t wbm_internal_error : 1, - reserved_2b : 22, - buffer_or_desc_type : 3, - reserved_2a : 3, - release_source_module : 3; - uint32_t reserved_3a : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_5a : 32; - uint32_t reserved_6a : 32; - uint32_t looping_count : 4, - reserved_7a : 28; -#endif -}; - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RESERVED_2A_LSB 3 -#define WBM_RELEASE_RING_RESERVED_2A_MSB 5 -#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 - -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RESERVED_2B_LSB 9 -#define WBM_RELEASE_RING_RESERVED_2B_MSB 30 -#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 - -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 - -#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c -#define WBM_RELEASE_RING_RESERVED_3A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_3A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 -#define WBM_RELEASE_RING_RESERVED_4A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_4A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 -#define WBM_RELEASE_RING_RESERVED_5A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_5A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 -#define WBM_RELEASE_RING_RESERVED_6A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_6A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c -#define WBM_RELEASE_RING_RESERVED_7A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_7A_MSB 27 -#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff - -#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 -#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 -#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_rx.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_rx.h deleted file mode 100644 index a68bc8115a82..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_rx.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_RX_H_ -#define _WBM_RELEASE_RING_RX_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 4 - -struct wbm_release_ring_rx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - buffer_or_desc_type : 3, - reserved_2a : 14, - mpdu_sequence_number : 12; - uint32_t reserved_3a : 32; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t mpdu_sequence_number : 12, - reserved_2a : 14, - buffer_or_desc_type : 3, - release_source_module : 3; - uint32_t reserved_3a : 32; -#endif -}; - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 3 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 5 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x00000038 - -#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 6 -#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 19 -#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x000fffc0 - -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_LSB 20 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MSB 31 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 - -#define WBM_RELEASE_RING_RX_RESERVED_3A_OFFSET 0x0000000c -#define WBM_RELEASE_RING_RX_RESERVED_3A_LSB 0 -#define WBM_RELEASE_RING_RX_RESERVED_3A_MSB 31 -#define WBM_RELEASE_RING_RX_RESERVED_3A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_tx.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_tx.h deleted file mode 100644 index d1412153c6ae..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_tx.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_TX_H_ -#define _WBM_RELEASE_RING_TX_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 4 - -struct wbm_release_ring_tx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - buffer_or_desc_type : 3, - reserved_2a : 26; - uint32_t tqm_status_number : 32; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t reserved_2a : 26, - buffer_or_desc_type : 3, - release_source_module : 3; - uint32_t tqm_status_number : 32; -#endif -}; - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 3 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 5 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x00000038 - -#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 6 -#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 31 -#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0xffffffc0 - -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 31 -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwiobase.h deleted file mode 100644 index 4e455f399300..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwiobase.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOBASE_H -#define WCSS_SEQ_HWIOBASE_H - -#define UMAC_NOC_BASE 0x140000 -#define UMAC_NOC_BASE_SIZE 0x00004480 -#define UMAC_NOC_BASE_PHYS 0x00140000 - -#define PHYA0_BASE 0x300000 -#define PHYA0_BASE_SIZE 0x00300000 -#define PHYA0_BASE_PHYS 0x00300000 - -#define PHYA1_BASE 0x600000 -#define PHYA1_BASE_SIZE 0x00300000 -#define PHYA1_BASE_PHYS 0x00600000 - -#define DMAC_BASE 0x900000 -#define DMAC_BASE_SIZE 0x00080000 -#define DMAC_BASE_PHYS 0x00900000 - -#define UMAC_BASE 0xa00000 -#define UMAC_BASE_SIZE 0x0004d000 -#define UMAC_BASE_PHYS 0x00a00000 - -#define PMAC0_BASE 0xa80000 -#define PMAC0_BASE_SIZE 0x00040000 -#define PMAC0_BASE_PHYS 0x00a80000 - -#define PMAC1_BASE 0xac0000 -#define PMAC1_BASE_SIZE 0x00040000 -#define PMAC1_BASE_PHYS 0x00ac0000 - -#define WFSS_AMCSS_BASE 0xb00000 -#define WFSS_AMCSS_BASE_SIZE 0x00040000 -#define WFSS_AMCSS_BASE_PHYS 0x00b00000 - -#define CXC_BASE 0xb40000 -#define CXC_BASE_SIZE 0x00010000 -#define CXC_BASE_PHYS 0x00b40000 - -#define WFSS_PMM_BASE 0xb50000 -#define WFSS_PMM_BASE_SIZE 0x00002401 -#define WFSS_PMM_BASE_PHYS 0x00b50000 - -#define WFSS_CC_BASE 0xb60000 -#define WFSS_CC_BASE_SIZE 0x00008000 -#define WFSS_CC_BASE_PHYS 0x00b60000 - -#define WCMN_CORE_BASE 0xb68000 -#define WCMN_CORE_BASE_SIZE 0x000008a9 -#define WCMN_CORE_BASE_PHYS 0x00b68000 - -#define WIFI_CFGBUS_APB_TSLV_BASE 0xb6b000 -#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000 -#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000 - -#define WFSS_CFGBUS_BASE 0xb6c000 -#define WFSS_CFGBUS_BASE_SIZE 0x000000a0 -#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000 - -#define WIFI_CFGBUS_AHB_TSLV_BASE 0xb6d000 -#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000 -#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000 - -#define UMAC_ACMT_BASE 0xb6e000 -#define UMAC_ACMT_BASE_SIZE 0x00001000 -#define UMAC_ACMT_BASE_PHYS 0x00b6e000 - -#define WCSS_CC_BASE 0xb80000 -#define WCSS_CC_BASE_SIZE 0x00010000 -#define WCSS_CC_BASE_PHYS 0x00b80000 - -#define PMM_TOP_BASE 0xb90000 -#define PMM_TOP_BASE_SIZE 0x00010000 -#define PMM_TOP_BASE_PHYS 0x00b90000 - -#define WCSS_TOP_CMN_BASE 0xba0000 -#define WCSS_TOP_CMN_BASE_SIZE 0x00004000 -#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000 - -#define WCSS_CFGBUS_BASE 0xba4000 -#define WCSS_CFGBUS_BASE_SIZE 0x00008000 -#define WCSS_CFGBUS_BASE_PHYS 0x00ba4000 - -#define MSIP_BASE 0xbb0000 -#define MSIP_BASE_SIZE 0x00010000 -#define MSIP_BASE_PHYS 0x00bb0000 - -#define RFA_BASE 0xbc0000 -#define RFA_BASE_SIZE 0x00040000 -#define RFA_BASE_PHYS 0x00bc0000 - -#define DBG_BASE 0x1000000 -#define DBG_BASE_SIZE 0x00100000 -#define DBG_BASE_PHYS 0x01000000 - -#define Q6SS_WLAN_BASE 0x1100000 -#define Q6SS_WLAN_BASE_SIZE 0x00100000 -#define Q6SS_WLAN_BASE_PHYS 0x01100000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_umac.h deleted file mode 100644 index 60d2a0b5099f..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_umac.h +++ /dev/null @@ -1,13579 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOREG_UMAC_H -#define WCSS_SEQ_HWIOREG_UMAC_H - -#include "seq_hwio.h" -#include "wcss_seq_hwiobase.h" -#ifdef SCALE_INCLUDES -#include "HALhwio.h" -#else -#include "msmhwio.h" -#endif - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x) ((x) + 0x1c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_PHYS(x) ((x) + 0x1c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_OFFS (0x1c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDRESS_RANGE_LIMIT_SHFT 30 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_WINDOW_SIZE_BMSK 0x38000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_WINDOW_SIZE_SHFT 27 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_RESET_CNT_BMSK 0x4000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_RESET_CNT_SHFT 26 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_CNTR_EN_BMSK 0x2000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_CNTR_EN_SHFT 25 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ID_BITMAP_BMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n) ((base) + 0X20 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_PHYS(base,n) ((base) + 0X20 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_OFFS(n) (0X20 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_ADDR(x) ((x) + 0x30) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_PHYS(x) ((x) + 0x30) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_OFFS (0x30) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_ADDR(x) ((x) + 0x34) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_PHYS(x) ((x) + 0x34) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_OFFS (0x34) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x) ((x) + 0x38) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_PHYS(x) ((x) + 0x38) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_OFFS (0x38) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDRESS_RANGE_LIMIT_SHFT 30 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_WINDOW_SIZE_BMSK 0x38000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_WINDOW_SIZE_SHFT 27 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_RESET_CNT_BMSK 0x4000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_RESET_CNT_SHFT 26 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_CNTR_EN_BMSK 0x2000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_CNTR_EN_SHFT 25 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ID_BITMAP_BMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n) ((base) + 0X3C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_PHYS(base,n) ((base) + 0X3C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_OFFS(n) (0X3C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_ADDR(x) ((x) + 0x4c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_PHYS(x) ((x) + 0x4c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_OFFS (0x4c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_ADDR(x) ((x) + 0x50) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_PHYS(x) ((x) + 0x50) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_OFFS (0x50) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x) ((x) + 0x54) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_PHYS(x) ((x) + 0x54) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_OFFS (0x54) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDRESS_RANGE_LIMIT_SHFT 30 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_WINDOW_SIZE_BMSK 0x38000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_WINDOW_SIZE_SHFT 27 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_RESET_CNT_BMSK 0x4000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_RESET_CNT_SHFT 26 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_CNTR_EN_BMSK 0x2000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_CNTR_EN_SHFT 25 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ID_BITMAP_BMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n) ((base) + 0X58 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_PHYS(base,n) ((base) + 0X58 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_OFFS(n) (0X58 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_ADDR(x) ((x) + 0x68) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_PHYS(x) ((x) + 0x68) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_OFFS (0x68) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_ADDR(x) ((x) + 0x6c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_PHYS(x) ((x) + 0x6c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_OFFS (0x6c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x) ((x) + 0x70) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_PHYS(x) ((x) + 0x70) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_OFFS (0x70) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDRESS_RANGE_LIMIT_SHFT 30 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_WINDOW_SIZE_BMSK 0x38000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_WINDOW_SIZE_SHFT 27 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_RESET_CNT_BMSK 0x4000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_RESET_CNT_SHFT 26 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_CNTR_EN_BMSK 0x2000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_CNTR_EN_SHFT 25 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ID_BITMAP_BMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n) ((base) + 0X74 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_PHYS(base,n) ((base) + 0X74 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_OFFS(n) (0X74 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_ADDR(x) ((x) + 0x84) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_PHYS(x) ((x) + 0x84) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_OFFS (0x84) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_ADDR(x) ((x) + 0x88) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_PHYS(x) ((x) + 0x88) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_OFFS (0x88) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n) ((base) + 0X94 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_PHYS(base,n) ((base) + 0X94 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_OFFS(n) (0X94 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n) ((base) + 0XB0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_PHYS(base,n) ((base) + 0XB0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_OFFS(n) (0XB0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x) ((x) + 0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x) ((x) + 0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS (0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK 0x7 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK 0x7 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x) ((x) + 0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x) ((x) + 0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS (0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR 0x00001ffe -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK 0x1ffe000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT 13 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK 0x1ffe -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT 1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_DATA_FIFORAM_BMSK 0x2000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_DATA_FIFORAM_SHFT 13 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK 0x1000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT 12 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK 0x800 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT 11 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK 0x400 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT 10 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK 0x200 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT 9 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x) ((x) + 0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x) ((x) + 0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS (0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK 0xff000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT 24 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK 0xff0000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT 16 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK 0xff00 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT 8 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK 0xff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_SNAPSHOT_ENABLE_BMSK 0x2 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_SNAPSHOT_ENABLE_SHFT 1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n) ((base) + 0X138 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_PHYS(base,n) ((base) + 0X138 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_OFFS(n) (0X138 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n) ((base) + 0X14C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_PHYS(base,n) ((base) + 0X14C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_OFFS(n) (0X14C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_FREEZE_EN_BMSK 0x40000000 -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_FREEZE_EN_SHFT 30 -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n) ((base) + 0X1B8 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_PHYS(base,n) ((base) + 0X1B8 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_OFFS(n) (0X1B8 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n) ((base) + 0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n) ((base) + 0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n) (0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK 0xfff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn 31 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK 0xfff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT 0 - -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x) ((x) + 0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x) ((x) + 0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS (0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK 0x3 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x)) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK 0x2 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT 1 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n) ((base) + 0X364 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_PHYS(base,n) ((base) + 0X364 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_OFFS(n) (0X364 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_POR 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n) ((base) + 0X36C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_PHYS(base,n) ((base) + 0X36C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_OFFS(n) (0X36C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_POR 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_ADDR(x) ((x) + 0x374) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_PHYS(x) ((x) + 0x374) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_OFFS (0x374) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_RMSK 0xffffff7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_POR 0x7ffff07f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWVALID_BMSK 0x80000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWVALID_SHFT 31 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWADDR_22_4_BMSK 0x7ffff000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWADDR_22_4_SHFT 12 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWREADY_BMSK 0x800 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWREADY_SHFT 11 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WVALID_BMSK 0x400 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WVALID_SHFT 10 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WREADY_BMSK 0x200 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WREADY_SHFT 9 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WLAST_BMSK 0x100 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WLAST_SHFT 8 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_BID_BMSK 0x7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_BID_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_ADDR(x) ((x) + 0x378) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_PHYS(x) ((x) + 0x378) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_OFFS (0x378) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_REM_ADDR_WCOUNT_BMSK 0xfff80000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_REM_ADDR_WCOUNT_SHFT 19 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_REM_DATA_WCOUNT_BMSK 0x7ffc0 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_REM_DATA_WCOUNT_SHFT 6 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_AXI_PENDING_CNT_BMSK 0x3f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_AXI_PENDING_CNT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_ADDR(x) ((x) + 0x37c) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_PHYS(x) ((x) + 0x37c) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_OFFS (0x37c) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_RMSK 0x7fffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_PREFIL_CNT_BMSK 0x70000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_PREFIL_CNT_SHFT 28 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_WR_BMSK 0x8000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_WR_SHFT 27 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_WR_ADDR_BMSK 0x7e00000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_WR_ADDR_SHFT 21 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_RD_BMSK 0x100000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_RD_SHFT 20 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_RD_ADDR_BMSK 0xfc000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_RD_ADDR_SHFT 14 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_WR_BMSK 0x2000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_WR_SHFT 13 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_WR_ADDR_BMSK 0x1f80 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_WR_ADDR_SHFT 7 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_RD_BMSK 0x40 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_RD_SHFT 6 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_RD_ADDR_BMSK 0x3f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_RD_ADDR_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_ADDR(x) ((x) + 0x380) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_PHYS(x) ((x) + 0x380) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_OFFS (0x380) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_RMSK 0x1ffff7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_POR 0x00044f7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_STATE_BMSK 0x1fc0000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_STATE_SHFT 18 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_ADDR_STATE_BMSK 0x3c000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_ADDR_STATE_SHFT 14 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_FLUSH_DONE_BMSK 0x2000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_FLUSH_DONE_SHFT 13 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_FLUSH_BMSK 0x1000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_FLUSH_SHFT 12 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_PHASE_SUBID_BMSK 0xf00 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_PHASE_SUBID_SHFT 8 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_PHASE_ID_BMSK 0x7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_PHASE_ID_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_ADDR(x) ((x) + 0x384) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_PHYS(x) ((x) + 0x384) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_OFFS (0x384) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_POR 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_WR_DATA_PHASE_ADDR_31_0_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_WR_DATA_PHASE_ADDR_31_0_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_ADDR(x) ((x) + 0x388) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_PHYS(x) ((x) + 0x388) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_OFFS (0x388) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_RMSK 0x1fffff7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_POR 0x00e04f7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_AXI_WR_IF_BRESP_BMSK 0x18000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_AXI_WR_IF_BRESP_SHFT 27 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_AXI_WR_IF_BVALID_BMSK 0x4000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_AXI_WR_IF_BVALID_SHFT 26 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_MAX_OT_REACHED_BMSK 0x2000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_MAX_OT_REACHED_SHFT 25 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_GXI_BACKPRESSURE_BMSK 0x1000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_GXI_BACKPRESSURE_SHFT 24 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_GXI_IDLE_BMSK 0x800000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_GXI_IDLE_SHFT 23 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_DATA_IDLE_BMSK 0x400000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_DATA_IDLE_SHFT 22 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_IDLE_BMSK 0x200000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_IDLE_SHFT 21 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_AXI_PENDING_CNT_DATA_BMSK 0x1f8000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_AXI_PENDING_CNT_DATA_SHFT 15 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_CMD_FIFO_EMPTY_BMSK 0x4000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_CMD_FIFO_EMPTY_SHFT 14 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_CMD_FIFO_FULL_BMSK 0x2000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_CMD_FIFO_FULL_SHFT 13 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_DATA_FIFO_FULL_BMSK 0x1000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_DATA_FIFO_FULL_SHFT 12 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_PHASE_SUBID_BMSK 0xf00 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_PHASE_SUBID_SHFT 8 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_PHASE_ID_BMSK 0x7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_PHASE_ID_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_ADDR(x) ((x) + 0x38c) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_PHYS(x) ((x) + 0x38c) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_OFFS (0x38c) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_POR 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_WR_ADDR_PHASE_ADDR_31_0_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_WR_ADDR_PHASE_ADDR_31_0_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_ADDR(x) ((x) + 0x390) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_PHYS(x) ((x) + 0x390) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_OFFS (0x390) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_RMSK 0xffffff7f -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_POR 0x7ffff07f -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARVALID_BMSK 0x80000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARVALID_SHFT 31 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARADDR_22_4_BMSK 0x7ffff000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARADDR_22_4_SHFT 12 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARREADY_BMSK 0x800 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARREADY_SHFT 11 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RVALID_BMSK 0x400 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RVALID_SHFT 10 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RREADY_BMSK 0x200 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RREADY_SHFT 9 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RLAST_BMSK 0x100 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RLAST_SHFT 8 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RID_BMSK 0x7f -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RID_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_ADDR(x) ((x) + 0x394) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_PHYS(x) ((x) + 0x394) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_OFFS (0x394) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RMSK 0xfffff7ff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_POR 0x800007ff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_DATA_FIFO_EMPTY_BMSK 0x80000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_DATA_FIFO_EMPTY_SHFT 31 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_DATA_FIFO_FULL_BMSK 0x40000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_DATA_FIFO_FULL_SHFT 30 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_REM_ADDR_WCOUNT_BMSK 0x3ffc0000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_REM_ADDR_WCOUNT_SHFT 18 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_AXI_PENDING_CNT_BMSK 0x3f000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_AXI_PENDING_CNT_SHFT 12 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_CMD_FIFO_RDATA_ID_BMSK 0x7f0 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_CMD_FIFO_RDATA_ID_SHFT 4 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_CMD_FIFO_RDATA_SUB_ID_BMSK 0xf -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_CMD_FIFO_RDATA_SUB_ID_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_ADDR(x) ((x) + 0x398) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_PHYS(x) ((x) + 0x398) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_OFFS (0x398) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_POR 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_RD_CMD_FIFO_RDATA_ADDR_31_0_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_RD_CMD_FIFO_RDATA_ADDR_31_0_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_ADDR(x) ((x) + 0x39c) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_PHYS(x) ((x) + 0x39c) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_OFFS (0x39c) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_POR 0x3fe04002 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_STATE_BMSK 0xe0000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_STATE_SHFT 29 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_RDATA_ADDR_39_32_BMSK 0x1fe00000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_RDATA_ADDR_39_32_SHFT 21 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_AXI_RD_IF_INT_RREADY_BMSK 0x100000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_AXI_RD_IF_INT_RREADY_SHFT 20 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_MAX_OUTSTANDING_REACHED_BMSK 0x80000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_MAX_OUTSTANDING_REACHED_SHFT 19 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_AXI_RD_IF_RRESP_BMSK 0x60000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_AXI_RD_IF_RRESP_SHFT 17 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_DATA_FLUSH_BMSK 0x10000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_DATA_FLUSH_SHFT 16 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_DATA_FLUSH_DONE_BMSK 0x8000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_DATA_FLUSH_DONE_SHFT 15 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_IDLE_BMSK 0x4000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_IDLE_SHFT 14 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_WR_ADDR_BMSK 0x3f00 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_WR_ADDR_SHFT 8 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_RD_ADDR_BMSK 0xfc -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_RD_ADDR_SHFT 2 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_EMPTY_BMSK 0x2 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_EMPTY_SHFT 1 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_FULL_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_FULL_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x) ((x) + 0x3a0) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_PHYS(x) ((x) + 0x3a0) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_OFFS (0x3a0) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_RMSK 0x3ff -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_POR 0x0000014a -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_WR_LATENCY_VAL_BMSK 0x3e0 -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_WR_LATENCY_VAL_SHFT 5 -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_RD_LATENCY_VAL_BMSK 0x1f -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_RD_LATENCY_VAL_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x) ((x) + 0x3a4) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_PHYS(x) ((x) + 0x3a4) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_OFFS (0x3a4) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_RMSK 0xf -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_POR 0x00000001 -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_RD_DATA_WORD_SEL_BITMAP_BMSK 0xf -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_RD_DATA_WORD_SEL_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n) (0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn 63 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) -#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x40) -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x130) -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x134) -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x138) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x13c) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x140) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x144) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x148) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x14c) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x150) -#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x24c) -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0x51c) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0x52c) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS (0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK 0x3f -#define HWIO_WBM_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK 0x20 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT 5 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK 0x10 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT 4 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x) ((x) + 0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x) ((x) + 0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS (0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK 0xffffffff -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR 0x00000000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR 0x3 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x) \ - in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x)) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v) \ - out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x)) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK 0xffe00000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT 21 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK 0x1f0000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT 16 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK 0xf800 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT 11 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK 0x7c0 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT 6 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK 0x3e -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT 1 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK 0x1 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT 0 - -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x3ff -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000020 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK 0x200 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT 9 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK 0x100 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT 8 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn 255 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010) -#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x3040) -#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) -#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x) ((x) + 0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x) ((x) + 0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS (0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR 0x76043210 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x) ((x) + 0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x) ((x) + 0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS (0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x6666ba98 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x) ((x) + 0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x) ((x) + 0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS (0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR 0x66666666 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x) ((x) + 0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x) ((x) + 0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS (0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR 0x66666666 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x38) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x3c) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x) ((x) + 0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x) ((x) + 0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS (0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR 0x00000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR 0x3 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x) ((x) + 0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x) ((x) + 0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS (0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR 0x00000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR 0x3 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT 0 - -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x) ((x) + 0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x) ((x) + 0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS (0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK 0x1ffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR 0x00000000 -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR 0x3 -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x) \ - in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v) \ - out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK 0x1ffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT 0 - -#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x6c) -#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x70) -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 -#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 -#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff -#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 - -#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x344) -#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x524) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_PHYS(x) ((x) + 0x524) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_OFFS (0x524) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x) ((x) + 0x528) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_PHYS(x) ((x) + 0x528) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_OFFS (0x528) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_ID_ADDR(x) ((x) + 0x52c) -#define HWIO_REO_R0_FW2REO_RING_ID_PHYS(x) ((x) + 0x52c) -#define HWIO_REO_R0_FW2REO_RING_ID_OFFS (0x52c) -#define HWIO_REO_R0_FW2REO_RING_ID_RMSK 0xff -#define HWIO_REO_R0_FW2REO_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_ID_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_ID_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_ID_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_FW2REO_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_STATUS_ADDR(x) ((x) + 0x530) -#define HWIO_REO_R0_FW2REO_RING_STATUS_PHYS(x) ((x) + 0x530) -#define HWIO_REO_R0_FW2REO_RING_STATUS_OFFS (0x530) -#define HWIO_REO_R0_FW2REO_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_FW2REO_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_FW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_FW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x) ((x) + 0x534) -#define HWIO_REO_R0_FW2REO_RING_MISC_PHYS(x) ((x) + 0x534) -#define HWIO_REO_R0_FW2REO_RING_MISC_OFFS (0x534) -#define HWIO_REO_R0_FW2REO_RING_MISC_RMSK 0x7fffff -#define HWIO_REO_R0_FW2REO_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_FW2REO_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MISC_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_FW2REO_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_REO_R0_FW2REO_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_FW2REO_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_FW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_FW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_FW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_FW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_FW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_FW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_FW2REO_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_FW2REO_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_FW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_FW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_FW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_FW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x540) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x540) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_OFFS (0x540) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x544) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x544) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_OFFS (0x544) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x554) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x554) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x554) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x558) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x558) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x558) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x55c) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x55c) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_OFFS (0x55c) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x560) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x560) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x560) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x564) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x564) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x564) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x568) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x568) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x568) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x56c) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x56c) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_OFFS (0x56c) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x570) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x570) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_OFFS (0x570) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x) ((x) + 0x574) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_PHYS(x) ((x) + 0x574) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_OFFS (0x574) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x594) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x594) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_OFFS (0x594) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x) ((x) + 0x598) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_PHYS(x) ((x) + 0x598) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_OFFS (0x598) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_FW2REO_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_FW2REO_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_FW2REO_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x) ((x) + 0x59c) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_PHYS(x) ((x) + 0x59c) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_OFFS (0x59c) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x) ((x) + 0x5a0) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_PHYS(x) ((x) + 0x5a0) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_OFFS (0x5a0) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x) ((x) + 0x5a4) -#define HWIO_REO_R0_FW2REO1_RING_ID_PHYS(x) ((x) + 0x5a4) -#define HWIO_REO_R0_FW2REO1_RING_ID_OFFS (0x5a4) -#define HWIO_REO_R0_FW2REO1_RING_ID_RMSK 0xff -#define HWIO_REO_R0_FW2REO1_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_ID_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_FW2REO1_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_STATUS_ADDR(x) ((x) + 0x5a8) -#define HWIO_REO_R0_FW2REO1_RING_STATUS_PHYS(x) ((x) + 0x5a8) -#define HWIO_REO_R0_FW2REO1_RING_STATUS_OFFS (0x5a8) -#define HWIO_REO_R0_FW2REO1_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_FW2REO1_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_FW2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_FW2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x) ((x) + 0x5ac) -#define HWIO_REO_R0_FW2REO1_RING_MISC_PHYS(x) ((x) + 0x5ac) -#define HWIO_REO_R0_FW2REO1_RING_MISC_OFFS (0x5ac) -#define HWIO_REO_R0_FW2REO1_RING_MISC_RMSK 0x7fffff -#define HWIO_REO_R0_FW2REO1_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_FW2REO1_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MISC_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_FW2REO1_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_FW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_FW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_FW2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_FW2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_FW2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_FW2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_FW2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_FW2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_FW2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_FW2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x5b8) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x5b8) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_OFFS (0x5b8) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x5bc) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x5bc) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_OFFS (0x5bc) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x5cc) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x5cc) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x5cc) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x5d0) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x5d0) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x5d0) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x5d4) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x5d4) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_OFFS (0x5d4) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x5d8) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x5d8) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x5d8) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x5dc) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x5dc) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x5dc) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x5e0) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x5e0) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x5e0) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x5e4) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x5e4) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_OFFS (0x5e4) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x5e8) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x5e8) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_OFFS (0x5e8) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x) ((x) + 0x5ec) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_PHYS(x) ((x) + 0x5ec) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_OFFS (0x5ec) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x60c) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x60c) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_OFFS (0x60c) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x) ((x) + 0x610) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_PHYS(x) ((x) + 0x610) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_OFFS (0x610) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x7d0) -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x7d4) -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x7d8) -#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x7e0) -#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x7e4) -#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x7e8) -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7f4) -#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x818) -#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x81c) -#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x820) -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x824) -#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x828) -#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x82c) -#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x830) -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x844) -#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x848) -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 -#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW7_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW7_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW8_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW8_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x) ((x) + 0xb90) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_PHYS(x) ((x) + 0xb90) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_OFFS (0xb90) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x) ((x) + 0xb94) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_PHYS(x) ((x) + 0xb94) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_OFFS (0xb94) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RMSK 0xfffffff -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x) ((x) + 0xb98) -#define HWIO_REO_R0_REO2SW9_RING_ID_PHYS(x) ((x) + 0xb98) -#define HWIO_REO_R0_REO2SW9_RING_ID_OFFS (0xb98) -#define HWIO_REO_R0_REO2SW9_RING_ID_RMSK 0xffff -#define HWIO_REO_R0_REO2SW9_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_ID_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_REO_R0_REO2SW9_RING_ID_RING_ID_SHFT 8 -#define HWIO_REO_R0_REO2SW9_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_REO2SW9_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_STATUS_ADDR(x) ((x) + 0xb9c) -#define HWIO_REO_R0_REO2SW9_RING_STATUS_PHYS(x) ((x) + 0xb9c) -#define HWIO_REO_R0_REO2SW9_RING_STATUS_OFFS (0xb9c) -#define HWIO_REO_R0_REO2SW9_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_REO2SW9_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW9_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_REO2SW9_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_REO2SW9_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x) ((x) + 0xba0) -#define HWIO_REO_R0_REO2SW9_RING_MISC_PHYS(x) ((x) + 0xba0) -#define HWIO_REO_R0_REO2SW9_RING_MISC_OFFS (0xba0) -#define HWIO_REO_R0_REO2SW9_RING_MISC_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_REO2SW9_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MISC_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW9_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW9_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_REO_R0_REO2SW9_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_REO2SW9_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_REO2SW9_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_REO2SW9_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_REO2SW9_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_REO2SW9_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_REO2SW9_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_REO2SW9_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_REO2SW9_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_REO2SW9_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_REO2SW9_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xba4) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xba4) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_OFFS (0xba4) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xba8) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xba8) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_OFFS (0xba8) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xbb4) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xbb4) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_OFFS (0xbb4) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xbb8) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xbb8) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_OFFS (0xbb8) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xbbc) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xbbc) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_OFFS (0xbbc) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xbd8) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xbd8) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_OFFS (0xbd8) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xbdc) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xbdc) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_OFFS (0xbdc) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x) ((x) + 0xbe0) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_PHYS(x) ((x) + 0xbe0) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_OFFS (0xbe0) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xbe4) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xbe4) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_OFFS (0xbe4) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xbe8) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xbe8) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_OFFS (0xbe8) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xbec) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xbec) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_OFFS (0xbec) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x) ((x) + 0xbf0) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_PHYS(x) ((x) + 0xbf0) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_OFFS (0xbf0) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xc00) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xc00) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_OFFS (0xc00) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x) ((x) + 0xc04) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_PHYS(x) ((x) + 0xc04) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_OFFS (0xc04) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0xc08) -#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_REO2SW0_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW0_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x) ((x) + 0x126c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_PHYS(x) ((x) + 0x126c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_OFFS (0x126c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x) ((x) + 0x1270) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_PHYS(x) ((x) + 0x1270) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_OFFS (0x1270) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x) ((x) + 0x1274) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_PHYS(x) ((x) + 0x1274) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_OFFS (0x1274) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_RMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_ID_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_ADDR(x) ((x) + 0x1278) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_PHYS(x) ((x) + 0x1278) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_OFFS (0x1278) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x) ((x) + 0x127c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_PHYS(x) ((x) + 0x127c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_OFFS (0x127c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_RMSK 0x7fffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1288) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1288) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_OFFS (0x1288) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x128c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x128c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_OFFS (0x128c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x129c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x129c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x129c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x12a0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x12a0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x12a0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x12a4) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x12a4) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_OFFS (0x12a4) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x12a8) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x12a8) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x12a8) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x12ac) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x12ac) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x12ac) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x12b0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x12b0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x12b0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x12b4) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x12b4) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_OFFS (0x12b4) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x12b8) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x12b8) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_OFFS (0x12b8) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x) ((x) + 0x12bc) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_PHYS(x) ((x) + 0x12bc) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_OFFS (0x12bc) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x12dc) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x12dc) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_OFFS (0x12dc) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x) ((x) + 0x12e0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_PHYS(x) ((x) + 0x12e0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_OFFS (0x12e0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x) ((x) + 0x12e4) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_PHYS(x) ((x) + 0x12e4) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_OFFS (0x12e4) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x) ((x) + 0x12e8) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_PHYS(x) ((x) + 0x12e8) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_OFFS (0x12e8) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x) ((x) + 0x12ec) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_PHYS(x) ((x) + 0x12ec) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_OFFS (0x12ec) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_RMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_ID_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_ADDR(x) ((x) + 0x12f0) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_PHYS(x) ((x) + 0x12f0) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_OFFS (0x12f0) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x) ((x) + 0x12f4) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_PHYS(x) ((x) + 0x12f4) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_OFFS (0x12f4) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_RMSK 0x7fffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1300) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1300) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_OFFS (0x1300) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x1304) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x1304) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_OFFS (0x1304) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x1314) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x1314) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x1314) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x1318) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x1318) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x1318) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x131c) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x131c) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_OFFS (0x131c) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x1320) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x1320) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x1320) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x1324) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x1324) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x1324) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x1328) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x1328) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x1328) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x132c) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x132c) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_OFFS (0x132c) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1330) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1330) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_OFFS (0x1330) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x) ((x) + 0x1334) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_PHYS(x) ((x) + 0x1334) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_OFFS (0x1334) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1354) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1354) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_OFFS (0x1354) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x) ((x) + 0x1358) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_PHYS(x) ((x) + 0x1358) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_OFFS (0x1358) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x) ((x) + 0x135c) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_PHYS(x) ((x) + 0x135c) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_OFFS (0x135c) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x) ((x) + 0x1360) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_PHYS(x) ((x) + 0x1360) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_OFFS (0x1360) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x) ((x) + 0x1364) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_PHYS(x) ((x) + 0x1364) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_OFFS (0x1364) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_ID_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_RING_ID_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_ADDR(x) ((x) + 0x1368) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_PHYS(x) ((x) + 0x1368) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_OFFS (0x1368) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x) ((x) + 0x136c) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_PHYS(x) ((x) + 0x136c) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_OFFS (0x136c) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x1370) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x1370) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_OFFS (0x1370) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x1374) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x1374) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_OFFS (0x1374) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x1380) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x1380) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_OFFS (0x1380) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x1384) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x1384) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_OFFS (0x1384) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x1388) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x1388) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_OFFS (0x1388) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x13a4) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x13a4) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_OFFS (0x13a4) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x13a8) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x13a8) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_OFFS (0x13a8) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x) ((x) + 0x13ac) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_PHYS(x) ((x) + 0x13ac) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_OFFS (0x13ac) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x13b0) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x13b0) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_OFFS (0x13b0) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x13b4) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x13b4) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_OFFS (0x13b4) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x13b8) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x13b8) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_OFFS (0x13b8) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x) ((x) + 0x13bc) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_PHYS(x) ((x) + 0x13bc) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_OFFS (0x13bc) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x13cc) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x13cc) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_OFFS (0x13cc) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x) ((x) + 0x13d0) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_PHYS(x) ((x) + 0x13d0) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_OFFS (0x13d0) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x) ((x) + 0x13d4) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_PHYS(x) ((x) + 0x13d4) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_OFFS (0x13d4) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x) ((x) + 0x13d8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_PHYS(x) ((x) + 0x13d8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_OFFS (0x13d8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x) ((x) + 0x13dc) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_PHYS(x) ((x) + 0x13dc) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_OFFS (0x13dc) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_ID_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_RING_ID_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_ADDR(x) ((x) + 0x13e0) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_PHYS(x) ((x) + 0x13e0) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_OFFS (0x13e0) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x) ((x) + 0x13e4) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_PHYS(x) ((x) + 0x13e4) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_OFFS (0x13e4) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x13e8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x13e8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_OFFS (0x13e8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x13ec) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x13ec) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_OFFS (0x13ec) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x13f8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x13f8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_OFFS (0x13f8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x13fc) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x13fc) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_OFFS (0x13fc) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x1400) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x1400) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_OFFS (0x1400) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x141c) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x141c) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_OFFS (0x141c) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1420) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1420) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_OFFS (0x1420) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x) ((x) + 0x1424) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_PHYS(x) ((x) + 0x1424) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_OFFS (0x1424) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x1428) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x1428) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_OFFS (0x1428) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x142c) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x142c) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_OFFS (0x142c) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x1430) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x1430) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_OFFS (0x1430) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x) ((x) + 0x1434) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_PHYS(x) ((x) + 0x1434) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_OFFS (0x1434) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1444) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1444) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_OFFS (0x1444) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x) ((x) + 0x1448) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_PHYS(x) ((x) + 0x1448) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_OFFS (0x1448) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_SW2FW_REO1_P_RING_BACK_PRESSURE_BMSK 0x10000 -#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_SW2FW_REO1_P_RING_BACK_PRESSURE_SHFT 16 -#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_SW2FW_REO0_P_RING_BACK_PRESSURE_BMSK 0x8000 -#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_SW2FW_REO0_P_RING_BACK_PRESSURE_SHFT 15 -#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW9_RING_BACK_PRESSURE_BMSK 0x4000 -#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW9_RING_BACK_PRESSURE_SHFT 14 -#define HWIO_REO_R0_MISC_CFG_ADDR(x) ((x) + 0x1458) -#define HWIO_REO_R0_MISC_CFG_PHYS(x) ((x) + 0x1458) -#define HWIO_REO_R0_MISC_CFG_OFFS (0x1458) -#define HWIO_REO_R0_MISC_CFG_RMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_POR 0x00000000 -#define HWIO_REO_R0_MISC_CFG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MISC_CFG_ATTR 0x3 -#define HWIO_REO_R0_MISC_CFG_IN(x) \ - in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x)) -#define HWIO_REO_R0_MISC_CFG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m) -#define HWIO_REO_R0_MISC_CFG_OUT(x, v) \ - out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v) -#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x)) -#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT 0 - -#define HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x) ((x) + 0x145c) -#define HWIO_REO_R0_MISC_CFG_BN_1_PHYS(x) ((x) + 0x145c) -#define HWIO_REO_R0_MISC_CFG_BN_1_OFFS (0x145c) -#define HWIO_REO_R0_MISC_CFG_BN_1_RMSK 0x3cfff -#define HWIO_REO_R0_MISC_CFG_BN_1_POR 0x00000801 -#define HWIO_REO_R0_MISC_CFG_BN_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MISC_CFG_BN_1_ATTR 0x3 -#define HWIO_REO_R0_MISC_CFG_BN_1_IN(x) \ - in_dword(HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x)) -#define HWIO_REO_R0_MISC_CFG_BN_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x), m) -#define HWIO_REO_R0_MISC_CFG_BN_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x),v) -#define HWIO_REO_R0_MISC_CFG_BN_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_BN_1_IN(x)) -#define HWIO_REO_R0_MISC_CFG_BN_1_NULL_BUFFER_ERROR_DEST_RING_BMSK 0x3c000 -#define HWIO_REO_R0_MISC_CFG_BN_1_NULL_BUFFER_ERROR_DEST_RING_SHFT 14 -#define HWIO_REO_R0_MISC_CFG_BN_1_STOP_DELINKING_DURING_CORRUPTION_BMSK 0x800 -#define HWIO_REO_R0_MISC_CFG_BN_1_STOP_DELINKING_DURING_CORRUPTION_SHFT 11 -#define HWIO_REO_R0_MISC_CFG_BN_1_MSDU_LINK_SHARING_BW_MPDU_FEATURE_ENABLE_BMSK 0x400 -#define HWIO_REO_R0_MISC_CFG_BN_1_MSDU_LINK_SHARING_BW_MPDU_FEATURE_ENABLE_SHFT 10 -#define HWIO_REO_R0_MISC_CFG_BN_1_ADDITIONAL_BMSK 0x3c0 -#define HWIO_REO_R0_MISC_CFG_BN_1_ADDITIONAL_SHFT 6 -#define HWIO_REO_R0_MISC_CFG_BN_1_ACCUM_RESOLUTION_BMSK 0x20 -#define HWIO_REO_R0_MISC_CFG_BN_1_ACCUM_RESOLUTION_SHFT 5 -#define HWIO_REO_R0_MISC_CFG_BN_1_RX_RXDMA_ERROR_COMPLETION_EN_BMSK 0x10 -#define HWIO_REO_R0_MISC_CFG_BN_1_RX_RXDMA_ERROR_COMPLETION_EN_SHFT 4 -#define HWIO_REO_R0_MISC_CFG_BN_1_RX_REO_ERROR_COMPLETION_EN_BMSK 0x8 -#define HWIO_REO_R0_MISC_CFG_BN_1_RX_REO_ERROR_COMPLETION_EN_SHFT 3 -#define HWIO_REO_R0_MISC_CFG_BN_1_NULL_OUT_MSDU_LINK_BEFORE_RELEASE_TO_WBM_BMSK 0x4 -#define HWIO_REO_R0_MISC_CFG_BN_1_NULL_OUT_MSDU_LINK_BEFORE_RELEASE_TO_WBM_SHFT 2 -#define HWIO_REO_R0_MISC_CFG_BN_1_MSDU_FETCH_GXI_OPTIMISATION_BMSK 0x2 -#define HWIO_REO_R0_MISC_CFG_BN_1_MSDU_FETCH_GXI_OPTIMISATION_SHFT 1 -#define HWIO_REO_R0_MISC_CFG_BN_1_REO_LITE_EN_BMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_BN_1_REO_LITE_EN_SHFT 0 - -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x) ((x) + 0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_PHYS(x) ((x) + 0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OFFS (0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_RMSK 0x7ff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR 0x000003ff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR_RMSK 0xffffffff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ATTR 0x3 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x) \ - in_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x)) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x), m) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUT(x, v) \ - out_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),v) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),m,v,HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x)) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_BMSK 0x400 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_SHFT 10 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_BMSK 0x200 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_SHFT 9 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_BMSK 0x100 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_SHFT 8 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_BMSK 0x80 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_SHFT 7 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_BMSK 0x40 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_SHFT 6 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_BMSK 0x20 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_SHFT 5 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_BMSK 0x10 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_SHFT 4 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_BMSK 0x8 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_SHFT 3 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_BMSK 0x4 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_SHFT 2 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_BMSK 0x2 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_SHFT 1 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_BMSK 0x1 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_SHFT 0 - -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x) ((x) + 0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x) ((x) + 0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS (0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK 0x1ff -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR 0x0000002d -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR 0x3 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x) \ - in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v) \ - out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK 0x1fe -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT 1 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK 0x1 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT 0 - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0x1468) -#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0x146c) -#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0x1470) -#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0x1474) -#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0x14dc) -#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 -#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 -#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 -#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 -#define HWIO_REO_R0_MISC_CTL_2_REO2SW9_RING_PRIORITY_BMSK 0x30000000 -#define HWIO_REO_R0_MISC_CTL_2_REO2SW9_RING_PRIORITY_SHFT 28 -#define HWIO_REO_R0_MISC_CTL_5_ADDR(x) ((x) + 0x14ec) -#define HWIO_REO_R0_MISC_CTL_5_PHYS(x) ((x) + 0x14ec) -#define HWIO_REO_R0_MISC_CTL_5_OFFS (0x14ec) -#define HWIO_REO_R0_MISC_CTL_5_RMSK 0x3f -#define HWIO_REO_R0_MISC_CTL_5_POR 0x00000000 -#define HWIO_REO_R0_MISC_CTL_5_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MISC_CTL_5_ATTR 0x3 -#define HWIO_REO_R0_MISC_CTL_5_IN(x) \ - in_dword(HWIO_REO_R0_MISC_CTL_5_ADDR(x)) -#define HWIO_REO_R0_MISC_CTL_5_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MISC_CTL_5_ADDR(x), m) -#define HWIO_REO_R0_MISC_CTL_5_OUT(x, v) \ - out_dword(HWIO_REO_R0_MISC_CTL_5_ADDR(x),v) -#define HWIO_REO_R0_MISC_CTL_5_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_5_ADDR(x),m,v,HWIO_REO_R0_MISC_CTL_5_IN(x)) -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO1_C_VC_ID_BMSK 0x20 -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO1_C_VC_ID_SHFT 5 -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO0_C_VC_ID_BMSK 0x10 -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO0_C_VC_ID_SHFT 4 -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO1_P_RING_PRIORITY_BMSK 0xc -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO1_P_RING_PRIORITY_SHFT 2 -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO0_P_RING_PRIORITY_BMSK 0x3 -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO0_P_RING_PRIORITY_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) ((x) + 0x16b4) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) ((x) + 0x16b4) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_OFFS (0x16b4) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_IN(x)) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 16 -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0xf -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_REO_R0_CREDIT_ADDR(x) ((x) + 0x16d0) -#define HWIO_REO_R0_CREDIT_PHYS(x) ((x) + 0x16d0) -#define HWIO_REO_R0_CREDIT_OFFS (0x16d0) -#define HWIO_REO_R0_CREDIT_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_POR 0x00000000 -#define HWIO_REO_R0_CREDIT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_ATTR 0x3 -#define HWIO_REO_R0_CREDIT_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_ADDR(x)) -#define HWIO_REO_R0_CREDIT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_OUT(x, v) \ - out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v) -#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x)) -#define HWIO_REO_R0_CREDIT_VAL_BMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_VAL_SHFT 0 - -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x) ((x) + 0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x) ((x) + 0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS (0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK 0x7 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR 0x00000002 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR 0x3 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x)) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v) \ - out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x)) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK 0x7 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT 0 - -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x) ((x) + 0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x) ((x) + 0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS (0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR 0x00000000 -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR 0x1 -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x)) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT 0 - -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_CMD_FIFO_MEM_BMSK 0x2000000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_CMD_FIFO_MEM_SHFT 25 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM3_BMSK 0x1000000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM3_SHFT 24 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM222_BMSK 0x800000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM222_SHFT 23 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM1_BMSK 0x400000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM1_SHFT 22 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM0_BMSK 0x200000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM0_SHFT 21 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW2FW_REO1_MEM_BMSK 0x100000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW2FW_REO1_MEM_SHFT 20 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW2FW_REO0_MEM_BMSK 0x80000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW2FW_REO0_MEM_SHFT 19 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_REO_RELEASE_RING_MEM_BMSK 0x40000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_REO_RELEASE_RING_MEM_SHFT 18 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW_PROD_MEM_MEM_BMSK 0x20000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW_PROD_MEM_MEM_SHFT 17 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_RING_PREFETCH_MEM_BMSK 0x10000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_RING_PREFETCH_MEM_SHFT 16 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK 0x2000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT 13 -#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_OFFS (0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_RMSK 0x7 -#define HWIO_REO_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_REO_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_REO_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x) ((x) + 0x1708) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_PHYS(x) ((x) + 0x1708) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_OFFS (0x1708) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_RMSK 0xffff -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_POR 0x00000000 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_ATTR 0x3 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x)) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x), m) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x),v) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x),m,v,HWIO_REO_R0_ERROR_CODE_REO_DELINK_IN(x)) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_OTHER_BMSK 0x8000 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_OTHER_SHFT 15 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_14_BMSK 0x4000 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_14_SHFT 14 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_13_BMSK 0x2000 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_13_SHFT 13 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_12_BMSK 0x1000 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_12_SHFT 12 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_11_BMSK 0x800 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_11_SHFT 11 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_10_BMSK 0x400 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_10_SHFT 10 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_9_BMSK 0x200 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_9_SHFT 9 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_8_BMSK 0x100 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_8_SHFT 8 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_7_BMSK 0x80 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_7_SHFT 7 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_6_BMSK 0x40 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_6_SHFT 6 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_5_BMSK 0x20 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_5_SHFT 5 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_4_BMSK 0x10 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_4_SHFT 4 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_3_BMSK 0x8 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_3_SHFT 3 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_2_BMSK 0x4 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_2_SHFT 2 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_1_BMSK 0x2 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_1_SHFT 1 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_0_BMSK 0x1 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x) ((x) + 0x170c) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_PHYS(x) ((x) + 0x170c) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_OFFS (0x170c) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_RMSK 0xffff -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_POR 0x00000000 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ATTR 0x3 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x)) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x), m) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x),v) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x),m,v,HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_IN(x)) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_OTHER_BMSK 0x8000 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_OTHER_SHFT 15 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_14_BMSK 0x4000 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_14_SHFT 14 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_13_BMSK 0x2000 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_13_SHFT 13 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_12_BMSK 0x1000 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_12_SHFT 12 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_11_BMSK 0x800 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_11_SHFT 11 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_10_BMSK 0x400 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_10_SHFT 10 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_9_BMSK 0x200 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_9_SHFT 9 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_8_BMSK 0x100 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_8_SHFT 8 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_7_BMSK 0x80 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_7_SHFT 7 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_6_BMSK 0x40 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_6_SHFT 6 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_5_BMSK 0x20 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_5_SHFT 5 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_4_BMSK 0x10 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_4_SHFT 4 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_3_BMSK 0x8 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_3_SHFT 3 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_2_BMSK 0x4 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_2_SHFT 2 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_1_BMSK 0x2 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_1_SHFT 1 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_0_BMSK 0x1 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_0_SHFT 0 - -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_PHYS(x) ((x) + 0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OFFS (0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR 0x00060000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ATTR 0x3 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x), m) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),v) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_BMSK 0xf0000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_SHFT 28 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_BMSK 0xf000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_SHFT 24 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_BMSK 0xf00000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_SHFT 20 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_BMSK 0xf0000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_SHFT 16 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_BMSK 0xf000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_SHFT 12 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_BMSK 0xf00 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_SHFT 8 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_BMSK 0xf0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_SHFT 4 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_BMSK 0xf -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_SHFT 0 - -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_PHYS(x) ((x) + 0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OFFS (0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR 0x00060000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ATTR 0x3 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x), m) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),v) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_BMSK 0xf0000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_SHFT 28 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_BMSK 0xf000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_SHFT 24 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_BMSK 0xf00000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_SHFT 20 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_BMSK 0xf0000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_SHFT 16 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_BMSK 0xf000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_SHFT 12 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_BMSK 0xf00 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_SHFT 8 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_BMSK 0xf0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_SHFT 4 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_BMSK 0xf -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_SHFT 0 - -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR(x) ((x) + 0x2008) -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_PHYS(x) ((x) + 0x2008) -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_OFFS (0x2008) -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_POR 0x00000000 -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_POR_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ATTR 0x1 -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_IN(x) \ - in_dword(HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR(x)) -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR(x), m) -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR_39_8_BMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR_39_8_SHFT 0 - -#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x) ((x) + 0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x) ((x) + 0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS (0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK 0x3f -#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR 0x00000000 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR 0x1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x) \ - in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK 0x20 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT 5 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK 0x10 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT 4 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK 0x8 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT 3 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK 0x4 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT 2 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK 0x2 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT 1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK 0x1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT 0 - -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x) ((x) + 0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x) ((x) + 0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS (0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR 0x00000000 -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR 0x3 -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x) \ - in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v) \ - out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT 0 - -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn 255 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028) -#define HWIO_REO_R2_FW2REO_RING_HP_ADDR(x) ((x) + 0x3048) -#define HWIO_REO_R2_FW2REO_RING_HP_PHYS(x) ((x) + 0x3048) -#define HWIO_REO_R2_FW2REO_RING_HP_OFFS (0x3048) -#define HWIO_REO_R2_FW2REO_RING_HP_RMSK 0xffff -#define HWIO_REO_R2_FW2REO_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_FW2REO_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_FW2REO_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_FW2REO_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_FW2REO_RING_HP_ADDR(x)) -#define HWIO_REO_R2_FW2REO_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_FW2REO_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_FW2REO_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_FW2REO_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_FW2REO_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_FW2REO_RING_HP_ADDR(x),m,v,HWIO_REO_R2_FW2REO_RING_HP_IN(x)) -#define HWIO_REO_R2_FW2REO_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_REO_R2_FW2REO_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_FW2REO_RING_TP_ADDR(x) ((x) + 0x304c) -#define HWIO_REO_R2_FW2REO_RING_TP_PHYS(x) ((x) + 0x304c) -#define HWIO_REO_R2_FW2REO_RING_TP_OFFS (0x304c) -#define HWIO_REO_R2_FW2REO_RING_TP_RMSK 0xffff -#define HWIO_REO_R2_FW2REO_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_FW2REO_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_FW2REO_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_FW2REO_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_FW2REO_RING_TP_ADDR(x)) -#define HWIO_REO_R2_FW2REO_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_FW2REO_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_FW2REO_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_FW2REO_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_FW2REO_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_FW2REO_RING_TP_ADDR(x),m,v,HWIO_REO_R2_FW2REO_RING_TP_IN(x)) -#define HWIO_REO_R2_FW2REO_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R2_FW2REO_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x) ((x) + 0x3050) -#define HWIO_REO_R2_FW2REO1_RING_HP_PHYS(x) ((x) + 0x3050) -#define HWIO_REO_R2_FW2REO1_RING_HP_OFFS (0x3050) -#define HWIO_REO_R2_FW2REO1_RING_HP_RMSK 0xffff -#define HWIO_REO_R2_FW2REO1_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_FW2REO1_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_FW2REO1_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_FW2REO1_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x)) -#define HWIO_REO_R2_FW2REO1_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_FW2REO1_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_FW2REO1_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x),m,v,HWIO_REO_R2_FW2REO1_RING_HP_IN(x)) -#define HWIO_REO_R2_FW2REO1_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_REO_R2_FW2REO1_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x) ((x) + 0x3054) -#define HWIO_REO_R2_FW2REO1_RING_TP_PHYS(x) ((x) + 0x3054) -#define HWIO_REO_R2_FW2REO1_RING_TP_OFFS (0x3054) -#define HWIO_REO_R2_FW2REO1_RING_TP_RMSK 0xffff -#define HWIO_REO_R2_FW2REO1_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_FW2REO1_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_FW2REO1_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_FW2REO1_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x)) -#define HWIO_REO_R2_FW2REO1_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_FW2REO1_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_FW2REO1_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x),m,v,HWIO_REO_R2_FW2REO1_RING_TP_IN(x)) -#define HWIO_REO_R2_FW2REO1_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R2_FW2REO1_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3070) -#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x3074) -#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3078) -#define HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x) ((x) + 0x30b0) -#define HWIO_REO_R2_REO2SW9_RING_HP_PHYS(x) ((x) + 0x30b0) -#define HWIO_REO_R2_REO2SW9_RING_HP_OFFS (0x30b0) -#define HWIO_REO_R2_REO2SW9_RING_HP_RMSK 0xfffff -#define HWIO_REO_R2_REO2SW9_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_REO2SW9_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_REO2SW9_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_REO2SW9_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x)) -#define HWIO_REO_R2_REO2SW9_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_REO2SW9_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_REO2SW9_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW9_RING_HP_IN(x)) -#define HWIO_REO_R2_REO2SW9_RING_HP_HEAD_PTR_BMSK 0xfffff -#define HWIO_REO_R2_REO2SW9_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x) ((x) + 0x30b4) -#define HWIO_REO_R2_REO2SW9_RING_TP_PHYS(x) ((x) + 0x30b4) -#define HWIO_REO_R2_REO2SW9_RING_TP_OFFS (0x30b4) -#define HWIO_REO_R2_REO2SW9_RING_TP_RMSK 0xfffff -#define HWIO_REO_R2_REO2SW9_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_REO2SW9_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_REO2SW9_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_REO2SW9_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x)) -#define HWIO_REO_R2_REO2SW9_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_REO2SW9_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_REO2SW9_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW9_RING_TP_IN(x)) -#define HWIO_REO_R2_REO2SW9_RING_TP_TAIL_PTR_BMSK 0xfffff -#define HWIO_REO_R2_REO2SW9_RING_TP_TAIL_PTR_SHFT 0 -#define TQM_REG_REG_BASE (UMAC_BASE + 0x0003c000) -#define TQM_REG_REG_BASE_SIZE 0x4000 - -#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x30b8) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x) ((x) + 0x3118) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_PHYS(x) ((x) + 0x3118) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_OFFS (0x3118) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO0_C_RING_HP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x) ((x) + 0x311c) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_PHYS(x) ((x) + 0x311c) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_OFFS (0x311c) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO0_C_RING_TP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x) ((x) + 0x3120) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_PHYS(x) ((x) + 0x3120) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_OFFS (0x3120) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO1_C_RING_HP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x) ((x) + 0x3124) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_PHYS(x) ((x) + 0x3124) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_OFFS (0x3124) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO1_C_RING_TP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x) ((x) + 0x3128) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_PHYS(x) ((x) + 0x3128) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_OFFS (0x3128) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO0_P_RING_HP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x) ((x) + 0x312c) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_PHYS(x) ((x) + 0x312c) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_OFFS (0x312c) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO0_P_RING_TP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x) ((x) + 0x3130) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_PHYS(x) ((x) + 0x3130) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_OFFS (0x3130) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO1_P_RING_HP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x) ((x) + 0x3134) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_PHYS(x) ((x) + 0x3134) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_OFFS (0x3134) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO1_P_RING_TP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK 0x80 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT 7 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK 0x40 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT 6 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK 0x20 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT 5 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK 0x10 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT 4 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK 0x8 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT 3 -#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x64c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x64c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_OFFS (0x64c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x650) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x650) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_OFFS (0x650) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x) ((x) + 0x654) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_PHYS(x) ((x) + 0x654) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_OFFS (0x654) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x658) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x658) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_OFFS (0x658) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x) ((x) + 0x65c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_PHYS(x) ((x) + 0x65c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_OFFS (0x65c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x660) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x660) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_OFFS (0x660) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x664) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x664) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_OFFS (0x664) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x670) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x670) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x670) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x674) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x674) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x674) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x678) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x678) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x678) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x694) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x694) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x694) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x698) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x698) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x698) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x69c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x69c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_OFFS (0x69c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x6a0) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x6a0) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x6a0) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x6a4) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x6a4) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x6a4) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x6a8) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x6a8) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x6a8) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x6ac) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x6ac) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_OFFS (0x6ac) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x6bc) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x6bc) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x6bc) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x6c0) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x6c0) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_OFFS (0x6c0) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x6c4) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x6c4) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_OFFS (0x6c4) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x6c8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x6c8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_OFFS (0x6c8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x) ((x) + 0x6cc) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_PHYS(x) ((x) + 0x6cc) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_OFFS (0x6cc) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x6d0) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x6d0) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_OFFS (0x6d0) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x) ((x) + 0x6d4) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_PHYS(x) ((x) + 0x6d4) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_OFFS (0x6d4) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6d8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6d8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_OFFS (0x6d8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x6dc) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x6dc) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_OFFS (0x6dc) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x6e8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x6e8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x6e8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x6ec) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x6ec) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x6ec) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x6f0) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x6f0) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x6f0) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x70c) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x70c) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x70c) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x710) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x710) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x710) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x714) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x714) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_OFFS (0x714) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x718) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x718) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x718) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x71c) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x71c) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x71c) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x720) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x720) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x720) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x724) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x724) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_OFFS (0x724) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x734) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x734) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x734) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x738) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x738) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_OFFS (0x738) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OFFS (0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x740) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x740) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_OFFS (0x740) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x) ((x) + 0x744) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_PHYS(x) ((x) + 0x744) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_OFFS (0x744) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x748) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x748) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_OFFS (0x748) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x) ((x) + 0x74c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_PHYS(x) ((x) + 0x74c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_OFFS (0x74c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x750) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x750) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_OFFS (0x750) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x754) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x754) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_OFFS (0x754) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x760) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x760) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x760) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x764) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x764) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x764) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x768) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x768) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x768) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x784) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x784) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x784) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x788) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x788) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x788) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x78c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x78c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_OFFS (0x78c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x790) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x790) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x790) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x794) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x794) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x794) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x798) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x798) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x798) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x79c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x79c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_OFFS (0x79c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x7ac) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x7ac) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x7ac) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x7b0) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x7b0) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_OFFS (0x7b0) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OFFS (0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x7b8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x7b8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_OFFS (0x7b8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x) ((x) + 0x7bc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_PHYS(x) ((x) + 0x7bc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_OFFS (0x7bc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x7c0) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x7c0) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_OFFS (0x7c0) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x) ((x) + 0x7c4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_PHYS(x) ((x) + 0x7c4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_OFFS (0x7c4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x7c8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x7c8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_OFFS (0x7c8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x7cc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x7cc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_OFFS (0x7cc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7d8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7d8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x7d8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x7dc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x7dc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x7dc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x7e0) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x7e0) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x7e0) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x7fc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x7fc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x7fc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x800) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x800) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x800) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x804) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x804) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_OFFS (0x804) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x808) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x808) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x808) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x80c) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x80c) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x80c) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x810) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x810) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x810) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x814) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x814) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_OFFS (0x814) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x824) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x824) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x824) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x828) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x828) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_OFFS (0x828) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x82c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x82c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_OFFS (0x82c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x830) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x830) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_OFFS (0x830) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x) ((x) + 0x834) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_PHYS(x) ((x) + 0x834) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_OFFS (0x834) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x838) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x838) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_OFFS (0x838) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x) ((x) + 0x83c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_PHYS(x) ((x) + 0x83c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_OFFS (0x83c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x840) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x840) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_OFFS (0x840) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x844) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x844) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_OFFS (0x844) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x850) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x850) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x850) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x854) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x854) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x854) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x858) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x858) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x858) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x874) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x874) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x874) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x878) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x878) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x878) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x87c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x87c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_OFFS (0x87c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x880) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x880) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x880) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x884) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x884) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x884) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x888) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x888) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x888) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x88c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x88c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_OFFS (0x88c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x89c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x89c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x89c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x8a0) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x8a0) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_OFFS (0x8a0) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x8a4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x8a4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_OFFS (0x8a4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x8a8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x8a8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_OFFS (0x8a8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x) ((x) + 0x8ac) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_PHYS(x) ((x) + 0x8ac) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_OFFS (0x8ac) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x8b0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x8b0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_OFFS (0x8b0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x) ((x) + 0x8b4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_PHYS(x) ((x) + 0x8b4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_OFFS (0x8b4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x8b8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x8b8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_OFFS (0x8b8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x8bc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x8bc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_OFFS (0x8bc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x8c8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x8c8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x8c8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x8cc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x8cc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x8cc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x8d0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x8d0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x8d0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x8ec) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x8ec) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x8ec) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x8f0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x8f0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x8f0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x8f4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x8f4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_OFFS (0x8f4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x8f8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x8f8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x8f8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x8fc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x8fc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x8fc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x900) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x900) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x900) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x904) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x904) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_OFFS (0x904) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x914) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x914) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x914) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x918) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x918) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_OFFS (0x918) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x91c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x91c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_OFFS (0x91c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x920) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x920) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_OFFS (0x920) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x) ((x) + 0x924) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_PHYS(x) ((x) + 0x924) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_OFFS (0x924) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x928) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x928) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_OFFS (0x928) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x) ((x) + 0x92c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_PHYS(x) ((x) + 0x92c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_OFFS (0x92c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x930) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x930) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_OFFS (0x930) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x934) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x934) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_OFFS (0x934) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x940) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x940) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x940) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x944) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x944) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x944) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x948) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x948) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x948) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x964) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x964) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x964) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x968) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x968) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x968) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x96c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x96c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_OFFS (0x96c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x970) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x970) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x970) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x974) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x974) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x974) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x978) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x978) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x978) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x97c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x97c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_OFFS (0x97c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x98c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x98c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x98c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x990) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x990) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_OFFS (0x990) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x994) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x994) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_OFFS (0x994) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x998) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x998) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_OFFS (0x998) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x) ((x) + 0x99c) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_PHYS(x) ((x) + 0x99c) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_OFFS (0x99c) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x9a0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x9a0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_OFFS (0x9a0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x) ((x) + 0x9a4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_PHYS(x) ((x) + 0x9a4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_OFFS (0x9a4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x9a8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x9a8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_OFFS (0x9a8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x9ac) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x9ac) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_OFFS (0x9ac) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x9b8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x9b8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x9b8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x9bc) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x9bc) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x9bc) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x9c0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x9c0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x9c0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x9dc) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x9dc) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x9dc) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x9e0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x9e0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x9e0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x9e4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x9e4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_OFFS (0x9e4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x9e8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x9e8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x9e8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x9ec) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x9ec) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x9ec) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x9f0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x9f0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x9f0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x9f4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x9f4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_OFFS (0x9f4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa04) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa04) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xa04) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xa08) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xa08) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_OFFS (0xa08) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xa0c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xa0c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_OFFS (0xa0c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xa10) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xa10) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_OFFS (0xa10) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x) ((x) + 0xa14) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_PHYS(x) ((x) + 0xa14) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_OFFS (0xa14) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xa18) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xa18) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_OFFS (0xa18) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x) ((x) + 0xa1c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_PHYS(x) ((x) + 0xa1c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_OFFS (0xa1c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xa20) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xa20) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_OFFS (0xa20) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xa24) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xa24) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_OFFS (0xa24) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xa30) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xa30) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xa30) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xa34) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xa34) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xa34) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xa38) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xa38) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xa38) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa54) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa54) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xa54) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa58) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa58) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xa58) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xa5c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xa5c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_OFFS (0xa5c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xa60) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xa60) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xa60) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xa64) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xa64) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xa64) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xa68) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xa68) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xa68) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xa6c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xa6c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_OFFS (0xa6c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa7c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa7c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xa7c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xa80) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xa80) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_OFFS (0xa80) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xddc) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xddc) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_OFFS (0xddc) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xde0) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xde0) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_OFFS (0xde0) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x) ((x) + 0xde4) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_PHYS(x) ((x) + 0xde4) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_OFFS (0xde4) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_RMSK 0xff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xde8) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xde8) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_OFFS (0xde8) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x) ((x) + 0xdec) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_PHYS(x) ((x) + 0xdec) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_OFFS (0xdec) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_RMSK 0x7fffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xdf8) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xdf8) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_OFFS (0xdf8) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xdfc) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xdfc) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_OFFS (0xdfc) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xe0c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xe0c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xe0c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xe10) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xe10) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xe10) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xe14) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xe14) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0xe14) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xe18) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xe18) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xe18) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xe1c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xe1c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xe1c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xe20) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xe20) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xe20) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xe24) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xe24) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xe24) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xe28) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xe28) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xe28) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xe2c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xe2c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_OFFS (0xe2c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xe4c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xe4c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xe4c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xe50) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xe50) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_OFFS (0xe50) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x) ((x) + 0xeac) -#define HWIO_TQM_R0_EVENTMASK_IX_4_PHYS(x) ((x) + 0xeac) -#define HWIO_TQM_R0_EVENTMASK_IX_4_OFFS (0xeac) -#define HWIO_TQM_R0_EVENTMASK_IX_4_RMSK 0xffffffff -#define HWIO_TQM_R0_EVENTMASK_IX_4_POR 0x00000000 -#define HWIO_TQM_R0_EVENTMASK_IX_4_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_EVENTMASK_IX_4_ATTR 0x3 -#define HWIO_TQM_R0_EVENTMASK_IX_4_IN(x) \ - in_dword(HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x)) -#define HWIO_TQM_R0_EVENTMASK_IX_4_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x), m) -#define HWIO_TQM_R0_EVENTMASK_IX_4_OUT(x, v) \ - out_dword(HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x),v) -#define HWIO_TQM_R0_EVENTMASK_IX_4_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_4_IN(x)) -#define HWIO_TQM_R0_EVENTMASK_IX_4_MASK_BMSK 0xffffffff -#define HWIO_TQM_R0_EVENTMASK_IX_4_MASK_SHFT 0 - -#define HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x) ((x) + 0xeb0) -#define HWIO_TQM_R0_EVENTMASK_IX_5_PHYS(x) ((x) + 0xeb0) -#define HWIO_TQM_R0_EVENTMASK_IX_5_OFFS (0xeb0) -#define HWIO_TQM_R0_EVENTMASK_IX_5_RMSK 0xffffffff -#define HWIO_TQM_R0_EVENTMASK_IX_5_POR 0x00000000 -#define HWIO_TQM_R0_EVENTMASK_IX_5_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_EVENTMASK_IX_5_ATTR 0x3 -#define HWIO_TQM_R0_EVENTMASK_IX_5_IN(x) \ - in_dword(HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x)) -#define HWIO_TQM_R0_EVENTMASK_IX_5_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x), m) -#define HWIO_TQM_R0_EVENTMASK_IX_5_OUT(x, v) \ - out_dword(HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x),v) -#define HWIO_TQM_R0_EVENTMASK_IX_5_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_5_IN(x)) -#define HWIO_TQM_R0_EVENTMASK_IX_5_MASK_BMSK 0xffffffff -#define HWIO_TQM_R0_EVENTMASK_IX_5_MASK_SHFT 0 - -#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK 0x80000000 -#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT 31 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_EMPTY_INDICATION_UPDATE_BMSK 0x10000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_EMPTY_INDICATION_UPDATE_SHFT 16 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK 0x8000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT 15 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK 0x4000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT 14 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK 0x2000 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT 13 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK 0x1000 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT 12 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK 0x800 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT 11 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK 0x400 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT 10 -#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS (0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK 0xf -#define HWIO_TQM_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x) ((x) + 0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x) ((x) + 0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS (0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK 0x1ffff -#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR 0x00000000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR 0x3 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x) \ - in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x)) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v) \ - out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x)) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TQM_STATUS_MEM_BMSK 0x10000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TQM_STATUS_MEM_SHFT 16 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TQM_PREFETCH_MEM_BMSK 0x8000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TQM_PREFETCH_MEM_SHFT 15 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LINK_ZERO_OUT_BMSK 0x4000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LINK_ZERO_OUT_SHFT 14 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_MSDU_DELINK_BMSK 0x2000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_MSDU_DELINK_SHFT 13 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_RLS_REQ_PARSER_BMSK 0x1000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_RLS_REQ_PARSER_SHFT 12 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW6_PROD_RELEASE_BMSK 0x800 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW6_PROD_RELEASE_SHFT 11 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW5_PROD_RELEASE_BMSK 0x400 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW5_PROD_RELEASE_SHFT 10 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW4_PROD_RELEASE_BMSK 0x200 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW4_PROD_RELEASE_SHFT 9 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW3_PROD_RELEASE_BMSK 0x100 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW3_PROD_RELEASE_SHFT 8 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW2_PROD_RELEASE_BMSK 0x80 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW2_PROD_RELEASE_SHFT 7 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW1_PROD_RELEASE_BMSK 0x40 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW1_PROD_RELEASE_SHFT 6 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW0_PROD_RELEASE_BMSK 0x20 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW0_PROD_RELEASE_SHFT 5 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_FW2TQM_RELEASE_RING_SM_BMSK 0x10 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_FW2TQM_RELEASE_RING_SM_SHFT 4 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_ERROR_RELEASE_BMSK 0x8 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_ERROR_RELEASE_SHFT 3 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_FW_PROD_RELEASE_BMSK 0x4 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_FW_PROD_RELEASE_SHFT 2 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK 0x2 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT 1 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK 0x1 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT 0 - -#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK 0x20000000 -#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT 29 -#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_FW2TQM_RELEASE_RING_BMSK 0xc00000 -#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_FW2TQM_RELEASE_RING_SHFT 22 -#define HWIO_TQM_R0_VC_ID_FW2TQM_RELEASE_C_SRNG_BMSK 0x40 -#define HWIO_TQM_R0_VC_ID_FW2TQM_RELEASE_C_SRNG_SHFT 6 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x) ((x) + 0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x) ((x) + 0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS (0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT 0 - -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x) ((x) + 0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x) ((x) + 0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS (0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT 0 - -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x) ((x) + 0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x) ((x) + 0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS (0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT 0 - -#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x) ((x) + 0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x) ((x) + 0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS (0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK 0xfff -#define HWIO_TQM_R0_WATCHDOG_SRNG_POR 0x00000710 -#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR 0x3 -#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x) \ - in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)) -#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)) -#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK 0xfff -#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_PHYS(x) ((x) + 0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OFFS (0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_RMSK 0x1ff -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR 0x000001fe -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_SHFT 7 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_SHFT 6 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_SHFT 5 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_SHFT 4 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_SHFT 3 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_SHFT 2 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_SHFT 1 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_SHFT 0 - -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x) ((x) + 0x120c) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_PHYS(x) ((x) + 0x120c) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_OFFS (0x120c) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_RMSK 0xfffff -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_POR 0x00000000 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_ATTR 0x3 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_IN(x) \ - in_dword(HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x)) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x), m) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x),v) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x),m,v,HWIO_TQM_R0_RING_PRIORITY_CFG1_IN(x)) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_SW_COOKIE_CONV_GXI_PRIORITY_BMSK 0xc0000 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_SW_COOKIE_CONV_GXI_PRIORITY_SHFT 18 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW6_RELEASE_RING_PRIORITY_BMSK 0x30000 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW6_RELEASE_RING_PRIORITY_SHFT 16 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW5_RELEASE_RING_PRIORITY_BMSK 0xc000 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW5_RELEASE_RING_PRIORITY_SHFT 14 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM_ERROR_RELEASE_RING_PRIORITY_BMSK 0x3000 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM_ERROR_RELEASE_RING_PRIORITY_SHFT 12 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW4_RELEASE_RING_PRIORITY_BMSK 0xc00 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW4_RELEASE_RING_PRIORITY_SHFT 10 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW3_RELEASE_RING_PRIORITY_BMSK 0x300 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW3_RELEASE_RING_PRIORITY_SHFT 8 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW2_RELEASE_RING_PRIORITY_BMSK 0xc0 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW2_RELEASE_RING_PRIORITY_SHFT 6 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW1_RELEASE_RING_PRIORITY_BMSK 0x30 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW1_RELEASE_RING_PRIORITY_SHFT 4 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW0_RELEASE_RING_PRIORITY_BMSK 0xc -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW0_RELEASE_RING_PRIORITY_SHFT 2 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2FW_RELEASE_RING_PRIORITY_BMSK 0x3 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2FW_RELEASE_RING_PRIORITY_SHFT 0 - -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1214) -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1214) -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_OFFS (0x1214) -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_RMSK 0x3fff -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x3f80 -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1218) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1218) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_OFFS (0x1218) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RMSK 0xff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0xfe -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x121c) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x121c) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_OFFS (0x121c) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1220) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1220) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_OFFS (0x1220) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1224) -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1224) -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_OFFS (0x1224) -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_RMSK 0x3fff -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x3f80 -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1228) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1228) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_OFFS (0x1228) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RMSK 0xff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0xfe -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x122c) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x122c) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_OFFS (0x122c) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1230) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1230) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_OFFS (0x1230) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1234) -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1234) -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_OFFS (0x1234) -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_RMSK 0x3fff -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x3f80 -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1238) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1238) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_OFFS (0x1238) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RMSK 0xff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0xfe -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x123c) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x123c) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_OFFS (0x123c) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1240) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1240) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_OFFS (0x1240) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1244) -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1244) -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_OFFS (0x1244) -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_RMSK 0x3fff -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x3f80 -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1248) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1248) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_OFFS (0x1248) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RMSK 0xff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0xfe -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x124c) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x124c) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_OFFS (0x124c) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1250) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1250) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_OFFS (0x1250) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1254) -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1254) -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_OFFS (0x1254) -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_RMSK 0x3fff -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x3f80 -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1258) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1258) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_OFFS (0x1258) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RMSK 0xff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0xfe -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x125c) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x125c) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_OFFS (0x125c) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1260) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1260) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_OFFS (0x1260) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1264) -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1264) -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_OFFS (0x1264) -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_RMSK 0x3fff -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x3f80 -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1268) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1268) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_OFFS (0x1268) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RMSK 0xff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0xfe -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x126c) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x126c) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_OFFS (0x126c) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1270) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1270) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_OFFS (0x1270) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1274) -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1274) -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_OFFS (0x1274) -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_RMSK 0x1fff -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x1f80 -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1278) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1278) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_OFFS (0x1278) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RMSK 0x7f -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x7e -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x127c) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x127c) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_OFFS (0x127c) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1280) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1280) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_OFFS (0x1280) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x12d4) -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x12d4) -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_OFFS (0x12d4) -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_RMSK 0x1fff -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x1f80 -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x12d8) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x12d8) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_OFFS (0x12d8) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RMSK 0x7f -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x7e -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x12dc) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x12dc) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_OFFS (0x12dc) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x12e0) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x12e0) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_OFFS (0x12e0) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x12e4) -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x12e4) -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_OFFS (0x12e4) -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_RMSK 0x1fff -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x1f80 -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x12e8) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x12e8) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_OFFS (0x12e8) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RMSK 0x7f -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x7e -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x12ec) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x12ec) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_OFFS (0x12ec) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x12f0) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x12f0) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_OFFS (0x12f0) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x) ((x) + 0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PHYS(x) ((x) + 0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OFFS (0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RMSK 0x3fefff -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR 0x00080170 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ATTR 0x3 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x) \ - in_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x)) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x), m) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),v) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),m,v,HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x)) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_BMSK 0x200000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_SHFT 21 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_BMSK 0x100000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_SHFT 20 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x80000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT 19 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_BMSK 0x40000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_SHFT 18 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_BMSK 0x20000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_SHFT 17 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_BMSK 0x10000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_SHFT 16 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_BMSK 0x8000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_SHFT 15 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_BMSK 0x4000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_SHFT 14 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_BMSK 0x2000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_SHFT 13 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_BMSK 0x800 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_SHFT 11 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_BMSK 0x400 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_SHFT 10 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_BMSK 0x200 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_SHFT 9 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_BMSK 0x80 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_SHFT 7 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_BMSK 0x40 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_SHFT 6 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_BMSK 0x20 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_SHFT 5 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_BMSK 0x10 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_SHFT 4 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_BMSK 0x8 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_SHFT 3 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_BMSK 0x4 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_SHFT 2 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_SHFT 1 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_PHYS(x) ((x) + 0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OFFS (0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR 0x00000000 -#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PHYS(x) ((x) + 0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OFFS (0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_RMSK 0x7ffff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR 0x00011100 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1300) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1300) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_OFFS (0x1300) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RMSK 0x7f -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_PTR_BMSK 0x7e -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x) ((x) + 0x1304) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_PHYS(x) ((x) + 0x1304) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_OFFS (0x1304) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_RMSK 0x1fff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x1f80 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1308) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1308) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_OFFS (0x1308) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x130c) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x130c) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_OFFS (0x130c) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x) ((x) + 0x1310) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_PHYS(x) ((x) + 0x1310) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_OFFS (0x1310) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_RMSK 0x1f -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x18 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_INTERNAL_PTR_SHFT 3 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_UD_CNT_BMSK 0x7 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1314) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1314) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OFFS (0x1314) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RMSK 0x7 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_PTR_BMSK 0x6 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1318) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1318) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_OFFS (0x1318) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_ADDR(x) ((x) + 0x131c) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_PHYS(x) ((x) + 0x131c) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_OFFS (0x131c) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_RMSK 0x1f -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x18 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_INTERNAL_PTR_SHFT 3 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_UD_CNT_BMSK 0x7 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1320) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1320) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_OFFS (0x1320) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RMSK 0x7 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RD_PTR_BMSK 0x6 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1324) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1324) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_OFFS (0x1324) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x) ((x) + 0x1328) -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_PHYS(x) ((x) + 0x1328) -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_OFFS (0x1328) -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_RMSK 0xfffffff -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_POR 0x00000000 -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ATTR 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_VALUE_BMSK 0xfffffff -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_VALUE_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x) ((x) + 0x132c) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_PHYS(x) ((x) + 0x132c) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OFFS (0x132c) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RMSK 0x3fff -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ATTR 0x3 -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x),v) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_IN(x)) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RESOLUTION_UNITS_BMSK 0x3000 -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RESOLUTION_UNITS_SHFT 12 -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x) ((x) + 0x1330) -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_PHYS(x) ((x) + 0x1330) -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_OFFS (0x1330) -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_RMSK 0xfffffff -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_POR 0x00000000 -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ATTR 0x1 -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_IN(x) \ - in_dword(HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x)) -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x), m) -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_VALUE_BMSK 0xfffffff -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_VALUE_SHFT 0 - -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x) ((x) + 0x1334) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_PHYS(x) ((x) + 0x1334) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_OFFS (0x1334) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_RMSK 0x7ff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x7c0 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_INTERNAL_PTR_SHFT 6 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_UD_CNT_BMSK 0x3f -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1338) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1338) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_OFFS (0x1338) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RMSK 0x3f -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x133c) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x133c) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_OFFS (0x133c) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1340) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1340) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_OFFS (0x1340) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x) ((x) + 0x1344) -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_PHYS(x) ((x) + 0x1344) -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_OFFS (0x1344) -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RMSK 0x1fffff -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_POR 0x00000000 -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_ATTR 0x1 -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_IN(x) \ - in_dword(HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x)) -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x), m) -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_ERR_BMSK 0x1e0000 -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_ERR_SHFT 17 -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_BMSK 0x1fff0 -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_SHFT 4 -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_P_STATE_ENC_BMSK 0xf -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_P_STATE_ENC_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x) ((x) + 0x1348) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_PHYS(x) ((x) + 0x1348) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_OFFS (0x1348) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_RMSK 0x7 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_POR 0x00000000 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_ATTR 0x3 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x),v) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_MSDU_PARSER_CONTROL_IN(x)) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_BMSK 0x4 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_SHFT 2 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_BMSK 0x2 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_SHFT 1 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_BMSK 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_ADDR(x) ((x) + 0x134c) -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_PHYS(x) ((x) + 0x134c) -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_OFFS (0x134c) -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_RMSK 0x3ffff -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_POR 0x00001441 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_STATUS_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_2_DONE_BMSK 0x20000 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_2_DONE_SHFT 17 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_CACHE_2_STATE_BMSK 0x1f000 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_CACHE_2_STATE_SHFT 12 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_BMSK 0x800 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_SHFT 11 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_BMSK 0x400 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_SHFT 10 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_BMSK 0x3c0 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_SHFT 6 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_BMSK 0x20 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_SHFT 5 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_BMSK 0x1f -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_SHFT 0 - -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ADDR(x) ((x) + 0x1350) -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_PHYS(x) ((x) + 0x1350) -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_OFFS (0x1350) -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_RMSK 0xffffffff -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_POR 0x00000000 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ATTR 0x1 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_IN(x) \ - in_dword(HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ADDR(x)) -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ADDR(x), m) -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_BMSK 0x80000000 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_SHFT 31 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_BMSK 0x40000000 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_SHFT 30 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_BMSK 0x30000000 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_SHFT 28 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_BMSK 0xffffe00 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_SHFT 9 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_BM_ACTION_BMSK 0x180 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_BM_ACTION_SHFT 7 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_BMSK 0x70 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_SHFT 4 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_BMSK 0xf -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_SHFT 0 - -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x) ((x) + 0x1354) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_PHYS(x) ((x) + 0x1354) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_OFFS (0x1354) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RMSK 0x13fff -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_POR 0x00000020 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_ATTR 0x3 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_IN(x) \ - in_dword(HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x)) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x), m) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_OUT(x, v) \ - out_dword(HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x),v) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x),m,v,HWIO_TQM_R0_RELEASE_RING_FLUSH_IN(x)) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_BMSK 0x10000 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_SHFT 16 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_BMSK 0x2000 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_SHFT 13 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_BMSK 0x1000 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_SHFT 12 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_BMSK 0xfff -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_SHFT 0 - -#define HWIO_TQM_R0_SM_STATES_IX4_ADDR(x) ((x) + 0x15f0) -#define HWIO_TQM_R0_SM_STATES_IX4_PHYS(x) ((x) + 0x15f0) -#define HWIO_TQM_R0_SM_STATES_IX4_OFFS (0x15f0) -#define HWIO_TQM_R0_SM_STATES_IX4_RMSK 0xffffffff -#define HWIO_TQM_R0_SM_STATES_IX4_POR 0x00000000 -#define HWIO_TQM_R0_SM_STATES_IX4_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SM_STATES_IX4_ATTR 0x1 -#define HWIO_TQM_R0_SM_STATES_IX4_IN(x) \ - in_dword(HWIO_TQM_R0_SM_STATES_IX4_ADDR(x)) -#define HWIO_TQM_R0_SM_STATES_IX4_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SM_STATES_IX4_ADDR(x), m) -#define HWIO_TQM_R0_SM_STATES_IX4_SW6_RELEASE_PROD_SM_STATE_BMSK 0xc0000000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW6_RELEASE_PROD_SM_STATE_SHFT 30 -#define HWIO_TQM_R0_SM_STATES_IX4_SW5_RELEASE_PROD_SM_STATE_BMSK 0x30000000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW5_RELEASE_PROD_SM_STATE_SHFT 28 -#define HWIO_TQM_R0_SM_STATES_IX4_SW4_RELEASE_PROD_SM_STATE_BMSK 0xc000000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW4_RELEASE_PROD_SM_STATE_SHFT 26 -#define HWIO_TQM_R0_SM_STATES_IX4_SW3_RELEASE_PROD_SM_STATE_BMSK 0x3000000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW3_RELEASE_PROD_SM_STATE_SHFT 24 -#define HWIO_TQM_R0_SM_STATES_IX4_SW2_RELEASE_PROD_SM_STATE_BMSK 0xc00000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW2_RELEASE_PROD_SM_STATE_SHFT 22 -#define HWIO_TQM_R0_SM_STATES_IX4_SW1_RELEASE_PROD_SM_STATE_BMSK 0x300000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW1_RELEASE_PROD_SM_STATE_SHFT 20 -#define HWIO_TQM_R0_SM_STATES_IX4_SW0_RELEASE_PROD_SM_STATE_BMSK 0xc0000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW0_RELEASE_PROD_SM_STATE_SHFT 18 -#define HWIO_TQM_R0_SM_STATES_IX4_ERROR_RELEASE_PROD_SM_STATE_BMSK 0x30000 -#define HWIO_TQM_R0_SM_STATES_IX4_ERROR_RELEASE_PROD_SM_STATE_SHFT 16 -#define HWIO_TQM_R0_SM_STATES_IX4_FW_RELEASE_PROD_SM_STATE_BMSK 0xc000 -#define HWIO_TQM_R0_SM_STATES_IX4_FW_RELEASE_PROD_SM_STATE_SHFT 14 -#define HWIO_TQM_R0_SM_STATES_IX4_LINK_ZERO_OUT_STATE_BMSK 0x3000 -#define HWIO_TQM_R0_SM_STATES_IX4_LINK_ZERO_OUT_STATE_SHFT 12 -#define HWIO_TQM_R0_SM_STATES_IX4_MSDU_DELINK_PARSER_STATE_BMSK 0xf00 -#define HWIO_TQM_R0_SM_STATES_IX4_MSDU_DELINK_PARSER_STATE_SHFT 8 -#define HWIO_TQM_R0_SM_STATES_IX4_DELINK_CACHE_STATE_BMSK 0xf8 -#define HWIO_TQM_R0_SM_STATES_IX4_DELINK_CACHE_STATE_SHFT 3 -#define HWIO_TQM_R0_SM_STATES_IX4_RLS_REQ_STATE_SM_BMSK 0x7 -#define HWIO_TQM_R0_SM_STATES_IX4_RLS_REQ_STATE_SM_SHFT 0 - -#define HWIO_TQM_R0_SM_STATES_IX5_ADDR(x) ((x) + 0x15f4) -#define HWIO_TQM_R0_SM_STATES_IX5_PHYS(x) ((x) + 0x15f4) -#define HWIO_TQM_R0_SM_STATES_IX5_OFFS (0x15f4) -#define HWIO_TQM_R0_SM_STATES_IX5_RMSK 0xf -#define HWIO_TQM_R0_SM_STATES_IX5_POR 0x00000000 -#define HWIO_TQM_R0_SM_STATES_IX5_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SM_STATES_IX5_ATTR 0x1 -#define HWIO_TQM_R0_SM_STATES_IX5_IN(x) \ - in_dword(HWIO_TQM_R0_SM_STATES_IX5_ADDR(x)) -#define HWIO_TQM_R0_SM_STATES_IX5_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SM_STATES_IX5_ADDR(x), m) -#define HWIO_TQM_R0_SM_STATES_IX5_FW2TQM_RELEASE_READ_REQ_STATE_BMSK 0xc -#define HWIO_TQM_R0_SM_STATES_IX5_FW2TQM_RELEASE_READ_REQ_STATE_SHFT 2 -#define HWIO_TQM_R0_SM_STATES_IX5_FW2TQM_RELEASE_PREFETCH_STATE_BMSK 0x3 -#define HWIO_TQM_R0_SM_STATES_IX5_FW2TQM_RELEASE_PREFETCH_STATE_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0 - -#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x) ((x) + 0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x) ((x) + 0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS (0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x) ((x) + 0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x) ((x) + 0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS (0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x) ((x) + 0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x) ((x) + 0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS (0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x) ((x) + 0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x) ((x) + 0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS (0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK 0xf -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR 0x00000000 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR 0x1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x)) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK 0x8 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT 3 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK 0x4 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT 2 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK 0x2 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT 1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK 0x1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT 0 - -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x) ((x) + 0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x) ((x) + 0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS (0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR 0x00000000 -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR 0x1 -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x) \ - in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x)) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT 0 - -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x) ((x) + 0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x) ((x) + 0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS (0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR 0x00000000 -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR 0x1 -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x) \ - in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x)) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT 0 - -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0xff -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_ADDR(x) ((x) + 0x211c) -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_PHYS(x) ((x) + 0x211c) -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_OFFS (0x211c) -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_RMSK 0xffffffff -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_POR 0x00000000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_ATTR 0x1 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_IN(x) \ - in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX4_ADDR(x)) -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX4_ADDR(x), m) -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW6_RELEASE_PROD_SM_STATE_BMSK 0xc0000000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW6_RELEASE_PROD_SM_STATE_SHFT 30 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW5_RELEASE_PROD_SM_STATE_BMSK 0x30000000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW5_RELEASE_PROD_SM_STATE_SHFT 28 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW4_RELEASE_PROD_SM_STATE_BMSK 0xc000000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW4_RELEASE_PROD_SM_STATE_SHFT 26 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW3_RELEASE_PROD_SM_STATE_BMSK 0x3000000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW3_RELEASE_PROD_SM_STATE_SHFT 24 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW2_RELEASE_PROD_SM_STATE_BMSK 0xc00000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW2_RELEASE_PROD_SM_STATE_SHFT 22 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW1_RELEASE_PROD_SM_STATE_BMSK 0x300000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW1_RELEASE_PROD_SM_STATE_SHFT 20 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW0_RELEASE_PROD_SM_STATE_BMSK 0xc0000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW0_RELEASE_PROD_SM_STATE_SHFT 18 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_ERROR_RELEASE_PROD_SM_STATE_BMSK 0x30000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_ERROR_RELEASE_PROD_SM_STATE_SHFT 16 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_FW_RELEASE_PROD_SM_STATE_BMSK 0xc000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_FW_RELEASE_PROD_SM_STATE_SHFT 14 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_LINK_ZERO_OUT_STATE_BMSK 0x3000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_LINK_ZERO_OUT_STATE_SHFT 12 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_MSDU_DELINK_PARSER_STATE_BMSK 0xf00 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_MSDU_DELINK_PARSER_STATE_SHFT 8 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_DELINK_CACHE_STATE_BMSK 0xf8 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_DELINK_CACHE_STATE_SHFT 3 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_RLS_REQ_STATE_SM_BMSK 0x7 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_RLS_REQ_STATE_SM_SHFT 0 - -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_ADDR(x) ((x) + 0x2120) -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_PHYS(x) ((x) + 0x2120) -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_OFFS (0x2120) -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_RMSK 0xf -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_POR 0x00000000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_ATTR 0x1 -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_IN(x) \ - in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX5_ADDR(x)) -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX5_ADDR(x), m) -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_FW2TQM_RELEASE_READ_REQ_STATE_BMSK 0xc -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_FW2TQM_RELEASE_READ_REQ_STATE_SHFT 2 -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_FW2TQM_RELEASE_PREFETCH_STATE_BMSK 0x3 -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_FW2TQM_RELEASE_PREFETCH_STATE_SHFT 0 - -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn 127 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3068) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_PHYS(x) ((x) + 0x3068) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_OFFS (0x3068) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x) ((x) + 0x306c) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_PHYS(x) ((x) + 0x306c) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_OFFS (0x306c) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x) ((x) + 0x3070) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_PHYS(x) ((x) + 0x3070) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_OFFS (0x3070) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x) ((x) + 0x3074) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_PHYS(x) ((x) + 0x3074) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_OFFS (0x3074) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_PHYS(x) ((x) + 0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OFFS (0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x) ((x) + 0x307c) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_PHYS(x) ((x) + 0x307c) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_OFFS (0x307c) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_PHYS(x) ((x) + 0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OFFS (0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x) ((x) + 0x3084) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_PHYS(x) ((x) + 0x3084) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_OFFS (0x3084) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x) ((x) + 0x3088) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_PHYS(x) ((x) + 0x3088) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_OFFS (0x3088) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x) ((x) + 0x308c) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_PHYS(x) ((x) + 0x308c) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_OFFS (0x308c) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x) ((x) + 0x3090) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_PHYS(x) ((x) + 0x3090) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_OFFS (0x3090) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x) ((x) + 0x3094) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_PHYS(x) ((x) + 0x3094) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_OFFS (0x3094) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x) ((x) + 0x3098) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_PHYS(x) ((x) + 0x3098) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_OFFS (0x3098) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x) ((x) + 0x309c) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_PHYS(x) ((x) + 0x309c) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_OFFS (0x309c) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x) ((x) + 0x30a0) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_PHYS(x) ((x) + 0x30a0) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_OFFS (0x30a0) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x) ((x) + 0x30a4) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_PHYS(x) ((x) + 0x30a4) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_OFFS (0x30a4) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x) ((x) + 0x30a8) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_PHYS(x) ((x) + 0x30a8) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_OFFS (0x30a8) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x) ((x) + 0x30ac) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_PHYS(x) ((x) + 0x30ac) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_OFFS (0x30ac) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x) ((x) + 0x30e8) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_PHYS(x) ((x) + 0x30e8) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_OFFS (0x30e8) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x) ((x) + 0x30ec) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_PHYS(x) ((x) + 0x30ec) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_OFFS (0x30ec) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK 0x80 -#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT 7 -#define HWIO_UMCMN_R0_ISR_P_TQM3_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_P_TQM3_SHFT 18 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 28 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO1_P_RING_WDG_BMSK 0x4000000 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO1_P_RING_WDG_SHFT 26 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO0_P_RING_WDG_BMSK 0x2000000 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO0_P_RING_WDG_SHFT 25 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO1_C_RING_WDG_BMSK 0x1000000 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO1_C_RING_WDG_SHFT 24 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO0_C_RING_WDG_BMSK 0x800000 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO0_C_RING_WDG_SHFT 23 -#define HWIO_UMCMN_R0_ISR_S6_REO2SW9_RING_WDG_BMSK 0x400000 -#define HWIO_UMCMN_R0_ISR_S6_REO2SW9_RING_WDG_SHFT 22 -#define HWIO_UMCMN_R0_ISR_S6_FW2REO1_RING_WDG_BMSK 0x80 -#define HWIO_UMCMN_R0_ISR_S6_FW2REO1_RING_WDG_SHFT 7 -#define HWIO_UMCMN_R0_ISR_S6_FW2REO_RING_WDG_BMSK 0x1 -#define HWIO_UMCMN_R0_ISR_S6_FW2REO_RING_WDG_SHFT 0 - -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO1_P_WDG_ERR_BMSK 0x800000 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO1_P_WDG_ERR_SHFT 23 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO0_P_WDG_ERR_BMSK 0x400000 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO0_P_WDG_ERR_SHFT 22 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO1_C_WDG_ERR_BMSK 0x200000 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO1_C_WDG_ERR_SHFT 21 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO0_C_WDG_ERR_BMSK 0x100000 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO0_C_WDG_ERR_SHFT 20 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO1_P_RING_REQ_ERR_BMSK 0x400000 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO1_P_RING_REQ_ERR_SHFT 22 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO0_P_RING_REQ_ERR_BMSK 0x200000 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO0_P_RING_REQ_ERR_SHFT 21 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO1_C_RING_REQ_ERR_BMSK 0x100000 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO1_C_RING_REQ_ERR_SHFT 20 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO0_C_RING_REQ_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO0_C_RING_REQ_ERR_SHFT 19 -#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG12_REQ_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG12_REQ_ERR_SHFT 18 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 -#define HWIO_UMCMN_R0_ISR_S12_TCL_EXTN_SEG1_LEN_ZERO_ERR_BMSK 0x80000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_EXTN_SEG1_LEN_ZERO_ERR_SHFT 31 -#define HWIO_UMCMN_R0_ISR_S12_TCL_EXTN_SEG1_ADDR_ZERO_ERR_BMSK 0x40000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_EXTN_SEG1_ADDR_ZERO_ERR_SHFT 30 -#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_LEN_ZERO_ERR_BMSK 0x20000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_LEN_ZERO_ERR_SHFT 29 -#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_ADDR_ZERO_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_ADDR_ZERO_ERR_SHFT 28 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_ZERO_LEN_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_ZERO_LEN_ERR_SHFT 27 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_RING_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_RING_WDG_ERR_SHFT 26 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_RING_REQ_ERR_BMSK 0x2000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_RING_REQ_ERR_SHFT 25 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_ZERO_LEN_ERR_BMSK 0x1000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_ZERO_LEN_ERR_SHFT 24 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_RING_WDG_ERR_BMSK 0x800000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_RING_WDG_ERR_SHFT 23 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_RING_REQ_ERR_BMSK 0x400000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_RING_REQ_ERR_SHFT 22 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 -#define HWIO_UMCMN_R0_ISR_S15_TQM_RELEASE_PARSER_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_S15_TQM_RELEASE_PARSER_WDG_ERR_SHFT 18 -#define HWIO_UMCMN_R0_ISR_S15_TQM_MSDU_PARSER_ERROR_INT_BMSK 0x20000 -#define HWIO_UMCMN_R0_ISR_S15_TQM_MSDU_PARSER_ERROR_INT_SHFT 17 -#define HWIO_UMCMN_R0_ISR_S15_TQM_FW2TQM_RELEASE_RING_REQ_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_ISR_S15_TQM_FW2TQM_RELEASE_RING_REQ_ERR_SHFT 16 -#define HWIO_UMCMN_R0_ISR_S15_TQM_FW2TQM_RELEASE_RING_WDG_ERR_BMSK 0x8000 -#define HWIO_UMCMN_R0_ISR_S15_TQM_FW2TQM_RELEASE_RING_WDG_ERR_SHFT 15 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 -#define HWIO_UMCMN_R0_IMR_P_TQM3_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_P_TQM3_SHFT 18 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 28 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO1_P_RING_WDG_BMSK 0x4000000 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO1_P_RING_WDG_SHFT 26 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO0_P_RING_WDG_BMSK 0x2000000 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO0_P_RING_WDG_SHFT 25 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO1_C_RING_WDG_BMSK 0x1000000 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO1_C_RING_WDG_SHFT 24 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO0_C_RING_WDG_BMSK 0x800000 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO0_C_RING_WDG_SHFT 23 -#define HWIO_UMCMN_R0_IMR_S6_REO2SW9_RING_WDG_BMSK 0x400000 -#define HWIO_UMCMN_R0_IMR_S6_REO2SW9_RING_WDG_SHFT 22 -#define HWIO_UMCMN_R0_IMR_S6_FW2REO1_RING_WDG_BMSK 0x80 -#define HWIO_UMCMN_R0_IMR_S6_FW2REO1_RING_WDG_SHFT 7 -#define HWIO_UMCMN_R0_IMR_S6_FW2REO_RING_WDG_BMSK 0x1 -#define HWIO_UMCMN_R0_IMR_S6_FW2REO_RING_WDG_SHFT 0 - -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO1_P_WDG_ERR_BMSK 0x800000 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO1_P_WDG_ERR_SHFT 23 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO0_P_WDG_ERR_BMSK 0x400000 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO0_P_WDG_ERR_SHFT 22 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO1_C_WDG_ERR_BMSK 0x200000 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO1_C_WDG_ERR_SHFT 21 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO0_C_WDG_ERR_BMSK 0x100000 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO0_C_WDG_ERR_SHFT 20 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO1_P_RING_REQ_ERR_BMSK 0x400000 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO1_P_RING_REQ_ERR_SHFT 22 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO0_P_RING_REQ_ERR_BMSK 0x200000 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO0_P_RING_REQ_ERR_SHFT 21 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO1_C_RING_REQ_ERR_BMSK 0x100000 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO1_C_RING_REQ_ERR_SHFT 20 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO0_C_RING_REQ_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO0_C_RING_REQ_ERR_SHFT 19 -#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG12_REQ_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG12_REQ_ERR_SHFT 18 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 -#define HWIO_UMCMN_R0_IMR_S12_TCL_EXTN_SEG1_LEN_ZERO_ERR_BMSK 0x80000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_EXTN_SEG1_LEN_ZERO_ERR_SHFT 31 -#define HWIO_UMCMN_R0_IMR_S12_TCL_EXTN_SEG1_ADDR_ZERO_ERR_BMSK 0x40000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_EXTN_SEG1_ADDR_ZERO_ERR_SHFT 30 -#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_LEN_ZERO_ERR_BMSK 0x20000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_LEN_ZERO_ERR_SHFT 29 -#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_ADDR_ZERO_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_ADDR_ZERO_ERR_SHFT 28 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_ZERO_LEN_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_ZERO_LEN_ERR_SHFT 27 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_RING_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_RING_WDG_ERR_SHFT 26 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_RING_REQ_ERR_BMSK 0x2000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_RING_REQ_ERR_SHFT 25 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_ZERO_LEN_ERR_BMSK 0x1000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_ZERO_LEN_ERR_SHFT 24 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_RING_WDG_ERR_BMSK 0x800000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_RING_WDG_ERR_SHFT 23 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_RING_REQ_ERR_BMSK 0x400000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_RING_REQ_ERR_SHFT 22 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 -#define HWIO_UMCMN_R0_IMR_S15_TQM_RELEASE_PARSER_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_S15_TQM_RELEASE_PARSER_WDG_ERR_SHFT 18 -#define HWIO_UMCMN_R0_IMR_S15_TQM_MSDU_PARSER_ERROR_INT_BMSK 0x20000 -#define HWIO_UMCMN_R0_IMR_S15_TQM_MSDU_PARSER_ERROR_INT_SHFT 17 -#define HWIO_UMCMN_R0_IMR_S15_TQM_FW2TQM_RELEASE_RING_REQ_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_IMR_S15_TQM_FW2TQM_RELEASE_RING_REQ_ERR_SHFT 16 -#define HWIO_UMCMN_R0_IMR_S15_TQM_FW2TQM_RELEASE_RING_WDG_ERR_BMSK 0x8000 -#define HWIO_UMCMN_R0_IMR_S15_TQM_FW2TQM_RELEASE_RING_WDG_ERR_SHFT 15 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 -#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK 0x40 -#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT 6 -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x) ((x) + 0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x) ((x) + 0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS (0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK 0xf -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR 0x0000000a -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR 0x3 -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x) \ - in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK 0xf -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT 0 - -#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS (0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK 0x1f -#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK 0x10 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT 4 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK 0x8 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT 3 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK 0x4 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT 2 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK 0x2 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT 1 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_UMCMN_R0_LINK_ID_ADDR(x) ((x) + 0x170) -#define HWIO_UMCMN_R0_LINK_ID_PHYS(x) ((x) + 0x170) -#define HWIO_UMCMN_R0_LINK_ID_OFFS (0x170) -#define HWIO_UMCMN_R0_LINK_ID_RMSK 0xffff -#define HWIO_UMCMN_R0_LINK_ID_POR 0x000052c8 -#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_LINK_ID_ATTR 0x3 -#define HWIO_UMCMN_R0_LINK_ID_IN(x) \ - in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x)) -#define HWIO_UMCMN_R0_LINK_ID_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m) -#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v) -#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x)) -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK 0x80 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT 7 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK 0x40 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT 6 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK 0x38 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT 3 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK 0x7 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT 0 - -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK 0x4000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT 14 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK 0x2000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT 13 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK 0x1000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT 12 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK 0x800 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT 11 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK 0x400 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT 10 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK 0x200 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT 9 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK 0x100 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT 8 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK 0x80 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT 7 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK 0x40 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT 6 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK 0x20 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT 5 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK 0x10 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT 4 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK 0x8 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT 3 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK 0x4 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT 2 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK 0x2 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT 1 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK 0x1 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT 0 - -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x) ((x) + 0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x) ((x) + 0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS (0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK 0x1 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR 0x00000000 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR 0x3 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x) \ - in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x)) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x)) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK 0x1 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT 0 - -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x) ((x) + 0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x) ((x) + 0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS (0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK 0x1ffff -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR 0x00000000 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR 0x3 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x) \ - in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x)) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x)) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK 0x1fe00 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT 9 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK 0x1fe -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT 1 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK 0x1 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT 0 - -#define HWIO_UMCMN_R0_ISR_S18_ADDR(x) ((x) + 0x194) -#define HWIO_UMCMN_R0_ISR_S18_PHYS(x) ((x) + 0x194) -#define HWIO_UMCMN_R0_ISR_S18_OFFS (0x194) -#define HWIO_UMCMN_R0_ISR_S18_RMSK 0x7fffffff -#define HWIO_UMCMN_R0_ISR_S18_POR 0x00000000 -#define HWIO_UMCMN_R0_ISR_S18_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_ISR_S18_ATTR 0x0 -#define HWIO_UMCMN_R0_ISR_S18_IN(x) \ - in_dword(HWIO_UMCMN_R0_ISR_S18_ADDR(x)) -#define HWIO_UMCMN_R0_ISR_S18_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_ISR_S18_ADDR(x), m) -#define HWIO_UMCMN_R0_ISR_S18_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_ISR_S18_ADDR(x),v) -#define HWIO_UMCMN_R0_ISR_S18_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S18_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S18_IN(x)) -#define HWIO_UMCMN_R0_ISR_S18_TQM_VA_CONV_ERR_INTR_BMSK 0x40000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_VA_CONV_ERR_INTR_SHFT 30 -#define HWIO_UMCMN_R0_ISR_S18_TQM_MSDU_DELINK_PARSE_ERR_INTR_BMSK 0x20000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_MSDU_DELINK_PARSE_ERR_INTR_SHFT 29 -#define HWIO_UMCMN_R0_ISR_S18_TQM_MSDU_DELINK_WATCHDOG_INTR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_MSDU_DELINK_WATCHDOG_INTR_SHFT 28 -#define HWIO_UMCMN_R0_ISR_S18_TQM_FW_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_FW_BUFFER_PROD_WATCHDOG_INTR_SHFT 27 -#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_PROD_WATCHDOG_INTR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_PROD_WATCHDOG_INTR_SHFT 26 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW0_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x2000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW0_BUFFER_PROD_WATCHDOG_INTR_SHFT 25 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW1_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x1000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW1_BUFFER_PROD_WATCHDOG_INTR_SHFT 24 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW2_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x800000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW2_BUFFER_PROD_WATCHDOG_INTR_SHFT 23 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW3_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x400000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW3_BUFFER_PROD_WATCHDOG_INTR_SHFT 22 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW4_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x200000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW4_BUFFER_PROD_WATCHDOG_INTR_SHFT 21 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW5_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x100000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW5_BUFFER_PROD_WATCHDOG_INTR_SHFT 20 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW6_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x80000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW6_BUFFER_PROD_WATCHDOG_INTR_SHFT 19 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW_COOKIE_IDLE_TIMEOUT_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW_COOKIE_IDLE_TIMEOUT_SHFT 18 -#define HWIO_UMCMN_R0_ISR_S18_TQM2FW_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x20000 -#define HWIO_UMCMN_R0_ISR_S18_TQM2FW_RELEASE_RING_REQ_ERROR_INTR_SHFT 17 -#define HWIO_UMCMN_R0_ISR_S18_TQM2FW_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x10000 -#define HWIO_UMCMN_R0_ISR_S18_TQM2FW_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 16 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW0_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x8000 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW0_RELEASE_RING_REQ_ERROR_INTR_SHFT 15 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW0_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x4000 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW0_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 14 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW1_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x2000 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW1_RELEASE_RING_REQ_ERROR_INTR_SHFT 13 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW1_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x1000 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW1_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 12 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW2_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x800 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW2_RELEASE_RING_REQ_ERROR_INTR_SHFT 11 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW2_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x400 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW2_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 10 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW3_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x200 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW3_RELEASE_RING_REQ_ERROR_INTR_SHFT 9 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW3_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x100 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW3_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 8 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW4_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x80 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW4_RELEASE_RING_REQ_ERROR_INTR_SHFT 7 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW4_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x40 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW4_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 6 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW5_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x20 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW5_RELEASE_RING_REQ_ERROR_INTR_SHFT 5 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW5_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x10 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW5_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 4 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW6_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x8 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW6_RELEASE_RING_REQ_ERROR_INTR_SHFT 3 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW6_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x4 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW6_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 2 -#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x2 -#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_RING_REQ_ERROR_INTR_SHFT 1 -#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x1 -#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 0 - -#define HWIO_UMCMN_R0_IMR_S18_ADDR(x) ((x) + 0x198) -#define HWIO_UMCMN_R0_IMR_S18_PHYS(x) ((x) + 0x198) -#define HWIO_UMCMN_R0_IMR_S18_OFFS (0x198) -#define HWIO_UMCMN_R0_IMR_S18_RMSK 0x7fffffff -#define HWIO_UMCMN_R0_IMR_S18_POR 0x00000000 -#define HWIO_UMCMN_R0_IMR_S18_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_IMR_S18_ATTR 0x3 -#define HWIO_UMCMN_R0_IMR_S18_IN(x) \ - in_dword(HWIO_UMCMN_R0_IMR_S18_ADDR(x)) -#define HWIO_UMCMN_R0_IMR_S18_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_IMR_S18_ADDR(x), m) -#define HWIO_UMCMN_R0_IMR_S18_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_IMR_S18_ADDR(x),v) -#define HWIO_UMCMN_R0_IMR_S18_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S18_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S18_IN(x)) -#define HWIO_UMCMN_R0_IMR_S18_TQM_VA_CONV_ERR_INTR_BMSK 0x40000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_VA_CONV_ERR_INTR_SHFT 30 -#define HWIO_UMCMN_R0_IMR_S18_TQM_MSDU_DELINK_PARSE_ERR_INTR_BMSK 0x20000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_MSDU_DELINK_PARSE_ERR_INTR_SHFT 29 -#define HWIO_UMCMN_R0_IMR_S18_TQM_MSDU_DELINK_WATCHDOG_INTR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_MSDU_DELINK_WATCHDOG_INTR_SHFT 28 -#define HWIO_UMCMN_R0_IMR_S18_TQM_FW_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_FW_BUFFER_PROD_WATCHDOG_INTR_SHFT 27 -#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_PROD_WATCHDOG_INTR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_PROD_WATCHDOG_INTR_SHFT 26 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW0_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x2000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW0_BUFFER_PROD_WATCHDOG_INTR_SHFT 25 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW1_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x1000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW1_BUFFER_PROD_WATCHDOG_INTR_SHFT 24 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW2_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x800000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW2_BUFFER_PROD_WATCHDOG_INTR_SHFT 23 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW3_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x400000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW3_BUFFER_PROD_WATCHDOG_INTR_SHFT 22 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW4_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x200000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW4_BUFFER_PROD_WATCHDOG_INTR_SHFT 21 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW5_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x100000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW5_BUFFER_PROD_WATCHDOG_INTR_SHFT 20 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW6_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x80000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW6_BUFFER_PROD_WATCHDOG_INTR_SHFT 19 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW_COOKIE_IDLE_TIMEOUT_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW_COOKIE_IDLE_TIMEOUT_SHFT 18 -#define HWIO_UMCMN_R0_IMR_S18_TQM2FW_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x20000 -#define HWIO_UMCMN_R0_IMR_S18_TQM2FW_RELEASE_RING_REQ_ERROR_INTR_SHFT 17 -#define HWIO_UMCMN_R0_IMR_S18_TQM2FW_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x10000 -#define HWIO_UMCMN_R0_IMR_S18_TQM2FW_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 16 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW0_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x8000 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW0_RELEASE_RING_REQ_ERROR_INTR_SHFT 15 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW0_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x4000 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW0_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 14 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW1_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x2000 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW1_RELEASE_RING_REQ_ERROR_INTR_SHFT 13 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW1_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x1000 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW1_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 12 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW2_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x800 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW2_RELEASE_RING_REQ_ERROR_INTR_SHFT 11 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW2_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x400 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW2_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 10 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW3_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x200 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW3_RELEASE_RING_REQ_ERROR_INTR_SHFT 9 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW3_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x100 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW3_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 8 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW4_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x80 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW4_RELEASE_RING_REQ_ERROR_INTR_SHFT 7 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW4_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x40 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW4_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 6 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW5_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x20 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW5_RELEASE_RING_REQ_ERROR_INTR_SHFT 5 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW5_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x10 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW5_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 4 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW6_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x8 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW6_RELEASE_RING_REQ_ERROR_INTR_SHFT 3 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW6_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x4 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW6_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 2 -#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x2 -#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_RING_REQ_ERROR_INTR_SHFT 1 -#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x1 -#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 0 - -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x1ff -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK 0x100 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT 8 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK 0x80 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT 7 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK 0x40 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT 6 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK 0x20 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT 5 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n) ((base) + 0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n) ((base) + 0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n) (0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn 7 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR 0x00000000 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR 0x3 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n) \ - in_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n)) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val) \ - out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n)) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT 0 - -#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x) ((x) + 0x14) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_PHYS(x) ((x) + 0x14) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_OFFS (0x14) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_RMSK 0x3ffe0 -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CTRL_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_TIMEOUT_VAL_SHFT 6 -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_RNG_PRTY_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_RNG_PRTY_SHFT 5 - -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x) ((x) + 0x18) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_PHYS(x) ((x) + 0x18) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_OFFS (0x18) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_RMSK 0x3ffe0 -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CTRL_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_TIMEOUT_VAL_SHFT 6 -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_RNG_PRTY_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_RNG_PRTY_SHFT 5 - -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL7_RNG_HALT_STAT_BMSK 0x20000 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL7_RNG_HALT_STAT_SHFT 17 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL6_RNG_HALT_STAT_BMSK 0x10000 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL6_RNG_HALT_STAT_SHFT 16 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL7_RNG_HALT_BMSK 0x200 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL7_RNG_HALT_SHFT 9 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL6_RNG_HALT_BMSK 0x100 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL6_RNG_HALT_SHFT 8 -#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK 0x200000 -#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT 21 -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x) ((x) + 0x34) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_PHYS(x) ((x) + 0x34) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_OFFS (0x34) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_RMSK 0xffffffff -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_POR 0x005a0060 -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ATTR 0x3 -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_IN(x) \ - in_dword(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x)) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x), m) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_OUT(x, v) \ - out_dword(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x),v) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x),m,v,HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_IN(x)) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_NATIVE_WIFI_BMSK 0xffff0000 -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_NATIVE_WIFI_SHFT 16 -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_RAW_WIFI_BMSK 0xffff -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_RAW_WIFI_SHFT 0 - -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x) ((x) + 0x38) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_PHYS(x) ((x) + 0x38) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_OFFS (0x38) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_RMSK 0xffffffff -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_POR 0x004a004a -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ATTR 0x3 -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_IN(x) \ - in_dword(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x)) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x), m) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_OUT(x, v) \ - out_dword(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x),v) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x),m,v,HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_IN(x)) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_IEEE_802_BMSK 0xffff0000 -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_IEEE_802_SHFT 16 -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ETHERNET_II_BMSK 0xffff -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ETHERNET_II_SHFT 0 - -#define HWIO_TCL_R0_UMXI_PRIORITY0_FW2TCL1_RING_BMSK 0xc000 -#define HWIO_TCL_R0_UMXI_PRIORITY0_FW2TCL1_RING_SHFT 14 -#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL7_RING_BMSK 0x3000 -#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL7_RING_SHFT 12 -#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL6_RING_BMSK 0xc00 -#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL6_RING_SHFT 10 -#define HWIO_TCL_R0_UMXI_PRIORITY1_METADATA_FETCH_GXI_RD_BMSK 0xc0 -#define HWIO_TCL_R0_UMXI_PRIORITY1_METADATA_FETCH_GXI_RD_SHFT 6 -#define HWIO_TCL_R0_UMXI_PRIORITY1_PEER_TABLE_FETCH_GXI_RD_BMSK 0x30 -#define HWIO_TCL_R0_UMXI_PRIORITY1_PEER_TABLE_FETCH_GXI_RD_SHFT 4 - -#define HWIO_TCL_R0_VC_ID_MAP_FW2TCL1_RING_BMSK 0x80 -#define HWIO_TCL_R0_VC_ID_MAP_FW2TCL1_RING_SHFT 7 -#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL7_RING_BMSK 0x40 -#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL7_RING_SHFT 6 -#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL6_RING_BMSK 0x20 -#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL6_RING_SHFT 5 -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x) ((x) + 0x64) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_PHYS(x) ((x) + 0x64) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_OFFS (0x64) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_RMSK 0x1fff -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_POR 0x00000004 -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_DESC_RD_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_TIMEOUT_LIMIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_BUNCH_COUNT_BMSK 0x1f -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_BUNCH_COUNT_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x) ((x) + 0x68) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_PHYS(x) ((x) + 0x68) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_OFFS (0x68) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_RMSK 0x1fff -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_POR 0x00000004 -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_DESC_RD_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_TIMEOUT_LIMIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_BUNCH_COUNT_BMSK 0x1f -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_BUNCH_COUNT_SHFT 0 - -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x) ((x) + 0x6c) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_PHYS(x) ((x) + 0x6c) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_OFFS (0x6c) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_RMSK 0x1fff -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_POR 0x00000004 -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_ATTR 0x3 -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_IN(x) \ - in_dword(HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x)) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x), m) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_OUT(x, v) \ - out_dword(HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x),v) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_DESC_RD_IN(x)) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_TIMEOUT_LIMIT_SHFT 5 -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_BUNCH_COUNT_BMSK 0x1f -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_BUNCH_COUNT_SHFT 0 - -#define HWIO_TCL_R0_RBM_MAPPING0_FW2TCL1_RING_BMSK 0xf0000000 -#define HWIO_TCL_R0_RBM_MAPPING0_FW2TCL1_RING_SHFT 28 -#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL7_RING_BMSK 0xf000000 -#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL7_RING_SHFT 24 -#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL6_RING_BMSK 0xf00000 -#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL6_RING_SHFT 20 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X74 + (0x4*(n))) -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 - -#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X174 + (0x4*(n))) -#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_3_TUPLE_IP_ADDR_INDEX_BMSK 0x6000000 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_3_TUPLE_IP_ADDR_INDEX_SHFT 25 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_3_TUPLE_BMSK 0x1000000 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_3_TUPLE_SHFT 24 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK 0x800000 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT 23 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x) ((x) + 0x818) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_PHYS(x) ((x) + 0x818) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_OFFS (0x818) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_RMSK 0xff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IPV6_BMSK 0xf0 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IPV6_SHFT 4 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IPV4_BMSK 0xf -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IPV4_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x) ((x) + 0x81c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_PHYS(x) ((x) + 0x81c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_OFFS (0x81c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x) ((x) + 0x820) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_PHYS(x) ((x) + 0x820) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_OFFS (0x820) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x) ((x) + 0x824) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_PHYS(x) ((x) + 0x824) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_OFFS (0x824) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x) ((x) + 0x828) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_PHYS(x) ((x) + 0x828) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_OFFS (0x828) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x) ((x) + 0x82c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_PHYS(x) ((x) + 0x82c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_OFFS (0x82c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x) ((x) + 0x830) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_PHYS(x) ((x) + 0x830) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_OFFS (0x830) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x) ((x) + 0x834) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_PHYS(x) ((x) + 0x834) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_OFFS (0x834) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x) ((x) + 0x838) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_PHYS(x) ((x) + 0x838) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_OFFS (0x838) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x) ((x) + 0x83c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_PHYS(x) ((x) + 0x83c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_OFFS (0x83c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x) ((x) + 0x840) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_PHYS(x) ((x) + 0x840) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_OFFS (0x840) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x) ((x) + 0x844) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_PHYS(x) ((x) + 0x844) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_OFFS (0x844) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x) ((x) + 0x848) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_PHYS(x) ((x) + 0x848) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_OFFS (0x848) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x) ((x) + 0x84c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_PHYS(x) ((x) + 0x84c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_OFFS (0x84c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x) ((x) + 0x850) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_PHYS(x) ((x) + 0x850) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_OFFS (0x850) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x) ((x) + 0x854) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_PHYS(x) ((x) + 0x854) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_OFFS (0x854) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x) ((x) + 0x858) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_PHYS(x) ((x) + 0x858) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_OFFS (0x858) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_VAL_SHFT 0 - -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x) ((x) + 0x85c) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_PHYS(x) ((x) + 0x85c) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_OFFS (0x85c) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_RMSK 0x3f -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_POR 0x00000000 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ATTR 0x3 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_IN(x) \ - in_dword(HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x)) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x), m) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x),v) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x),m,v,HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_IN(x)) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_HDR_FETCH_BMSK 0x20 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_HDR_FETCH_SHFT 5 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_FLOW_LOOKUP_LCE_RES_BMSK 0x10 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_FLOW_LOOKUP_LCE_RES_SHFT 4 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_LCE_INPUT_FIFO_BMSK 0x8 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_LCE_INPUT_FIFO_SHFT 3 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_FLOW_LOOKUP_INPUT_FIFO_BMSK 0x4 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_FLOW_LOOKUP_INPUT_FIFO_SHFT 2 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_DSCP_TID_MAP_MEM_CTRL_BMSK 0x2 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_DSCP_TID_MAP_MEM_CTRL_SHFT 1 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_LITE_CMD_MAPPER_BMSK 0x1 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_LITE_CMD_MAPPER_SHFT 0 - -#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_8_BMSK 0x1000 -#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_8_SHFT 12 -#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_7_BMSK 0x800 -#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_7_SHFT 11 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_DSCP_TID_MAP_MEM_BMSK 0x1000 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_DSCP_TID_MAP_MEM_SHFT 12 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_FLOW_LOOKUP_RES_MEM_BMSK 0x800 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_FLOW_LOOKUP_RES_MEM_SHFT 11 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_HDR_DATA_MEM_BMSK 0x400 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_HDR_DATA_MEM_SHFT 10 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_DESC_DATA_MEM_BMSK 0x200 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_DESC_DATA_MEM_SHFT 9 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK 0x40 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT 6 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK 0x20 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT 5 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TQM_SRNG_BUNCH_BMSK 0x2 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TQM_SRNG_BUNCH_SHFT 1 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_APB_CLK_BMSK 0x1 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_APB_CLK_SHFT 0 - -#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x) ((x) + 0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x) ((x) + 0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS (0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK 0x3 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR 0x00000000 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR 0x3 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x) \ - in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x)) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v) \ - out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x)) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK 0x2 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT 1 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK 0x1 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT 0 - -#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING7_BMSK 0x80 -#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING7_SHFT 7 -#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS (0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK 0x7 -#define HWIO_TCL_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x) ((x) + 0x8c0) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_PHYS(x) ((x) + 0x8c0) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_OFFS (0x8c0) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_POR 0x00000000 -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ATTR 0x3 -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x)) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x), m) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x),v) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x),m,v,HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_IN(x)) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_BASE_ADDR_BMSK 0xffffffff -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_BASE_ADDR_SHFT 0 - -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x) ((x) + 0x8c4) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_PHYS(x) ((x) + 0x8c4) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_OFFS (0x8c4) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_RMSK 0xff -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_POR 0x00000000 -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ATTR 0x3 -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x)) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x), m) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x),v) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x),m,v,HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_IN(x)) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_BASE_ADDR_BMSK 0xff -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_BASE_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x8c8) -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x8cc) -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x8d0) -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x8d8) -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x8e4) -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x8e8) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x8f8) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x8fc) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x910) -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x914) -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x918) -#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x940) -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x) ((x) + 0xb20) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_PHYS(x) ((x) + 0xb20) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_OFFS (0xb20) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x) ((x) + 0xb24) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_PHYS(x) ((x) + 0xb24) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_OFFS (0xb24) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RMSK 0xfffffff -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x) ((x) + 0xb28) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_PHYS(x) ((x) + 0xb28) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_OFFS (0xb28) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_RMSK 0xff -#define HWIO_TCL_R0_SW2TCL6_RING_ID_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_ID_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_ID_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_ID_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL6_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_ADDR(x) ((x) + 0xb2c) -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_PHYS(x) ((x) + 0xb2c) -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_OFFS (0xb2c) -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_ATTR 0x1 -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_STATUS_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_STATUS_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x) ((x) + 0xb30) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_PHYS(x) ((x) + 0xb30) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_OFFS (0xb30) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_RMSK 0x7fffff -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_POR 0x00000080 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MISC_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xb3c) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xb3c) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_OFFS (0xb3c) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xb40) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xb40) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_OFFS (0xb40) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xb50) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xb50) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xb50) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xb54) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xb54) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xb54) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xb58) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xb58) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_OFFS (0xb58) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xb5c) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xb5c) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xb5c) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xb60) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xb60) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xb60) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xb64) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xb64) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xb64) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xb68) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xb68) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_OFFS (0xb68) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xb6c) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xb6c) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_OFFS (0xb6c) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x) ((x) + 0xb70) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_PHYS(x) ((x) + 0xb70) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_OFFS (0xb70) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xb90) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xb90) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_OFFS (0xb90) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x) ((x) + 0xb94) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_PHYS(x) ((x) + 0xb94) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_OFFS (0xb94) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MISC_1_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x) ((x) + 0xb98) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_PHYS(x) ((x) + 0xb98) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_OFFS (0xb98) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x) ((x) + 0xb9c) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_PHYS(x) ((x) + 0xb9c) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_OFFS (0xb9c) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RMSK 0xfffffff -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x) ((x) + 0xba0) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_PHYS(x) ((x) + 0xba0) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_OFFS (0xba0) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_RMSK 0xff -#define HWIO_TCL_R0_SW2TCL7_RING_ID_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_ID_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_ID_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_ID_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL7_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_ADDR(x) ((x) + 0xba4) -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_PHYS(x) ((x) + 0xba4) -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_OFFS (0xba4) -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_ATTR 0x1 -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_STATUS_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_STATUS_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x) ((x) + 0xba8) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_PHYS(x) ((x) + 0xba8) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_OFFS (0xba8) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_RMSK 0x7fffff -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_POR 0x00000080 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MISC_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xbb4) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xbb4) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_OFFS (0xbb4) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xbb8) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xbb8) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_OFFS (0xbb8) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xbc8) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xbc8) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xbc8) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xbcc) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xbcc) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xbcc) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xbd0) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xbd0) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_OFFS (0xbd0) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xbd4) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xbd4) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xbd4) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xbd8) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xbd8) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xbd8) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xbdc) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xbdc) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xbdc) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xbe0) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xbe0) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_OFFS (0xbe0) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xbe4) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xbe4) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_OFFS (0xbe4) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x) ((x) + 0xbe8) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_PHYS(x) ((x) + 0xbe8) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_OFFS (0xbe8) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xc08) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xc08) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_OFFS (0xc08) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x) ((x) + 0xc0c) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_PHYS(x) ((x) + 0xc0c) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_OFFS (0xc0c) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MISC_1_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL7_RING_BMSK 0x1c0000 -#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL7_RING_SHFT 18 -#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL6_RING_BMSK 0x38000 -#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL6_RING_SHFT 15 -#define HWIO_TCL_R1_SM_STATES_IX_2_EXTN_DESC_FETCH_BMSK 0x1c00 -#define HWIO_TCL_R1_SM_STATES_IX_2_EXTN_DESC_FETCH_SHFT 10 - -#define HWIO_TCL_R1_STATUS_TIMESTMP_FIFO_EMPTY_BMSK 0x4000000 -#define HWIO_TCL_R1_STATUS_TIMESTMP_FIFO_EMPTY_SHFT 26 -#define HWIO_TCL_R1_STATUS_FLOW_LOOKUP_INPUT_FIFO_EMPTY_BMSK 0x2000000 -#define HWIO_TCL_R1_STATUS_FLOW_LOOKUP_INPUT_FIFO_EMPTY_SHFT 25 -#define HWIO_TCL_R1_STATUS_LCE_INPUT_FIFO_EMPTY_BMSK 0x1000000 -#define HWIO_TCL_R1_STATUS_LCE_INPUT_FIFO_EMPTY_SHFT 24 -#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x10000 -#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 16 -#define HWIO_TCL_R1_STATUS_SW2TCL7_CONS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R1_STATUS_SW2TCL7_CONS_IDLE_SHFT 12 -#define HWIO_TCL_R1_STATUS_SW2TCL6_CONS_IDLE_BMSK 0x800 -#define HWIO_TCL_R1_STATUS_SW2TCL6_CONS_IDLE_SHFT 11 -#define HWIO_TCL_R1_STATUS_HDR_FETCH_IDLE_BMSK 0x4 -#define HWIO_TCL_R1_STATUS_HDR_FETCH_IDLE_SHFT 2 -#define HWIO_TCL_R1_STATUS_CMD_MAPPER_IDLE_BMSK 0x2 -#define HWIO_TCL_R1_STATUS_CMD_MAPPER_IDLE_SHFT 1 -#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL7_RING_BMSK 0x1c0000 -#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL7_RING_SHFT 18 -#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL6_RING_BMSK 0x38000 -#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL6_RING_SHFT 15 -#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_EXTN_DESC_FETCH_BMSK 0x1c00 -#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_EXTN_DESC_FETCH_SHFT 10 - -#define HWIO_TCL_R1_WDOG_STATUS_TIMESTMP_FIFO_EMPTY_BMSK 0x4000000 -#define HWIO_TCL_R1_WDOG_STATUS_TIMESTMP_FIFO_EMPTY_SHFT 26 -#define HWIO_TCL_R1_WDOG_STATUS_FLOW_LOOKUP_INPUT_FIFO_EMPTY_BMSK 0x2000000 -#define HWIO_TCL_R1_WDOG_STATUS_FLOW_LOOKUP_INPUT_FIFO_EMPTY_SHFT 25 -#define HWIO_TCL_R1_WDOG_STATUS_LCE_INPUT_FIFO_EMPTY_BMSK 0x1000000 -#define HWIO_TCL_R1_WDOG_STATUS_LCE_INPUT_FIFO_EMPTY_SHFT 24 -#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x10000 -#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 16 -#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL7_CONS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL7_CONS_IDLE_SHFT 12 -#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL6_CONS_IDLE_BMSK 0x800 -#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL6_CONS_IDLE_SHFT 11 -#define HWIO_TCL_R1_WDOG_STATUS_HDR_FETCH_IDLE_BMSK 0x4 -#define HWIO_TCL_R1_WDOG_STATUS_HDR_FETCH_IDLE_SHFT 2 -#define HWIO_TCL_R1_WDOG_STATUS_CMD_MAPPER_IDLE_BMSK 0x2 -#define HWIO_TCL_R1_WDOG_STATUS_CMD_MAPPER_IDLE_SHFT 1 -#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL7_BMSK 0x40 -#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL7_SHFT 6 -#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL6_BMSK 0x20 -#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL6_SHFT 5 -#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS (0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK 0x1ff -#define HWIO_TCL_R1_TESTBUS_CTRL_POR 0x00000000 -#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR 0x3 -#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x) \ - in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)) -#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m) -#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v) -#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x)) -#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x100 -#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 8 -#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK 0xc0 -#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT 6 -#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK 0x3f -#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT 0 - -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn 511 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) -#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) -#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x) ((x) + 0x2028) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_PHYS(x) ((x) + 0x2028) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_OFFS (0x2028) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_RMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL6_RING_HP_POR 0x00000000 -#define HWIO_TCL_R2_SW2TCL6_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TCL_R2_SW2TCL6_RING_HP_ATTR 0x3 -#define HWIO_TCL_R2_SW2TCL6_RING_HP_IN(x) \ - in_dword(HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x)) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x), m) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_OUT(x, v) \ - out_dword(HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x),v) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL6_RING_HP_IN(x)) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_HEAD_PTR_BMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL6_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x) ((x) + 0x202c) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_PHYS(x) ((x) + 0x202c) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_OFFS (0x202c) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_RMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL6_RING_TP_POR 0x00000000 -#define HWIO_TCL_R2_SW2TCL6_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TCL_R2_SW2TCL6_RING_TP_ATTR 0x3 -#define HWIO_TCL_R2_SW2TCL6_RING_TP_IN(x) \ - in_dword(HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x)) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x), m) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_OUT(x, v) \ - out_dword(HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x),v) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL6_RING_TP_IN(x)) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_TAIL_PTR_BMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL6_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x) ((x) + 0x2030) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_PHYS(x) ((x) + 0x2030) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_OFFS (0x2030) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_RMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL7_RING_HP_POR 0x00000000 -#define HWIO_TCL_R2_SW2TCL7_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TCL_R2_SW2TCL7_RING_HP_ATTR 0x3 -#define HWIO_TCL_R2_SW2TCL7_RING_HP_IN(x) \ - in_dword(HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x)) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x), m) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_OUT(x, v) \ - out_dword(HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x),v) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL7_RING_HP_IN(x)) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_HEAD_PTR_BMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL7_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x) ((x) + 0x2034) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_PHYS(x) ((x) + 0x2034) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_OFFS (0x2034) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_RMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL7_RING_TP_POR 0x00000000 -#define HWIO_TCL_R2_SW2TCL7_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TCL_R2_SW2TCL7_RING_TP_ATTR 0x3 -#define HWIO_TCL_R2_SW2TCL7_RING_TP_IN(x) \ - in_dword(HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x)) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x), m) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_OUT(x, v) \ - out_dword(HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x),v) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL7_RING_TP_IN(x)) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_TAIL_PTR_BMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL7_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT16_BMSK 0x10000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT16_SHFT 16 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT15_BMSK 0x8000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT15_SHFT 15 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT12_BMSK 0x1000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT12_SHFT 12 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT7_BMSK 0x80 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT7_SHFT 7 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT16_BMSK 0x10000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT16_SHFT 16 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT15_BMSK 0x8000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT15_SHFT 15 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT12_BMSK 0x1000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT12_SHFT 12 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT7_BMSK 0x80 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT7_SHFT 7 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT1_SHFT 1 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT1_SHFT 1 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT1_SHFT 1 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT1_SHFT 1 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT23_BMSK 0x800000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT23_SHFT 23 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT22_BMSK 0x400000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT22_SHFT 22 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT21_BMSK 0x200000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT21_SHFT 21 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT20_BMSK 0x100000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT20_SHFT 20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT19_BMSK 0x80000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT19_SHFT 19 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT18_BMSK 0x40000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT18_SHFT 18 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT17_BMSK 0x20000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT17_SHFT 17 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT16_BMSK 0x10000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT16_SHFT 16 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT15_BMSK 0x8000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT15_SHFT 15 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT12_BMSK 0x1000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT12_SHFT 12 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT7_BMSK 0x80 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT7_SHFT 7 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT23_BMSK 0x800000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT23_SHFT 23 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT22_BMSK 0x400000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT22_SHFT 22 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT21_BMSK 0x200000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT21_SHFT 21 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT20_BMSK 0x100000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT20_SHFT 20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT19_BMSK 0x80000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT19_SHFT 19 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT18_BMSK 0x40000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT18_SHFT 18 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT17_BMSK 0x20000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT17_SHFT 17 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT16_BMSK 0x10000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT16_SHFT 16 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT15_BMSK 0x8000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT15_SHFT 15 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT12_BMSK 0x1000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT12_SHFT 12 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT7_BMSK 0x80 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT7_SHFT 7 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT23_BMSK 0x800000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT23_SHFT 23 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT22_BMSK 0x400000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT22_SHFT 22 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT21_BMSK 0x200000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT21_SHFT 21 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT20_BMSK 0x100000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT20_SHFT 20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT19_BMSK 0x80000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT19_SHFT 19 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT18_BMSK 0x40000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT18_SHFT 18 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT17_BMSK 0x20000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT17_SHFT 17 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT16_BMSK 0x10000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT16_SHFT 16 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT15_BMSK 0x8000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT15_SHFT 15 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT12_BMSK 0x1000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT12_SHFT 12 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT7_BMSK 0x80 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT7_SHFT 7 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT19_BMSK 0x80000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT19_SHFT 19 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT18_BMSK 0x40000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT18_SHFT 18 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT17_BMSK 0x20000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT17_SHFT 17 - -#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 -#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 -#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 -#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 -#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_ADDR(x) ((x) + 0x4400) -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_PHYS(x) ((x) + 0x4400) -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_OFFS (0x4400) -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_RMSK 0xffffff -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_POR 0x0020e93b -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_POR_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_ATTR 0x1 -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_IN(x) \ - in_dword(HWIO_UMAC_NOC_DEBUG_SWID_LOW_ADDR(x)) -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_INM(x, m) \ - in_dword_masked(HWIO_UMAC_NOC_DEBUG_SWID_LOW_ADDR(x), m) -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_UNITTYPEID_BMSK 0xff0000 -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_UNITTYPEID_SHFT 16 -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_UNITCONFID_BMSK 0xffff -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_UNITCONFID_SHFT 0 - -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_ADDR(x) ((x) + 0x4404) -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_PHYS(x) ((x) + 0x4404) -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_OFFS (0x4404) -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_POR 0xb51bbb75 -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_POR_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_ATTR 0x1 -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_IN(x) \ - in_dword(HWIO_UMAC_NOC_DEBUG_SWID_HIGH_ADDR(x)) -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_INM(x, m) \ - in_dword_masked(HWIO_UMAC_NOC_DEBUG_SWID_HIGH_ADDR(x), m) -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_QNOCID_BMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_QNOCID_SHFT 0 - -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_ADDR(x) ((x) + 0x4408) -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_PHYS(x) ((x) + 0x4408) -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_OFFS (0x4408) -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_RMSK 0x1 -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_POR 0x00000000 -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_POR_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_ATTR 0x1 -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_IN(x) \ - in_dword(HWIO_UMAC_NOC_DEBUG_LOAD_LOW_ADDR(x)) -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_INM(x, m) \ - in_dword_masked(HWIO_UMAC_NOC_DEBUG_LOAD_LOW_ADDR(x), m) -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_LOAD_BMSK 0x1 -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_LOAD_SHFT 0 - -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_ADDR(x) ((x) + 0x4410) -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_PHYS(x) ((x) + 0x4410) -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_OFFS (0x4410) -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_POR 0xdeadbeef -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_POR_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_ATTR 0x1 -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_IN(x) \ - in_dword(HWIO_UMAC_NOC_DEBUG_DUMP_LOW_ADDR(x)) -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_INM(x, m) \ - in_dword_masked(HWIO_UMAC_NOC_DEBUG_DUMP_LOW_ADDR(x), m) -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_DUMP_LSB_BMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_DUMP_LSB_SHFT 0 - -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_ADDR(x) ((x) + 0x4414) -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_PHYS(x) ((x) + 0x4414) -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_OFFS (0x4414) -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_POR 0xdeadbeef -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_POR_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_ATTR 0x1 -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_IN(x) \ - in_dword(HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_ADDR(x)) -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_INM(x, m) \ - in_dword_masked(HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_ADDR(x), m) -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_DUMP_MSB_BMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_DUMP_MSB_SHFT 0 - -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_ADDR(x) ((x) + 0x4418) -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_PHYS(x) ((x) + 0x4418) -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_OFFS (0x4418) -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_RMSK 0xffff -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_POR 0x000000dd -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_POR_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_ATTR 0x1 -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_IN(x) \ - in_dword(HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_ADDR(x)) -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_INM(x, m) \ - in_dword_masked(HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_ADDR(x), m) -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_SHIFTREGLEN_BMSK 0xffff -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_SHIFTREGLEN_SHFT 0 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h b/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h deleted file mode 100644 index 072ec2ed4af7..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOREG_WIFI_TOP_H -#define WCSS_SEQ_HWIOREG_WIFI_TOP_H - -#include "wcss_seq_hwiobase.h" - -#define WFSS_PMM_REG_BASE (WFSS_PMM_BASE + 0x00000000) - -#define HWIO_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_26_ADDR(x) ((x) + 0x164) - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_version.h b/drivers/staging/fw-api/hw/wcn8750/v1/wcss_version.h deleted file mode 100644 index cbfded86e5a4..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_version.h +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#define WCSS_VERSION 3150 diff --git a/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_internal.h b/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_internal.h index 61c290aea844..77b1337baca5 100644 --- a/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_internal.h +++ b/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_internal.h @@ -2363,14 +2363,6 @@ void dp_is_hw_dbs_enable(struct dp_soc *soc, #if defined(WLAN_SUPPORT_RX_FISA) void dp_rx_dump_fisa_table(struct dp_soc *soc); -/** - * dp_print_fisa_stats() - Print FISA stats - * @soc: DP soc handle - * - * Return: None - */ -void dp_print_fisa_stats(struct dp_soc *soc); - /* * dp_rx_fst_update_cmem_params() - Update CMEM FST params * @soc: DP SoC context @@ -2396,10 +2388,6 @@ static inline void dp_rx_fst_update_pm_suspend_status(struct dp_soc *soc, bool suspended) { } - -static inline void dp_print_fisa_stats(struct dp_soc *soc) -{ -} #endif /* WLAN_SUPPORT_RX_FISA */ #ifdef MAX_ALLOC_PAGE_SIZE diff --git a/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_main.c b/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_main.c index c0806f998969..7016cfacc9e6 100644 --- a/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_main.c +++ b/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_main.c @@ -10101,7 +10101,6 @@ static QDF_STATUS dp_txrx_dump_stats(struct cdp_soc_t *psoc, uint16_t value, dp_txrx_path_stats(soc); dp_print_soc_interrupt_stats(soc); hal_dump_reg_write_stats(soc->hal_soc); - dp_print_fisa_stats(soc); break; case CDP_RX_RING_STATS: diff --git a/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_types.h b/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_types.h index 65057170c078..25ba47531cd1 100644 --- a/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_types.h +++ b/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_types.h @@ -3134,23 +3134,10 @@ struct dp_rx_fst { #define DP_RX_GET_SW_FT_ENTRY_SIZE sizeof(struct dp_rx_fse) #elif WLAN_SUPPORT_RX_FISA -/** - * struct dp_fisa_reo_mismatch_stats - reo mismatch sub-case stats for FISA - * @allow_cce_match: packet allowed due to cce mismatch - * @allow_fse_metdata_mismatch: packet allowed since it belongs to same flow, - * only fse_metadata is not same. - * @allow_non_aggr: packet allowed due to any other reason. - */ -struct dp_fisa_reo_mismatch_stats { - uint32_t allow_cce_match; - uint32_t allow_fse_metdata_mismatch; - uint32_t allow_non_aggr; -}; - struct dp_fisa_stats { /* flow index invalid from RX HW TLV */ uint32_t invalid_flow_index; - struct dp_fisa_reo_mismatch_stats reo_mismatch; + uint32_t reo_mismatch; uint32_t incorrect_rdi; }; diff --git a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_main.c b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_main.c index 895c1bd94f46..14f4f978fef5 100644 --- a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_main.c +++ b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_main.c @@ -2227,7 +2227,7 @@ hif_send_head(struct hif_opaque_softc *hif_ctx, if (qdf_unlikely(!ce_hdl)) { hif_err("CE handle is null"); - return QDF_STATUS_E_FAILURE; + return A_ERROR; } QDF_NBUF_UPDATE_TX_PKT_COUNT(nbuf, QDF_NBUF_TX_PKT_HIF); diff --git a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_trace.c b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_trace.c index 30815cb19d89..0b3e2dbd150d 100644 --- a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_trace.c +++ b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_trace.c @@ -411,19 +411,10 @@ void qdf_mtrace_log(QDF_MODULE_ID src_module, QDF_MODULE_ID dst_module, uint16_t message_id, uint8_t vdev_id) { uint32_t trace_log, payload; - static __qdf_atomic_t counter; - static bool initialized = false; - - // Initialize counter only once - if (!initialized) { - qdf_atomic_init(&counter); - initialized = true; - } + static uint16_t counter; trace_log = (src_module << 23) | (dst_module << 15) | message_id; - - qdf_atomic_add(1, &counter); - payload = ((uint32_t)vdev_id << 16) | (qdf_atomic_read(&counter) & 0xFFFF); + payload = (vdev_id << 16) | counter++; QDF_TRACE(src_module, QDF_TRACE_LEVEL_TRACE, "%x %x", trace_log, payload); diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_build_chan_list.c b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_build_chan_list.c index b5d40a746a81..6059b406d57b 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_build_chan_list.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_build_chan_list.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1079,7 +1079,7 @@ reg_append_mas_chan_list_for_6g_lpi(struct wlan_regulatory_pdev_priv_obj struct regulatory_channel *master_chan_list_6g_client_lpi; uint8_t i, j; - if (!pdev_priv_obj->reg_rules.num_of_6g_client_reg_rules[REG_INDOOR_AP]) { + if (!pdev_priv_obj->reg_rules.num_of_6g_ap_reg_rules[REG_INDOOR_AP]) { reg_debug("No LPI reg rules"); return; } @@ -1117,7 +1117,7 @@ reg_append_mas_chan_list_for_6g_vlp(struct wlan_regulatory_pdev_priv_obj struct regulatory_channel *master_chan_list_6g_client_vlp; uint8_t i, j; - if (!pdev_priv_obj->reg_rules.num_of_6g_client_reg_rules[REG_VERY_LOW_POWER_AP]) { + if (!pdev_priv_obj->reg_rules.num_of_6g_ap_reg_rules[REG_VERY_LOW_POWER_AP]) { reg_debug("No VLP reg rules"); return; } @@ -1758,8 +1758,9 @@ static void reg_store_regulatory_ext_info_to_socpriv( soc_reg->domain_code_6g_ap[i] = regulat_info->domain_code_6g_ap[i]; - soc_reg->mas_chan_params[phy_id]. - is_6g_channel_list_populated = true; + if (soc_reg->domain_code_6g_ap[i]) + soc_reg->mas_chan_params[phy_id]. + is_6g_channel_list_populated = true; qdf_mem_copy(soc_reg->domain_code_6g_client[i], regulat_info->domain_code_6g_client[i], @@ -2088,11 +2089,6 @@ QDF_STATUS reg_process_master_chan_list_ext( reg_store_regulatory_ext_info_to_socpriv(soc_reg, regulat_info, phy_id); - if (this_mchan_params->client_type >= REG_MAX_CLIENT_TYPE) { - reg_err("6 GHz reg client type invalid"); - return QDF_STATUS_E_FAILURE; - } - status = reg_fill_master_channels(regulat_info, &this_mchan_params->reg_rules, this_mchan_params->client_type, diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.c b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.c index 328a4898dcd1..7732e35b5ee4 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022,2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -5113,7 +5113,7 @@ QDF_STATUS reg_get_6g_chan_ap_power(struct wlan_objmgr_pdev *pdev, QDF_STATUS reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, enum reg_6g_ap_type ap_type, qdf_freq_t chan_freq, - bool is_psd, + bool *is_psd, uint16_t *tx_power, uint16_t *eirp_psd_power) { @@ -5136,7 +5136,8 @@ QDF_STATUS reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, reg_find_txpower_from_6g_list(chan_freq, master_chan_list, tx_power); - if (is_psd) + *is_psd = reg_is_6g_psd_power(pdev); + if (*is_psd) status = reg_get_6g_chan_psd_eirp_power(chan_freq, master_chan_list, eirp_psd_power); diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.h b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.h index 3a94a215298a..c0d478ea1887 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * * * Permission to use, copy, modify, and/or distribute this software for @@ -1484,7 +1484,7 @@ QDF_STATUS reg_get_6g_chan_ap_power(struct wlan_objmgr_pdev *pdev, * * This function is meant to be called to find the channel frequency power * information for a client when the device is operating as a client. It will - * fill in the parameters tx_power and eirp_psd_power. eirp_psd_power + * fill in the parameter is_psd, tx_power, and eirp_psd_power. eirp_psd_power * will only be filled if the channel is PSD. * * Return: QDF_STATUS @@ -1492,7 +1492,7 @@ QDF_STATUS reg_get_6g_chan_ap_power(struct wlan_objmgr_pdev *pdev, QDF_STATUS reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, enum reg_6g_ap_type ap_type, qdf_freq_t chan_freq, - bool is_psd, + bool *is_psd, uint16_t *tx_power, uint16_t *eirp_psd_power); @@ -1582,10 +1582,11 @@ static inline QDF_STATUS reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, enum reg_6g_ap_type ap_type, qdf_freq_t chan_freq, - bool is_psd, + bool *is_psd, uint16_t *tx_power, uint16_t *eirp_psd_power) { + *is_psd = false; *tx_power = 0; *eirp_psd_power = 0; return QDF_STATUS_E_NOSUPPORT; diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/wlan_reg_services_api.h b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/wlan_reg_services_api.h index c380a077abe5..d8c7ad95a133 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/wlan_reg_services_api.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/wlan_reg_services_api.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1869,8 +1869,8 @@ QDF_STATUS wlan_reg_get_6g_chan_ap_power(struct wlan_objmgr_pdev *pdev, * * This function is meant to be called to find the channel frequency power * information for a client when the device is operating as a client. It will - * fill in the parameters tx_power and eirp_psd_power. eirp_psd_power will - * only be filled if the channel is PSD. + * fill in the parameter is_psd, tx_power, and eirp_psd_power. eirp_psd_power + * will only be filled if the channel is PSD. * * Return: QDF_STATUS */ @@ -1878,7 +1878,7 @@ QDF_STATUS wlan_reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, enum reg_6g_ap_type ap_type, qdf_freq_t chan_freq, - bool is_psd, uint16_t *tx_power, + bool *is_psd, uint16_t *tx_power, uint16_t *eirp_psd_power); /** @@ -1985,9 +1985,10 @@ static inline QDF_STATUS wlan_reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, enum reg_6g_ap_type ap_type, qdf_freq_t chan_freq, - bool is_psd, uint16_t *tx_power, + bool *is_psd, uint16_t *tx_power, uint16_t *eirp_psd_power) { + *is_psd = false; *tx_power = 0; *eirp_psd_power = 0; return QDF_STATUS_E_NOSUPPORT; diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/src/wlan_reg_services_api.c b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/src/wlan_reg_services_api.c index 7d458f0421fc..2b720dee6ca6 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/src/wlan_reg_services_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/src/wlan_reg_services_api.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * * Permission to use, copy, modify, and/or distribute this software for @@ -1443,7 +1443,7 @@ QDF_STATUS wlan_reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, enum reg_6g_ap_type ap_type, qdf_freq_t chan_freq, - bool is_psd, uint16_t *tx_power, + bool *is_psd, uint16_t *tx_power, uint16_t *eirp_psd_power) { return reg_get_client_power_for_connecting_ap(pdev, ap_type, chan_freq, diff --git a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c index b9359e099ce6..cd998b35ca7e 100644 --- a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c +++ b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c @@ -14208,14 +14208,9 @@ extract_roam_scan_ap_stats_tlv(wmi_unified_t wmi_handle, void *evt_buf, return QDF_STATUS_E_FAILURE; } - /* - * Check to validate that the requested number of APs do not exceed the - * remaining APs in param_buf after ap_idx to prevent out of bounds - * access. - */ - if ((ap_idx + num_cand) > param_buf->num_roam_ap_info) { - wmi_err("Invalid roam scan AP tlv ap_idx:%d, num_cand:%d, total_ap:%d", - ap_idx, num_cand, param_buf->num_roam_ap_info); + if (ap_idx >= param_buf->num_roam_ap_info) { + wmi_err("Invalid roam scan AP tlv ap_idx:%d total_ap:%d", + ap_idx, param_buf->num_roam_ap_info); return QDF_STATUS_E_FAILURE; } @@ -14729,12 +14724,6 @@ static QDF_STATUS extract_pdev_csa_switch_count_status_tlv( wmi_handle, csa_status->pdev_id); param->current_switch_count = csa_status->current_switch_count; - - if (param_buf->num_vdev_ids != csa_status->num_vdevs) { - wmi_err("Invalid number of vdevs: received = %d, expected = %d", - csa_status->num_vdevs, param_buf->num_vdev_ids); - return QDF_STATUS_E_INVAL; - } param->num_vdevs = csa_status->num_vdevs; param->vdev_ids = param_buf->vdev_ids; diff --git a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h index 141ce08f47a2..d902f7ee4327 100644 --- a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h +++ b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h @@ -210,24 +210,6 @@ QDF_STATUS policy_mgr_get_sta_sap_scc_on_dfs_chnl(struct wlan_objmgr_psoc *psoc, uint8_t *sta_sap_scc_on_dfs_chnl); -/** - * policy_mgr_is_bonded_chan_dfs() - check whether the given bonded - * channel configuration falls under DFS - * @psoc: pointer to psoc - * @ch_width: channel width of the operating channel - * @mhz_freq_seg1: center frequency of segment 1; used for 80+80 MHz - * @chan_freq: primary/operating channel frequency in MHz - * - * This API checks whether the given channel or bonded channel span - * includes DFS, based on the channel width and frequency segments. - * - * Return: true if the given bonded channel is DFS, else false. - */ -bool -policy_mgr_is_bonded_chan_dfs(struct wlan_objmgr_psoc *psoc, - enum phy_ch_width ch_width, - qdf_freq_t mhz_freq_seg1, - uint32_t chan_freq); /** * policy_mgr_get_dfs_master_dynamic_enabled() - support dfs master or not * on AP interafce when STA+SAP(GO) concurrency diff --git a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c index 0bffbe5e612e..5661c5a03491 100644 --- a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c +++ b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c @@ -181,45 +181,6 @@ policy_mgr_get_sta_sap_scc_on_dfs_chnl(struct wlan_objmgr_psoc *psoc, return QDF_STATUS_SUCCESS; } -bool -policy_mgr_is_bonded_chan_dfs(struct wlan_objmgr_psoc *psoc, - enum phy_ch_width ch_width, - qdf_freq_t mhz_freq_seg1, - uint32_t chan_freq) -{ - bool is_ch_dfs = false; - struct policy_mgr_psoc_priv_obj *pm_ctx; - - pm_ctx = policy_mgr_get_context(psoc); - if (!pm_ctx) { - policy_mgr_err("pm_ctx is NULL"); - return false; - } - - if (ch_width == CH_WIDTH_160MHZ) { - if (wlan_reg_get_5g_bonded_channel_state_for_freq(pm_ctx->pdev, - chan_freq, - ch_width) - == CHANNEL_STATE_DFS) - is_ch_dfs = true; - } else if (ch_width == CH_WIDTH_80P80MHZ) { - if (wlan_reg_get_channel_state_for_freq( - pm_ctx->pdev, - chan_freq) == - CHANNEL_STATE_DFS || - wlan_reg_get_channel_state_for_freq( - pm_ctx->pdev, - mhz_freq_seg1) == - CHANNEL_STATE_DFS) - is_ch_dfs = true; - } else { - if (wlan_reg_is_dfs_for_freq(pm_ctx->pdev, chan_freq)) - is_ch_dfs = true; - } - - return is_ch_dfs; -} - static bool policy_mgr_update_dfs_master_dynamic_enabled( struct wlan_objmgr_psoc *psoc, uint8_t vdev_id) diff --git a/drivers/staging/qcacld-3.0/components/mlme/core/src/wlan_mlme_main.c b/drivers/staging/qcacld-3.0/components/mlme/core/src/wlan_mlme_main.c index 131518cc5cd9..66f4ef140432 100644 --- a/drivers/staging/qcacld-3.0/components/mlme/core/src/wlan_mlme_main.c +++ b/drivers/staging/qcacld-3.0/components/mlme/core/src/wlan_mlme_main.c @@ -1,7 +1,6 @@ /* * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1847,8 +1846,6 @@ static void mlme_init_lfr_cfg(struct wlan_objmgr_psoc *psoc, cfg_get(psoc, CFG_LFR3_ROAM_PREAUTH_RETRY_COUNT); lfr->roam_rssi_diff = cfg_get(psoc, CFG_LFR_ROAM_RSSI_DIFF); lfr->roam_rssi_diff_6ghz = cfg_get(psoc, CFG_LFR_ROAM_RSSI_DIFF_6GHZ); - lfr->roam_rssi_delta_6ghz_to_non_6ghz = - cfg_get(psoc, CFG_LFR_ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ); lfr->bg_rssi_threshold = cfg_get(psoc, CFG_LFR_ROAM_BG_RSSI_TH); lfr->roam_scan_offload_enabled = cfg_get(psoc, CFG_LFR_ROAM_SCAN_OFFLOAD_ENABLED); diff --git a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/cfg_mlme_lfr.h b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/cfg_mlme_lfr.h index 135eb7597a3c..6ad5d7011e58 100644 --- a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/cfg_mlme_lfr.h +++ b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/cfg_mlme_lfr.h @@ -1,7 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1281,38 +1280,6 @@ CFG_VALUE_OR_DEFAULT, \ "Enable 6 GHz roam based on rssi") -/* - * - * roam_rssi_delta_from_6ghz_to_non_6ghz - Enable roam to Non 6 GHz AP based - * on rssi - * @Min: 0 - * @Max: 100 - * @Default: 0 - * - * This INI is used to decide whether to roam to Non 6 GHz AP or not based on - * RSSI. AP1 is the currently associated AP(6 GHz) and AP2(2.4 GHz / 5 GHz) is - * chosen for roaming. The Roaming will happen only if AP2 has better Signal - * Quality and it has a RSSI better than AP1. - * roam_rssi_delta_from_6ghz_to_non_6ghz is the number of dB units AP2 is - * better than AP1. - * - * - * Related: None - * - * Supported Feature: Roaming - * - * Usage: External - * - * - */ -#define CFG_LFR_ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ CFG_INI_UINT( \ - "roam_rssi_delta_from_6ghz_to_non_6ghz", \ - 0, \ - 100, \ - 0, \ - CFG_VALUE_OR_DEFAULT, \ - "Enable 6 GHz to non 6 GHz roam based on rssi") - /* * * bg_rssi_threshold - To set RSSI Threshold for BG scan roaming @@ -2963,7 +2930,6 @@ CFG(CFG_LFR_FAST_TRANSITION_ENABLED) \ CFG(CFG_LFR_ROAM_RSSI_DIFF) \ CFG(CFG_LFR_ROAM_RSSI_DIFF_6GHZ) \ - CFG(CFG_LFR_ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ) \ CFG(CFG_LFR_ROAM_BG_RSSI_TH) \ CFG(CFG_LFR_ENABLE_WES_MODE) \ CFG(CFG_LFR_ROAM_SCAN_OFFLOAD_ENABLED) \ diff --git a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_api.h b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_api.h index 3b757579f129..401bd9c549e5 100644 --- a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_api.h +++ b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_api.h @@ -2444,30 +2444,11 @@ wlan_mlme_get_ignore_fw_reg_offload_ind(struct wlan_objmgr_psoc *psoc, char *mlme_get_roam_trigger_str(uint32_t roam_scan_trigger); /** - * enum roam_stats_scan_type - Roam scan type defines - * @ROAM_STATS_SCAN_TYPE_PARTIAL: Partial scan - * @ROAM_STATS_SCAN_TYPE_FULL: Full scan - * @ROAM_STATS_SCAN_TYPE_NO_SCAN: No roam scan was triggered. This is generally - * used in BTM events to indicate BTM frame exchange logs. - * @ROAM_STATS_SCAN_TYPE_HIGHER_BAND_5GHZ_6GHZ: Higher band roam scan from 2 GHz - * to 5 GHz or 6 GHz - * @ROAM_STATS_SCAN_TYPE_HIGHER_BAND_6GHZ: Higher band roam scan from 5 GHz to - * 6 GHz - */ -enum roam_stats_scan_type { - ROAM_STATS_SCAN_TYPE_PARTIAL = 0, - ROAM_STATS_SCAN_TYPE_FULL = 1, - ROAM_STATS_SCAN_TYPE_NO_SCAN = 2, - ROAM_STATS_SCAN_TYPE_HIGHER_BAND_5GHZ_6GHZ = 3, - ROAM_STATS_SCAN_TYPE_HIGHER_BAND_6GHZ = 4, -}; - -/** - * mlme_get_roam_scan_type_str() - Get the string for roam scan type + * mlme_get_roam_scan_type_str() - Get the string for roam sacn type * @roam_scan_type: roam scan type coming from fw via * wmi_roam_scan_info tlv * - * Return: Meaningful string for roam scan type + * Return: Meaningful string for roam sacn type */ char *mlme_get_roam_scan_type_str(uint32_t roam_scan_type); diff --git a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_public_struct.h b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_public_struct.h index 9ca94e78d468..ad48cd35c0cd 100644 --- a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_public_struct.h +++ b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_public_struct.h @@ -1,7 +1,6 @@ /* * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1681,10 +1680,8 @@ struct fw_scan_channels { * @roam_preauth_no_ack_timeout: Configure the no ack timeout period * @roam_rssi_diff: Enable roam based on rssi * @roam_rssi_diff_6ghz: RSSI diff value to be used for roaming to 6 GHz AP. - * @roam_rssi_delta_6ghz_to_non_6ghz: RSSI diff value to be used for - * roaming from 6 GHz to Non 6GHz AP. - * @roam_scan_offload_enabled: Enable Roam Scan Offload - * @neighbor_scan_timer_period: Neighbor scan timer period + * @roam_scan_offload_enabled: Enable Roam Scan Offload + * @neighbor_scan_timer_period: Neighbor scan timer period * @neighbor_scan_min_timer_period: Min neighbor scan timer period * @neighbor_lookup_rssi_threshold: Neighbor lookup rssi threshold * @opportunistic_scan_threshold_diff: Set oppurtunistic threshold diff @@ -1807,7 +1804,6 @@ struct wlan_mlme_lfr_cfg { uint32_t roam_preauth_no_ack_timeout; uint8_t roam_rssi_diff; uint8_t roam_rssi_diff_6ghz; - uint8_t roam_rssi_delta_6ghz_to_non_6ghz; uint8_t bg_rssi_threshold; bool roam_scan_offload_enabled; uint32_t neighbor_scan_timer_period; diff --git a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/src/wlan_mlme_api.c b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/src/wlan_mlme_api.c index 633b36067c91..dd930d969742 100644 --- a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/src/wlan_mlme_api.c +++ b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/src/wlan_mlme_api.c @@ -3793,16 +3793,14 @@ char *mlme_get_roam_status_str(uint32_t roam_status) char *mlme_get_roam_scan_type_str(uint32_t roam_scan_type) { switch (roam_scan_type) { - case ROAM_STATS_SCAN_TYPE_PARTIAL: + case 0: return "PARTIAL"; - case ROAM_STATS_SCAN_TYPE_FULL: + case 1: return "FULL"; - case ROAM_STATS_SCAN_TYPE_NO_SCAN: + case 2: return "NO SCAN"; - case ROAM_STATS_SCAN_TYPE_HIGHER_BAND_5GHZ_6GHZ: - return "Higher Band: 5 GHz + 6 GHz"; - case ROAM_STATS_SCAN_TYPE_HIGHER_BAND_6GHZ: - return "Higher Band : 6 GHz"; + case 3: + return "Higher Band"; default: return "UNKNOWN"; } diff --git a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.c b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.c index 857e619900a8..1478df85dce7 100644 --- a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.c +++ b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -211,7 +211,7 @@ static QDF_STATUS p2p_check_and_update_channel(struct tx_action_context *tx_ctx) struct p2p_soc_priv_obj *p2p_soc_obj; struct p2p_roc_context *curr_roc_ctx; - if (!tx_ctx || tx_ctx->chan_freq) { + if (!tx_ctx || tx_ctx->chan) { p2p_err("NULL tx ctx or channel valid"); return QDF_STATUS_E_INVAL; } @@ -232,7 +232,7 @@ static QDF_STATUS p2p_check_and_update_channel(struct tx_action_context *tx_ctx) (mode == QDF_P2P_DEVICE_MODE || mode == QDF_P2P_CLIENT_MODE || mode == QDF_P2P_GO_MODE)) - tx_ctx->chan_freq = curr_roc_ctx->chan_freq; + tx_ctx->chan = curr_roc_ctx->chan; wlan_objmgr_vdev_release_ref(vdev, WLAN_P2P_ID); @@ -1068,13 +1068,16 @@ static QDF_STATUS p2p_mgmt_tx(struct tx_action_context *tx_ctx, void *mac_addr; uint8_t pdev_id; struct wlan_objmgr_vdev *vdev; + uint16_t chanfreq = 0; psoc = tx_ctx->p2p_soc_obj->soc; mgmt_param.tx_frame = packet; mgmt_param.frm_len = buf_len; mgmt_param.vdev_id = tx_ctx->vdev_id; mgmt_param.pdata = frame; - mgmt_param.chanfreq = tx_ctx->chan_freq; + if (tx_ctx->chan) + chanfreq = (uint16_t)wlan_chan_to_freq(tx_ctx->chan); + mgmt_param.chanfreq = chanfreq; mgmt_param.qdf_ctx = wlan_psoc_get_qdf_dev(psoc); if (!(mgmt_param.qdf_ctx)) { @@ -1158,7 +1161,7 @@ static QDF_STATUS p2p_roc_req_for_tx_action( p2p_soc_obj = tx_ctx->p2p_soc_obj; roc_ctx->p2p_soc_obj = p2p_soc_obj; roc_ctx->vdev_id = tx_ctx->vdev_id; - roc_ctx->chan_freq = tx_ctx->chan_freq; + roc_ctx->chan = tx_ctx->chan; roc_ctx->duration = tx_ctx->duration; roc_ctx->roc_state = ROC_STATE_IDLE; roc_ctx->roc_type = OFF_CHANNEL_TX; @@ -1801,15 +1804,13 @@ void p2p_dump_tx_queue(struct p2p_soc_priv_obj *p2p_soc_obj) while (QDF_IS_STATUS_SUCCESS(status)) { tx_ctx = qdf_container_of(p_node, struct tx_action_context, node); - p2p_debug("p2p soc object:%pK, tx ctx:%pK, vdev_id:%d, " - "scan_id:%d, roc_cookie:%llx, freq:%d, buf:%pK, " - "len:%d, off_chan:%d, cck:%d, ack:%d, duration:%d", - p2p_soc_obj, tx_ctx, - tx_ctx->vdev_id, tx_ctx->scan_id, - tx_ctx->roc_cookie, tx_ctx->chan_freq, - tx_ctx->buf, tx_ctx->buf_len, - tx_ctx->off_chan, tx_ctx->no_cck, - tx_ctx->no_ack, tx_ctx->duration); + p2p_debug("p2p soc object:%pK, tx ctx:%pK, vdev_id:%d, scan_id:%d, roc_cookie:%llx, chan:%d, buf:%pK, len:%d, off_chan:%d, cck:%d, ack:%d, duration:%d", + p2p_soc_obj, tx_ctx, + tx_ctx->vdev_id, tx_ctx->scan_id, + tx_ctx->roc_cookie, tx_ctx->chan, + tx_ctx->buf, tx_ctx->buf_len, + tx_ctx->off_chan, tx_ctx->no_cck, + tx_ctx->no_ack, tx_ctx->duration); status = qdf_list_peek_next(&p2p_soc_obj->tx_q_roc, p_node, &p_node); @@ -1821,15 +1822,13 @@ void p2p_dump_tx_queue(struct p2p_soc_priv_obj *p2p_soc_obj) while (QDF_IS_STATUS_SUCCESS(status)) { tx_ctx = qdf_container_of(p_node, struct tx_action_context, node); - p2p_debug("p2p soc object:%pK, tx_ctx:%pK, vdev_id:%d, " - "scan_id:%d, roc_cookie:%llx, freq:%d, buf:%pK, " - "len:%d, off_chan:%d, cck:%d, ack:%d, duration:%d", - p2p_soc_obj, tx_ctx, - tx_ctx->vdev_id, tx_ctx->scan_id, - tx_ctx->roc_cookie, tx_ctx->chan_freq, - tx_ctx->buf, tx_ctx->buf_len, - tx_ctx->off_chan, tx_ctx->no_cck, - tx_ctx->no_ack, tx_ctx->duration); + p2p_debug("p2p soc object:%pK, tx_ctx:%pK, vdev_id:%d, scan_id:%d, roc_cookie:%llx, chan:%d, buf:%pK, len:%d, off_chan:%d, cck:%d, ack:%d, duration:%d", + p2p_soc_obj, tx_ctx, + tx_ctx->vdev_id, tx_ctx->scan_id, + tx_ctx->roc_cookie, tx_ctx->chan, + tx_ctx->buf, tx_ctx->buf_len, + tx_ctx->off_chan, tx_ctx->no_cck, + tx_ctx->no_ack, tx_ctx->duration); status = qdf_list_peek_next(&p2p_soc_obj->tx_q_ack, p_node, &p_node); @@ -2919,17 +2918,17 @@ void p2p_rand_mac_tx(struct tx_action_context *tx_action) return; soc = tx_action->p2p_soc_obj->soc; - if (!tx_action->no_ack && tx_action->chan_freq && + if (!tx_action->no_ack && tx_action->chan && tx_action->buf_len > MIN_MAC_HEADER_LEN && p2p_is_vdev_support_rand_mac_by_id(soc, tx_action->vdev_id) && p2p_is_random_mac(soc, tx_action->vdev_id, &tx_action->buf[SRC_MAC_ADDR_OFFSET])) { status = p2p_request_random_mac( - soc, tx_action->vdev_id, - &tx_action->buf[SRC_MAC_ADDR_OFFSET], - tx_action->chan_freq, - tx_action->id, - tx_action->duration); + soc, tx_action->vdev_id, + &tx_action->buf[SRC_MAC_ADDR_OFFSET], + wlan_chan_to_freq(tx_action->chan), + tx_action->id, + tx_action->duration); if (status == QDF_STATUS_SUCCESS) tx_action->rand_mac_tx = true; else @@ -2999,13 +2998,11 @@ QDF_STATUS p2p_process_mgmt_tx(struct tx_action_context *tx_ctx) p2p_soc_obj = tx_ctx->p2p_soc_obj; - p2p_debug("soc:%pK, tx_ctx:%pK, vdev_id:%d, scan_id:%d, " - "roc_cookie:%llx, freq:%d, buf:%pK, len:%d, " - "off_chan:%d, cck:%d, ack:%d, duration:%d", - p2p_soc_obj->soc, tx_ctx, tx_ctx->vdev_id, - tx_ctx->scan_id, tx_ctx->roc_cookie, tx_ctx->chan_freq, - tx_ctx->buf, tx_ctx->buf_len, tx_ctx->off_chan, - tx_ctx->no_cck, tx_ctx->no_ack, tx_ctx->duration); + p2p_debug("soc:%pK, tx_ctx:%pK, vdev_id:%d, scan_id:%d, roc_cookie:%llx, chan:%d, buf:%pK, len:%d, off_chan:%d, cck:%d, ack:%d, duration:%d", + p2p_soc_obj->soc, tx_ctx, tx_ctx->vdev_id, + tx_ctx->scan_id, tx_ctx->roc_cookie, tx_ctx->chan, + tx_ctx->buf, tx_ctx->buf_len, tx_ctx->off_chan, + tx_ctx->no_cck, tx_ctx->no_ack, tx_ctx->duration); status = p2p_get_frame_info(tx_ctx->buf, tx_ctx->buf_len, &(tx_ctx->frame_info)); @@ -3034,8 +3031,8 @@ QDF_STATUS p2p_process_mgmt_tx(struct tx_action_context *tx_ctx) tx_ctx->no_ack = 1; } - if (!tx_ctx->off_chan || !tx_ctx->chan_freq) { - if (!tx_ctx->chan_freq) + if (!tx_ctx->off_chan || !tx_ctx->chan) { + if (!tx_ctx->chan) p2p_check_and_update_channel(tx_ctx); status = p2p_execute_tx_action_frame(tx_ctx); if (status != QDF_STATUS_SUCCESS) { @@ -3047,7 +3044,7 @@ QDF_STATUS p2p_process_mgmt_tx(struct tx_action_context *tx_ctx) /* For off channel tx case */ curr_roc_ctx = p2p_find_current_roc_ctx(p2p_soc_obj); - if (curr_roc_ctx && (curr_roc_ctx->chan_freq == tx_ctx->chan_freq)) { + if (curr_roc_ctx && (curr_roc_ctx->chan == tx_ctx->chan)) { if ((curr_roc_ctx->roc_state == ROC_STATE_REQUESTED) || (curr_roc_ctx->roc_state == ROC_STATE_STARTED)) { tx_ctx->roc_cookie = (uintptr_t)curr_roc_ctx; @@ -3078,8 +3075,7 @@ QDF_STATUS p2p_process_mgmt_tx(struct tx_action_context *tx_ctx) } } - curr_roc_ctx = p2p_find_roc_by_chan_freq(p2p_soc_obj, - tx_ctx->chan_freq); + curr_roc_ctx = p2p_find_roc_by_chan(p2p_soc_obj, tx_ctx->chan); if (curr_roc_ctx && (curr_roc_ctx->roc_state == ROC_STATE_IDLE)) { tx_ctx->roc_cookie = (uintptr_t)curr_roc_ctx; status = qdf_list_insert_back( diff --git a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.h b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.h index 5b98ccbc7066..46e80fca5a33 100644 --- a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.h +++ b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. - * Copyright (c) 2022, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -157,7 +157,7 @@ struct p2p_frame_info { * @scan_id: Scan id given by scan component for this roc req * @roc_cookie: Cookie for remain on channel request * @id: Identifier of this tx context - * @chan_freq: Chan frequency for which this tx has been requested + * @chan: Chan for which this tx has been requested * @buf: tx buffer * @buf_len: Length of tx buffer * @off_chan: Is this off channel tx @@ -174,7 +174,7 @@ struct tx_action_context { int scan_id; uint64_t roc_cookie; int32_t id; - qdf_freq_t chan_freq; + uint8_t chan; uint8_t *buf; int buf_len; bool off_chan; diff --git a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.c b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.c index 643d54a1a428..7146367eae62 100644 --- a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.c +++ b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -114,7 +114,7 @@ static QDF_STATUS p2p_scan_start(struct p2p_roc_context *roc_ctx) req->scan_req.scan_type = SCAN_TYPE_P2P_LISTEN; req->scan_req.scan_req_id = p2p_soc_obj->scan_req_id; req->scan_req.chan_list.num_chan = 1; - req->scan_req.chan_list.chan[0].freq = roc_ctx->chan_freq; + req->scan_req.chan_list.chan[0].freq = wlan_chan_to_freq(roc_ctx->chan); req->scan_req.dwell_time_passive = roc_ctx->duration; req->scan_req.dwell_time_active = 0; req->scan_req.scan_priority = SCAN_PRIORITY_HIGH; @@ -278,7 +278,7 @@ static QDF_STATUS p2p_send_roc_event( p2p_evt.vdev_id = roc_ctx->vdev_id; p2p_evt.roc_event = evt; p2p_evt.cookie = (uint64_t)roc_ctx->id; - p2p_evt.chan_freq = roc_ctx->chan_freq; + p2p_evt.chan = roc_ctx->chan; p2p_evt.duration = roc_ctx->duration; p2p_debug("roc_event: %d, cookie:%llx", p2p_evt.roc_event, @@ -305,10 +305,9 @@ static QDF_STATUS p2p_destroy_roc_ctx(struct p2p_roc_context *roc_ctx, QDF_STATUS status = QDF_STATUS_SUCCESS; struct p2p_soc_priv_obj *p2p_soc_obj = roc_ctx->p2p_soc_obj; - p2p_debug("p2p_soc_obj:%pK, roc_ctx:%pK, up_layer_event:%d," - " in_roc_queue:%d vdev_id:%d freq:%d duration:%d", - p2p_soc_obj, roc_ctx, up_layer_event, in_roc_queue, - roc_ctx->vdev_id, roc_ctx->chan_freq, roc_ctx->duration); + p2p_debug("p2p_soc_obj:%pK, roc_ctx:%pK, up_layer_event:%d, in_roc_queue:%d vdev_id:%d chan:%d duration:%d", + p2p_soc_obj, roc_ctx, up_layer_event, in_roc_queue, + roc_ctx->vdev_id, roc_ctx->chan, roc_ctx->duration); if (up_layer_event) { if (roc_ctx->roc_state < ROC_STATE_ON_CHAN) @@ -392,13 +391,11 @@ static void p2p_roc_timeout(void *pdata) return; } - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d," - " tx ctx:%pK, freq:%d, phy_mode:%d, duration:%d," - " roc_type:%d, roc_state:%d", - roc_ctx->p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, - roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan_freq, - roc_ctx->phy_mode, roc_ctx->duration, - roc_ctx->roc_type, roc_ctx->roc_state); + p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", + roc_ctx->p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, + roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan, + roc_ctx->phy_mode, roc_ctx->duration, + roc_ctx->roc_type, roc_ctx->roc_state); if (roc_ctx->roc_state == ROC_STATE_CANCEL_IN_PROG) { p2p_err("Cancellation already in progress"); @@ -421,13 +418,11 @@ static QDF_STATUS p2p_execute_roc_req(struct p2p_roc_context *roc_ctx) QDF_STATUS status; struct p2p_soc_priv_obj *p2p_soc_obj = roc_ctx->p2p_soc_obj; - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d," - " tx ctx:%pK, freq:%d, phy_mode:%d, duration:%d," - " roc_type:%d, roc_state:%d", - p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, - roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan_freq, - roc_ctx->phy_mode, roc_ctx->duration, - roc_ctx->roc_type, roc_ctx->roc_state); + p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", + p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, + roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan, + roc_ctx->phy_mode, roc_ctx->duration, + roc_ctx->roc_type, roc_ctx->roc_state); /* prevent runtime suspend */ qdf_runtime_pm_prevent_suspend(&p2p_soc_obj->roc_runtime_lock); @@ -650,14 +645,14 @@ struct p2p_roc_context *p2p_find_current_roc_ctx( struct p2p_roc_context, node); if (roc_ctx->roc_state != ROC_STATE_IDLE) { p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id" - ":%d, scan_id:%d, tx ctx:%pK, freq:" - "%d, phy_mode:%d, duration:%d, " - "roc_type:%d, roc_state:%d", - roc_ctx->p2p_soc_obj, roc_ctx, - roc_ctx->vdev_id, roc_ctx->scan_id, - roc_ctx->tx_ctx, roc_ctx->chan_freq, - roc_ctx->phy_mode, roc_ctx->duration, - roc_ctx->roc_type, roc_ctx->roc_state); + ":%d, scan_id:%d, tx ctx:%pK, chan:" + "%d, phy_mode:%d, duration:%d, " + "roc_type:%d, roc_state:%d", + roc_ctx->p2p_soc_obj, roc_ctx, + roc_ctx->vdev_id, roc_ctx->scan_id, + roc_ctx->tx_ctx, roc_ctx->chan, + roc_ctx->phy_mode, roc_ctx->duration, + roc_ctx->roc_type, roc_ctx->roc_state); return roc_ctx; } @@ -690,8 +685,8 @@ struct p2p_roc_context *p2p_find_roc_by_tx_ctx( return NULL; } -struct p2p_roc_context *p2p_find_roc_by_chan_freq( - struct p2p_soc_priv_obj *p2p_soc_obj, qdf_freq_t chan_freq) +struct p2p_roc_context *p2p_find_roc_by_chan( + struct p2p_soc_priv_obj *p2p_soc_obj, uint8_t chan) { struct p2p_roc_context *roc_ctx; qdf_list_node_t *p_node; @@ -702,14 +697,11 @@ struct p2p_roc_context *p2p_find_roc_by_chan_freq( roc_ctx = qdf_container_of(p_node, struct p2p_roc_context, node); - if (roc_ctx->chan_freq == chan_freq) { - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d," - " scan_id:%d, tx ctx:%pK, freq:%d," - " phy_mode:%d, duration:%d," - " roc_type:%d, roc_state:%d", + if (roc_ctx->chan == chan) { + p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", roc_ctx->p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, roc_ctx->scan_id, - roc_ctx->tx_ctx, roc_ctx->chan_freq, + roc_ctx->tx_ctx, roc_ctx->chan, roc_ctx->phy_mode, roc_ctx->duration, roc_ctx->roc_type, roc_ctx->roc_state); @@ -816,12 +808,10 @@ QDF_STATUS p2p_process_cleanup_roc_queue( roc_ctx = qdf_container_of(p_node, struct p2p_roc_context, node); - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, " - "scan_id:%d, tx ctx:%pK, freq:%d, phy_mode:%d, " - "duration:%d, roc_type:%d, roc_state:%d", + p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", roc_ctx->p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, roc_ctx->scan_id, - roc_ctx->tx_ctx, roc_ctx->chan_freq, + roc_ctx->tx_ctx, roc_ctx->chan, roc_ctx->phy_mode, roc_ctx->duration, roc_ctx->roc_type, roc_ctx->roc_state); status = qdf_list_peek_next(&p2p_soc_obj->roc_q, @@ -846,11 +836,9 @@ QDF_STATUS p2p_process_cleanup_roc_queue( roc_ctx = qdf_container_of(p_node, struct p2p_roc_context, node); - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, " - "scan_id:%d, tx ctx:%pK, freq:%d, phy_mode:%d, " - "duration:%d, roc_type:%d, roc_state:%d", + p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", roc_ctx->p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, - roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan_freq, + roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan, roc_ctx->phy_mode, roc_ctx->duration, roc_ctx->roc_type, roc_ctx->roc_state); @@ -883,13 +871,11 @@ QDF_STATUS p2p_process_roc_req(struct p2p_roc_context *roc_ctx) p2p_soc_obj = roc_ctx->p2p_soc_obj; - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, " - "tx_ctx:%pK, freq:%d, phy_mode:%d, duration:%d, " - "roc_type:%d, roc_state:%d", - p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, - roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan_freq, - roc_ctx->phy_mode, roc_ctx->duration, - roc_ctx->roc_type, roc_ctx->roc_state); + p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx_ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", + p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, + roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan, + roc_ctx->phy_mode, roc_ctx->duration, + roc_ctx->roc_type, roc_ctx->roc_state); status = qdf_list_insert_back(&p2p_soc_obj->roc_q, &roc_ctx->node); diff --git a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.h b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.h index b800b20174b4..143e01726a8f 100644 --- a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.h +++ b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -81,7 +81,7 @@ enum roc_state { * @vdev_id: Vdev id on which this request has come * @scan_id: Scan id given by scan component for this roc req * @tx_ctx: TX context if this ROC is for tx MGMT - * @chan_freq: Chan frequency for which this RoC has been requested + * @chan: Chan for which this RoC has been requested * @phy_mode: PHY mode * @duration: Duration for the RoC * @roc_type: RoC type User requested or internal @@ -95,7 +95,7 @@ struct p2p_roc_context { uint32_t vdev_id; uint32_t scan_id; void *tx_ctx; - qdf_freq_t chan_freq; + uint8_t chan; uint8_t phy_mode; uint32_t duration; enum roc_type roc_type; @@ -165,9 +165,9 @@ struct p2p_roc_context *p2p_find_roc_by_tx_ctx( struct p2p_soc_priv_obj *p2p_soc_obj, uint64_t cookie); /** - * p2p_find_roc_by_chan_freq() - Find out roc context by channel + * p2p_find_roc_by_chan() - Find out roc context by channel * @p2p_soc_obj: p2p psoc private object - * @chan_freq: channel frequency of the ROC + * @chan: channel of the ROC * * This function finds out roc context by channel from p2p psoc * private object @@ -175,8 +175,8 @@ struct p2p_roc_context *p2p_find_roc_by_tx_ctx( * Return: Pointer to roc context - success * NULL - failure */ -struct p2p_roc_context *p2p_find_roc_by_chan_freq( - struct p2p_soc_priv_obj *p2p_soc_obj, qdf_freq_t chan_freq); +struct p2p_roc_context *p2p_find_roc_by_chan( + struct p2p_soc_priv_obj *p2p_soc_obj, uint8_t chan); /** * p2p_restart_roc_timer() - Restarts roc timer diff --git a/drivers/staging/qcacld-3.0/components/p2p/dispatcher/inc/wlan_p2p_public_struct.h b/drivers/staging/qcacld-3.0/components/p2p/dispatcher/inc/wlan_p2p_public_struct.h index 060f0df3ba8b..33fd71c70b40 100644 --- a/drivers/staging/qcacld-3.0/components/p2p/dispatcher/inc/wlan_p2p_public_struct.h +++ b/drivers/staging/qcacld-3.0/components/p2p/dispatcher/inc/wlan_p2p_public_struct.h @@ -1,6 +1,5 @@ /* * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. - * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -62,13 +61,13 @@ struct p2p_ps_params { /** * struct p2p_roc_req - P2P roc request * @vdev_id: Vdev id on which this request has come - * @chan_freq: Chan frequency for which this RoC has been requested + * @chan: Chan for which this RoC has been requested * @phy_mode: PHY mode * @duration: Duration for the RoC */ struct p2p_roc_req { uint32_t vdev_id; - qdf_freq_t chan_freq; + uint32_t chan; uint32_t phy_mode; uint32_t duration; }; @@ -90,14 +89,14 @@ enum p2p_roc_event { * @vdev_id: Vdev id * @roc_event: RoC event * @cookie: Cookie which is given to supplicant for this roc req - * @chan_freq: Chan frequency for which this RoC has been requested + * @chan: Chan for which this RoC has been requested * @duration: Duration for the RoC */ struct p2p_event { uint32_t vdev_id; enum p2p_roc_event roc_event; uint64_t cookie; - qdf_freq_t chan_freq; + uint32_t chan; uint32_t duration; }; @@ -138,7 +137,7 @@ struct p2p_tx_cnf { /** * struct p2p_mgmt_tx - p2p mgmt tx structure * @vdev_id: Vdev id - * @chan_freq: Chan frequency for which this RoC has been requested + * @chan: Chan for which this RoC has been requested * @wait: Duration for the RoC * @len: Length of tx buffer * @no_cck: Required cck or not @@ -148,7 +147,7 @@ struct p2p_tx_cnf { */ struct p2p_mgmt_tx { uint32_t vdev_id; - qdf_freq_t chan_freq; + uint32_t chan; uint32_t wait; uint32_t len; uint32_t no_cck; diff --git a/drivers/staging/qcacld-3.0/components/p2p/dispatcher/src/wlan_p2p_ucfg_api.c b/drivers/staging/qcacld-3.0/components/p2p/dispatcher/src/wlan_p2p_ucfg_api.c index 3b862f62d3de..50444dc6d8e4 100644 --- a/drivers/staging/qcacld-3.0/components/p2p/dispatcher/src/wlan_p2p_ucfg_api.c +++ b/drivers/staging/qcacld-3.0/components/p2p/dispatcher/src/wlan_p2p_ucfg_api.c @@ -1,6 +1,5 @@ /* * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -119,9 +118,9 @@ QDF_STATUS ucfg_p2p_roc_req(struct wlan_objmgr_psoc *soc, QDF_STATUS status; int32_t id; - p2p_debug("soc:%pK, vdev_id:%d, chanfreq:%d, phy_mode:%d, duration:%d", - soc, roc_req->vdev_id, roc_req->chan_freq, - roc_req->phy_mode, roc_req->duration); + p2p_debug("soc:%pK, vdev_id:%d, chan:%d, phy_mode:%d, duration:%d", + soc, roc_req->vdev_id, roc_req->chan, + roc_req->phy_mode, roc_req->duration); if (!soc) { p2p_err("psoc context passed is NULL"); @@ -149,7 +148,7 @@ QDF_STATUS ucfg_p2p_roc_req(struct wlan_objmgr_psoc *soc, *cookie = (uint64_t)id; roc_ctx->p2p_soc_obj = p2p_soc_obj; roc_ctx->vdev_id = roc_req->vdev_id; - roc_ctx->chan_freq = roc_req->chan_freq; + roc_ctx->chan = roc_req->chan; roc_ctx->phy_mode = roc_req->phy_mode; roc_ctx->duration = roc_req->duration; roc_ctx->roc_state = ROC_STATE_IDLE; @@ -325,11 +324,10 @@ QDF_STATUS ucfg_p2p_mgmt_tx(struct wlan_objmgr_psoc *soc, QDF_STATUS status; int32_t id; - p2p_debug("soc:%pK, vdev_id:%d, freq:%d, wait:%d, buf_len:%d," - " cck:%d, no ack:%d, off chan:%d", - soc, mgmt_frm->vdev_id, mgmt_frm->chan_freq, - mgmt_frm->wait, mgmt_frm->len, mgmt_frm->no_cck, - mgmt_frm->dont_wait_for_ack, mgmt_frm->off_chan); + p2p_debug("soc:%pK, vdev_id:%d, chan:%d, wait:%d, buf_len:%d, cck:%d, no ack:%d, off chan:%d", + soc, mgmt_frm->vdev_id, mgmt_frm->chan, + mgmt_frm->wait, mgmt_frm->len, mgmt_frm->no_cck, + mgmt_frm->dont_wait_for_ack, mgmt_frm->off_chan); if (!soc) { p2p_err("psoc context passed is NULL"); @@ -363,7 +361,7 @@ QDF_STATUS ucfg_p2p_mgmt_tx(struct wlan_objmgr_psoc *soc, *cookie = (uint64_t)id; tx_action->p2p_soc_obj = p2p_soc_obj; tx_action->vdev_id = mgmt_frm->vdev_id; - tx_action->chan_freq = mgmt_frm->chan_freq; + tx_action->chan = mgmt_frm->chan; tx_action->duration = mgmt_frm->wait; tx_action->buf_len = mgmt_frm->len; tx_action->no_cck = mgmt_frm->no_cck; diff --git a/drivers/staging/qcacld-3.0/components/target_if/connection_mgr/src/target_if_cm_roam_offload.c b/drivers/staging/qcacld-3.0/components/target_if/connection_mgr/src/target_if_cm_roam_offload.c index 970d0429f1b7..46e1cab26484 100644 --- a/drivers/staging/qcacld-3.0/components/target_if/connection_mgr/src/target_if_cm_roam_offload.c +++ b/drivers/staging/qcacld-3.0/components/target_if/connection_mgr/src/target_if_cm_roam_offload.c @@ -1,7 +1,6 @@ /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -265,41 +264,6 @@ target_if_cm_roam_rssi_diff_6ghz(struct wlan_objmgr_vdev *vdev, return status; } -/** - * target_if_cm_roam_rssi_delta_6ghz_to_non_6ghz() - Sends the roam RSSI - * diff value to the FW. This value is used to determine how much better - * the RSSI of the new/roamable non-6 GHz AP must be for roaming. - * - * @vdev: vdev object - * @roam_rssi_delta_6ghz_to_non_6ghz: RSSI diff value to be used for roaming to - * Non 6 GHz AP - * - * Return: QDF_STATUS - */ -static QDF_STATUS -target_if_cm_roam_rssi_delta_6ghz_to_non_6ghz(struct wlan_objmgr_vdev *vdev, - uint8_t roam_rssi_delta_6ghz_to_non_6ghz) -{ - QDF_STATUS status = QDF_STATUS_E_FAILURE; - uint8_t vdev_id; - wmi_unified_t wmi_handle; - - wmi_handle = target_if_cm_roam_get_wmi_handle_from_vdev(vdev); - if (!wmi_handle) - return status; - - vdev_id = wlan_vdev_get_id(vdev); - status = target_if_roam_set_param( - wmi_handle, vdev_id, - WMI_ROAM_PARAM_ROAM_RSSI_PENALTY_FOR_NON_6GHZ_CAND_AP, - roam_rssi_delta_6ghz_to_non_6ghz); - - if (QDF_IS_STATUS_ERROR(status)) - target_if_err("Failed to set WMI_ROAM_PARAM_ROAM_RSSI_PENALTY_FOR_NON_6GHZ_CAND_AP"); - - return status; -} - static QDF_STATUS target_if_cm_roam_scan_offload_rssi_thresh( wmi_unified_t wmi_handle, @@ -403,13 +367,6 @@ target_if_cm_roam_rssi_diff_6ghz(struct wlan_objmgr_vdev *vdev, return QDF_STATUS_E_NOSUPPORT; } -static QDF_STATUS -target_if_cm_roam_rssi_delta_6ghz_to_non_6ghz(struct wlan_objmgr_vdev *vdev, - uint8_t roam_rssi_diff_6ghz) -{ - return QDF_STATUS_E_NOSUPPORT; -} - static inline void target_if_check_hi_rssi_5ghz_support( wmi_unified_t wmi_handle, @@ -1319,9 +1276,6 @@ target_if_cm_roam_send_start(struct wlan_objmgr_vdev *vdev, if (req->wlan_roam_rssi_diff_6ghz) target_if_cm_roam_rssi_diff_6ghz(vdev, req->wlan_roam_rssi_diff_6ghz); - if (req->wlan_roam_rssi_delta_6ghz_to_non_6ghz) - target_if_cm_roam_rssi_delta_6ghz_to_non_6ghz( - vdev, req->wlan_roam_rssi_delta_6ghz_to_non_6ghz); /* add other wmi commands */ end: @@ -1562,10 +1516,6 @@ target_if_cm_roam_send_update_config(struct wlan_objmgr_vdev *vdev, if (req->wlan_roam_rssi_diff_6ghz) target_if_cm_roam_rssi_diff_6ghz( vdev, req->wlan_roam_rssi_diff_6ghz); - - if (req->wlan_roam_rssi_delta_6ghz_to_non_6ghz) - target_if_cm_roam_rssi_delta_6ghz_to_non_6ghz( - vdev, req->wlan_roam_rssi_delta_6ghz_to_non_6ghz); } end: return status; diff --git a/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/core/src/wlan_cm_roam_offload.c b/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/core/src/wlan_cm_roam_offload.c index 8f5e5272d77c..647f5e0229b2 100644 --- a/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/core/src/wlan_cm_roam_offload.c +++ b/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/core/src/wlan_cm_roam_offload.c @@ -629,10 +629,6 @@ cm_roam_start_req(struct wlan_objmgr_psoc *psoc, uint8_t vdev_id, wlan_cm_roam_cfg_get_value(psoc, vdev_id, ROAM_RSSI_DIFF_6GHZ, &temp); start_req->wlan_roam_rssi_diff_6ghz = temp.uint_value; - wlan_cm_roam_cfg_get_value(psoc, vdev_id, - ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ, &temp); - start_req->wlan_roam_rssi_delta_6ghz_to_non_6ghz = temp.uint_value; - status = wlan_cm_tgt_send_roam_start_req(psoc, vdev_id, start_req); if (QDF_IS_STATUS_ERROR(status)) mlme_debug("fail to send roam start"); @@ -695,10 +691,6 @@ cm_roam_update_config_req(struct wlan_objmgr_psoc *psoc, uint8_t vdev_id, wlan_cm_roam_cfg_get_value(psoc, vdev_id, ROAM_RSSI_DIFF_6GHZ, &temp); update_req->wlan_roam_rssi_diff_6ghz = temp.uint_value; - wlan_cm_roam_cfg_get_value(psoc, vdev_id, - ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ, &temp); - update_req->wlan_roam_rssi_delta_6ghz_to_non_6ghz = temp.uint_value; - status = wlan_cm_tgt_send_roam_update_req(psoc, vdev_id, update_req); if (QDF_IS_STATUS_ERROR(status)) mlme_debug("fail to send update config"); diff --git a/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/inc/wlan_cm_roam_public_struct.h b/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/inc/wlan_cm_roam_public_struct.h index b4d17e9c04fe..9a027bc6a11f 100644 --- a/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/inc/wlan_cm_roam_public_struct.h +++ b/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/inc/wlan_cm_roam_public_struct.h @@ -1,7 +1,6 @@ /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -121,14 +120,12 @@ * @BEACON_RSSI_WEIGHT: Beacon Rssi weight parameter * @HI_RSSI_DELAY_BTW_SCANS: High Rssi delay between scans * @ROAM_RSSI_DIFF_6GHZ: roam rssi diff for 6 GHz AP - * @ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ: roam rssi diff for Non 6 GHz AP */ enum roam_cfg_param { RSSI_CHANGE_THRESHOLD, BEACON_RSSI_WEIGHT, HI_RSSI_DELAY_BTW_SCANS, ROAM_RSSI_DIFF_6GHZ, - ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ, }; /** @@ -1209,8 +1206,6 @@ enum roam_rt_stats_params { * scan only on prior discovery of any 6 GHz support in the environment. * @wlan_roam_rssi_diff_6ghz: This value is used as to how better the RSSI of * the new/roamable 6GHz AP should be for roaming. - * @wlan_roam_rssi_delta_6ghz_to_non_6ghz: This value is used as to how better - * the RSSI of the new/roamable non 6GHz AP should be for roaming. */ struct wlan_roam_start_config { struct wlan_roam_offload_scan_rssi_params rssi_params; @@ -1234,7 +1229,6 @@ struct wlan_roam_start_config { uint8_t wlan_exclude_rm_partial_scan_freq; uint8_t wlan_roam_full_scan_6ghz_on_disc; uint8_t wlan_roam_rssi_diff_6ghz; - uint8_t wlan_roam_rssi_delta_6ghz_to_non_6ghz; /* other wmi cmd structures */ }; @@ -1287,8 +1281,6 @@ struct wlan_roam_stop_config { * scan only on prior discovery of any 6 GHz support in the environment. * @wlan_roam_rssi_diff_6ghz: This value is used as to how better the RSSI of * the new/roamable 6GHz AP should be for roaming. - * @wlan_roam_rssi_delta_6ghz_to_non_6ghz: This value is used as to how better - * the RSSI of the new/roamable non 6GHz AP should be for roaming. */ struct wlan_roam_update_config { struct wlan_roam_beacon_miss_cnt beacon_miss_cnt; @@ -1307,7 +1299,6 @@ struct wlan_roam_update_config { uint8_t wlan_exclude_rm_partial_scan_freq; uint8_t wlan_roam_full_scan_6ghz_on_disc; uint8_t wlan_roam_rssi_diff_6ghz; - uint8_t wlan_roam_rssi_delta_6ghz_to_non_6ghz; }; #if defined(WLAN_FEATURE_HOST_ROAM) || defined(WLAN_FEATURE_ROAM_OFFLOAD) @@ -1531,8 +1522,6 @@ enum roam_fail_params { * @roam_invoke_fail_reason: One of reason id from enum * wmi_roam_invoke_status_error in case of forced roam * @roam_rssi_diff_6ghz: roam rssi diff for 6 GHz AP - * @roam_rssi_delta_6ghz_to_non_6ghz: RSSI Delta value to be used for roaming - * from 6 GHz to Non 6GHz AP. */ struct wlan_cm_rso_configs { uint8_t rescan_rssi_delta; @@ -1543,7 +1532,6 @@ struct wlan_cm_rso_configs { uint32_t roam_trigger_reason; uint32_t roam_invoke_fail_reason; uint8_t roam_rssi_diff_6ghz; - uint8_t roam_rssi_delta_6ghz_to_non_6ghz; }; /** diff --git a/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/src/wlan_cm_roam_api.c b/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/src/wlan_cm_roam_api.c index 8ad4cef25e38..53fce94e29c3 100644 --- a/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/src/wlan_cm_roam_api.c +++ b/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/src/wlan_cm_roam_api.c @@ -1,7 +1,6 @@ /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -520,10 +519,6 @@ QDF_STATUS wlan_cm_roam_cfg_get_value(struct wlan_objmgr_psoc *psoc, case ROAM_RSSI_DIFF_6GHZ: dst_config->uint_value = src_config->roam_rssi_diff_6ghz; break; - case ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ: - dst_config->uint_value = - src_config->roam_rssi_delta_6ghz_to_non_6ghz; - break; default: mlme_err("Invalid roam config requested:%d", roam_cfg_type); status = QDF_STATUS_E_FAILURE; @@ -573,10 +568,6 @@ wlan_cm_roam_cfg_set_value(struct wlan_objmgr_psoc *psoc, uint8_t vdev_id, case ROAM_RSSI_DIFF_6GHZ: dst_config->roam_rssi_diff_6ghz = src_config->uint_value; break; - case ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ: - dst_config->roam_rssi_delta_6ghz_to_non_6ghz = - src_config->uint_value; - break; default: mlme_err("Invalid roam config requested:%d", roam_cfg_type); status = QDF_STATUS_E_FAILURE; diff --git a/drivers/staging/qcacld-3.0/core/dp/htt/htt_h2t.c b/drivers/staging/qcacld-3.0/core/dp/htt/htt_h2t.c index 3038b831a3e5..e1bed656e5ec 100644 --- a/drivers/staging/qcacld-3.0/core/dp/htt/htt_h2t.c +++ b/drivers/staging/qcacld-3.0/core/dp/htt/htt_h2t.c @@ -629,7 +629,7 @@ htt_h2t_rx_ring_cfg_msg_hl(struct htt_pdev_t *pdev) pkt = htt_htc_pkt_alloc(pdev); if (!pkt) - return QDF_STATUS_E_FAILURE; /* failure */ + return A_ERROR; /* failure */ /* * show that this is not a tx frame download @@ -645,7 +645,7 @@ htt_h2t_rx_ring_cfg_msg_hl(struct htt_pdev_t *pdev) HTC_HEADER_LEN + HTC_HDR_ALIGNMENT_PADDING, 4, true); if (!msg) { htt_htc_pkt_free(pdev, pkt); - return QDF_STATUS_E_FAILURE; /* failure */ + return A_ERROR; /* failure */ } /* * Set the length of the message. diff --git a/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_fisa_rx.c b/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_fisa_rx.c index 835f795e7736..d0d84e40a9ce 100644 --- a/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_fisa_rx.c +++ b/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_fisa_rx.c @@ -1677,33 +1677,15 @@ static int dp_add_nbuf_to_fisa_flow(struct dp_rx_fst *fisa_hdl, fse_metadata = hal_rx_msdu_fse_metadata_get(hal_soc_hdl, rx_tlv_hdr); cce_match = hal_rx_msdu_cce_match_get(rx_tlv_hdr); - /* - * For two cases the fse_metadata will not match the metadata - * from the fisa_flow_table entry - * 1) Flow has been evicted (lru deletion), and this packet is - * one of the few packets pending in the rx ring from the prev - * flow - * 2) HW flow table match fails for some packets in the - * currently active flow. - */ - if (cce_match) { + if (cce_match || (fisa_hdl->del_flow_count && + fse_metadata != fisa_flow->metadata)) { dp_rx_fisa_release_ft_lock(fisa_hdl, napi_id); - DP_STATS_INC(fisa_hdl, reo_mismatch.allow_cce_match, - 1); - return FISA_AGGR_NOT_ELIGIBLE; - } - - if (fse_metadata != fisa_flow->metadata) { - dp_rx_fisa_release_ft_lock(fisa_hdl, napi_id); - DP_STATS_INC(fisa_hdl, - reo_mismatch.allow_fse_metdata_mismatch, - 1); return FISA_AGGR_NOT_ELIGIBLE; } dp_err("REO id mismatch flow: %pK napi_id: %u nbuf: %pK reo_id: %u", fisa_flow, fisa_flow->napi_id, nbuf, napi_id); - DP_STATS_INC(fisa_hdl, reo_mismatch.allow_non_aggr, 1); + DP_STATS_INC(fisa_hdl, reo_mismatch, 1); QDF_BUG(0); dp_rx_fisa_release_ft_lock(fisa_hdl, napi_id); return FISA_AGGR_NOT_ELIGIBLE; diff --git a/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_rx_fst.c b/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_rx_fst.c index 4d88045dedf1..023729a53bf1 100644 --- a/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_rx_fst.c +++ b/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_rx_fst.c @@ -63,24 +63,6 @@ void dp_rx_dump_fisa_table(struct dp_soc *soc) } } -void dp_print_fisa_stats(struct dp_soc *soc) -{ - struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx; - struct dp_rx_fst *fst = soc->rx_fst; - - /* Check if it is enabled in the INI */ - if (!wlan_cfg_is_rx_fisa_enabled(cfg)) - return; - - dp_info("invalid flow index: %u", fst->stats.invalid_flow_index); - dp_info("reo_mismatch: cce_match: %u", - fst->stats.reo_mismatch.allow_cce_match); - dp_info("reo_mismatch: allow_fse_metdata_mismatch: %u", - fst->stats.reo_mismatch.allow_fse_metdata_mismatch); - dp_info("reo_mismatch: allow_non_aggr: %u", - fst->stats.reo_mismatch.allow_non_aggr); -} - /** * dp_rx_flow_send_htt_operation_cmd() - Invalidate FSE cache on FT change * @pdev: handle to DP pdev diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c index 8166bd994710..5ffa66dabe3d 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c @@ -1718,7 +1718,7 @@ static const struct nl80211_vendor_cmd_info wlan_hdd_cfg80211_vendor_events[] = }; /** - * __is_driver_dfs_capable() - get driver DFS offload capability + * __is_driver_dfs_capable() - get driver DFS capability * @wiphy: pointer to wireless wiphy structure. * @wdev: pointer to wireless_dev structure. * @data: Pointer to the data to be passed via vendor interface @@ -17744,7 +17744,7 @@ void wlan_hdd_update_wiphy(struct hdd_context *hdd_ctx) { int value; bool fils_enabled, mac_spoofing_enabled; - bool is_oce_sta_enabled = false; + bool dfs_master_capable = true, is_oce_sta_enabled = false; QDF_STATUS status; struct wiphy *wiphy = hdd_ctx->wiphy; uint8_t allow_mcc_go_diff_bi = 0, enable_mcc = 0; @@ -17769,7 +17769,11 @@ void wlan_hdd_update_wiphy(struct hdd_context *hdd_ctx) if (fils_enabled) wlan_hdd_cfg80211_set_wiphy_fils_feature(wiphy); - wlan_hdd_cfg80211_set_dfs_offload_feature(wiphy); + status = ucfg_mlme_get_dfs_master_capability(hdd_ctx->psoc, + &dfs_master_capable); + if (QDF_IS_STATUS_SUCCESS(status) && dfs_master_capable) + wlan_hdd_cfg80211_set_dfs_offload_feature(wiphy); + status = ucfg_mlme_get_bigtk_support(hdd_ctx->psoc, &is_bigtk_supported); diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.c index 76a1a5228125..80659541d94a 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.c @@ -5244,7 +5244,6 @@ int wlan_hdd_cfg80211_start_bss(struct hdd_adapter *adapter, bool deliver_start_evt = true; struct s_ext_cap *p_ext_cap; enum reg_phymode reg_phy_mode, updated_phy_mode; - bool dfs_master_capable; hdd_enter(); @@ -5788,24 +5787,6 @@ int wlan_hdd_cfg80211_start_bss(struct hdd_adapter *adapter, config->ch_width_orig = CH_WIDTH_20MHZ; } - status = ucfg_mlme_get_dfs_master_capability(hdd_ctx->psoc, - &dfs_master_capable); - if (QDF_IS_STATUS_ERROR(status)) { - hdd_err("Failed to get dfs master capable"); - ret = -EINVAL; - goto error; - } - - if (!dfs_master_capable && - policy_mgr_is_bonded_chan_dfs(hdd_ctx->psoc, - config->ch_width_orig, - config->ch_params.mhz_freq_seg1, - config->chan_freq)) { - hdd_err("Failed to bringup SAP; Atleast one bonded channel is DFS"); - ret = -EINVAL; - goto error; - } - if (wlan_hdd_setup_driver_overrides(adapter)) { ret = -EINVAL; goto error; diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_p2p.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_p2p.c index d8aee3c9ee21..4743ce81ba2a 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_p2p.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_p2p.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -286,16 +286,15 @@ wlan_hdd_validate_and_override_offchan(struct hdd_adapter *adapter, struct ieee80211_channel *chan, bool *offchan) { - qdf_freq_t home_ch_freq; + uint8_t home_ch; if (!offchan || !chan || !(*offchan)) return; - home_ch_freq = hdd_get_adapter_home_channel(adapter); + home_ch = hdd_get_adapter_home_channel(adapter); - if (chan->center_freq == home_ch_freq) { - hdd_debug("override offchan to 0 at home channel %d", - home_ch_freq); + if (ieee80211_frequency_to_channel(chan->center_freq) == home_ch) { + hdd_debug("override offchan to 0 at home channel %d", home_ch); *offchan = false; } } diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_stats.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_stats.c index 67f104883d23..82e357d2e799 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_stats.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_stats.c @@ -3917,8 +3917,7 @@ hdd_get_roam_rt_stats_event_len(struct mlme_roam_debug_info *roam_stats) len += nla_total_size(sizeof(uint8_t)); if (roam_stats->scan.present) { - if (roam_stats->scan.num_chan && - roam_stats->scan.type == ROAM_STATS_SCAN_TYPE_PARTIAL) + if (roam_stats->scan.num_chan && !roam_stats->scan.type) for (i = 0; i < roam_stats->scan.num_chan;) i++; @@ -3991,8 +3990,7 @@ roam_rt_stats_fill_scan_freq(struct sk_buff *vendor_event, kfree_skb(vendor_event); return; } - if (roam_stats->scan.num_chan && - roam_stats->scan.type == ROAM_STATS_SCAN_TYPE_PARTIAL) { + if (roam_stats->scan.num_chan && !roam_stats->scan.type) { for (i = 0; i < roam_stats->scan.num_chan; i++) { if (nla_put_u32(vendor_event, i, roam_stats->scan.chan_freq[i])) { diff --git a/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h b/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h index 500f1f71f75c..c8f76c9a8572 100644 --- a/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h +++ b/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h @@ -32,9 +32,9 @@ #define QWLAN_VERSION_MAJOR 2 #define QWLAN_VERSION_MINOR 0 #define QWLAN_VERSION_PATCH 8 -#define QWLAN_VERSION_EXTRA "G" -#define QWLAN_VERSION_BUILD 35 +#define QWLAN_VERSION_EXTRA "Z" +#define QWLAN_VERSION_BUILD 34 -#define QWLAN_VERSIONSTR "2.0.8.35G" +#define QWLAN_VERSIONSTR "2.0.8.34Z" #endif /* QWLAN_VERSION_H */ diff --git a/drivers/staging/qcacld-3.0/core/mac/inc/sir_api.h b/drivers/staging/qcacld-3.0/core/mac/inc/sir_api.h index d520ba3f3525..3bdcdf7f390a 100644 --- a/drivers/staging/qcacld-3.0/core/mac/inc/sir_api.h +++ b/drivers/staging/qcacld-3.0/core/mac/inc/sir_api.h @@ -786,7 +786,6 @@ struct bss_description { #if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) uint32_t is_single_pmk; #endif - uint16_t neg_rsn_caps; /* Please keep the structure 4 bytes aligned above the ieFields */ uint32_t ieFields[1]; }; diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_session.h b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_session.h index 25f2f90143c5..5488a180a145 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_session.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_session.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -140,7 +140,6 @@ struct obss_detection_cfg { * @prev_auth_seq_num: Sequence number of previously received auth frame to * detect duplicate frames. * @prev_auth_mac_addr: mac_addr of the sta correspond to @prev_auth_seq_num - * @cal_tpc_post_csa: Recalculate tx power power csa */ struct pe_session { /* To check session table is in use or free */ @@ -581,7 +580,6 @@ struct pe_session { uint32_t dfs_regdomain; uint8_t ap_defined_power_type_6g; uint8_t best_6g_power_type; - bool cal_tpc_post_csa; }; /*------------------------------------------------------------------------- diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_api.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_api.c index 2e0f0511dc89..80ee8867c140 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_api.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_api.c @@ -2631,10 +2631,6 @@ pe_roam_synch_callback(struct mac_context *mac_ctx, lim_fill_ft_session(mac_ctx, bss_desc, ft_session_ptr, session_ptr, roam_sync_ind_ptr->phy_mode); pe_update_crypto_params(mac_ctx, ft_session_ptr, roam_sync_ind_ptr); - - /* Reset the SPMK global cache */ - wlan_mlme_set_sae_single_pmk_bss_cap(mac_ctx->psoc, - ft_session_ptr->vdev_id, false); /* Next routine may update nss based on dot11Mode */ lim_ft_prepare_add_bss_req(mac_ctx, ft_session_ptr, bss_desc); if (session_ptr->is11Rconnection) diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_sme_req_messages.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_sme_req_messages.c index f9eb195526dd..49113c9529e4 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_sme_req_messages.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_sme_req_messages.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1604,14 +1604,6 @@ __lim_process_sme_join_req(struct mac_context *mac_ctx, void *msg_buf) session->connected_akm = sme_join_req->akm; session->is_adaptive_11r_connection = sme_join_req->is_adaptive_11r_connection; - /* Reset the SPMK global cache for non-SAE connection */ - if (session->connected_akm != ANI_AKM_TYPE_SAE) { - wlan_mlme_set_sae_single_pmk_bss_cap(mac_ctx->psoc, - session->vdev_id, - false); - wlan_mlme_clear_sae_single_pmk_info(session->vdev, - NULL); - } #ifdef FEATURE_WLAN_ESE session->isESEconnection = sme_join_req->isESEconnection; #endif @@ -1840,7 +1832,7 @@ __lim_process_sme_join_req(struct mac_context *mac_ctx, void *msg_buf) session->spectrumMgtEnabled = true; session->isOSENConnection = sme_join_req->isOSENConnection; - pe_debug("Freq %d width %d freq0 %d freq1 %d, Smps %d: mode %d action %d, nss 1x1 %d vdev_nss %d nss %d cbMode %d dot11mode %d subfer %d subfee %d csn %d is_cisco %d akm %d", + pe_debug("Freq %d width %d freq0 %d freq1 %d, Smps %d: mode %d action %d, nss 1x1 %d vdev_nss %d nss %d cbMode %d dot11mode %d subfer %d subfee %d csn %d is_cisco %d", session->curr_op_freq, session->ch_width, session->ch_center_freq_seg0, session->ch_center_freq_seg1, @@ -1851,7 +1843,7 @@ __lim_process_sme_join_req(struct mac_context *mac_ctx, void *msg_buf) session->vht_config.su_beam_former, session->vht_config.su_beam_formee, session->vht_config.csnof_beamformer_antSup, - session->isCiscoVendorAP, session->connected_akm); + session->isCiscoVendorAP); /* Issue LIM_MLM_JOIN_REQ to MLM */ status = lim_send_join_req(session, mlm_join_req); @@ -1911,8 +1903,6 @@ void lim_parse_tpe_ie(struct mac_context *mac, struct pe_session *session, uint16_t bw_val, ch_width; qdf_freq_t curr_op_freq, curr_freq; enum reg_6g_client_type client_mobility_type; - enum reg_6g_ap_type ap_power_type_6g; - uint16_t reg_max = 0, psd_power = 0; struct ch_params ch_params = {0}; tDot11fIEtransmit_power_env single_tpe; /* @@ -1989,25 +1979,6 @@ void lim_parse_tpe_ie(struct mac_context *mac, struct pe_session *session, curr_op_freq = session->curr_op_freq; bw_val = wlan_reg_get_bw_value(session->ch_width); - if (psd_set) { - if (wlan_reg_is_6ghz_chan_freq(curr_op_freq)) { - ap_power_type_6g = session->best_6g_power_type; - - wlan_reg_get_client_power_for_connecting_ap( - mac->pdev, ap_power_type_6g, - curr_op_freq, true, ®_max, &psd_power); - - /* If reg rules don't support psd power, ignore PSD - * TPE IE - */ - if (!psd_power) { - pe_debug_rl("reg rule doesn't support psd for %d ap type %d", - curr_op_freq, ap_power_type_6g); - psd_set = false; - } - } - } - if (non_psd_set && !psd_set) { single_tpe = tpe_ies[non_psd_index]; vdev_mlme->reg_tpc_obj.is_psd_power = false; @@ -2088,9 +2059,6 @@ void lim_parse_tpe_ie(struct mac_context *mac, struct pe_session *session, single_tpe = tpe_ies[non_psd_index]; vdev_mlme->reg_tpc_obj.eirp_power = single_tpe.tx_power[single_tpe.max_tx_pwr_count]; - pe_debug("eirp_power %d", vdev_mlme->reg_tpc_obj.eirp_power); - if (!psd_set) - vdev_mlme->reg_tpc_obj.is_psd_power = false; } } @@ -2234,6 +2202,7 @@ void lim_calculate_tpc(struct mac_context *mac, skip_tpe = wlan_mlme_skip_tpe(mac->psoc); } else { is_6ghz_freq = true; + is_psd_power = wlan_reg_is_6g_psd_power(mac->pdev); if (LIM_IS_STA_ROLE(session)) ap_power_type_6g = session->best_6g_power_type; } @@ -2241,7 +2210,6 @@ void lim_calculate_tpc(struct mac_context *mac, if (mlme_obj->reg_tpc_obj.num_pwr_levels) { is_tpe_present = true; num_pwr_levels = mlme_obj->reg_tpc_obj.num_pwr_levels; - is_psd_power = mlme_obj->reg_tpc_obj.is_psd_power; } else { num_pwr_levels = lim_get_num_pwr_levels(is_psd_power, session->ch_width); @@ -2255,21 +2223,13 @@ void lim_calculate_tpc(struct mac_context *mac, ch_params.ch_width = CH_WIDTH_20MHZ; - for (i = 0; - i < num_pwr_levels && (ch_params.ch_width != CH_WIDTH_INVALID); - i++) { + for (i = 0; i < num_pwr_levels; i++) { if (is_tpe_present) { if (is_6ghz_freq) { - if (is_psd_power) { - wlan_reg_get_client_power_for_connecting_ap( - mac->pdev, ap_power_type_6g, - mlme_obj->reg_tpc_obj.frequency[i], - is_psd_power, ®_max, &psd_power); - } else { - wlan_reg_get_client_power_for_connecting_ap( - mac->pdev, ap_power_type_6g, oper_freq, - is_psd_power, ®_max, &psd_power); - } + wlan_reg_get_client_power_for_connecting_ap( + mac->pdev, ap_power_type_6g, + mlme_obj->reg_tpc_obj.frequency[i], + &is_psd_power, ®_max, &psd_power); } } else { /* center frequency calculation */ @@ -2281,18 +2241,18 @@ void lim_calculate_tpc(struct mac_context *mac, mac->pdev, oper_freq, 0, &ch_params); mlme_obj->reg_tpc_obj.frequency[i] = ch_params.mhz_freq_seg0; - if (ch_params.ch_width != CH_WIDTH_INVALID) - ch_params.ch_width = - get_next_higher_bw[ch_params.ch_width]; + ch_params.ch_width = + get_next_higher_bw[ch_params.ch_width]; } if (is_6ghz_freq) { if (LIM_IS_STA_ROLE(session)) { wlan_reg_get_client_power_for_connecting_ap (mac->pdev, ap_power_type_6g, mlme_obj->reg_tpc_obj.frequency[i], - is_psd_power, ®_max, &psd_power); + &is_psd_power, ®_max, &psd_power); } else { - wlan_reg_get_cur_6g_ap_pwr_type( + ap_power_type_6g = + wlan_reg_get_cur_6g_ap_pwr_type( mac->pdev, &ap_power_type_6g); wlan_reg_get_6g_chan_ap_power( @@ -2358,6 +2318,7 @@ void lim_calculate_tpc(struct mac_context *mac, } mlme_obj->reg_tpc_obj.num_pwr_levels = num_pwr_levels; + mlme_obj->reg_tpc_obj.is_psd_power = is_psd_power; mlme_obj->reg_tpc_obj.eirp_power = reg_max; mlme_obj->reg_tpc_obj.power_type_6g = ap_power_type_6g; @@ -6528,9 +6489,6 @@ static void lim_process_set_ie_req(struct mac_context *mac_ctx, uint32_t *msg_bu if (p_ext_cap->interworking_service) p_ext_cap->qos_map = 1; - if (wma_is_mbssid_enabled()) - p_ext_cap->multi_bssid = 1; - extra_ext_cap.num_bytes = lim_compute_ext_cap_ie_length(&extra_ext_cap); send_ie: diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_sme_rsp_messages.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_sme_rsp_messages.c index 639fac0c3c4f..8b6a073ea59e 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_sme_rsp_messages.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_sme_rsp_messages.c @@ -1,6 +1,5 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1885,7 +1884,6 @@ void lim_handle_csa_offload_msg(struct mac_context *mac_ctx, err: qdf_mem_free(csa_params); - session_entry->cal_tpc_post_csa = true; } /*-------------------------------------------------------------------------- diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_process.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_process.c index 8ffa424d5962..3c0914e6c71a 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_process.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_process.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -704,9 +704,8 @@ static void __sch_beacon_process_for_session(struct mac_context *mac_ctx, } if ((ap_constraint_change && local_constraint) || - (tpe_change && !skip_tpe) || session->cal_tpc_post_csa) { + (tpe_change && !skip_tpe)) { lim_calculate_tpc(mac_ctx, session); - session->cal_tpc_post_csa = false; if (tx_ops->set_tpc_power) tx_ops->set_tpc_power(mac_ctx->psoc, diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_roam.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_roam.c index cf719e8501a6..262b4f292c30 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_roam.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_roam.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -17422,8 +17422,6 @@ static void csr_cm_update_driver_assoc_ies( MIN_TX_PWR_CAP, MAX_TX_PWR_CAP}; uint8_t max_tx_pwr_cap = 0; uint8_t supp_chan_ie[DOT11F_IE_SUPPCHANNELS_MAX_LEN], supp_chan_ie_len; - struct s_ext_cap *extcap; - uint8_t *ext_cap_ie; static const uint8_t qcn_ie[] = {0x8C, 0xFD, 0xF0, 0x1, QCN_IE_VERSION_SUBATTR_ID, QCN_IE_VERSION_SUBATTR_DATA_LEN, @@ -17435,14 +17433,6 @@ static void csr_cm_update_driver_assoc_ies( qdf_mem_copy(rso_mode_cfg->assoc_ie, session->pAddIEAssoc, rso_mode_cfg->assoc_ie_length); - ext_cap_ie = (uint8_t *)wlan_get_ie_ptr_from_eid(WLAN_ELEMID_XCAPS, - rso_mode_cfg->assoc_ie, - rso_mode_cfg->assoc_ie_length); - if (ext_cap_ie && wma_is_mbssid_enabled()) { - extcap = (struct s_ext_cap *)&ext_cap_ie[2]; - extcap->multi_bssid = 1; - } - if (session->pConnectBssDesc) max_tx_pwr_cap = csr_get_cfg_max_tx_power( mac_ctx, @@ -21461,15 +21451,12 @@ csr_process_roam_sync_callback(struct mac_context *mac_ctx, mac_ctx->psoc); mac_ctx->sme.set_connection_info_cb(false); - if (roam_synch_data->pmk_len) { - mlme_debug("Received pmk in roam sync. Length: %d", - roam_synch_data->pmk_len); + if (roam_synch_data->pmk_len) csr_check_and_set_sae_single_pmk_cap( mac_ctx, session, session_id, roam_synch_data->pmk, roam_synch_data->pmk_len); - } if (ucfg_pkt_capture_get_pktcap_mode(mac_ctx->psoc)) ucfg_pkt_capture_record_channel(vdev); @@ -21599,12 +21586,11 @@ csr_process_roam_sync_callback(struct mac_context *mac_ctx, * eapol. So the session->psk_pmk will be stale in PMKSA cached * SAE/OWE roaming case. */ - akm_type = session->connectedProfile.AuthType; - if (roam_synch_data->authStatus == CSR_ROAM_AUTH_STATUS_AUTHENTICATED || - akm_type == eCSR_AUTH_TYPE_SAE || - akm_type == eCSR_AUTH_TYPE_FT_SAE || - akm_type == eCSR_AUTH_TYPE_OWE) { + session->pCurRoamProfile->negotiatedAuthType == + eCSR_AUTH_TYPE_SAE || + session->pCurRoamProfile->negotiatedAuthType == + eCSR_AUTH_TYPE_OWE) { csr_roam_substate_change(mac_ctx, eCSR_ROAM_SUBSTATE_NONE, session_id); /* @@ -21629,7 +21615,8 @@ csr_process_roam_sync_callback(struct mac_context *mac_ctx, &session->connectedProfile.bssid); sme_debug("Trying to find PMKID for " QDF_MAC_ADDR_FMT " AKM Type:%d", QDF_MAC_ADDR_REF(pmkid_cache->BSSID.bytes), - akm_type); + session->pCurRoamProfile->negotiatedAuthType); + akm_type = session->connectedProfile.AuthType; mdie_present = session->connectedProfile.mdid.mdie_present; if (csr_lookup_pmkid_using_bssid(mac_ctx, session, @@ -21709,8 +21696,6 @@ csr_process_roam_sync_callback(struct mac_context *mac_ctx, qdf_mem_zero(pmksa, sizeof(*pmksa)); qdf_mem_free(pmksa); } - } else { - sme_debug("PMK not received from fw"); } sme_debug("pmkid found for " QDF_MAC_ADDR_FMT " len %d", QDF_MAC_ADDR_REF(pmkid_cache->BSSID.bytes), diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c index 5ce7d5345138..8ba4ef61b6a1 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c @@ -2256,7 +2256,6 @@ static QDF_STATUS csr_fill_bss_from_scan_entry(struct mac_context *mac_ctx, bss_desc->beaconInterval = scan_entry->bcn_int; bss_desc->capabilityInfo = scan_entry->cap_info.value; - bss_desc->neg_rsn_caps = scan_entry->neg_sec_info.rsn_caps; if (WLAN_REG_IS_5GHZ_CH_FREQ(scan_entry->channel.chan_freq) || WLAN_REG_IS_6GHZ_CHAN_FREQ(scan_entry->channel.chan_freq)) diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_neighbor_roam.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_neighbor_roam.c index ccfa013b89c3..e40a9efd179c 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_neighbor_roam.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_neighbor_roam.c @@ -848,9 +848,6 @@ static void csr_neighbor_roam_info_ctx_init(struct mac_context *mac, wlan_cm_roam_cfg_set_value(mac->psoc, session_id, ROAM_RSSI_DIFF_6GHZ, &src_cfg); - src_cfg.uint_value = mac->mlme_cfg->lfr.roam_rssi_delta_6ghz_to_non_6ghz; - wlan_cm_roam_cfg_set_value(mac->psoc, session_id, - ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ, &src_cfg); /* * Now we can clear the preauthDone that * was saved as we are connected afresh diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c index c2e0f97e1e1f..f8c2f48b711c 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2451,27 +2451,18 @@ static void csr_update_key_mgmt_crypto_param(struct wlan_objmgr_vdev *vdev, { int32_t key_mgmt = 0; int32_t neg_akm; - int32_t ap_akm = 0; uint8_t i; - neg_akm = wlan_crypto_get_param(vdev, WLAN_CRYPTO_PARAM_ORIG_KEY_MGMT); + neg_akm = wlan_crypto_get_param(vdev, WLAN_CRYPTO_PARAM_KEY_MGMT); if (neg_akm < 0) { sme_err("Invalid AKM suite"); return; } for (i = 0; i < ap_rsn.akm_suite_cnt; i++) - SET_PARAM(ap_akm, + SET_PARAM(neg_akm, wlan_crypto_rsn_suite_to_keymgmt(ap_rsn.akm_suite[i])); - /* Intersect crypto AKM and candidate AP's AKM */ - neg_akm &= ap_akm; - if (neg_akm <= 0) { - sme_err("Invalid AKM suite"); - return; - } - sme_debug("Intersected AKM with AP's AKM 0x%x", neg_akm); - /* * As there can be multiple AKM present select the most secured AKM * present @@ -2540,7 +2531,6 @@ static void csr_update_ucast_cipher_crypto_param(struct wlan_objmgr_vdev *vdev, { int32_t ucastcipherset = 0; int32_t neg_ucastcipher; - int32_t ap_ucastcipher = 0; uint8_t i; neg_ucastcipher = wlan_crypto_get_param(vdev, @@ -2551,16 +2541,9 @@ static void csr_update_ucast_cipher_crypto_param(struct wlan_objmgr_vdev *vdev, } for (i = 0; i < ap_rsn.pwise_cipher_suite_count; i++) - SET_PARAM(ap_ucastcipher, + SET_PARAM(neg_ucastcipher, wlan_crypto_rsn_suite_to_cipher(ap_rsn.pwise_cipher_suites[i])); - /* Intersect crypto cipherset and candidate AP's cipherset */ - neg_ucastcipher &= ap_ucastcipher; - if (neg_ucastcipher <= 0) { - sme_err("Invalid unicast cipherset"); - return; - } - /* * As there can be multiple ucastcipher present select the most secured * ucastcipher present. @@ -2604,6 +2587,8 @@ uint8_t csr_construct_rsn_ie(struct mac_context *mac, uint32_t sessionId, (mac, pSirBssDesc, &local_ap_ie)))) return ie_len; + /* get AP RSN cap */ + qdf_mem_copy(&rsn_cap, local_ap_ie->RSN.RSN_Cap, sizeof(rsn_cap)); if (!ap_ie && local_ap_ie) /* locally allocated */ qdf_mem_free(local_ap_ie); @@ -2623,8 +2608,6 @@ uint8_t csr_construct_rsn_ie(struct mac_context *mac, uint32_t sessionId, } self_rsn_cap = (uint16_t)rsn_val; - /* get AP RSN cap */ - rsn_cap = pSirBssDesc->neg_rsn_caps; /* If AP is capable then use self capability else set PMF as 0 */ if (rsn_cap & WLAN_CRYPTO_RSN_CAP_MFP_ENABLED && pProfile->MFPCapable) { diff --git a/drivers/staging/qcacld-3.0/core/wma/inc/wma.h b/drivers/staging/qcacld-3.0/core/wma/inc/wma.h index 99b2164e618a..5474fe767d0f 100644 --- a/drivers/staging/qcacld-3.0/core/wma/inc/wma.h +++ b/drivers/staging/qcacld-3.0/core/wma/inc/wma.h @@ -909,12 +909,11 @@ struct wma_wlm_stats_data { * @dynamic_nss_chains_update: per vdev nss, chains update * @ito_repeat_count: Indicates ito repeated count * @wma_fw_time_sync_timer: timer used for firmware time sync - * @fw_therm_throt_support: FW Supports thermal throttling? - * @roam_sync_runtime_lock: roam sync runtime lock - * @is_roam_lock_acquired: Is roam_sync_runtime_lock acquired + * * @fw_therm_throt_support: FW Supports thermal throttling? * * This structure is the global wma context. It contains global wma * module parameters and handles of other modules. + */ typedef struct { void *wmi_handle; @@ -1046,8 +1045,6 @@ typedef struct { qdf_mc_timer_t wma_fw_time_sync_timer; bool fw_therm_throt_support; bool enable_tx_compl_tsf64; - qdf_runtime_lock_t roam_sync_runtime_lock; - bool is_roam_lock_acquired; } t_wma_handle, *tp_wma_handle; /** diff --git a/drivers/staging/qcacld-3.0/core/wma/inc/wma_internal.h b/drivers/staging/qcacld-3.0/core/wma/inc/wma_internal.h index 45e2e678442b..1d7f88d5392c 100644 --- a/drivers/staging/qcacld-3.0/core/wma/inc/wma_internal.h +++ b/drivers/staging/qcacld-3.0/core/wma/inc/wma_internal.h @@ -1587,23 +1587,6 @@ void wma_acquire_wakelock(qdf_wake_lock_t *wl, uint32_t msec); */ void wma_release_wakelock(qdf_wake_lock_t *wl); -/** - * wma_prevent_pm_during_roam_sync() - prevent runtime PM during roam sync - * @wma: a reference to the global WMA handle - * - * Return: None - */ -void wma_prevent_pm_during_roam_sync(t_wma_handle *wma); - -/** - * wma_allow_pm_after_roam_sync() - allow runtime PM after roam - * sync complete - * @wma: a reference to the global WMA handle - * - * Return: None - */ -void wma_allow_pm_after_roam_sync(t_wma_handle *wma); - /** * wma_send_vdev_stop_to_fw() - send the vdev stop command to firmware * @wma: a reference to the global WMA handle diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_dev_if.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_dev_if.c index 4d045b27df28..15f3c657a065 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_dev_if.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_dev_if.c @@ -943,14 +943,14 @@ static void wma_peer_send_phymode(struct wlan_objmgr_vdev *vdev, fw_phymode = wma_host_to_fw_phymode(new_phymode); vdev_id = wlan_vdev_get_id(vdev); + wma_set_peer_param(wma, peer_mac_addr, WMI_PEER_PHYMODE, + fw_phymode, vdev_id); + max_ch_width_supported = wmi_get_ch_width_from_phy_mode(wma->wmi_handle, fw_phymode); wma_set_peer_param(wma, peer_mac_addr, WMI_PEER_CHWIDTH, max_ch_width_supported, vdev_id); - wma_set_peer_param(wma, peer_mac_addr, WMI_PEER_PHYMODE, - fw_phymode, vdev_id); - wma_debug("FW phymode %d old phymode %d new phymode %d bw %d macaddr "QDF_MAC_ADDR_FMT, fw_phymode, old_peer_phymode, new_phymode, max_ch_width_supported, QDF_MAC_ADDR_REF(peer_mac_addr)); diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_features.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_features.c index 2d22d4726167..dcd409da821b 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_features.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_features.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2907,9 +2907,6 @@ int wma_wow_wakeup_host_event(void *handle, uint8_t *event, uint32_t len) WMI_WOW_WAKEUP_HOST_EVENTID_param_tlvs *event_param; WOW_EVENT_INFO_fixed_param *wake_info; - if (!wma || !wma->psoc) - return -EINVAL; - event_param = (WMI_WOW_WAKEUP_HOST_EVENTID_param_tlvs *)event; if (!event_param) { wma_err("Wake event data is null"); diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c index 7021b8720fc3..b48b2729e9ae 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c @@ -3428,8 +3428,6 @@ QDF_STATUS wma_open(struct wlan_objmgr_psoc *psoc, "wlan_fw_rsp_wakelock"); qdf_runtime_lock_init(&wma_handle->wmi_cmd_rsp_runtime_lock); qdf_runtime_lock_init(&wma_handle->sap_prevent_runtime_pm_lock); - qdf_runtime_lock_init(&wma_handle->roam_sync_runtime_lock); - wma_handle->is_roam_lock_acquired = false; /* Register peer assoc conf event handler */ wmi_unified_register_event_handler(wma_handle->wmi_handle, @@ -3540,7 +3538,6 @@ err_dbglog_init: qdf_runtime_lock_deinit(&wma_handle->sap_prevent_runtime_pm_lock); qdf_runtime_lock_deinit(&wma_handle->wmi_cmd_rsp_runtime_lock); qdf_spinlock_destroy(&wma_handle->wma_hold_req_q_lock); - qdf_runtime_lock_deinit(&wma_handle->roam_sync_runtime_lock); err_event_init: wmi_unified_unregister_event_handler(wma_handle->wmi_handle, wmi_debug_print_event_id); @@ -4595,7 +4592,6 @@ QDF_STATUS wma_close(void) qdf_wake_lock_destroy(&wma_handle->wmi_cmd_rsp_wake_lock); qdf_runtime_lock_deinit(&wma_handle->sap_prevent_runtime_pm_lock); qdf_runtime_lock_deinit(&wma_handle->wmi_cmd_rsp_runtime_lock); - qdf_runtime_lock_deinit(&wma_handle->roam_sync_runtime_lock); qdf_spinlock_destroy(&wma_handle->wma_hold_req_q_lock); if (wma_handle->pGetRssiReq) { diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_mgmt.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_mgmt.c index ec3e079e5096..3c7e6c9105e0 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_mgmt.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_mgmt.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022, 2026 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2732,10 +2732,6 @@ void wma_process_update_opmode(tp_wma_handle wma_handle, wma_set_peer_param(wma_handle, update_vht_opmode->peer_mac, WMI_PEER_CHWIDTH, update_vht_opmode->opMode, update_vht_opmode->smesessionId); - - wma_set_peer_param(wma_handle, update_vht_opmode->peer_mac, - WMI_PEER_PHYMODE, - fw_phymode, update_vht_opmode->smesessionId); } /** diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_power.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_power.c index 66ca5d8947a4..4fdc73e85179 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_power.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_power.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1171,28 +1171,20 @@ static void wma_update_beacon_noa_ie(struct beacon_info *bcn, /* TODO: Assuming p2p noa ie is last ie in the beacon */ qdf_mem_zero(bcn->noa_ie, (bcn->noa_sub_ie_len + sizeof(struct p2p_ie))); - if (bcn->len < (bcn->noa_sub_ie_len + - sizeof(struct p2p_ie))) - bcn->len = 0; - else - bcn->len -= (bcn->noa_sub_ie_len + - sizeof(struct p2p_ie)); + bcn->len -= (bcn->noa_sub_ie_len + + sizeof(struct p2p_ie)); bcn->noa_ie = NULL; bcn->noa_sub_ie_len = 0; } + wma_debug("No need to update NoA"); return; } if (bcn->noa_sub_ie_len && bcn->noa_ie) { - if (bcn->len < (bcn->noa_sub_ie_len + sizeof(struct p2p_ie))) - bcn->len = 0; - else - bcn->len -= (bcn->noa_sub_ie_len + - sizeof(struct p2p_ie)); - /* NoA present in previous beacon, update it */ wma_debug("NoA present in previous beacon, update the NoA IE, bcn->len %u bcn->noa_sub_ie_len %u", - bcn->len, bcn->noa_sub_ie_len); + bcn->len, bcn->noa_sub_ie_len); + bcn->len -= (bcn->noa_sub_ie_len + sizeof(struct p2p_ie)); qdf_mem_zero(bcn->noa_ie, (bcn->noa_sub_ie_len + sizeof(struct p2p_ie))); } else { /* NoA is not present in previous beacon */ diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c index 915e196f4d81..702063ef6170 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c @@ -1617,23 +1617,21 @@ int wma_roam_synch_event_handler(void *handle, uint8_t *event, return status; } - wma_prevent_pm_during_roam_sync(wma); - param_buf = (WMI_ROAM_SYNCH_EVENTID_param_tlvs *)event; if (!param_buf) { wma_err_rl("received null buf from target"); - goto fail; + return status; } synch_event = param_buf->fixed_param; if (!synch_event) { wma_err_rl("received null event data from target"); - goto fail; + return status; } if (synch_event->vdev_id >= wma->max_bssid) { wma_err_rl("received invalid vdev_id %d", synch_event->vdev_id); - goto fail; + return status; } iface = &wma->interfaces[synch_event->vdev_id]; @@ -1649,14 +1647,10 @@ int wma_roam_synch_event_handler(void *handle, uint8_t *event, if (QDF_IS_STATUS_ERROR(qdf_status)) { wma_err("Failed to send the EV_ROAM"); wma_post_roam_sync_failure(wma, synch_event->vdev_id); - goto fail; + return status; } wma_debug("Posted EV_ROAM to VDEV SM"); return 0; - -fail: - wma_allow_pm_after_roam_sync(wma); - return status; } int wma_roam_auth_offload_event_handler(WMA_HANDLE handle, uint8_t *event, @@ -2070,7 +2064,7 @@ wma_rso_print_scan_info(struct wmi_roam_scan_data *scan, uint8_t vdev_id, tmp = buf; /* For partial scans, print the channel info */ - if (scan->type == ROAM_STATS_SCAN_TYPE_PARTIAL) { + if (!scan->type) { buf_cons = qdf_snprint(tmp, buf_left, "{"); buf_left -= buf_cons; tmp += buf_cons; @@ -2839,7 +2833,6 @@ void wma_process_roam_synch_complete(WMA_HANDLE handle, uint8_t vdev_id) wma_info("LFR3: vdev[%d] Sent ROAM_SYNCH_COMPLETE", vdev_id); wlan_roam_debug_log(vdev_id, DEBUG_ROAM_SYNCH_CNF, DEBUG_INVALID_PEER_ID, NULL, NULL, 0, 0); - wma_allow_pm_after_roam_sync(wma_handle); } #endif /* WLAN_FEATURE_ROAM_OFFLOAD */ @@ -4558,12 +4551,10 @@ static void wma_invalid_roam_reason_handler(tp_wma_handle wma_handle, if (notif == WMI_ROAM_NOTIF_ROAM_START) { wma_handle->interfaces[vdev_id].roaming_in_progress = true; op_code = SIR_ROAMING_START; - wma_prevent_pm_during_roam_sync(wma_handle); } else if (notif == WMI_ROAM_NOTIF_ROAM_ABORT) { wma_handle->interfaces[vdev_id].roaming_in_progress = false; op_code = SIR_ROAMING_ABORT; lim_sae_auth_cleanup_retry(wma_handle->mac_context, vdev_id); - wma_allow_pm_after_roam_sync(wma_handle); } else { wma_debug("Invalid notif %d", notif); return; @@ -4739,7 +4730,6 @@ int wma_roam_event_callback(WMA_HANDLE handle, uint8_t *event_buf, = false; lim_sae_auth_cleanup_retry(wma_handle->mac_context, wmi_event->vdev_id); - wma_allow_pm_after_roam_sync(wma_handle); break; #endif case WMI_ROAM_REASON_INVALID: diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_utils.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_utils.c index 23d2e9a87be8..57d3d09ea1da 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_utils.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_utils.c @@ -1361,15 +1361,6 @@ wma_fill_rx_stats(struct sir_wifi_ll_ext_stats *ll_stats, wmi_peer_rx, wmi_rx, peer_stats); return QDF_STATUS_E_FAILURE; } - - /* Check if num_rx_stats is sufficient to avoid buffer overflow */ - if (param_buf->num_rx_stats < - fix_param->num_peer_ac_rx_stats * WLAN_MAX_AC) { - wma_err("Insufficient rx_stats buffer: available %d, required %d", - param_buf->num_rx_stats, - fix_param->num_peer_ac_rx_stats * WLAN_MAX_AC); - return QDF_STATUS_E_FAILURE; - } for (i = 0; i < fix_param->num_peer_ac_rx_stats; i++) { uint32_t peer_id = wmi_peer_rx[i].peer_id; struct sir_wifi_rx *ac; @@ -3824,30 +3815,6 @@ void wma_release_wakelock(qdf_wake_lock_t *wl) qdf_runtime_pm_allow_suspend(&wma->wmi_cmd_rsp_runtime_lock); } -void wma_prevent_pm_during_roam_sync(t_wma_handle *wma) -{ - if (!wma) - return; - - if (wma->is_roam_lock_acquired) - return; - - qdf_runtime_pm_prevent_suspend(&wma->roam_sync_runtime_lock); - wma->is_roam_lock_acquired = true; -} - -void wma_allow_pm_after_roam_sync(t_wma_handle *wma) -{ - if (!wma) - return; - - if (!wma->is_roam_lock_acquired) - return; - - qdf_runtime_pm_allow_suspend(&wma->roam_sync_runtime_lock); - wma->is_roam_lock_acquired = false; -} - QDF_STATUS wma_send_vdev_stop_to_fw(t_wma_handle *wma, uint8_t vdev_id) { QDF_STATUS status = QDF_STATUS_E_FAILURE; diff --git a/drivers/staging/qcacld-3.0/os_if/p2p/src/wlan_cfg80211_p2p.c b/drivers/staging/qcacld-3.0/os_if/p2p/src/wlan_cfg80211_p2p.c index 8363fbe52a80..ddeba7bf0d51 100644 --- a/drivers/staging/qcacld-3.0/os_if/p2p/src/wlan_cfg80211_p2p.c +++ b/drivers/staging/qcacld-3.0/os_if/p2p/src/wlan_cfg80211_p2p.c @@ -1,6 +1,5 @@ /* * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -282,7 +281,8 @@ static void wlan_p2p_event_callback(void *user_data, goto fail; } - chan = ieee80211_get_channel(wdev->wiphy, p2p_event->chan_freq); + chan = ieee80211_get_channel(wdev->wiphy, + wlan_chan_to_freq(p2p_event->chan)); if (!chan) { osif_err("channel conversion failed"); goto fail; @@ -360,7 +360,7 @@ int wlan_cfg80211_roc(struct wlan_objmgr_vdev *vdev, return -EINVAL; } - roc_req.chan_freq = chan->center_freq; + roc_req.chan = (uint32_t)wlan_freq_to_chan(chan->center_freq); roc_req.duration = duration; roc_req.vdev_id = (uint32_t)vdev_id; @@ -372,7 +372,7 @@ int wlan_cfg80211_roc(struct wlan_objmgr_vdev *vdev, } if (!ok) { - osif_err("channel%d not OK for DNBS", roc_req.chan_freq); + osif_err("channel%d not OK for DNBS", roc_req.chan); return -EINVAL; } @@ -409,7 +409,7 @@ int wlan_cfg80211_mgmt_tx(struct wlan_objmgr_vdev *vdev, struct p2p_mgmt_tx mgmt_tx = {0}; struct wlan_objmgr_psoc *psoc; uint8_t vdev_id; - qdf_freq_t chan_freq = 0; + uint32_t channel = 0; if (!vdev) { osif_err("invalid vdev object"); @@ -417,7 +417,7 @@ int wlan_cfg80211_mgmt_tx(struct wlan_objmgr_vdev *vdev, } if (chan) - chan_freq = chan->center_freq; + channel = (uint32_t)wlan_freq_to_chan(chan->center_freq); else osif_debug("NULL chan, set channel to 0"); @@ -436,7 +436,8 @@ int wlan_cfg80211_mgmt_tx(struct wlan_objmgr_vdev *vdev, int ret; bool ok; - ret = policy_mgr_is_chan_ok_for_dnbs(psoc, chan_freq, &ok); + ret = policy_mgr_is_chan_ok_for_dnbs( + psoc, wlan_chan_to_freq(channel), &ok); if (QDF_IS_STATUS_ERROR(ret)) { osif_err("policy_mgr_is_chan_ok_for_dnbs():ret:%d", ret); @@ -444,13 +445,13 @@ int wlan_cfg80211_mgmt_tx(struct wlan_objmgr_vdev *vdev, } if (!ok) { osif_err("Rejecting mgmt_tx for channel:%d as DNSC is set", - chan_freq); + channel); return -EINVAL; } } mgmt_tx.vdev_id = (uint32_t)vdev_id; - mgmt_tx.chan_freq = chan_freq; + mgmt_tx.chan = channel; mgmt_tx.wait = wait; mgmt_tx.len = len; mgmt_tx.no_cck = (uint32_t)no_cck; diff --git a/drivers/staging/qcacld-3.0/uapi/linux/a_types.h b/drivers/staging/qcacld-3.0/uapi/linux/a_types.h index 5537fae67697..190d40df6afd 100644 --- a/drivers/staging/qcacld-3.0/uapi/linux/a_types.h +++ b/drivers/staging/qcacld-3.0/uapi/linux/a_types.h @@ -1,6 +1,5 @@ /* * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -30,21 +29,15 @@ #define _A_TYPES_H_ #include -typedef unsigned long long A_UINT64; -typedef long long A_INT64; - typedef unsigned int A_UINT32; -typedef int A_INT32; - +typedef unsigned long long A_UINT64; typedef unsigned short A_UINT16; -typedef short A_INT16; - typedef unsigned char A_UINT8; -typedef char A_INT8; - +typedef int A_INT32; +typedef short A_INT16; +typedef char A_INT8; typedef unsigned char A_UCHAR; -typedef char A_CHAR; - +typedef char A_CHAR; typedef _Bool A_BOOL; #endif /* _ATHTYPES_H_ */ diff --git a/drivers/staging/vme/devices/vme_user.c b/drivers/staging/vme/devices/vme_user.c index fd0ea4dbcb91..6a33aaa1a49f 100644 --- a/drivers/staging/vme/devices/vme_user.c +++ b/drivers/staging/vme/devices/vme_user.c @@ -494,7 +494,7 @@ static const struct file_operations vme_user_fops = { .write = vme_user_write, .llseek = vme_user_llseek, .unlocked_ioctl = vme_user_unlocked_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = vme_user_unlocked_ioctl, .mmap = vme_user_mmap, }; diff --git a/drivers/tee/tee_core.c b/drivers/tee/tee_core.c index faa6ac8719cc..28cbe4613ed9 100644 --- a/drivers/tee/tee_core.c +++ b/drivers/tee/tee_core.c @@ -683,7 +683,7 @@ static const struct file_operations tee_fops = { .open = tee_open, .release = tee_release, .unlocked_ioctl = tee_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = tee_ioctl, }; static void tee_release_device(struct device *dev) diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c index 47c50bb1eef3..cfee5b5799b6 100644 --- a/drivers/tty/serial/msm_serial_hs.c +++ b/drivers/tty/serial/msm_serial_hs.c @@ -2684,7 +2684,7 @@ static int msm_hs_startup(struct uart_port *uport) tx->dma_in_flight = false; MSM_HS_DBG("%s():desc usage flag 0x%lx\n", __func__, rx->queued_flag); timer_setup(&(tx->tx_timeout_timer), - tx_timeout_handler, TIMER_IRQSAFE); + tx_timeout_handler, 0); /* Enable reading the current CTS, no harm even if CTS is ignored */ msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK; diff --git a/drivers/tty/tty_ioctl.c b/drivers/tty/tty_ioctl.c index 2fbd991f5e34..5d833f0b412d 100644 --- a/drivers/tty/tty_ioctl.c +++ b/drivers/tty/tty_ioctl.c @@ -807,7 +807,7 @@ int tty_mode_ioctl(struct tty_struct *tty, struct file *file, ret = -EFAULT; return ret; case TIOCSLCKTRMIOS: - if (!checkpoint_restore_ns_capable(&init_user_ns)) + if (!capable(CAP_SYS_ADMIN)) return -EPERM; copy_termios_locked(real_tty, &kterm); if (user_termios_to_kernel_termios(&kterm, @@ -824,7 +824,7 @@ int tty_mode_ioctl(struct tty_struct *tty, struct file *file, ret = -EFAULT; return ret; case TIOCSLCKTRMIOS: - if (!checkpoint_restore_ns_capable(&init_user_ns)) + if (!capable(CAP_SYS_ADMIN)) return -EPERM; copy_termios_locked(real_tty, &kterm); if (user_termios_to_kernel_termios_1(&kterm, diff --git a/drivers/usb/class/cdc-wdm.c b/drivers/usb/class/cdc-wdm.c index d2bbc9a43e7b..6afb941dd267 100644 --- a/drivers/usb/class/cdc-wdm.c +++ b/drivers/usb/class/cdc-wdm.c @@ -790,7 +790,7 @@ static const struct file_operations wdm_fops = { .release = wdm_release, .poll = wdm_poll, .unlocked_ioctl = wdm_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = wdm_ioctl, .llseek = noop_llseek, }; diff --git a/drivers/usb/class/usbtmc.c b/drivers/usb/class/usbtmc.c index 7ad47637f2a7..d8ed205e6b43 100644 --- a/drivers/usb/class/usbtmc.c +++ b/drivers/usb/class/usbtmc.c @@ -2241,7 +2241,9 @@ static const struct file_operations fops = { .release = usbtmc_release, .flush = usbtmc_flush, .unlocked_ioctl = usbtmc_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = usbtmc_ioctl, +#endif .fasync = usbtmc_fasync, .poll = usbtmc_poll, .llseek = default_llseek, diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 2b9a638bbd60..a12c5c9ed397 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -491,10 +491,6 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, dwc3_gadget_ep_get_transfer_index(dep); } - if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER && - !(cmd & DWC3_DEPCMD_CMDIOC)) - mdelay(1); - if (saved_config) { reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg |= saved_config; @@ -3754,6 +3750,9 @@ int dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt) else dep->flags |= DWC3_EP_END_TRANSFER_PENDING; + if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) + udelay(100); + return ret; } EXPORT_SYMBOL(dwc3_stop_active_transfer); diff --git a/drivers/usb/gadget/function/f_uvc.c b/drivers/usb/gadget/function/f_uvc.c index b4c08b4ed602..094a88ff9a67 100644 --- a/drivers/usb/gadget/function/f_uvc.c +++ b/drivers/usb/gadget/function/f_uvc.c @@ -808,9 +808,9 @@ static struct usb_function_instance *uvc_alloc_inst(void) cd->wObjectiveFocalLengthMax = cpu_to_le16(0); cd->wOcularFocalLength = cpu_to_le16(0); cd->bControlSize = 3; - cd->bmControls[0] = 62; - cd->bmControls[1] = 126; - cd->bmControls[2] = 10; + cd->bmControls[0] = 2; + cd->bmControls[1] = 0; + cd->bmControls[2] = 0; pd = &opts->uvc_processing; pd->bLength = UVC_DT_PROCESSING_UNIT_SIZE(2); @@ -820,8 +820,8 @@ static struct usb_function_instance *uvc_alloc_inst(void) pd->bSourceID = 1; pd->wMaxMultiplier = cpu_to_le16(16*1024); pd->bControlSize = 2; - pd->bmControls[0] = 91; - pd->bmControls[1] = 23; + pd->bmControls[0] = 1; + pd->bmControls[1] = 0; pd->iProcessing = 0; pd->bmVideoStandards = 0; diff --git a/drivers/usb/gadget/function/uvc.h b/drivers/usb/gadget/function/uvc.h index 9961d7d04546..1473d25ff17a 100644 --- a/drivers/usb/gadget/function/uvc.h +++ b/drivers/usb/gadget/function/uvc.h @@ -65,7 +65,7 @@ extern unsigned int uvc_gadget_trace_param; * Driver specific constants */ -#define UVC_NUM_REQUESTS 64 +#define UVC_NUM_REQUESTS 4 #define UVC_MAX_REQUEST_SIZE 64 #define UVC_MAX_EVENTS 4 diff --git a/drivers/usb/gadget/function/uvc_configfs.c b/drivers/usb/gadget/function/uvc_configfs.c index 5480a2988fe4..00fb58e50a15 100644 --- a/drivers/usb/gadget/function/uvc_configfs.c +++ b/drivers/usb/gadget/function/uvc_configfs.c @@ -762,19 +762,16 @@ static const struct uvcg_config_group_type uvcg_control_grp_type = { /* ----------------------------------------------------------------------------- * streaming/uncompressed * streaming/mjpeg - * streaming/framebased */ static const char * const uvcg_format_names[] = { "uncompressed", "mjpeg", - "framebased" }; enum uvcg_format_type { UVCG_UNCOMPRESSED = 0, UVCG_MJPEG, - UVCG_FRAMEBASED, }; struct uvcg_format { @@ -1083,7 +1080,6 @@ struct uvcg_frame { u32 dw_max_video_frame_buffer_size; u32 dw_default_frame_interval; u8 b_frame_interval_type; - u32 dw_bytes_perline; } __attribute__((packed)) frame; u32 *dw_frame_interval; }; @@ -1194,7 +1190,6 @@ UVCG_FRAME_ATTR(dw_min_bit_rate, dwMinBitRate, 32); UVCG_FRAME_ATTR(dw_max_bit_rate, dwMaxBitRate, 32); UVCG_FRAME_ATTR(dw_max_video_frame_buffer_size, dwMaxVideoFrameBufferSize, 32); UVCG_FRAME_ATTR(dw_default_frame_interval, dwDefaultFrameInterval, 32); -UVCG_FRAME_ATTR(dw_bytes_perline, dwBytesPerLine, 32); #undef UVCG_FRAME_ATTR @@ -1329,7 +1324,7 @@ end: UVC_ATTR(uvcg_frame_, dw_frame_interval, dwFrameInterval); -static struct configfs_attribute *uvcg_frame_attrs1[] = { +static struct configfs_attribute *uvcg_frame_attrs[] = { &uvcg_frame_attr_b_frame_index, &uvcg_frame_attr_bm_capabilities, &uvcg_frame_attr_w_width, @@ -1342,32 +1337,12 @@ static struct configfs_attribute *uvcg_frame_attrs1[] = { NULL, }; -static struct configfs_attribute *uvcg_frame_attrs2[] = { - &uvcg_frame_attr_b_frame_index, - &uvcg_frame_attr_bm_capabilities, - &uvcg_frame_attr_w_width, - &uvcg_frame_attr_w_height, - &uvcg_frame_attr_dw_min_bit_rate, - &uvcg_frame_attr_dw_max_bit_rate, - &uvcg_frame_attr_dw_max_video_frame_buffer_size, - &uvcg_frame_attr_dw_default_frame_interval, - &uvcg_frame_attr_dw_frame_interval, - &uvcg_frame_attr_dw_bytes_perline, - NULL, -}; - -static const struct config_item_type uvcg_frame_type1 = { +static const struct config_item_type uvcg_frame_type = { .ct_item_ops = &uvcg_config_item_ops, - .ct_attrs = uvcg_frame_attrs1, + .ct_attrs = uvcg_frame_attrs, .ct_owner = THIS_MODULE, }; -static const struct config_item_type uvcg_frame_type2 = { - .ct_item_ops = &uvcg_config_item_ops, - .ct_attrs = uvcg_frame_attrs2, - .ct_owner = THIS_MODULE, -}; - static struct config_item *uvcg_frame_make(struct config_group *group, const char *name) { @@ -1388,7 +1363,6 @@ static struct config_item *uvcg_frame_make(struct config_group *group, h->frame.dw_max_bit_rate = 55296000; h->frame.dw_max_video_frame_buffer_size = 460800; h->frame.dw_default_frame_interval = 666666; - h->frame.dw_bytes_perline = 0; opts_item = group->cg_item.ci_parent->ci_parent->ci_parent; opts = to_f_uvc_opts(opts_item); @@ -1401,9 +1375,6 @@ static struct config_item *uvcg_frame_make(struct config_group *group, } else if (fmt->type == UVCG_MJPEG) { h->frame.b_descriptor_subtype = UVC_VS_FRAME_MJPEG; h->fmt_type = UVCG_MJPEG; - } else if (fmt->type == UVCG_FRAMEBASED) { - h->frame.b_descriptor_subtype = UVC_VS_FRAME_FRAME_BASED; - h->fmt_type = UVCG_FRAMEBASED; } else { mutex_unlock(&opts->lock); kfree(h); @@ -1412,10 +1383,7 @@ static struct config_item *uvcg_frame_make(struct config_group *group, ++fmt->num_frames; mutex_unlock(&opts->lock); - if (fmt->type == UVCG_FRAMEBASED) - config_item_init_type_name(&h->item, name, &uvcg_frame_type2); - else - config_item_init_type_name(&h->item, name, &uvcg_frame_type1); + config_item_init_type_name(&h->item, name, &uvcg_frame_type); return &h->item; } @@ -1445,6 +1413,9 @@ static void uvcg_format_set_indices(struct config_group *fmt) list_for_each_entry(ci, &fmt->cg_children, ci_entry) { struct uvcg_frame *frm; + if (ci->ci_type != &uvcg_frame_type) + continue; + frm = to_uvcg_frame(ci); frm->frame.b_frame_index = i++; } @@ -1885,260 +1856,6 @@ static const struct uvcg_config_group_type uvcg_mjpeg_grp_type = { .name = "mjpeg", }; -/* ----------------------------------------------------------------------------- - * streaming/framebased/ - */ - -struct uvcg_framebased { - struct uvcg_format fmt; - struct uvc_format_framebased desc; -}; - -static inline struct uvcg_framebased *to_uvcg_framebased(struct config_item *item) -{ - return container_of(to_uvcg_format(item), struct uvcg_framebased, fmt); -} - -static struct configfs_group_operations uvcg_framebased_group_ops = { - .make_item = uvcg_frame_make, - .drop_item = uvcg_frame_drop, -}; - -#define UVCG_FRAMEBASED_ATTR_RO(cname, aname, bits) \ - static ssize_t uvcg_framebased_##cname##_show(struct config_item *item, \ - char *page) \ -{ \ - struct uvcg_framebased *u = to_uvcg_framebased(item); \ - struct f_uvc_opts *opts; \ - struct config_item *opts_item; \ - struct mutex *su_mutex = &u->fmt.group.cg_subsys->su_mutex; \ - int result; \ - \ - mutex_lock(su_mutex); /* for navigating configfs hierarchy */ \ - \ - opts_item = u->fmt.group.cg_item.ci_parent->ci_parent->ci_parent; \ - opts = to_f_uvc_opts(opts_item); \ - \ - mutex_lock(&opts->lock); \ - result = scnprintf(page, PAGE_SIZE, "%u\n", le##bits##_to_cpu(u->desc.aname));\ - mutex_unlock(&opts->lock); \ - \ - mutex_unlock(su_mutex); \ - return result; \ -} \ - \ -UVC_ATTR_RO(uvcg_framebased_, cname, aname) - -#define UVCG_FRAMEBASED_ATTR(cname, aname, bits) \ - static ssize_t uvcg_framebased_##cname##_show(struct config_item *item, \ - char *page) \ -{ \ - struct uvcg_framebased *u = to_uvcg_framebased(item); \ - struct f_uvc_opts *opts; \ - struct config_item *opts_item; \ - struct mutex *su_mutex = &u->fmt.group.cg_subsys->su_mutex; \ - int result; \ - \ - mutex_lock(su_mutex); /* for navigating configfs hierarchy */ \ - \ - opts_item = u->fmt.group.cg_item.ci_parent->ci_parent->ci_parent;\ - opts = to_f_uvc_opts(opts_item); \ - \ - mutex_lock(&opts->lock); \ - result = scnprintf(page, PAGE_SIZE, "%u\n", le##bits##_to_cpu(u->desc.aname));\ - mutex_unlock(&opts->lock); \ - \ - mutex_unlock(su_mutex); \ - return result; \ -} \ - \ -static ssize_t \ -uvcg_framebased_##cname##_store(struct config_item *item, \ - const char *page, size_t len) \ -{ \ - struct uvcg_framebased *u = to_uvcg_framebased(item); \ - struct f_uvc_opts *opts; \ - struct config_item *opts_item; \ - struct mutex *su_mutex = &u->fmt.group.cg_subsys->su_mutex; \ - int ret; \ - u8 num; \ - \ - mutex_lock(su_mutex); /* for navigating configfs hierarchy */ \ - \ - opts_item = u->fmt.group.cg_item.ci_parent->ci_parent->ci_parent;\ - opts = to_f_uvc_opts(opts_item); \ - \ - mutex_lock(&opts->lock); \ - if (u->fmt.linked || opts->refcnt) { \ - ret = -EBUSY; \ - goto end; \ - } \ - \ - ret = kstrtou8(page, 0, &num); \ - if (ret) \ - goto end; \ - \ - if (num > 255) { \ - ret = -EINVAL; \ - goto end; \ - } \ - u->desc.aname = num; \ - ret = len; \ -end: \ - mutex_unlock(&opts->lock); \ - mutex_unlock(su_mutex); \ - return ret; \ -} \ - \ -UVC_ATTR(uvcg_framebased_, cname, aname) - -UVCG_FRAMEBASED_ATTR_RO(b_format_index, bFormatIndex, 8); -UVCG_FRAMEBASED_ATTR_RO(b_bits_per_pixel, bBitsPerPixel, 8); -UVCG_FRAMEBASED_ATTR(b_default_frame_index, bDefaultFrameIndex, 8); -UVCG_FRAMEBASED_ATTR_RO(b_aspect_ratio_x, bAspectRatioX, 8); -UVCG_FRAMEBASED_ATTR_RO(b_aspect_ratio_y, bAspectRatioY, 8); -UVCG_FRAMEBASED_ATTR_RO(bm_interface_flags, bmInterfaceFlags, 8); - -#undef UVCG_FRAMEBASED_ATTR -#undef UVCG_FRAMEBASED_ATTR_RO - -static ssize_t uvcg_framebased_guid_format_show(struct config_item *item, - char *page) -{ - struct uvcg_framebased *ch = to_uvcg_framebased(item); - struct f_uvc_opts *opts; - struct config_item *opts_item; - struct mutex *su_mutex = &ch->fmt.group.cg_subsys->su_mutex; - - mutex_lock(su_mutex); /* for navigating configfs hierarchy */ - - opts_item = ch->fmt.group.cg_item.ci_parent->ci_parent->ci_parent; - opts = to_f_uvc_opts(opts_item); - - mutex_lock(&opts->lock); - memcpy(page, ch->desc.guidFormat, sizeof(ch->desc.guidFormat)); - mutex_unlock(&opts->lock); - - mutex_unlock(su_mutex); - - return sizeof(ch->desc.guidFormat); -} - -static ssize_t uvcg_framebased_guid_format_store(struct config_item *item, - const char *page, size_t len) -{ - struct uvcg_framebased *ch = to_uvcg_framebased(item); - struct f_uvc_opts *opts; - struct config_item *opts_item; - struct mutex *su_mutex = &ch->fmt.group.cg_subsys->su_mutex; - int ret; - - mutex_lock(su_mutex); /* for navigating configfs hierarchy */ - - opts_item = ch->fmt.group.cg_item.ci_parent->ci_parent->ci_parent; - opts = to_f_uvc_opts(opts_item); - - mutex_lock(&opts->lock); - if (ch->fmt.linked || opts->refcnt) { - ret = -EBUSY; - goto end; - } - - memcpy(ch->desc.guidFormat, page, - min(sizeof(ch->desc.guidFormat), len)); - ret = sizeof(ch->desc.guidFormat); - -end: - mutex_unlock(&opts->lock); - mutex_unlock(su_mutex); - return ret; -} - -UVC_ATTR(uvcg_framebased_, guid_format, guidFormat); - - static inline ssize_t -uvcg_framebased_bma_controls_show(struct config_item *item, char *page) -{ - struct uvcg_framebased *u = to_uvcg_framebased(item); - - return uvcg_format_bma_controls_show(&u->fmt, page); -} - - static inline ssize_t -uvcg_framebased_bma_controls_store(struct config_item *item, - const char *page, size_t len) -{ - struct uvcg_framebased *u = to_uvcg_framebased(item); - - return uvcg_format_bma_controls_store(&u->fmt, page, len); -} - -UVC_ATTR(uvcg_framebased_, bma_controls, bmaControls); - -static struct configfs_attribute *uvcg_framebased_attrs[] = { - &uvcg_framebased_attr_b_format_index, - &uvcg_framebased_attr_b_default_frame_index, - &uvcg_framebased_attr_b_bits_per_pixel, - &uvcg_framebased_attr_b_aspect_ratio_x, - &uvcg_framebased_attr_b_aspect_ratio_y, - &uvcg_framebased_attr_bm_interface_flags, - &uvcg_framebased_attr_bma_controls, - &uvcg_framebased_attr_guid_format, - NULL, -}; - -static const struct config_item_type uvcg_framebased_type = { - .ct_item_ops = &uvcg_config_item_ops, - .ct_group_ops = &uvcg_framebased_group_ops, - .ct_attrs = uvcg_framebased_attrs, - .ct_owner = THIS_MODULE, -}; - -static struct config_group *uvcg_framebased_make(struct config_group *group, - const char *name) -{ - static char guid[] = { /*Declear frame based as H264 format*/ - 'H', '2', '6', '4', 0x00, 0x00, 0x10, 0x00, - 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71 - }; - struct uvcg_framebased *h; - - h = kzalloc(sizeof(*h), GFP_KERNEL); - if (!h) - return ERR_PTR(-ENOMEM); - - h->desc.bLength = UVC_DT_FORMAT_FRAMEBASED_SIZE; - h->desc.bDescriptorType = USB_DT_CS_INTERFACE; - h->desc.bDescriptorSubType = UVC_VS_FORMAT_FRAME_BASED; - memcpy(h->desc.guidFormat, guid, sizeof(guid)); - h->desc.bBitsPerPixel = 0; - h->desc.bDefaultFrameIndex = 1; - h->desc.bAspectRatioX = 0; - h->desc.bAspectRatioY = 0; - h->desc.bmInterfaceFlags = 0; - h->desc.bCopyProtect = 0; - h->desc.bVariableSize = 1; - - h->fmt.type = UVCG_FRAMEBASED; - config_group_init_type_name(&h->fmt.group, name, - &uvcg_framebased_type); - - return &h->fmt.group; -} - -static struct configfs_group_operations uvcg_framebased_grp_ops = { - .make_group = uvcg_framebased_make, -}; - -static const struct uvcg_config_group_type uvcg_framebased_grp_type = { - .type = { - .ct_item_ops = &uvcg_config_item_ops, - .ct_group_ops = &uvcg_framebased_grp_ops, - .ct_owner = THIS_MODULE, - }, - .name = "framebased", -}; - /* ----------------------------------------------------------------------------- * streaming/color_matching/default */ @@ -2284,7 +2001,6 @@ static int __uvcg_iter_strm_cls(struct uvcg_streaming_header *h, if (ret) return ret; grp = &f->fmt->group; - j = 0; list_for_each_entry(item, &grp->cg_children, ci_entry) { frm = to_uvcg_frame(item); ret = fun(frm, priv2, priv3, j++, UVCG_FRAME); @@ -2333,11 +2049,6 @@ static int __uvcg_cnt_strm(void *priv1, void *priv2, void *priv3, int n, container_of(fmt, struct uvcg_mjpeg, fmt); *size += sizeof(m->desc); - } else if (fmt->type == UVCG_FRAMEBASED) { - struct uvcg_framebased *f = - container_of(fmt, struct uvcg_framebased, fmt); - - *size += sizeof(f->desc); } else { return -EINVAL; } @@ -2348,11 +2059,6 @@ static int __uvcg_cnt_strm(void *priv1, void *priv2, void *priv3, int n, int sz = sizeof(frm->dw_frame_interval); *size += sizeof(frm->frame); - /* - * framebased has duplicate member with uncompressed and - * mjpeg, so minus it - */ - *size -= sizeof(u32); *size += frm->frame.b_frame_interval_type * sz; } break; @@ -2363,27 +2069,6 @@ static int __uvcg_cnt_strm(void *priv1, void *priv2, void *priv3, int n, return 0; } -static int __uvcg_copy_framebased_desc(void *dest, struct uvcg_frame *frm, - int sz) -{ - struct uvc_frame_framebased *desc = dest; - - desc->bLength = frm->frame.b_length; - desc->bDescriptorType = frm->frame.b_descriptor_type; - desc->bDescriptorSubType = frm->frame.b_descriptor_subtype; - desc->bFrameIndex = frm->frame.b_frame_index; - desc->bmCapabilities = frm->frame.bm_capabilities; - desc->wWidth = frm->frame.w_width; - desc->wHeight = frm->frame.w_height; - desc->dwMinBitRate = frm->frame.dw_min_bit_rate; - desc->dwMaxBitRate = frm->frame.dw_max_bit_rate; - desc->dwDefaultFrameInterval = frm->frame.dw_default_frame_interval; - desc->bFrameIntervalType = frm->frame.b_frame_interval_type; - desc->dwBytesPerLine = frm->frame.dw_bytes_perline; - - return 0; -} - /* * Fill an array of streaming descriptors. * @@ -2438,15 +2123,6 @@ static int __uvcg_fill_strm(void *priv1, void *priv2, void *priv3, int n, m->desc.bNumFrameDescriptors = fmt->num_frames; memcpy(*dest, &m->desc, sizeof(m->desc)); *dest += sizeof(m->desc); - } else if (fmt->type == UVCG_FRAMEBASED) { - struct uvcg_framebased *f = - container_of(fmt, struct uvcg_framebased, - fmt); - - f->desc.bFormatIndex = n + 1; - f->desc.bNumFrameDescriptors = fmt->num_frames; - memcpy(*dest, &f->desc, sizeof(f->desc)); - *dest += sizeof(f->desc); } else { return -EINVAL; } @@ -2456,11 +2132,8 @@ static int __uvcg_fill_strm(void *priv1, void *priv2, void *priv3, int n, struct uvcg_frame *frm = priv1; struct uvc_descriptor_header *h = *dest; - sz = sizeof(frm->frame) - 4; - if (frm->fmt_type != UVCG_FRAMEBASED) - memcpy(*dest, &frm->frame, sz); - else - __uvcg_copy_framebased_desc(*dest, frm, sz); + sz = sizeof(frm->frame); + memcpy(*dest, &frm->frame, sz); *dest += sz; sz = frm->frame.b_frame_interval_type * sizeof(*frm->dw_frame_interval); @@ -2472,9 +2145,6 @@ static int __uvcg_fill_strm(void *priv1, void *priv2, void *priv3, int n, else if (frm->fmt_type == UVCG_MJPEG) h->bLength = UVC_DT_FRAME_MJPEG_SIZE( frm->frame.b_frame_interval_type); - else if (frm->fmt_type == UVCG_FRAMEBASED) - h->bLength = UVC_DT_FRAME_FRAMEBASED_SIZE( - frm->frame.b_frame_interval_type); } break; } @@ -2687,7 +2357,6 @@ static const struct uvcg_config_group_type uvcg_streaming_grp_type = { &uvcg_streaming_header_grp_type, &uvcg_uncompressed_grp_type, &uvcg_mjpeg_grp_type, - &uvcg_framebased_grp_type, &uvcg_color_matching_grp_type, &uvcg_streaming_class_grp_type, NULL, diff --git a/drivers/usb/gadget/function/uvc_v4l2.c b/drivers/usb/gadget/function/uvc_v4l2.c index 49f1f2ad134e..495f0ec663ea 100644 --- a/drivers/usb/gadget/function/uvc_v4l2.c +++ b/drivers/usb/gadget/function/uvc_v4l2.c @@ -58,9 +58,6 @@ struct uvc_format { static struct uvc_format uvc_formats[] = { { 16, V4L2_PIX_FMT_YUYV }, { 0, V4L2_PIX_FMT_MJPEG }, - { 0, V4L2_PIX_FMT_H264 }, - { 12, V4L2_PIX_FMT_YUV420 }, - { 8, V4L2_PIX_FMT_GREY }, }; static int diff --git a/drivers/virt/fsl_hypervisor.c b/drivers/virt/fsl_hypervisor.c index 46ee0a0998b6..fb292f9cf29d 100644 --- a/drivers/virt/fsl_hypervisor.c +++ b/drivers/virt/fsl_hypervisor.c @@ -705,7 +705,7 @@ static const struct file_operations fsl_hv_fops = { .poll = fsl_hv_poll, .read = fsl_hv_read, .unlocked_ioctl = fsl_hv_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = fsl_hv_ioctl, }; static struct miscdevice fsl_hv_misc_dev = { diff --git a/fs/9p/vfs_inode.c b/fs/9p/vfs_inode.c index 4446e83aea7a..ffce168296bd 100644 --- a/fs/9p/vfs_inode.c +++ b/fs/9p/vfs_inode.c @@ -455,7 +455,7 @@ static int v9fs_test_inode(struct inode *inode, void *data) umode = p9mode2unixmode(v9ses, st, &rdev); /* don't match inode of different type */ - if (inode_wrong_type(inode, umode)) + if ((inode->i_mode & S_IFMT) != (umode & S_IFMT)) return 0; /* compare qid details */ @@ -1412,7 +1412,7 @@ int v9fs_refresh_inode(struct p9_fid *fid, struct inode *inode) * Don't update inode if the file type is different */ umode = p9mode2unixmode(v9ses, st, &rdev); - if (inode_wrong_type(inode, umode)) + if ((inode->i_mode & S_IFMT) != (umode & S_IFMT)) goto out; /* diff --git a/fs/9p/vfs_inode_dotl.c b/fs/9p/vfs_inode_dotl.c index 614f23a9d2bc..9795fe0f1ba2 100644 --- a/fs/9p/vfs_inode_dotl.c +++ b/fs/9p/vfs_inode_dotl.c @@ -59,7 +59,7 @@ static int v9fs_test_inode_dotl(struct inode *inode, void *data) struct p9_stat_dotl *st = (struct p9_stat_dotl *)data; /* don't match inode of different type */ - if (inode_wrong_type(inode, st->st_mode)) + if ((inode->i_mode & S_IFMT) != (st->st_mode & S_IFMT)) return 0; if (inode->i_generation != st->st_gen) @@ -924,7 +924,7 @@ int v9fs_refresh_inode_dotl(struct p9_fid *fid, struct inode *inode) /* * Don't update inode if the file type is different */ - if (inode_wrong_type(inode, st->st_mode)) + if ((inode->i_mode & S_IFMT) != (st->st_mode & S_IFMT)) goto out; /* diff --git a/fs/9p/vfs_super.c b/fs/9p/vfs_super.c index c226d876383d..46e58fdf9ba5 100644 --- a/fs/9p/vfs_super.c +++ b/fs/9p/vfs_super.c @@ -80,10 +80,8 @@ v9fs_fill_super(struct super_block *sb, struct v9fs_session_info *v9ses, if (ret) return ret; - if (!v9ses->cache) { - sb->s_bdi->ra_pages = 0; - sb->s_bdi->io_pages = 0; - } + if (v9ses->cache) + sb->s_bdi->ra_pages = VM_READAHEAD_PAGES; sb->s_flags |= SB_ACTIVE | SB_DIRSYNC; if (!v9ses->cache) diff --git a/fs/afs/super.c b/fs/afs/super.c index f432713872e3..554119068ea4 100644 --- a/fs/afs/super.c +++ b/fs/afs/super.c @@ -449,6 +449,7 @@ static int afs_fill_super(struct super_block *sb, struct afs_fs_context *ctx) ret = super_setup_bdi(sb); if (ret) return ret; + sb->s_bdi->ra_pages = VM_READAHEAD_PAGES; /* allocate the root inode and dentry */ if (as->dyn_root) { diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 176ba981f055..660544fc0781 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -3008,6 +3008,7 @@ int open_ctree(struct super_block *sb, sb->s_bdi->congested_fn = btrfs_congested_fn; sb->s_bdi->congested_data = fs_info; sb->s_bdi->capabilities |= BDI_CAP_CGROUP_WRITEBACK; + sb->s_bdi->ra_pages = VM_READAHEAD_PAGES; sb->s_bdi->ra_pages *= btrfs_super_num_devices(disk_super); sb->s_bdi->ra_pages = max(sb->s_bdi->ra_pages, SZ_4M / PAGE_SIZE); diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c index daa0c0467991..e271f1f8c601 100644 --- a/fs/btrfs/super.c +++ b/fs/btrfs/super.c @@ -2322,7 +2322,7 @@ static const struct super_operations btrfs_super_ops = { static const struct file_operations btrfs_ctl_fops = { .open = btrfs_control_open, .unlocked_ioctl = btrfs_control_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = btrfs_control_ioctl, .owner = THIS_MODULE, .llseek = noop_llseek, }; diff --git a/fs/cifs/inode.c b/fs/cifs/inode.c index 932aa65182b3..af0980c720c7 100644 --- a/fs/cifs/inode.c +++ b/fs/cifs/inode.c @@ -420,7 +420,8 @@ int cifs_get_inode_info_unix(struct inode **pinode, } /* if filetype is different, return error */ - if (unlikely(inode_wrong_type(*pinode, fattr.cf_mode))) { + if (unlikely(((*pinode)->i_mode & S_IFMT) != + (fattr.cf_mode & S_IFMT))) { CIFS_I(*pinode)->time = 0; /* force reval */ rc = -ESTALE; goto cgiiu_exit; @@ -979,7 +980,7 @@ cifs_find_inode(struct inode *inode, void *opaque) return 0; /* don't match inode of different type */ - if (inode_wrong_type(inode, fattr->cf_mode)) + if ((inode->i_mode & S_IFMT) != (fattr->cf_mode & S_IFMT)) return 0; /* if it's not a directory or has no dentries, then flag it */ diff --git a/fs/fs-writeback.c b/fs/fs-writeback.c index 963a3ac0e08d..3ec2c16abece 100644 --- a/fs/fs-writeback.c +++ b/fs/fs-writeback.c @@ -2195,7 +2195,7 @@ static int __init start_dirtytime_writeback(void) __initcall(start_dirtytime_writeback); int dirtytime_interval_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret; diff --git a/fs/fuse/Kconfig b/fs/fuse/Kconfig index ab3428492b61..0635cba19971 100644 --- a/fs/fuse/Kconfig +++ b/fs/fuse/Kconfig @@ -8,7 +8,7 @@ config FUSE_FS There's also a companion library: libfuse2. This library is available from the FUSE homepage: - + although chances are your distribution already has that library installed if you've installed the "fuse" package itself. @@ -34,29 +34,7 @@ config VIRTIO_FS select VIRTIO help The Virtio Filesystem allows guests to mount file systems from the - host. + host. If you want to share files between guests or with the host, answer Y - or M. - -config FUSE_DAX - bool "Virtio Filesystem Direct Host Memory Access support" - default y - select INTERVAL_TREE - depends on VIRTIO_FS - depends on FS_DAX - depends on DAX_DRIVER - help - This allows bypassing guest page cache and allows mapping host page - cache directly in guest address space. - - If you want to allow mounting a Virtio Filesystem with the "dax" - option, answer Y. - -config FUSE_BPF - bool "Adds BPF to fuse" - depends on FUSE_FS - depends on BPF - help - Extends FUSE by adding BPF to prefilter calls and potentially pass to a - backing file system + or M. diff --git a/fs/fuse/Makefile b/fs/fuse/Makefile index 7bd922ff8604..6971454a2bdf 100644 --- a/fs/fuse/Makefile +++ b/fs/fuse/Makefile @@ -7,8 +7,6 @@ obj-$(CONFIG_FUSE_FS) += fuse.o obj-$(CONFIG_CUSE) += cuse.o obj-$(CONFIG_VIRTIO_FS) += virtiofs.o -fuse-y := dev.o dir.o file.o inode.o control.o xattr.o acl.o readdir.o passthrough.o -fuse-$(CONFIG_FUSE_DAX) += dax.o -fuse-$(CONFIG_FUSE_BPF) += backing.o - -virtiofs-y := virtio_fs.o +fuse-objs := dev.o dir.o file.o inode.o control.o xattr.o acl.o readdir.o +fuse-objs += passthrough.o +virtiofs-y += virtio_fs.o diff --git a/fs/fuse/backing.c b/fs/fuse/backing.c deleted file mode 100644 index 013a03259f0c..000000000000 --- a/fs/fuse/backing.c +++ /dev/null @@ -1,2546 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * FUSE-BPF: Filesystem in Userspace with BPF - * Copyright (c) 2021 Google LLC - */ - -#include "fuse_i.h" - -#include -#include -#include -#include - -#include "../internal.h" - -#define FUSE_BPF_IOCB_MASK (IOCB_APPEND | IOCB_DSYNC | IOCB_HIPRI | IOCB_NOWAIT | IOCB_SYNC) - -struct fuse_bpf_aio_req { - struct kiocb iocb; - refcount_t ref; - struct kiocb *iocb_orig; -}; - -static struct kmem_cache *fuse_bpf_aio_request_cachep; - -static void fuse_stat_to_attr(struct fuse_conn *fc, struct inode *inode, - struct kstat *stat, struct fuse_attr *attr); - -static void fuse_file_accessed(struct file *dst_file, struct file *src_file) -{ - struct inode *dst_inode; - struct inode *src_inode; - - if (dst_file->f_flags & O_NOATIME) - return; - - dst_inode = file_inode(dst_file); - src_inode = file_inode(src_file); - - if ((!timespec64_equal(&dst_inode->i_mtime, &src_inode->i_mtime) || - !timespec64_equal(&dst_inode->i_ctime, &src_inode->i_ctime))) { - dst_inode->i_mtime = src_inode->i_mtime; - dst_inode->i_ctime = src_inode->i_ctime; - } - - touch_atime(&dst_file->f_path); -} - -struct bpf_prog *fuse_get_bpf_prog(struct file *file) -{ - struct bpf_prog *bpf_prog = ERR_PTR(-EINVAL); - - if (!file || IS_ERR(file)) - return bpf_prog; - /** - * Two ways of getting a bpf prog from another task's fd, since - * bpf_prog_get_type_dev only works with an fd - * - * 1) Duplicate a little of the needed code. Requires access to - * bpf_prog_fops for validation, which is not exported for modules - * 2) Insert the bpf_file object into a fd from the current task - * Stupidly complex, but I think OK, as security checks are not run - * during the existence of the handle - * - * Best would be to upstream 1) into kernel/bpf/syscall.c and export it - * for use here. Failing that, we have to use 2, since fuse must be - * compilable as a module. - */ -#if 0 - if (file->f_op != &bpf_prog_fops) - goto out; - - bpf_prog = file->private_data; - if (bpf_prog->type == BPF_PROG_TYPE_FUSE) - bpf_prog_inc(bpf_prog); - else - bpf_prog = ERR_PTR(-EINVAL); - -#else - { - int task_fd = get_unused_fd_flags(file->f_flags); - - if (task_fd < 0) - goto out; - - fd_install(task_fd, file); - - bpf_prog = bpf_prog_get_type_dev(task_fd, BPF_PROG_TYPE_FUSE, - false); - - /* Close the fd, which also closes the file */ - __close_fd(current->files, task_fd); - file = NULL; - } -#endif - -out: - if (file) - fput(file); - return bpf_prog; -} - -int fuse_open_initialize(struct fuse_bpf_args *fa, struct fuse_open_io *foio, - struct inode *inode, struct file *file, bool isdir) -{ - foio->foi = (struct fuse_open_in) { - .flags = file->f_flags & ~(O_CREAT | O_EXCL | O_NOCTTY), - }; - - foio->foo = (struct fuse_open_out) {0}; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(inode)->nodeid, - .opcode = isdir ? FUSE_OPENDIR : FUSE_OPEN, - .in_numargs = 1, - .out_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(foio->foi), - .value = &foio->foi, - }, - .out_args[0] = (struct fuse_bpf_arg) { - .size = sizeof(foio->foo), - .value = &foio->foo, - }, - }; - - return 0; -} - -int fuse_open_backing(struct fuse_bpf_args *fa, - struct inode *inode, struct file *file, bool isdir) -{ - struct fuse_mount *fm = get_fuse_mount(inode); - const struct fuse_open_in *foi = fa->in_args[0].value; - struct fuse_file *ff; - int retval; - int mask; - struct fuse_dentry *fd = get_fuse_dentry(file->f_path.dentry); - struct file *backing_file; - - ff = fuse_file_alloc(fm); - if (!ff) - return -ENOMEM; - file->private_data = ff; - - switch (foi->flags & O_ACCMODE) { - case O_RDONLY: - mask = MAY_READ; - break; - - case O_WRONLY: - mask = MAY_WRITE; - break; - - case O_RDWR: - mask = MAY_READ | MAY_WRITE; - break; - - default: - return -EINVAL; - } - - retval = inode_permission(get_fuse_inode(inode)->backing_inode, mask); - if (retval) - return retval; - - backing_file = dentry_open(&fd->backing_path, - foi->flags, - current_cred()); - - if (IS_ERR(backing_file)) { - fuse_file_free(ff); - file->private_data = NULL; - return PTR_ERR(backing_file); - } - ff->backing_file = backing_file; - - return 0; -} - -void *fuse_open_finalize(struct fuse_bpf_args *fa, - struct inode *inode, struct file *file, bool isdir) -{ - struct fuse_file *ff = file->private_data; - struct fuse_open_out *foo = fa->out_args[0].value; - - if (ff) { - ff->fh = foo->fh; - ff->nodeid = get_fuse_inode(inode)->nodeid; - } - return 0; -} - -int fuse_create_open_initialize( - struct fuse_bpf_args *fa, struct fuse_create_open_io *fcoio, - struct inode *dir, struct dentry *entry, - struct file *file, unsigned int flags, umode_t mode) -{ - fcoio->fci = (struct fuse_create_in) { - .flags = file->f_flags & ~(O_CREAT | O_EXCL | O_NOCTTY), - .mode = mode, - }; - - fcoio->feo = (struct fuse_entry_out) {0}; - fcoio->foo = (struct fuse_open_out) {0}; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(dir), - .opcode = FUSE_CREATE, - .in_numargs = 2, - .out_numargs = 2, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(fcoio->fci), - .value = &fcoio->fci, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - .out_args[0] = (struct fuse_bpf_arg) { - .size = sizeof(fcoio->feo), - .value = &fcoio->feo, - }, - .out_args[1] = (struct fuse_bpf_arg) { - .size = sizeof(fcoio->foo), - .value = &fcoio->foo, - }, - }; - - return 0; -} - -static int fuse_open_file_backing(struct inode *inode, struct file *file) -{ - struct fuse_mount *fm = get_fuse_mount(inode); - struct dentry *entry = file->f_path.dentry; - struct fuse_dentry *fuse_dentry = get_fuse_dentry(entry); - struct fuse_file *fuse_file; - struct file *backing_file; - - fuse_file = fuse_file_alloc(fm); - if (!fuse_file) - return -ENOMEM; - file->private_data = fuse_file; - - backing_file = dentry_open(&fuse_dentry->backing_path, file->f_flags, - current_cred()); - if (IS_ERR(backing_file)) { - fuse_file_free(fuse_file); - file->private_data = NULL; - return PTR_ERR(backing_file); - } - fuse_file->backing_file = backing_file; - - return 0; -} - -int fuse_create_open_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, - struct file *file, unsigned int flags, umode_t mode) -{ - struct fuse_inode *dir_fuse_inode = get_fuse_inode(dir); - struct fuse_dentry *fuse_entry = get_fuse_dentry(entry); - struct fuse_dentry *dir_fuse_dentry = get_fuse_dentry(entry->d_parent); - struct dentry *backing_dentry = NULL; - struct inode *inode = NULL; - struct dentry *newent; - int err = 0; - const struct fuse_create_in *fci = fa->in_args[0].value; - struct inode *d_inode = entry->d_inode; - u64 target_nodeid = 0; - - if (!dir_fuse_inode || !dir_fuse_dentry) - return -EIO; - - inode_lock_nested(dir_fuse_inode->backing_inode, I_MUTEX_PARENT); - backing_dentry = lookup_one_len(fa->in_args[1].value, - dir_fuse_dentry->backing_path.dentry, - strlen(fa->in_args[1].value)); - inode_unlock(dir_fuse_inode->backing_inode); - - if (IS_ERR(backing_dentry)) - return PTR_ERR(backing_dentry); - - if (d_really_is_positive(backing_dentry)) { - err = -EIO; - goto out; - } - - err = vfs_create(dir_fuse_inode->backing_inode, backing_dentry, - fci->mode, true); - if (err) - goto out; - - if (fuse_entry->backing_path.dentry) - path_put(&fuse_entry->backing_path); - fuse_entry->backing_path = (struct path) { - .mnt = dir_fuse_dentry->backing_path.mnt, - .dentry = backing_dentry, - }; - path_get(&fuse_entry->backing_path); - - if (d_inode) - target_nodeid = get_fuse_inode(d_inode)->nodeid; - - inode = fuse_iget_backing(dir->i_sb, target_nodeid, - fuse_entry->backing_path.dentry->d_inode); - if (!inode) { - err = -EIO; - goto out; - } - - if (get_fuse_inode(inode)->bpf) - bpf_prog_put(get_fuse_inode(inode)->bpf); - get_fuse_inode(inode)->bpf = fuse_entry->bpf; - fuse_entry->bpf = NULL; - - newent = d_splice_alias(inode, entry); - if (IS_ERR(newent)) { - err = PTR_ERR(newent); - goto out; - } - - inode = NULL; - entry = newent ? newent : entry; - err = finish_open(file, entry, fuse_open_file_backing); - -out: - iput(inode); - dput(backing_dentry); - return err; -} - -void *fuse_create_open_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, - struct file *file, unsigned int flags, umode_t mode) -{ - struct fuse_file *ff = file->private_data; - struct fuse_inode *fi = get_fuse_inode(file->f_inode); - struct fuse_entry_out *feo = fa->out_args[0].value; - struct fuse_open_out *foo = fa->out_args[1].value; - - if (fi) - fi->nodeid = feo->nodeid; - if (ff) - ff->fh = foo->fh; - return 0; -} - -int fuse_release_initialize(struct fuse_bpf_args *fa, struct fuse_release_in *fri, - struct inode *inode, struct fuse_file *ff) -{ - /* Always put backing file whatever bpf/userspace says */ - if (ff->backing_file) { - fput(ff->backing_file); - } - - *fri = (struct fuse_release_in) { - .fh = ff->fh, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(inode)->nodeid, - .opcode = S_ISDIR(inode->i_mode) ? FUSE_RELEASEDIR - : FUSE_RELEASE, - .in_numargs = 1, - .in_args[0].size = sizeof(*fri), - .in_args[0].value = fri, - }; - - return 0; -} - -int fuse_release_backing(struct fuse_bpf_args *fa, - struct inode *inode, struct fuse_file *ff) -{ - return 0; -} - -void *fuse_release_finalize(struct fuse_bpf_args *fa, - struct inode *inode, struct fuse_file *ff) -{ - return NULL; -} - -int fuse_flush_initialize(struct fuse_bpf_args *fa, struct fuse_flush_in *ffi, - struct file *file, fl_owner_t id) -{ - struct fuse_file *fuse_file = file->private_data; - - *ffi = (struct fuse_flush_in) { - .fh = fuse_file->fh, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(file->f_inode), - .opcode = FUSE_FLUSH, - .in_numargs = 1, - .in_args[0].size = sizeof(*ffi), - .in_args[0].value = ffi, - .flags = FUSE_BPF_FORCE, - }; - - return 0; -} - -int fuse_flush_backing(struct fuse_bpf_args *fa, struct file *file, fl_owner_t id) -{ - struct fuse_file *fuse_file = file->private_data; - struct file *backing_file = fuse_file->backing_file; - - if (backing_file->f_op->flush) - return backing_file->f_op->flush(backing_file, id); - return 0; -} - -void *fuse_flush_finalize(struct fuse_bpf_args *fa, struct file *file, fl_owner_t id) -{ - return NULL; -} - -int fuse_lseek_initialize(struct fuse_bpf_args *fa, struct fuse_lseek_io *flio, - struct file *file, loff_t offset, int whence) -{ - struct fuse_file *fuse_file = file->private_data; - - flio->fli = (struct fuse_lseek_in) { - .fh = fuse_file->fh, - .offset = offset, - .whence = whence, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(file->f_inode), - .opcode = FUSE_LSEEK, - .in_numargs = 1, - .in_args[0].size = sizeof(flio->fli), - .in_args[0].value = &flio->fli, - .out_numargs = 1, - .out_args[0].size = sizeof(flio->flo), - .out_args[0].value = &flio->flo, - }; - - return 0; -} - -int fuse_lseek_backing(struct fuse_bpf_args *fa, struct file *file, loff_t offset, int whence) -{ - const struct fuse_lseek_in *fli = fa->in_args[0].value; - struct fuse_lseek_out *flo = fa->out_args[0].value; - struct fuse_file *fuse_file = file->private_data; - struct file *backing_file = fuse_file->backing_file; - loff_t ret; - - if (offset == 0) { - if (whence == SEEK_CUR) { - flo->offset = file->f_pos; - return 0; - } - - if (whence == SEEK_SET) { - flo->offset = vfs_setpos(file, 0, 0); - return 0; - } - } - - inode_lock(file->f_inode); - backing_file->f_pos = file->f_pos; - ret = vfs_llseek(backing_file, fli->offset, fli->whence); - - if (!IS_ERR(ERR_PTR(ret))) { - flo->offset = ret; - ret = 0; - } - inode_unlock(file->f_inode); - return ret; -} - -void *fuse_lseek_finalize(struct fuse_bpf_args *fa, struct file *file, loff_t offset, int whence) -{ - struct fuse_lseek_out *flo = fa->out_args[0].value; - - if (!fa->error_in) - file->f_pos = flo->offset; - return ERR_PTR(flo->offset); -} - -int fuse_copy_file_range_initialize(struct fuse_bpf_args *fa, struct fuse_copy_file_range_io *fcf, - struct file *file_in, loff_t pos_in, struct file *file_out, - loff_t pos_out, size_t len, unsigned int flags) -{ - struct fuse_file *fuse_file_in = file_in->private_data; - struct fuse_file *fuse_file_out = file_out->private_data; - - - fcf->fci = (struct fuse_copy_file_range_in) { - .fh_in = fuse_file_in->fh, - .off_in = pos_in, - .nodeid_out = fuse_file_out->nodeid, - .fh_out = fuse_file_out->fh, - .off_out = pos_out, - .len = len, - .flags = flags, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(file_in->f_inode), - .opcode = FUSE_COPY_FILE_RANGE, - .in_numargs = 1, - .in_args[0].size = sizeof(fcf->fci), - .in_args[0].value = &fcf->fci, - .out_numargs = 1, - .out_args[0].size = sizeof(fcf->fwo), - .out_args[0].value = &fcf->fwo, - }; - - return 0; -} - -int fuse_copy_file_range_backing(struct fuse_bpf_args *fa, struct file *file_in, loff_t pos_in, - struct file *file_out, loff_t pos_out, size_t len, - unsigned int flags) -{ - const struct fuse_copy_file_range_in *fci = fa->in_args[0].value; - struct fuse_file *fuse_file_in = file_in->private_data; - struct file *backing_file_in = fuse_file_in->backing_file; - struct fuse_file *fuse_file_out = file_out->private_data; - struct file *backing_file_out = fuse_file_out->backing_file; - - /* TODO: Handle changing of in/out files */ - if (backing_file_out) - return vfs_copy_file_range(backing_file_in, fci->off_in, backing_file_out, - fci->off_out, fci->len, fci->flags); - else - return generic_copy_file_range(file_in, pos_in, file_out, pos_out, len, - flags); -} - -void *fuse_copy_file_range_finalize(struct fuse_bpf_args *fa, struct file *file_in, loff_t pos_in, - struct file *file_out, loff_t pos_out, size_t len, - unsigned int flags) -{ - return NULL; -} - -int fuse_fsync_initialize(struct fuse_bpf_args *fa, struct fuse_fsync_in *ffi, - struct file *file, loff_t start, loff_t end, int datasync) -{ - struct fuse_file *fuse_file = file->private_data; - - *ffi = (struct fuse_fsync_in) { - .fh = fuse_file->fh, - .fsync_flags = datasync ? FUSE_FSYNC_FDATASYNC : 0, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(file->f_inode)->nodeid, - .opcode = FUSE_FSYNC, - .in_numargs = 1, - .in_args[0].size = sizeof(*ffi), - .in_args[0].value = ffi, - .flags = FUSE_BPF_FORCE, - }; - - return 0; -} - -int fuse_fsync_backing(struct fuse_bpf_args *fa, - struct file *file, loff_t start, loff_t end, int datasync) -{ - struct fuse_file *fuse_file = file->private_data; - struct file *backing_file = fuse_file->backing_file; - const struct fuse_fsync_in *ffi = fa->in_args[0].value; - int new_datasync = (ffi->fsync_flags & FUSE_FSYNC_FDATASYNC) ? 1 : 0; - - return vfs_fsync(backing_file, new_datasync); -} - -void *fuse_fsync_finalize(struct fuse_bpf_args *fa, - struct file *file, loff_t start, loff_t end, int datasync) -{ - return NULL; -} - -int fuse_dir_fsync_initialize(struct fuse_bpf_args *fa, struct fuse_fsync_in *ffi, - struct file *file, loff_t start, loff_t end, int datasync) -{ - struct fuse_file *fuse_file = file->private_data; - - *ffi = (struct fuse_fsync_in) { - .fh = fuse_file->fh, - .fsync_flags = datasync ? FUSE_FSYNC_FDATASYNC : 0, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(file->f_inode)->nodeid, - .opcode = FUSE_FSYNCDIR, - .in_numargs = 1, - .in_args[0].size = sizeof(*ffi), - .in_args[0].value = ffi, - .flags = FUSE_BPF_FORCE, - }; - - return 0; -} - -int fuse_getxattr_initialize(struct fuse_bpf_args *fa, - struct fuse_getxattr_io *fgio, - struct dentry *dentry, const char *name, void *value, - size_t size) -{ - *fgio = (struct fuse_getxattr_io) { - .fgi.size = size, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(dentry->d_inode)->nodeid, - .opcode = FUSE_GETXATTR, - .in_numargs = 2, - .out_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(fgio->fgi), - .value = &fgio->fgi, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = strlen(name) + 1, - .value = name, - }, - .flags = size ? FUSE_BPF_OUT_ARGVAR : 0, - .out_args[0].size = size ? size : sizeof(fgio->fgo), - .out_args[0].value = size ? value : &fgio->fgo, - }; - return 0; -} - -int fuse_getxattr_backing(struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name, void *value, - size_t size) -{ - ssize_t ret = vfs_getxattr(get_fuse_dentry(dentry)->backing_path.dentry, - fa->in_args[1].value, value, size); - - if (fa->flags & FUSE_BPF_OUT_ARGVAR) - fa->out_args[0].size = ret; - else - ((struct fuse_getxattr_out *)fa->out_args[0].value)->size = ret; - - return 0; -} - -void *fuse_getxattr_finalize(struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name, void *value, - size_t size) -{ - struct fuse_getxattr_out *fgo; - - if (fa->flags & FUSE_BPF_OUT_ARGVAR) - return ERR_PTR(fa->out_args[0].size); - - fgo = fa->out_args[0].value; - - return ERR_PTR(fgo->size); - -} - -int fuse_listxattr_initialize(struct fuse_bpf_args *fa, - struct fuse_getxattr_io *fgio, - struct dentry *dentry, char *list, size_t size) -{ - *fgio = (struct fuse_getxattr_io){ - .fgi.size = size, - }; - - *fa = (struct fuse_bpf_args){ - .nodeid = get_fuse_inode(dentry->d_inode)->nodeid, - .opcode = FUSE_LISTXATTR, - .in_numargs = 1, - .out_numargs = 1, - .in_args[0] = - (struct fuse_bpf_in_arg){ - .size = sizeof(fgio->fgi), - .value = &fgio->fgi, - }, - .flags = size ? FUSE_BPF_OUT_ARGVAR : 0, - .out_args[0].size = size ? size : sizeof(fgio->fgo), - .out_args[0].value = size ? (void *)list : &fgio->fgo, - }; - - return 0; -} - -int fuse_listxattr_backing(struct fuse_bpf_args *fa, struct dentry *dentry, - char *list, size_t size) -{ - ssize_t ret = - vfs_listxattr(get_fuse_dentry(dentry)->backing_path.dentry, - list, size); - - if (ret < 0) - return ret; - - if (fa->flags & FUSE_BPF_OUT_ARGVAR) - fa->out_args[0].size = ret; - else - ((struct fuse_getxattr_out *)fa->out_args[0].value)->size = ret; - - return ret; -} - -void *fuse_listxattr_finalize(struct fuse_bpf_args *fa, struct dentry *dentry, - char *list, size_t size) -{ - struct fuse_getxattr_out *fgo; - - if (fa->error_in) - return NULL; - - if (fa->flags & FUSE_BPF_OUT_ARGVAR) - return ERR_PTR(fa->out_args[0].size); - - fgo = fa->out_args[0].value; - return ERR_PTR(fgo->size); -} - -int fuse_setxattr_initialize(struct fuse_bpf_args *fa, - struct fuse_setxattr_in *fsxi, - struct dentry *dentry, const char *name, - const void *value, size_t size, int flags) -{ - *fsxi = (struct fuse_setxattr_in) { - .size = size, - .flags = flags, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(dentry->d_inode)->nodeid, - .opcode = FUSE_SETXATTR, - .in_numargs = 3, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(*fsxi), - .value = fsxi, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = strlen(name) + 1, - .value = name, - }, - .in_args[2] = (struct fuse_bpf_in_arg) { - .size = size, - .value = value, - }, - }; - - return 0; -} - -int fuse_setxattr_backing(struct fuse_bpf_args *fa, struct dentry *dentry, - const char *name, const void *value, size_t size, - int flags) -{ - return vfs_setxattr(get_fuse_dentry(dentry)->backing_path.dentry, name, - value, size, flags); -} - -void *fuse_setxattr_finalize(struct fuse_bpf_args *fa, struct dentry *dentry, - const char *name, const void *value, size_t size, - int flags) -{ - return NULL; -} - -int fuse_removexattr_initialize(struct fuse_bpf_args *fa, - struct fuse_dummy_io *unused, - struct dentry *dentry, const char *name) -{ - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(dentry->d_inode)->nodeid, - .opcode = FUSE_REMOVEXATTR, - .in_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = strlen(name) + 1, - .value = name, - }, - }; - - return 0; -} - -int fuse_removexattr_backing(struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name) -{ - struct path *backing_path = - &get_fuse_dentry(dentry)->backing_path; - - /* TODO account for changes of the name by prefilter */ - return vfs_removexattr(backing_path->dentry, name); -} - -void *fuse_removexattr_finalize(struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name) -{ - return NULL; -} - -static inline void fuse_bpf_aio_put(struct fuse_bpf_aio_req *aio_req) -{ - if (refcount_dec_and_test(&aio_req->ref)) - kmem_cache_free(fuse_bpf_aio_request_cachep, aio_req); -} - -static void fuse_bpf_aio_cleanup_handler(struct fuse_bpf_aio_req *aio_req) -{ - struct kiocb *iocb = &aio_req->iocb; - struct kiocb *iocb_orig = aio_req->iocb_orig; - - if (iocb->ki_flags & IOCB_WRITE) { - __sb_writers_acquired(file_inode(iocb->ki_filp)->i_sb, - SB_FREEZE_WRITE); - file_end_write(iocb->ki_filp); - fuse_copyattr(iocb_orig->ki_filp, iocb->ki_filp); - } - iocb_orig->ki_pos = iocb->ki_pos; - fuse_bpf_aio_put(aio_req); -} - -static void fuse_bpf_aio_rw_complete(struct kiocb *iocb, long res, long res2) -{ - struct fuse_bpf_aio_req *aio_req = - container_of(iocb, struct fuse_bpf_aio_req, iocb); - struct kiocb *iocb_orig = aio_req->iocb_orig; - - fuse_bpf_aio_cleanup_handler(aio_req); - iocb_orig->ki_complete(iocb_orig, res, res2); -} - - -int fuse_file_read_iter_initialize( - struct fuse_bpf_args *fa, struct fuse_file_read_iter_io *fri, - struct kiocb *iocb, struct iov_iter *to) -{ - struct file *file = iocb->ki_filp; - struct fuse_file *ff = file->private_data; - - fri->fri = (struct fuse_read_in) { - .fh = ff->fh, - .offset = iocb->ki_pos, - .size = to->count, - }; - - fri->frio = (struct fuse_read_iter_out) { - .ret = fri->fri.size, - }; - - /* TODO we can't assume 'to' is a kvec */ - /* TODO we also can't assume the vector has only one component */ - *fa = (struct fuse_bpf_args) { - .opcode = FUSE_READ, - .nodeid = ff->nodeid, - .in_numargs = 1, - .in_args[0].size = sizeof(fri->fri), - .in_args[0].value = &fri->fri, - .out_numargs = 1, - .out_args[0].size = sizeof(fri->frio), - .out_args[0].value = &fri->frio, - /* - * TODO Design this properly. - * Possible approach: do not pass buf to bpf - * If going to userland, do a deep copy - * For extra credit, do that to/from the vector, rather than - * making an extra copy in the kernel - */ - }; - - return 0; -} - -int fuse_file_read_iter_backing(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *to) -{ - struct fuse_read_iter_out *frio = fa->out_args[0].value; - struct file *file = iocb->ki_filp; - struct fuse_file *ff = file->private_data; - ssize_t ret; - - if (!iov_iter_count(to)) - return 0; - - if ((iocb->ki_flags & IOCB_DIRECT) && - (!ff->backing_file->f_mapping->a_ops || - !ff->backing_file->f_mapping->a_ops->direct_IO)) - return -EINVAL; - - /* TODO This just plain ignores any change to fuse_read_in */ - if (is_sync_kiocb(iocb)) { - ret = vfs_iter_read(ff->backing_file, to, &iocb->ki_pos, - iocb_to_rw_flags(iocb->ki_flags, FUSE_BPF_IOCB_MASK)); - } else { - struct fuse_bpf_aio_req *aio_req; - - ret = -ENOMEM; - aio_req = kmem_cache_zalloc(fuse_bpf_aio_request_cachep, GFP_KERNEL); - if (!aio_req) - goto out; - - aio_req->iocb_orig = iocb; - kiocb_clone(&aio_req->iocb, iocb, ff->backing_file); - aio_req->iocb.ki_complete = fuse_bpf_aio_rw_complete; - refcount_set(&aio_req->ref, 2); - ret = vfs_iocb_iter_read(ff->backing_file, &aio_req->iocb, to); - fuse_bpf_aio_put(aio_req); - if (ret != -EIOCBQUEUED) - fuse_bpf_aio_cleanup_handler(aio_req); - } - - frio->ret = ret; - - /* TODO Need to point value at the buffer for post-modification */ - -out: - fuse_file_accessed(file, ff->backing_file); - - return ret; -} - -void *fuse_file_read_iter_finalize(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *to) -{ - struct fuse_read_iter_out *frio = fa->out_args[0].value; - - return ERR_PTR(frio->ret); -} - -int fuse_file_write_iter_initialize( - struct fuse_bpf_args *fa, struct fuse_file_write_iter_io *fwio, - struct kiocb *iocb, struct iov_iter *from) -{ - struct file *file = iocb->ki_filp; - struct fuse_file *ff = file->private_data; - - *fwio = (struct fuse_file_write_iter_io) { - .fwi.fh = ff->fh, - .fwi.offset = iocb->ki_pos, - .fwi.size = from->count, - }; - - /* TODO we can't assume 'from' is a kvec */ - *fa = (struct fuse_bpf_args) { - .opcode = FUSE_WRITE, - .nodeid = ff->nodeid, - .in_numargs = 2, - .in_args[0].size = sizeof(fwio->fwi), - .in_args[0].value = &fwio->fwi, - .in_args[1].size = fwio->fwi.size, - .in_args[1].value = from->kvec->iov_base, - .out_numargs = 1, - .out_args[0].size = sizeof(fwio->fwio), - .out_args[0].value = &fwio->fwio, - }; - - return 0; -} - -int fuse_file_write_iter_backing(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *from) -{ - struct file *file = iocb->ki_filp; - struct fuse_file *ff = file->private_data; - struct fuse_write_iter_out *fwio = fa->out_args[0].value; - ssize_t ret; - - if (!iov_iter_count(from)) - return 0; - - /* TODO This just plain ignores any change to fuse_write_in */ - /* TODO uint32_t seems smaller than ssize_t.... right? */ - inode_lock(file_inode(file)); - - fuse_copyattr(file, ff->backing_file); - - if (is_sync_kiocb(iocb)) { - file_start_write(ff->backing_file); - ret = vfs_iter_write(ff->backing_file, from, &iocb->ki_pos, - iocb_to_rw_flags(iocb->ki_flags, FUSE_BPF_IOCB_MASK)); - file_end_write(ff->backing_file); - - /* Must reflect change in size of backing file to upper file */ - if (ret > 0) - fuse_copyattr(file, ff->backing_file); - } else { - struct fuse_bpf_aio_req *aio_req; - - ret = -ENOMEM; - aio_req = kmem_cache_zalloc(fuse_bpf_aio_request_cachep, GFP_KERNEL); - if (!aio_req) - goto out; - - file_start_write(ff->backing_file); - __sb_writers_release(file_inode(ff->backing_file)->i_sb, SB_FREEZE_WRITE); - aio_req->iocb_orig = iocb; - kiocb_clone(&aio_req->iocb, iocb, ff->backing_file); - aio_req->iocb.ki_complete = fuse_bpf_aio_rw_complete; - refcount_set(&aio_req->ref, 2); - ret = vfs_iocb_iter_write(ff->backing_file, &aio_req->iocb, from); - fuse_bpf_aio_put(aio_req); - if (ret != -EIOCBQUEUED) - fuse_bpf_aio_cleanup_handler(aio_req); - } - -out: - inode_unlock(file_inode(file)); - fwio->ret = ret; - if (ret < 0) - return ret; - return 0; -} - -void *fuse_file_write_iter_finalize(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *from) -{ - struct fuse_write_iter_out *fwio = fa->out_args[0].value; - - return ERR_PTR(fwio->ret); -} - -long fuse_backing_ioctl(struct file *file, unsigned int command, unsigned long arg, int flags) -{ - struct fuse_file *ff = file->private_data; - long ret; - - if (flags & FUSE_IOCTL_COMPAT) - ret = -ENOTTY; - else - ret = vfs_ioctl(ff->backing_file, command, arg); - - return ret; -} - -int fuse_file_flock_backing(struct file *file, int cmd, struct file_lock *fl) -{ - struct fuse_file *ff = file->private_data; - struct file *backing_file = ff->backing_file; - int error; - - fl->fl_file = backing_file; - if (backing_file->f_op->flock) - error = backing_file->f_op->flock(backing_file, cmd, fl); - else - error = locks_lock_file_wait(backing_file, fl); - return error; -} - -ssize_t fuse_backing_mmap(struct file *file, struct vm_area_struct *vma) -{ - int ret; - struct fuse_file *ff = file->private_data; - struct inode *fuse_inode = file_inode(file); - struct file *backing_file = ff->backing_file; - struct inode *backing_inode = file_inode(backing_file); - - if (!backing_file->f_op->mmap) - return -ENODEV; - - if (WARN_ON(file != vma->vm_file)) - return -EIO; - - get_file(backing_file); - swap(vma->vm_file, backing_file); - fput(backing_file); - ret = call_mmap(vma->vm_file, vma); - if (ret) - return ret; - - if (file->f_flags & O_NOATIME) - return ret; - - if ((!timespec64_equal(&fuse_inode->i_mtime, - &backing_inode->i_mtime) || - !timespec64_equal(&fuse_inode->i_ctime, - &backing_inode->i_ctime))) { - fuse_inode->i_mtime = backing_inode->i_mtime; - fuse_inode->i_ctime = backing_inode->i_ctime; - } - touch_atime(&file->f_path); - - return ret; -} - -int fuse_file_fallocate_initialize(struct fuse_bpf_args *fa, - struct fuse_fallocate_in *ffi, - struct file *file, int mode, loff_t offset, loff_t length) -{ - struct fuse_file *ff = file->private_data; - - *ffi = (struct fuse_fallocate_in) { - .fh = ff->fh, - .offset = offset, - .length = length, - .mode = mode - }; - - *fa = (struct fuse_bpf_args) { - .opcode = FUSE_FALLOCATE, - .nodeid = ff->nodeid, - .in_numargs = 1, - .in_args[0].size = sizeof(*ffi), - .in_args[0].value = ffi, - }; - - return 0; -} - -int fuse_file_fallocate_backing(struct fuse_bpf_args *fa, - struct file *file, int mode, loff_t offset, loff_t length) -{ - const struct fuse_fallocate_in *ffi = fa->in_args[0].value; - struct fuse_file *ff = file->private_data; - - return vfs_fallocate(ff->backing_file, ffi->mode, ffi->offset, - ffi->length); -} - -void *fuse_file_fallocate_finalize(struct fuse_bpf_args *fa, - struct file *file, int mode, loff_t offset, loff_t length) -{ - return NULL; -} - -/******************************************************************************* - * Directory operations after here * - ******************************************************************************/ - -int fuse_lookup_initialize(struct fuse_bpf_args *fa, struct fuse_lookup_io *fli, - struct inode *dir, struct dentry *entry, unsigned int flags) -{ - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(dir)->nodeid, - .opcode = FUSE_LOOKUP, - .in_numargs = 1, - .out_numargs = 2, - .flags = FUSE_BPF_OUT_ARGVAR, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - .out_args[0] = (struct fuse_bpf_arg) { - .size = sizeof(fli->feo), - .value = &fli->feo, - }, - .out_args[1] = (struct fuse_bpf_arg) { - .size = sizeof(fli->feb.out), - .value = &fli->feb.out, - }, - }; - - return 0; -} - -int fuse_lookup_backing(struct fuse_bpf_args *fa, struct inode *dir, - struct dentry *entry, unsigned int flags) -{ - struct fuse_dentry *fuse_entry = get_fuse_dentry(entry); - struct fuse_dentry *dir_fuse_entry = get_fuse_dentry(entry->d_parent); - struct dentry *dir_backing_entry = dir_fuse_entry->backing_path.dentry; - struct inode *dir_backing_inode = dir_backing_entry->d_inode; - struct dentry *backing_entry; - struct fuse_entry_out *feo = (void *)fa->out_args[0].value; - struct kstat stat; - int err; - - inode_lock_nested(dir_backing_inode, I_MUTEX_PARENT); - backing_entry = lookup_one_len(entry->d_name.name, dir_backing_entry, - strlen(entry->d_name.name)); - inode_unlock(dir_backing_inode); - - if (IS_ERR(backing_entry)) - return PTR_ERR(backing_entry); - - fuse_entry->backing_path = (struct path) { - .dentry = backing_entry, - .mnt = mntget(dir_fuse_entry->backing_path.mnt), - }; - - if (d_is_negative(backing_entry)) { - fa->error_in = -ENOENT; - return 0; - } - - err = follow_down(&fuse_entry->backing_path); - if (err) - goto err_out; - - err = vfs_getattr(&fuse_entry->backing_path, &stat, - STATX_BASIC_STATS, 0); - if (err) - goto err_out; - - fuse_stat_to_attr(get_fuse_conn(dir), - backing_entry->d_inode, &stat, &feo->attr); - return 0; - -err_out: - path_put_init(&fuse_entry->backing_path); - return err; -} - -int fuse_handle_backing(struct fuse_entry_bpf *feb, struct inode **backing_inode, - struct path *backing_path) { - switch (feb->out.backing_action) { - case FUSE_ACTION_KEEP: - /* backing inode/path are added in fuse_lookup_backing */ - break; - - case FUSE_ACTION_REMOVE: - iput(*backing_inode); - *backing_inode = NULL; - path_put_init(backing_path); - break; - - case FUSE_ACTION_REPLACE: { - struct file *backing_file = feb->backing_file; - - if (!backing_file) - return -EINVAL; - if (IS_ERR(backing_file)) - return PTR_ERR(backing_file); - - if (backing_inode) - iput(*backing_inode); - *backing_inode = backing_file->f_inode; - ihold(*backing_inode); - - path_put(backing_path); - *backing_path = backing_file->f_path; - path_get(backing_path); - break; - } - - default: - return -EINVAL; - } - - return 0; -} - -int fuse_handle_bpf_prog(struct fuse_entry_bpf *feb, struct inode *parent, - struct bpf_prog **bpf) -{ - struct bpf_prog *new_bpf = NULL; - - switch (feb->out.bpf_action) { - case FUSE_ACTION_KEEP: { - /* Parent isn't presented, but we want to keep - * Don't touch bpf program at all in this case - */ - if (!parent) - return 0; - - new_bpf = get_fuse_inode(parent)->bpf; - if (new_bpf) - bpf_prog_inc(new_bpf); - break; - } - - case FUSE_ACTION_REMOVE: - break; - - case FUSE_ACTION_REPLACE: { - struct file *bpf_file = feb->bpf_file; - - if (!bpf_file) - return -EINVAL; - if (IS_ERR(bpf_file)) - return PTR_ERR(bpf_file); - - new_bpf = fuse_get_bpf_prog(bpf_file); - if (IS_ERR(new_bpf)) - return PTR_ERR(new_bpf); - break; - } - - default: - return -EINVAL; - } - - /* Cannot change existing program */ - if (*bpf) { - if (new_bpf) - bpf_prog_put(new_bpf); - return new_bpf == *bpf ? 0 : -EINVAL; - } - - *bpf = new_bpf; - return 0; -} - -struct dentry *fuse_lookup_finalize(struct fuse_bpf_args *fa, struct inode *dir, - struct dentry *entry, unsigned int flags) -{ - struct fuse_dentry *fuse_entry; - struct dentry *backing_entry; - struct inode *inode = NULL, *backing_inode; - struct inode *entry_inode = entry->d_inode; - struct fuse_entry_out *feo = fa->out_args[0].value; - struct fuse_entry_bpf_out *febo = fa->out_args[1].value; - struct fuse_entry_bpf *feb = container_of(febo, struct fuse_entry_bpf, - out); - int error = -1; - u64 target_nodeid = 0; - struct dentry *ret = NULL; - - fuse_entry = get_fuse_dentry(entry); - if (!fuse_entry) { - ret = ERR_PTR(-EIO); - goto out; - } - - backing_entry = fuse_entry->backing_path.dentry; - if (!backing_entry) { - ret = ERR_PTR(-ENOENT); - goto out; - } - - if (entry_inode) - target_nodeid = get_fuse_inode(entry_inode)->nodeid; - - backing_inode = backing_entry->d_inode; - if (backing_inode) - inode = fuse_iget_backing(dir->i_sb, target_nodeid, - backing_inode); - - error = inode ? - fuse_handle_bpf_prog(feb, dir, &get_fuse_inode(inode)->bpf) : - fuse_handle_bpf_prog(feb, dir, &fuse_entry->bpf); - if (error) { - ret = ERR_PTR(error); - goto out; - } - - if (inode) { - error = fuse_handle_backing(feb, - &get_fuse_inode(inode)->backing_inode, - &fuse_entry->backing_path); - if (error) { - ret = ERR_PTR(error); - goto out; - } - - get_fuse_inode(inode)->nodeid = feo->nodeid; - ret = d_splice_alias(inode, entry); - if (!IS_ERR(ret)) - inode = NULL; - } -out: - iput(inode); - if (feb->backing_file) - fput(feb->backing_file); - return ret; -} - -int fuse_revalidate_backing(struct dentry *entry, unsigned int flags) -{ - struct fuse_dentry *fuse_dentry = get_fuse_dentry(entry); - struct dentry *backing_entry = fuse_dentry->backing_path.dentry; - - spin_lock(&backing_entry->d_lock); - if (d_unhashed(backing_entry)) { - spin_unlock(&backing_entry->d_lock); - return 0; - } - spin_unlock(&backing_entry->d_lock); - - if (unlikely(backing_entry->d_flags & DCACHE_OP_REVALIDATE)) - return backing_entry->d_op->d_revalidate(backing_entry, flags); - return 1; -} - -int fuse_canonical_path_initialize(struct fuse_bpf_args *fa, - struct fuse_dummy_io *fdi, - const struct path *path, - struct path *canonical_path) -{ - fa->opcode = FUSE_CANONICAL_PATH; - return 0; -} - -int fuse_canonical_path_backing(struct fuse_bpf_args *fa, const struct path *path, - struct path *canonical_path) -{ - get_fuse_backing_path(path->dentry, canonical_path); - return 0; -} - -void *fuse_canonical_path_finalize(struct fuse_bpf_args *fa, - const struct path *path, - struct path *canonical_path) -{ - return NULL; -} - -int fuse_mknod_initialize( - struct fuse_bpf_args *fa, struct fuse_mknod_in *fmi, - struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev) -{ - *fmi = (struct fuse_mknod_in) { - .mode = mode, - .rdev = new_encode_dev(rdev), - .umask = current_umask(), - }; - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(dir), - .opcode = FUSE_MKNOD, - .in_numargs = 2, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(*fmi), - .value = fmi, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - }; - - return 0; -} - -int fuse_mknod_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev) -{ - int err = 0; - const struct fuse_mknod_in *fmi = fa->in_args[0].value; - struct fuse_inode *fuse_inode = get_fuse_inode(dir); - struct inode *backing_inode = fuse_inode->backing_inode; - struct path backing_path = {}; - struct inode *inode = NULL; - - //TODO Actually deal with changing the backing entry in mknod - get_fuse_backing_path(entry, &backing_path); - if (!backing_path.dentry) - return -EBADF; - - inode_lock_nested(backing_inode, I_MUTEX_PARENT); - mode = fmi->mode; - if (!IS_POSIXACL(backing_inode)) - mode &= ~fmi->umask; - err = vfs_mknod(backing_inode, backing_path.dentry, - mode, new_decode_dev(fmi->rdev)); - inode_unlock(backing_inode); - if (err) - goto out; - if (d_really_is_negative(backing_path.dentry) || - unlikely(d_unhashed(backing_path.dentry))) { - err = -EINVAL; - /** - * TODO: overlayfs responds to this situation with a - * lookupOneLen. Should we do that too? - */ - goto out; - } - inode = fuse_iget_backing(dir->i_sb, fuse_inode->nodeid, backing_inode); - if (IS_ERR(inode)) { - err = PTR_ERR(inode); - goto out; - } - d_instantiate(entry, inode); -out: - path_put(&backing_path); - return err; -} - -void *fuse_mknod_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev) -{ - return NULL; -} - -int fuse_mkdir_initialize( - struct fuse_bpf_args *fa, struct fuse_mkdir_in *fmi, - struct inode *dir, struct dentry *entry, umode_t mode) -{ - *fmi = (struct fuse_mkdir_in) { - .mode = mode, - .umask = current_umask(), - }; - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(dir), - .opcode = FUSE_MKDIR, - .in_numargs = 2, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(*fmi), - .value = fmi, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - }; - - return 0; -} - -int fuse_mkdir_backing( - struct fuse_bpf_args *fa, - struct inode *dir_inode, struct dentry *entry, umode_t mode) -{ - int err = 0; - const struct fuse_mkdir_in *fmi = fa->in_args[0].value; - struct fuse_inode *dir_fuse_inode = get_fuse_inode(dir_inode); - struct inode *dir_backing_inode = dir_fuse_inode->backing_inode; - struct path backing_path = {}; - struct inode *inode = NULL; - - //TODO Actually deal with changing the backing entry in mkdir - get_fuse_backing_path(entry, &backing_path); - if (!backing_path.dentry) - return -EBADF; - - inode_lock_nested(dir_backing_inode, I_MUTEX_PARENT); - mode = fmi->mode; - if (!IS_POSIXACL(dir_backing_inode)) - mode &= ~fmi->umask; - err = vfs_mkdir(dir_backing_inode, backing_path.dentry, mode); - if (err) - goto out; - if (d_really_is_negative(backing_path.dentry) || - unlikely(d_unhashed(backing_path.dentry))) { - struct dentry *d = lookup_one_len(entry->d_name.name, - backing_path.dentry->d_parent, - entry->d_name.len); - - if (IS_ERR(d)) { - err = PTR_ERR(d); - goto out; - } - dput(backing_path.dentry); - backing_path.dentry = d; - } - inode = fuse_iget_backing(dir_inode->i_sb, 0, - backing_path.dentry->d_inode); - if (IS_ERR(inode)) { - err = PTR_ERR(inode); - goto out; - } - d_instantiate(entry, inode); - if (get_fuse_inode(inode)->bpf) - bpf_prog_put(get_fuse_inode(inode)->bpf); - get_fuse_inode(inode)->bpf = get_fuse_dentry(entry)->bpf; - get_fuse_dentry(entry)->bpf = NULL; -out: - inode_unlock(dir_backing_inode); - path_put(&backing_path); - return err; -} - -void *fuse_mkdir_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode) -{ - return NULL; -} - -int fuse_rmdir_initialize( - struct fuse_bpf_args *fa, struct fuse_dummy_io *dummy, - struct inode *dir, struct dentry *entry) -{ - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(dir), - .opcode = FUSE_RMDIR, - .in_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - }; - - return 0; -} - -int fuse_rmdir_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry) -{ - int err = 0; - struct path backing_path = {}; - struct dentry *backing_parent_dentry; - struct inode *backing_inode; - - /* TODO Actually deal with changing the backing entry in rmdir */ - get_fuse_backing_path(entry, &backing_path); - if (!backing_path.dentry) - return -EBADF; - - /* TODO Not sure if we should reverify like overlayfs, or get inode from d_parent */ - backing_parent_dentry = dget_parent(backing_path.dentry); - backing_inode = d_inode(backing_parent_dentry); - - inode_lock_nested(backing_inode, I_MUTEX_PARENT); - err = vfs_rmdir(backing_inode, backing_path.dentry); - inode_unlock(backing_inode); - - dput(backing_parent_dentry); - if (!err) - d_drop(entry); - path_put(&backing_path); - return err; -} - -void *fuse_rmdir_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry) -{ - return NULL; -} - -static int fuse_rename_backing_common( - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags) -{ - int err = 0; - struct path old_backing_path; - struct path new_backing_path; - struct dentry *old_backing_dir_dentry; - struct dentry *old_backing_dentry; - struct dentry *new_backing_dir_dentry; - struct dentry *new_backing_dentry; - struct dentry *trap = NULL; - struct inode *target_inode; - - //TODO Actually deal with changing anything that isn't a flag - get_fuse_backing_path(oldent, &old_backing_path); - if (!old_backing_path.dentry) - return -EBADF; - get_fuse_backing_path(newent, &new_backing_path); - if (!new_backing_path.dentry) { - /* - * TODO A file being moved from a backing path to another - * backing path which is not yet instrumented with FUSE-BPF. - * This may be slow and should be substituted with something - * more clever. - */ - err = -EXDEV; - goto put_old_path; - } - if (new_backing_path.mnt != old_backing_path.mnt) { - err = -EXDEV; - goto put_new_path; - } - old_backing_dentry = old_backing_path.dentry; - new_backing_dentry = new_backing_path.dentry; - old_backing_dir_dentry = dget_parent(old_backing_dentry); - new_backing_dir_dentry = dget_parent(new_backing_dentry); - target_inode = d_inode(newent); - - trap = lock_rename(old_backing_dir_dentry, new_backing_dir_dentry); - if (trap == old_backing_dentry) { - err = -EINVAL; - goto put_parents; - } - if (trap == new_backing_dentry) { - err = -ENOTEMPTY; - goto put_parents; - } - err = vfs_rename(d_inode(old_backing_dir_dentry), old_backing_dentry, - d_inode(new_backing_dir_dentry), new_backing_dentry, - NULL, flags); - if (err) - goto unlock; - if (target_inode) - fsstack_copy_attr_all(target_inode, - get_fuse_inode(target_inode)->backing_inode); - fsstack_copy_attr_all(d_inode(oldent), d_inode(old_backing_dentry)); -unlock: - unlock_rename(old_backing_dir_dentry, new_backing_dir_dentry); -put_parents: - dput(new_backing_dir_dentry); - dput(old_backing_dir_dentry); -put_new_path: - path_put(&new_backing_path); -put_old_path: - path_put(&old_backing_path); - return err; -} - -int fuse_rename2_initialize(struct fuse_bpf_args *fa, struct fuse_rename2_in *fri, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags) -{ - *fri = (struct fuse_rename2_in) { - .newdir = get_node_id(newdir), - .flags = flags, - }; - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(olddir), - .opcode = FUSE_RENAME2, - .in_numargs = 3, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(*fri), - .value = fri, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = oldent->d_name.len + 1, - .value = oldent->d_name.name, - }, - .in_args[2] = (struct fuse_bpf_in_arg) { - .size = newent->d_name.len + 1, - .value = newent->d_name.name, - }, - }; - - return 0; -} - -int fuse_rename2_backing(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags) -{ - const struct fuse_rename2_in *fri = fa->in_args[0].value; - - /* TODO: deal with changing dirs/ents */ - return fuse_rename_backing_common(olddir, oldent, newdir, newent, fri->flags); -} - -void *fuse_rename2_finalize(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags) -{ - return NULL; -} - -int fuse_rename_initialize(struct fuse_bpf_args *fa, struct fuse_rename_in *fri, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent) -{ - *fri = (struct fuse_rename_in) { - .newdir = get_node_id(newdir), - }; - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(olddir), - .opcode = FUSE_RENAME, - .in_numargs = 3, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(*fri), - .value = fri, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = oldent->d_name.len + 1, - .value = oldent->d_name.name, - }, - .in_args[2] = (struct fuse_bpf_in_arg) { - .size = newent->d_name.len + 1, - .value = newent->d_name.name, - }, - }; - - return 0; -} - -int fuse_rename_backing(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent) -{ - /* TODO: deal with changing dirs/ents */ - return fuse_rename_backing_common(olddir, oldent, newdir, newent, 0); -} - -void *fuse_rename_finalize(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent) -{ - return NULL; -} - -int fuse_unlink_initialize( - struct fuse_bpf_args *fa, struct fuse_dummy_io *dummy, - struct inode *dir, struct dentry *entry) -{ - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(dir), - .opcode = FUSE_UNLINK, - .in_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - }; - - return 0; -} - -int fuse_unlink_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry) -{ - int err = 0; - struct path backing_path = {}; - struct dentry *backing_parent_dentry; - struct inode *backing_inode; - - /* TODO Actually deal with changing the backing entry in unlink */ - get_fuse_backing_path(entry, &backing_path); - if (!backing_path.dentry) - return -EBADF; - - /* TODO Not sure if we should reverify like overlayfs, or get inode from d_parent */ - backing_parent_dentry = dget_parent(backing_path.dentry); - backing_inode = d_inode(backing_parent_dentry); - - inode_lock_nested(backing_inode, I_MUTEX_PARENT); - err = vfs_unlink(backing_inode, backing_path.dentry, NULL); - inode_unlock(backing_inode); - - dput(backing_parent_dentry); - if (!err) - d_drop(entry); - path_put(&backing_path); - return err; -} - -void *fuse_unlink_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry) -{ - return NULL; -} - -int fuse_link_initialize(struct fuse_bpf_args *fa, struct fuse_link_in *fli, - struct dentry *entry, struct inode *dir, - struct dentry *newent) -{ - struct inode *src_inode = entry->d_inode; - - *fli = (struct fuse_link_in){ - .oldnodeid = get_node_id(src_inode), - }; - - fa->opcode = FUSE_LINK; - fa->in_numargs = 2; - fa->in_args[0].size = sizeof(*fli); - fa->in_args[0].value = fli; - fa->in_args[1].size = newent->d_name.len + 1; - fa->in_args[1].value = newent->d_name.name; - - return 0; -} - -int fuse_link_backing(struct fuse_bpf_args *fa, struct dentry *entry, - struct inode *dir, struct dentry *newent) -{ - int err = 0; - struct path backing_old_path = {}; - struct path backing_new_path = {}; - struct dentry *backing_dir_dentry; - struct inode *fuse_new_inode = NULL; - struct fuse_inode *fuse_dir_inode = get_fuse_inode(dir); - struct inode *backing_dir_inode = fuse_dir_inode->backing_inode; - - get_fuse_backing_path(entry, &backing_old_path); - if (!backing_old_path.dentry) - return -EBADF; - - get_fuse_backing_path(newent, &backing_new_path); - if (!backing_new_path.dentry) { - err = -EBADF; - goto err_dst_path; - } - - backing_dir_dentry = dget_parent(backing_new_path.dentry); - backing_dir_inode = d_inode(backing_dir_dentry); - - inode_lock_nested(backing_dir_inode, I_MUTEX_PARENT); - err = vfs_link(backing_old_path.dentry, backing_dir_inode, backing_new_path.dentry, NULL); - inode_unlock(backing_dir_inode); - if (err) - goto out; - - if (d_really_is_negative(backing_new_path.dentry) || - unlikely(d_unhashed(backing_new_path.dentry))) { - err = -EINVAL; - /** - * TODO: overlayfs responds to this situation with a - * lookupOneLen. Should we do that too? - */ - goto out; - } - - fuse_new_inode = fuse_iget_backing(dir->i_sb, fuse_dir_inode->nodeid, backing_dir_inode); - if (IS_ERR(fuse_new_inode)) { - err = PTR_ERR(fuse_new_inode); - goto out; - } - d_instantiate(newent, fuse_new_inode); - -out: - dput(backing_dir_dentry); - path_put(&backing_new_path); -err_dst_path: - path_put(&backing_old_path); - return err; -} - -void *fuse_link_finalize(struct fuse_bpf_args *fa, struct dentry *entry, - struct inode *dir, struct dentry *newent) -{ - return NULL; -} - -int fuse_getattr_initialize(struct fuse_bpf_args *fa, struct fuse_getattr_io *fgio, - const struct dentry *entry, struct kstat *stat, - u32 request_mask, unsigned int flags) -{ - fgio->fgi = (struct fuse_getattr_in) { - .getattr_flags = flags, - .fh = -1, /* TODO is this OK? */ - }; - - fgio->fao = (struct fuse_attr_out) {0}; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(entry->d_inode), - .opcode = FUSE_GETATTR, - .in_numargs = 1, - .out_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(fgio->fgi), - .value = &fgio->fgi, - }, - .out_args[0] = (struct fuse_bpf_arg) { - .size = sizeof(fgio->fao), - .value = &fgio->fao, - }, - }; - - return 0; -} - -static void fuse_stat_to_attr(struct fuse_conn *fc, struct inode *inode, - struct kstat *stat, struct fuse_attr *attr) -{ - unsigned int blkbits; - - /* see the comment in fuse_change_attributes() */ - if (fc->writeback_cache && S_ISREG(inode->i_mode)) { - stat->size = i_size_read(inode); - stat->mtime.tv_sec = inode->i_mtime.tv_sec; - stat->mtime.tv_nsec = inode->i_mtime.tv_nsec; - stat->ctime.tv_sec = inode->i_ctime.tv_sec; - stat->ctime.tv_nsec = inode->i_ctime.tv_nsec; - } - - attr->ino = stat->ino; - attr->mode = (inode->i_mode & S_IFMT) | (stat->mode & 07777); - attr->nlink = stat->nlink; - attr->uid = from_kuid(fc->user_ns, stat->uid); - attr->gid = from_kgid(fc->user_ns, stat->gid); - attr->atime = stat->atime.tv_sec; - attr->atimensec = stat->atime.tv_nsec; - attr->mtime = stat->mtime.tv_sec; - attr->mtimensec = stat->mtime.tv_nsec; - attr->ctime = stat->ctime.tv_sec; - attr->ctimensec = stat->ctime.tv_nsec; - attr->size = stat->size; - attr->blocks = stat->blocks; - - if (stat->blksize != 0) - blkbits = ilog2(stat->blksize); - else - blkbits = inode->i_sb->s_blocksize_bits; - - attr->blksize = 1 << blkbits; -} - -int fuse_getattr_backing(struct fuse_bpf_args *fa, - const struct dentry *entry, struct kstat *stat, - u32 request_mask, unsigned int flags) -{ - struct path *backing_path = - &get_fuse_dentry(entry)->backing_path; - struct inode *backing_inode = backing_path->dentry->d_inode; - struct fuse_attr_out *fao = fa->out_args[0].value; - struct kstat tmp; - int err; - - if (!stat) - stat = &tmp; - - err = vfs_getattr(backing_path, stat, request_mask, flags); - - if (!err) - fuse_stat_to_attr(get_fuse_conn(entry->d_inode), - backing_inode, stat, &fao->attr); - - return err; -} - -void *fuse_getattr_finalize(struct fuse_bpf_args *fa, - const struct dentry *entry, struct kstat *stat, - u32 request_mask, unsigned int flags) -{ - struct fuse_attr_out *outarg = fa->out_args[0].value; - struct inode *inode = entry->d_inode; - u64 attr_version = fuse_get_attr_version(get_fuse_mount(inode)->fc); - int err = 0; - - /* TODO: Ensure this doesn't happen if we had an error getting attrs in - * backing. - */ - err = finalize_attr(inode, outarg, attr_version, stat); - return ERR_PTR(err); -} - -static void fattr_to_iattr(struct fuse_conn *fc, - const struct fuse_setattr_in *arg, - struct iattr *iattr) -{ - unsigned int fvalid = arg->valid; - - if (fvalid & FATTR_MODE) - iattr->ia_valid |= ATTR_MODE, iattr->ia_mode = arg->mode; - if (fvalid & FATTR_UID) { - iattr->ia_valid |= ATTR_UID; - iattr->ia_uid = make_kuid(fc->user_ns, arg->uid); - } - if (fvalid & FATTR_GID) { - iattr->ia_valid |= ATTR_GID; - iattr->ia_gid = make_kgid(fc->user_ns, arg->gid); - } - if (fvalid & FATTR_SIZE) - iattr->ia_valid |= ATTR_SIZE, iattr->ia_size = arg->size; - if (fvalid & FATTR_ATIME) { - iattr->ia_valid |= ATTR_ATIME; - iattr->ia_atime.tv_sec = arg->atime; - iattr->ia_atime.tv_nsec = arg->atimensec; - if (!(fvalid & FATTR_ATIME_NOW)) - iattr->ia_valid |= ATTR_ATIME_SET; - } - if (fvalid & FATTR_MTIME) { - iattr->ia_valid |= ATTR_MTIME; - iattr->ia_mtime.tv_sec = arg->mtime; - iattr->ia_mtime.tv_nsec = arg->mtimensec; - if (!(fvalid & FATTR_MTIME_NOW)) - iattr->ia_valid |= ATTR_MTIME_SET; - } - if (fvalid & FATTR_CTIME) { - iattr->ia_valid |= ATTR_CTIME; - iattr->ia_ctime.tv_sec = arg->ctime; - iattr->ia_ctime.tv_nsec = arg->ctimensec; - } -} - -int fuse_setattr_initialize(struct fuse_bpf_args *fa, struct fuse_setattr_io *fsio, - struct dentry *dentry, struct iattr *attr, struct file *file) -{ - struct fuse_conn *fc = get_fuse_conn(dentry->d_inode); - - *fsio = (struct fuse_setattr_io) {0}; - iattr_to_fattr(fc, attr, &fsio->fsi, true); - - *fa = (struct fuse_bpf_args) { - .opcode = FUSE_SETATTR, - .nodeid = get_node_id(dentry->d_inode), - .in_numargs = 1, - .in_args[0].size = sizeof(fsio->fsi), - .in_args[0].value = &fsio->fsi, - .out_numargs = 1, - .out_args[0].size = sizeof(fsio->fao), - .out_args[0].value = &fsio->fao, - }; - - return 0; -} - -int fuse_setattr_backing(struct fuse_bpf_args *fa, - struct dentry *dentry, struct iattr *attr, struct file *file) -{ - struct fuse_conn *fc = get_fuse_conn(dentry->d_inode); - const struct fuse_setattr_in *fsi = fa->in_args[0].value; - struct iattr new_attr = {0}; - struct path *backing_path = &get_fuse_dentry(dentry)->backing_path; - int res; - - fattr_to_iattr(fc, fsi, &new_attr); - /* TODO: Some info doesn't get saved by the attr->fattr->attr transition - * When we actually allow the bpf to change these, we may have to consider - * the extra flags more, or pass more info into the bpf. Until then we can - * keep everything except for ATTR_FILE, since we'd need a file on the - * lower fs. For what it's worth, neither f2fs nor ext4 make use of that - * even if it is present. - */ - new_attr.ia_valid = attr->ia_valid & ~ATTR_FILE; - inode_lock(d_inode(backing_path->dentry)); - res = notify_change(backing_path->dentry, &new_attr, NULL); - inode_unlock(d_inode(backing_path->dentry)); - - if (res == 0 && (new_attr.ia_valid & ATTR_SIZE)) - i_size_write(dentry->d_inode, new_attr.ia_size); - return res; -} - -void *fuse_setattr_finalize(struct fuse_bpf_args *fa, - struct dentry *dentry, struct iattr *attr, struct file *file) -{ - return NULL; -} - -int fuse_statfs_initialize( - struct fuse_bpf_args *fa, struct fuse_statfs_out *fso, - struct dentry *dentry, struct kstatfs *buf) -{ - *fso = (struct fuse_statfs_out) {0}; - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(d_inode(dentry)), - .opcode = FUSE_STATFS, - .out_numargs = 1, - .out_numargs = 1, - .out_args[0].size = sizeof(fso), - .out_args[0].value = fso, - }; - - return 0; -} - -int fuse_statfs_backing( - struct fuse_bpf_args *fa, - struct dentry *dentry, struct kstatfs *buf) -{ - int err = 0; - struct path backing_path; - struct fuse_statfs_out *fso = fa->out_args[0].value; - - get_fuse_backing_path(dentry, &backing_path); - if (!backing_path.dentry) - return -EBADF; - err = vfs_statfs(&backing_path, buf); - path_put(&backing_path); - buf->f_type = FUSE_SUPER_MAGIC; - - //TODO Provide postfilter opportunity to modify - if (!err) - convert_statfs_to_fuse(&fso->st, buf); - - return err; -} - -void *fuse_statfs_finalize( - struct fuse_bpf_args *fa, - struct dentry *dentry, struct kstatfs *buf) -{ - struct fuse_statfs_out *fso = fa->out_args[0].value; - - if (!fa->error_in) - convert_fuse_statfs(buf, &fso->st); - return NULL; -} - -int fuse_get_link_initialize(struct fuse_bpf_args *fa, struct fuse_dummy_io *unused, - struct inode *inode, struct dentry *dentry, - struct delayed_call *callback, const char **out) -{ - /* - * TODO - * If we want to handle changing these things, we'll need to copy - * the lower fs's data into our own buffer, and provide our own callback - * to free that buffer. - * - * Pre could change the name we're looking at - * postfilter can change the name we return - * - * We ought to only make that buffer if it's been requested, so leaving - * this unimplemented for the moment - */ - *fa = (struct fuse_bpf_args) { - .opcode = FUSE_READLINK, - .nodeid = get_node_id(inode), - .in_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = dentry->d_name.len + 1, - .value = dentry->d_name.name, - }, - /* - * .out_argvar = 1, - * .out_numargs = 1, - * .out_args[0].size = , - * .out_args[0].value = , - */ - }; - - return 0; -} - -int fuse_get_link_backing(struct fuse_bpf_args *fa, - struct inode *inode, struct dentry *dentry, - struct delayed_call *callback, const char **out) -{ - struct path backing_path; - - if (!dentry) { - *out = ERR_PTR(-ECHILD); - return PTR_ERR(*out); - } - - get_fuse_backing_path(dentry, &backing_path); - if (!backing_path.dentry) { - *out = ERR_PTR(-ECHILD); - return PTR_ERR(*out); - } - - /* - * TODO: If we want to do our own thing, copy the data and then call the - * callback - */ - *out = vfs_get_link(backing_path.dentry, callback); - - path_put(&backing_path); - return 0; -} - -void *fuse_get_link_finalize(struct fuse_bpf_args *fa, - struct inode *inode, struct dentry *dentry, - struct delayed_call *callback, const char **out) -{ - return NULL; -} - -int fuse_symlink_initialize( - struct fuse_bpf_args *fa, struct fuse_dummy_io *unused, - struct inode *dir, struct dentry *entry, const char *link, int len) -{ - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(dir), - .opcode = FUSE_SYMLINK, - .in_numargs = 2, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = len, - .value = link, - }, - }; - - return 0; -} - -int fuse_symlink_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, const char *link, int len) -{ - int err = 0; - struct fuse_inode *fuse_inode = get_fuse_inode(dir); - struct inode *backing_inode = fuse_inode->backing_inode; - struct path backing_path = {}; - struct inode *inode = NULL; - - //TODO Actually deal with changing the backing entry in symlink - get_fuse_backing_path(entry, &backing_path); - if (!backing_path.dentry) - return -EBADF; - - inode_lock_nested(backing_inode, I_MUTEX_PARENT); - err = vfs_symlink(backing_inode, backing_path.dentry, link); - inode_unlock(backing_inode); - if (err) - goto out; - if (d_really_is_negative(backing_path.dentry) || - unlikely(d_unhashed(backing_path.dentry))) { - err = -EINVAL; - /** - * TODO: overlayfs responds to this situation with a - * lookupOneLen. Should we do that too? - */ - goto out; - } - inode = fuse_iget_backing(dir->i_sb, fuse_inode->nodeid, backing_inode); - if (IS_ERR(inode)) { - err = PTR_ERR(inode); - goto out; - } - d_instantiate(entry, inode); -out: - path_put(&backing_path); - return err; -} - -void *fuse_symlink_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, const char *link, int len) -{ - return NULL; -} - -int fuse_readdir_initialize(struct fuse_bpf_args *fa, struct fuse_read_io *frio, - struct file *file, struct dir_context *ctx, - bool *force_again, bool *allow_force, bool is_continued) -{ - struct fuse_file *ff = file->private_data; - u8 *page = (u8 *)__get_free_page(GFP_KERNEL); - - if (!page) - return -ENOMEM; - - *fa = (struct fuse_bpf_args) { - .nodeid = ff->nodeid, - .opcode = FUSE_READDIR, - .in_numargs = 1, - .flags = FUSE_BPF_OUT_ARGVAR, - .out_numargs = 2, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(frio->fri), - .value = &frio->fri, - }, - .out_args[0] = (struct fuse_bpf_arg) { - .size = sizeof(frio->fro), - .value = &frio->fro, - }, - .out_args[1] = (struct fuse_bpf_arg) { - .size = PAGE_SIZE, - .value = page, - }, - }; - - frio->fri = (struct fuse_read_in) { - .fh = ff->fh, - .offset = ctx->pos, - .size = PAGE_SIZE, - }; - frio->fro = (struct fuse_read_out) { - .again = 0, - .offset = 0, - }; - *force_again = false; - *allow_force = true; - return 0; -} - -struct extfuse_ctx { - struct dir_context ctx; - u8 *addr; - size_t offset; -}; - -static int filldir(struct dir_context *ctx, const char *name, int namelen, - loff_t offset, u64 ino, unsigned int d_type) -{ - struct extfuse_ctx *ec = container_of(ctx, struct extfuse_ctx, ctx); - struct fuse_dirent *fd = (struct fuse_dirent *) (ec->addr + ec->offset); - - if (ec->offset + sizeof(struct fuse_dirent) + namelen > PAGE_SIZE) - return -ENOMEM; - - *fd = (struct fuse_dirent) { - .ino = ino, - .off = offset, - .namelen = namelen, - .type = d_type, - }; - - memcpy(fd->name, name, namelen); - ec->offset += FUSE_DIRENT_SIZE(fd); - - return 0; -} - -static int parse_dirfile(char *buf, size_t nbytes, struct dir_context *ctx) -{ - while (nbytes >= FUSE_NAME_OFFSET) { - struct fuse_dirent *dirent = (struct fuse_dirent *) buf; - size_t reclen = FUSE_DIRENT_SIZE(dirent); - - if (!dirent->namelen || dirent->namelen > FUSE_NAME_MAX) - return -EIO; - if (reclen > nbytes) - break; - if (memchr(dirent->name, '/', dirent->namelen) != NULL) - return -EIO; - - ctx->pos = dirent->off; - if (!dir_emit(ctx, dirent->name, dirent->namelen, dirent->ino, - dirent->type)) - break; - - buf += reclen; - nbytes -= reclen; - } - - return 0; -} - - -int fuse_readdir_backing(struct fuse_bpf_args *fa, - struct file *file, struct dir_context *ctx, - bool *force_again, bool *allow_force, bool is_continued) -{ - struct fuse_file *ff = file->private_data; - struct file *backing_dir = ff->backing_file; - struct fuse_read_out *fro = fa->out_args[0].value; - struct extfuse_ctx ec; - int err; - - ec = (struct extfuse_ctx) { - .ctx.actor = filldir, - .ctx.pos = ctx->pos, - .addr = fa->out_args[1].value, - }; - - if (!ec.addr) - return -ENOMEM; - - if (!is_continued) - backing_dir->f_pos = file->f_pos; - - err = iterate_dir(backing_dir, &ec.ctx); - if (ec.offset == 0) - *allow_force = false; - fa->out_args[1].size = ec.offset; - - fro->offset = ec.ctx.pos; - fro->again = false; - return err; -} - -void *fuse_readdir_finalize(struct fuse_bpf_args *fa, - struct file *file, struct dir_context *ctx, - bool *force_again, bool *allow_force, bool is_continued) -{ - struct fuse_read_out *fro = fa->out_args[0].value; - struct fuse_file *ff = file->private_data; - struct file *backing_dir = ff->backing_file; - int err = 0; - - err = parse_dirfile(fa->out_args[1].value, fa->out_args[1].size, ctx); - *force_again = !!fro->again; - if (*force_again && !*allow_force) - err = -EINVAL; - - ctx->pos = fro->offset; - backing_dir->f_pos = fro->offset; - - free_page((unsigned long) fa->out_args[1].value); - return ERR_PTR(err); -} - -int fuse_access_initialize(struct fuse_bpf_args *fa, struct fuse_access_in *fai, - struct inode *inode, int mask) -{ - *fai = (struct fuse_access_in) { - .mask = mask, - }; - - *fa = (struct fuse_bpf_args) { - .opcode = FUSE_ACCESS, - .nodeid = get_node_id(inode), - .in_numargs = 1, - .in_args[0].size = sizeof(*fai), - .in_args[0].value = fai, - }; - - return 0; -} - -int fuse_access_backing(struct fuse_bpf_args *fa, struct inode *inode, int mask) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - const struct fuse_access_in *fai = fa->in_args[0].value; - - return inode_permission(/* For mainline: init_user_ns,*/ - fi->backing_inode, fai->mask); -} - -void *fuse_access_finalize(struct fuse_bpf_args *fa, struct inode *inode, int mask) -{ - return NULL; -} - -int __init fuse_bpf_init(void) -{ - fuse_bpf_aio_request_cachep = kmem_cache_create("fuse_bpf_aio_req", - sizeof(struct fuse_bpf_aio_req), - 0, SLAB_HWCACHE_ALIGN, NULL); - if (!fuse_bpf_aio_request_cachep) - return -ENOMEM; - - return 0; -} - -void __exit fuse_bpf_cleanup(void) -{ - kmem_cache_destroy(fuse_bpf_aio_request_cachep); -} - -ssize_t fuse_bpf_simple_request(struct fuse_mount *fm, struct fuse_bpf_args *bpf_args) -{ - int i; - ssize_t res; - struct fuse_args args = { - .nodeid = bpf_args->nodeid, - .opcode = bpf_args->opcode, - .error_in = bpf_args->error_in, - .in_numargs = bpf_args->in_numargs, - .out_numargs = bpf_args->out_numargs, - .force = !!(bpf_args->flags & FUSE_BPF_FORCE), - .out_argvar = !!(bpf_args->flags & FUSE_BPF_OUT_ARGVAR), - }; - - for (i = 0; i < args.in_numargs; ++i) - args.in_args[i] = (struct fuse_in_arg) { - .size = bpf_args->in_args[i].size, - .value = bpf_args->in_args[i].value, - }; - for (i = 0; i < args.out_numargs; ++i) - args.out_args[i] = (struct fuse_arg) { - .size = bpf_args->out_args[i].size, - .value = bpf_args->out_args[i].value, - }; - - res = fuse_simple_request(fm, &args); - - *bpf_args = (struct fuse_bpf_args) { - .nodeid = args.nodeid, - .opcode = args.opcode, - .error_in = args.error_in, - .in_numargs = args.in_numargs, - .out_numargs = args.out_numargs, - }; - if (args.force) - bpf_args->flags |= FUSE_BPF_FORCE; - if (args.out_argvar) - bpf_args->flags |= FUSE_BPF_OUT_ARGVAR; - for (i = 0; i < args.in_numargs; ++i) - bpf_args->in_args[i] = (struct fuse_bpf_in_arg) { - .size = args.in_args[i].size, - .value = args.in_args[i].value, - }; - for (i = 0; i < args.out_numargs; ++i) - bpf_args->out_args[i] = (struct fuse_bpf_arg) { - .size = args.out_args[i].size, - .value = args.out_args[i].value, - }; - return res; -} diff --git a/fs/fuse/control.c b/fs/fuse/control.c index 4aae0e606ba4..7092958c43ed 100644 --- a/fs/fuse/control.c +++ b/fs/fuse/control.c @@ -164,7 +164,6 @@ static ssize_t fuse_conn_congestion_threshold_write(struct file *file, { unsigned val; struct fuse_conn *fc; - struct fuse_mount *fm; ssize_t ret; ret = fuse_conn_limit_write(file, buf, count, ppos, &val, @@ -175,27 +174,18 @@ static ssize_t fuse_conn_congestion_threshold_write(struct file *file, if (!fc) goto out; - down_read(&fc->killsb); spin_lock(&fc->bg_lock); fc->congestion_threshold = val; - - /* - * Get any fuse_mount belonging to this fuse_conn; s_bdi is - * shared between all of them - */ - - if (!list_empty(&fc->mounts)) { - fm = list_first_entry(&fc->mounts, struct fuse_mount, fc_entry); + if (fc->sb) { if (fc->num_background < fc->congestion_threshold) { - clear_bdi_congested(fm->sb->s_bdi, BLK_RW_SYNC); - clear_bdi_congested(fm->sb->s_bdi, BLK_RW_ASYNC); + clear_bdi_congested(fc->sb->s_bdi, BLK_RW_SYNC); + clear_bdi_congested(fc->sb->s_bdi, BLK_RW_ASYNC); } else { - set_bdi_congested(fm->sb->s_bdi, BLK_RW_SYNC); - set_bdi_congested(fm->sb->s_bdi, BLK_RW_ASYNC); + set_bdi_congested(fc->sb->s_bdi, BLK_RW_SYNC); + set_bdi_congested(fc->sb->s_bdi, BLK_RW_ASYNC); } } spin_unlock(&fc->bg_lock); - up_read(&fc->killsb); fuse_conn_put(fc); out: return ret; @@ -328,7 +318,7 @@ void fuse_ctl_remove_conn(struct fuse_conn *fc) drop_nlink(d_inode(fuse_control_sb->s_root)); } -static int fuse_ctl_fill_super(struct super_block *sb, struct fs_context *fsc) +static int fuse_ctl_fill_super(struct super_block *sb, struct fs_context *fctx) { static const struct tree_descr empty_descr = {""}; struct fuse_conn *fc; @@ -354,18 +344,18 @@ static int fuse_ctl_fill_super(struct super_block *sb, struct fs_context *fsc) return 0; } -static int fuse_ctl_get_tree(struct fs_context *fsc) +static int fuse_ctl_get_tree(struct fs_context *fc) { - return get_tree_single(fsc, fuse_ctl_fill_super); + return get_tree_single(fc, fuse_ctl_fill_super); } static const struct fs_context_operations fuse_ctl_context_ops = { .get_tree = fuse_ctl_get_tree, }; -static int fuse_ctl_init_fs_context(struct fs_context *fsc) +static int fuse_ctl_init_fs_context(struct fs_context *fc) { - fsc->ops = &fuse_ctl_context_ops; + fc->ops = &fuse_ctl_context_ops; return 0; } @@ -395,7 +385,7 @@ int __init fuse_ctl_init(void) return register_filesystem(&fuse_ctl_fs_type); } -void fuse_ctl_cleanup(void) +void __exit fuse_ctl_cleanup(void) { unregister_filesystem(&fuse_ctl_fs_type); } diff --git a/fs/fuse/cuse.c b/fs/fuse/cuse.c index a37528b51798..072b68fbf8f4 100644 --- a/fs/fuse/cuse.c +++ b/fs/fuse/cuse.c @@ -57,7 +57,6 @@ struct cuse_conn { struct list_head list; /* linked on cuse_conntbl */ - struct fuse_mount fm; /* Dummy mount referencing fc */ struct fuse_conn fc; /* fuse connection */ struct cdev *cdev; /* associated character device */ struct device *dev; /* device representing @cdev */ @@ -135,7 +134,7 @@ static int cuse_open(struct inode *inode, struct file *file) * Generic permission check is already done against the chrdev * file, proceed to open. */ - rc = fuse_do_open(&cc->fm, 0, file, 0); + rc = fuse_do_open(&cc->fc, 0, file, 0); if (rc) fuse_conn_put(&cc->fc); return rc; @@ -144,10 +143,10 @@ static int cuse_open(struct inode *inode, struct file *file) static int cuse_release(struct inode *inode, struct file *file) { struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; fuse_sync_release(NULL, ff, file->f_flags); - fuse_conn_put(fm->fc); + fuse_conn_put(fc); return 0; } @@ -156,7 +155,7 @@ static long cuse_file_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { struct fuse_file *ff = file->private_data; - struct cuse_conn *cc = fc_to_cc(ff->fm->fc); + struct cuse_conn *cc = fc_to_cc(ff->fc); unsigned int flags = 0; if (cc->unrestricted_ioctl) @@ -169,7 +168,7 @@ static long cuse_file_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { struct fuse_file *ff = file->private_data; - struct cuse_conn *cc = fc_to_cc(ff->fm->fc); + struct cuse_conn *cc = fc_to_cc(ff->fc); unsigned int flags = FUSE_IOCTL_COMPAT; if (cc->unrestricted_ioctl) @@ -314,10 +313,9 @@ struct cuse_init_args { * required data structures for it. Please read the comment at the * top of this file for high level overview. */ -static void cuse_process_init_reply(struct fuse_mount *fm, +static void cuse_process_init_reply(struct fuse_conn *fc, struct fuse_args *args, int error) { - struct fuse_conn *fc = fm->fc; struct cuse_init_args *ia = container_of(args, typeof(*ia), ap.args); struct fuse_args_pages *ap = &ia->ap; struct cuse_conn *cc = fc_to_cc(fc), *pos; @@ -426,7 +424,7 @@ static int cuse_send_init(struct cuse_conn *cc) { int rc; struct page *page; - struct fuse_mount *fm = &cc->fm; + struct fuse_conn *fc = &cc->fc; struct cuse_init_args *ia; struct fuse_args_pages *ap; @@ -453,8 +451,8 @@ static int cuse_send_init(struct cuse_conn *cc) ap->args.out_args[0].size = sizeof(ia->out); ap->args.out_args[0].value = &ia->out; ap->args.out_args[1].size = CUSE_INIT_INFO_MAX; - ap->args.out_argvar = true; - ap->args.out_pages = true; + ap->args.out_argvar = 1; + ap->args.out_pages = 1; ap->num_pages = 1; ap->pages = &ia->page; ap->descs = &ia->desc; @@ -462,7 +460,7 @@ static int cuse_send_init(struct cuse_conn *cc) ia->desc.length = ap->args.out_args[1].size; ap->args.end = cuse_process_init_reply; - rc = fuse_simple_background(fm, &ap->args, GFP_KERNEL); + rc = fuse_simple_background(fc, &ap->args, GFP_KERNEL); if (rc) { kfree(ia); err_free_page: @@ -508,8 +506,7 @@ static int cuse_channel_open(struct inode *inode, struct file *file) * Limit the cuse channel to requests that can * be represented in file->f_cred->user_ns. */ - fuse_conn_init(&cc->fc, &cc->fm, file->f_cred->user_ns, - &fuse_dev_fiq_ops, NULL); + fuse_conn_init(&cc->fc, file->f_cred->user_ns, &fuse_dev_fiq_ops, NULL); fud = fuse_dev_alloc_install(&cc->fc); if (!fud) { diff --git a/fs/fuse/dax.c b/fs/fuse/dax.c deleted file mode 100644 index 2739e218df64..000000000000 --- a/fs/fuse/dax.c +++ /dev/null @@ -1,1366 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dax: direct host memory access - * Copyright (C) 2020 Red Hat, Inc. - */ - -#include "fuse_i.h" - -#include -#include -#include -#include -#include -#include - -/* - * Default memory range size. A power of 2 so it agrees with common FUSE_INIT - * map_alignment values 4KB and 64KB. - */ -#define FUSE_DAX_SHIFT 21 -#define FUSE_DAX_SZ (1 << FUSE_DAX_SHIFT) -#define FUSE_DAX_PAGES (FUSE_DAX_SZ / PAGE_SIZE) - -/* Number of ranges reclaimer will try to free in one invocation */ -#define FUSE_DAX_RECLAIM_CHUNK (10) - -/* - * Dax memory reclaim threshold in percetage of total ranges. When free - * number of free ranges drops below this threshold, reclaim can trigger - * Default is 20% - */ -#define FUSE_DAX_RECLAIM_THRESHOLD (20) - -/** Translation information for file offsets to DAX window offsets */ -struct fuse_dax_mapping { - /* Pointer to inode where this memory range is mapped */ - struct inode *inode; - - /* Will connect in fcd->free_ranges to keep track of free memory */ - struct list_head list; - - /* For interval tree in file/inode */ - struct interval_tree_node itn; - - /* Will connect in fc->busy_ranges to keep track busy memory */ - struct list_head busy_list; - - /** Position in DAX window */ - u64 window_offset; - - /** Length of mapping, in bytes */ - loff_t length; - - /* Is this mapping read-only or read-write */ - bool writable; - - /* reference count when the mapping is used by dax iomap. */ - refcount_t refcnt; -}; - -/* Per-inode dax map */ -struct fuse_inode_dax { - /* Semaphore to protect modifications to the dmap tree */ - struct rw_semaphore sem; - - /* Sorted rb tree of struct fuse_dax_mapping elements */ - struct rb_root_cached tree; - unsigned long nr; -}; - -struct fuse_conn_dax { - /* DAX device */ - struct dax_device *dev; - - /* Lock protecting accessess to members of this structure */ - spinlock_t lock; - - /* List of memory ranges which are busy */ - unsigned long nr_busy_ranges; - struct list_head busy_ranges; - - /* Worker to free up memory ranges */ - struct delayed_work free_work; - - /* Wait queue for a dax range to become free */ - wait_queue_head_t range_waitq; - - /* DAX Window Free Ranges */ - long nr_free_ranges; - struct list_head free_ranges; - - unsigned long nr_ranges; -}; - -static inline struct fuse_dax_mapping * -node_to_dmap(struct interval_tree_node *node) -{ - if (!node) - return NULL; - - return container_of(node, struct fuse_dax_mapping, itn); -} - -static struct fuse_dax_mapping * -alloc_dax_mapping_reclaim(struct fuse_conn_dax *fcd, struct inode *inode); - -static void -__kick_dmap_free_worker(struct fuse_conn_dax *fcd, unsigned long delay_ms) -{ - unsigned long free_threshold; - - /* If number of free ranges are below threshold, start reclaim */ - free_threshold = max_t(unsigned long, fcd->nr_ranges * FUSE_DAX_RECLAIM_THRESHOLD / 100, - 1); - if (fcd->nr_free_ranges < free_threshold) - queue_delayed_work(system_long_wq, &fcd->free_work, - msecs_to_jiffies(delay_ms)); -} - -static void kick_dmap_free_worker(struct fuse_conn_dax *fcd, - unsigned long delay_ms) -{ - spin_lock(&fcd->lock); - __kick_dmap_free_worker(fcd, delay_ms); - spin_unlock(&fcd->lock); -} - -static struct fuse_dax_mapping *alloc_dax_mapping(struct fuse_conn_dax *fcd) -{ - struct fuse_dax_mapping *dmap; - - spin_lock(&fcd->lock); - dmap = list_first_entry_or_null(&fcd->free_ranges, - struct fuse_dax_mapping, list); - if (dmap) { - list_del_init(&dmap->list); - WARN_ON(fcd->nr_free_ranges <= 0); - fcd->nr_free_ranges--; - } - spin_unlock(&fcd->lock); - - kick_dmap_free_worker(fcd, 0); - return dmap; -} - -/* This assumes fcd->lock is held */ -static void __dmap_remove_busy_list(struct fuse_conn_dax *fcd, - struct fuse_dax_mapping *dmap) -{ - list_del_init(&dmap->busy_list); - WARN_ON(fcd->nr_busy_ranges == 0); - fcd->nr_busy_ranges--; -} - -static void dmap_remove_busy_list(struct fuse_conn_dax *fcd, - struct fuse_dax_mapping *dmap) -{ - spin_lock(&fcd->lock); - __dmap_remove_busy_list(fcd, dmap); - spin_unlock(&fcd->lock); -} - -/* This assumes fcd->lock is held */ -static void __dmap_add_to_free_pool(struct fuse_conn_dax *fcd, - struct fuse_dax_mapping *dmap) -{ - list_add_tail(&dmap->list, &fcd->free_ranges); - fcd->nr_free_ranges++; - wake_up(&fcd->range_waitq); -} - -static void dmap_add_to_free_pool(struct fuse_conn_dax *fcd, - struct fuse_dax_mapping *dmap) -{ - /* Return fuse_dax_mapping to free list */ - spin_lock(&fcd->lock); - __dmap_add_to_free_pool(fcd, dmap); - spin_unlock(&fcd->lock); -} - -static int fuse_setup_one_mapping(struct inode *inode, unsigned long start_idx, - struct fuse_dax_mapping *dmap, bool writable, - bool upgrade) -{ - struct fuse_mount *fm = get_fuse_mount(inode); - struct fuse_conn_dax *fcd = fm->fc->dax; - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_setupmapping_in inarg; - loff_t offset = start_idx << FUSE_DAX_SHIFT; - FUSE_ARGS(args); - ssize_t err; - - WARN_ON(fcd->nr_free_ranges < 0); - - /* Ask fuse daemon to setup mapping */ - memset(&inarg, 0, sizeof(inarg)); - inarg.foffset = offset; - inarg.fh = -1; - inarg.moffset = dmap->window_offset; - inarg.len = FUSE_DAX_SZ; - inarg.flags |= FUSE_SETUPMAPPING_FLAG_READ; - if (writable) - inarg.flags |= FUSE_SETUPMAPPING_FLAG_WRITE; - args.opcode = FUSE_SETUPMAPPING; - args.nodeid = fi->nodeid; - args.in_numargs = 1; - args.in_args[0].size = sizeof(inarg); - args.in_args[0].value = &inarg; - err = fuse_simple_request(fm, &args); - if (err < 0) - return err; - dmap->writable = writable; - if (!upgrade) { - /* - * We don't take a refernce on inode. inode is valid right now - * and when inode is going away, cleanup logic should first - * cleanup dmap entries. - */ - dmap->inode = inode; - dmap->itn.start = dmap->itn.last = start_idx; - /* Protected by fi->dax->sem */ - interval_tree_insert(&dmap->itn, &fi->dax->tree); - fi->dax->nr++; - spin_lock(&fcd->lock); - list_add_tail(&dmap->busy_list, &fcd->busy_ranges); - fcd->nr_busy_ranges++; - spin_unlock(&fcd->lock); - } - return 0; -} - -static int fuse_send_removemapping(struct inode *inode, - struct fuse_removemapping_in *inargp, - struct fuse_removemapping_one *remove_one) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_mount *fm = get_fuse_mount(inode); - FUSE_ARGS(args); - - args.opcode = FUSE_REMOVEMAPPING; - args.nodeid = fi->nodeid; - args.in_numargs = 2; - args.in_args[0].size = sizeof(*inargp); - args.in_args[0].value = inargp; - args.in_args[1].size = inargp->count * sizeof(*remove_one); - args.in_args[1].value = remove_one; - return fuse_simple_request(fm, &args); -} - -static int dmap_removemapping_list(struct inode *inode, unsigned int num, - struct list_head *to_remove) -{ - struct fuse_removemapping_one *remove_one, *ptr; - struct fuse_removemapping_in inarg; - struct fuse_dax_mapping *dmap; - int ret, i = 0, nr_alloc; - - nr_alloc = min_t(unsigned int, num, FUSE_REMOVEMAPPING_MAX_ENTRY); - remove_one = kmalloc_array(nr_alloc, sizeof(*remove_one), GFP_NOFS); - if (!remove_one) - return -ENOMEM; - - ptr = remove_one; - list_for_each_entry(dmap, to_remove, list) { - ptr->moffset = dmap->window_offset; - ptr->len = dmap->length; - ptr++; - i++; - num--; - if (i >= nr_alloc || num == 0) { - memset(&inarg, 0, sizeof(inarg)); - inarg.count = i; - ret = fuse_send_removemapping(inode, &inarg, - remove_one); - if (ret) - goto out; - ptr = remove_one; - i = 0; - } - } -out: - kfree(remove_one); - return ret; -} - -/* - * Cleanup dmap entry and add back to free list. This should be called with - * fcd->lock held. - */ -static void dmap_reinit_add_to_free_pool(struct fuse_conn_dax *fcd, - struct fuse_dax_mapping *dmap) -{ - pr_debug("fuse: freeing memory range start_idx=0x%lx end_idx=0x%lx window_offset=0x%llx length=0x%llx\n", - dmap->itn.start, dmap->itn.last, dmap->window_offset, - dmap->length); - __dmap_remove_busy_list(fcd, dmap); - dmap->inode = NULL; - dmap->itn.start = dmap->itn.last = 0; - __dmap_add_to_free_pool(fcd, dmap); -} - -/* - * Free inode dmap entries whose range falls inside [start, end]. - * Does not take any locks. At this point of time it should only be - * called from evict_inode() path where we know all dmap entries can be - * reclaimed. - */ -static void inode_reclaim_dmap_range(struct fuse_conn_dax *fcd, - struct inode *inode, - loff_t start, loff_t end) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_dax_mapping *dmap, *n; - int err, num = 0; - LIST_HEAD(to_remove); - unsigned long start_idx = start >> FUSE_DAX_SHIFT; - unsigned long end_idx = end >> FUSE_DAX_SHIFT; - struct interval_tree_node *node; - - while (1) { - node = interval_tree_iter_first(&fi->dax->tree, start_idx, - end_idx); - if (!node) - break; - dmap = node_to_dmap(node); - /* inode is going away. There should not be any users of dmap */ - WARN_ON(refcount_read(&dmap->refcnt) > 1); - interval_tree_remove(&dmap->itn, &fi->dax->tree); - num++; - list_add(&dmap->list, &to_remove); - } - - /* Nothing to remove */ - if (list_empty(&to_remove)) - return; - - WARN_ON(fi->dax->nr < num); - fi->dax->nr -= num; - err = dmap_removemapping_list(inode, num, &to_remove); - if (err && err != -ENOTCONN) { - pr_warn("Failed to removemappings. start=0x%llx end=0x%llx\n", - start, end); - } - spin_lock(&fcd->lock); - list_for_each_entry_safe(dmap, n, &to_remove, list) { - list_del_init(&dmap->list); - dmap_reinit_add_to_free_pool(fcd, dmap); - } - spin_unlock(&fcd->lock); -} - -static int dmap_removemapping_one(struct inode *inode, - struct fuse_dax_mapping *dmap) -{ - struct fuse_removemapping_one forget_one; - struct fuse_removemapping_in inarg; - - memset(&inarg, 0, sizeof(inarg)); - inarg.count = 1; - memset(&forget_one, 0, sizeof(forget_one)); - forget_one.moffset = dmap->window_offset; - forget_one.len = dmap->length; - - return fuse_send_removemapping(inode, &inarg, &forget_one); -} - -/* - * It is called from evict_inode() and by that time inode is going away. So - * this function does not take any locks like fi->dax->sem for traversing - * that fuse inode interval tree. If that lock is taken then lock validator - * complains of deadlock situation w.r.t fs_reclaim lock. - */ -void fuse_dax_inode_cleanup(struct inode *inode) -{ - struct fuse_conn *fc = get_fuse_conn(inode); - struct fuse_inode *fi = get_fuse_inode(inode); - - /* - * fuse_evict_inode() has already called truncate_inode_pages_final() - * before we arrive here. So we should not have to worry about any - * pages/exception entries still associated with inode. - */ - inode_reclaim_dmap_range(fc->dax, inode, 0, -1); - WARN_ON(fi->dax->nr); -} - -static void fuse_fill_iomap_hole(struct iomap *iomap, loff_t length) -{ - iomap->addr = IOMAP_NULL_ADDR; - iomap->length = length; - iomap->type = IOMAP_HOLE; -} - -static void fuse_fill_iomap(struct inode *inode, loff_t pos, loff_t length, - struct iomap *iomap, struct fuse_dax_mapping *dmap, - unsigned int flags) -{ - loff_t offset, len; - loff_t i_size = i_size_read(inode); - - offset = pos - (dmap->itn.start << FUSE_DAX_SHIFT); - len = min(length, dmap->length - offset); - - /* If length is beyond end of file, truncate further */ - if (pos + len > i_size) - len = i_size - pos; - - if (len > 0) { - iomap->addr = dmap->window_offset + offset; - iomap->length = len; - if (flags & IOMAP_FAULT) - iomap->length = ALIGN(len, PAGE_SIZE); - iomap->type = IOMAP_MAPPED; - /* - * increace refcnt so that reclaim code knows this dmap is in - * use. This assumes fi->dax->sem mutex is held either - * shared/exclusive. - */ - refcount_inc(&dmap->refcnt); - - /* iomap->private should be NULL */ - WARN_ON_ONCE(iomap->private); - iomap->private = dmap; - } else { - /* Mapping beyond end of file is hole */ - fuse_fill_iomap_hole(iomap, length); - } -} - -static int fuse_setup_new_dax_mapping(struct inode *inode, loff_t pos, - loff_t length, unsigned int flags, - struct iomap *iomap) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_conn *fc = get_fuse_conn(inode); - struct fuse_conn_dax *fcd = fc->dax; - struct fuse_dax_mapping *dmap, *alloc_dmap = NULL; - int ret; - bool writable = flags & IOMAP_WRITE; - unsigned long start_idx = pos >> FUSE_DAX_SHIFT; - struct interval_tree_node *node; - - /* - * Can't do inline reclaim in fault path. We call - * dax_layout_busy_page() before we free a range. And - * fuse_wait_dax_page() drops fi->i_mmap_sem lock and requires it. - * In fault path we enter with fi->i_mmap_sem held and can't drop - * it. Also in fault path we hold fi->i_mmap_sem shared and not - * exclusive, so that creates further issues with fuse_wait_dax_page(). - * Hence return -EAGAIN and fuse_dax_fault() will wait for a memory - * range to become free and retry. - */ - if (flags & IOMAP_FAULT) { - alloc_dmap = alloc_dax_mapping(fcd); - if (!alloc_dmap) - return -EAGAIN; - } else { - alloc_dmap = alloc_dax_mapping_reclaim(fcd, inode); - if (IS_ERR(alloc_dmap)) - return PTR_ERR(alloc_dmap); - } - - /* If we are here, we should have memory allocated */ - if (WARN_ON(!alloc_dmap)) - return -EIO; - - /* - * Take write lock so that only one caller can try to setup mapping - * and other waits. - */ - down_write(&fi->dax->sem); - /* - * We dropped lock. Check again if somebody else setup - * mapping already. - */ - node = interval_tree_iter_first(&fi->dax->tree, start_idx, start_idx); - if (node) { - dmap = node_to_dmap(node); - fuse_fill_iomap(inode, pos, length, iomap, dmap, flags); - dmap_add_to_free_pool(fcd, alloc_dmap); - up_write(&fi->dax->sem); - return 0; - } - - /* Setup one mapping */ - ret = fuse_setup_one_mapping(inode, pos >> FUSE_DAX_SHIFT, alloc_dmap, - writable, false); - if (ret < 0) { - dmap_add_to_free_pool(fcd, alloc_dmap); - up_write(&fi->dax->sem); - return ret; - } - fuse_fill_iomap(inode, pos, length, iomap, alloc_dmap, flags); - up_write(&fi->dax->sem); - return 0; -} - -static int fuse_upgrade_dax_mapping(struct inode *inode, loff_t pos, - loff_t length, unsigned int flags, - struct iomap *iomap) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_dax_mapping *dmap; - int ret; - unsigned long idx = pos >> FUSE_DAX_SHIFT; - struct interval_tree_node *node; - - /* - * Take exclusive lock so that only one caller can try to setup - * mapping and others wait. - */ - down_write(&fi->dax->sem); - node = interval_tree_iter_first(&fi->dax->tree, idx, idx); - - /* We are holding either inode lock or i_mmap_sem, and that should - * ensure that dmap can't be truncated. We are holding a reference - * on dmap and that should make sure it can't be reclaimed. So dmap - * should still be there in tree despite the fact we dropped and - * re-acquired the fi->dax->sem lock. - */ - ret = -EIO; - if (WARN_ON(!node)) - goto out_err; - - dmap = node_to_dmap(node); - - /* We took an extra reference on dmap to make sure its not reclaimd. - * Now we hold fi->dax->sem lock and that reference is not needed - * anymore. Drop it. - */ - if (refcount_dec_and_test(&dmap->refcnt)) { - /* refcount should not hit 0. This object only goes - * away when fuse connection goes away - */ - WARN_ON_ONCE(1); - } - - /* Maybe another thread already upgraded mapping while we were not - * holding lock. - */ - if (dmap->writable) { - ret = 0; - goto out_fill_iomap; - } - - ret = fuse_setup_one_mapping(inode, pos >> FUSE_DAX_SHIFT, dmap, true, - true); - if (ret < 0) - goto out_err; -out_fill_iomap: - fuse_fill_iomap(inode, pos, length, iomap, dmap, flags); -out_err: - up_write(&fi->dax->sem); - return ret; -} - -/* This is just for DAX and the mapping is ephemeral, do not use it for other - * purposes since there is no block device with a permanent mapping. - */ -static int fuse_iomap_begin(struct inode *inode, loff_t pos, loff_t length, - unsigned int flags, struct iomap *iomap, - struct iomap *srcmap) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_conn *fc = get_fuse_conn(inode); - struct fuse_dax_mapping *dmap; - bool writable = flags & IOMAP_WRITE; - unsigned long start_idx = pos >> FUSE_DAX_SHIFT; - struct interval_tree_node *node; - - /* We don't support FIEMAP */ - if (WARN_ON(flags & IOMAP_REPORT)) - return -EIO; - - iomap->offset = pos; - iomap->flags = 0; - iomap->bdev = NULL; - iomap->dax_dev = fc->dax->dev; - - /* - * Both read/write and mmap path can race here. So we need something - * to make sure if we are setting up mapping, then other path waits - * - * For now, use a semaphore for this. It probably needs to be - * optimized later. - */ - down_read(&fi->dax->sem); - node = interval_tree_iter_first(&fi->dax->tree, start_idx, start_idx); - if (node) { - dmap = node_to_dmap(node); - if (writable && !dmap->writable) { - /* Upgrade read-only mapping to read-write. This will - * require exclusive fi->dax->sem lock as we don't want - * two threads to be trying to this simultaneously - * for same dmap. So drop shared lock and acquire - * exclusive lock. - * - * Before dropping fi->dax->sem lock, take reference - * on dmap so that its not freed by range reclaim. - */ - refcount_inc(&dmap->refcnt); - up_read(&fi->dax->sem); - pr_debug("%s: Upgrading mapping at offset 0x%llx length 0x%llx\n", - __func__, pos, length); - return fuse_upgrade_dax_mapping(inode, pos, length, - flags, iomap); - } else { - fuse_fill_iomap(inode, pos, length, iomap, dmap, flags); - up_read(&fi->dax->sem); - return 0; - } - } else { - up_read(&fi->dax->sem); - pr_debug("%s: no mapping at offset 0x%llx length 0x%llx\n", - __func__, pos, length); - if (pos >= i_size_read(inode)) - goto iomap_hole; - - return fuse_setup_new_dax_mapping(inode, pos, length, flags, - iomap); - } - - /* - * If read beyond end of file happnes, fs code seems to return - * it as hole - */ -iomap_hole: - fuse_fill_iomap_hole(iomap, length); - pr_debug("%s returning hole mapping. pos=0x%llx length_asked=0x%llx length_returned=0x%llx\n", - __func__, pos, length, iomap->length); - return 0; -} - -static int fuse_iomap_end(struct inode *inode, loff_t pos, loff_t length, - ssize_t written, unsigned int flags, - struct iomap *iomap) -{ - struct fuse_dax_mapping *dmap = iomap->private; - - if (dmap) { - if (refcount_dec_and_test(&dmap->refcnt)) { - /* refcount should not hit 0. This object only goes - * away when fuse connection goes away - */ - WARN_ON_ONCE(1); - } - } - - /* DAX writes beyond end-of-file aren't handled using iomap, so the - * file size is unchanged and there is nothing to do here. - */ - return 0; -} - -static const struct iomap_ops fuse_iomap_ops = { - .iomap_begin = fuse_iomap_begin, - .iomap_end = fuse_iomap_end, -}; - -static void fuse_wait_dax_page(struct inode *inode) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - - up_write(&fi->i_mmap_sem); - schedule(); - down_write(&fi->i_mmap_sem); -} - -/* Should be called with fi->i_mmap_sem lock held exclusively */ -static int __fuse_dax_break_layouts(struct inode *inode, bool *retry, - loff_t start, loff_t end) -{ - struct page *page; - - page = dax_layout_busy_page_range(inode->i_mapping, start, end); - if (!page) - return 0; - - *retry = true; - return ___wait_var_event(&page->_refcount, - atomic_read(&page->_refcount) == 1, TASK_INTERRUPTIBLE, - 0, 0, fuse_wait_dax_page(inode)); -} - -/* dmap_end == 0 leads to unmapping of whole file */ -int fuse_dax_break_layouts(struct inode *inode, u64 dmap_start, - u64 dmap_end) -{ - bool retry; - int ret; - - do { - retry = false; - ret = __fuse_dax_break_layouts(inode, &retry, dmap_start, - dmap_end); - } while (ret == 0 && retry); - - return ret; -} - -ssize_t fuse_dax_read_iter(struct kiocb *iocb, struct iov_iter *to) -{ - struct inode *inode = file_inode(iocb->ki_filp); - ssize_t ret; - - if (iocb->ki_flags & IOCB_NOWAIT) { - if (!inode_trylock_shared(inode)) - return -EAGAIN; - } else { - inode_lock_shared(inode); - } - - ret = dax_iomap_rw(iocb, to, &fuse_iomap_ops); - inode_unlock_shared(inode); - - /* TODO file_accessed(iocb->f_filp) */ - return ret; -} - -static bool file_extending_write(struct kiocb *iocb, struct iov_iter *from) -{ - struct inode *inode = file_inode(iocb->ki_filp); - - return (iov_iter_rw(from) == WRITE && - ((iocb->ki_pos) >= i_size_read(inode) || - (iocb->ki_pos + iov_iter_count(from) > i_size_read(inode)))); -} - -static ssize_t fuse_dax_direct_write(struct kiocb *iocb, struct iov_iter *from) -{ - struct inode *inode = file_inode(iocb->ki_filp); - struct fuse_io_priv io = FUSE_IO_PRIV_SYNC(iocb); - ssize_t ret; - - ret = fuse_direct_io(&io, from, &iocb->ki_pos, FUSE_DIO_WRITE); - if (ret < 0) - return ret; - - fuse_invalidate_attr(inode); - fuse_write_update_size(inode, iocb->ki_pos); - return ret; -} - -ssize_t fuse_dax_write_iter(struct kiocb *iocb, struct iov_iter *from) -{ - struct inode *inode = file_inode(iocb->ki_filp); - ssize_t ret; - - if (iocb->ki_flags & IOCB_NOWAIT) { - if (!inode_trylock(inode)) - return -EAGAIN; - } else { - inode_lock(inode); - } - - ret = generic_write_checks(iocb, from); - if (ret <= 0) - goto out; - - ret = file_remove_privs(iocb->ki_filp); - if (ret) - goto out; - /* TODO file_update_time() but we don't want metadata I/O */ - - /* Do not use dax for file extending writes as write and on - * disk i_size increase are not atomic otherwise. - */ - if (file_extending_write(iocb, from)) - ret = fuse_dax_direct_write(iocb, from); - else - ret = dax_iomap_rw(iocb, from, &fuse_iomap_ops); - -out: - inode_unlock(inode); - - if (ret > 0) - ret = generic_write_sync(iocb, ret); - return ret; -} - -static int fuse_dax_writepages(struct address_space *mapping, - struct writeback_control *wbc) -{ - - struct inode *inode = mapping->host; - struct fuse_conn *fc = get_fuse_conn(inode); - - return dax_writeback_mapping_range(mapping, fc->dax->dev, wbc); -} - -static vm_fault_t __fuse_dax_fault(struct vm_fault *vmf, - enum page_entry_size pe_size, bool write) -{ - vm_fault_t ret; - struct inode *inode = file_inode(vmf->vma->vm_file); - struct super_block *sb = inode->i_sb; - pfn_t pfn; - int error = 0; - struct fuse_conn *fc = get_fuse_conn(inode); - struct fuse_conn_dax *fcd = fc->dax; - bool retry = false; - - if (write) - sb_start_pagefault(sb); -retry: - if (retry && !(fcd->nr_free_ranges > 0)) - wait_event(fcd->range_waitq, (fcd->nr_free_ranges > 0)); - - /* - * We need to serialize against not only truncate but also against - * fuse dax memory range reclaim. While a range is being reclaimed, - * we do not want any read/write/mmap to make progress and try - * to populate page cache or access memory we are trying to free. - */ - down_read(&get_fuse_inode(inode)->i_mmap_sem); - ret = dax_iomap_fault(vmf, pe_size, &pfn, &error, &fuse_iomap_ops); - if ((ret & VM_FAULT_ERROR) && error == -EAGAIN) { - error = 0; - retry = true; - up_read(&get_fuse_inode(inode)->i_mmap_sem); - goto retry; - } - - if (ret & VM_FAULT_NEEDDSYNC) - ret = dax_finish_sync_fault(vmf, pe_size, pfn); - up_read(&get_fuse_inode(inode)->i_mmap_sem); - - if (write) - sb_end_pagefault(sb); - - return ret; -} - -static vm_fault_t fuse_dax_fault(struct vm_fault *vmf) -{ - return __fuse_dax_fault(vmf, PE_SIZE_PTE, - vmf->flags & FAULT_FLAG_WRITE); -} - -static vm_fault_t fuse_dax_huge_fault(struct vm_fault *vmf, - enum page_entry_size pe_size) -{ - return __fuse_dax_fault(vmf, pe_size, vmf->flags & FAULT_FLAG_WRITE); -} - -static vm_fault_t fuse_dax_page_mkwrite(struct vm_fault *vmf) -{ - return __fuse_dax_fault(vmf, PE_SIZE_PTE, true); -} - -static vm_fault_t fuse_dax_pfn_mkwrite(struct vm_fault *vmf) -{ - return __fuse_dax_fault(vmf, PE_SIZE_PTE, true); -} - -static const struct vm_operations_struct fuse_dax_vm_ops = { - .fault = fuse_dax_fault, - .huge_fault = fuse_dax_huge_fault, - .page_mkwrite = fuse_dax_page_mkwrite, - .pfn_mkwrite = fuse_dax_pfn_mkwrite, -}; - -int fuse_dax_mmap(struct file *file, struct vm_area_struct *vma) -{ - file_accessed(file); - vma->vm_ops = &fuse_dax_vm_ops; - vma->vm_flags |= VM_MIXEDMAP | VM_HUGEPAGE; - return 0; -} - -static int dmap_writeback_invalidate(struct inode *inode, - struct fuse_dax_mapping *dmap) -{ - int ret; - loff_t start_pos = dmap->itn.start << FUSE_DAX_SHIFT; - loff_t end_pos = (start_pos + FUSE_DAX_SZ - 1); - - ret = filemap_fdatawrite_range(inode->i_mapping, start_pos, end_pos); - if (ret) { - pr_debug("fuse: filemap_fdatawrite_range() failed. err=%d start_pos=0x%llx, end_pos=0x%llx\n", - ret, start_pos, end_pos); - return ret; - } - - ret = invalidate_inode_pages2_range(inode->i_mapping, - start_pos >> PAGE_SHIFT, - end_pos >> PAGE_SHIFT); - if (ret) - pr_debug("fuse: invalidate_inode_pages2_range() failed err=%d\n", - ret); - - return ret; -} - -static int reclaim_one_dmap_locked(struct inode *inode, - struct fuse_dax_mapping *dmap) -{ - int ret; - struct fuse_inode *fi = get_fuse_inode(inode); - - /* - * igrab() was done to make sure inode won't go under us, and this - * further avoids the race with evict(). - */ - ret = dmap_writeback_invalidate(inode, dmap); - if (ret) - return ret; - - /* Remove dax mapping from inode interval tree now */ - interval_tree_remove(&dmap->itn, &fi->dax->tree); - fi->dax->nr--; - - /* It is possible that umount/shutdown has killed the fuse connection - * and worker thread is trying to reclaim memory in parallel. Don't - * warn in that case. - */ - ret = dmap_removemapping_one(inode, dmap); - if (ret && ret != -ENOTCONN) { - pr_warn("Failed to remove mapping. offset=0x%llx len=0x%llx ret=%d\n", - dmap->window_offset, dmap->length, ret); - } - return 0; -} - -/* Find first mapped dmap for an inode and return file offset. Caller needs - * to hold fi->dax->sem lock either shared or exclusive. - */ -static struct fuse_dax_mapping *inode_lookup_first_dmap(struct inode *inode) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_dax_mapping *dmap; - struct interval_tree_node *node; - - for (node = interval_tree_iter_first(&fi->dax->tree, 0, -1); node; - node = interval_tree_iter_next(node, 0, -1)) { - dmap = node_to_dmap(node); - /* still in use. */ - if (refcount_read(&dmap->refcnt) > 1) - continue; - - return dmap; - } - - return NULL; -} - -/* - * Find first mapping in the tree and free it and return it. Do not add - * it back to free pool. - */ -static struct fuse_dax_mapping * -inode_inline_reclaim_one_dmap(struct fuse_conn_dax *fcd, struct inode *inode, - bool *retry) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_dax_mapping *dmap; - u64 dmap_start, dmap_end; - unsigned long start_idx; - int ret; - struct interval_tree_node *node; - - down_write(&fi->i_mmap_sem); - - /* Lookup a dmap and corresponding file offset to reclaim. */ - down_read(&fi->dax->sem); - dmap = inode_lookup_first_dmap(inode); - if (dmap) { - start_idx = dmap->itn.start; - dmap_start = start_idx << FUSE_DAX_SHIFT; - dmap_end = dmap_start + FUSE_DAX_SZ - 1; - } - up_read(&fi->dax->sem); - - if (!dmap) - goto out_mmap_sem; - /* - * Make sure there are no references to inode pages using - * get_user_pages() - */ - ret = fuse_dax_break_layouts(inode, dmap_start, dmap_end); - if (ret) { - pr_debug("fuse: fuse_dax_break_layouts() failed. err=%d\n", - ret); - dmap = ERR_PTR(ret); - goto out_mmap_sem; - } - - down_write(&fi->dax->sem); - node = interval_tree_iter_first(&fi->dax->tree, start_idx, start_idx); - /* Range already got reclaimed by somebody else */ - if (!node) { - if (retry) - *retry = true; - goto out_write_dmap_sem; - } - - dmap = node_to_dmap(node); - /* still in use. */ - if (refcount_read(&dmap->refcnt) > 1) { - dmap = NULL; - if (retry) - *retry = true; - goto out_write_dmap_sem; - } - - ret = reclaim_one_dmap_locked(inode, dmap); - if (ret < 0) { - dmap = ERR_PTR(ret); - goto out_write_dmap_sem; - } - - /* Clean up dmap. Do not add back to free list */ - dmap_remove_busy_list(fcd, dmap); - dmap->inode = NULL; - dmap->itn.start = dmap->itn.last = 0; - - pr_debug("fuse: %s: inline reclaimed memory range. inode=%p, window_offset=0x%llx, length=0x%llx\n", - __func__, inode, dmap->window_offset, dmap->length); - -out_write_dmap_sem: - up_write(&fi->dax->sem); -out_mmap_sem: - up_write(&fi->i_mmap_sem); - return dmap; -} - -static struct fuse_dax_mapping * -alloc_dax_mapping_reclaim(struct fuse_conn_dax *fcd, struct inode *inode) -{ - struct fuse_dax_mapping *dmap; - struct fuse_inode *fi = get_fuse_inode(inode); - - while (1) { - bool retry = false; - - dmap = alloc_dax_mapping(fcd); - if (dmap) - return dmap; - - dmap = inode_inline_reclaim_one_dmap(fcd, inode, &retry); - /* - * Either we got a mapping or it is an error, return in both - * the cases. - */ - if (dmap) - return dmap; - - /* If we could not reclaim a mapping because it - * had a reference or some other temporary failure, - * Try again. We want to give up inline reclaim only - * if there is no range assigned to this node. Otherwise - * if a deadlock is possible if we sleep with fi->i_mmap_sem - * held and worker to free memory can't make progress due - * to unavailability of fi->i_mmap_sem lock. So sleep - * only if fi->dax->nr=0 - */ - if (retry) - continue; - /* - * There are no mappings which can be reclaimed. Wait for one. - * We are not holding fi->dax->sem. So it is possible - * that range gets added now. But as we are not holding - * fi->i_mmap_sem, worker should still be able to free up - * a range and wake us up. - */ - if (!fi->dax->nr && !(fcd->nr_free_ranges > 0)) { - if (wait_event_killable_exclusive(fcd->range_waitq, - (fcd->nr_free_ranges > 0))) { - return ERR_PTR(-EINTR); - } - } - } -} - -static int lookup_and_reclaim_dmap_locked(struct fuse_conn_dax *fcd, - struct inode *inode, - unsigned long start_idx) -{ - int ret; - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_dax_mapping *dmap; - struct interval_tree_node *node; - - /* Find fuse dax mapping at file offset inode. */ - node = interval_tree_iter_first(&fi->dax->tree, start_idx, start_idx); - - /* Range already got cleaned up by somebody else */ - if (!node) - return 0; - dmap = node_to_dmap(node); - - /* still in use. */ - if (refcount_read(&dmap->refcnt) > 1) - return 0; - - ret = reclaim_one_dmap_locked(inode, dmap); - if (ret < 0) - return ret; - - /* Cleanup dmap entry and add back to free list */ - spin_lock(&fcd->lock); - dmap_reinit_add_to_free_pool(fcd, dmap); - spin_unlock(&fcd->lock); - return ret; -} - -/* - * Free a range of memory. - * Locking: - * 1. Take fi->i_mmap_sem to block dax faults. - * 2. Take fi->dax->sem to protect interval tree and also to make sure - * read/write can not reuse a dmap which we might be freeing. - */ -static int lookup_and_reclaim_dmap(struct fuse_conn_dax *fcd, - struct inode *inode, - unsigned long start_idx, - unsigned long end_idx) -{ - int ret; - struct fuse_inode *fi = get_fuse_inode(inode); - loff_t dmap_start = start_idx << FUSE_DAX_SHIFT; - loff_t dmap_end = (dmap_start + FUSE_DAX_SZ) - 1; - - down_write(&fi->i_mmap_sem); - ret = fuse_dax_break_layouts(inode, dmap_start, dmap_end); - if (ret) { - pr_debug("virtio_fs: fuse_dax_break_layouts() failed. err=%d\n", - ret); - goto out_mmap_sem; - } - - down_write(&fi->dax->sem); - ret = lookup_and_reclaim_dmap_locked(fcd, inode, start_idx); - up_write(&fi->dax->sem); -out_mmap_sem: - up_write(&fi->i_mmap_sem); - return ret; -} - -static int try_to_free_dmap_chunks(struct fuse_conn_dax *fcd, - unsigned long nr_to_free) -{ - struct fuse_dax_mapping *dmap, *pos, *temp; - int ret, nr_freed = 0; - unsigned long start_idx = 0, end_idx = 0; - struct inode *inode = NULL; - - /* Pick first busy range and free it for now*/ - while (1) { - if (nr_freed >= nr_to_free) - break; - - dmap = NULL; - spin_lock(&fcd->lock); - - if (!fcd->nr_busy_ranges) { - spin_unlock(&fcd->lock); - return 0; - } - - list_for_each_entry_safe(pos, temp, &fcd->busy_ranges, - busy_list) { - /* skip this range if it's in use. */ - if (refcount_read(&pos->refcnt) > 1) - continue; - - inode = igrab(pos->inode); - /* - * This inode is going away. That will free - * up all the ranges anyway, continue to - * next range. - */ - if (!inode) - continue; - /* - * Take this element off list and add it tail. If - * this element can't be freed, it will help with - * selecting new element in next iteration of loop. - */ - dmap = pos; - list_move_tail(&dmap->busy_list, &fcd->busy_ranges); - start_idx = end_idx = dmap->itn.start; - break; - } - spin_unlock(&fcd->lock); - if (!dmap) - return 0; - - ret = lookup_and_reclaim_dmap(fcd, inode, start_idx, end_idx); - iput(inode); - if (ret) - return ret; - nr_freed++; - } - return 0; -} - -static void fuse_dax_free_mem_worker(struct work_struct *work) -{ - int ret; - struct fuse_conn_dax *fcd = container_of(work, struct fuse_conn_dax, - free_work.work); - ret = try_to_free_dmap_chunks(fcd, FUSE_DAX_RECLAIM_CHUNK); - if (ret) { - pr_debug("fuse: try_to_free_dmap_chunks() failed with err=%d\n", - ret); - } - - /* If number of free ranges are still below threhold, requeue */ - kick_dmap_free_worker(fcd, 1); -} - -static void fuse_free_dax_mem_ranges(struct list_head *mem_list) -{ - struct fuse_dax_mapping *range, *temp; - - /* Free All allocated elements */ - list_for_each_entry_safe(range, temp, mem_list, list) { - list_del(&range->list); - if (!list_empty(&range->busy_list)) - list_del(&range->busy_list); - kfree(range); - } -} - -void fuse_dax_conn_free(struct fuse_conn *fc) -{ - if (fc->dax) { - fuse_free_dax_mem_ranges(&fc->dax->free_ranges); - kfree(fc->dax); - fc->dax = NULL; - } -} - -static int fuse_dax_mem_range_init(struct fuse_conn_dax *fcd) -{ - long nr_pages, nr_ranges; - void *kaddr; - pfn_t pfn; - struct fuse_dax_mapping *range; - int ret, id; - size_t dax_size = -1; - unsigned long i; - - init_waitqueue_head(&fcd->range_waitq); - INIT_LIST_HEAD(&fcd->free_ranges); - INIT_LIST_HEAD(&fcd->busy_ranges); - INIT_DELAYED_WORK(&fcd->free_work, fuse_dax_free_mem_worker); - - id = dax_read_lock(); - nr_pages = dax_direct_access(fcd->dev, 0, PHYS_PFN(dax_size), &kaddr, - &pfn); - dax_read_unlock(id); - if (nr_pages < 0) { - pr_debug("dax_direct_access() returned %ld\n", nr_pages); - return nr_pages; - } - - nr_ranges = nr_pages/FUSE_DAX_PAGES; - pr_debug("%s: dax mapped %ld pages. nr_ranges=%ld\n", - __func__, nr_pages, nr_ranges); - - for (i = 0; i < nr_ranges; i++) { - range = kzalloc(sizeof(struct fuse_dax_mapping), GFP_KERNEL); - ret = -ENOMEM; - if (!range) - goto out_err; - - /* TODO: This offset only works if virtio-fs driver is not - * having some memory hidden at the beginning. This needs - * better handling - */ - range->window_offset = i * FUSE_DAX_SZ; - range->length = FUSE_DAX_SZ; - INIT_LIST_HEAD(&range->busy_list); - refcount_set(&range->refcnt, 1); - list_add_tail(&range->list, &fcd->free_ranges); - } - - fcd->nr_free_ranges = nr_ranges; - fcd->nr_ranges = nr_ranges; - return 0; -out_err: - /* Free All allocated elements */ - fuse_free_dax_mem_ranges(&fcd->free_ranges); - return ret; -} - -int fuse_dax_conn_alloc(struct fuse_conn *fc, struct dax_device *dax_dev) -{ - struct fuse_conn_dax *fcd; - int err; - - if (!dax_dev) - return 0; - - fcd = kzalloc(sizeof(*fcd), GFP_KERNEL); - if (!fcd) - return -ENOMEM; - - spin_lock_init(&fcd->lock); - fcd->dev = dax_dev; - err = fuse_dax_mem_range_init(fcd); - if (err) { - kfree(fcd); - return err; - } - - fc->dax = fcd; - return 0; -} - -bool fuse_dax_inode_alloc(struct super_block *sb, struct fuse_inode *fi) -{ - struct fuse_conn *fc = get_fuse_conn_super(sb); - - fi->dax = NULL; - if (fc->dax) { - fi->dax = kzalloc(sizeof(*fi->dax), GFP_KERNEL_ACCOUNT); - if (!fi->dax) - return false; - - init_rwsem(&fi->dax->sem); - fi->dax->tree = RB_ROOT_CACHED; - } - - return true; -} - -static const struct address_space_operations fuse_dax_file_aops = { - .writepages = fuse_dax_writepages, - .direct_IO = noop_direct_IO, - .set_page_dirty = noop_set_page_dirty, - .invalidatepage = noop_invalidatepage, -}; - -void fuse_dax_inode_init(struct inode *inode) -{ - struct fuse_conn *fc = get_fuse_conn(inode); - - if (!fc->dax) - return; - - inode->i_flags |= S_DAX; - inode->i_data.a_ops = &fuse_dax_file_aops; -} - -bool fuse_dax_check_alignment(struct fuse_conn *fc, unsigned int map_alignment) -{ - if (fc->dax && (map_alignment > FUSE_DAX_SHIFT)) { - pr_warn("FUSE: map_alignment %u incompatible with dax mem range size %u\n", - map_alignment, FUSE_DAX_SZ); - return false; - } - return true; -} - -void fuse_dax_cancel_work(struct fuse_conn *fc) -{ - struct fuse_conn_dax *fcd = fc->dax; - - if (fcd) - cancel_delayed_work_sync(&fcd->free_work); - -} -EXPORT_SYMBOL_GPL(fuse_dax_cancel_work); diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c index c908eb46cbd0..90afaa7eeeeb 100644 --- a/fs/fuse/dev.c +++ b/fs/fuse/dev.c @@ -42,21 +42,20 @@ static struct fuse_dev *fuse_get_dev(struct file *file) return READ_ONCE(file->private_data); } -static void fuse_request_init(struct fuse_mount *fm, struct fuse_req *req) +static void fuse_request_init(struct fuse_req *req) { INIT_LIST_HEAD(&req->list); INIT_LIST_HEAD(&req->intr_entry); init_waitqueue_head(&req->waitq); refcount_set(&req->count, 1); __set_bit(FR_PENDING, &req->flags); - req->fm = fm; } -static struct fuse_req *fuse_request_alloc(struct fuse_mount *fm, gfp_t flags) +static struct fuse_req *fuse_request_alloc(gfp_t flags) { struct fuse_req *req = kmem_cache_zalloc(fuse_req_cachep, flags); if (req) - fuse_request_init(fm, req); + fuse_request_init(req); return req; } @@ -103,11 +102,10 @@ static void fuse_drop_waiting(struct fuse_conn *fc) } } -static void fuse_put_request(struct fuse_req *req); +static void fuse_put_request(struct fuse_conn *fc, struct fuse_req *req); -static struct fuse_req *fuse_get_req(struct fuse_mount *fm, bool for_background) +static struct fuse_req *fuse_get_req(struct fuse_conn *fc, bool for_background) { - struct fuse_conn *fc = fm->fc; struct fuse_req *req; int err; atomic_inc(&fc->num_waiting); @@ -129,7 +127,7 @@ static struct fuse_req *fuse_get_req(struct fuse_mount *fm, bool for_background) if (fc->conn_error) goto out; - req = fuse_request_alloc(fm, GFP_KERNEL); + req = fuse_request_alloc(GFP_KERNEL); err = -ENOMEM; if (!req) { if (for_background) @@ -147,7 +145,7 @@ static struct fuse_req *fuse_get_req(struct fuse_mount *fm, bool for_background) if (unlikely(req->in.h.uid == ((uid_t)-1) || req->in.h.gid == ((gid_t)-1))) { - fuse_put_request(req); + fuse_put_request(fc, req); return ERR_PTR(-EOVERFLOW); } return req; @@ -157,10 +155,8 @@ static struct fuse_req *fuse_get_req(struct fuse_mount *fm, bool for_background) return ERR_PTR(err); } -static void fuse_put_request(struct fuse_req *req) +static void fuse_put_request(struct fuse_conn *fc, struct fuse_req *req) { - struct fuse_conn *fc = req->fm->fc; - if (refcount_dec_and_test(&req->count)) { if (test_bit(FR_BACKGROUND, &req->flags)) { /* @@ -243,11 +239,6 @@ void fuse_queue_forget(struct fuse_conn *fc, struct fuse_forget_link *forget, { struct fuse_iqueue *fiq = &fc->iq; - if (nodeid == 0) { - kfree(forget); - return; - } - forget->forget_one.nodeid = nodeid; forget->forget_one.nlookup = nlookup; @@ -287,10 +278,8 @@ static void flush_bg_queue(struct fuse_conn *fc) * the 'end' callback is called if given, else the reference to the * request is released */ -void fuse_request_end(struct fuse_req *req) +void fuse_request_end(struct fuse_conn *fc, struct fuse_req *req) { - struct fuse_mount *fm = req->fm; - struct fuse_conn *fc = fm->fc; struct fuse_iqueue *fiq = &fc->iq; if (test_and_set_bit(FR_FINISHED, &req->flags)) @@ -325,9 +314,9 @@ void fuse_request_end(struct fuse_req *req) wake_up(&fc->blocked_waitq); } - if (fc->num_background == fc->congestion_threshold && fm->sb) { - clear_bdi_congested(fm->sb->s_bdi, BLK_RW_SYNC); - clear_bdi_congested(fm->sb->s_bdi, BLK_RW_ASYNC); + if (fc->num_background == fc->congestion_threshold && fc->sb) { + clear_bdi_congested(fc->sb->s_bdi, BLK_RW_SYNC); + clear_bdi_congested(fc->sb->s_bdi, BLK_RW_ASYNC); } fc->num_background--; fc->active_background--; @@ -339,16 +328,14 @@ void fuse_request_end(struct fuse_req *req) } if (test_bit(FR_ASYNC, &req->flags)) - req->args->end(fm, req->args, req->out.h.error); + req->args->end(fc, req->args, req->out.h.error); put_request: - fuse_put_request(req); + fuse_put_request(fc, req); } EXPORT_SYMBOL_GPL(fuse_request_end); -static int queue_interrupt(struct fuse_req *req) +static int queue_interrupt(struct fuse_iqueue *fiq, struct fuse_req *req) { - struct fuse_iqueue *fiq = &req->fm->fc->iq; - spin_lock(&fiq->lock); /* Check for we've sent request to interrupt this req */ if (unlikely(!test_bit(FR_INTERRUPTED, &req->flags))) { @@ -360,7 +347,7 @@ static int queue_interrupt(struct fuse_req *req) list_add_tail(&req->intr_entry, &fiq->interrupts); /* * Pairs with smp_mb() implied by test_and_set_bit() - * from fuse_request_end(). + * from request_end(). */ smp_mb(); if (test_bit(FR_FINISHED, &req->flags)) { @@ -375,9 +362,8 @@ static int queue_interrupt(struct fuse_req *req) return 0; } -static void request_wait_answer(struct fuse_req *req) +static void request_wait_answer(struct fuse_conn *fc, struct fuse_req *req) { - struct fuse_conn *fc = req->fm->fc; struct fuse_iqueue *fiq = &fc->iq; int err; @@ -392,7 +378,7 @@ static void request_wait_answer(struct fuse_req *req) /* matches barrier in fuse_dev_do_read() */ smp_mb__after_atomic(); if (test_bit(FR_SENT, &req->flags)) - queue_interrupt(req); + queue_interrupt(fiq, req); } if (!test_bit(FR_FORCE, &req->flags)) { @@ -423,9 +409,9 @@ static void request_wait_answer(struct fuse_req *req) test_bit(FR_FINISHED, &req->flags)); } -static void __fuse_request_send(struct fuse_req *req) +static void __fuse_request_send(struct fuse_conn *fc, struct fuse_req *req) { - struct fuse_iqueue *fiq = &req->fm->fc->iq; + struct fuse_iqueue *fiq = &fc->iq; BUG_ON(test_bit(FR_BACKGROUND, &req->flags)); spin_lock(&fiq->lock); @@ -439,7 +425,7 @@ static void __fuse_request_send(struct fuse_req *req) __fuse_get_request(req); queue_request_and_unlock(fiq, req, 1); - request_wait_answer(req); + request_wait_answer(fc, req); /* Pairs with smp_wmb() in fuse_request_end() */ smp_rmb(); } @@ -478,10 +464,8 @@ static void fuse_adjust_compat(struct fuse_conn *fc, struct fuse_args *args) } } -static void fuse_force_creds(struct fuse_req *req) +static void fuse_force_creds(struct fuse_conn *fc, struct fuse_req *req) { - struct fuse_conn *fc = req->fm->fc; - req->in.h.uid = from_kuid_munged(fc->user_ns, current_fsuid()); req->in.h.gid = from_kgid_munged(fc->user_ns, current_fsgid()); req->in.h.pid = pid_nr_ns(task_pid(current), fc->pid_ns); @@ -491,30 +475,28 @@ static void fuse_args_to_req(struct fuse_req *req, struct fuse_args *args) { req->in.h.opcode = args->opcode; req->in.h.nodeid = args->nodeid; - req->in.h.error_in = args->error_in; req->args = args; if (args->end) __set_bit(FR_ASYNC, &req->flags); } -ssize_t fuse_simple_request(struct fuse_mount *fm, struct fuse_args *args) +ssize_t fuse_simple_request(struct fuse_conn *fc, struct fuse_args *args) { - struct fuse_conn *fc = fm->fc; struct fuse_req *req; ssize_t ret; if (args->force) { atomic_inc(&fc->num_waiting); - req = fuse_request_alloc(fm, GFP_KERNEL | __GFP_NOFAIL); + req = fuse_request_alloc(GFP_KERNEL | __GFP_NOFAIL); if (!args->nocreds) - fuse_force_creds(req); + fuse_force_creds(fc, req); __set_bit(FR_WAITING, &req->flags); __set_bit(FR_FORCE, &req->flags); } else { WARN_ON(args->nocreds); - req = fuse_get_req(fm, false); + req = fuse_get_req(fc, false); if (IS_ERR(req)) return PTR_ERR(req); } @@ -525,21 +507,20 @@ ssize_t fuse_simple_request(struct fuse_mount *fm, struct fuse_args *args) if (!args->noreply) __set_bit(FR_ISREPLY, &req->flags); - __fuse_request_send(req); + __fuse_request_send(fc, req); ret = req->out.h.error; if (!ret && args->out_argvar) { BUG_ON(args->out_numargs == 0); ret = args->out_args[args->out_numargs - 1].size; } - fuse_put_request(req); + fuse_put_request(fc, req); return ret; } -static bool fuse_request_queue_background(struct fuse_req *req) +static bool fuse_request_queue_background(struct fuse_conn *fc, + struct fuse_req *req) { - struct fuse_mount *fm = req->fm; - struct fuse_conn *fc = fm->fc; bool queued = false; WARN_ON(!test_bit(FR_BACKGROUND, &req->flags)); @@ -553,9 +534,9 @@ static bool fuse_request_queue_background(struct fuse_req *req) fc->num_background++; if (fc->num_background == fc->max_background) fc->blocked = 1; - if (fc->num_background == fc->congestion_threshold && fm->sb) { - set_bdi_congested(fm->sb->s_bdi, BLK_RW_SYNC); - set_bdi_congested(fm->sb->s_bdi, BLK_RW_ASYNC); + if (fc->num_background == fc->congestion_threshold && fc->sb) { + set_bdi_congested(fc->sb->s_bdi, BLK_RW_SYNC); + set_bdi_congested(fc->sb->s_bdi, BLK_RW_ASYNC); } list_add_tail(&req->list, &fc->bg_queue); flush_bg_queue(fc); @@ -566,28 +547,28 @@ static bool fuse_request_queue_background(struct fuse_req *req) return queued; } -int fuse_simple_background(struct fuse_mount *fm, struct fuse_args *args, +int fuse_simple_background(struct fuse_conn *fc, struct fuse_args *args, gfp_t gfp_flags) { struct fuse_req *req; if (args->force) { WARN_ON(!args->nocreds); - req = fuse_request_alloc(fm, gfp_flags); + req = fuse_request_alloc(gfp_flags); if (!req) return -ENOMEM; __set_bit(FR_BACKGROUND, &req->flags); } else { WARN_ON(args->nocreds); - req = fuse_get_req(fm, true); + req = fuse_get_req(fc, true); if (IS_ERR(req)) return PTR_ERR(req); } fuse_args_to_req(req, args); - if (!fuse_request_queue_background(req)) { - fuse_put_request(req); + if (!fuse_request_queue_background(fc, req)) { + fuse_put_request(fc, req); return -ENOTCONN; } @@ -595,14 +576,14 @@ int fuse_simple_background(struct fuse_mount *fm, struct fuse_args *args, } EXPORT_SYMBOL_GPL(fuse_simple_background); -static int fuse_simple_notify_reply(struct fuse_mount *fm, +static int fuse_simple_notify_reply(struct fuse_conn *fc, struct fuse_args *args, u64 unique) { struct fuse_req *req; - struct fuse_iqueue *fiq = &fm->fc->iq; + struct fuse_iqueue *fiq = &fc->iq; int err = 0; - req = fuse_get_req(fm, false); + req = fuse_get_req(fc, false); if (IS_ERR(req)) return PTR_ERR(req); @@ -617,7 +598,7 @@ static int fuse_simple_notify_reply(struct fuse_mount *fm, } else { err = -ENODEV; spin_unlock(&fiq->lock); - fuse_put_request(req); + fuse_put_request(fc, req); } return err; @@ -696,10 +677,6 @@ static void fuse_copy_finish(struct fuse_copy_state *cs) flush_dcache_page(cs->pg); set_page_dirty_lock(cs->pg); } - /* - * The page could be GUP page(see iov_iter_get_pages in - * fuse_copy_fill) so use put_page to release it. - */ put_page(cs->pg); } cs->pg = NULL; @@ -803,7 +780,8 @@ static int fuse_check_page(struct page *page) 1 << PG_workingset | 1 << PG_reclaim | 1 << PG_waiters))) { - dump_page(page, "fuse: trying to steal weird page"); + pr_warn("trying to steal weird page\n"); + pr_warn(" page=%p index=%li flags=%08lx, count=%i, mapcount=%i, mapping=%p\n", page, page->index, page->flags, page_count(page), page_mapcount(page), page->mapping); return 1; } return 0; @@ -1305,7 +1283,7 @@ static ssize_t fuse_dev_do_read(struct fuse_dev *fud, struct file *file, /* SETXATTR is special, since it may contain too large data */ if (args->opcode == FUSE_SETXATTR) req->out.h.error = -E2BIG; - fuse_request_end(req); + fuse_request_end(fc, req); goto restart; } spin_lock(&fpq->lock); @@ -1348,8 +1326,8 @@ static ssize_t fuse_dev_do_read(struct fuse_dev *fud, struct file *file, /* matches barrier in request_wait_answer() */ smp_mb__after_atomic(); if (test_bit(FR_INTERRUPTED, &req->flags)) - queue_interrupt(req); - fuse_put_request(req); + queue_interrupt(fiq, req); + fuse_put_request(fc, req); return reqsize; @@ -1357,7 +1335,7 @@ out_end: if (!test_bit(FR_PRIVATE, &req->flags)) list_del_init(&req->list); spin_unlock(&fpq->lock); - fuse_request_end(req); + fuse_request_end(fc, req); return err; err_unlock: @@ -1480,8 +1458,11 @@ static int fuse_notify_inval_inode(struct fuse_conn *fc, unsigned int size, fuse_copy_finish(cs); down_read(&fc->killsb); - err = fuse_reverse_inval_inode(fc, outarg.ino, - outarg.off, outarg.len); + err = -ENOENT; + if (fc->sb) { + err = fuse_reverse_inval_inode(fc->sb, outarg.ino, + outarg.off, outarg.len); + } up_read(&fc->killsb); return err; @@ -1527,7 +1508,9 @@ static int fuse_notify_inval_entry(struct fuse_conn *fc, unsigned int size, buf[outarg.namelen] = 0; down_read(&fc->killsb); - err = fuse_reverse_inval_entry(fc, outarg.parent, 0, &name); + err = -ENOENT; + if (fc->sb) + err = fuse_reverse_inval_entry(fc->sb, outarg.parent, 0, &name); up_read(&fc->killsb); kfree(buf); return err; @@ -1575,7 +1558,10 @@ static int fuse_notify_delete(struct fuse_conn *fc, unsigned int size, buf[outarg.namelen] = 0; down_read(&fc->killsb); - err = fuse_reverse_inval_entry(fc, outarg.parent, outarg.child, &name); + err = -ENOENT; + if (fc->sb) + err = fuse_reverse_inval_entry(fc->sb, outarg.parent, + outarg.child, &name); up_read(&fc->killsb); kfree(buf); return err; @@ -1617,7 +1603,10 @@ static int fuse_notify_store(struct fuse_conn *fc, unsigned int size, down_read(&fc->killsb); err = -ENOENT; - inode = fuse_ilookup(fc, nodeid, NULL); + if (!fc->sb) + goto out_up_killsb; + + inode = ilookup5(fc->sb, nodeid, fuse_inode_eq, &nodeid); if (!inode) goto out_up_killsb; @@ -1676,7 +1665,7 @@ struct fuse_retrieve_args { struct fuse_notify_retrieve_in inarg; }; -static void fuse_retrieve_end(struct fuse_mount *fm, struct fuse_args *args, +static void fuse_retrieve_end(struct fuse_conn *fc, struct fuse_args *args, int error) { struct fuse_retrieve_args *ra = @@ -1686,7 +1675,7 @@ static void fuse_retrieve_end(struct fuse_mount *fm, struct fuse_args *args, kfree(ra); } -static int fuse_retrieve(struct fuse_mount *fm, struct inode *inode, +static int fuse_retrieve(struct fuse_conn *fc, struct inode *inode, struct fuse_notify_retrieve_out *outarg) { int err; @@ -1697,7 +1686,6 @@ static int fuse_retrieve(struct fuse_mount *fm, struct inode *inode, unsigned int offset; size_t total_len = 0; unsigned int num_pages; - struct fuse_conn *fc = fm->fc; struct fuse_retrieve_args *ra; size_t args_size = sizeof(*ra); struct fuse_args_pages *ap; @@ -1759,9 +1747,9 @@ static int fuse_retrieve(struct fuse_mount *fm, struct inode *inode, args->in_args[0].value = &ra->inarg; args->in_args[1].size = total_len; - err = fuse_simple_notify_reply(fm, args, outarg->notify_unique); + err = fuse_simple_notify_reply(fc, args, outarg->notify_unique); if (err) - fuse_retrieve_end(fm, args, err); + fuse_retrieve_end(fc, args, err); return err; } @@ -1770,9 +1758,7 @@ static int fuse_notify_retrieve(struct fuse_conn *fc, unsigned int size, struct fuse_copy_state *cs) { struct fuse_notify_retrieve_out outarg; - struct fuse_mount *fm; struct inode *inode; - u64 nodeid; int err; err = -EINVAL; @@ -1787,12 +1773,14 @@ static int fuse_notify_retrieve(struct fuse_conn *fc, unsigned int size, down_read(&fc->killsb); err = -ENOENT; - nodeid = outarg.nodeid; + if (fc->sb) { + u64 nodeid = outarg.nodeid; - inode = fuse_ilookup(fc, nodeid, &fm); - if (inode) { - err = fuse_retrieve(fm, inode, &outarg); - iput(inode); + inode = ilookup5(fc->sb, nodeid, fuse_inode_eq, &nodeid); + if (inode) { + err = fuse_retrieve(fc, inode, &outarg); + iput(inode); + } } up_read(&fc->killsb); @@ -1931,9 +1919,9 @@ static ssize_t fuse_dev_do_write(struct fuse_dev *fud, else if (oh.error == -ENOSYS) fc->no_interrupt = 1; else if (oh.error == -EAGAIN) - err = queue_interrupt(req); + err = queue_interrupt(&fc->iq, req); - fuse_put_request(req); + fuse_put_request(fc, req); goto copy_finish; } @@ -1959,19 +1947,6 @@ static ssize_t fuse_dev_do_write(struct fuse_dev *fud, req->out.h.error = kern_path(path, 0, req->args->canonical_path); } - if (!err && (req->in.h.opcode == FUSE_LOOKUP || - req->in.h.opcode == (FUSE_LOOKUP | FUSE_POSTFILTER)) && - req->args->out_args[1].size == sizeof(struct fuse_entry_bpf_out)) { - struct fuse_entry_bpf_out *febo = (struct fuse_entry_bpf_out *) - req->args->out_args[1].value; - struct fuse_entry_bpf *feb = container_of(febo, struct fuse_entry_bpf, out); - - if (febo->backing_action == FUSE_ACTION_REPLACE) - feb->backing_file = fget(febo->backing_fd); - if (febo->bpf_action == FUSE_ACTION_REPLACE) - feb->bpf_file = fget(febo->bpf_fd); - } - spin_lock(&fpq->lock); clear_bit(FR_LOCKED, &req->flags); if (!fpq->connected) @@ -1982,7 +1957,7 @@ static ssize_t fuse_dev_do_write(struct fuse_dev *fud, list_del_init(&req->list); spin_unlock(&fpq->lock); - fuse_request_end(req); + fuse_request_end(fc, req); out: return err ? err : nbytes; @@ -2118,7 +2093,7 @@ static __poll_t fuse_dev_poll(struct file *file, poll_table *wait) } /* Abort all requests on the given list (pending or processing) */ -static void end_requests(struct list_head *head) +static void end_requests(struct fuse_conn *fc, struct list_head *head) { while (!list_empty(head)) { struct fuse_req *req; @@ -2126,7 +2101,7 @@ static void end_requests(struct list_head *head) req->out.h.error = -ECONNABORTED; clear_bit(FR_SENT, &req->flags); list_del_init(&req->list); - fuse_request_end(req); + fuse_request_end(fc, req); } } @@ -2221,7 +2196,7 @@ void fuse_abort_conn(struct fuse_conn *fc) wake_up_all(&fc->blocked_waitq); spin_unlock(&fc->lock); - end_requests(&to_end); + end_requests(fc, &to_end); } else { spin_unlock(&fc->lock); } @@ -2251,7 +2226,7 @@ int fuse_dev_release(struct inode *inode, struct file *file) list_splice_init(&fpq->processing[i], &to_end); spin_unlock(&fpq->lock); - end_requests(&to_end); + end_requests(fc, &to_end); /* Are we the last open device? */ if (atomic_dec_and_test(&fc->dev_count)) { @@ -2353,7 +2328,7 @@ const struct file_operations fuse_dev_operations = { .release = fuse_dev_release, .fasync = fuse_dev_fasync, .unlocked_ioctl = fuse_dev_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = fuse_dev_ioctl, }; EXPORT_SYMBOL_GPL(fuse_dev_operations); diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c index a55375ae2797..7cf55a7635fa 100644 --- a/fs/fuse/dir.c +++ b/fs/fuse/dir.c @@ -8,11 +8,8 @@ #include "fuse_i.h" -#include #include #include -#include -#include #include #include #include @@ -20,8 +17,6 @@ #include #include -#include "../internal.h" - static void fuse_advise_use_readdirplus(struct inode *dir) { struct fuse_inode *fi = get_fuse_inode(dir); @@ -29,7 +24,7 @@ static void fuse_advise_use_readdirplus(struct inode *dir) set_bit(FUSE_I_ADVISE_RDPLUS, &fi->state); } -#if BITS_PER_LONG >= 64 && !defined(CONFIG_FUSE_BPF) +#if BITS_PER_LONG >= 64 static inline void __fuse_dentry_settime(struct dentry *entry, u64 time) { entry->d_fsdata = (void *) time; @@ -41,15 +36,19 @@ static inline u64 fuse_dentry_time(const struct dentry *entry) } #else +union fuse_dentry { + u64 time; + struct rcu_head rcu; +}; static inline void __fuse_dentry_settime(struct dentry *dentry, u64 time) { - ((struct fuse_dentry *) dentry->d_fsdata)->time = time; + ((union fuse_dentry *) dentry->d_fsdata)->time = time; } static inline u64 fuse_dentry_time(const struct dentry *entry) { - return ((struct fuse_dentry *) entry->d_fsdata)->time; + return ((union fuse_dentry *) entry->d_fsdata)->time; } #endif @@ -74,16 +73,26 @@ static void fuse_dentry_settime(struct dentry *dentry, u64 time) __fuse_dentry_settime(dentry, time); } -void fuse_init_dentry_root(struct dentry *root, struct file *backing_dir) -{ -#ifdef CONFIG_FUSE_BPF - struct fuse_dentry *fuse_dentry = root->d_fsdata; +/* + * FUSE caches dentries and attributes with separate timeout. The + * time in jiffies until the dentry/attributes are valid is stored in + * dentry->d_fsdata and fuse_inode->i_time respectively. + */ - if (backing_dir) { - fuse_dentry->backing_path = backing_dir->f_path; - path_get(&fuse_dentry->backing_path); - } -#endif +/* + * Calculate the time in jiffies until a dentry/attributes are valid + */ +static u64 time_to_jiffies(u64 sec, u32 nsec) +{ + if (sec || nsec) { + struct timespec64 ts = { + sec, + min_t(u32, nsec, NSEC_PER_SEC - 1) + }; + + return get_jiffies_64() + timespec64_to_jiffies(&ts); + } else + return 0; } /* @@ -96,6 +105,11 @@ void fuse_change_entry_timeout(struct dentry *entry, struct fuse_entry_out *o) time_to_jiffies(o->entry_valid, o->entry_valid_nsec)); } +static u64 attr_timeout(struct fuse_attr_out *o) +{ + return time_to_jiffies(o->attr_valid, o->attr_valid_nsec); +} + u64 entry_attr_timeout(struct fuse_entry_out *o) { return time_to_jiffies(o->attr_valid, o->attr_valid_nsec); @@ -156,8 +170,7 @@ static void fuse_invalidate_entry(struct dentry *entry) static void fuse_lookup_init(struct fuse_conn *fc, struct fuse_args *args, u64 nodeid, const struct qstr *name, - struct fuse_entry_out *outarg, - struct fuse_entry_bpf_out *bpf_outarg) + struct fuse_entry_out *outarg) { memset(outarg, 0, sizeof(struct fuse_entry_out)); args->opcode = FUSE_LOOKUP; @@ -165,57 +178,11 @@ static void fuse_lookup_init(struct fuse_conn *fc, struct fuse_args *args, args->in_numargs = 1; args->in_args[0].size = name->len + 1; args->in_args[0].value = name->name; - args->out_argvar = true; - args->out_numargs = 2; + args->out_numargs = 1; args->out_args[0].size = sizeof(struct fuse_entry_out); args->out_args[0].value = outarg; - args->out_args[1].size = sizeof(struct fuse_entry_bpf_out); - args->out_args[1].value = bpf_outarg; } -#ifdef CONFIG_FUSE_BPF -static bool backing_data_changed(struct fuse_inode *fi, struct dentry *entry, - struct fuse_entry_bpf *bpf_arg) -{ - struct path new_backing_path; - struct inode *new_backing_inode; - struct bpf_prog *bpf = NULL; - int err; - bool ret = true; - - if (!entry || !fi->backing_inode) { - ret = false; - goto put_backing_file; - } - - get_fuse_backing_path(entry, &new_backing_path); - new_backing_inode = fi->backing_inode; - ihold(new_backing_inode); - - err = fuse_handle_backing(bpf_arg, &new_backing_inode, &new_backing_path); - - if (err) - goto put_inode; - - err = fuse_handle_bpf_prog(bpf_arg, entry->d_parent->d_inode, &bpf); - if (err) - goto put_bpf; - - ret = (bpf != fi->bpf || fi->backing_inode != new_backing_inode || - !path_equal(&get_fuse_dentry(entry)->backing_path, &new_backing_path)); -put_bpf: - if (bpf) - bpf_prog_put(bpf); -put_inode: - iput(new_backing_inode); - path_put(&new_backing_path); -put_backing_file: - if (bpf_arg->backing_file) - fput(bpf_arg->backing_file); - return ret; -} -#endif - /* * Check whether the dentry is still valid * @@ -229,29 +196,16 @@ static int fuse_dentry_revalidate(struct dentry *entry, unsigned int flags) { struct inode *inode; struct dentry *parent; - struct fuse_mount *fm; + struct fuse_conn *fc; struct fuse_inode *fi; int ret; inode = d_inode_rcu(entry); if (inode && fuse_is_bad(inode)) goto invalid; -#ifdef CONFIG_FUSE_BPF - /* TODO: Do we need bpf support for revalidate? - * If the lower filesystem says the entry is invalid, FUSE probably shouldn't - * try to fix that without going through the normal lookup path... - */ - if (get_fuse_dentry(entry)->backing_path.dentry) { - ret = fuse_revalidate_backing(entry, flags); - if (ret <= 0) { - goto out; - } - } -#endif - if (time_before64(fuse_dentry_time(entry), get_jiffies_64()) || - (flags & (LOOKUP_EXCL | LOOKUP_REVAL | LOOKUP_RENAME_TARGET))) { + else if (time_before64(fuse_dentry_time(entry), get_jiffies_64()) || + (flags & LOOKUP_REVAL)) { struct fuse_entry_out outarg; - struct fuse_entry_bpf bpf_arg; FUSE_ARGS(args); struct fuse_forget_link *forget; u64 attr_version; @@ -263,47 +217,28 @@ static int fuse_dentry_revalidate(struct dentry *entry, unsigned int flags) ret = -ECHILD; if (flags & LOOKUP_RCU) goto out; - fm = get_fuse_mount(inode); - parent = dget_parent(entry); + fc = get_fuse_conn(inode); -#ifdef CONFIG_FUSE_BPF - /* TODO: Once we're handling timeouts for backing inodes, do a - * bpf based lookup_revalidate here. - */ - if (get_fuse_inode(parent->d_inode)->backing_inode) { - dput(parent); - ret = 1; - goto out; - } -#endif forget = fuse_alloc_forget(); ret = -ENOMEM; - if (!forget) { - dput(parent); + if (!forget) goto out; - } - attr_version = fuse_get_attr_version(fm->fc); + attr_version = fuse_get_attr_version(fc); - fuse_lookup_init(fm->fc, &args, get_node_id(d_inode(parent)), - &entry->d_name, &outarg, &bpf_arg.out); - ret = fuse_simple_request(fm, &args); + parent = dget_parent(entry); + fuse_lookup_init(fc, &args, get_node_id(d_inode(parent)), + &entry->d_name, &outarg); + ret = fuse_simple_request(fc, &args); dput(parent); - /* Zero nodeid is same as -ENOENT */ if (!ret && !outarg.nodeid) ret = -ENOENT; - if (!ret || ret == sizeof(bpf_arg.out)) { + if (!ret) { fi = get_fuse_inode(inode); - if (outarg.nodeid != get_node_id(inode) || -#ifdef CONFIG_FUSE_BPF - (ret == sizeof(bpf_arg.out) && - backing_data_changed(fi, entry, &bpf_arg)) || -#endif - (bool) IS_AUTOMOUNT(inode) != (bool) (outarg.attr.flags & FUSE_ATTR_SUBMOUNT)) { - fuse_queue_forget(fm->fc, forget, - outarg.nodeid, 1); + if (outarg.nodeid != get_node_id(inode)) { + fuse_queue_forget(fc, forget, outarg.nodeid, 1); goto invalid; } spin_lock(&fi->lock); @@ -314,7 +249,7 @@ static int fuse_dentry_revalidate(struct dentry *entry, unsigned int flags) if (ret == -ENOMEM || ret == -EINTR) goto out; if (ret || fuse_invalid_attr(&outarg.attr) || - fuse_stale_inode(inode, outarg.generation, &outarg.attr)) + (outarg.attr.mode ^ inode->i_mode) & S_IFMT) goto invalid; forget_all_cached_acls(inode); @@ -342,25 +277,17 @@ invalid: goto out; } -#if BITS_PER_LONG < 64 || defined(CONFIG_FUSE_BPF) +#if BITS_PER_LONG < 64 static int fuse_dentry_init(struct dentry *dentry) { - dentry->d_fsdata = kzalloc(sizeof(struct fuse_dentry), + dentry->d_fsdata = kzalloc(sizeof(union fuse_dentry), GFP_KERNEL_ACCOUNT | __GFP_RECLAIMABLE); return dentry->d_fsdata ? 0 : -ENOMEM; } static void fuse_dentry_release(struct dentry *dentry) { - struct fuse_dentry *fd = dentry->d_fsdata; - -#ifdef CONFIG_FUSE_BPF - if (fd && fd->backing_path.dentry) - path_put(&fd->backing_path); - - if (fd && fd->bpf) - bpf_prog_put(fd->bpf); -#endif + union fuse_dentry *fd = dentry->d_fsdata; kfree_rcu(fd, rcu); } @@ -379,25 +306,11 @@ static int fuse_dentry_delete(const struct dentry *dentry) */ static void fuse_dentry_canonical_path(const struct path *path, struct path *canonical_path) { struct inode *inode = d_inode(path->dentry); - //struct fuse_conn *fc = get_fuse_conn(inode); - struct fuse_mount *fm = get_fuse_mount_super(path->mnt->mnt_sb); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); char *path_name; int err; - -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_dummy_io, - fuse_canonical_path_initialize, - fuse_canonical_path_backing, - fuse_canonical_path_finalize, path, - canonical_path); - if (fer.ret) - return; -#endif - path_name = (char *)get_zeroed_page(GFP_KERNEL); if (!path_name) goto default_path; @@ -411,7 +324,7 @@ static void fuse_dentry_canonical_path(const struct path *path, struct path *can args.canonical_path = canonical_path; args.out_argvar = 1; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); free_page((unsigned long)path_name); if (err > 0) return; @@ -421,107 +334,18 @@ default_path: path_get(canonical_path); } -/* - * Create a fuse_mount object with a new superblock (with path->dentry - * as the root), and return that mount so it can be auto-mounted on - * @path. - */ -static struct vfsmount *fuse_dentry_automount(struct path *path) -{ - struct fs_context *fsc; - struct fuse_mount *parent_fm = get_fuse_mount_super(path->mnt->mnt_sb); - struct fuse_conn *fc = parent_fm->fc; - struct fuse_mount *fm; - struct vfsmount *mnt; - struct fuse_inode *mp_fi = get_fuse_inode(d_inode(path->dentry)); - struct super_block *sb; - int err; - - fsc = fs_context_for_submount(path->mnt->mnt_sb->s_type, path->dentry); - if (IS_ERR(fsc)) { - err = PTR_ERR(fsc); - goto out; - } - - err = -ENOMEM; - fm = kzalloc(sizeof(struct fuse_mount), GFP_KERNEL); - if (!fm) - goto out_put_fsc; - - refcount_set(&fm->count, 1); - fsc->s_fs_info = fm; - sb = sget_fc(fsc, NULL, set_anon_super_fc); - if (IS_ERR(sb)) { - err = PTR_ERR(sb); - fuse_mount_put(fm); - goto out_put_fsc; - } - fm->fc = fuse_conn_get(fc); - - /* Initialize superblock, making @mp_fi its root */ - err = fuse_fill_super_submount(sb, mp_fi); - if (err) { - fuse_conn_put(fc); - kfree(fm); - sb->s_fs_info = NULL; - goto out_put_sb; - } - - down_write(&fc->killsb); - list_add_tail(&fm->fc_entry, &fc->mounts); - up_write(&fc->killsb); - - sb->s_flags |= SB_ACTIVE; - fsc->root = dget(sb->s_root); - - /* - * FIXME: setting SB_BORN requires a write barrier for - * super_cache_count(). We should actually come - * up with a proper ->get_tree() implementation - * for submounts and call vfs_get_tree() to take - * care of the write barrier. - */ - smp_wmb(); - sb->s_flags |= SB_BORN; - - /* We are done configuring the superblock, so unlock it */ - up_write(&sb->s_umount); - - /* Create the submount */ - mnt = vfs_create_mount(fsc); - if (IS_ERR(mnt)) { - err = PTR_ERR(mnt); - goto out_put_fsc; - } - mntget(mnt); - put_fs_context(fsc); - return mnt; - -out_put_sb: - /* - * Only jump here when fsc->root is NULL and sb is still locked - * (otherwise put_fs_context() will put the superblock) - */ - deactivate_locked_super(sb); -out_put_fsc: - put_fs_context(fsc); -out: - return ERR_PTR(err); -} - const struct dentry_operations fuse_dentry_operations = { .d_revalidate = fuse_dentry_revalidate, .d_delete = fuse_dentry_delete, -#if BITS_PER_LONG < 64 || defined(CONFIG_FUSE_BPF) +#if BITS_PER_LONG < 64 .d_init = fuse_dentry_init, .d_release = fuse_dentry_release, #endif - .d_automount = fuse_dentry_automount, .d_canonical_path = fuse_dentry_canonical_path, }; const struct dentry_operations fuse_root_dentry_operations = { -#if BITS_PER_LONG < 64 || defined(CONFIG_FUSE_BPF) +#if BITS_PER_LONG < 64 .d_init = fuse_dentry_init, .d_release = fuse_dentry_release, #endif @@ -540,13 +364,10 @@ bool fuse_invalid_attr(struct fuse_attr *attr) } int fuse_lookup_name(struct super_block *sb, u64 nodeid, const struct qstr *name, - struct fuse_entry_out *outarg, - struct dentry *entry, - struct inode **inode) + struct fuse_entry_out *outarg, struct inode **inode) { - struct fuse_mount *fm = get_fuse_mount_super(sb); + struct fuse_conn *fc = get_fuse_conn_super(sb); FUSE_ARGS(args); - struct fuse_entry_bpf bpf_arg = {0}; struct fuse_forget_link *forget; u64 attr_version; int err; @@ -556,77 +377,32 @@ int fuse_lookup_name(struct super_block *sb, u64 nodeid, const struct qstr *name if (name->len > FUSE_NAME_MAX) goto out; + forget = fuse_alloc_forget(); err = -ENOMEM; if (!forget) goto out; - attr_version = fuse_get_attr_version(fm->fc); + attr_version = fuse_get_attr_version(fc); - fuse_lookup_init(fm->fc, &args, nodeid, name, outarg, &bpf_arg.out); - err = fuse_simple_request(fm, &args); + fuse_lookup_init(fc, &args, nodeid, name, outarg); + err = fuse_simple_request(fc, &args); + /* Zero nodeid is same as -ENOENT, but with valid timeout */ + if (err || !outarg->nodeid) + goto out_put_forget; -#ifdef CONFIG_FUSE_BPF - if (err == sizeof(bpf_arg.out)) { - /* TODO Make sure this handles invalid handles */ - struct file *backing_file; - struct inode *backing_inode; - - err = -ENOENT; - if (!entry) - goto out_put_forget; - - err = -EINVAL; - backing_file = bpf_arg.backing_file; - if (!backing_file) - goto out_put_forget; - - if (IS_ERR(backing_file)) { - err = PTR_ERR(backing_file); - goto out_put_forget; - } - - backing_inode = backing_file->f_inode; - *inode = fuse_iget_backing(sb, outarg->nodeid, backing_inode); - if (!*inode) - goto out_put_forget; - - err = fuse_handle_backing(&bpf_arg, - &get_fuse_inode(*inode)->backing_inode, - &get_fuse_dentry(entry)->backing_path); - if (!err) - err = fuse_handle_bpf_prog(&bpf_arg, NULL, - &get_fuse_inode(*inode)->bpf); - if (err) { - iput(*inode); - *inode = NULL; - goto out_put_forget; - } - } else -#endif - { - /* Zero nodeid is same as -ENOENT, but with valid timeout */ - if (err || !outarg->nodeid) - goto out_put_forget; - - err = -EIO; - if (!outarg->nodeid) - goto out_put_forget; - if (fuse_invalid_attr(&outarg->attr)) - goto out_put_forget; - if (outarg->nodeid == FUSE_ROOT_ID && outarg->generation != 0) { - pr_warn_once("root generation should be zero\n"); - outarg->generation = 0; - } - - *inode = fuse_iget(sb, outarg->nodeid, outarg->generation, - &outarg->attr, entry_attr_timeout(outarg), - attr_version); - } + err = -EIO; + if (!outarg->nodeid) + goto out_put_forget; + if (fuse_invalid_attr(&outarg->attr)) + goto out_put_forget; + *inode = fuse_iget(sb, outarg->nodeid, outarg->generation, + &outarg->attr, entry_attr_timeout(outarg), + attr_version); err = -ENOMEM; - if (!*inode && outarg->nodeid) { - fuse_queue_forget(fm->fc, forget, outarg->nodeid, 1); + if (!*inode) { + fuse_queue_forget(fc, forget, outarg->nodeid, 1); goto out; } err = 0; @@ -634,8 +410,6 @@ int fuse_lookup_name(struct super_block *sb, u64 nodeid, const struct qstr *name out_put_forget: kfree(forget); out: - if (bpf_arg.backing_file) - fput(bpf_arg.backing_file); return err; } @@ -649,23 +423,12 @@ static struct dentry *fuse_lookup(struct inode *dir, struct dentry *entry, bool outarg_valid = true; bool locked; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_lookup_io, - fuse_lookup_initialize, fuse_lookup_backing, - fuse_lookup_finalize, - dir, entry, flags); - if (fer.ret) - return fer.result; -#endif - if (fuse_is_bad(dir)) return ERR_PTR(-EIO); locked = fuse_lock_inode(dir); err = fuse_lookup_name(dir->i_sb, get_node_id(dir), &entry->d_name, - &outarg, entry, &inode); + &outarg, &inode); fuse_unlock_inode(dir, locked); if (err == -ENOENT) { outarg_valid = false; @@ -712,7 +475,6 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry, int err; struct inode *inode; struct fuse_conn *fc = get_fuse_conn(dir); - struct fuse_mount *fm = get_fuse_mount(dir); FUSE_ARGS(args); struct fuse_forget_link *forget; struct fuse_create_in inarg; @@ -720,36 +482,21 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry, struct fuse_entry_out outentry; struct fuse_inode *fi; struct fuse_file *ff; - bool trunc = flags & O_TRUNC; /* Userspace expects S_IFREG in create mode */ BUG_ON((mode & S_IFMT) != S_IFREG); -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_create_open_io, - fuse_create_open_initialize, - fuse_create_open_backing, - fuse_create_open_finalize, - dir, entry, file, flags, mode); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - forget = fuse_alloc_forget(); err = -ENOMEM; if (!forget) goto out_err; err = -ENOMEM; - ff = fuse_file_alloc(fm); + ff = fuse_file_alloc(fc); if (!ff) goto out_put_forget_req; - if (!fm->fc->dont_mask) + if (!fc->dont_mask) mode &= ~current_umask(); flags &= ~O_NOCTTY; @@ -770,7 +517,7 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry, args.out_args[0].value = &outentry; args.out_args[1].size = sizeof(outopen); args.out_args[1].value = &outopen; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err) goto out_free_ff; @@ -788,7 +535,7 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry, if (!inode) { flags &= ~(O_CREAT | O_EXCL | O_TRUNC); fuse_sync_release(NULL, ff, flags); - fuse_queue_forget(fm->fc, forget, outentry.nodeid, 1); + fuse_queue_forget(fc, forget, outentry.nodeid, 1); err = -ENOMEM; goto out_err; } @@ -803,10 +550,6 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry, } else { file->private_data = ff; fuse_finish_open(inode, file); - if (fm->fc->atomic_o_trunc && trunc) - truncate_pagecache(inode, 0); - else if (!(ff->open_flags & FOPEN_KEEP_CACHE)) - invalidate_inode_pages2(inode->i_mapping); } return err; @@ -868,7 +611,7 @@ no_open: /* * Code shared between mknod, mkdir, symlink and link */ -static int create_new_entry(struct fuse_mount *fm, struct fuse_args *args, +static int create_new_entry(struct fuse_conn *fc, struct fuse_args *args, struct inode *dir, struct dentry *entry, umode_t mode) { @@ -890,7 +633,7 @@ static int create_new_entry(struct fuse_mount *fm, struct fuse_args *args, args->out_numargs = 1; args->out_args[0].size = sizeof(outarg); args->out_args[0].value = &outarg; - err = fuse_simple_request(fm, args); + err = fuse_simple_request(fc, args); if (err) goto out_put_forget_req; @@ -904,7 +647,7 @@ static int create_new_entry(struct fuse_mount *fm, struct fuse_args *args, inode = fuse_iget(dir->i_sb, outarg.nodeid, outarg.generation, &outarg.attr, entry_attr_timeout(&outarg), 0); if (!inode) { - fuse_queue_forget(fm->fc, forget, outarg.nodeid, 1); + fuse_queue_forget(fc, forget, outarg.nodeid, 1); return -ENOMEM; } kfree(forget); @@ -932,21 +675,10 @@ static int fuse_mknod(struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev) { struct fuse_mknod_in inarg; - struct fuse_mount *fm = get_fuse_mount(dir); + struct fuse_conn *fc = get_fuse_conn(dir); FUSE_ARGS(args); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_mknod_in, - fuse_mknod_initialize, fuse_mknod_backing, - fuse_mknod_finalize, - dir, entry, mode, rdev); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - - if (!fm->fc->dont_mask) + if (!fc->dont_mask) mode &= ~current_umask(); memset(&inarg, 0, sizeof(inarg)); @@ -959,7 +691,7 @@ static int fuse_mknod(struct inode *dir, struct dentry *entry, umode_t mode, args.in_args[0].value = &inarg; args.in_args[1].size = entry->d_name.len + 1; args.in_args[1].value = entry->d_name.name; - return create_new_entry(fm, &args, dir, entry, mode); + return create_new_entry(fc, &args, dir, entry, mode); } static int fuse_create(struct inode *dir, struct dentry *entry, umode_t mode, @@ -971,21 +703,10 @@ static int fuse_create(struct inode *dir, struct dentry *entry, umode_t mode, static int fuse_mkdir(struct inode *dir, struct dentry *entry, umode_t mode) { struct fuse_mkdir_in inarg; - struct fuse_mount *fm = get_fuse_mount(dir); + struct fuse_conn *fc = get_fuse_conn(dir); FUSE_ARGS(args); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_mkdir_in, - fuse_mkdir_initialize, fuse_mkdir_backing, - fuse_mkdir_finalize, - dir, entry, mode); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - - if (!fm->fc->dont_mask) + if (!fc->dont_mask) mode &= ~current_umask(); memset(&inarg, 0, sizeof(inarg)); @@ -997,41 +718,23 @@ static int fuse_mkdir(struct inode *dir, struct dentry *entry, umode_t mode) args.in_args[0].value = &inarg; args.in_args[1].size = entry->d_name.len + 1; args.in_args[1].value = entry->d_name.name; - return create_new_entry(fm, &args, dir, entry, S_IFDIR); + return create_new_entry(fc, &args, dir, entry, S_IFDIR); } static int fuse_symlink(struct inode *dir, struct dentry *entry, const char *link) { - struct fuse_mount *fm = get_fuse_mount(dir); + struct fuse_conn *fc = get_fuse_conn(dir); unsigned len = strlen(link) + 1; FUSE_ARGS(args); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_dummy_io, - fuse_symlink_initialize, fuse_symlink_backing, - fuse_symlink_finalize, - dir, entry, link, len); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - args.opcode = FUSE_SYMLINK; args.in_numargs = 2; args.in_args[0].size = entry->d_name.len + 1; args.in_args[0].value = entry->d_name.name; args.in_args[1].size = len; args.in_args[1].value = link; - return create_new_entry(fm, &args, dir, entry, S_IFLNK); -} - -void fuse_flush_time_update(struct inode *inode) -{ - int err = sync_inode_metadata(inode, 1); - - mapping_set_error(inode->i_mapping, err); + return create_new_entry(fc, &args, dir, entry, S_IFLNK); } void fuse_update_ctime(struct inode *inode) @@ -1039,45 +742,30 @@ void fuse_update_ctime(struct inode *inode) if (!IS_NOCMTIME(inode)) { inode->i_ctime = current_time(inode); mark_inode_dirty_sync(inode); - fuse_flush_time_update(inode); } } static int fuse_unlink(struct inode *dir, struct dentry *entry) { int err; - struct fuse_mount *fm = get_fuse_mount(dir); + struct fuse_conn *fc = get_fuse_conn(dir); FUSE_ARGS(args); if (fuse_is_bad(dir)) return -EIO; -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_dummy_io, - fuse_unlink_initialize, - fuse_unlink_backing, - fuse_unlink_finalize, - dir, entry); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - args.opcode = FUSE_UNLINK; args.nodeid = get_node_id(dir); args.in_numargs = 1; args.in_args[0].size = entry->d_name.len + 1; args.in_args[0].value = entry->d_name.name; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (!err) { struct inode *inode = d_inode(entry); struct fuse_inode *fi = get_fuse_inode(inode); spin_lock(&fi->lock); - fi->attr_version = atomic64_inc_return(&fm->fc->attr_version); + fi->attr_version = atomic64_inc_return(&fc->attr_version); /* * If i_nlink == 0 then unlink doesn't make sense, yet this can * happen if userspace filesystem is careless. It would be @@ -1099,32 +787,18 @@ static int fuse_unlink(struct inode *dir, struct dentry *entry) static int fuse_rmdir(struct inode *dir, struct dentry *entry) { int err; - struct fuse_mount *fm = get_fuse_mount(dir); + struct fuse_conn *fc = get_fuse_conn(dir); FUSE_ARGS(args); if (fuse_is_bad(dir)) return -EIO; -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_dummy_io, - fuse_rmdir_initialize, - fuse_rmdir_backing, - fuse_rmdir_finalize, - dir, entry); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - args.opcode = FUSE_RMDIR; args.nodeid = get_node_id(dir); args.in_numargs = 1; args.in_args[0].size = entry->d_name.len + 1; args.in_args[0].value = entry->d_name.name; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (!err) { clear_nlink(d_inode(entry)); fuse_dir_changed(dir); @@ -1140,7 +814,7 @@ static int fuse_rename_common(struct inode *olddir, struct dentry *oldent, { int err; struct fuse_rename2_in inarg; - struct fuse_mount *fm = get_fuse_mount(olddir); + struct fuse_conn *fc = get_fuse_conn(olddir); FUSE_ARGS(args); memset(&inarg, 0, argsize); @@ -1155,7 +829,7 @@ static int fuse_rename_common(struct inode *olddir, struct dentry *oldent, args.in_args[1].value = oldent->d_name.name; args.in_args[2].size = newent->d_name.len + 1; args.in_args[2].value = newent->d_name.name; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (!err) { /* ctime changes */ fuse_invalidate_attr(d_inode(oldent)); @@ -1200,22 +874,10 @@ static int fuse_rename2(struct inode *olddir, struct dentry *oldent, if (fuse_is_bad(olddir)) return -EIO; - if (flags & ~(RENAME_NOREPLACE | RENAME_EXCHANGE | RENAME_WHITEOUT)) + if (flags & ~(RENAME_NOREPLACE | RENAME_EXCHANGE)) return -EINVAL; if (flags) { -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(olddir, struct fuse_rename2_in, - fuse_rename2_initialize, fuse_rename2_backing, - fuse_rename2_finalize, - olddir, oldent, newdir, newent, flags); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - - /* TODO: how should this go with bpfs involved? */ if (fc->no_rename2 || fc->minor < 23) return -EINVAL; @@ -1227,17 +889,6 @@ static int fuse_rename2(struct inode *olddir, struct dentry *oldent, err = -EINVAL; } } else { -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(olddir, struct fuse_rename_in, - fuse_rename_initialize, fuse_rename_backing, - fuse_rename_finalize, - olddir, oldent, newdir, newent); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - err = fuse_rename_common(olddir, oldent, newdir, newent, 0, FUSE_RENAME, sizeof(struct fuse_rename_in)); @@ -1252,19 +903,9 @@ static int fuse_link(struct dentry *entry, struct inode *newdir, int err; struct fuse_link_in inarg; struct inode *inode = d_inode(entry); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_link_in, fuse_link_initialize, - fuse_link_backing, fuse_link_finalize, entry, - newdir, newent); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - memset(&inarg, 0, sizeof(inarg)); inarg.oldnodeid = get_node_id(inode); args.opcode = FUSE_LINK; @@ -1273,7 +914,7 @@ static int fuse_link(struct dentry *entry, struct inode *newdir, args.in_args[0].value = &inarg; args.in_args[1].size = newent->d_name.len + 1; args.in_args[1].value = newent->d_name.name; - err = create_new_entry(fm, &args, newdir, newent, inode->i_mode); + err = create_new_entry(fc, &args, newdir, newent, inode->i_mode); /* Contrary to "normal" filesystems it can happen that link makes two "logical" inodes point to the same "physical" inode. We invalidate the attributes of the old one, so it @@ -1284,7 +925,7 @@ static int fuse_link(struct dentry *entry, struct inode *newdir, struct fuse_inode *fi = get_fuse_inode(inode); spin_lock(&fi->lock); - fi->attr_version = atomic64_inc_return(&fm->fc->attr_version); + fi->attr_version = atomic64_inc_return(&fc->attr_version); if (likely(inode->i_nlink < UINT_MAX)) inc_nlink(inode); spin_unlock(&fi->lock); @@ -1296,7 +937,7 @@ static int fuse_link(struct dentry *entry, struct inode *newdir, return err; } -void fuse_fillattr(struct inode *inode, struct fuse_attr *attr, +static void fuse_fillattr(struct inode *inode, struct fuse_attr *attr, struct kstat *stat) { unsigned int blkbits; @@ -1341,11 +982,11 @@ static int fuse_do_getattr(struct inode *inode, struct kstat *stat, int err; struct fuse_getattr_in inarg; struct fuse_attr_out outarg; - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); u64 attr_version; - attr_version = fuse_get_attr_version(fm->fc); + attr_version = fuse_get_attr_version(fc); memset(&inarg, 0, sizeof(inarg)); memset(&outarg, 0, sizeof(outarg)); @@ -1364,14 +1005,24 @@ static int fuse_do_getattr(struct inode *inode, struct kstat *stat, args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); - if (!err) - err = finalize_attr(inode, &outarg, attr_version, stat); + err = fuse_simple_request(fc, &args); + if (!err) { + if (fuse_invalid_attr(&outarg.attr) || + (inode->i_mode ^ outarg.attr.mode) & S_IFMT) { + fuse_make_bad(inode); + err = -EIO; + } else { + fuse_change_attributes(inode, &outarg.attr, + attr_timeout(&outarg), + attr_version); + if (stat) + fuse_fillattr(inode, &outarg.attr, stat); + } + } return err; } static int fuse_update_get_attr(struct inode *inode, struct file *file, - const struct path *path, struct kstat *stat, u32 request_mask, unsigned int flags) { @@ -1379,17 +1030,6 @@ static int fuse_update_get_attr(struct inode *inode, struct file *file, int err = 0; bool sync; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_getattr_io, - fuse_getattr_initialize, fuse_getattr_backing, - fuse_getattr_finalize, - path->dentry, stat, request_mask, flags); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (flags & AT_STATX_FORCE_SYNC) sync = true; else if (flags & AT_STATX_DONT_SYNC) @@ -1414,11 +1054,11 @@ static int fuse_update_get_attr(struct inode *inode, struct file *file, int fuse_update_attributes(struct inode *inode, struct file *file) { /* Do *not* need to get atime for internal purposes */ - return fuse_update_get_attr(inode, file, &file->f_path, NULL, + return fuse_update_get_attr(inode, file, NULL, STATX_BASIC_STATS & ~STATX_ATIME, 0); } -int fuse_reverse_inval_entry(struct fuse_conn *fc, u64 parent_nodeid, +int fuse_reverse_inval_entry(struct super_block *sb, u64 parent_nodeid, u64 child_nodeid, struct qstr *name) { int err = -ENOTDIR; @@ -1426,7 +1066,7 @@ int fuse_reverse_inval_entry(struct fuse_conn *fc, u64 parent_nodeid, struct dentry *dir; struct dentry *entry; - parent = fuse_ilookup(fc, parent_nodeid, NULL); + parent = ilookup5(sb, parent_nodeid, fuse_inode_eq, &parent_nodeid); if (!parent) return -ENOENT; @@ -1518,24 +1158,14 @@ int fuse_allow_current_process(struct fuse_conn *fc) static int fuse_access(struct inode *inode, int mask) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_access_in inarg; int err; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_access_in, - fuse_access_initialize, fuse_access_backing, - fuse_access_finalize, inode, mask); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - BUG_ON(mask & MAY_NOT_BLOCK); - if (fm->fc->no_access) + if (fc->no_access) return 0; memset(&inarg, 0, sizeof(inarg)); @@ -1545,9 +1175,9 @@ static int fuse_access(struct inode *inode, int mask) args.in_numargs = 1; args.in_args[0].size = sizeof(inarg); args.in_args[0].value = &inarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) { - fm->fc->no_access = 1; + fc->no_access = 1; err = 0; } return err; @@ -1580,10 +1210,6 @@ static int fuse_permission(struct inode *inode, int mask) struct fuse_conn *fc = get_fuse_conn(inode); bool refreshed = false; int err = 0; - struct fuse_inode *fi = get_fuse_inode(inode); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; -#endif if (fuse_is_bad(inode)) return -EIO; @@ -1591,19 +1217,12 @@ static int fuse_permission(struct inode *inode, int mask) if (!fuse_allow_current_process(fc)) return -EACCES; -#ifdef CONFIG_FUSE_BPF - fer = fuse_bpf_backing(inode, struct fuse_access_in, - fuse_access_initialize, fuse_access_backing, - fuse_access_finalize, inode, mask); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - /* * If attributes are needed, refresh them before proceeding */ if (fc->default_permissions || ((mask & MAY_EXEC) && S_ISREG(inode->i_mode))) { + struct fuse_inode *fi = get_fuse_inode(inode); u32 perm_mask = STATX_MODE | STATX_UID | STATX_GID; if (perm_mask & READ_ONCE(fi->inval_mask) || @@ -1649,7 +1268,7 @@ static int fuse_permission(struct inode *inode, int mask) static int fuse_readlink_page(struct inode *inode, struct page *page) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_page_desc desc = { .length = PAGE_SIZE - 1 }; struct fuse_args_pages ap = { .num_pages = 1, @@ -1666,7 +1285,7 @@ static int fuse_readlink_page(struct inode *inode, struct page *page) ap.args.page_zeroing = true; ap.args.out_numargs = 1; ap.args.out_args[0].size = desc.length; - res = fuse_simple_request(fm, &ap.args); + res = fuse_simple_request(fc, &ap.args); fuse_invalidate_atime(inode); @@ -1693,21 +1312,6 @@ static const char *fuse_get_link(struct dentry *dentry, struct inode *inode, if (fuse_is_bad(inode)) goto out_err; -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - const char *out = NULL; - - fer = fuse_bpf_backing(inode, struct fuse_dummy_io, - fuse_get_link_initialize, - fuse_get_link_backing, - fuse_get_link_finalize, - inode, dentry, callback, &out); - if (fer.ret) - return fer.result ?: out; - } -#endif - if (fc->cache_symlinks) return page_get_link_raw(dentry, inode, callback); @@ -1742,6 +1346,7 @@ static int fuse_dir_open(struct inode *inode, struct file *file) static int fuse_dir_release(struct inode *inode, struct file *file) { fuse_release_common(file, true); + return 0; } @@ -1755,19 +1360,6 @@ static int fuse_dir_fsync(struct file *file, loff_t start, loff_t end, if (fuse_is_bad(inode)) return -EIO; -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_fsync_in, - fuse_dir_fsync_initialize, fuse_fsync_backing, - fuse_fsync_finalize, - file, start, end, datasync); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - if (fc->no_fsyncdir) return 0; @@ -1806,6 +1398,58 @@ static long fuse_dir_compat_ioctl(struct file *file, unsigned int cmd, FUSE_IOCTL_COMPAT | FUSE_IOCTL_DIR); } +static bool update_mtime(unsigned ivalid, bool trust_local_mtime) +{ + /* Always update if mtime is explicitly set */ + if (ivalid & ATTR_MTIME_SET) + return true; + + /* Or if kernel i_mtime is the official one */ + if (trust_local_mtime) + return true; + + /* If it's an open(O_TRUNC) or an ftruncate(), don't update */ + if ((ivalid & ATTR_SIZE) && (ivalid & (ATTR_OPEN | ATTR_FILE))) + return false; + + /* In all other cases update */ + return true; +} + +static void iattr_to_fattr(struct fuse_conn *fc, struct iattr *iattr, + struct fuse_setattr_in *arg, bool trust_local_cmtime) +{ + unsigned ivalid = iattr->ia_valid; + + if (ivalid & ATTR_MODE) + arg->valid |= FATTR_MODE, arg->mode = iattr->ia_mode; + if (ivalid & ATTR_UID) + arg->valid |= FATTR_UID, arg->uid = from_kuid(fc->user_ns, iattr->ia_uid); + if (ivalid & ATTR_GID) + arg->valid |= FATTR_GID, arg->gid = from_kgid(fc->user_ns, iattr->ia_gid); + if (ivalid & ATTR_SIZE) + arg->valid |= FATTR_SIZE, arg->size = iattr->ia_size; + if (ivalid & ATTR_ATIME) { + arg->valid |= FATTR_ATIME; + arg->atime = iattr->ia_atime.tv_sec; + arg->atimensec = iattr->ia_atime.tv_nsec; + if (!(ivalid & ATTR_ATIME_SET)) + arg->valid |= FATTR_ATIME_NOW; + } + if ((ivalid & ATTR_MTIME) && update_mtime(ivalid, trust_local_cmtime)) { + arg->valid |= FATTR_MTIME; + arg->mtime = iattr->ia_mtime.tv_sec; + arg->mtimensec = iattr->ia_mtime.tv_nsec; + if (!(ivalid & ATTR_MTIME_SET) && !trust_local_cmtime) + arg->valid |= FATTR_MTIME_NOW; + } + if ((ivalid & ATTR_CTIME) && trust_local_cmtime) { + arg->valid |= FATTR_CTIME; + arg->ctime = iattr->ia_ctime.tv_sec; + arg->ctimensec = iattr->ia_ctime.tv_nsec; + } +} + /* * Prevent concurrent writepages on inode * @@ -1869,7 +1513,7 @@ static void fuse_setattr_fill(struct fuse_conn *fc, struct fuse_args *args, */ int fuse_flush_times(struct inode *inode, struct fuse_file *ff) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_setattr_in inarg; struct fuse_attr_out outarg; @@ -1880,7 +1524,7 @@ int fuse_flush_times(struct inode *inode, struct fuse_file *ff) inarg.valid = FATTR_MTIME; inarg.mtime = inode->i_mtime.tv_sec; inarg.mtimensec = inode->i_mtime.tv_nsec; - if (fm->fc->minor >= 23) { + if (fc->minor >= 23) { inarg.valid |= FATTR_CTIME; inarg.ctime = inode->i_ctime.tv_sec; inarg.ctimensec = inode->i_ctime.tv_nsec; @@ -1889,9 +1533,9 @@ int fuse_flush_times(struct inode *inode, struct fuse_file *ff) inarg.valid |= FATTR_FH; inarg.fh = ff->fh; } - fuse_setattr_fill(fm->fc, &args, inode, &inarg, &outarg); + fuse_setattr_fill(fc, &args, inode, &inarg, &outarg); - return fuse_simple_request(fm, &args); + return fuse_simple_request(fc, &args); } /* @@ -1906,8 +1550,7 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, struct file *file) { struct inode *inode = d_inode(dentry); - struct fuse_mount *fm = get_fuse_mount(inode); - struct fuse_conn *fc = fm->fc; + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_inode *fi = get_fuse_inode(inode); FUSE_ARGS(args); struct fuse_setattr_in inarg; @@ -1917,17 +1560,6 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, loff_t oldsize; int err; bool trust_local_cmtime = is_wb && S_ISREG(inode->i_mode); - bool fault_blocked = false; - -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_setattr_io, - fuse_setattr_initialize, fuse_setattr_backing, - fuse_setattr_finalize, dentry, attr, file); - if (fer.ret) - return PTR_ERR(fer.result); -#endif if (!fc->default_permissions) attr->ia_valid |= ATTR_FORCE; @@ -1936,22 +1568,6 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, if (err) return err; - if (attr->ia_valid & ATTR_SIZE) { - if (WARN_ON(!S_ISREG(inode->i_mode))) - return -EIO; - is_truncate = true; - } - - if (FUSE_IS_DAX(inode) && is_truncate) { - down_write(&fi->i_mmap_sem); - fault_blocked = true; - err = fuse_dax_break_layouts(inode, 0, 0); - if (err) { - up_write(&fi->i_mmap_sem); - return err; - } - } - if (attr->ia_valid & ATTR_OPEN) { /* This is coming from open(..., ... | O_TRUNC); */ WARN_ON(!(attr->ia_valid & ATTR_SIZE)); @@ -1964,11 +1580,17 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, */ i_size_write(inode, 0); truncate_pagecache(inode, 0); - goto out; + return 0; } file = NULL; } + if (attr->ia_valid & ATTR_SIZE) { + if (WARN_ON(!S_ISREG(inode->i_mode))) + return -EIO; + is_truncate = true; + } + /* Flush dirty data/metadata before non-truncate SETATTR */ if (is_wb && S_ISREG(inode->i_mode) && attr->ia_valid & @@ -2003,7 +1625,7 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, inarg.lock_owner = fuse_lock_owner_id(fc, current->files); } fuse_setattr_fill(fc, &args, inode, &inarg, &outarg); - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err) { if (err == -EINTR) fuse_invalidate_attr(inode); @@ -2011,7 +1633,7 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, } if (fuse_invalid_attr(&outarg.attr) || - inode_wrong_type(inode, outarg.attr.mode)) { + (inode->i_mode ^ outarg.attr.mode) & S_IFMT) { fuse_make_bad(inode); err = -EIO; goto error; @@ -2051,10 +1673,6 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, } clear_bit(FUSE_I_SIZE_UNSTABLE, &fi->state); -out: - if (fault_blocked) - up_write(&fi->i_mmap_sem); - return 0; error: @@ -2062,9 +1680,6 @@ error: fuse_release_nowrite(inode); clear_bit(FUSE_I_SIZE_UNSTABLE, &fi->state); - - if (fault_blocked) - up_write(&fi->i_mmap_sem); return err; } @@ -2092,22 +1707,11 @@ static int fuse_setattr(struct dentry *entry, struct iattr *attr) * This should be done on write(), truncate() and chown(). */ if (!fc->handle_killpriv) { -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - /* * ia_mode calculation may have used stale i_mode. * Refresh and recalculate. */ - fer = fuse_bpf_backing(inode, struct fuse_getattr_io, - fuse_getattr_initialize, fuse_getattr_backing, - fuse_getattr_finalize, - entry, NULL, 0, 0); - if (fer.ret) - ret = PTR_ERR(fer.result); - else -#endif - ret = fuse_do_getattr(inode, NULL, file); + ret = fuse_do_getattr(inode, NULL, file); if (ret) return ret; @@ -2150,21 +1754,10 @@ static int fuse_getattr(const struct path *path, struct kstat *stat, if (fuse_is_bad(inode)) return -EIO; - if (!fuse_allow_current_process(fc)) { - if (!request_mask) { - /* - * If user explicitly requested *nothing* then don't - * error out, but return st_dev only. - */ - stat->result_mask = 0; - stat->dev = inode->i_sb->s_dev; - return 0; - } + if (!fuse_allow_current_process(fc)) return -EACCES; - } - return fuse_update_get_attr(inode, NULL, path, stat, request_mask, - flags); + return fuse_update_get_attr(inode, NULL, stat, request_mask, flags); } static const struct inode_operations fuse_dir_inode_operations = { diff --git a/fs/fuse/file.c b/fs/fuse/file.c index cb34aa80c4f8..8a715e80c486 100644 --- a/fs/fuse/file.c +++ b/fs/fuse/file.c @@ -8,7 +8,6 @@ #include "fuse_i.h" -#include #include #include #include @@ -33,7 +32,7 @@ static struct page **fuse_pages_alloc(unsigned int npages, gfp_t flags, return pages; } -static int fuse_send_open(struct fuse_mount *fm, u64 nodeid, struct file *file, +static int fuse_send_open(struct fuse_conn *fc, u64 nodeid, struct file *file, int opcode, struct fuse_open_out *outargp) { struct fuse_open_in inarg; @@ -41,7 +40,7 @@ static int fuse_send_open(struct fuse_mount *fm, u64 nodeid, struct file *file, memset(&inarg, 0, sizeof(inarg)); inarg.flags = file->f_flags & ~(O_CREAT | O_EXCL | O_NOCTTY); - if (!fm->fc->atomic_o_trunc) + if (!fc->atomic_o_trunc) inarg.flags &= ~O_TRUNC; args.opcode = opcode; args.nodeid = nodeid; @@ -52,7 +51,7 @@ static int fuse_send_open(struct fuse_mount *fm, u64 nodeid, struct file *file, args.out_args[0].size = sizeof(*outargp); args.out_args[0].value = outargp; - return fuse_simple_request(fm, &args); + return fuse_simple_request(fc, &args); } struct fuse_release_args { @@ -61,7 +60,7 @@ struct fuse_release_args { struct inode *inode; }; -struct fuse_file *fuse_file_alloc(struct fuse_mount *fm) +struct fuse_file *fuse_file_alloc(struct fuse_conn *fc) { struct fuse_file *ff; @@ -69,7 +68,7 @@ struct fuse_file *fuse_file_alloc(struct fuse_mount *fm) if (unlikely(!ff)) return NULL; - ff->fm = fm; + ff->fc = fc; ff->release_args = kzalloc(sizeof(*ff->release_args), GFP_KERNEL_ACCOUNT); if (!ff->release_args) { @@ -83,7 +82,7 @@ struct fuse_file *fuse_file_alloc(struct fuse_mount *fm) RB_CLEAR_NODE(&ff->polled_node); init_waitqueue_head(&ff->poll_wait); - ff->kh = atomic64_inc_return(&fm->fc->khctr); + ff->kh = atomic64_inc_return(&fc->khctr); return ff; } @@ -101,7 +100,7 @@ static struct fuse_file *fuse_file_get(struct fuse_file *ff) return ff; } -static void fuse_release_end(struct fuse_mount *fm, struct fuse_args *args, +static void fuse_release_end(struct fuse_conn *fc, struct fuse_args *args, int error) { struct fuse_release_args *ra = container_of(args, typeof(*ra), args); @@ -110,53 +109,34 @@ static void fuse_release_end(struct fuse_mount *fm, struct fuse_args *args, kfree(ra); } -static void fuse_file_put(struct inode *inode, struct fuse_file *ff, - bool sync, bool isdir) +static void fuse_file_put(struct fuse_file *ff, bool sync, bool isdir) { - struct fuse_args *args = &ff->release_args->args; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; -#endif + if (refcount_dec_and_test(&ff->count)) { + struct fuse_args *args = &ff->release_args->args; - if (!refcount_dec_and_test(&ff->count)) - return; - -#ifdef CONFIG_FUSE_BPF - fer = fuse_bpf_backing(inode, struct fuse_release_in, - fuse_release_initialize, fuse_release_backing, - fuse_release_finalize, - inode, ff); - if (fer.ret) { - fuse_release_end(ff->fm, args, 0); - } else -#endif - if (isdir ? ff->fm->fc->no_opendir : ff->fm->fc->no_open) { - /* Do nothing when client does not implement 'open' */ - fuse_release_end(ff->fm, args, 0); - } else if (sync) { - fuse_simple_request(ff->fm, args); - fuse_release_end(ff->fm, args, 0); - } else { - args->end = fuse_release_end; - if (fuse_simple_background(ff->fm, args, - GFP_KERNEL | __GFP_NOFAIL)) - fuse_release_end(ff->fm, args, -ENOTCONN); + if (isdir ? ff->fc->no_opendir : ff->fc->no_open) { + /* Do nothing when client does not implement 'open' */ + fuse_release_end(ff->fc, args, 0); + } else if (sync) { + fuse_simple_request(ff->fc, args); + fuse_release_end(ff->fc, args, 0); + } else { + args->end = fuse_release_end; + if (fuse_simple_background(ff->fc, args, + GFP_KERNEL | __GFP_NOFAIL)) + fuse_release_end(ff->fc, args, -ENOTCONN); + } + kfree(ff); } - kfree(ff); } -int fuse_do_open(struct fuse_mount *fm, u64 nodeid, struct file *file, +int fuse_do_open(struct fuse_conn *fc, u64 nodeid, struct file *file, bool isdir) { - struct fuse_conn *fc = fm->fc; struct fuse_file *ff; int opcode = isdir ? FUSE_OPENDIR : FUSE_OPEN; - if (file->private_data) { - ff = file->private_data; - file->private_data = NULL; - } else - ff = fuse_file_alloc(fm); + ff = fuse_file_alloc(fc); if (!ff) return -ENOMEM; @@ -167,7 +147,7 @@ int fuse_do_open(struct fuse_mount *fm, u64 nodeid, struct file *file, struct fuse_open_out outarg; int err; - err = fuse_send_open(fm, nodeid, file, opcode, &outarg); + err = fuse_send_open(fc, nodeid, file, opcode, &outarg); if (!err) { ff->fh = outarg.fh; ff->open_flags = outarg.open_flags; @@ -225,24 +205,25 @@ void fuse_finish_open(struct inode *inode, struct file *file) fi->attr_version = atomic64_inc_return(&fc->attr_version); i_size_write(inode, 0); spin_unlock(&fi->lock); + truncate_pagecache(inode, 0); fuse_invalidate_attr(inode); if (fc->writeback_cache) file_update_time(file); + } else if (!(ff->open_flags & FOPEN_KEEP_CACHE)) { + invalidate_inode_pages2(inode->i_mapping); } + if ((file->f_mode & FMODE_WRITE) && fc->writeback_cache) fuse_link_write_file(file); } int fuse_open_common(struct inode *inode, struct file *file, bool isdir) { - struct fuse_mount *fm = get_fuse_mount(inode); - struct fuse_conn *fc = fm->fc; + struct fuse_conn *fc = get_fuse_conn(inode); int err; bool is_wb_truncate = (file->f_flags & O_TRUNC) && fc->atomic_o_trunc && fc->writeback_cache; - bool dax_truncate = (file->f_flags & O_TRUNC) && - fc->atomic_o_trunc && FUSE_IS_DAX(inode); if (fuse_is_bad(inode)) return -EIO; @@ -251,53 +232,20 @@ int fuse_open_common(struct inode *inode, struct file *file, bool isdir) if (err) return err; -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_open_io, - fuse_open_initialize, - fuse_open_backing, - fuse_open_finalize, - inode, file, isdir); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - - if (is_wb_truncate || dax_truncate) + if (is_wb_truncate) { inode_lock(inode); - - if (dax_truncate) { - down_write(&get_fuse_inode(inode)->i_mmap_sem); - err = fuse_dax_break_layouts(inode, 0, 0); - if (err) - goto out_inode_unlock; + fuse_set_nowrite(inode); } - if (is_wb_truncate || dax_truncate) - fuse_set_nowrite(inode); + err = fuse_do_open(fc, get_node_id(inode), file, isdir); - err = fuse_do_open(fm, get_node_id(inode), file, isdir); if (!err) fuse_finish_open(inode, file); - if (is_wb_truncate || dax_truncate) + if (is_wb_truncate) { fuse_release_nowrite(inode); - if (!err) { - struct fuse_file *ff = file->private_data; - - if (fc->atomic_o_trunc && (file->f_flags & O_TRUNC)) - truncate_pagecache(inode, 0); - else if (!(ff->open_flags & FOPEN_KEEP_CACHE)) - invalidate_inode_pages2(inode->i_mapping); - } - if (dax_truncate) - up_write(&get_fuse_inode(inode)->i_mmap_sem); - -out_inode_unlock: - if (is_wb_truncate || dax_truncate) inode_unlock(inode); + } return err; } @@ -305,7 +253,7 @@ out_inode_unlock: static void fuse_prepare_release(struct fuse_inode *fi, struct fuse_file *ff, int flags, int opcode) { - struct fuse_conn *fc = ff->fm->fc; + struct fuse_conn *fc = ff->fc; struct fuse_release_args *ra = ff->release_args; /* Inode is NULL on error path of fuse_create_open() */ @@ -345,7 +293,7 @@ void fuse_release_common(struct file *file, bool isdir) if (ff->flock) { ra->inarg.release_flags |= FUSE_RELEASE_FLOCK_UNLOCK; - ra->inarg.lock_owner = fuse_lock_owner_id(ff->fm->fc, + ra->inarg.lock_owner = fuse_lock_owner_id(ff->fc, (fl_owner_t) file); } /* Hold inode until release is finished */ @@ -359,14 +307,8 @@ void fuse_release_common(struct file *file, bool isdir) * Make the release synchronous if this is a fuseblk mount, * synchronous RELEASE is allowed (and desirable) in this case * because the server can be trusted not to screw up. - * - * Always use the asynchronous file put because the current thread - * might be the fuse server. This can happen if a process starts some - * aio and closes the fd before the aio completes. Since aio takes its - * own ref to the file, the IO completion has to drop the ref, which is - * how the fuse server can end up closing its clients' files. */ - fuse_file_put(ra->inode, ff, false, isdir); + fuse_file_put(ff, ff->fc->destroy, isdir); } static int fuse_open(struct inode *inode, struct file *file) @@ -396,7 +338,7 @@ void fuse_sync_release(struct fuse_inode *fi, struct fuse_file *ff, int flags) * iput(NULL) is a no-op and since the refcount is 1 and everything's * synchronous, we are fine with not doing igrab() here" */ - fuse_file_put(&fi->inode, ff, true, false); + fuse_file_put(ff, true, false); } EXPORT_SYMBOL_GPL(fuse_sync_release); @@ -424,7 +366,7 @@ u64 fuse_lock_owner_id(struct fuse_conn *fc, fl_owner_t id) struct fuse_writepage_args { struct fuse_io_args ia; - struct rb_node writepages_entry; + struct list_head writepages_entry; struct list_head queue_entry; struct fuse_writepage_args *next; struct inode *inode; @@ -433,23 +375,17 @@ struct fuse_writepage_args { static struct fuse_writepage_args *fuse_find_writeback(struct fuse_inode *fi, pgoff_t idx_from, pgoff_t idx_to) { - struct rb_node *n; + struct fuse_writepage_args *wpa; - n = fi->writepages.rb_node; - - while (n) { - struct fuse_writepage_args *wpa; + list_for_each_entry(wpa, &fi->writepages, writepages_entry) { pgoff_t curr_index; - wpa = rb_entry(n, struct fuse_writepage_args, writepages_entry); WARN_ON(get_fuse_inode(wpa->inode) != fi); curr_index = wpa->ia.write.in.offset >> PAGE_SHIFT; - if (idx_from >= curr_index + wpa->ia.ap.num_pages) - n = n->rb_right; - else if (idx_to < curr_index) - n = n->rb_left; - else + if (idx_from < curr_index + wpa->ia.ap.num_pages && + curr_index <= idx_to) { return wpa; + } } return NULL; } @@ -509,26 +445,18 @@ static void fuse_sync_writes(struct inode *inode) static int fuse_flush(struct file *file, fl_owner_t id) { struct inode *inode = file_inode(file); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_file *ff = file->private_data; struct fuse_flush_in inarg; FUSE_ARGS(args); int err; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(file->f_inode, struct fuse_flush_in, - fuse_flush_initialize, fuse_flush_backing, - fuse_flush_finalize, - file, id); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fuse_is_bad(inode)) return -EIO; + if (fc->no_flush) + return 0; + err = write_inode_now(inode, 1); if (err) return err; @@ -541,13 +469,9 @@ static int fuse_flush(struct file *file, fl_owner_t id) if (err) return err; - err = 0; - if (fm->fc->no_flush) - goto inval_attr_out; - memset(&inarg, 0, sizeof(inarg)); inarg.fh = ff->fh; - inarg.lock_owner = fuse_lock_owner_id(fm->fc, id); + inarg.lock_owner = fuse_lock_owner_id(fc, id); args.opcode = FUSE_FLUSH; args.nodeid = get_node_id(inode); args.in_numargs = 1; @@ -555,19 +479,11 @@ static int fuse_flush(struct file *file, fl_owner_t id) args.in_args[0].value = &inarg; args.force = true; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) { - fm->fc->no_flush = 1; + fc->no_flush = 1; err = 0; } - -inval_attr_out: - /* - * In memory i_blocks is not maintained by fuse, if writeback cache is - * enabled, i_blocks from cached attr may not be accurate. - */ - if (!err && fm->fc->writeback_cache) - fuse_invalidate_attr(inode); return err; } @@ -575,7 +491,7 @@ int fuse_fsync_common(struct file *file, loff_t start, loff_t end, int datasync, int opcode) { struct inode *inode = file->f_mapping->host; - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_file *ff = file->private_data; FUSE_ARGS(args); struct fuse_fsync_in inarg; @@ -588,7 +504,7 @@ int fuse_fsync_common(struct file *file, loff_t start, loff_t end, args.in_numargs = 1; args.in_args[0].size = sizeof(inarg); args.in_args[0].value = &inarg; - return fuse_simple_request(fm, &args); + return fuse_simple_request(fc, &args); } static int fuse_fsync(struct file *file, loff_t start, loff_t end, @@ -598,17 +514,6 @@ static int fuse_fsync(struct file *file, loff_t start, loff_t end, struct fuse_conn *fc = get_fuse_conn(inode); int err; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_fsync_in, - fuse_fsync_initialize, fuse_fsync_backing, - fuse_fsync_finalize, - file, start, end, datasync); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fuse_is_bad(inode)) return -EIO; @@ -774,7 +679,7 @@ static void fuse_io_free(struct fuse_io_args *ia) kfree(ia); } -static void fuse_aio_complete_req(struct fuse_mount *fm, struct fuse_args *args, +static void fuse_aio_complete_req(struct fuse_conn *fc, struct fuse_args *args, int err) { struct fuse_io_args *ia = container_of(args, typeof(*ia), ap.args); @@ -803,7 +708,7 @@ static void fuse_aio_complete_req(struct fuse_mount *fm, struct fuse_args *args, fuse_io_free(ia); } -static ssize_t fuse_async_req_send(struct fuse_mount *fm, +static ssize_t fuse_async_req_send(struct fuse_conn *fc, struct fuse_io_args *ia, size_t num_bytes) { ssize_t err; @@ -817,9 +722,9 @@ static ssize_t fuse_async_req_send(struct fuse_mount *fm, ia->ap.args.end = fuse_aio_complete_req; ia->ap.args.may_block = io->should_dirty; - err = fuse_simple_background(fm, &ia->ap.args, GFP_KERNEL); + err = fuse_simple_background(fc, &ia->ap.args, GFP_KERNEL); if (err) - fuse_aio_complete_req(fm, &ia->ap.args, err); + fuse_aio_complete_req(fc, &ia->ap.args, err); return num_bytes; } @@ -829,18 +734,18 @@ static ssize_t fuse_send_read(struct fuse_io_args *ia, loff_t pos, size_t count, { struct file *file = ia->io->iocb->ki_filp; struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; fuse_read_args_fill(ia, file, pos, count, FUSE_READ); if (owner != NULL) { ia->read.in.read_flags |= FUSE_READ_LOCKOWNER; - ia->read.in.lock_owner = fuse_lock_owner_id(fm->fc, owner); + ia->read.in.lock_owner = fuse_lock_owner_id(fc, owner); } if (ia->io->async) - return fuse_async_req_send(fm, ia, count); + return fuse_async_req_send(fc, ia, count); - return fuse_simple_request(fm, &ia->ap.args); + return fuse_simple_request(fc, &ia->ap.args); } static void fuse_read_update_size(struct inode *inode, loff_t size, @@ -850,7 +755,7 @@ static void fuse_read_update_size(struct inode *inode, loff_t size, struct fuse_inode *fi = get_fuse_inode(inode); spin_lock(&fi->lock); - if (attr_ver >= fi->attr_version && size < inode->i_size && + if (attr_ver == fi->attr_version && size < inode->i_size && !test_bit(FUSE_I_SIZE_UNSTABLE, &fi->state)) { fi->attr_version = atomic64_inc_return(&fc->attr_version); i_size_write(inode, size); @@ -886,7 +791,7 @@ static void fuse_short_read(struct inode *inode, u64 attr_ver, size_t num_read, static int fuse_do_readpage(struct file *file, struct page *page) { struct inode *inode = page->mapping->host; - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); loff_t pos = page_offset(page); struct fuse_page_desc desc = { .length = PAGE_SIZE }; struct fuse_io_args ia = { @@ -906,14 +811,14 @@ static int fuse_do_readpage(struct file *file, struct page *page) */ fuse_wait_on_page_writeback(inode, page->index); - attr_ver = fuse_get_attr_version(fm->fc); + attr_ver = fuse_get_attr_version(fc); /* Don't overflow end offset */ if (pos + (desc.length - 1) == LLONG_MAX) desc.length--; fuse_read_args_fill(&ia, file, pos, desc.length, FUSE_READ); - res = fuse_simple_request(fm, &ia.ap.args); + res = fuse_simple_request(fc, &ia.ap.args); if (res < 0) return res; /* @@ -943,7 +848,7 @@ static int fuse_readpage(struct file *file, struct page *page) return err; } -static void fuse_readpages_end(struct fuse_mount *fm, struct fuse_args *args, +static void fuse_readpages_end(struct fuse_conn *fc, struct fuse_args *args, int err) { int i; @@ -978,11 +883,8 @@ static void fuse_readpages_end(struct fuse_mount *fm, struct fuse_args *args, unlock_page(page); put_page(page); } - if (ia->ff) { - WARN_ON(!mapping); - fuse_file_put(mapping ? mapping->host : NULL, ia->ff, - false, false); - } + if (ia->ff) + fuse_file_put(ia->ff, false, false); fuse_io_free(ia); } @@ -990,7 +892,7 @@ static void fuse_readpages_end(struct fuse_mount *fm, struct fuse_args *args, static void fuse_send_readpages(struct fuse_io_args *ia, struct file *file) { struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; struct fuse_args_pages *ap = &ia->ap; loff_t pos = page_offset(ap->pages[0]); size_t count = ap->num_pages << PAGE_SHIFT; @@ -1009,18 +911,18 @@ static void fuse_send_readpages(struct fuse_io_args *ia, struct file *file) WARN_ON((loff_t) (pos + count) < 0); fuse_read_args_fill(ia, file, pos, count, FUSE_READ); - ia->read.attr_ver = fuse_get_attr_version(fm->fc); - if (fm->fc->async_read) { + ia->read.attr_ver = fuse_get_attr_version(fc); + if (fc->async_read) { ia->ff = fuse_file_get(ff); ap->args.end = fuse_readpages_end; - err = fuse_simple_background(fm, &ap->args, GFP_KERNEL); + err = fuse_simple_background(fc, &ap->args, GFP_KERNEL); if (!err) return; } else { - res = fuse_simple_request(fm, &ap->args); + res = fuse_simple_request(fc, &ap->args); err = res < 0 ? res : 0; } - fuse_readpages_end(fm, &ap->args, err); + fuse_readpages_end(fc, &ap->args, err); } struct fuse_fill_data { @@ -1039,19 +941,6 @@ static int fuse_readpages_fill(void *_data, struct page *page) struct inode *inode = data->inode; struct fuse_conn *fc = get_fuse_conn(inode); -#ifdef CONFIG_FUSE_BPF - /* - * Currently no meaningful readahead is possible with fuse-bpf within - * the kernel, so unless the daemon is aware of this file, ignore this - * call. - */ - if (!get_fuse_inode(inode)->nodeid) - return -EIO; -#endif - - if (fuse_is_bad(inode)) - return -EIO; - fuse_wait_on_page_writeback(inode, page->index); if (ap->num_pages && @@ -1148,7 +1037,7 @@ static void fuse_write_args_fill(struct fuse_io_args *ia, struct fuse_file *ff, args->opcode = FUSE_WRITE; args->nodeid = ff->nodeid; args->in_numargs = 2; - if (ff->fm->fc->minor < 9) + if (ff->fc->minor < 9) args->in_args[0].size = FUSE_COMPAT_WRITE_IN_SIZE; else args->in_args[0].size = sizeof(ia->write.in); @@ -1177,7 +1066,7 @@ static ssize_t fuse_send_write(struct fuse_io_args *ia, loff_t pos, struct kiocb *iocb = ia->io->iocb; struct file *file = iocb->ki_filp; struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; struct fuse_write_in *inarg = &ia->write.in; ssize_t err; @@ -1185,13 +1074,13 @@ static ssize_t fuse_send_write(struct fuse_io_args *ia, loff_t pos, inarg->flags = fuse_write_flags(iocb); if (owner != NULL) { inarg->write_flags |= FUSE_WRITE_LOCKOWNER; - inarg->lock_owner = fuse_lock_owner_id(fm->fc, owner); + inarg->lock_owner = fuse_lock_owner_id(fc, owner); } if (ia->io->async) - return fuse_async_req_send(fm, ia, count); + return fuse_async_req_send(fc, ia, count); - err = fuse_simple_request(fm, &ia->ap.args); + err = fuse_simple_request(fc, &ia->ap.args); if (!err && ia->write.out.size > count) err = -EIO; @@ -1222,7 +1111,7 @@ static ssize_t fuse_send_write_pages(struct fuse_io_args *ia, struct fuse_args_pages *ap = &ia->ap; struct file *file = iocb->ki_filp; struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; unsigned int offset, i; bool short_write; int err; @@ -1233,7 +1122,7 @@ static ssize_t fuse_send_write_pages(struct fuse_io_args *ia, fuse_write_args_fill(ia, ff, pos, count); ia->write.in.flags = fuse_write_flags(iocb); - err = fuse_simple_request(fm, &ap->args); + err = fuse_simple_request(fc, &ap->args); if (!err && ia->write.out.size > count) err = -EIO; @@ -1548,9 +1437,9 @@ static int fuse_get_user_pages(struct fuse_args_pages *ap, struct iov_iter *ii, ap->args.user_pages = true; if (write) - ap->args.in_pages = true; + ap->args.in_pages = 1; else - ap->args.out_pages = true; + ap->args.out_pages = 1; *nbytesp = nbytes; @@ -1565,7 +1454,7 @@ ssize_t fuse_direct_io(struct fuse_io_priv *io, struct iov_iter *iter, struct file *file = io->iocb->ki_filp; struct inode *inode = file->f_mapping->host; struct fuse_file *ff = file->private_data; - struct fuse_conn *fc = ff->fm->fc; + struct fuse_conn *fc = ff->fc; size_t nmax = write ? fc->max_write : fc->max_read; loff_t pos = *ppos; size_t count = iov_iter_count(iter); @@ -1705,28 +1594,10 @@ static ssize_t fuse_file_read_iter(struct kiocb *iocb, struct iov_iter *to) { struct file *file = iocb->ki_filp; struct fuse_file *ff = file->private_data; - struct inode *inode = file_inode(file); - if (fuse_is_bad(inode)) + if (fuse_is_bad(file_inode(file))) return -EIO; - if (FUSE_IS_DAX(inode)) - return fuse_dax_read_iter(iocb, to); - -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_file_read_iter_io, - fuse_file_read_iter_initialize, - fuse_file_read_iter_backing, - fuse_file_read_iter_finalize, - iocb, to); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - if (ff->passthrough.filp) return fuse_passthrough_read_iter(iocb, to); else if (!(ff->open_flags & FOPEN_DIRECT_IO)) @@ -1739,28 +1610,10 @@ static ssize_t fuse_file_write_iter(struct kiocb *iocb, struct iov_iter *from) { struct file *file = iocb->ki_filp; struct fuse_file *ff = file->private_data; - struct inode *inode = file_inode(file); - if (fuse_is_bad(inode)) + if (fuse_is_bad(file_inode(file))) return -EIO; - if (FUSE_IS_DAX(inode)) - return fuse_dax_write_iter(iocb, from); - -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_file_write_iter_io, - fuse_file_write_iter_initialize, - fuse_file_write_iter_backing, - fuse_file_write_iter_finalize, - iocb, from); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - if (ff->passthrough.filp) return fuse_passthrough_write_iter(iocb, from); else if (!(ff->open_flags & FOPEN_DIRECT_IO)) @@ -1778,13 +1631,13 @@ static void fuse_writepage_free(struct fuse_writepage_args *wpa) __free_page(ap->pages[i]); if (wpa->ia.ff) - fuse_file_put(wpa->inode, wpa->ia.ff, false, false); + fuse_file_put(wpa->ia.ff, false, false); kfree(ap->pages); kfree(wpa); } -static void fuse_writepage_finish(struct fuse_mount *fm, +static void fuse_writepage_finish(struct fuse_conn *fc, struct fuse_writepage_args *wpa) { struct fuse_args_pages *ap = &wpa->ia.ap; @@ -1793,6 +1646,7 @@ static void fuse_writepage_finish(struct fuse_mount *fm, struct backing_dev_info *bdi = inode_to_bdi(inode); int i; + list_del(&wpa->writepages_entry); for (i = 0; i < ap->num_pages; i++) { dec_wb_stat(&bdi->wb, WB_WRITEBACK); dec_node_page_state(ap->pages[i], NR_WRITEBACK_TEMP); @@ -1802,7 +1656,7 @@ static void fuse_writepage_finish(struct fuse_mount *fm, } /* Called under fi->lock, may release and reacquire it */ -static void fuse_send_writepage(struct fuse_mount *fm, +static void fuse_send_writepage(struct fuse_conn *fc, struct fuse_writepage_args *wpa, loff_t size) __releases(fi->lock) __acquires(fi->lock) @@ -1828,10 +1682,10 @@ __acquires(fi->lock) args->force = true; args->nocreds = true; - err = fuse_simple_background(fm, args, GFP_ATOMIC); + err = fuse_simple_background(fc, args, GFP_ATOMIC); if (err == -ENOMEM) { spin_unlock(&fi->lock); - err = fuse_simple_background(fm, args, GFP_NOFS | __GFP_NOFAIL); + err = fuse_simple_background(fc, args, GFP_NOFS | __GFP_NOFAIL); spin_lock(&fi->lock); } @@ -1843,8 +1697,7 @@ __acquires(fi->lock) out_free: fi->writectr--; - rb_erase(&wpa->writepages_entry, &fi->writepages); - fuse_writepage_finish(fm, wpa); + fuse_writepage_finish(fc, wpa); spin_unlock(&fi->lock); /* After rb_erase() aux request list is private */ @@ -1874,7 +1727,7 @@ void fuse_flush_writepages(struct inode *inode) __releases(fi->lock) __acquires(fi->lock) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_inode *fi = get_fuse_inode(inode); loff_t crop = i_size_read(inode); struct fuse_writepage_args *wpa; @@ -1883,76 +1736,29 @@ __acquires(fi->lock) wpa = list_entry(fi->queued_writes.next, struct fuse_writepage_args, queue_entry); list_del_init(&wpa->queue_entry); - fuse_send_writepage(fm, wpa, crop); + fuse_send_writepage(fc, wpa, crop); } } -static struct fuse_writepage_args *fuse_insert_writeback(struct rb_root *root, - struct fuse_writepage_args *wpa) -{ - pgoff_t idx_from = wpa->ia.write.in.offset >> PAGE_SHIFT; - pgoff_t idx_to = idx_from + wpa->ia.ap.num_pages - 1; - struct rb_node **p = &root->rb_node; - struct rb_node *parent = NULL; - - WARN_ON(!wpa->ia.ap.num_pages); - while (*p) { - struct fuse_writepage_args *curr; - pgoff_t curr_index; - - parent = *p; - curr = rb_entry(parent, struct fuse_writepage_args, - writepages_entry); - WARN_ON(curr->inode != wpa->inode); - curr_index = curr->ia.write.in.offset >> PAGE_SHIFT; - - if (idx_from >= curr_index + curr->ia.ap.num_pages) - p = &(*p)->rb_right; - else if (idx_to < curr_index) - p = &(*p)->rb_left; - else - return curr; - } - - rb_link_node(&wpa->writepages_entry, parent, p); - rb_insert_color(&wpa->writepages_entry, root); - return NULL; -} - -static void tree_insert(struct rb_root *root, struct fuse_writepage_args *wpa) -{ - WARN_ON(fuse_insert_writeback(root, wpa)); -} - -static void fuse_writepage_end(struct fuse_mount *fm, struct fuse_args *args, +static void fuse_writepage_end(struct fuse_conn *fc, struct fuse_args *args, int error) { struct fuse_writepage_args *wpa = container_of(args, typeof(*wpa), ia.ap.args); struct inode *inode = wpa->inode; struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_conn *fc = get_fuse_conn(inode); mapping_set_error(inode->i_mapping, error); - /* - * A writeback finished and this might have updated mtime/ctime on - * server making local mtime/ctime stale. Hence invalidate attrs. - * Do this only if writeback_cache is not enabled. If writeback_cache - * is enabled, we trust local ctime/mtime. - */ - if (!fc->writeback_cache) - fuse_invalidate_attr(inode); spin_lock(&fi->lock); - rb_erase(&wpa->writepages_entry, &fi->writepages); while (wpa->next) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_write_in *inarg = &wpa->ia.write.in; struct fuse_writepage_args *next = wpa->next; wpa->next = next->next; next->next = NULL; next->ia.ff = fuse_file_get(wpa->ia.ff); - tree_insert(&fi->writepages, next); + list_add(&next->writepages_entry, &fi->writepages); /* * Skip fuse_flush_writepages() to make it easy to crop requests @@ -1977,10 +1783,10 @@ static void fuse_writepage_end(struct fuse_mount *fm, struct fuse_args *args, * no invocations of fuse_writepage_end() while we're in * fuse_set_nowrite..fuse_release_nowrite section. */ - fuse_send_writepage(fm, next, inarg->offset + inarg->size); + fuse_send_writepage(fc, next, inarg->offset + inarg->size); } fi->writectr--; - fuse_writepage_finish(fm, wpa); + fuse_writepage_finish(fc, wpa); spin_unlock(&fi->lock); fuse_writepage_free(wpa); } @@ -2016,33 +1822,10 @@ int fuse_write_inode(struct inode *inode, struct writeback_control *wbc) struct fuse_file *ff; int err; - /** - * TODO - fully understand why this is necessary - * - * With fuse-bpf, fsstress fails if rename is enabled without this - * - * We are getting writes here on directory inodes, which do not have an - * initialized file list so crash. - * - * The question is why we are getting those writes - */ - if (!S_ISREG(inode->i_mode)) - return 0; - /* - * Inode is always written before the last reference is dropped and - * hence this should not be reached from reclaim. - * - * Writing back the inode from reclaim can deadlock if the request - * processing itself needs an allocation. Allocations triggering - * reclaim while serving a request can't be prevented, because it can - * involve any number of unrelated userspace processes. - */ - WARN_ON(wbc->for_reclaim); - ff = __fuse_write_file_get(fc, fi); err = fuse_flush_times(inode, ff); if (ff) - fuse_file_put(inode, ff, false, false); + fuse_file_put(ff, false, false); return err; } @@ -2110,7 +1893,7 @@ static int fuse_writepage_locked(struct page *page) inc_node_page_state(tmp_page, NR_WRITEBACK_TEMP); spin_lock(&fi->lock); - tree_insert(&fi->writepages, wpa); + list_add(&wpa->writepages_entry, &fi->writepages); list_add_tail(&wpa->queue_entry, &fi->queued_writes); fuse_flush_writepages(inode); spin_unlock(&fi->lock); @@ -2205,14 +1988,14 @@ static void fuse_writepages_send(struct fuse_fill_wb_data *data) } /* - * Check under fi->lock if the page is under writeback, and insert it onto the - * rb_tree if not. Otherwise iterate auxiliary write requests, to see if there's + * First recheck under fi->lock if the offending offset is still under + * writeback. If yes, then iterate auxiliary write requests, to see if there's * one already added for a page at this offset. If there's none, then insert * this new request onto the auxiliary list, otherwise reuse the existing one by - * swapping the new temp page with the old one. + * copying the new page contents over to the old temporary page. */ -static bool fuse_writepage_add(struct fuse_writepage_args *new_wpa, - struct page *page) +static bool fuse_writepage_in_flight(struct fuse_writepage_args *new_wpa, + struct page *page) { struct fuse_inode *fi = get_fuse_inode(new_wpa->inode); struct fuse_writepage_args *tmp; @@ -2220,15 +2003,17 @@ static bool fuse_writepage_add(struct fuse_writepage_args *new_wpa, struct fuse_args_pages *new_ap = &new_wpa->ia.ap; WARN_ON(new_ap->num_pages != 0); - new_ap->num_pages = 1; spin_lock(&fi->lock); - old_wpa = fuse_insert_writeback(&fi->writepages, new_wpa); + list_del(&new_wpa->writepages_entry); + old_wpa = fuse_find_writeback(fi, page->index, page->index); if (!old_wpa) { + list_add(&new_wpa->writepages_entry, &fi->writepages); spin_unlock(&fi->lock); - return true; + return false; } + new_ap->num_pages = 1; for (tmp = old_wpa->next; tmp; tmp = tmp->next) { pgoff_t curr_index; @@ -2257,41 +2042,7 @@ static bool fuse_writepage_add(struct fuse_writepage_args *new_wpa, fuse_writepage_free(new_wpa); } - return false; -} - -static bool fuse_writepage_need_send(struct fuse_conn *fc, struct page *page, - struct fuse_args_pages *ap, - struct fuse_fill_wb_data *data) -{ - WARN_ON(!ap->num_pages); - - /* - * Being under writeback is unlikely but possible. For example direct - * read to an mmaped fuse file will set the page dirty twice; once when - * the pages are faulted with get_user_pages(), and then after the read - * completed. - */ - if (fuse_page_is_writeback(data->inode, page->index)) - return true; - - /* Reached max pages */ - if (ap->num_pages == fc->max_pages) - return true; - - /* Reached max write bytes */ - if ((ap->num_pages + 1) * PAGE_SIZE > fc->max_write) - return true; - - /* Discontinuity */ - if (data->orig_pages[ap->num_pages - 1]->index + 1 != page->index) - return true; - - /* Need to grow the pages array? If so, did the expansion fail? */ - if (ap->num_pages == data->max_pages && !fuse_pages_realloc(data)) - return true; - - return false; + return true; } static int fuse_writepages_fill(struct page *page, @@ -2304,6 +2055,7 @@ static int fuse_writepages_fill(struct page *page, struct fuse_inode *fi = get_fuse_inode(inode); struct fuse_conn *fc = get_fuse_conn(inode); struct page *tmp_page; + bool is_writeback; int err; if (!data->ff) { @@ -2313,9 +2065,25 @@ static int fuse_writepages_fill(struct page *page, goto out_unlock; } - if (wpa && fuse_writepage_need_send(fc, page, ap, data)) { + /* + * Being under writeback is unlikely but possible. For example direct + * read to an mmaped fuse file will set the page dirty twice; once when + * the pages are faulted with get_user_pages(), and then after the read + * completed. + */ + is_writeback = fuse_page_is_writeback(inode, page->index); + + if (wpa && ap->num_pages && + (is_writeback || ap->num_pages == fc->max_pages || + (ap->num_pages + 1) * PAGE_SIZE > fc->max_write || + data->orig_pages[ap->num_pages - 1]->index + 1 != page->index)) { fuse_writepages_send(data); data->wpa = NULL; + } else if (wpa && ap->num_pages == data->max_pages) { + if (!fuse_pages_realloc(data)) { + fuse_writepages_send(data); + data->wpa = NULL; + } } err = -ENOMEM; @@ -2353,6 +2121,12 @@ static int fuse_writepages_fill(struct page *page, ap->args.end = fuse_writepage_end; ap->num_pages = 0; wpa->inode = inode; + + spin_lock(&fi->lock); + list_add(&wpa->writepages_entry, &fi->writepages); + spin_unlock(&fi->lock); + + data->wpa = wpa; } set_page_writeback(page); @@ -2360,25 +2134,26 @@ static int fuse_writepages_fill(struct page *page, ap->pages[ap->num_pages] = tmp_page; ap->descs[ap->num_pages].offset = 0; ap->descs[ap->num_pages].length = PAGE_SIZE; - data->orig_pages[ap->num_pages] = page; inc_wb_stat(&inode_to_bdi(inode)->wb, WB_WRITEBACK); inc_node_page_state(tmp_page, NR_WRITEBACK_TEMP); err = 0; - if (data->wpa) { - /* - * Protected by fi->lock against concurrent access by - * fuse_page_is_writeback(). - */ - spin_lock(&fi->lock); - ap->num_pages++; - spin_unlock(&fi->lock); - } else if (fuse_writepage_add(wpa, page)) { - data->wpa = wpa; - } else { + if (is_writeback && fuse_writepage_in_flight(wpa, page)) { end_page_writeback(page); + data->wpa = NULL; + goto out_unlock; } + data->orig_pages[ap->num_pages] = page; + + /* + * Protected by fi->lock against concurrent access by + * fuse_page_is_writeback(). + */ + spin_lock(&fi->lock); + ap->num_pages++; + spin_unlock(&fi->lock); + out_unlock: unlock_page(page); @@ -2414,7 +2189,7 @@ static int fuse_writepages(struct address_space *mapping, fuse_writepages_send(&data); } if (data.ff) - fuse_file_put(inode, data.ff, false, false); + fuse_file_put(data.ff, false, false); kfree(data.orig_pages); out: @@ -2561,16 +2336,6 @@ static int fuse_file_mmap(struct file *file, struct vm_area_struct *vma) { struct fuse_file *ff = file->private_data; - /* DAX mmap is superior to direct_io mmap */ - if (FUSE_IS_DAX(file_inode(file))) - return fuse_dax_mmap(file, vma); - -#ifdef CONFIG_FUSE_BPF - /* TODO - this is simply passthrough, not a proper BPF filter */ - if (ff->backing_file) - return fuse_backing_mmap(file, vma); -#endif - if (ff->passthrough.filp) return fuse_passthrough_mmap(file, vma); @@ -2652,7 +2417,7 @@ static void fuse_lk_fill(struct fuse_args *args, struct file *file, static int fuse_getlk(struct file *file, struct file_lock *fl) { struct inode *inode = file_inode(file); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_lk_in inarg; struct fuse_lk_out outarg; @@ -2662,9 +2427,9 @@ static int fuse_getlk(struct file *file, struct file_lock *fl) args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (!err) - err = convert_fuse_file_lock(fm->fc, &outarg.lk, fl); + err = convert_fuse_file_lock(fc, &outarg.lk, fl); return err; } @@ -2672,12 +2437,12 @@ static int fuse_getlk(struct file *file, struct file_lock *fl) static int fuse_setlk(struct file *file, struct file_lock *fl, int flock) { struct inode *inode = file_inode(file); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_lk_in inarg; int opcode = (fl->fl_flags & FL_SLEEP) ? FUSE_SETLKW : FUSE_SETLK; struct pid *pid = fl->fl_type != F_UNLCK ? task_tgid(current) : NULL; - pid_t pid_nr = pid_nr_ns(pid, fm->fc->pid_ns); + pid_t pid_nr = pid_nr_ns(pid, fc->pid_ns); int err; if (fl->fl_lmops && fl->fl_lmops->lm_grant) { @@ -2690,7 +2455,7 @@ static int fuse_setlk(struct file *file, struct file_lock *fl, int flock) return 0; fuse_lk_fill(&args, file, fl, opcode, pid_nr, flock, &inarg); - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); /* locking is restartable */ if (err == -EINTR) @@ -2726,18 +2491,12 @@ static int fuse_file_flock(struct file *file, int cmd, struct file_lock *fl) { struct inode *inode = file_inode(file); struct fuse_conn *fc = get_fuse_conn(inode); - struct fuse_file *ff = file->private_data; int err; -#ifdef CONFIG_FUSE_BPF - /* TODO - this is simply passthrough, not a proper BPF filter */ - if (ff->backing_file) - return fuse_file_flock_backing(file, cmd, fl); -#endif - if (fc->no_flock) { err = locks_lock_file_wait(file, fl); } else { + struct fuse_file *ff = file->private_data; /* emulate flock with POSIX locks */ ff->flock = true; @@ -2750,13 +2509,13 @@ static int fuse_file_flock(struct file *file, int cmd, struct file_lock *fl) static sector_t fuse_bmap(struct address_space *mapping, sector_t block) { struct inode *inode = mapping->host; - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_bmap_in inarg; struct fuse_bmap_out outarg; int err; - if (!inode->i_sb->s_bdev || fm->fc->no_bmap) + if (!inode->i_sb->s_bdev || fc->no_bmap) return 0; memset(&inarg, 0, sizeof(inarg)); @@ -2770,9 +2529,9 @@ static sector_t fuse_bmap(struct address_space *mapping, sector_t block) args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) - fm->fc->no_bmap = 1; + fc->no_bmap = 1; return err ? 0 : outarg.block; } @@ -2780,7 +2539,7 @@ static sector_t fuse_bmap(struct address_space *mapping, sector_t block) static loff_t fuse_lseek(struct file *file, loff_t offset, int whence) { struct inode *inode = file->f_mapping->host; - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_file *ff = file->private_data; FUSE_ARGS(args); struct fuse_lseek_in inarg = { @@ -2791,7 +2550,7 @@ static loff_t fuse_lseek(struct file *file, loff_t offset, int whence) struct fuse_lseek_out outarg; int err; - if (fm->fc->no_lseek) + if (fc->no_lseek) goto fallback; args.opcode = FUSE_LSEEK; @@ -2802,10 +2561,10 @@ static loff_t fuse_lseek(struct file *file, loff_t offset, int whence) args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err) { if (err == -ENOSYS) { - fm->fc->no_lseek = 1; + fc->no_lseek = 1; goto fallback; } return err; @@ -2825,17 +2584,6 @@ static loff_t fuse_file_llseek(struct file *file, loff_t offset, int whence) { loff_t retval; struct inode *inode = file_inode(file); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_lseek_io, - fuse_lseek_initialize, - fuse_lseek_backing, - fuse_lseek_finalize, - file, offset, whence); - if (fer.ret) - return PTR_ERR(fer.result); -#endif switch (whence) { case SEEK_SET: @@ -3002,7 +2750,7 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg, unsigned int flags) { struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; struct fuse_ioctl_in inarg = { .fh = ff->fh, .cmd = cmd, @@ -3035,12 +2783,12 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg, BUILD_BUG_ON(sizeof(struct fuse_ioctl_iovec) * FUSE_IOCTL_MAX_IOV > PAGE_SIZE); err = -ENOMEM; - ap.pages = fuse_pages_alloc(fm->fc->max_pages, GFP_KERNEL, &ap.descs); + ap.pages = fuse_pages_alloc(fc->max_pages, GFP_KERNEL, &ap.descs); iov_page = (struct iovec *) __get_free_page(GFP_KERNEL); if (!ap.pages || !iov_page) goto out; - fuse_page_descs_length_init(ap.descs, 0, fm->fc->max_pages); + fuse_page_descs_length_init(ap.descs, 0, fc->max_pages); /* * If restricted, initialize IO parameters as encoded in @cmd. @@ -3085,7 +2833,7 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg, /* make sure there are enough buffer pages and init request with them */ err = -ENOMEM; - if (max_pages > fm->fc->max_pages) + if (max_pages > fc->max_pages) goto out; while (ap.num_pages < max_pages) { ap.pages[ap.num_pages] = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); @@ -3122,7 +2870,7 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg, ap.args.out_pages = true; ap.args.out_argvar = true; - transferred = fuse_simple_request(fm, &ap.args); + transferred = fuse_simple_request(fc, &ap.args); err = transferred; if (transferred < 0) goto out; @@ -3150,7 +2898,7 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg, goto out; vaddr = kmap_atomic(ap.pages[0]); - err = fuse_copy_ioctl_iovec(fm->fc, iov_page, vaddr, + err = fuse_copy_ioctl_iovec(fc, iov_page, vaddr, transferred, in_iovs + out_iovs, (flags & FUSE_IOCTL_COMPAT) != 0); kunmap_atomic(vaddr); @@ -3160,11 +2908,11 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg, in_iov = iov_page; out_iov = in_iov + in_iovs; - err = fuse_verify_ioctl_iov(fm->fc, in_iov, in_iovs); + err = fuse_verify_ioctl_iov(fc, in_iov, in_iovs); if (err) goto out; - err = fuse_verify_ioctl_iov(fm->fc, out_iov, out_iovs); + err = fuse_verify_ioctl_iov(fc, out_iov, out_iovs); if (err) goto out; @@ -3205,15 +2953,6 @@ long fuse_ioctl_common(struct file *file, unsigned int cmd, if (fuse_is_bad(inode)) return -EIO; -#ifdef CONFIG_FUSE_BPF - { - struct fuse_file *ff = file->private_data; - - /* TODO - this is simply passthrough, not a proper BPF filter */ - if (ff->backing_file) - return fuse_backing_ioctl(file, cmd, arg, flags); - } -#endif return fuse_do_ioctl(file, cmd, arg, flags); } @@ -3283,13 +3022,13 @@ static void fuse_register_polled_file(struct fuse_conn *fc, __poll_t fuse_file_poll(struct file *file, poll_table *wait) { struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; struct fuse_poll_in inarg = { .fh = ff->fh, .kh = ff->kh }; struct fuse_poll_out outarg; FUSE_ARGS(args); int err; - if (fm->fc->no_poll) + if (fc->no_poll) return DEFAULT_POLLMASK; poll_wait(file, &ff->poll_wait, wait); @@ -3301,7 +3040,7 @@ __poll_t fuse_file_poll(struct file *file, poll_table *wait) */ if (waitqueue_active(&ff->poll_wait)) { inarg.flags |= FUSE_POLL_SCHEDULE_NOTIFY; - fuse_register_polled_file(fm->fc, ff); + fuse_register_polled_file(fc, ff); } args.opcode = FUSE_POLL; @@ -3312,12 +3051,12 @@ __poll_t fuse_file_poll(struct file *file, poll_table *wait) args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (!err) return demangle_poll(outarg.revents); if (err == -ENOSYS) { - fm->fc->no_poll = 1; + fc->no_poll = 1; return DEFAULT_POLLMASK; } return EPOLLERR; @@ -3403,13 +3142,13 @@ fuse_direct_IO(struct kiocb *iocb, struct iov_iter *iter) * By default, we want to optimize all I/Os with async request * submission to the client filesystem if supported. */ - io->async = ff->fm->fc->async_dio; + io->async = ff->fc->async_dio; io->iocb = iocb; io->blocking = is_sync_kiocb(iocb); /* optimization for short read */ if (io->async && !io->write && offset + count > i_size) { - iov_iter_truncate(iter, fuse_round_up(ff->fm->fc, i_size - offset)); + iov_iter_truncate(iter, fuse_round_up(ff->fc, i_size - offset)); shortened = count - iov_iter_count(iter); count -= shortened; } @@ -3479,7 +3218,7 @@ static long fuse_file_fallocate(struct file *file, int mode, loff_t offset, struct fuse_file *ff = file->private_data; struct inode *inode = file_inode(file); struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; FUSE_ARGS(args); struct fuse_fallocate_in inarg = { .fh = ff->fh, @@ -3488,36 +3227,13 @@ static long fuse_file_fallocate(struct file *file, int mode, loff_t offset, .mode = mode }; int err; - bool block_faults = FUSE_IS_DAX(inode) && - (!(mode & FALLOC_FL_KEEP_SIZE) || - (mode & FALLOC_FL_PUNCH_HOLE)); - -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_fallocate_in, - fuse_file_fallocate_initialize, - fuse_file_fallocate_backing, - fuse_file_fallocate_finalize, - file, mode, offset, length); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (mode & ~(FALLOC_FL_KEEP_SIZE | FALLOC_FL_PUNCH_HOLE)) return -EOPNOTSUPP; - if (fm->fc->no_fallocate) + if (fc->no_fallocate) return -EOPNOTSUPP; inode_lock(inode); - if (block_faults) { - down_write(&fi->i_mmap_sem); - err = fuse_dax_break_layouts(inode, 0, 0); - if (err) - goto out; - } - if (mode & FALLOC_FL_PUNCH_HOLE) { loff_t endbyte = offset + length - 1; @@ -3545,9 +3261,9 @@ static long fuse_file_fallocate(struct file *file, int mode, loff_t offset, args.in_numargs = 1; args.in_args[0].size = sizeof(inarg); args.in_args[0].value = &inarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) { - fm->fc->no_fallocate = 1; + fc->no_fallocate = 1; err = -EOPNOTSUPP; } if (err) @@ -3557,7 +3273,7 @@ static long fuse_file_fallocate(struct file *file, int mode, loff_t offset, if (!(mode & FALLOC_FL_KEEP_SIZE)) { bool changed = fuse_write_update_size(inode, offset + length); - if (changed && fm->fc->writeback_cache) + if (changed && fc->writeback_cache) file_update_time(file); } @@ -3570,13 +3286,8 @@ out: if (!(mode & FALLOC_FL_KEEP_SIZE)) clear_bit(FUSE_I_SIZE_UNSTABLE, &fi->state); - if (block_faults) - up_write(&fi->i_mmap_sem); - inode_unlock(inode); - fuse_flush_time_update(inode); - return err; } @@ -3589,8 +3300,7 @@ static ssize_t __fuse_copy_file_range(struct file *file_in, loff_t pos_in, struct inode *inode_in = file_inode(file_in); struct inode *inode_out = file_inode(file_out); struct fuse_inode *fi_out = get_fuse_inode(inode_out); - struct fuse_mount *fm = ff_in->fm; - struct fuse_conn *fc = fm->fc; + struct fuse_conn *fc = ff_in->fc; FUSE_ARGS(args); struct fuse_copy_file_range_in inarg = { .fh_in = ff_in->fh, @@ -3608,18 +3318,6 @@ static ssize_t __fuse_copy_file_range(struct file *file_in, loff_t pos_in, bool is_unstable = (!fc->writeback_cache) && ((pos_out + len) > inode_out->i_size); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(file_in->f_inode, struct fuse_copy_file_range_io, - fuse_copy_file_range_initialize, - fuse_copy_file_range_backing, - fuse_copy_file_range_finalize, - file_in, pos_in, file_out, pos_out, len, flags); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fc->no_copy_file_range) return -EOPNOTSUPP; @@ -3671,7 +3369,7 @@ static ssize_t __fuse_copy_file_range(struct file *file_in, loff_t pos_in, args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) { fc->no_copy_file_range = 1; err = -EOPNOTSUPP; @@ -3729,7 +3427,6 @@ static const struct file_operations fuse_file_operations = { .release = fuse_release, .fsync = fuse_fsync, .lock = fuse_file_lock, - .get_unmapped_area = thp_get_unmapped_area, .flock = fuse_file_flock, .splice_read = generic_file_splice_read, .splice_write = iter_file_splice_write, @@ -3764,8 +3461,5 @@ void fuse_init_file_inode(struct inode *inode) INIT_LIST_HEAD(&fi->queued_writes); fi->writectr = 0; init_waitqueue_head(&fi->page_waitq); - fi->writepages = RB_ROOT; - - if (IS_ENABLED(CONFIG_FUSE_DAX)) - fuse_dax_inode_init(inode); + INIT_LIST_HEAD(&fi->writepages); } diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h index 97b44bbf5274..2eec57bb3707 100644 --- a/fs/fuse/fuse_i.h +++ b/fs/fuse/fuse_i.h @@ -13,8 +13,6 @@ # define pr_fmt(fmt) "fuse: " fmt #endif -#include -#include #include #include #include @@ -33,9 +31,6 @@ #include #include #include -#include - -#define FUSE_SUPER_MAGIC 0x65735546 /** Default max number of pages that can be used in a single read request */ #define FUSE_DEFAULT_MAX_PAGES_PER_REQ 32 @@ -68,63 +63,11 @@ struct fuse_forget_link { struct fuse_forget_link *next; }; -/** FUSE specific dentry data */ -#if BITS_PER_LONG < 64 || defined(CONFIG_FUSE_BPF) -struct fuse_dentry { - union { - u64 time; - struct rcu_head rcu; - }; - -#ifdef CONFIG_FUSE_BPF - struct path backing_path; - - /* bpf program *only* set for negative dentries */ - struct bpf_prog *bpf; -#endif -}; - -static inline struct fuse_dentry *get_fuse_dentry(const struct dentry *entry) -{ - return entry->d_fsdata; -} -#endif - -#ifdef CONFIG_FUSE_BPF -static inline void get_fuse_backing_path(const struct dentry *d, - struct path *path) -{ - struct fuse_dentry *di = get_fuse_dentry(d); - - if (!di) { - *path = (struct path) {}; - return; - } - - *path = di->backing_path; - path_get(path); -} -#endif - /** FUSE inode */ struct fuse_inode { /** Inode data */ struct inode inode; -#ifdef CONFIG_FUSE_BPF - /** - * Backing inode, if this inode is from a backing file system. - * If this is set, nodeid is 0. - */ - struct inode *backing_inode; - - /** - * bpf_prog, run on all operations to determine whether to pass through - * or handle in place - */ - struct bpf_prog *bpf; -#endif - /** Unique ID, which identifies the inode between userspace * and kernel */ u64 nodeid; @@ -168,7 +111,7 @@ struct fuse_inode { wait_queue_head_t page_waitq; /* List of writepage requestst (pending or sent) */ - struct rb_root writepages; + struct list_head writepages; }; /* readdir cache (directory only) */ @@ -205,20 +148,6 @@ struct fuse_inode { /** Lock to protect write related fields */ spinlock_t lock; - - /** - * Can't take inode lock in fault path (leads to circular dependency). - * Introduce another semaphore which can be taken in fault path and - * then other filesystem paths can take this to block faults. - */ - struct rw_semaphore i_mmap_sem; - -#ifdef CONFIG_FUSE_DAX - /* - * Dax specific inode data - */ - struct fuse_inode_dax *dax; -#endif }; /** FUSE inode state bits */ @@ -234,7 +163,6 @@ enum { }; struct fuse_conn; -struct fuse_mount; struct fuse_release_args; /** @@ -251,7 +179,7 @@ struct fuse_passthrough { /** FUSE specific file data */ struct fuse_file { /** Fuse connection for this file */ - struct fuse_mount *fm; + struct fuse_conn *fc; /* Argument space reserved for release */ struct fuse_release_args *release_args; @@ -296,14 +224,6 @@ struct fuse_file { /** Container for data related to the passthrough functionality */ struct fuse_passthrough passthrough; -#ifdef CONFIG_FUSE_BPF - /** - * TODO: Reconcile with passthrough file - * backing file when in bpf mode - */ - struct file *backing_file; -#endif - /** RB node to be linked on fuse_conn->polled_files */ struct rb_node polled_node; @@ -335,7 +255,6 @@ struct fuse_page_desc { struct fuse_args { uint64_t nodeid; uint32_t opcode; - uint32_t error_in; unsigned short in_numargs; unsigned short out_numargs; bool force:1; @@ -348,9 +267,9 @@ struct fuse_args { bool page_zeroing:1; bool page_replace:1; bool may_block:1; - struct fuse_in_arg in_args[FUSE_MAX_IN_ARGS]; - struct fuse_arg out_args[FUSE_MAX_OUT_ARGS]; - void (*end)(struct fuse_mount *fm, struct fuse_args *args, int error); + struct fuse_in_arg in_args[3]; + struct fuse_arg out_args[2]; + void (*end)(struct fuse_conn *fc, struct fuse_args *args, int error); /* Path used for completing d_canonical_path */ struct path *canonical_path; @@ -457,11 +376,10 @@ struct fuse_req { /** Used to wake up the task waiting for completion of request*/ wait_queue_head_t waitq; +#if IS_ENABLED(CONFIG_VIRTIO_FS) /** virtio-fs's physically contiguous buffer for in and out args */ void *argbuf; - - /** fuse_mount this request belongs to */ - struct fuse_mount *fm; +#endif }; struct fuse_iqueue; @@ -584,17 +502,10 @@ struct fuse_fs_context { bool destroy:1; bool no_control:1; bool no_force_umount:1; - bool legacy_opts_show:1; - bool dax:1; - bool no_daemon:1; + bool no_mount_options:1; unsigned int max_read; unsigned int blksize; const char *subtype; - struct bpf_prog *root_bpf; - struct file *root_dir; - - /* DAX device, may be NULL */ - struct dax_device *dax_dev; /* fuse_dev pointer to fill in, should contain NULL on entry */ void **fudptr; @@ -603,9 +514,9 @@ struct fuse_fs_context { /** * A Fuse connection. * - * This structure is created, when the root filesystem is mounted, and - * is destroyed, when the client device is closed and the last - * fuse_mount is destroyed. + * This structure is created, when the filesystem is mounted, and is + * destroyed, when the client device is closed and the filesystem is + * unmounted. */ struct fuse_conn { /** Lock protecting accessess to members of this structure */ @@ -640,9 +551,6 @@ struct fuse_conn { /** Maxmum number of pages that can be used in a single request */ unsigned int max_pages; - /** Constrain ->max_pages to this value during feature negotiation */ - unsigned int max_pages_limit; - /** Input queue */ struct fuse_iqueue iq; @@ -722,9 +630,6 @@ struct fuse_conn { /** cache READLINK responses in page cache */ unsigned cache_symlinks:1; - /* show legacy mount options */ - unsigned int legacy_opts_show:1; - /* * The following bitfields are only for optimization purposes * and hence races in setting them will not cause malfunction @@ -832,25 +737,22 @@ struct fuse_conn { /** Do not allow MNT_FORCE umount */ unsigned int no_force_umount:1; - /* Auto-mount submounts announced by the server */ - unsigned int auto_submounts:1; + /* Do not show mount options */ + unsigned int no_mount_options:1; /** Passthrough mode for read/write IO */ unsigned int passthrough:1; - /** BPF Only, no Daemon running */ - unsigned int no_daemon:1; - /** The number of requests waiting for completion */ atomic_t num_waiting; /** Negotiated minor version */ unsigned minor; - /** Entry on the fuse_mount_list */ + /** Entry on the fuse_conn_list */ struct list_head entry; - /** Device ID from the root super block */ + /** Device ID from super block */ dev_t dev; /** Dentries in the control filesystem */ @@ -868,23 +770,15 @@ struct fuse_conn { /** Called on final put */ void (*release)(struct fuse_conn *); - /** - * Read/write semaphore to hold when accessing the sb of any - * fuse_mount belonging to this connection - */ + /** Super block for this connection. */ + struct super_block *sb; + + /** Read/write semaphore to hold when accessing sb. */ struct rw_semaphore killsb; /** List of device instances belonging to this connection */ struct list_head devices; -#ifdef CONFIG_FUSE_DAX - /* Dax specific conn data, non-NULL if DAX is enabled */ - struct fuse_conn_dax *dax; -#endif - - /** List of filesystems using this connection */ - struct list_head mounts; - /** IDR for passthrough requests */ struct idr passthrough_req; @@ -892,52 +786,14 @@ struct fuse_conn { spinlock_t passthrough_req_lock; }; -/* - * Represents a mounted filesystem, potentially a submount. - * - * This object allows sharing a fuse_conn between separate mounts to - * allow submounts with dedicated superblocks and thus separate device - * IDs. - */ -struct fuse_mount { - /* Underlying (potentially shared) connection to the FUSE server */ - struct fuse_conn *fc; - - /* Refcount */ - refcount_t count; - - /* - * Super block for this connection (fc->killsb must be held when - * accessing this). - */ - struct super_block *sb; - - /* Entry on fc->mounts */ - struct list_head fc_entry; -}; - -static inline struct fuse_mount *get_fuse_mount_super(struct super_block *sb) +static inline struct fuse_conn *get_fuse_conn_super(struct super_block *sb) { return sb->s_fs_info; } -static inline struct fuse_conn *get_fuse_conn_super(struct super_block *sb) -{ - struct fuse_mount *fm = get_fuse_mount_super(sb); - - return fm ? fm->fc : NULL; -} - -static inline struct fuse_mount *get_fuse_mount(struct inode *inode) -{ - return get_fuse_mount_super(inode->i_sb); -} - static inline struct fuse_conn *get_fuse_conn(struct inode *inode) { - struct fuse_mount *fm = get_fuse_mount(inode); - - return fm ? fm->fc : NULL; + return get_fuse_conn_super(inode->i_sb); } static inline struct fuse_inode *get_fuse_inode(struct inode *inode) @@ -960,13 +816,6 @@ static inline u64 fuse_get_attr_version(struct fuse_conn *fc) return atomic64_read(&fc->attr_version); } -static inline bool fuse_stale_inode(const struct inode *inode, int generation, - struct fuse_attr *attr) -{ - return inode->i_generation != generation || - inode_wrong_type(inode, attr->mode); -} - static inline void fuse_make_bad(struct inode *inode) { set_bit(FUSE_I_BAD, &get_fuse_inode(inode)->state); @@ -984,18 +833,19 @@ extern const struct dentry_operations fuse_dentry_operations; extern const struct dentry_operations fuse_root_dentry_operations; /** - * Get a filled-in inode + * Inode to nodeid comparison. + */ +int fuse_inode_eq(struct inode *inode, void *_nodeidp); + +/** + * Get a filled in inode */ -struct inode *fuse_iget_backing(struct super_block *sb, - u64 nodeid, - struct inode *backing_inode); struct inode *fuse_iget(struct super_block *sb, u64 nodeid, int generation, struct fuse_attr *attr, u64 attr_valid, u64 attr_version); int fuse_lookup_name(struct super_block *sb, u64 nodeid, const struct qstr *name, - struct fuse_entry_out *outarg, - struct dentry *entry, struct inode **inode); + struct fuse_entry_out *outarg, struct inode **inode); /** * Send FORGET command @@ -1032,12 +882,13 @@ struct fuse_io_args { void fuse_read_args_fill(struct fuse_io_args *ia, struct file *file, loff_t pos, size_t count, int opcode); + /** * Send OPEN or OPENDIR request */ int fuse_open_common(struct inode *inode, struct file *file, bool isdir); -struct fuse_file *fuse_file_alloc(struct fuse_mount *fm); +struct fuse_file *fuse_file_alloc(struct fuse_conn *fc); void fuse_file_free(struct fuse_file *ff); void fuse_finish_open(struct inode *inode, struct file *file); @@ -1100,19 +951,19 @@ int fuse_dev_init(void); void fuse_dev_cleanup(void); int fuse_ctl_init(void); -void fuse_ctl_cleanup(void); +void __exit fuse_ctl_cleanup(void); /** * Simple request sending that does request allocation and freeing */ -ssize_t fuse_simple_request(struct fuse_mount *fm, struct fuse_args *args); -int fuse_simple_background(struct fuse_mount *fm, struct fuse_args *args, +ssize_t fuse_simple_request(struct fuse_conn *fc, struct fuse_args *args); +int fuse_simple_background(struct fuse_conn *fc, struct fuse_args *args, gfp_t gfp_flags); /** * End a finished request */ -void fuse_request_end(struct fuse_req *req); +void fuse_request_end(struct fuse_conn *fc, struct fuse_req *req); /* Abort all requests */ void fuse_abort_conn(struct fuse_conn *fc); @@ -1128,7 +979,6 @@ void fuse_invalidate_entry_cache(struct dentry *entry); void fuse_invalidate_atime(struct inode *inode); u64 entry_attr_timeout(struct fuse_entry_out *o); -void fuse_init_dentry_root(struct dentry *root, struct file *backing_dir); void fuse_change_entry_timeout(struct dentry *entry, struct fuse_entry_out *o); /** @@ -1139,8 +989,7 @@ struct fuse_conn *fuse_conn_get(struct fuse_conn *fc); /** * Initialize fuse_conn */ -void fuse_conn_init(struct fuse_conn *fc, struct fuse_mount *fm, - struct user_namespace *user_ns, +void fuse_conn_init(struct fuse_conn *fc, struct user_namespace *user_ns, const struct fuse_iqueue_ops *fiq_ops, void *fiq_priv); /** @@ -1148,21 +997,11 @@ void fuse_conn_init(struct fuse_conn *fc, struct fuse_mount *fm, */ void fuse_conn_put(struct fuse_conn *fc); -/** - * Acquire reference to fuse_mount - */ -struct fuse_mount *fuse_mount_get(struct fuse_mount *fm); - -/** - * Release reference to fuse_mount - */ -void fuse_mount_put(struct fuse_mount *fm); - struct fuse_dev *fuse_dev_alloc_install(struct fuse_conn *fc); struct fuse_dev *fuse_dev_alloc(void); void fuse_dev_install(struct fuse_dev *fud, struct fuse_conn *fc); void fuse_dev_free(struct fuse_dev *fud); -void fuse_send_init(struct fuse_mount *fm); +void fuse_send_init(struct fuse_conn *fc); /** * Fill in superblock and initialize fuse connection @@ -1171,26 +1010,12 @@ void fuse_send_init(struct fuse_mount *fm); */ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx); -/* - * Fill in superblock for submounts - * @sb: partially-initialized superblock to fill in - * @parent_fi: The fuse_inode of the parent filesystem where this submount is - * mounted - */ -int fuse_fill_super_submount(struct super_block *sb, - struct fuse_inode *parent_fi); - -/* - * Remove the mount from the connection +/** + * Disassociate fuse connection from superblock and kill the superblock * - * Returns whether this was the last mount + * Calls kill_anon_super(), do not use with bdev mounts. */ -bool fuse_mount_remove(struct fuse_mount *fm); - -/* - * Shut down the connection (possibly sending DESTROY request). - */ -void fuse_conn_destroy(struct fuse_mount *fm); +void fuse_kill_sb_anon(struct super_block *sb); /** * Add connection to control filesystem @@ -1216,7 +1041,6 @@ int fuse_allow_current_process(struct fuse_conn *fc); u64 fuse_lock_owner_id(struct fuse_conn *fc, fl_owner_t id); -void fuse_flush_time_update(struct inode *inode); void fuse_update_ctime(struct inode *inode); int fuse_update_attributes(struct inode *inode, struct file *file); @@ -1226,20 +1050,10 @@ void fuse_flush_writepages(struct inode *inode); void fuse_set_nowrite(struct inode *inode); void fuse_release_nowrite(struct inode *inode); -/** - * Scan all fuse_mounts belonging to fc to find the first where - * ilookup5() returns a result. Return that result and the - * respective fuse_mount in *fm (unless fm is NULL). - * - * The caller must hold fc->killsb. - */ -struct inode *fuse_ilookup(struct fuse_conn *fc, u64 nodeid, - struct fuse_mount **fm); - /** * File-system tells the kernel to invalidate cache for the given node id. */ -int fuse_reverse_inval_inode(struct fuse_conn *fc, u64 nodeid, +int fuse_reverse_inval_inode(struct super_block *sb, u64 nodeid, loff_t offset, loff_t len); /** @@ -1252,10 +1066,10 @@ int fuse_reverse_inval_inode(struct fuse_conn *fc, u64 nodeid, * - is a file or oan empty directory * then the dentry is unhashed (d_delete()). */ -int fuse_reverse_inval_entry(struct fuse_conn *fc, u64 parent_nodeid, +int fuse_reverse_inval_entry(struct super_block *sb, u64 parent_nodeid, u64 child_nodeid, struct qstr *name); -int fuse_do_open(struct fuse_mount *fm, u64 nodeid, struct file *file, +int fuse_do_open(struct fuse_conn *fc, u64 nodeid, struct file *file, bool isdir); /** @@ -1319,24 +1133,7 @@ unsigned int fuse_len_args(unsigned int numargs, struct fuse_arg *args); u64 fuse_get_unique(struct fuse_iqueue *fiq); void fuse_free_conn(struct fuse_conn *fc); -/* dax.c */ - -#define FUSE_IS_DAX(inode) (IS_ENABLED(CONFIG_FUSE_DAX) && IS_DAX(inode)) - -ssize_t fuse_dax_read_iter(struct kiocb *iocb, struct iov_iter *to); -ssize_t fuse_dax_write_iter(struct kiocb *iocb, struct iov_iter *from); -int fuse_dax_mmap(struct file *file, struct vm_area_struct *vma); -int fuse_dax_break_layouts(struct inode *inode, u64 dmap_start, u64 dmap_end); -int fuse_dax_conn_alloc(struct fuse_conn *fc, struct dax_device *dax_dev); -void fuse_dax_conn_free(struct fuse_conn *fc); -bool fuse_dax_inode_alloc(struct super_block *sb, struct fuse_inode *fi); -void fuse_dax_inode_init(struct inode *inode); -void fuse_dax_inode_cleanup(struct inode *inode); -bool fuse_dax_check_alignment(struct fuse_conn *fc, unsigned int map_alignment); -void fuse_dax_cancel_work(struct fuse_conn *fc); - /* passthrough.c */ -void fuse_copyattr(struct file *dst_file, struct file *src_file); int fuse_passthrough_open(struct fuse_dev *fud, u32 lower_fd); int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff, struct fuse_open_out *openarg); @@ -1345,648 +1142,4 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb, struct iov_iter *to); ssize_t fuse_passthrough_write_iter(struct kiocb *iocb, struct iov_iter *from); ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma); -/* backing.c */ - -struct bpf_prog *fuse_get_bpf_prog(struct file *file); - -/* - * Dummy io passed to fuse_bpf_backing when io operation needs no scratch space - */ -struct fuse_dummy_io { - int unused; -}; - -struct fuse_open_io { - struct fuse_open_in foi; - struct fuse_open_out foo; -}; - -int fuse_open_initialize(struct fuse_bpf_args *fa, struct fuse_open_io *foi, - struct inode *inode, struct file *file, bool isdir); -int fuse_open_backing(struct fuse_bpf_args *fa, - struct inode *inode, struct file *file, bool isdir); -void *fuse_open_finalize(struct fuse_bpf_args *fa, - struct inode *inode, struct file *file, bool isdir); - -struct fuse_create_open_io { - struct fuse_create_in fci; - struct fuse_entry_out feo; - struct fuse_open_out foo; -}; - -int fuse_create_open_initialize( - struct fuse_bpf_args *fa, struct fuse_create_open_io *fcoi, - struct inode *dir, struct dentry *entry, - struct file *file, unsigned int flags, umode_t mode); -int fuse_create_open_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, - struct file *file, unsigned int flags, umode_t mode); -void *fuse_create_open_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, - struct file *file, unsigned int flags, umode_t mode); - -int fuse_mknod_initialize( - struct fuse_bpf_args *fa, struct fuse_mknod_in *fmi, - struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev); -int fuse_mknod_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev); -void *fuse_mknod_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev); - -int fuse_mkdir_initialize( - struct fuse_bpf_args *fa, struct fuse_mkdir_in *fmi, - struct inode *dir, struct dentry *entry, umode_t mode); -int fuse_mkdir_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode); -void *fuse_mkdir_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode); - -int fuse_rmdir_initialize( - struct fuse_bpf_args *fa, struct fuse_dummy_io *fmi, - struct inode *dir, struct dentry *entry); -int fuse_rmdir_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry); -void *fuse_rmdir_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry); - -int fuse_rename2_initialize(struct fuse_bpf_args *fa, struct fuse_rename2_in *fri, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags); -int fuse_rename2_backing(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags); -void *fuse_rename2_finalize(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags); - -int fuse_rename_initialize(struct fuse_bpf_args *fa, struct fuse_rename_in *fri, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent); -int fuse_rename_backing(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent); -void *fuse_rename_finalize(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent); - -int fuse_unlink_initialize( - struct fuse_bpf_args *fa, struct fuse_dummy_io *fmi, - struct inode *dir, struct dentry *entry); -int fuse_unlink_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry); -void *fuse_unlink_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry); - -int fuse_link_initialize(struct fuse_bpf_args *fa, struct fuse_link_in *fli, - struct dentry *entry, struct inode *dir, - struct dentry *newent); -int fuse_link_backing(struct fuse_bpf_args *fa, struct dentry *entry, - struct inode *dir, struct dentry *newent); -void *fuse_link_finalize(struct fuse_bpf_args *fa, struct dentry *entry, - struct inode *dir, struct dentry *newent); - -int fuse_release_initialize(struct fuse_bpf_args *fa, struct fuse_release_in *fri, - struct inode *inode, struct fuse_file *ff); -int fuse_release_backing(struct fuse_bpf_args *fa, - struct inode *inode, struct fuse_file *ff); -void *fuse_release_finalize(struct fuse_bpf_args *fa, - struct inode *inode, struct fuse_file *ff); - -int fuse_flush_initialize(struct fuse_bpf_args *fa, struct fuse_flush_in *ffi, - struct file *file, fl_owner_t id); -int fuse_flush_backing(struct fuse_bpf_args *fa, struct file *file, fl_owner_t id); -void *fuse_flush_finalize(struct fuse_bpf_args *fa, - struct file *file, fl_owner_t id); - -struct fuse_lseek_io { - struct fuse_lseek_in fli; - struct fuse_lseek_out flo; -}; - -int fuse_lseek_initialize(struct fuse_bpf_args *fa, struct fuse_lseek_io *fli, - struct file *file, loff_t offset, int whence); -int fuse_lseek_backing(struct fuse_bpf_args *fa, struct file *file, loff_t offset, int whence); -void *fuse_lseek_finalize(struct fuse_bpf_args *fa, struct file *file, loff_t offset, int whence); - -struct fuse_copy_file_range_io { - struct fuse_copy_file_range_in fci; - struct fuse_write_out fwo; -}; - -int fuse_copy_file_range_initialize(struct fuse_bpf_args *fa, - struct fuse_copy_file_range_io *fcf, - struct file *file_in, loff_t pos_in, - struct file *file_out, loff_t pos_out, - size_t len, unsigned int flags); -int fuse_copy_file_range_backing(struct fuse_bpf_args *fa, - struct file *file_in, loff_t pos_in, - struct file *file_out, loff_t pos_out, - size_t len, unsigned int flags); -void *fuse_copy_file_range_finalize(struct fuse_bpf_args *fa, - struct file *file_in, loff_t pos_in, - struct file *file_out, loff_t pos_out, - size_t len, unsigned int flags); - -int fuse_fsync_initialize(struct fuse_bpf_args *fa, struct fuse_fsync_in *ffi, - struct file *file, loff_t start, loff_t end, int datasync); -int fuse_fsync_backing(struct fuse_bpf_args *fa, - struct file *file, loff_t start, loff_t end, int datasync); -void *fuse_fsync_finalize(struct fuse_bpf_args *fa, - struct file *file, loff_t start, loff_t end, int datasync); -int fuse_dir_fsync_initialize(struct fuse_bpf_args *fa, struct fuse_fsync_in *ffi, - struct file *file, loff_t start, loff_t end, int datasync); - -struct fuse_getxattr_io { - struct fuse_getxattr_in fgi; - struct fuse_getxattr_out fgo; -}; - -int fuse_getxattr_initialize( - struct fuse_bpf_args *fa, struct fuse_getxattr_io *fgio, - struct dentry *dentry, const char *name, void *value, - size_t size); -int fuse_getxattr_backing( - struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name, void *value, - size_t size); -void *fuse_getxattr_finalize( - struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name, void *value, - size_t size); - -int fuse_listxattr_initialize(struct fuse_bpf_args *fa, - struct fuse_getxattr_io *fgio, - struct dentry *dentry, char *list, size_t size); -int fuse_listxattr_backing(struct fuse_bpf_args *fa, struct dentry *dentry, - char *list, size_t size); -void *fuse_listxattr_finalize(struct fuse_bpf_args *fa, struct dentry *dentry, - char *list, size_t size); - -int fuse_setxattr_initialize(struct fuse_bpf_args *fa, - struct fuse_setxattr_in *fsxi, - struct dentry *dentry, const char *name, - const void *value, size_t size, int flags); -int fuse_setxattr_backing(struct fuse_bpf_args *fa, struct dentry *dentry, - const char *name, const void *value, size_t size, - int flags); -void *fuse_setxattr_finalize(struct fuse_bpf_args *fa, struct dentry *dentry, - const char *name, const void *value, size_t size, - int flags); - -int fuse_removexattr_initialize(struct fuse_bpf_args *fa, - struct fuse_dummy_io *unused, - struct dentry *dentry, const char *name); -int fuse_removexattr_backing(struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name); -void *fuse_removexattr_finalize(struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name); - -struct fuse_read_iter_out { - uint64_t ret; -}; -struct fuse_file_read_iter_io { - struct fuse_read_in fri; - struct fuse_read_iter_out frio; -}; - -int fuse_file_read_iter_initialize( - struct fuse_bpf_args *fa, struct fuse_file_read_iter_io *fri, - struct kiocb *iocb, struct iov_iter *to); -int fuse_file_read_iter_backing(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *to); -void *fuse_file_read_iter_finalize(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *to); - -struct fuse_write_iter_out { - uint64_t ret; -}; -struct fuse_file_write_iter_io { - struct fuse_write_in fwi; - struct fuse_write_out fwo; - struct fuse_write_iter_out fwio; -}; - -int fuse_file_write_iter_initialize( - struct fuse_bpf_args *fa, struct fuse_file_write_iter_io *fwio, - struct kiocb *iocb, struct iov_iter *from); -int fuse_file_write_iter_backing(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *from); -void *fuse_file_write_iter_finalize(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *from); - -long fuse_backing_ioctl(struct file *file, unsigned int command, unsigned long arg, int flags); - -int fuse_file_flock_backing(struct file *file, int cmd, struct file_lock *fl); -ssize_t fuse_backing_mmap(struct file *file, struct vm_area_struct *vma); - -int fuse_file_fallocate_initialize(struct fuse_bpf_args *fa, - struct fuse_fallocate_in *ffi, - struct file *file, int mode, loff_t offset, loff_t length); -int fuse_file_fallocate_backing(struct fuse_bpf_args *fa, - struct file *file, int mode, loff_t offset, loff_t length); -void *fuse_file_fallocate_finalize(struct fuse_bpf_args *fa, - struct file *file, int mode, loff_t offset, loff_t length); - -struct fuse_lookup_io { - struct fuse_entry_out feo; - struct fuse_entry_bpf feb; -}; - -int fuse_handle_backing(struct fuse_entry_bpf *feb, struct inode **backing_inode, - struct path *backing_path); -int fuse_handle_bpf_prog(struct fuse_entry_bpf *feb, struct inode *parent, - struct bpf_prog **bpf); - -int fuse_lookup_initialize(struct fuse_bpf_args *fa, struct fuse_lookup_io *feo, - struct inode *dir, struct dentry *entry, unsigned int flags); -int fuse_lookup_backing(struct fuse_bpf_args *fa, struct inode *dir, - struct dentry *entry, unsigned int flags); -struct dentry *fuse_lookup_finalize(struct fuse_bpf_args *fa, struct inode *dir, - struct dentry *entry, unsigned int flags); -int fuse_revalidate_backing(struct dentry *entry, unsigned int flags); - -int fuse_canonical_path_initialize(struct fuse_bpf_args *fa, - struct fuse_dummy_io *fdi, - const struct path *path, - struct path *canonical_path); -int fuse_canonical_path_backing(struct fuse_bpf_args *fa, const struct path *path, - struct path *canonical_path); -void *fuse_canonical_path_finalize(struct fuse_bpf_args *fa, - const struct path *path, - struct path *canonical_path); - -struct fuse_getattr_io { - struct fuse_getattr_in fgi; - struct fuse_attr_out fao; -}; -int fuse_getattr_initialize(struct fuse_bpf_args *fa, struct fuse_getattr_io *fgio, - const struct dentry *entry, struct kstat *stat, - u32 request_mask, unsigned int flags); -int fuse_getattr_backing(struct fuse_bpf_args *fa, - const struct dentry *entry, struct kstat *stat, - u32 request_mask, unsigned int flags); -void *fuse_getattr_finalize(struct fuse_bpf_args *fa, - const struct dentry *entry, struct kstat *stat, - u32 request_mask, unsigned int flags); - -struct fuse_setattr_io { - struct fuse_setattr_in fsi; - struct fuse_attr_out fao; -}; - -int fuse_setattr_initialize(struct fuse_bpf_args *fa, struct fuse_setattr_io *fsi, - struct dentry *dentry, struct iattr *attr, struct file *file); -int fuse_setattr_backing(struct fuse_bpf_args *fa, - struct dentry *dentry, struct iattr *attr, struct file *file); -void *fuse_setattr_finalize(struct fuse_bpf_args *fa, - struct dentry *dentry, struct iattr *attr, struct file *file); - -int fuse_statfs_initialize(struct fuse_bpf_args *fa, struct fuse_statfs_out *fso, - struct dentry *dentry, struct kstatfs *buf); -int fuse_statfs_backing(struct fuse_bpf_args *fa, - struct dentry *dentry, struct kstatfs *buf); -void *fuse_statfs_finalize(struct fuse_bpf_args *fa, - struct dentry *dentry, struct kstatfs *buf); - -int fuse_get_link_initialize(struct fuse_bpf_args *fa, struct fuse_dummy_io *dummy, - struct inode *inode, struct dentry *dentry, - struct delayed_call *callback, const char **out); -int fuse_get_link_backing(struct fuse_bpf_args *fa, - struct inode *inode, struct dentry *dentry, - struct delayed_call *callback, const char **out); -void *fuse_get_link_finalize(struct fuse_bpf_args *fa, - struct inode *inode, struct dentry *dentry, - struct delayed_call *callback, const char **out); - -int fuse_symlink_initialize( - struct fuse_bpf_args *fa, struct fuse_dummy_io *unused, - struct inode *dir, struct dentry *entry, const char *link, int len); -int fuse_symlink_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, const char *link, int len); -void *fuse_symlink_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, const char *link, int len); - -struct fuse_read_io { - struct fuse_read_in fri; - struct fuse_read_out fro; -}; - -int fuse_readdir_initialize(struct fuse_bpf_args *fa, struct fuse_read_io *frio, - struct file *file, struct dir_context *ctx, - bool *force_again, bool *allow_force, bool is_continued); -int fuse_readdir_backing(struct fuse_bpf_args *fa, - struct file *file, struct dir_context *ctx, - bool *force_again, bool *allow_force, bool is_continued); -void *fuse_readdir_finalize(struct fuse_bpf_args *fa, - struct file *file, struct dir_context *ctx, - bool *force_again, bool *allow_force, bool is_continued); - -int fuse_access_initialize(struct fuse_bpf_args *fa, struct fuse_access_in *fai, - struct inode *inode, int mask); -int fuse_access_backing(struct fuse_bpf_args *fa, struct inode *inode, int mask); -void *fuse_access_finalize(struct fuse_bpf_args *fa, struct inode *inode, int mask); - -/* - * FUSE caches dentries and attributes with separate timeout. The - * time in jiffies until the dentry/attributes are valid is stored in - * dentry->d_fsdata and fuse_inode->i_time respectively. - */ - -/* - * Calculate the time in jiffies until a dentry/attributes are valid - */ -static inline u64 time_to_jiffies(u64 sec, u32 nsec) -{ - if (sec || nsec) { - struct timespec64 ts = { - sec, - min_t(u32, nsec, NSEC_PER_SEC - 1) - }; - - return get_jiffies_64() + timespec64_to_jiffies(&ts); - } else - return 0; -} - -static inline u64 attr_timeout(struct fuse_attr_out *o) -{ - return time_to_jiffies(o->attr_valid, o->attr_valid_nsec); -} - -static inline bool update_mtime(unsigned ivalid, bool trust_local_mtime) -{ - /* Always update if mtime is explicitly set */ - if (ivalid & ATTR_MTIME_SET) - return true; - - /* Or if kernel i_mtime is the official one */ - if (trust_local_mtime) - return true; - - /* If it's an open(O_TRUNC) or an ftruncate(), don't update */ - if ((ivalid & ATTR_SIZE) && (ivalid & (ATTR_OPEN | ATTR_FILE))) - return false; - - /* In all other cases update */ - return true; -} - -void fuse_fillattr(struct inode *inode, struct fuse_attr *attr, - struct kstat *stat); - -static inline void iattr_to_fattr(struct fuse_conn *fc, struct iattr *iattr, - struct fuse_setattr_in *arg, bool trust_local_cmtime) -{ - unsigned ivalid = iattr->ia_valid; - - if (ivalid & ATTR_MODE) - arg->valid |= FATTR_MODE, arg->mode = iattr->ia_mode; - if (ivalid & ATTR_UID) - arg->valid |= FATTR_UID, arg->uid = from_kuid(fc->user_ns, iattr->ia_uid); - if (ivalid & ATTR_GID) - arg->valid |= FATTR_GID, arg->gid = from_kgid(fc->user_ns, iattr->ia_gid); - if (ivalid & ATTR_SIZE) - arg->valid |= FATTR_SIZE, arg->size = iattr->ia_size; - if (ivalid & ATTR_ATIME) { - arg->valid |= FATTR_ATIME; - arg->atime = iattr->ia_atime.tv_sec; - arg->atimensec = iattr->ia_atime.tv_nsec; - if (!(ivalid & ATTR_ATIME_SET)) - arg->valid |= FATTR_ATIME_NOW; - } - if ((ivalid & ATTR_MTIME) && update_mtime(ivalid, trust_local_cmtime)) { - arg->valid |= FATTR_MTIME; - arg->mtime = iattr->ia_mtime.tv_sec; - arg->mtimensec = iattr->ia_mtime.tv_nsec; - if (!(ivalid & ATTR_MTIME_SET) && !trust_local_cmtime) - arg->valid |= FATTR_MTIME_NOW; - } - if ((ivalid & ATTR_CTIME) && trust_local_cmtime) { - arg->valid |= FATTR_CTIME; - arg->ctime = iattr->ia_ctime.tv_sec; - arg->ctimensec = iattr->ia_ctime.tv_nsec; - } -} - -static inline int finalize_attr(struct inode *inode, struct fuse_attr_out *outarg, - u64 attr_version, struct kstat *stat) -{ - int err = 0; - - if (fuse_invalid_attr(&outarg->attr) || - ((inode->i_mode ^ outarg->attr.mode) & S_IFMT)) { - fuse_make_bad(inode); - err = -EIO; - } else { - fuse_change_attributes(inode, &outarg->attr, - attr_timeout(outarg), - attr_version); - if (stat) - fuse_fillattr(inode, &outarg->attr, stat); - } - return err; -} - -static inline void convert_statfs_to_fuse(struct fuse_kstatfs *attr, struct kstatfs *stbuf) -{ - attr->bsize = stbuf->f_bsize; - attr->frsize = stbuf->f_frsize; - attr->blocks = stbuf->f_blocks; - attr->bfree = stbuf->f_bfree; - attr->bavail = stbuf->f_bavail; - attr->files = stbuf->f_files; - attr->ffree = stbuf->f_ffree; - attr->namelen = stbuf->f_namelen; - /* fsid is left zero */ -} - -static inline void convert_fuse_statfs(struct kstatfs *stbuf, struct fuse_kstatfs *attr) -{ - stbuf->f_type = FUSE_SUPER_MAGIC; - stbuf->f_bsize = attr->bsize; - stbuf->f_frsize = attr->frsize; - stbuf->f_blocks = attr->blocks; - stbuf->f_bfree = attr->bfree; - stbuf->f_bavail = attr->bavail; - stbuf->f_files = attr->files; - stbuf->f_ffree = attr->ffree; - stbuf->f_namelen = attr->namelen; - /* fsid is left zero */ -} - -#ifdef CONFIG_FUSE_BPF -struct fuse_err_ret { - void *result; - bool ret; -}; - -int __init fuse_bpf_init(void); -void __exit fuse_bpf_cleanup(void); - -ssize_t fuse_bpf_simple_request(struct fuse_mount *fm, struct fuse_bpf_args *args); - -static inline int fuse_bpf_run(struct bpf_prog *prog, struct fuse_bpf_args *fba) -{ - int ret; - - migrate_disable(); - ret = BPF_PROG_RUN(prog, fba); - migrate_enable(); - return ret; -} - -/* - * expression statement to wrap the backing filter logic - * struct inode *inode: inode with bpf and backing inode - * typedef io: (typically complex) type whose components fuse_args can point to. - * An instance of this type is created locally and passed to initialize - * void initialize(struct fuse_bpf_args *fa, io *in_out, args...): function that sets - * up fa and io based on args - * int backing(struct fuse_bpf_args *fa, args...): function that actually performs - * the backing io operation - * void *finalize(struct fuse_bpf_args *, args...): function that performs any final - * work needed to commit the backing io - */ -#define fuse_bpf_backing(inode, io, initialize, backing, finalize, \ - args...) \ -({ \ - struct fuse_err_ret fer = {0}; \ - int ext_flags; \ - struct fuse_inode *fuse_inode = get_fuse_inode(inode); \ - struct fuse_mount *fm = get_fuse_mount(inode); \ - io feo = {0}; \ - struct fuse_bpf_args fa = {0}, fa_backup = {0}; \ - bool locked; \ - ssize_t res; \ - void *err; \ - int i; \ - bool initialized = false; \ - \ - do { \ - if (!fuse_inode || !fuse_inode->backing_inode) \ - break; \ - \ - err = ERR_PTR(initialize(&fa, &feo, args)); \ - if (err) { \ - fer = (struct fuse_err_ret) { \ - err, \ - true, \ - }; \ - break; \ - } \ - initialized = true; \ - \ - fa_backup = fa; \ - fa.opcode |= FUSE_PREFILTER; \ - for (i = 0; i < fa.in_numargs; ++i) \ - fa.out_args[i] = (struct fuse_bpf_arg) { \ - .size = fa.in_args[i].size, \ - .value = (void *)fa.in_args[i].value, \ - }; \ - fa.out_numargs = fa.in_numargs; \ - \ - ext_flags = fuse_inode->bpf ? \ - fuse_bpf_run(fuse_inode->bpf, &fa) : \ - FUSE_BPF_BACKING; \ - if (ext_flags < 0) { \ - fer = (struct fuse_err_ret) { \ - ERR_PTR(ext_flags), \ - true, \ - }; \ - break; \ - } \ - \ - if (ext_flags & FUSE_BPF_USER_FILTER) { \ - locked = fuse_lock_inode(inode); \ - res = fuse_bpf_simple_request(fm, &fa); \ - fuse_unlock_inode(inode, locked); \ - if (res < 0) { \ - fer = (struct fuse_err_ret) { \ - ERR_PTR(res), \ - true, \ - }; \ - break; \ - } \ - } \ - \ - if (!(ext_flags & FUSE_BPF_BACKING)) \ - break; \ - \ - fa.opcode &= ~FUSE_PREFILTER; \ - for (i = 0; i < fa.in_numargs; ++i) \ - fa.in_args[i] = (struct fuse_bpf_in_arg) { \ - .size = fa.out_args[i].size, \ - .value = fa.out_args[i].value, \ - }; \ - for (i = 0; i < fa_backup.out_numargs; ++i) \ - fa.out_args[i] = (struct fuse_bpf_arg) { \ - .size = fa_backup.out_args[i].size, \ - .value = fa_backup.out_args[i].value, \ - }; \ - fa.out_numargs = fa_backup.out_numargs; \ - \ - fer = (struct fuse_err_ret) { \ - ERR_PTR(backing(&fa, args)), \ - true, \ - }; \ - if (IS_ERR(fer.result)) \ - fa.error_in = PTR_ERR(fer.result); \ - if (!(ext_flags & FUSE_BPF_POST_FILTER)) \ - break; \ - \ - fa.opcode |= FUSE_POSTFILTER; \ - for (i = 0; i < fa.out_numargs; ++i) \ - fa.in_args[fa.in_numargs++] = \ - (struct fuse_bpf_in_arg) { \ - .size = fa.out_args[i].size, \ - .value = fa.out_args[i].value, \ - }; \ - ext_flags = fuse_bpf_run(fuse_inode->bpf, &fa); \ - if (ext_flags < 0) { \ - fer = (struct fuse_err_ret) { \ - ERR_PTR(ext_flags), \ - true, \ - }; \ - break; \ - } \ - if (!(ext_flags & FUSE_BPF_USER_FILTER)) \ - break; \ - \ - fa.out_args[0].size = fa_backup.out_args[0].size; \ - fa.out_args[1].size = fa_backup.out_args[1].size; \ - fa.out_numargs = fa_backup.out_numargs; \ - locked = fuse_lock_inode(inode); \ - res = fuse_bpf_simple_request(fm, &fa); \ - fuse_unlock_inode(inode, locked); \ - if (res < 0) { \ - fer.result = ERR_PTR(res); \ - break; \ - } \ - } while (false); \ - \ - if (initialized && fer.ret) { \ - err = finalize(&fa, args); \ - if (err) \ - fer.result = err; \ - } \ - \ - fer; \ -}) -#endif /* CONFIG_FUSE_BPF */ - #endif /* _FS_FUSE_I_H */ diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c index e37fba257c8b..b32c5c84004c 100644 --- a/fs/fuse/inode.c +++ b/fs/fuse/inode.c @@ -50,6 +50,8 @@ MODULE_PARM_DESC(max_user_congthresh, "Global limit for the maximum congestion threshold an " "unprivileged user can set"); +#define FUSE_SUPER_MAGIC 0x65735546 + #define FUSE_DEFAULT_BLKSIZE 512 /** Maximum number of outstanding background requests */ @@ -77,32 +79,20 @@ static struct inode *fuse_alloc_inode(struct super_block *sb) fi->i_time = 0; fi->inval_mask = 0; -#ifdef CONFIG_FUSE_BPF - fi->backing_inode = NULL; - fi->bpf = NULL; -#endif fi->nodeid = 0; fi->nlookup = 0; fi->attr_version = 0; fi->orig_ino = 0; fi->state = 0; mutex_init(&fi->mutex); - init_rwsem(&fi->i_mmap_sem); spin_lock_init(&fi->lock); fi->forget = fuse_alloc_forget(); - if (!fi->forget) - goto out_free; - - if (IS_ENABLED(CONFIG_FUSE_DAX) && !fuse_dax_inode_alloc(sb, fi)) - goto out_free_forget; + if (!fi->forget) { + kmem_cache_free(fuse_inode_cachep, fi); + return NULL; + } return &fi->inode; - -out_free_forget: - kfree(fi->forget); -out_free: - kmem_cache_free(fuse_inode_cachep, fi); - return NULL; } static void fuse_free_inode(struct inode *inode) @@ -111,13 +101,6 @@ static void fuse_free_inode(struct inode *inode) mutex_destroy(&fi->mutex); kfree(fi->forget); -#ifdef CONFIG_FUSE_DAX - kfree(fi->dax); -#endif -#ifdef CONFIG_FUSE_BPF - if (fi->bpf) - bpf_prog_put(fi->bpf); -#endif kmem_cache_free(fuse_inode_cachep, fi); } @@ -125,21 +108,12 @@ static void fuse_evict_inode(struct inode *inode) { struct fuse_inode *fi = get_fuse_inode(inode); - /* Will write inode on close/munmap and in all other dirtiers */ - WARN_ON(inode->i_state & I_DIRTY_INODE); - truncate_inode_pages_final(&inode->i_data); clear_inode(inode); if (inode->i_sb->s_flags & SB_ACTIVE) { struct fuse_conn *fc = get_fuse_conn(inode); - - if (FUSE_IS_DAX(inode)) - fuse_dax_inode_cleanup(inode); - if (fi->nlookup) { - fuse_queue_forget(fc, fi->forget, fi->nodeid, - fi->nlookup); - fi->forget = NULL; - } + fuse_queue_forget(fc, fi->forget, fi->nodeid, fi->nlookup); + fi->forget = NULL; } if (S_ISREG(inode->i_mode) && !fuse_is_bad(inode)) { WARN_ON(!list_empty(&fi->write_files)); @@ -147,21 +121,12 @@ static void fuse_evict_inode(struct inode *inode) } } -#ifdef CONFIG_FUSE_BPF -static void fuse_destroy_inode(struct inode *inode) +static int fuse_reconfigure(struct fs_context *fc) { - struct fuse_inode *fi = get_fuse_inode(inode); - - iput(fi->backing_inode); -} -#endif - -static int fuse_reconfigure(struct fs_context *fsc) -{ - struct super_block *sb = fsc->root->d_sb; + struct super_block *sb = fc->root->d_sb; sync_filesystem(sb); - if (fsc->sb_flags & SB_MANDLOCK) + if (fc->sb_flags & SB_MANDLOCK) return -EINVAL; return 0; @@ -179,28 +144,6 @@ static ino_t fuse_squash_ino(u64 ino64) return ino; } -static void fuse_fill_attr_from_inode(struct fuse_attr *attr, - const struct inode *inode) -{ - *attr = (struct fuse_attr){ - .ino = inode->i_ino, - .size = inode->i_size, - .blocks = inode->i_blocks, - .atime = inode->i_atime.tv_sec, - .mtime = inode->i_mtime.tv_sec, - .ctime = inode->i_ctime.tv_sec, - .atimensec = inode->i_atime.tv_nsec, - .mtimensec = inode->i_mtime.tv_nsec, - .ctimensec = inode->i_ctime.tv_nsec, - .mode = inode->i_mode, - .nlink = inode->i_nlink, - .uid = inode->i_uid.val, - .gid = inode->i_gid.val, - .rdev = inode->i_rdev, - .blksize = 1u << inode->i_blkbits, - }; -} - void fuse_change_attributes_common(struct inode *inode, struct fuse_attr *attr, u64 attr_valid) { @@ -325,104 +268,28 @@ static void fuse_init_inode(struct inode *inode, struct fuse_attr *attr) else if (S_ISCHR(inode->i_mode) || S_ISBLK(inode->i_mode) || S_ISFIFO(inode->i_mode) || S_ISSOCK(inode->i_mode)) { fuse_init_common(inode); - init_special_inode(inode, inode->i_mode, attr->rdev); + init_special_inode(inode, inode->i_mode, + new_decode_dev(attr->rdev)); } else BUG(); } -struct fuse_inode_identifier { - u64 nodeid; - struct inode *backing_inode; -}; - -static int fuse_inode_eq(struct inode *inode, void *_nodeidp) +int fuse_inode_eq(struct inode *inode, void *_nodeidp) { - struct fuse_inode_identifier *fii = - (struct fuse_inode_identifier *) _nodeidp; - struct fuse_inode *fi = get_fuse_inode(inode); - - return fii->nodeid == fi->nodeid; -} - -static int fuse_inode_backing_eq(struct inode *inode, void *_nodeidp) -{ - struct fuse_inode_identifier *fii = - (struct fuse_inode_identifier *) _nodeidp; - struct fuse_inode *fi = get_fuse_inode(inode); - - return fii->nodeid == fi->nodeid -#ifdef CONFIG_FUSE_BPF - && fii->backing_inode == fi->backing_inode -#endif - ; + u64 nodeid = *(u64 *) _nodeidp; + if (get_node_id(inode) == nodeid) + return 1; + else + return 0; } static int fuse_inode_set(struct inode *inode, void *_nodeidp) { - struct fuse_inode_identifier *fii = - (struct fuse_inode_identifier *) _nodeidp; - struct fuse_inode *fi = get_fuse_inode(inode); - - fi->nodeid = fii->nodeid; - + u64 nodeid = *(u64 *) _nodeidp; + get_fuse_inode(inode)->nodeid = nodeid; return 0; } -static int fuse_inode_backing_set(struct inode *inode, void *_nodeidp) -{ - struct fuse_inode_identifier *fii = - (struct fuse_inode_identifier *) _nodeidp; - struct fuse_inode *fi = get_fuse_inode(inode); - - fi->nodeid = fii->nodeid; -#ifdef CONFIG_FUSE_BPF - fi->backing_inode = fii->backing_inode; - if (fi->backing_inode) - ihold(fi->backing_inode); -#endif - - return 0; -} - -struct inode *fuse_iget_backing(struct super_block *sb, u64 nodeid, - struct inode *backing_inode) -{ - struct inode *inode; - struct fuse_inode *fi; - struct fuse_conn *fc = get_fuse_conn_super(sb); - struct fuse_inode_identifier fii = { - .nodeid = nodeid, - .backing_inode = backing_inode, - }; - struct fuse_attr attr; - unsigned long hash = (unsigned long) backing_inode; - - if (nodeid) - hash = nodeid; - - fuse_fill_attr_from_inode(&attr, backing_inode); - inode = iget5_locked(sb, hash, fuse_inode_backing_eq, - fuse_inode_backing_set, &fii); - if (!inode) - return NULL; - - if ((inode->i_state & I_NEW)) { - inode->i_flags |= S_NOATIME; - if (!fc->writeback_cache) - inode->i_flags |= S_NOCMTIME; - fuse_init_common(inode); - unlock_new_inode(inode); - } - - fi = get_fuse_inode(inode); - fuse_init_inode(inode, &attr); - spin_lock(&fi->lock); - fi->nlookup++; - spin_unlock(&fi->lock); - - return inode; -} - struct inode *fuse_iget(struct super_block *sb, u64 nodeid, int generation, struct fuse_attr *attr, u64 attr_valid, u64 attr_version) @@ -430,31 +297,9 @@ struct inode *fuse_iget(struct super_block *sb, u64 nodeid, struct inode *inode; struct fuse_inode *fi; struct fuse_conn *fc = get_fuse_conn_super(sb); - struct fuse_inode_identifier fii = { - .nodeid = nodeid, - }; - /* - * Auto mount points get their node id from the submount root, which is - * not a unique identifier within this filesystem. - * - * To avoid conflicts, do not place submount points into the inode hash - * table. - */ - if (fc->auto_submounts && (attr->flags & FUSE_ATTR_SUBMOUNT) && - S_ISDIR(attr->mode)) { - inode = new_inode(sb); - if (!inode) - return NULL; - - fuse_init_inode(inode, attr); - get_fuse_inode(inode)->nodeid = nodeid; - inode->i_flags |= S_AUTOMOUNT; - goto done; - } - -retry: - inode = iget5_locked(sb, nodeid, fuse_inode_eq, fuse_inode_set, &fii); + retry: + inode = iget5_locked(sb, nodeid, fuse_inode_eq, fuse_inode_set, &nodeid); if (!inode) return NULL; @@ -465,8 +310,8 @@ retry: inode->i_generation = generation; fuse_init_inode(inode, attr); unlock_new_inode(inode); - } else if (fuse_stale_inode(inode, generation, attr)) { - /* nodeid was reused, any I/O on the old inode should fail */ + } else if ((inode->i_mode ^ attr->mode) & S_IFMT) { + /* Inode has changed type, any I/O on the old should fail */ fuse_make_bad(inode); if (inode != d_inode(sb->s_root)) { remove_inode_hash(inode); @@ -474,7 +319,7 @@ retry: goto retry; } } -done: + fi = get_fuse_inode(inode); spin_lock(&fi->lock); fi->nlookup++; @@ -484,40 +329,16 @@ done: return inode; } -struct inode *fuse_ilookup(struct fuse_conn *fc, u64 nodeid, - struct fuse_mount **fm) -{ - struct fuse_mount *fm_iter; - struct inode *inode; - struct fuse_inode_identifier fii = { - .nodeid = nodeid, - }; - - WARN_ON(!rwsem_is_locked(&fc->killsb)); - list_for_each_entry(fm_iter, &fc->mounts, fc_entry) { - if (!fm_iter->sb) - continue; - - inode = ilookup5(fm_iter->sb, nodeid, fuse_inode_eq, &fii); - if (inode) { - if (fm) - *fm = fm_iter; - return inode; - } - } - - return NULL; -} - -int fuse_reverse_inval_inode(struct fuse_conn *fc, u64 nodeid, +int fuse_reverse_inval_inode(struct super_block *sb, u64 nodeid, loff_t offset, loff_t len) { + struct fuse_conn *fc = get_fuse_conn_super(sb); struct fuse_inode *fi; struct inode *inode; pgoff_t pg_start; pgoff_t pg_end; - inode = fuse_ilookup(fc, nodeid, NULL); + inode = ilookup5(sb, nodeid, fuse_inode_eq, &nodeid); if (!inode) return -ENOENT; @@ -567,50 +388,57 @@ static void fuse_umount_begin(struct super_block *sb) fuse_abort_conn(fc); } -static void fuse_send_destroy(struct fuse_mount *fm) +static void fuse_send_destroy(struct fuse_conn *fc) { - if (fm->fc->conn_init) { + if (fc->conn_init) { FUSE_ARGS(args); args.opcode = FUSE_DESTROY; args.force = true; args.nocreds = true; - fuse_simple_request(fm, &args); + fuse_simple_request(fc, &args); } } static void fuse_put_super(struct super_block *sb) { - struct fuse_mount *fm = get_fuse_mount_super(sb); + struct fuse_conn *fc = get_fuse_conn_super(sb); - fuse_mount_put(fm); + mutex_lock(&fuse_mutex); + list_del(&fc->entry); + fuse_ctl_remove_conn(fc); + mutex_unlock(&fuse_mutex); + + fuse_conn_put(fc); +} + +static void convert_fuse_statfs(struct kstatfs *stbuf, struct fuse_kstatfs *attr) +{ + stbuf->f_type = FUSE_SUPER_MAGIC; + stbuf->f_bsize = attr->bsize; + stbuf->f_frsize = attr->frsize; + stbuf->f_blocks = attr->blocks; + stbuf->f_bfree = attr->bfree; + stbuf->f_bavail = attr->bavail; + stbuf->f_files = attr->files; + stbuf->f_ffree = attr->ffree; + stbuf->f_namelen = attr->namelen; + /* fsid is left zero */ } static int fuse_statfs(struct dentry *dentry, struct kstatfs *buf) { struct super_block *sb = dentry->d_sb; - struct fuse_mount *fm = get_fuse_mount_super(sb); + struct fuse_conn *fc = get_fuse_conn_super(sb); FUSE_ARGS(args); struct fuse_statfs_out outarg; int err; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; -#endif - if (!fuse_allow_current_process(fm->fc)) { + if (!fuse_allow_current_process(fc)) { buf->f_type = FUSE_SUPER_MAGIC; return 0; } -#ifdef CONFIG_FUSE_BPF - fer = fuse_bpf_backing(dentry->d_inode, struct fuse_statfs_out, - fuse_statfs_initialize, fuse_statfs_backing, - fuse_statfs_finalize, - dentry, buf); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - memset(&outarg, 0, sizeof(outarg)); args.in_numargs = 0; args.opcode = FUSE_STATFS; @@ -618,7 +446,7 @@ static int fuse_statfs(struct dentry *dentry, struct kstatfs *buf) args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (!err) convert_fuse_statfs(buf, &outarg.st); return err; @@ -635,9 +463,6 @@ enum { OPT_ALLOW_OTHER, OPT_MAX_READ, OPT_BLKSIZE, - OPT_ROOT_BPF, - OPT_ROOT_DIR, - OPT_NO_DAEMON, OPT_ERR }; @@ -652,9 +477,6 @@ static const struct fs_parameter_spec fuse_param_specs[] = { fsparam_u32 ("max_read", OPT_MAX_READ), fsparam_u32 ("blksize", OPT_BLKSIZE), fsparam_string ("subtype", OPT_SUBTYPE), - fsparam_u32 ("root_bpf", OPT_ROOT_BPF), - fsparam_u32 ("root_dir", OPT_ROOT_DIR), - fsparam_flag ("no_daemon", OPT_NO_DAEMON), {} }; @@ -663,90 +485,70 @@ static const struct fs_parameter_description fuse_fs_parameters = { .specs = fuse_param_specs, }; -static int fuse_parse_param(struct fs_context *fsc, struct fs_parameter *param) +static int fuse_parse_param(struct fs_context *fc, struct fs_parameter *param) { struct fs_parse_result result; - struct fuse_fs_context *ctx = fsc->fs_private; + struct fuse_fs_context *ctx = fc->fs_private; int opt; - kuid_t kuid; - kgid_t kgid; - if (fsc->purpose == FS_CONTEXT_FOR_RECONFIGURE) { - /* - * Ignore options coming from mount(MS_REMOUNT) for backward - * compatibility. - */ - if (fsc->oldapi) - return 0; + /* + * Ignore options coming from mount(MS_REMOUNT) for backward + * compatibility. + */ + if (fc->purpose == FS_CONTEXT_FOR_RECONFIGURE) + return 0; - return invalf(fsc, "No changes allowed in reconfigure"); - } - - opt = fs_parse(fsc, &fuse_fs_parameters, param, &result); + opt = fs_parse(fc, &fuse_fs_parameters, param, &result); if (opt < 0) return opt; switch (opt) { case OPT_SOURCE: - if (fsc->source) - return invalf(fsc, "Multiple sources specified"); - fsc->source = param->string; + if (fc->source) + return invalf(fc, "fuse: Multiple sources specified"); + fc->source = param->string; param->string = NULL; break; case OPT_SUBTYPE: if (ctx->subtype) - return invalf(fsc, "Multiple subtypes specified"); + return invalf(fc, "fuse: Multiple subtypes specified"); ctx->subtype = param->string; param->string = NULL; return 0; case OPT_FD: ctx->fd = result.uint_32; - ctx->fd_present = true; + ctx->fd_present = 1; break; case OPT_ROOTMODE: if (!fuse_valid_type(result.uint_32)) - return invalf(fsc, "Invalid rootmode"); + return invalf(fc, "fuse: Invalid rootmode"); ctx->rootmode = result.uint_32; - ctx->rootmode_present = true; + ctx->rootmode_present = 1; break; case OPT_USER_ID: - kuid = make_kuid(fsc->user_ns, result.uint_32); - if (!uid_valid(kuid)) - return invalf(fsc, "Invalid user_id"); - /* - * The requested uid must be representable in the - * filesystem's idmapping. - */ - if (!kuid_has_mapping(fsc->user_ns, kuid)) - return invalf(fsc, "Invalid user_id"); - ctx->user_id = kuid; - ctx->user_id_present = true; + ctx->user_id = make_kuid(fc->user_ns, result.uint_32); + if (!uid_valid(ctx->user_id)) + return invalf(fc, "fuse: Invalid user_id"); + ctx->user_id_present = 1; break; case OPT_GROUP_ID: - kgid = make_kgid(fsc->user_ns, result.uint_32);; - if (!gid_valid(kgid)) - return invalf(fsc, "Invalid group_id"); - /* - * The requested gid must be representable in the - * filesystem's idmapping. - */ - if (!kgid_has_mapping(fsc->user_ns, kgid)) - return invalf(fsc, "Invalid group_id"); - ctx->group_id = kgid; - ctx->group_id_present = true; + ctx->group_id = make_kgid(fc->user_ns, result.uint_32); + if (!gid_valid(ctx->group_id)) + return invalf(fc, "fuse: Invalid group_id"); + ctx->group_id_present = 1; break; case OPT_DEFAULT_PERMISSIONS: - ctx->default_permissions = true; + ctx->default_permissions = 1; break; case OPT_ALLOW_OTHER: - ctx->allow_other = true; + ctx->allow_other = 1; break; case OPT_MAX_READ: @@ -755,30 +557,10 @@ static int fuse_parse_param(struct fs_context *fsc, struct fs_parameter *param) case OPT_BLKSIZE: if (!ctx->is_bdev) - return invalf(fsc, "blksize only supported for fuseblk"); + return invalf(fc, "fuse: blksize only supported for fuseblk"); ctx->blksize = result.uint_32; break; - case OPT_ROOT_BPF: - ctx->root_bpf = bpf_prog_get_type_dev(result.uint_32, - BPF_PROG_TYPE_FUSE, false); - if (IS_ERR(ctx->root_bpf)) { - ctx->root_bpf = NULL; - return invalf(fsc, "Unable to open bpf program"); - } - break; - - case OPT_ROOT_DIR: - ctx->root_dir = fget(result.uint_32); - if (!ctx->root_dir) - return invalf(fsc, "Unable to open root directory"); - break; - - case OPT_NO_DAEMON: - ctx->no_daemon = true; - ctx->fd_present = true; - break; - default: return -EINVAL; } @@ -786,15 +568,11 @@ static int fuse_parse_param(struct fs_context *fsc, struct fs_parameter *param) return 0; } -static void fuse_free_fsc(struct fs_context *fsc) +static void fuse_free_fc(struct fs_context *fc) { - struct fuse_fs_context *ctx = fsc->fs_private; + struct fuse_fs_context *ctx = fc->fs_private; if (ctx) { - if (ctx->root_dir) - fput(ctx->root_dir); - if (ctx->root_bpf) - bpf_prog_put(ctx->root_bpf); kfree(ctx->subtype); kfree(ctx); } @@ -805,25 +583,19 @@ static int fuse_show_options(struct seq_file *m, struct dentry *root) struct super_block *sb = root->d_sb; struct fuse_conn *fc = get_fuse_conn_super(sb); - if (fc->legacy_opts_show) { - seq_printf(m, ",user_id=%u", - from_kuid_munged(fc->user_ns, fc->user_id)); - seq_printf(m, ",group_id=%u", - from_kgid_munged(fc->user_ns, fc->group_id)); - if (fc->default_permissions) - seq_puts(m, ",default_permissions"); - if (fc->allow_other) - seq_puts(m, ",allow_other"); - if (fc->max_read != ~0) - seq_printf(m, ",max_read=%u", fc->max_read); - if (sb->s_bdev && sb->s_blocksize != FUSE_DEFAULT_BLKSIZE) - seq_printf(m, ",blksize=%lu", sb->s_blocksize); - } -#ifdef CONFIG_FUSE_DAX - if (fc->dax) - seq_puts(m, ",dax"); -#endif + if (fc->no_mount_options) + return 0; + seq_printf(m, ",user_id=%u", from_kuid_munged(fc->user_ns, fc->user_id)); + seq_printf(m, ",group_id=%u", from_kgid_munged(fc->user_ns, fc->group_id)); + if (fc->default_permissions) + seq_puts(m, ",default_permissions"); + if (fc->allow_other) + seq_puts(m, ",allow_other"); + if (fc->max_read != ~0) + seq_printf(m, ",max_read=%u", fc->max_read); + if (sb->s_bdev && sb->s_blocksize != FUSE_DEFAULT_BLKSIZE) + seq_printf(m, ",blksize=%lu", sb->s_blocksize); return 0; } @@ -853,8 +625,7 @@ static void fuse_pqueue_init(struct fuse_pqueue *fpq) fpq->connected = 1; } -void fuse_conn_init(struct fuse_conn *fc, struct fuse_mount *fm, - struct user_namespace *user_ns, +void fuse_conn_init(struct fuse_conn *fc, struct user_namespace *user_ns, const struct fuse_iqueue_ops *fiq_ops, void *fiq_priv) { memset(fc, 0, sizeof(*fc)); @@ -883,12 +654,6 @@ void fuse_conn_init(struct fuse_conn *fc, struct fuse_mount *fm, fc->pid_ns = get_pid_ns(task_active_pid_ns(current)); fc->user_ns = get_user_ns(user_ns); fc->max_pages = FUSE_DEFAULT_MAX_PAGES_PER_REQ; - fc->max_pages_limit = FUSE_MAX_MAX_PAGES; - - INIT_LIST_HEAD(&fc->mounts); - list_add(&fm->fc_entry, &fc->mounts); - fm->fc = fc; - refcount_set(&fm->count, 1); } EXPORT_SYMBOL_GPL(fuse_conn_init); @@ -897,8 +662,6 @@ void fuse_conn_put(struct fuse_conn *fc) if (refcount_dec_and_test(&fc->count)) { struct fuse_iqueue *fiq = &fc->iq; - if (IS_ENABLED(CONFIG_FUSE_DAX)) - fuse_dax_conn_free(fc); if (fiq->ops->release) fiq->ops->release(fiq); put_pid_ns(fc->pid_ns); @@ -915,51 +678,15 @@ struct fuse_conn *fuse_conn_get(struct fuse_conn *fc) } EXPORT_SYMBOL_GPL(fuse_conn_get); -void fuse_mount_put(struct fuse_mount *fm) -{ - if (refcount_dec_and_test(&fm->count)) { - if (fm->fc) - fuse_conn_put(fm->fc); - kfree(fm); - } -} -EXPORT_SYMBOL_GPL(fuse_mount_put); - -struct fuse_mount *fuse_mount_get(struct fuse_mount *fm) -{ - refcount_inc(&fm->count); - return fm; -} -EXPORT_SYMBOL_GPL(fuse_mount_get); - -static struct inode *fuse_get_root_inode(struct super_block *sb, - unsigned int mode, - struct bpf_prog *root_bpf, - struct file *backing_fd) +static struct inode *fuse_get_root_inode(struct super_block *sb, unsigned mode) { struct fuse_attr attr; - struct inode *inode; - memset(&attr, 0, sizeof(attr)); + attr.mode = mode; attr.ino = FUSE_ROOT_ID; attr.nlink = 1; - inode = fuse_iget(sb, 1, 0, &attr, 0, 0); - if (!inode) - return NULL; - -#ifdef CONFIG_FUSE_BPF - get_fuse_inode(inode)->bpf = root_bpf; - if (root_bpf) - bpf_prog_inc(root_bpf); - - if (backing_fd) { - get_fuse_inode(inode)->backing_inode = backing_fd->f_inode; - ihold(backing_fd->f_inode); - } -#endif - - return inode; + return fuse_iget(sb, 1, 0, &attr, 0, 0); } struct fuse_inode_handle { @@ -974,14 +701,11 @@ static struct dentry *fuse_get_dentry(struct super_block *sb, struct inode *inode; struct dentry *entry; int err = -ESTALE; - struct fuse_inode_identifier fii = { - .nodeid = handle->nodeid, - }; if (handle->nodeid == 0) goto out_err; - inode = ilookup5(sb, handle->nodeid, fuse_inode_eq, &fii); + inode = ilookup5(sb, handle->nodeid, fuse_inode_eq, &handle->nodeid); if (!inode) { struct fuse_entry_out outarg; const struct qstr name = QSTR_INIT(".", 1); @@ -990,7 +714,7 @@ static struct dentry *fuse_get_dentry(struct super_block *sb, goto out_err; err = fuse_lookup_name(sb, handle->nodeid, &name, &outarg, - NULL, &inode); + &inode); if (err && err != -ENOENT) goto out_err; if (err || !inode) { @@ -1091,7 +815,7 @@ static struct dentry *fuse_get_parent(struct dentry *child) return ERR_PTR(-ESTALE); err = fuse_lookup_name(child_inode->i_sb, get_node_id(child_inode), - &name, &outarg, NULL, &inode); + &name, &outarg, &inode); if (err) { if (err == -ENOENT) return ERR_PTR(-ESTALE); @@ -1114,9 +838,6 @@ static const struct export_operations fuse_export_operations = { static const struct super_operations fuse_super_operations = { .alloc_inode = fuse_alloc_inode, -#ifdef CONFIG_FUSE_BPF - .destroy_inode = fuse_destroy_inode, -#endif .free_inode = fuse_free_inode, .evict_inode = fuse_evict_inode, .write_inode = fuse_write_inode, @@ -1186,16 +907,14 @@ struct fuse_init_args { struct fuse_init_out out; }; -static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args, +static void process_init_reply(struct fuse_conn *fc, struct fuse_args *args, int error) { - struct fuse_conn *fc = fm->fc; struct fuse_init_args *ia = container_of(args, typeof(*ia), args); struct fuse_init_out *arg = &ia->out; - bool ok = true; if (error || arg->major != FUSE_KERNEL_VERSION) - ok = false; + fc->conn_error = 1; else { unsigned long ra_pages; @@ -1243,11 +962,11 @@ static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args, if (arg->flags & FUSE_HANDLE_KILLPRIV) fc->handle_killpriv = 1; if (arg->time_gran && arg->time_gran <= 1000000000) - fm->sb->s_time_gran = arg->time_gran; + fc->sb->s_time_gran = arg->time_gran; if ((arg->flags & FUSE_POSIX_ACL)) { fc->default_permissions = 1; fc->posix_acl = 1; - fm->sb->s_xattr = fuse_acl_xattr_handlers; + fc->sb->s_xattr = fuse_acl_xattr_handlers; } if (arg->flags & FUSE_CACHE_SYMLINKS) fc->cache_symlinks = 1; @@ -1255,18 +974,13 @@ static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args, fc->abort_err = 1; if (arg->flags & FUSE_MAX_PAGES) { fc->max_pages = - min_t(unsigned int, fc->max_pages_limit, + min_t(unsigned int, FUSE_MAX_MAX_PAGES, max_t(unsigned int, arg->max_pages, 1)); } - if (IS_ENABLED(CONFIG_FUSE_DAX) && - arg->flags & FUSE_MAP_ALIGNMENT && - !fuse_dax_check_alignment(fc, arg->map_alignment)) { - ok = false; - } if (arg->flags & FUSE_PASSTHROUGH) { fc->passthrough = 1; /* Prevent further stacking */ - fm->sb->s_stack_depth = + fc->sb->s_stack_depth = FILESYSTEM_MAX_STACK_DEPTH; } } else { @@ -1275,8 +989,8 @@ static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args, fc->no_flock = 1; } - fm->sb->s_bdi->ra_pages = - min(fm->sb->s_bdi->ra_pages, ra_pages); + fc->sb->s_bdi->ra_pages = + min(fc->sb->s_bdi->ra_pages, ra_pages); fc->minor = arg->minor; fc->max_write = arg->minor < 5 ? 4096 : arg->max_write; fc->max_write = max_t(unsigned, 4096, fc->max_write); @@ -1284,16 +998,11 @@ static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args, } kfree(ia); - if (!ok) { - fc->conn_init = 0; - fc->conn_error = 1; - } - fuse_set_initialized(fc); wake_up_all(&fc->blocked_waitq); } -void fuse_send_init(struct fuse_mount *fm) +void fuse_send_init(struct fuse_conn *fc) { struct fuse_init_args *ia; @@ -1301,7 +1010,7 @@ void fuse_send_init(struct fuse_mount *fm) ia->in.major = FUSE_KERNEL_VERSION; ia->in.minor = FUSE_KERNEL_MINOR_VERSION; - ia->in.max_readahead = fm->sb->s_bdi->ra_pages * PAGE_SIZE; + ia->in.max_readahead = fc->sb->s_bdi->ra_pages * PAGE_SIZE; ia->in.flags |= FUSE_ASYNC_READ | FUSE_POSIX_LOCKS | FUSE_ATOMIC_O_TRUNC | FUSE_EXPORT_SUPPORT | FUSE_BIG_WRITES | FUSE_DONT_MASK | @@ -1313,13 +1022,6 @@ void fuse_send_init(struct fuse_mount *fm) FUSE_ABORT_ERROR | FUSE_MAX_PAGES | FUSE_CACHE_SYMLINKS | FUSE_NO_OPENDIR_SUPPORT | FUSE_EXPLICIT_INVAL_DATA | FUSE_PASSTHROUGH; -#ifdef CONFIG_FUSE_DAX - if (fm->fc->dax) - ia->in.flags |= FUSE_MAP_ALIGNMENT; -#endif - if (fm->fc->auto_submounts) - ia->in.flags |= FUSE_SUBMOUNTS; - ia->args.opcode = FUSE_INIT; ia->args.in_numargs = 1; ia->args.in_args[0].size = sizeof(ia->in); @@ -1328,15 +1030,15 @@ void fuse_send_init(struct fuse_mount *fm) /* Variable length argument used for backward compatibility with interface version < 7.5. Rest of init_out is zeroed by do_get_request(), so a short reply is not a problem */ - ia->args.out_argvar = true; + ia->args.out_argvar = 1; ia->args.out_args[0].size = sizeof(ia->out); ia->args.out_args[0].value = &ia->out; ia->args.force = true; ia->args.nocreds = true; ia->args.end = process_init_reply; - if (unlikely(fm->fc->no_daemon) || fuse_simple_background(fm, &ia->args, GFP_KERNEL) != 0) - process_init_reply(fm, &ia->args, -ENOTCONN); + if (fuse_simple_background(fc, &ia->args, GFP_KERNEL) != 0) + process_init_reply(fc, &ia->args, -ENOTCONN); } EXPORT_SYMBOL_GPL(fuse_send_init); @@ -1378,6 +1080,7 @@ static int fuse_bdi_init(struct fuse_conn *fc, struct super_block *sb) if (err) return err; + sb->s_bdi->ra_pages = VM_READAHEAD_PAGES; /* fuse does it's own writeback accounting */ sb->s_bdi->capabilities = BDI_CAP_NO_ACCT_WB | BDI_CAP_STRICTLIMIT; @@ -1458,70 +1161,10 @@ void fuse_dev_free(struct fuse_dev *fud) } EXPORT_SYMBOL_GPL(fuse_dev_free); -static void fuse_sb_defaults(struct super_block *sb) -{ - sb->s_magic = FUSE_SUPER_MAGIC; - sb->s_op = &fuse_super_operations; - sb->s_xattr = fuse_xattr_handlers; - sb->s_maxbytes = MAX_LFS_FILESIZE; - sb->s_time_gran = 1; - sb->s_export_op = &fuse_export_operations; - sb->s_iflags |= SB_I_IMA_UNVERIFIABLE_SIGNATURE; - if (sb->s_user_ns != &init_user_ns) - sb->s_iflags |= SB_I_UNTRUSTED_MOUNTER; - sb->s_flags &= ~(SB_NOSEC | SB_I_VERSION); - - /* - * If we are not in the initial user namespace posix - * acls must be translated. - */ - if (sb->s_user_ns != &init_user_ns) - sb->s_xattr = fuse_no_acl_xattr_handlers; -} - -int fuse_fill_super_submount(struct super_block *sb, - struct fuse_inode *parent_fi) -{ - struct fuse_mount *fm = get_fuse_mount_super(sb); - struct super_block *parent_sb = parent_fi->inode.i_sb; - struct fuse_attr root_attr; - struct inode *root; - - fuse_sb_defaults(sb); - fm->sb = sb; - - WARN_ON(sb->s_bdi != &noop_backing_dev_info); - sb->s_bdi = bdi_get(parent_sb->s_bdi); - - sb->s_xattr = parent_sb->s_xattr; - sb->s_time_gran = parent_sb->s_time_gran; - sb->s_blocksize = parent_sb->s_blocksize; - sb->s_blocksize_bits = parent_sb->s_blocksize_bits; - sb->s_subtype = kstrdup(parent_sb->s_subtype, GFP_KERNEL); - if (parent_sb->s_subtype && !sb->s_subtype) - return -ENOMEM; - - fuse_fill_attr_from_inode(&root_attr, &parent_fi->inode); - root = fuse_iget(sb, parent_fi->nodeid, 0, &root_attr, 0, 0); - /* - * This inode is just a duplicate, so it is not looked up and - * its nlookup should not be incremented. fuse_iget() does - * that, though, so undo it here. - */ - get_fuse_inode(root)->nlookup--; - sb->s_d_op = &fuse_dentry_operations; - sb->s_root = d_make_root(root); - if (!sb->s_root) - return -ENOMEM; - - return 0; -} - int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx) { - struct fuse_dev *fud = NULL; - struct fuse_mount *fm = get_fuse_mount_super(sb); - struct fuse_conn *fc = fm->fc; + struct fuse_dev *fud; + struct fuse_conn *fc = get_fuse_conn_super(sb); struct inode *root; struct dentry *root_dentry; int err; @@ -1530,7 +1173,7 @@ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx) if (sb->s_flags & SB_MANDLOCK) goto err; - fuse_sb_defaults(sb); + sb->s_flags &= ~(SB_NOSEC | SB_I_VERSION); if (ctx->is_bdev) { #ifdef CONFIG_BLOCK @@ -1545,21 +1188,29 @@ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx) sb->s_subtype = ctx->subtype; ctx->subtype = NULL; - if (IS_ENABLED(CONFIG_FUSE_DAX)) { - err = fuse_dax_conn_alloc(fc, ctx->dax_dev); - if (err) - goto err; - } + sb->s_magic = FUSE_SUPER_MAGIC; + sb->s_op = &fuse_super_operations; + sb->s_xattr = fuse_xattr_handlers; + sb->s_maxbytes = MAX_LFS_FILESIZE; + sb->s_time_gran = 1; + sb->s_export_op = &fuse_export_operations; + sb->s_iflags |= SB_I_IMA_UNVERIFIABLE_SIGNATURE; + if (sb->s_user_ns != &init_user_ns) + sb->s_iflags |= SB_I_UNTRUSTED_MOUNTER; - if (ctx->fudptr) { - err = -ENOMEM; - fud = fuse_dev_alloc_install(fc); - if (!fud) - goto err_free_dax; - } + /* + * If we are not in the initial user namespace posix + * acls must be translated. + */ + if (sb->s_user_ns != &init_user_ns) + sb->s_xattr = fuse_no_acl_xattr_handlers; + + fud = fuse_dev_alloc_install(fc); + if (!fud) + goto err; fc->dev = sb->s_dev; - fm->sb = sb; + fc->sb = sb; err = fuse_bdi_init(fc, sb); if (err) goto err_dev_free; @@ -1573,27 +1224,24 @@ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx) fc->allow_other = ctx->allow_other; fc->user_id = ctx->user_id; fc->group_id = ctx->group_id; - fc->legacy_opts_show = ctx->legacy_opts_show; - fc->max_read = max_t(unsigned int, 4096, ctx->max_read); + fc->max_read = max_t(unsigned, 4096, ctx->max_read); fc->destroy = ctx->destroy; fc->no_control = ctx->no_control; fc->no_force_umount = ctx->no_force_umount; - fc->no_daemon = ctx->no_daemon; + fc->no_mount_options = ctx->no_mount_options; err = -ENOMEM; - root = fuse_get_root_inode(sb, ctx->rootmode, ctx->root_bpf, - ctx->root_dir); + root = fuse_get_root_inode(sb, ctx->rootmode); sb->s_d_op = &fuse_root_dentry_operations; root_dentry = d_make_root(root); if (!root_dentry) goto err_dev_free; - fuse_init_dentry_root(root_dentry, ctx->root_dir); /* Root dentry doesn't have .d_revalidate */ sb->s_d_op = &fuse_dentry_operations; mutex_lock(&fuse_mutex); err = -EINVAL; - if (ctx->fudptr && *ctx->fudptr) + if (*ctx->fudptr) goto err_unlock; err = fuse_ctl_add_conn(fc); @@ -1602,8 +1250,7 @@ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx) list_add_tail(&fc->entry, &fuse_conn_list); sb->s_root = root_dentry; - if (ctx->fudptr) - *ctx->fudptr = fud; + *ctx->fudptr = fud; mutex_unlock(&fuse_mutex); return 0; @@ -1611,11 +1258,7 @@ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx) mutex_unlock(&fuse_mutex); dput(root_dentry); err_dev_free: - if (fud) - fuse_dev_free(fud); - err_free_dax: - if (IS_ENABLED(CONFIG_FUSE_DAX)) - fuse_dax_conn_free(fc); + fuse_dev_free(fud); err: return err; } @@ -1627,39 +1270,29 @@ static int fuse_fill_super(struct super_block *sb, struct fs_context *fsc) struct file *file; int err; struct fuse_conn *fc; - struct fuse_mount *fm; err = -EINVAL; - if (!ctx->no_daemon) { - file = fget(ctx->fd); - if (!file) - goto err; + file = fget(ctx->fd); + if (!file) + goto err; - /* - * Require mount to happen from the same user namespace which - * opened /dev/fuse to prevent potential attacks. - */ - if ((file->f_op != &fuse_dev_operations) || - (file->f_cred->user_ns != sb->s_user_ns)) - goto err_fput; - ctx->fudptr = &file->private_data; - } + /* + * Require mount to happen from the same user namespace which + * opened /dev/fuse to prevent potential attacks. + */ + if ((file->f_op != &fuse_dev_operations) || + (file->f_cred->user_ns != sb->s_user_ns)) + goto err_fput; + ctx->fudptr = &file->private_data; fc = kmalloc(sizeof(*fc), GFP_KERNEL); err = -ENOMEM; if (!fc) goto err_fput; - fm = kzalloc(sizeof(*fm), GFP_KERNEL); - if (!fm) { - kfree(fc); - goto err_fput; - } - - fuse_conn_init(fc, fm, sb->s_user_ns, &fuse_dev_fiq_ops, NULL); + fuse_conn_init(fc, sb->s_user_ns, &fuse_dev_fiq_ops, NULL); fc->release = fuse_free_conn; - - sb->s_fs_info = fm; + sb->s_fs_info = fc; err = fuse_fill_super_common(sb, ctx); if (err) @@ -1669,24 +1302,22 @@ static int fuse_fill_super(struct super_block *sb, struct fs_context *fsc) * memory barrier for file->private_data to be visible on all * CPUs after this */ - if (!ctx->no_daemon) - fput(file); - fuse_send_init(get_fuse_mount_super(sb)); + fput(file); + fuse_send_init(get_fuse_conn_super(sb)); return 0; err_put_conn: - fuse_mount_put(fm); + fuse_conn_put(fc); sb->s_fs_info = NULL; err_fput: - if (!ctx->no_daemon) - fput(file); + fput(file); err: return err; } -static int fuse_get_tree(struct fs_context *fsc) +static int fuse_get_tree(struct fs_context *fc) { - struct fuse_fs_context *ctx = fsc->fs_private; + struct fuse_fs_context *ctx = fc->fs_private; if (!ctx->fd_present || !ctx->rootmode_present || !ctx->user_id_present || !ctx->group_id_present) @@ -1694,14 +1325,14 @@ static int fuse_get_tree(struct fs_context *fsc) #ifdef CONFIG_BLOCK if (ctx->is_bdev) - return get_tree_bdev(fsc, fuse_fill_super); + return get_tree_bdev(fc, fuse_fill_super); #endif - return get_tree_nodev(fsc, fuse_fill_super); + return get_tree_nodev(fc, fuse_fill_super); } static const struct fs_context_operations fuse_context_ops = { - .free = fuse_free_fsc, + .free = fuse_free_fc, .parse_param = fuse_parse_param, .reconfigure = fuse_reconfigure, .get_tree = fuse_get_tree, @@ -1710,7 +1341,7 @@ static const struct fs_context_operations fuse_context_ops = { /* * Set up the filesystem mount context. */ -static int fuse_init_fs_context(struct fs_context *fsc) +static int fuse_init_fs_context(struct fs_context *fc) { struct fuse_fs_context *ctx; @@ -1720,66 +1351,42 @@ static int fuse_init_fs_context(struct fs_context *fsc) ctx->max_read = ~0; ctx->blksize = FUSE_DEFAULT_BLKSIZE; - ctx->legacy_opts_show = true; #ifdef CONFIG_BLOCK - if (fsc->fs_type == &fuseblk_fs_type) { + if (fc->fs_type == &fuseblk_fs_type) { ctx->is_bdev = true; ctx->destroy = true; } #endif - fsc->fs_private = ctx; - fsc->ops = &fuse_context_ops; + fc->fs_private = ctx; + fc->ops = &fuse_context_ops; return 0; } -bool fuse_mount_remove(struct fuse_mount *fm) +static void fuse_sb_destroy(struct super_block *sb) { - struct fuse_conn *fc = fm->fc; - bool last = false; + struct fuse_conn *fc = get_fuse_conn_super(sb); - down_write(&fc->killsb); - list_del_init(&fm->fc_entry); - if (list_empty(&fc->mounts)) - last = true; - up_write(&fc->killsb); + if (fc) { + if (fc->destroy) + fuse_send_destroy(fc); - return last; -} -EXPORT_SYMBOL_GPL(fuse_mount_remove); + fuse_abort_conn(fc); + fuse_wait_aborted(fc); -void fuse_conn_destroy(struct fuse_mount *fm) -{ - struct fuse_conn *fc = fm->fc; - - if (fc->destroy) - fuse_send_destroy(fm); - - fuse_abort_conn(fc); - fuse_wait_aborted(fc); - - if (!list_empty(&fc->entry)) { - mutex_lock(&fuse_mutex); - list_del(&fc->entry); - fuse_ctl_remove_conn(fc); - mutex_unlock(&fuse_mutex); + down_write(&fc->killsb); + fc->sb = NULL; + up_write(&fc->killsb); } } -EXPORT_SYMBOL_GPL(fuse_conn_destroy); -static void fuse_kill_sb_anon(struct super_block *sb) +void fuse_kill_sb_anon(struct super_block *sb) { - struct fuse_mount *fm = get_fuse_mount_super(sb); - bool last; - - if (fm) { - last = fuse_mount_remove(fm); - if (last) - fuse_conn_destroy(fm); - } + fuse_sb_destroy(sb); kill_anon_super(sb); } +EXPORT_SYMBOL_GPL(fuse_kill_sb_anon); static struct file_system_type fuse_fs_type = { .owner = THIS_MODULE, @@ -1794,14 +1401,7 @@ MODULE_ALIAS_FS("fuse"); #ifdef CONFIG_BLOCK static void fuse_kill_sb_blk(struct super_block *sb) { - struct fuse_mount *fm = get_fuse_mount_super(sb); - bool last; - - if (sb->s_root) { - last = fuse_mount_remove(fm); - if (last) - fuse_conn_destroy(fm); - } + fuse_sb_destroy(sb); kill_block_super(sb); } @@ -1887,61 +1487,6 @@ static void fuse_fs_cleanup(void) static struct kobject *fuse_kobj; -#ifdef CONFIG_FUSE_BPF -static ssize_t fuse_bpf_show(struct kobject *kobj, - struct kobj_attribute *attr, char *buff) -{ - return sysfs_emit(buff, "supported\n"); -} - -static struct kobj_attribute fuse_bpf_attr = - __ATTR_RO(fuse_bpf); -#endif - -static struct attribute *bpf_features[] = { -#ifdef CONFIG_FUSE_BPF - &fuse_bpf_attr.attr, -#endif - NULL, -}; - -static const struct attribute_group bpf_features_group = { - .name = "features", - .attrs = bpf_features, -}; - -/* - * TODO Remove this once fuse-bpf is upstreamed - * - * bpf_prog_type_fuse exports the bpf_prog_type_fuse 'constant', which cannot be - * constant until the code is upstreamed - */ -static ssize_t bpf_prog_type_fuse_show(struct kobject *kobj, - struct kobj_attribute *attr, char *buff) -{ - return sysfs_emit(buff, "%d\n", BPF_PROG_TYPE_FUSE); -} - -static struct kobj_attribute bpf_prog_type_fuse_attr = - __ATTR_RO(bpf_prog_type_fuse); - -static struct attribute *bpf_attributes[] = { - &bpf_prog_type_fuse_attr.attr, - NULL, -}; - -static const struct attribute_group bpf_attr_group = { - .attrs = bpf_attributes, -}; - -static const struct attribute_group *attribute_groups[] = { - &bpf_features_group, - &bpf_attr_group, - NULL -}; - -/* TODO remove to here */ - static int fuse_sysfs_init(void) { int err; @@ -1956,15 +1501,8 @@ static int fuse_sysfs_init(void) if (err) goto out_fuse_unregister; - /* TODO Remove when BPF_PROG_TYPE_FUSE is upstreamed */ - err = sysfs_create_groups(fuse_kobj, attribute_groups); - if (err) - goto out_fuse_remove_mount_point; - return 0; - out_fuse_remove_mount_point: - sysfs_remove_mount_point(fuse_kobj, "connections"); out_fuse_unregister: kobject_put(fuse_kobj); out_err: @@ -1973,7 +1511,6 @@ static int fuse_sysfs_init(void) static void fuse_sysfs_cleanup(void) { - sysfs_remove_groups(fuse_kobj, attribute_groups); sysfs_remove_mount_point(fuse_kobj, "connections"); kobject_put(fuse_kobj); } @@ -2002,21 +1539,11 @@ static int __init fuse_init(void) if (res) goto err_sysfs_cleanup; -#ifdef CONFIG_FUSE_BPF - res = fuse_bpf_init(); - if (res) - goto err_ctl_cleanup; -#endif - sanitize_global_limit(&max_user_bgreq); sanitize_global_limit(&max_user_congthresh); return 0; -#ifdef CONFIG_FUSE_BPF - err_ctl_cleanup: - fuse_ctl_cleanup(); -#endif err_sysfs_cleanup: fuse_sysfs_cleanup(); err_dev_cleanup: @@ -2034,9 +1561,6 @@ static void __exit fuse_exit(void) fuse_ctl_cleanup(); fuse_sysfs_cleanup(); fuse_fs_cleanup(); -#ifdef CONFIG_FUSE_BPF - fuse_bpf_cleanup(); -#endif fuse_dev_cleanup(); } diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c index 1845e05db2da..95368ddfb53a 100644 --- a/fs/fuse/passthrough.c +++ b/fs/fuse/passthrough.c @@ -14,6 +14,18 @@ struct fuse_aio_req { struct kiocb *iocb_fuse; }; +static inline void kiocb_clone(struct kiocb *kiocb, struct kiocb *kiocb_src, + struct file *filp) +{ + *kiocb = (struct kiocb){ + .ki_filp = filp, + .ki_flags = kiocb_src->ki_flags, + .ki_hint = kiocb_src->ki_hint, + .ki_ioprio = kiocb_src->ki_ioprio, + .ki_pos = kiocb_src->ki_pos, + }; +} + static void fuse_file_accessed(struct file *dst_file, struct file *src_file) { struct inode *dst_inode; @@ -34,7 +46,7 @@ static void fuse_file_accessed(struct file *dst_file, struct file *src_file) touch_atime(&dst_file->f_path); } -void fuse_copyattr(struct file *dst_file, struct file *src_file) +static void fuse_copyattr(struct file *dst_file, struct file *src_file) { struct inode *dst = file_inode(dst_file); struct inode *src = file_inode(src_file); @@ -213,8 +225,7 @@ int fuse_passthrough_open(struct fuse_dev *fud, u32 lower_fd) } if (!passthrough_filp->f_op->read_iter || - !((passthrough_filp->f_path.mnt->mnt_flags | MNT_READONLY) || - passthrough_filp->f_op->write_iter)) { + !passthrough_filp->f_op->write_iter) { pr_err("FUSE: passthrough file misses file operations.\n"); res = -EBADF; goto err_free_file; diff --git a/fs/fuse/readdir.c b/fs/fuse/readdir.c index f9d0be56d34a..512609da8590 100644 --- a/fs/fuse/readdir.c +++ b/fs/fuse/readdir.c @@ -20,8 +20,6 @@ static bool fuse_use_readdirplus(struct inode *dir, struct dir_context *ctx) if (!fc->do_readdirplus) return false; - if (fi->nodeid == 0) - return false; if (!fc->readdirplus_auto) return true; if (test_and_clear_bit(FUSE_I_ADVISE_RDPLUS, &fi->state)) @@ -79,10 +77,8 @@ static void fuse_add_dirent_to_cache(struct file *file, goto unlock; addr = kmap_atomic(page); - if (!offset) { + if (!offset) clear_page(addr); - SetPageUptodate(page); - } memcpy(addr + offset, dirent, reclen); kunmap_atomic(addr); fi->rdc.size = (index << PAGE_SHIFT) + offset + reclen; @@ -204,12 +200,9 @@ retry: if (!d_in_lookup(dentry)) { struct fuse_inode *fi; inode = d_inode(dentry); - if (inode && get_node_id(inode) != o->nodeid) - inode = NULL; if (!inode || - fuse_stale_inode(inode, o->generation, &o->attr)) { - if (inode) - fuse_make_bad(inode); + get_node_id(inode) != o->nodeid || + ((o->attr.mode ^ inode->i_mode) & S_IFMT)) { d_invalidate(dentry); dput(dentry); goto retry; @@ -267,7 +260,7 @@ retry: static void fuse_force_forget(struct file *file, u64 nodeid) { struct inode *inode = file_inode(file); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_forget_in inarg; FUSE_ARGS(args); @@ -281,7 +274,7 @@ static void fuse_force_forget(struct file *file, u64 nodeid) args.force = true; args.noreply = true; - fuse_simple_request(fm, &args); + fuse_simple_request(fc, &args); /* ignore errors */ } @@ -335,7 +328,7 @@ static int fuse_readdir_uncached(struct file *file, struct dir_context *ctx) ssize_t res; struct page *page; struct inode *inode = file_inode(file); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_io_args ia = {}; struct fuse_args_pages *ap = &ia.ap; struct fuse_page_desc desc = { .length = PAGE_SIZE }; @@ -347,12 +340,12 @@ static int fuse_readdir_uncached(struct file *file, struct dir_context *ctx) return -ENOMEM; plus = fuse_use_readdirplus(inode, ctx); - ap->args.out_pages = true; + ap->args.out_pages = 1; ap->num_pages = 1; ap->pages = &page; ap->descs = &desc; if (plus) { - attr_version = fuse_get_attr_version(fm->fc); + attr_version = fuse_get_attr_version(fc); fuse_read_args_fill(&ia, file, ctx->pos, PAGE_SIZE, FUSE_READDIRPLUS); } else { @@ -360,7 +353,7 @@ static int fuse_readdir_uncached(struct file *file, struct dir_context *ctx) FUSE_READDIR); } locked = fuse_lock_inode(inode); - res = fuse_simple_request(fm, &ap->args); + res = fuse_simple_request(fc, &ap->args); fuse_unlock_inode(inode, locked); if (res >= 0) { if (!res) { @@ -528,12 +521,6 @@ retry_locked: page = find_get_page_flags(file->f_mapping, index, FGP_ACCESSED | FGP_LOCK); - /* Page gone missing, then re-added to cache, but not initialized? */ - if (page && !PageUptodate(page)) { - unlock_page(page); - put_page(page); - page = NULL; - } spin_lock(&fi->rdc.lock); if (!page) { /* @@ -589,26 +576,6 @@ int fuse_readdir(struct file *file, struct dir_context *ctx) struct inode *inode = file_inode(file); int err; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - bool allow_force; - bool force_again = false; - bool is_continued = false; - -again: - fer = fuse_bpf_backing(inode, struct fuse_read_io, - fuse_readdir_initialize, fuse_readdir_backing, - fuse_readdir_finalize, - file, ctx, &force_again, &allow_force, is_continued); - if (force_again && !IS_ERR(fer.result)) { - is_continued = true; - goto again; - } - - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fuse_is_bad(inode)) return -EIO; diff --git a/fs/fuse/virtio_fs.c b/fs/fuse/virtio_fs.c index c23a94d179fd..97259c6afac8 100644 --- a/fs/fuse/virtio_fs.c +++ b/fs/fuse/virtio_fs.c @@ -5,25 +5,14 @@ */ #include -#include -#include -#include #include #include #include #include #include -#include #include -#include #include "fuse_i.h" -/* Used to help calculate the FUSE connection's max_pages limit for a request's - * size. Parts of the struct fuse_req are sliced into scattergather lists in - * addition to the pages used, so this can help account for that overhead. - */ -#define FUSE_HEADER_OVERHEAD 4 - /* List of virtio-fs device instances and a lock for the list. Also provides * mutual exclusion in device removal and mounting path */ @@ -35,8 +24,6 @@ enum { VQ_REQUEST }; -#define VQ_NAME_LEN 24 - /* Per-virtqueue state */ struct virtio_fs_vq { spinlock_t lock; @@ -48,8 +35,7 @@ struct virtio_fs_vq { struct fuse_dev *fud; bool connected; long in_flight; - struct completion in_flight_zero; /* No inflight requests */ - char name[VQ_NAME_LEN]; + char name[24]; } ____cacheline_aligned_in_smp; /* A virtio-fs device instance */ @@ -60,23 +46,13 @@ struct virtio_fs { struct virtio_fs_vq *vqs; unsigned int nvqs; /* number of virtqueues */ unsigned int num_request_queues; /* number of request queues */ - struct dax_device *dax_dev; - - /* DAX memory window where file contents are mapped */ - void *window_kaddr; - phys_addr_t window_phys_addr; - size_t window_len; -}; - -struct virtio_fs_forget_req { - struct fuse_in_header ih; - struct fuse_forget_in arg; }; struct virtio_fs_forget { + struct fuse_in_header ih; + struct fuse_forget_in arg; /* This request can be temporarily queued on virt queue */ struct list_head list; - struct virtio_fs_forget_req req; }; struct virtio_fs_req_work { @@ -88,48 +64,6 @@ struct virtio_fs_req_work { static int virtio_fs_enqueue_req(struct virtio_fs_vq *fsvq, struct fuse_req *req, bool in_flight); -enum { - OPT_DAX, -}; - -static const struct fs_parameter_spec virtio_param_specs[] = { - fsparam_flag("dax", OPT_DAX), - {} -}; - -static const struct fs_parameter_description virtio_fs_parameters = { - .specs = virtio_param_specs, -}; - -static int virtio_fs_parse_param(struct fs_context *fsc, - struct fs_parameter *param) -{ - struct fs_parse_result result; - struct fuse_fs_context *ctx = fsc->fs_private; - int opt; - - opt = fs_parse(fsc, &virtio_fs_parameters, param, &result); - if (opt < 0) - return opt; - - switch (opt) { - case OPT_DAX: - ctx->dax = 1; - break; - default: - return -EINVAL; - } - - return 0; -} - -static void virtio_fs_free_fsc(struct fs_context *fsc) -{ - struct fuse_fs_context *ctx = fsc->fs_private; - - kfree(ctx); -} - static inline struct virtio_fs_vq *vq_to_fsvq(struct virtqueue *vq) { struct virtio_fs *fs = vq->vdev->priv; @@ -153,8 +87,6 @@ static inline void dec_in_flight_req(struct virtio_fs_vq *fsvq) { WARN_ON(fsvq->in_flight <= 0); fsvq->in_flight--; - if (!fsvq->in_flight) - complete(&fsvq->in_flight_zero); } static void release_virtio_fs_obj(struct kref *ref) @@ -185,23 +117,22 @@ static void virtio_fs_drain_queue(struct virtio_fs_vq *fsvq) WARN_ON(fsvq->in_flight < 0); /* Wait for in flight requests to finish.*/ - spin_lock(&fsvq->lock); - if (fsvq->in_flight) { - /* We are holding virtio_fs_mutex. There should not be any - * waiters waiting for completion. - */ - reinit_completion(&fsvq->in_flight_zero); - spin_unlock(&fsvq->lock); - wait_for_completion(&fsvq->in_flight_zero); - } else { + while (1) { + spin_lock(&fsvq->lock); + if (!fsvq->in_flight) { + spin_unlock(&fsvq->lock); + break; + } spin_unlock(&fsvq->lock); + /* TODO use completion instead of timeout */ + usleep_range(1000, 2000); } flush_work(&fsvq->done_work); flush_delayed_work(&fsvq->dispatch_work); } -static void virtio_fs_drain_all_queues_locked(struct virtio_fs *fs) +static void virtio_fs_drain_all_queues(struct virtio_fs *fs) { struct virtio_fs_vq *fsvq; int i; @@ -212,19 +143,6 @@ static void virtio_fs_drain_all_queues_locked(struct virtio_fs *fs) } } -static void virtio_fs_drain_all_queues(struct virtio_fs *fs) -{ - /* Provides mutual exclusion between ->remove and ->kill_sb - * paths. We don't want both of these draining queue at the - * same time. Current completion logic reinits completion - * and that means there should not be any other thread - * doing reinit or waiting for completion already. - */ - mutex_lock(&virtio_fs_mutex); - virtio_fs_drain_all_queues_locked(fs); - mutex_unlock(&virtio_fs_mutex); -} - static void virtio_fs_start_all_queues(struct virtio_fs *fs) { struct virtio_fs_vq *fsvq; @@ -360,6 +278,7 @@ static void virtio_fs_request_dispatch_work(struct work_struct *work) struct fuse_req *req; struct virtio_fs_vq *fsvq = container_of(work, struct virtio_fs_vq, dispatch_work.work); + struct fuse_conn *fc = fsvq->fud->fc; int ret; pr_debug("virtio-fs: worker %s called.\n", __func__); @@ -374,7 +293,7 @@ static void virtio_fs_request_dispatch_work(struct work_struct *work) list_del_init(&req->list); spin_unlock(&fsvq->lock); - fuse_request_end(req); + fuse_request_end(fc, req); } /* Dispatch pending requests */ @@ -405,77 +324,22 @@ static void virtio_fs_request_dispatch_work(struct work_struct *work) spin_unlock(&fsvq->lock); pr_err("virtio-fs: virtio_fs_enqueue_req() failed %d\n", ret); - fuse_request_end(req); + fuse_request_end(fc, req); } } } -/* - * Returns 1 if queue is full and sender should wait a bit before sending - * next request, 0 otherwise. - */ -static int send_forget_request(struct virtio_fs_vq *fsvq, - struct virtio_fs_forget *forget, - bool in_flight) -{ - struct scatterlist sg; - struct virtqueue *vq; - int ret = 0; - bool notify; - struct virtio_fs_forget_req *req = &forget->req; - - spin_lock(&fsvq->lock); - if (!fsvq->connected) { - if (in_flight) - dec_in_flight_req(fsvq); - kfree(forget); - goto out; - } - - sg_init_one(&sg, req, sizeof(*req)); - vq = fsvq->vq; - dev_dbg(&vq->vdev->dev, "%s\n", __func__); - - ret = virtqueue_add_outbuf(vq, &sg, 1, forget, GFP_ATOMIC); - if (ret < 0) { - if (ret == -ENOMEM || ret == -ENOSPC) { - pr_debug("virtio-fs: Could not queue FORGET: err=%d. Will try later\n", - ret); - list_add_tail(&forget->list, &fsvq->queued_reqs); - schedule_delayed_work(&fsvq->dispatch_work, - msecs_to_jiffies(1)); - if (!in_flight) - inc_in_flight_req(fsvq); - /* Queue is full */ - ret = 1; - } else { - pr_debug("virtio-fs: Could not queue FORGET: err=%d. Dropping it.\n", - ret); - kfree(forget); - if (in_flight) - dec_in_flight_req(fsvq); - } - goto out; - } - - if (!in_flight) - inc_in_flight_req(fsvq); - notify = virtqueue_kick_prepare(vq); - spin_unlock(&fsvq->lock); - - if (notify) - virtqueue_notify(vq); - return ret; -out: - spin_unlock(&fsvq->lock); - return ret; -} - static void virtio_fs_hiprio_dispatch_work(struct work_struct *work) { struct virtio_fs_forget *forget; struct virtio_fs_vq *fsvq = container_of(work, struct virtio_fs_vq, dispatch_work.work); + struct virtqueue *vq = fsvq->vq; + struct scatterlist sg; + struct scatterlist *sgs[] = {&sg}; + bool notify; + int ret; + pr_debug("virtio-fs: worker %s called.\n", __func__); while (1) { spin_lock(&fsvq->lock); @@ -487,9 +351,43 @@ static void virtio_fs_hiprio_dispatch_work(struct work_struct *work) } list_del(&forget->list); - spin_unlock(&fsvq->lock); - if (send_forget_request(fsvq, forget, true)) + if (!fsvq->connected) { + dec_in_flight_req(fsvq); + spin_unlock(&fsvq->lock); + kfree(forget); + continue; + } + + sg_init_one(&sg, forget, sizeof(*forget)); + + /* Enqueue the request */ + dev_dbg(&vq->vdev->dev, "%s\n", __func__); + ret = virtqueue_add_sgs(vq, sgs, 1, 0, forget, GFP_ATOMIC); + if (ret < 0) { + if (ret == -ENOMEM || ret == -ENOSPC) { + pr_debug("virtio-fs: Could not queue FORGET: err=%d. Will try later\n", + ret); + list_add_tail(&forget->list, + &fsvq->queued_reqs); + schedule_delayed_work(&fsvq->dispatch_work, + msecs_to_jiffies(1)); + } else { + pr_debug("virtio-fs: Could not queue FORGET: err=%d. Dropping it.\n", + ret); + dec_in_flight_req(fsvq); + kfree(forget); + } + spin_unlock(&fsvq->lock); return; + } + + notify = virtqueue_kick_prepare(vq); + spin_unlock(&fsvq->lock); + + if (notify) + virtqueue_notify(vq); + pr_debug("virtio-fs: worker %s dispatched one forget request.\n", + __func__); } } @@ -565,6 +463,7 @@ static void virtio_fs_request_complete(struct fuse_req *req, struct virtio_fs_vq *fsvq) { struct fuse_pqueue *fpq = &fsvq->fud->pq; + struct fuse_conn *fc = fsvq->fud->fc; struct fuse_args *args; struct fuse_args_pages *ap; unsigned int len, i, thislen; @@ -597,7 +496,7 @@ static void virtio_fs_request_complete(struct fuse_req *req, clear_bit(FR_SENT, &req->flags); spin_unlock(&fpq->lock); - fuse_request_end(req); + fuse_request_end(fc, req); spin_lock(&fsvq->lock); dec_in_flight_req(fsvq); spin_unlock(&fsvq->lock); @@ -665,26 +564,6 @@ static void virtio_fs_vq_done(struct virtqueue *vq) schedule_work(&fsvq->done_work); } -static void virtio_fs_init_vq(struct virtio_fs_vq *fsvq, char *name, - int vq_type) -{ - strncpy(fsvq->name, name, VQ_NAME_LEN); - spin_lock_init(&fsvq->lock); - INIT_LIST_HEAD(&fsvq->queued_reqs); - INIT_LIST_HEAD(&fsvq->end_reqs); - init_completion(&fsvq->in_flight_zero); - - if (vq_type == VQ_REQUEST) { - INIT_WORK(&fsvq->done_work, virtio_fs_requests_done_work); - INIT_DELAYED_WORK(&fsvq->dispatch_work, - virtio_fs_request_dispatch_work); - } else { - INIT_WORK(&fsvq->done_work, virtio_fs_hiprio_done_work); - INIT_DELAYED_WORK(&fsvq->dispatch_work, - virtio_fs_hiprio_dispatch_work); - } -} - /* Initialize virtqueues */ static int virtio_fs_setup_vqs(struct virtio_device *vdev, struct virtio_fs *fs) @@ -695,12 +574,12 @@ static int virtio_fs_setup_vqs(struct virtio_device *vdev, unsigned int i; int ret = 0; - virtio_cread_le(vdev, struct virtio_fs_config, num_request_queues, - &fs->num_request_queues); + virtio_cread(vdev, struct virtio_fs_config, num_request_queues, + &fs->num_request_queues); if (fs->num_request_queues == 0) return -EINVAL; - fs->nvqs = VQ_REQUEST + fs->num_request_queues; + fs->nvqs = 1 + fs->num_request_queues; fs->vqs = kcalloc(fs->nvqs, sizeof(fs->vqs[VQ_HIPRIO]), GFP_KERNEL); if (!fs->vqs) return -ENOMEM; @@ -714,17 +593,27 @@ static int virtio_fs_setup_vqs(struct virtio_device *vdev, goto out; } - /* Initialize the hiprio/forget request virtqueue */ callbacks[VQ_HIPRIO] = virtio_fs_vq_done; - virtio_fs_init_vq(&fs->vqs[VQ_HIPRIO], "hiprio", VQ_HIPRIO); + snprintf(fs->vqs[VQ_HIPRIO].name, sizeof(fs->vqs[VQ_HIPRIO].name), + "hiprio"); names[VQ_HIPRIO] = fs->vqs[VQ_HIPRIO].name; + INIT_WORK(&fs->vqs[VQ_HIPRIO].done_work, virtio_fs_hiprio_done_work); + INIT_LIST_HEAD(&fs->vqs[VQ_HIPRIO].queued_reqs); + INIT_LIST_HEAD(&fs->vqs[VQ_HIPRIO].end_reqs); + INIT_DELAYED_WORK(&fs->vqs[VQ_HIPRIO].dispatch_work, + virtio_fs_hiprio_dispatch_work); + spin_lock_init(&fs->vqs[VQ_HIPRIO].lock); /* Initialize the requests virtqueues */ for (i = VQ_REQUEST; i < fs->nvqs; i++) { - char vq_name[VQ_NAME_LEN]; - - snprintf(vq_name, VQ_NAME_LEN, "requests.%u", i - VQ_REQUEST); - virtio_fs_init_vq(&fs->vqs[i], vq_name, VQ_REQUEST); + spin_lock_init(&fs->vqs[i].lock); + INIT_WORK(&fs->vqs[i].done_work, virtio_fs_requests_done_work); + INIT_DELAYED_WORK(&fs->vqs[i].dispatch_work, + virtio_fs_request_dispatch_work); + INIT_LIST_HEAD(&fs->vqs[i].queued_reqs); + INIT_LIST_HEAD(&fs->vqs[i].end_reqs); + snprintf(fs->vqs[i].name, sizeof(fs->vqs[i].name), + "requests.%u", i - VQ_REQUEST); callbacks[i] = virtio_fs_vq_done; names[i] = fs->vqs[i].name; } @@ -753,130 +642,6 @@ static void virtio_fs_cleanup_vqs(struct virtio_device *vdev, vdev->config->del_vqs(vdev); } -/* Map a window offset to a page frame number. The window offset will have - * been produced by .iomap_begin(), which maps a file offset to a window - * offset. - */ -static long virtio_fs_direct_access(struct dax_device *dax_dev, pgoff_t pgoff, - long nr_pages, void **kaddr, pfn_t *pfn) -{ - struct virtio_fs *fs = dax_get_private(dax_dev); - phys_addr_t offset = PFN_PHYS(pgoff); - size_t max_nr_pages = fs->window_len/PAGE_SIZE - pgoff; - - if (kaddr) - *kaddr = fs->window_kaddr + offset; - if (pfn) - *pfn = phys_to_pfn_t(fs->window_phys_addr + offset, - PFN_DEV | PFN_MAP); - return nr_pages > max_nr_pages ? max_nr_pages : nr_pages; -} - -static size_t virtio_fs_copy_from_iter(struct dax_device *dax_dev, - pgoff_t pgoff, void *addr, - size_t bytes, struct iov_iter *i) -{ - return copy_from_iter(addr, bytes, i); -} - -static size_t virtio_fs_copy_to_iter(struct dax_device *dax_dev, - pgoff_t pgoff, void *addr, - size_t bytes, struct iov_iter *i) -{ - return copy_to_iter(addr, bytes, i); -} - -static int virtio_fs_zero_page_range(struct dax_device *dax_dev, - pgoff_t pgoff, size_t nr_pages) -{ - long rc; - void *kaddr; - - rc = dax_direct_access(dax_dev, pgoff, nr_pages, &kaddr, NULL); - if (rc < 0) - return rc; - memset(kaddr, 0, nr_pages << PAGE_SHIFT); - dax_flush(dax_dev, kaddr, nr_pages << PAGE_SHIFT); - return 0; -} - -static const struct dax_operations virtio_fs_dax_ops = { - .direct_access = virtio_fs_direct_access, - .copy_from_iter = virtio_fs_copy_from_iter, - .copy_to_iter = virtio_fs_copy_to_iter, - .zero_page_range = virtio_fs_zero_page_range, -}; - -static void virtio_fs_cleanup_dax(void *data) -{ - struct dax_device *dax_dev = data; - - kill_dax(dax_dev); - put_dax(dax_dev); -} - -static int virtio_fs_setup_dax(struct virtio_device *vdev, struct virtio_fs *fs) -{ - struct virtio_shm_region cache_reg; - struct dev_pagemap *pgmap; - bool have_cache; - - if (!IS_ENABLED(CONFIG_FUSE_DAX)) - return 0; - - /* Get cache region */ - have_cache = virtio_get_shm_region(vdev, &cache_reg, - (u8)VIRTIO_FS_SHMCAP_ID_CACHE); - if (!have_cache) { - dev_notice(&vdev->dev, "%s: No cache capability\n", __func__); - return 0; - } - - if (!devm_request_mem_region(&vdev->dev, cache_reg.addr, cache_reg.len, - dev_name(&vdev->dev))) { - dev_warn(&vdev->dev, "could not reserve region addr=0x%llx len=0x%llx\n", - cache_reg.addr, cache_reg.len); - return -EBUSY; - } - - dev_notice(&vdev->dev, "Cache len: 0x%llx @ 0x%llx\n", cache_reg.len, - cache_reg.addr); - - pgmap = devm_kzalloc(&vdev->dev, sizeof(*pgmap), GFP_KERNEL); - if (!pgmap) - return -ENOMEM; - - pgmap->type = MEMORY_DEVICE_FS_DAX; - - /* Ideally we would directly use the PCI BAR resource but - * devm_memremap_pages() wants its own copy in pgmap. So - * initialize a struct resource from scratch (only the start - * and end fields will be used). - */ - pgmap->res = (struct resource){ - .name = "virtio-fs dax window", - .start = (phys_addr_t) cache_reg.addr, - .end = (phys_addr_t) cache_reg.addr + cache_reg.len - 1, - }; - - fs->window_kaddr = devm_memremap_pages(&vdev->dev, pgmap); - if (IS_ERR(fs->window_kaddr)) - return PTR_ERR(fs->window_kaddr); - - fs->window_phys_addr = (phys_addr_t) cache_reg.addr; - fs->window_len = (phys_addr_t) cache_reg.len; - - dev_dbg(&vdev->dev, "%s: window kaddr 0x%px phys_addr 0x%llx len 0x%llx\n", - __func__, fs->window_kaddr, cache_reg.addr, cache_reg.len); - - fs->dax_dev = alloc_dax(fs, NULL, &virtio_fs_dax_ops, 0); - if (IS_ERR(fs->dax_dev)) - return PTR_ERR(fs->dax_dev); - - return devm_add_action_or_reset(&vdev->dev, virtio_fs_cleanup_dax, - fs->dax_dev); -} - static int virtio_fs_probe(struct virtio_device *vdev) { struct virtio_fs *fs; @@ -898,10 +663,6 @@ static int virtio_fs_probe(struct virtio_device *vdev) /* TODO vq affinity */ - ret = virtio_fs_setup_dax(vdev, fs); - if (ret < 0) - goto out_vqs; - /* Bring the device online in case the filesystem is mounted and * requests need to be sent before we return. */ @@ -945,7 +706,7 @@ static void virtio_fs_remove(struct virtio_device *vdev) /* This device is going away. No one should get new reference */ list_del_init(&fs->list); virtio_fs_stop_all_queues(fs); - virtio_fs_drain_all_queues_locked(fs); + virtio_fs_drain_all_queues(fs); vdev->config->reset(vdev); virtio_fs_cleanup_vqs(vdev, fs); @@ -970,12 +731,12 @@ static int virtio_fs_restore(struct virtio_device *vdev) } #endif /* CONFIG_PM_SLEEP */ -static const struct virtio_device_id id_table[] = { +const static struct virtio_device_id id_table[] = { { VIRTIO_ID_FS, VIRTIO_DEV_ANY_ID }, {}, }; -static const unsigned int feature_table[] = {}; +const static unsigned int feature_table[] = {}; static struct virtio_driver virtio_fs_driver = { .driver.name = KBUILD_MODNAME, @@ -996,10 +757,14 @@ __releases(fiq->lock) { struct fuse_forget_link *link; struct virtio_fs_forget *forget; - struct virtio_fs_forget_req *req; + struct scatterlist sg; + struct scatterlist *sgs[] = {&sg}; struct virtio_fs *fs; + struct virtqueue *vq; struct virtio_fs_vq *fsvq; + bool notify; u64 unique; + int ret; link = fuse_dequeue_forget(fiq, 1, NULL); unique = fuse_get_unique(fiq); @@ -1010,19 +775,57 @@ __releases(fiq->lock) /* Allocate a buffer for the request */ forget = kmalloc(sizeof(*forget), GFP_NOFS | __GFP_NOFAIL); - req = &forget->req; - req->ih = (struct fuse_in_header){ + forget->ih = (struct fuse_in_header){ .opcode = FUSE_FORGET, .nodeid = link->forget_one.nodeid, .unique = unique, - .len = sizeof(*req), + .len = sizeof(*forget), }; - req->arg = (struct fuse_forget_in){ + forget->arg = (struct fuse_forget_in){ .nlookup = link->forget_one.nlookup, }; - send_forget_request(fsvq, forget, false); + sg_init_one(&sg, forget, sizeof(*forget)); + + /* Enqueue the request */ + spin_lock(&fsvq->lock); + + if (!fsvq->connected) { + kfree(forget); + spin_unlock(&fsvq->lock); + goto out; + } + + vq = fsvq->vq; + dev_dbg(&vq->vdev->dev, "%s\n", __func__); + + ret = virtqueue_add_sgs(vq, sgs, 1, 0, forget, GFP_ATOMIC); + if (ret < 0) { + if (ret == -ENOMEM || ret == -ENOSPC) { + pr_debug("virtio-fs: Could not queue FORGET: err=%d. Will try later.\n", + ret); + list_add_tail(&forget->list, &fsvq->queued_reqs); + schedule_delayed_work(&fsvq->dispatch_work, + msecs_to_jiffies(1)); + inc_in_flight_req(fsvq); + } else { + pr_debug("virtio-fs: Could not queue FORGET: err=%d. Dropping it.\n", + ret); + kfree(forget); + } + spin_unlock(&fsvq->lock); + goto out; + } + + inc_in_flight_req(fsvq); + notify = virtqueue_kick_prepare(vq); + + spin_unlock(&fsvq->lock); + + if (notify) + virtqueue_notify(vq); +out: kfree(link); } @@ -1039,37 +842,18 @@ __releases(fiq->lock) spin_unlock(&fiq->lock); } -/* Count number of scatter-gather elements required */ -static unsigned int sg_count_fuse_pages(struct fuse_page_desc *page_descs, - unsigned int num_pages, - unsigned int total_len) -{ - unsigned int i; - unsigned int this_len; - - for (i = 0; i < num_pages && total_len; i++) { - this_len = min(page_descs[i].length, total_len); - total_len -= this_len; - } - - return i; -} - /* Return the number of scatter-gather list elements required */ static unsigned int sg_count_fuse_req(struct fuse_req *req) { struct fuse_args *args = req->args; struct fuse_args_pages *ap = container_of(args, typeof(*ap), args); - unsigned int size, total_sgs = 1 /* fuse_in_header */; + unsigned int total_sgs = 1 /* fuse_in_header */; if (args->in_numargs - args->in_pages) total_sgs += 1; - if (args->in_pages) { - size = args->in_args[args->in_numargs - 1].size; - total_sgs += sg_count_fuse_pages(ap->descs, ap->num_pages, - size); - } + if (args->in_pages) + total_sgs += ap->num_pages; if (!test_bit(FR_ISREPLY, &req->flags)) return total_sgs; @@ -1079,11 +863,8 @@ static unsigned int sg_count_fuse_req(struct fuse_req *req) if (args->out_numargs - args->out_pages) total_sgs += 1; - if (args->out_pages) { - size = args->out_args[args->out_numargs - 1].size; - total_sgs += sg_count_fuse_pages(ap->descs, ap->num_pages, - size); - } + if (args->out_pages) + total_sgs += ap->num_pages; return total_sgs; } @@ -1292,35 +1073,31 @@ __releases(fiq->lock) } } -static const struct fuse_iqueue_ops virtio_fs_fiq_ops = { +const static struct fuse_iqueue_ops virtio_fs_fiq_ops = { .wake_forget_and_unlock = virtio_fs_wake_forget_and_unlock, .wake_interrupt_and_unlock = virtio_fs_wake_interrupt_and_unlock, .wake_pending_and_unlock = virtio_fs_wake_pending_and_unlock, .release = virtio_fs_fiq_release, }; -static inline void virtio_fs_ctx_set_defaults(struct fuse_fs_context *ctx) +static int virtio_fs_fill_super(struct super_block *sb) { - ctx->rootmode = S_IFDIR; - ctx->default_permissions = 1; - ctx->allow_other = 1; - ctx->max_read = UINT_MAX; - ctx->blksize = 512; - ctx->destroy = true; - ctx->no_control = true; - ctx->no_force_umount = true; -} - -static int virtio_fs_fill_super(struct super_block *sb, struct fs_context *fsc) -{ - struct fuse_mount *fm = get_fuse_mount_super(sb); - struct fuse_conn *fc = fm->fc; + struct fuse_conn *fc = get_fuse_conn_super(sb); struct virtio_fs *fs = fc->iq.priv; - struct fuse_fs_context *ctx = fsc->fs_private; unsigned int i; int err; + struct fuse_fs_context ctx = { + .rootmode = S_IFDIR, + .default_permissions = 1, + .allow_other = 1, + .max_read = UINT_MAX, + .blksize = 512, + .destroy = true, + .no_control = true, + .no_force_umount = true, + .no_mount_options = true, + }; - virtio_fs_ctx_set_defaults(ctx); mutex_lock(&virtio_fs_mutex); /* After holding mutex, make sure virtiofs device is still there. @@ -1335,7 +1112,7 @@ static int virtio_fs_fill_super(struct super_block *sb, struct fs_context *fsc) err = -ENOMEM; /* Allocate fuse_dev for hiprio and notification queues */ - for (i = 0; i < fs->nvqs; i++) { + for (i = 0; i < VQ_REQUEST; i++) { struct virtio_fs_vq *fsvq = &fs->vqs[i]; fsvq->fud = fuse_dev_alloc(); @@ -1343,30 +1120,24 @@ static int virtio_fs_fill_super(struct super_block *sb, struct fs_context *fsc) goto err_free_fuse_devs; } - /* virtiofs allocates and installs its own fuse devices */ - ctx->fudptr = NULL; - if (ctx->dax) { - if (!fs->dax_dev) { - err = -EINVAL; - pr_err("virtio-fs: dax can't be enabled as filesystem" - " device does not support it.\n"); - goto err_free_fuse_devs; - } - ctx->dax_dev = fs->dax_dev; - } - err = fuse_fill_super_common(sb, ctx); + ctx.fudptr = (void **)&fs->vqs[VQ_REQUEST].fud; + err = fuse_fill_super_common(sb, &ctx); if (err < 0) goto err_free_fuse_devs; + fc = fs->vqs[VQ_REQUEST].fud->fc; + for (i = 0; i < fs->nvqs; i++) { struct virtio_fs_vq *fsvq = &fs->vqs[i]; + if (i == VQ_REQUEST) + continue; /* already initialized */ fuse_dev_install(fsvq->fud, fc); } /* Previous unmount will stop all queues. Start these again */ virtio_fs_start_all_queues(fs); - fuse_send_init(fm); + fuse_send_init(fc); mutex_unlock(&virtio_fs_mutex); return 0; @@ -1377,17 +1148,18 @@ err: return err; } -static void virtio_fs_conn_destroy(struct fuse_mount *fm) +static void virtio_kill_sb(struct super_block *sb) { - struct fuse_conn *fc = fm->fc; - struct virtio_fs *vfs = fc->iq.priv; - struct virtio_fs_vq *fsvq = &vfs->vqs[VQ_HIPRIO]; + struct fuse_conn *fc = get_fuse_conn_super(sb); + struct virtio_fs *vfs; + struct virtio_fs_vq *fsvq; - /* Stop dax worker. Soon evict_inodes() will be called which - * will free all memory ranges belonging to all inodes. - */ - if (IS_ENABLED(CONFIG_FUSE_DAX)) - fuse_dax_cancel_work(fc); + /* If mount failed, we can still be called without any fc */ + if (!fc) + return fuse_kill_sb_anon(sb); + + vfs = fc->iq.priv; + fsvq = &vfs->vqs[VQ_HIPRIO]; /* Stop forget queue. Soon destroy will be sent */ spin_lock(&fsvq->lock); @@ -1395,9 +1167,9 @@ static void virtio_fs_conn_destroy(struct fuse_mount *fm) spin_unlock(&fsvq->lock); virtio_fs_drain_all_queues(vfs); - fuse_conn_destroy(fm); + fuse_kill_sb_anon(sb); - /* fuse_conn_destroy() must have sent destroy. Stop all queues + /* fuse_kill_sb_anon() must have sent destroy. Stop all queues * and drain one more time and free fuse devices. Freeing fuse * devices will drop their reference on fuse_conn and that in * turn will drop its reference on virtio_fs object. @@ -1407,27 +1179,12 @@ static void virtio_fs_conn_destroy(struct fuse_mount *fm) virtio_fs_free_devs(vfs); } -static void virtio_kill_sb(struct super_block *sb) -{ - struct fuse_mount *fm = get_fuse_mount_super(sb); - bool last; - - /* If mount failed, we can still be called without any fc */ - if (sb->s_root) { - last = fuse_mount_remove(fm); - if (last) - virtio_fs_conn_destroy(fm); - } - kill_anon_super(sb); -} - static int virtio_fs_test_super(struct super_block *sb, struct fs_context *fsc) { - struct fuse_mount *fsc_fm = fsc->s_fs_info; - struct fuse_mount *sb_fm = get_fuse_mount_super(sb); + struct fuse_conn *fc = fsc->s_fs_info; - return fsc_fm->fc->iq.priv == sb_fm->fc->iq.priv; + return fc->iq.priv == get_fuse_conn_super(sb)->iq.priv; } static int virtio_fs_set_super(struct super_block *sb, @@ -1437,7 +1194,7 @@ static int virtio_fs_set_super(struct super_block *sb, err = get_anon_bdev(&sb->s_dev); if (!err) - fuse_mount_get(fsc->s_fs_info); + fuse_conn_get(fsc->s_fs_info); return err; } @@ -1446,10 +1203,8 @@ static int virtio_fs_get_tree(struct fs_context *fsc) { struct virtio_fs *fs; struct super_block *sb; - struct fuse_conn *fc = NULL; - struct fuse_mount *fm; - unsigned int virtqueue_size; - int err = -EIO; + struct fuse_conn *fc; + int err; if (!fsc->source) return invalf(fsc, "No source specified"); @@ -1464,39 +1219,28 @@ static int virtio_fs_get_tree(struct fs_context *fsc) return -EINVAL; } - virtqueue_size = virtqueue_get_vring_size(fs->vqs[VQ_REQUEST].vq); - if (WARN_ON(virtqueue_size <= FUSE_HEADER_OVERHEAD)) - goto out_err; - - err = -ENOMEM; fc = kzalloc(sizeof(struct fuse_conn), GFP_KERNEL); - if (!fc) - goto out_err; + if (!fc) { + mutex_lock(&virtio_fs_mutex); + virtio_fs_put(fs); + mutex_unlock(&virtio_fs_mutex); + return -ENOMEM; + } - fm = kzalloc(sizeof(struct fuse_mount), GFP_KERNEL); - if (!fm) - goto out_err; - - fuse_conn_init(fc, fm, fsc->user_ns, &virtio_fs_fiq_ops, fs); + fuse_conn_init(fc, get_user_ns(current_user_ns()), &virtio_fs_fiq_ops, + fs); fc->release = fuse_free_conn; fc->delete_stale = true; - fc->auto_submounts = true; - /* Tell FUSE to split requests that exceed the virtqueue's size */ - fc->max_pages_limit = min_t(unsigned int, fc->max_pages_limit, - virtqueue_size - FUSE_HEADER_OVERHEAD); - - fsc->s_fs_info = fm; + fsc->s_fs_info = fc; sb = sget_fc(fsc, virtio_fs_test_super, virtio_fs_set_super); - fuse_mount_put(fm); + fuse_conn_put(fc); if (IS_ERR(sb)) return PTR_ERR(sb); if (!sb->s_root) { - err = virtio_fs_fill_super(sb, fsc); + err = virtio_fs_fill_super(sb); if (err) { - fuse_mount_put(fm); - sb->s_fs_info = NULL; deactivate_locked_super(sb); return err; } @@ -1507,29 +1251,14 @@ static int virtio_fs_get_tree(struct fs_context *fsc) WARN_ON(fsc->root); fsc->root = dget(sb->s_root); return 0; - -out_err: - kfree(fc); - mutex_lock(&virtio_fs_mutex); - virtio_fs_put(fs); - mutex_unlock(&virtio_fs_mutex); - return err; } static const struct fs_context_operations virtio_fs_context_ops = { - .free = virtio_fs_free_fsc, - .parse_param = virtio_fs_parse_param, .get_tree = virtio_fs_get_tree, }; static int virtio_fs_init_fs_context(struct fs_context *fsc) { - struct fuse_fs_context *ctx; - - ctx = kzalloc(sizeof(struct fuse_fs_context), GFP_KERNEL); - if (!ctx) - return -ENOMEM; - fsc->fs_private = ctx; fsc->ops = &virtio_fs_context_ops; return 0; } diff --git a/fs/fuse/xattr.c b/fs/fuse/xattr.c index 3abdf0e2be89..9d3f28b1f6f8 100644 --- a/fs/fuse/xattr.c +++ b/fs/fuse/xattr.c @@ -14,12 +14,12 @@ int fuse_setxattr(struct inode *inode, const char *name, const void *value, size_t size, int flags) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_setxattr_in inarg; int err; - if (fm->fc->no_setxattr) + if (fc->no_setxattr) return -EOPNOTSUPP; memset(&inarg, 0, sizeof(inarg)); @@ -34,9 +34,9 @@ int fuse_setxattr(struct inode *inode, const char *name, const void *value, args.in_args[1].value = name; args.in_args[2].size = size; args.in_args[2].value = value; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) { - fm->fc->no_setxattr = 1; + fc->no_setxattr = 1; err = -EOPNOTSUPP; } if (!err) { @@ -49,13 +49,13 @@ int fuse_setxattr(struct inode *inode, const char *name, const void *value, ssize_t fuse_getxattr(struct inode *inode, const char *name, void *value, size_t size) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_getxattr_in inarg; struct fuse_getxattr_out outarg; ssize_t ret; - if (fm->fc->no_getxattr) + if (fc->no_getxattr) return -EOPNOTSUPP; memset(&inarg, 0, sizeof(inarg)); @@ -77,11 +77,11 @@ ssize_t fuse_getxattr(struct inode *inode, const char *name, void *value, args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; } - ret = fuse_simple_request(fm, &args); + ret = fuse_simple_request(fc, &args); if (!ret && !size) ret = min_t(size_t, outarg.size, XATTR_SIZE_MAX); if (ret == -ENOSYS) { - fm->fc->no_getxattr = 1; + fc->no_getxattr = 1; ret = -EOPNOTSUPP; } return ret; @@ -107,30 +107,19 @@ static int fuse_verify_xattr_list(char *list, size_t size) ssize_t fuse_listxattr(struct dentry *entry, char *list, size_t size) { struct inode *inode = d_inode(entry); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_getxattr_in inarg; struct fuse_getxattr_out outarg; ssize_t ret; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_getxattr_io, - fuse_listxattr_initialize, - fuse_listxattr_backing, fuse_listxattr_finalize, - entry, list, size); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fuse_is_bad(inode)) return -EIO; - if (!fuse_allow_current_process(fm->fc)) + if (!fuse_allow_current_process(fc)) return -EACCES; - if (fm->fc->no_listxattr) + if (fc->no_listxattr) return -EOPNOTSUPP; memset(&inarg, 0, sizeof(inarg)); @@ -150,13 +139,13 @@ ssize_t fuse_listxattr(struct dentry *entry, char *list, size_t size) args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; } - ret = fuse_simple_request(fm, &args); + ret = fuse_simple_request(fc, &args); if (!ret && !size) ret = min_t(size_t, outarg.size, XATTR_LIST_MAX); if (ret > 0 && size) ret = fuse_verify_xattr_list(list, ret); if (ret == -ENOSYS) { - fm->fc->no_listxattr = 1; + fc->no_listxattr = 1; ret = -EOPNOTSUPP; } return ret; @@ -164,11 +153,11 @@ ssize_t fuse_listxattr(struct dentry *entry, char *list, size_t size) int fuse_removexattr(struct inode *inode, const char *name) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); int err; - if (fm->fc->no_removexattr) + if (fc->no_removexattr) return -EOPNOTSUPP; args.opcode = FUSE_REMOVEXATTR; @@ -176,9 +165,9 @@ int fuse_removexattr(struct inode *inode, const char *name) args.in_numargs = 1; args.in_args[0].size = strlen(name) + 1; args.in_args[0].value = name; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) { - fm->fc->no_removexattr = 1; + fc->no_removexattr = 1; err = -EOPNOTSUPP; } if (!err) { @@ -192,17 +181,6 @@ static int fuse_xattr_get(const struct xattr_handler *handler, struct dentry *dentry, struct inode *inode, const char *name, void *value, size_t size, int flags) { -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_getxattr_io, - fuse_getxattr_initialize, fuse_getxattr_backing, - fuse_getxattr_finalize, - dentry, name, value, size); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fuse_is_bad(inode)) return -EIO; @@ -214,24 +192,6 @@ static int fuse_xattr_set(const struct xattr_handler *handler, const char *name, const void *value, size_t size, int flags) { -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - if (value) - fer = fuse_bpf_backing(inode, struct fuse_setxattr_in, - fuse_setxattr_initialize, fuse_setxattr_backing, - fuse_setxattr_finalize, dentry, name, value, - size, flags); - else - fer = fuse_bpf_backing(inode, struct fuse_dummy_io, - fuse_removexattr_initialize, - fuse_removexattr_backing, - fuse_removexattr_finalize, - dentry, name); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fuse_is_bad(inode)) return -EIO; diff --git a/fs/namespace.c b/fs/namespace.c index 176bccdf6f30..2fd0bf91aa77 100644 --- a/fs/namespace.c +++ b/fs/namespace.c @@ -2618,7 +2618,6 @@ static int do_remount(struct path *path, int ms_flags, int sb_flags, if (IS_ERR(fc)) return PTR_ERR(fc); - fc->oldapi = true; err = parse_monolithic_mount_data(fc, data); if (!err) { down_write(&sb->s_umount); diff --git a/fs/nfs/inode.c b/fs/nfs/inode.c index a4605b17f047..4f0d2fc810e4 100644 --- a/fs/nfs/inode.c +++ b/fs/nfs/inode.c @@ -310,7 +310,7 @@ nfs_find_actor(struct inode *inode, void *opaque) if (NFS_FILEID(inode) != fattr->fileid) return 0; - if (inode_wrong_type(inode, fattr->mode)) + if ((S_IFMT & inode->i_mode) != (S_IFMT & fattr->mode)) return 0; if (nfs_compare_fh(NFS_FH(inode), fh)) return 0; @@ -1418,7 +1418,7 @@ static int nfs_check_inode_attributes(struct inode *inode, struct nfs_fattr *fat return 0; return -ESTALE; } - if ((fattr->valid & NFS_ATTR_FATTR_TYPE) && inode_wrong_type(inode, fattr->mode)) + if ((fattr->valid & NFS_ATTR_FATTR_TYPE) && (inode->i_mode & S_IFMT) != (fattr->mode & S_IFMT)) return -ESTALE; @@ -1834,7 +1834,7 @@ static int nfs_update_inode(struct inode *inode, struct nfs_fattr *fattr) /* * Make sure the inode's type hasn't changed. */ - if ((fattr->valid & NFS_ATTR_FATTR_TYPE) && inode_wrong_type(inode, fattr->mode)) { + if ((fattr->valid & NFS_ATTR_FATTR_TYPE) && (inode->i_mode & S_IFMT) != (fattr->mode & S_IFMT)) { /* * Big trouble! The inode has become a different object. */ diff --git a/fs/nfsd/nfsproc.c b/fs/nfsd/nfsproc.c index 5f6186b2ca9b..4aca93e11af7 100644 --- a/fs/nfsd/nfsproc.c +++ b/fs/nfsd/nfsproc.c @@ -376,7 +376,7 @@ nfsd_proc_create(struct svc_rqst *rqstp) /* Make sure the type and device matches */ nfserr = nfserr_exist; - if (inode && inode_wrong_type(inode, type)) + if (inode && type != (inode->i_mode & S_IFMT)) goto out_unlock; } diff --git a/fs/notify/fanotify/fanotify_user.c b/fs/notify/fanotify/fanotify_user.c index e774f7851bc0..ec4eadf459ae 100644 --- a/fs/notify/fanotify/fanotify_user.c +++ b/fs/notify/fanotify/fanotify_user.c @@ -523,7 +523,7 @@ static const struct file_operations fanotify_fops = { .fasync = NULL, .release = fanotify_release, .unlocked_ioctl = fanotify_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = fanotify_ioctl, .llseek = noop_llseek, }; diff --git a/fs/overlayfs/namei.c b/fs/overlayfs/namei.c index f7f259614143..bcfb0b11b819 100644 --- a/fs/overlayfs/namei.c +++ b/fs/overlayfs/namei.c @@ -345,7 +345,7 @@ int ovl_check_origin_fh(struct ovl_fs *ofs, struct ovl_fh *fh, bool connected, return PTR_ERR(origin); if (upperdentry && !ovl_is_whiteout(upperdentry) && - inode_wrong_type(d_inode(upperdentry), d_inode(origin)->i_mode)) + ((d_inode(origin)->i_mode ^ d_inode(upperdentry)->i_mode) & S_IFMT)) goto invalid; if (!*stackp) @@ -717,7 +717,7 @@ struct dentry *ovl_lookup_index(struct ovl_fs *ofs, struct dentry *upper, index = ERR_PTR(-ESTALE); goto out; } else if (ovl_dentry_weird(index) || ovl_is_whiteout(index) || - inode_wrong_type(inode, d_inode(origin)->i_mode)) { + ((inode->i_mode ^ d_inode(origin)->i_mode) & S_IFMT)) { /* * Index should always be of the same file type as origin * except for the case of a whiteout index. A whiteout diff --git a/fs/proc/array.c b/fs/proc/array.c index be8a186d21ad..46dcb6f0eccf 100644 --- a/fs/proc/array.c +++ b/fs/proc/array.c @@ -342,10 +342,6 @@ static inline void task_seccomp(struct seq_file *m, struct task_struct *p) seq_put_decimal_ull(m, "NoNewPrivs:\t", task_no_new_privs(p)); #ifdef CONFIG_SECCOMP seq_put_decimal_ull(m, "\nSeccomp:\t", p->seccomp.mode); -#ifdef CONFIG_SECCOMP_FILTER - seq_put_decimal_ull(m, "\nSeccomp_filters:\t", - atomic_read(&p->seccomp.filter_count)); -#endif #endif seq_puts(m, "\nSpeculation_Store_Bypass:\t"); switch (arch_prctl_spec_ctrl_get(p, PR_SPEC_STORE_BYPASS)) { diff --git a/fs/proc/base.c b/fs/proc/base.c index 791ade1d1019..6cac23a218a5 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -2211,16 +2211,16 @@ struct map_files_info { }; /* - * Only allow CAP_SYS_ADMIN and CAP_CHECKPOINT_RESTORE to follow the links, due - * to concerns about how the symlinks may be used to bypass permissions on - * ancestor directories in the path to the file in question. + * Only allow CAP_SYS_ADMIN to follow the links, due to concerns about how the + * symlinks may be used to bypass permissions on ancestor directories in the + * path to the file in question. */ static const char * proc_map_files_get_link(struct dentry *dentry, struct inode *inode, struct delayed_call *done) { - if (!checkpoint_restore_ns_capable(&init_user_ns)) + if (!capable(CAP_SYS_ADMIN)) return ERR_PTR(-EPERM); return proc_pid_get_link(dentry, inode, done); @@ -3330,7 +3330,7 @@ static const struct pid_entry tgid_base_stuff[] = { DIR("task", S_IRUGO|S_IXUGO, proc_task_inode_operations, proc_task_operations), DIR("fd", S_IRUSR|S_IXUSR, proc_fd_inode_operations, proc_fd_operations), DIR("map_files", S_IRUSR|S_IXUSR, proc_map_files_inode_operations, proc_map_files_operations), - DIR("fdinfo", S_IRUGO|S_IXUGO, proc_fdinfo_inode_operations, proc_fdinfo_operations), + DIR("fdinfo", S_IRUSR|S_IXUSR, proc_fdinfo_inode_operations, proc_fdinfo_operations), DIR("ns", S_IRUSR|S_IXUGO, proc_ns_dir_inode_operations, proc_ns_dir_operations), #ifdef CONFIG_NET DIR("net", S_IRUGO|S_IXUGO, proc_net_inode_operations, proc_net_operations), @@ -3750,7 +3750,7 @@ static const struct inode_operations proc_tid_comm_inode_operations = { */ static const struct pid_entry tid_base_stuff[] = { DIR("fd", S_IRUSR|S_IXUSR, proc_fd_inode_operations, proc_fd_operations), - DIR("fdinfo", S_IRUGO|S_IXUGO, proc_fdinfo_inode_operations, proc_fdinfo_operations), + DIR("fdinfo", S_IRUSR|S_IXUSR, proc_fdinfo_inode_operations, proc_fdinfo_operations), DIR("ns", S_IRUSR|S_IXUGO, proc_ns_dir_inode_operations, proc_ns_dir_operations), #ifdef CONFIG_NET DIR("net", S_IRUGO|S_IXUGO, proc_net_inode_operations, proc_net_operations), diff --git a/fs/proc/fd.c b/fs/proc/fd.c index 6b634c0a9b6e..81882a13212d 100644 --- a/fs/proc/fd.c +++ b/fs/proc/fd.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -54,10 +53,9 @@ static int seq_show(struct seq_file *m, void *v) if (ret) return ret; - seq_printf(m, "pos:\t%lli\nflags:\t0%o\nmnt_id:\t%i\nino:\t%lu\n", + seq_printf(m, "pos:\t%lli\nflags:\t0%o\nmnt_id:\t%i\n", (long long)file->f_pos, f_flags, - real_mount(file->f_path.mnt)->mnt_id, - file_inode(file)->i_ino); + real_mount(file->f_path.mnt)->mnt_id); show_fd_locks(m, file, files); if (seq_has_overflowed(m)) @@ -71,30 +69,8 @@ out: return 0; } -static int proc_fdinfo_access_allowed(struct inode *inode) -{ - bool allowed = false; - struct task_struct *task = get_proc_task(inode); - - if (!task) - return -ESRCH; - - allowed = ptrace_may_access(task, PTRACE_MODE_READ_FSCREDS); - put_task_struct(task); - - if (!allowed) - return -EACCES; - - return 0; -} - static int seq_fdinfo_open(struct inode *inode, struct file *file) { - int ret = proc_fdinfo_access_allowed(inode); - - if (ret) - return ret; - return single_open(file, seq_show, inode); } @@ -349,7 +325,7 @@ static struct dentry *proc_fdinfo_instantiate(struct dentry *dentry, struct proc_inode *ei; struct inode *inode; - inode = proc_pid_make_inode(dentry->d_sb, task, S_IFREG | S_IRUGO); + inode = proc_pid_make_inode(dentry->d_sb, task, S_IFREG | S_IRUSR); if (!inode) return ERR_PTR(-ENOENT); @@ -375,23 +351,12 @@ static int proc_readfdinfo(struct file *file, struct dir_context *ctx) proc_fdinfo_instantiate); } -static int proc_open_fdinfo(struct inode *inode, struct file *file) -{ - int ret = proc_fdinfo_access_allowed(inode); - - if (ret) - return ret; - - return 0; -} - const struct inode_operations proc_fdinfo_inode_operations = { .lookup = proc_lookupfdinfo, .setattr = proc_setattr, }; const struct file_operations proc_fdinfo_operations = { - .open = proc_open_fdinfo, .read = generic_read_dir, .iterate_shared = proc_readfdinfo, .llseek = generic_file_llseek, diff --git a/fs/proc/proc_sysctl.c b/fs/proc/proc_sysctl.c index 7bcbf2b84055..145abe711fd5 100644 --- a/fs/proc/proc_sysctl.c +++ b/fs/proc/proc_sysctl.c @@ -604,7 +604,7 @@ static ssize_t proc_sys_call_handler(struct kiocb *iocb, struct iov_iter *iter, error = -ENOMEM; if (count >= KMALLOC_MAX_SIZE) goto out; - kbuf = kvzalloc(count + 1, GFP_KERNEL); + kbuf = kzalloc(count + 1, GFP_KERNEL); if (!kbuf) goto out; @@ -633,7 +633,7 @@ static ssize_t proc_sys_call_handler(struct kiocb *iocb, struct iov_iter *iter, error = count; out_free_buf: - kvfree(kbuf); + kfree(kbuf); out: sysctl_head_finish(head); diff --git a/fs/read_write.c b/fs/read_write.c index 301c4a4ba1d0..93d06b4c5f78 100644 --- a/fs/read_write.c +++ b/fs/read_write.c @@ -939,34 +939,6 @@ out: return ret; } -ssize_t vfs_iocb_iter_read(struct file *file, struct kiocb *iocb, - struct iov_iter *iter) -{ - size_t tot_len; - ssize_t ret = 0; - - if (!file->f_op->read_iter) - return -EINVAL; - if (!(file->f_mode & FMODE_READ)) - return -EBADF; - if (!(file->f_mode & FMODE_CAN_READ)) - return -EINVAL; - - tot_len = iov_iter_count(iter); - if (!tot_len) - goto out; - ret = rw_verify_area(READ, file, &iocb->ki_pos, tot_len); - if (ret < 0) - return ret; - - ret = call_read_iter(file, iocb, iter); -out: - if (ret >= 0) - fsnotify_access(file); - return ret; -} -EXPORT_SYMBOL(vfs_iocb_iter_read); - ssize_t vfs_iter_read(struct file *file, struct iov_iter *iter, loff_t *ppos, rwf_t flags) { @@ -1003,34 +975,6 @@ static ssize_t do_iter_write(struct file *file, struct iov_iter *iter, return ret; } -ssize_t vfs_iocb_iter_write(struct file *file, struct kiocb *iocb, - struct iov_iter *iter) -{ - size_t tot_len; - ssize_t ret = 0; - - if (!file->f_op->write_iter) - return -EINVAL; - if (!(file->f_mode & FMODE_WRITE)) - return -EBADF; - if (!(file->f_mode & FMODE_CAN_WRITE)) - return -EINVAL; - - tot_len = iov_iter_count(iter); - if (!tot_len) - return 0; - ret = rw_verify_area(WRITE, file, &iocb->ki_pos, tot_len); - if (ret < 0) - return ret; - - ret = call_write_iter(file, iocb, iter); - if (ret > 0) - fsnotify_modify(file); - - return ret; -} -EXPORT_SYMBOL(vfs_iocb_iter_write); - ssize_t vfs_iter_write(struct file *file, struct iov_iter *iter, loff_t *ppos, rwf_t flags) { diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index d67fd6a875bd..0b114f685be1 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -2189,8 +2189,6 @@ static int ubifs_fill_super(struct super_block *sb, void *data, int silent) c->vi.vol_id); if (err) goto out_close; - sb->s_bdi->ra_pages = 0; - sb->s_bdi->io_pages = 0; sb->s_fs_info = c; sb->s_magic = UBIFS_SUPER_MAGIC; diff --git a/fs/userfaultfd.c b/fs/userfaultfd.c index 69321d466379..de1203b48bb9 100644 --- a/fs/userfaultfd.c +++ b/fs/userfaultfd.c @@ -2017,7 +2017,7 @@ static const struct file_operations userfaultfd_fops = { .poll = userfaultfd_poll, .read = userfaultfd_read, .unlocked_ioctl = userfaultfd_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = userfaultfd_ioctl, .llseek = noop_llseek, }; diff --git a/include/asm-generic/seccomp.h b/include/asm-generic/seccomp.h index 6b6f42bc58f9..1321ac7821d7 100644 --- a/include/asm-generic/seccomp.h +++ b/include/asm-generic/seccomp.h @@ -33,7 +33,7 @@ static inline const int *get_compat_mode1_syscalls(void) static const int mode1_syscalls_32[] = { __NR_seccomp_read_32, __NR_seccomp_write_32, __NR_seccomp_exit_32, __NR_seccomp_sigreturn_32, - -1, /* negative terminated */ + 0, /* null terminated */ }; return mode1_syscalls_32; } diff --git a/include/linux/bpf.h b/include/linux/bpf.h index ed1d4cb6a99b..4bd9cd99cc06 100644 --- a/include/linux/bpf.h +++ b/include/linux/bpf.h @@ -21,7 +21,6 @@ #include #include #include -#include struct bpf_verifier_env; struct bpf_verifier_log; @@ -133,9 +132,6 @@ struct bpf_map_ops { /* bpf_iter info used to open a seq_file */ const struct bpf_iter_seq_info *iter_seq_info; - - ANDROID_KABI_RESERVE(1); - ANDROID_KABI_RESERVE(2); }; struct bpf_map_memory { @@ -222,8 +218,6 @@ struct bpf_map_dev_ops { int (*map_update_elem)(struct bpf_offloaded_map *map, void *key, void *value, u64 flags); int (*map_delete_elem)(struct bpf_offloaded_map *map, void *key); - - ANDROID_KABI_RESERVE(1); }; struct bpf_offloaded_map { @@ -465,7 +459,6 @@ struct bpf_verifier_ops { const struct btf_type *t, int off, int size, enum bpf_access_type atype, u32 *next_btf_id); - ANDROID_KABI_RESERVE(1); }; struct bpf_prog_offload_ops { @@ -481,7 +474,6 @@ struct bpf_prog_offload_ops { int (*prepare)(struct bpf_prog *prog); int (*translate)(struct bpf_prog *prog); void (*destroy)(struct bpf_prog *prog); - ANDROID_KABI_RESERVE(1); }; struct bpf_prog_offload { @@ -863,7 +855,6 @@ struct bpf_prog_aux { struct work_struct work; struct rcu_head rcu; }; - ANDROID_KABI_RESERVE(1); }; struct bpf_array_aux { @@ -1783,7 +1774,7 @@ static inline void bpf_map_offload_map_free(struct bpf_map *map) } #endif /* CONFIG_NET && CONFIG_BPF_SYSCALL */ -#if defined(CONFIG_INET) && defined(CONFIG_BPF_SYSCALL) +#if defined(CONFIG_BPF_STREAM_PARSER) int sock_map_prog_update(struct bpf_map *map, struct bpf_prog *prog, struct bpf_prog *old, u32 which); int sock_map_get_from_fd(const union bpf_attr *attr, struct bpf_prog *prog); @@ -1792,18 +1783,7 @@ int sock_map_update_elem_sys(struct bpf_map *map, void *key, void *value, u64 fl void sock_map_unhash(struct sock *sk); void sock_map_destroy(struct sock *sk); void sock_map_close(struct sock *sk, long timeout); - -void bpf_sk_reuseport_detach(struct sock *sk); -int bpf_fd_reuseport_array_lookup_elem(struct bpf_map *map, void *key, - void *value); -int bpf_fd_reuseport_array_update_elem(struct bpf_map *map, void *key, - void *value, u64 map_flags); #else -static inline void bpf_sk_reuseport_detach(struct sock *sk) -{ -} - -#ifdef CONFIG_BPF_SYSCALL static inline int sock_map_prog_update(struct bpf_map *map, struct bpf_prog *prog, struct bpf_prog *old, u32 which) @@ -1828,7 +1808,20 @@ static inline int sock_map_update_elem_sys(struct bpf_map *map, void *key, void { return -EOPNOTSUPP; } +#endif /* CONFIG_BPF_STREAM_PARSER */ +#if defined(CONFIG_INET) && defined(CONFIG_BPF_SYSCALL) +void bpf_sk_reuseport_detach(struct sock *sk); +int bpf_fd_reuseport_array_lookup_elem(struct bpf_map *map, void *key, + void *value); +int bpf_fd_reuseport_array_update_elem(struct bpf_map *map, void *key, + void *value, u64 map_flags); +#else +static inline void bpf_sk_reuseport_detach(struct sock *sk) +{ +} + +#ifdef CONFIG_BPF_SYSCALL static inline int bpf_fd_reuseport_array_lookup_elem(struct bpf_map *map, void *key, void *value) { diff --git a/include/linux/bpf_types.h b/include/linux/bpf_types.h index 2d8b63574aa8..a8137bb6dd3c 100644 --- a/include/linux/bpf_types.h +++ b/include/linux/bpf_types.h @@ -77,9 +77,6 @@ BPF_PROG_TYPE(BPF_PROG_TYPE_LSM, lsm, void *, void *) #endif /* CONFIG_BPF_LSM */ #endif -#ifdef CONFIG_FUSE_BPF -BPF_PROG_TYPE(BPF_PROG_TYPE_FUSE, fuse, struct fuse_bpf_args, struct fuse_bpf_args) -#endif BPF_MAP_TYPE(BPF_MAP_TYPE_ARRAY, array_map_ops) BPF_MAP_TYPE(BPF_MAP_TYPE_PERCPU_ARRAY, percpu_array_map_ops) @@ -106,6 +103,10 @@ BPF_MAP_TYPE(BPF_MAP_TYPE_HASH_OF_MAPS, htab_of_maps_map_ops) BPF_MAP_TYPE(BPF_MAP_TYPE_DEVMAP, dev_map_ops) BPF_MAP_TYPE(BPF_MAP_TYPE_DEVMAP_HASH, dev_map_hash_ops) BPF_MAP_TYPE(BPF_MAP_TYPE_SK_STORAGE, sk_storage_map_ops) +#if defined(CONFIG_BPF_STREAM_PARSER) +BPF_MAP_TYPE(BPF_MAP_TYPE_SOCKMAP, sock_map_ops) +BPF_MAP_TYPE(BPF_MAP_TYPE_SOCKHASH, sock_hash_ops) +#endif #ifdef CONFIG_BPF_LSM BPF_MAP_TYPE(BPF_MAP_TYPE_INODE_STORAGE, inode_storage_map_ops) #endif @@ -114,8 +115,6 @@ BPF_MAP_TYPE(BPF_MAP_TYPE_CPUMAP, cpu_map_ops) BPF_MAP_TYPE(BPF_MAP_TYPE_XSKMAP, xsk_map_ops) #endif #ifdef CONFIG_INET -BPF_MAP_TYPE(BPF_MAP_TYPE_SOCKMAP, sock_map_ops) -BPF_MAP_TYPE(BPF_MAP_TYPE_SOCKHASH, sock_hash_ops) BPF_MAP_TYPE(BPF_MAP_TYPE_REUSEPORT_SOCKARRAY, reuseport_array_ops) #endif #endif diff --git a/include/linux/bpf_verifier.h b/include/linux/bpf_verifier.h index f09a5bbc9b8b..00e134d3a896 100644 --- a/include/linux/bpf_verifier.h +++ b/include/linux/bpf_verifier.h @@ -7,7 +7,6 @@ #include /* for enum bpf_reg_type */ #include /* for MAX_BPF_STACK */ #include -#include /* Maximum variable offset umax_value permitted when resolving memory accesses. * In practice this is far bigger than any realistic pointer offset; this limit @@ -348,7 +347,7 @@ struct bpf_insn_aux_data { }; u64 map_key_state; /* constant (32 bit) key tracking for maps */ int ctx_field_size; /* the ctx field size for load insn, maybe 0 */ - u32 seen; /* this insn was processed by the verifier at env->pass_cnt */ + u32 seen; /* this insn was processed by the verifier */ bool sanitize_stack_spill; /* subject to Spectre v4 sanitation */ bool zext_dst; /* this insn zero extends dst reg */ u8 alu_state; /* used in combination with alu_limit */ @@ -406,8 +405,6 @@ struct bpf_subprog_info { bool has_tail_call; bool tail_call_reachable; bool has_ld_abs; - - ANDROID_KABI_RESERVE(1); }; /* single container for all structs @@ -465,9 +462,6 @@ struct bpf_verifier_env { u32 peak_states; /* longest register parentage chain walked for liveness marking */ u32 longest_mark_read_walk; - - ANDROID_KABI_RESERVE(1); - ANDROID_KABI_RESERVE(2); }; __printf(2, 0) void bpf_verifier_vlog(struct bpf_verifier_log *log, diff --git a/include/linux/bpfilter.h b/include/linux/bpfilter.h index 2ae3c8e1d83c..ec9972d822e0 100644 --- a/include/linux/bpfilter.h +++ b/include/linux/bpfilter.h @@ -4,22 +4,21 @@ #include #include -#include struct sock; -int bpfilter_ip_set_sockopt(struct sock *sk, int optname, sockptr_t optval, +int bpfilter_ip_set_sockopt(struct sock *sk, int optname, char __user *optval, unsigned int optlen); int bpfilter_ip_get_sockopt(struct sock *sk, int optname, char __user *optval, int __user *optlen); -void bpfilter_umh_cleanup(struct umd_info *info); - struct bpfilter_umh_ops { struct umd_info info; /* since ip_getsockopt() can run in parallel, serialize access to umh */ struct mutex lock; - int (*sockopt)(struct sock *sk, int optname, sockptr_t optval, + int (*sockopt)(struct sock *sk, int optname, + char __user *optval, unsigned int optlen, bool is_set); int (*start)(void); + bool stop; }; extern struct bpfilter_umh_ops bpfilter_ops; #endif diff --git a/include/linux/capability.h b/include/linux/capability.h index 1e7fe311cabe..b4345b38a6be 100644 --- a/include/linux/capability.h +++ b/include/linux/capability.h @@ -261,12 +261,6 @@ static inline bool bpf_capable(void) return capable(CAP_BPF) || capable(CAP_SYS_ADMIN); } -static inline bool checkpoint_restore_ns_capable(struct user_namespace *ns) -{ - return ns_capable(ns, CAP_CHECKPOINT_RESTORE) || - ns_capable(ns, CAP_SYS_ADMIN); -} - /* audit system wants to get cap info from files as well */ extern int get_vfs_caps_from_disk(const struct dentry *dentry, struct cpu_vfs_cap_data *cpu_caps); diff --git a/include/linux/dax.h b/include/linux/dax.h index d307f6cc7e0b..72a7f03a59f4 100644 --- a/include/linux/dax.h +++ b/include/linux/dax.h @@ -34,8 +34,6 @@ struct dax_operations { /* copy_to_iter: required operation for fs-dax direct-i/o */ size_t (*copy_to_iter)(struct dax_device *, pgoff_t, void *, size_t, struct iov_iter *); - /* zero_page_range: required operation. Zero page range */ - int (*zero_page_range)(struct dax_device *, pgoff_t, size_t); }; extern struct attribute_group dax_attribute_group; @@ -228,8 +226,6 @@ size_t dax_copy_from_iter(struct dax_device *dax_dev, pgoff_t pgoff, void *addr, size_t bytes, struct iov_iter *i); size_t dax_copy_to_iter(struct dax_device *dax_dev, pgoff_t pgoff, void *addr, size_t bytes, struct iov_iter *i); -int dax_zero_page_range(struct dax_device *dax_dev, pgoff_t pgoff, - size_t nr_pages); void dax_flush(struct dax_device *dax_dev, void *addr, size_t size); ssize_t dax_iomap_rw(struct kiocb *iocb, struct iov_iter *iter, diff --git a/include/linux/fs.h b/include/linux/fs.h index e79b51ff5807..773492ba2e6e 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -2167,18 +2167,6 @@ static inline void init_sync_kiocb(struct kiocb *kiocb, struct file *filp) }; } -static inline void kiocb_clone(struct kiocb *kiocb, struct kiocb *kiocb_src, - struct file *filp) -{ - *kiocb = (struct kiocb) { - .ki_filp = filp, - .ki_flags = kiocb_src->ki_flags, - .ki_hint = kiocb_src->ki_hint, - .ki_ioprio = kiocb_src->ki_ioprio, - .ki_pos = kiocb_src->ki_pos, - }; -} - /* * Inode state bits. Protected by inode->i_lock * @@ -2997,11 +2985,6 @@ static inline bool execute_ok(struct inode *inode) return (inode->i_mode & S_IXUGO) || S_ISDIR(inode->i_mode); } -static inline bool inode_wrong_type(const struct inode *inode, umode_t mode) -{ - return (inode->i_mode ^ mode) & S_IFMT; -} - static inline void file_start_write(struct file *file) { if (!S_ISREG(file_inode(file)->i_mode)) @@ -3232,10 +3215,6 @@ ssize_t vfs_iter_read(struct file *file, struct iov_iter *iter, loff_t *ppos, rwf_t flags); ssize_t vfs_iter_write(struct file *file, struct iov_iter *iter, loff_t *ppos, rwf_t flags); -ssize_t vfs_iocb_iter_read(struct file *file, struct kiocb *iocb, - struct iov_iter *iter); -ssize_t vfs_iocb_iter_write(struct file *file, struct kiocb *iocb, - struct iov_iter *iter); /* fs/block_dev.c */ extern ssize_t blkdev_read_iter(struct kiocb *iocb, struct iov_iter *to); diff --git a/include/linux/fs_context.h b/include/linux/fs_context.h index d5a73cd318f8..ebcb91a57e86 100644 --- a/include/linux/fs_context.h +++ b/include/linux/fs_context.h @@ -105,7 +105,6 @@ struct fs_context { enum fs_context_phase phase:8; /* The phase the context is in */ bool need_free:1; /* Need to call ops->free() */ bool global:1; /* Goes into &init_user_ns */ - bool oldapi:1; /* Coming from mount(2) */ }; struct fs_context_operations { diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h index a96941c30991..16cfbfbf861f 100644 --- a/include/linux/ftrace.h +++ b/include/linux/ftrace.h @@ -81,7 +81,8 @@ static inline int ftrace_mod_get_kallsym(unsigned int symnum, unsigned long *val extern int ftrace_enabled; extern int ftrace_enable_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, + loff_t *ppos); struct ftrace_ops; @@ -280,8 +281,9 @@ static inline void arch_ftrace_set_direct_caller(struct pt_regs *regs, extern int stack_tracer_enabled; -int stack_trace_sysctl(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos); +int stack_trace_sysctl(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); /* DO NOT MODIFY THIS VARIABLE DIRECTLY! */ DECLARE_PER_CPU(int, disable_stack_tracer); diff --git a/include/linux/if_bridge.h b/include/linux/if_bridge.h index e06623fa5b80..9e2ad3b81690 100644 --- a/include/linux/if_bridge.h +++ b/include/linux/if_bridge.h @@ -162,9 +162,5 @@ extern br_notify_hook_t __rcu *br_notify_hook; typedef int (br_multicast_handle_hook_t)(const struct net_bridge_port *src, struct sk_buff *skb); extern br_multicast_handle_hook_t __rcu *br_multicast_handle_hook; -typedef struct net_bridge_port *br_get_dst_hook_t( - const struct net_bridge_port *src, - struct sk_buff **skb); -extern br_get_dst_hook_t __rcu *br_get_dst_hook; #endif #endif diff --git a/include/linux/io-pgtable-fast.h b/include/linux/io-pgtable-fast.h index 95b05a85f61c..245f86fbbe46 100644 --- a/include/linux/io-pgtable-fast.h +++ b/include/linux/io-pgtable-fast.h @@ -44,7 +44,7 @@ struct av8l_fast_io_pgtable { int av8l_fast_map_public(struct io_pgtable_ops *ops, unsigned long iova, phys_addr_t paddr, size_t size, int prot); -size_t av8l_fast_unmap_public(struct io_pgtable_ops *ops, unsigned long iova, +void av8l_fast_unmap_public(struct io_pgtable_ops *ops, unsigned long iova, size_t size); int av8l_fast_map_sg_public(struct io_pgtable_ops *ops, @@ -63,10 +63,9 @@ av8l_fast_map_public(struct io_pgtable_ops *ops, unsigned long iova, { return -EINVAL; } -static inline size_t av8l_fast_unmap_public(struct io_pgtable_ops *ops, +static inline void av8l_fast_unmap_public(struct io_pgtable_ops *ops, unsigned long iova, size_t size) { - return 0; } static inline int av8l_fast_map_sg_public(struct io_pgtable_ops *ops, diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h index 6003273ec2e9..6f006ccbdca7 100644 --- a/include/linux/ipv6.h +++ b/include/linux/ipv6.h @@ -33,7 +33,6 @@ struct ipv6_devconf { __s32 max_addresses; __s32 accept_ra_defrtr; __s32 accept_ra_min_hop_limit; - __s32 accept_ra_min_lft; __s32 accept_ra_pinfo; __s32 ignore_routes_with_linkdown; #ifdef CONFIG_IPV6_ROUTER_PREF diff --git a/include/linux/kfence.h b/include/linux/kfence.h deleted file mode 100644 index 3fe6dd8a18c1..000000000000 --- a/include/linux/kfence.h +++ /dev/null @@ -1,223 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Kernel Electric-Fence (KFENCE). Public interface for allocator and fault - * handler integration. For more info see Documentation/dev-tools/kfence.rst. - * - * Copyright (C) 2020, Google LLC. - */ - -#ifndef _LINUX_KFENCE_H -#define _LINUX_KFENCE_H - -#include -#include - -#ifdef CONFIG_KFENCE - -/* - * We allocate an even number of pages, as it simplifies calculations to map - * address to metadata indices; effectively, the very first page serves as an - * extended guard page, but otherwise has no special purpose. - */ -#define KFENCE_POOL_SIZE ((CONFIG_KFENCE_NUM_OBJECTS + 1) * 2 * PAGE_SIZE) -extern char *__kfence_pool; - -#ifdef CONFIG_KFENCE_STATIC_KEYS -#include -DECLARE_STATIC_KEY_FALSE(kfence_allocation_key); -#else -#include -extern atomic_t kfence_allocation_gate; -#endif - -/** - * is_kfence_address() - check if an address belongs to KFENCE pool - * @addr: address to check - * - * Return: true or false depending on whether the address is within the KFENCE - * object range. - * - * KFENCE objects live in a separate page range and are not to be intermixed - * with regular heap objects (e.g. KFENCE objects must never be added to the - * allocator freelists). Failing to do so may and will result in heap - * corruptions, therefore is_kfence_address() must be used to check whether - * an object requires specific handling. - * - * Note: This function may be used in fast-paths, and is performance critical. - * Future changes should take this into account; for instance, we want to avoid - * introducing another load and therefore need to keep KFENCE_POOL_SIZE a - * constant (until immediate patching support is added to the kernel). - */ -static __always_inline bool is_kfence_address(const void *addr) -{ - /* - * The __kfence_pool != NULL check is required to deal with the case - * where __kfence_pool == NULL && addr < KFENCE_POOL_SIZE. Keep it in - * the slow-path after the range-check! - */ - return unlikely((unsigned long)((char *)addr - __kfence_pool) < KFENCE_POOL_SIZE && __kfence_pool); -} - -/** - * kfence_alloc_pool() - allocate the KFENCE pool via memblock - */ -void __init kfence_alloc_pool(void); - -/** - * kfence_init() - perform KFENCE initialization at boot time - * - * Requires that kfence_alloc_pool() was called before. This sets up the - * allocation gate timer, and requires that workqueues are available. - */ -void __init kfence_init(void); - -/** - * kfence_shutdown_cache() - handle shutdown_cache() for KFENCE objects - * @s: cache being shut down - * - * Before shutting down a cache, one must ensure there are no remaining objects - * allocated from it. Because KFENCE objects are not referenced from the cache - * directly, we need to check them here. - * - * Note that shutdown_cache() is internal to SL*B, and kmem_cache_destroy() does - * not return if allocated objects still exist: it prints an error message and - * simply aborts destruction of a cache, leaking memory. - * - * If the only such objects are KFENCE objects, we will not leak the entire - * cache, but instead try to provide more useful debug info by making allocated - * objects "zombie allocations". Objects may then still be used or freed (which - * is handled gracefully), but usage will result in showing KFENCE error reports - * which include stack traces to the user of the object, the original allocation - * site, and caller to shutdown_cache(). - */ -void kfence_shutdown_cache(struct kmem_cache *s); - -/* - * Allocate a KFENCE object. Allocators must not call this function directly, - * use kfence_alloc() instead. - */ -void *__kfence_alloc(struct kmem_cache *s, size_t size, gfp_t flags); - -/** - * kfence_alloc() - allocate a KFENCE object with a low probability - * @s: struct kmem_cache with object requirements - * @size: exact size of the object to allocate (can be less than @s->size - * e.g. for kmalloc caches) - * @flags: GFP flags - * - * Return: - * * NULL - must proceed with allocating as usual, - * * non-NULL - pointer to a KFENCE object. - * - * kfence_alloc() should be inserted into the heap allocation fast path, - * allowing it to transparently return KFENCE-allocated objects with a low - * probability using a static branch (the probability is controlled by the - * kfence.sample_interval boot parameter). - */ -static __always_inline void *kfence_alloc(struct kmem_cache *s, size_t size, gfp_t flags) -{ -#ifdef CONFIG_KFENCE_STATIC_KEYS - if (static_branch_unlikely(&kfence_allocation_key)) -#else - if (unlikely(!atomic_read(&kfence_allocation_gate))) -#endif - return __kfence_alloc(s, size, flags); - return NULL; -} - -/** - * kfence_ksize() - get actual amount of memory allocated for a KFENCE object - * @addr: pointer to a heap object - * - * Return: - * * 0 - not a KFENCE object, must call __ksize() instead, - * * non-0 - this many bytes can be accessed without causing a memory error. - * - * kfence_ksize() returns the number of bytes requested for a KFENCE object at - * allocation time. This number may be less than the object size of the - * corresponding struct kmem_cache. - */ -size_t kfence_ksize(const void *addr); - -/** - * kfence_object_start() - find the beginning of a KFENCE object - * @addr: address within a KFENCE-allocated object - * - * Return: address of the beginning of the object. - * - * SL[AU]B-allocated objects are laid out within a page one by one, so it is - * easy to calculate the beginning of an object given a pointer inside it and - * the object size. The same is not true for KFENCE, which places a single - * object at either end of the page. This helper function is used to find the - * beginning of a KFENCE-allocated object. - */ -void *kfence_object_start(const void *addr); - -/** - * __kfence_free() - release a KFENCE heap object to KFENCE pool - * @addr: object to be freed - * - * Requires: is_kfence_address(addr) - * - * Release a KFENCE object and mark it as freed. - */ -void __kfence_free(void *addr); - -/** - * kfence_free() - try to release an arbitrary heap object to KFENCE pool - * @addr: object to be freed - * - * Return: - * * false - object doesn't belong to KFENCE pool and was ignored, - * * true - object was released to KFENCE pool. - * - * Release a KFENCE object and mark it as freed. May be called on any object, - * even non-KFENCE objects, to simplify integration of the hooks into the - * allocator's free codepath. The allocator must check the return value to - * determine if it was a KFENCE object or not. - */ -static __always_inline __must_check bool kfence_free(void *addr) -{ - if (!is_kfence_address(addr)) - return false; - __kfence_free(addr); - return true; -} - -/** - * kfence_handle_page_fault() - perform page fault handling for KFENCE pages - * @addr: faulting address - * @is_write: is access a write - * @regs: current struct pt_regs (can be NULL, but shows full stack trace) - * - * Return: - * * false - address outside KFENCE pool, - * * true - page fault handled by KFENCE, no additional handling required. - * - * A page fault inside KFENCE pool indicates a memory error, such as an - * out-of-bounds access, a use-after-free or an invalid memory access. In these - * cases KFENCE prints an error message and marks the offending page as - * present, so that the kernel can proceed. - */ -bool __must_check kfence_handle_page_fault(unsigned long addr, bool is_write, struct pt_regs *regs); - -#else /* CONFIG_KFENCE */ - -static inline bool is_kfence_address(const void *addr) { return false; } -static inline void kfence_alloc_pool(void) { } -static inline void kfence_init(void) { } -static inline void kfence_shutdown_cache(struct kmem_cache *s) { } -static inline void *kfence_alloc(struct kmem_cache *s, size_t size, gfp_t flags) { return NULL; } -static inline size_t kfence_ksize(const void *addr) { return 0; } -static inline void *kfence_object_start(const void *addr) { return NULL; } -static inline void __kfence_free(void *addr) { } -static inline bool __must_check kfence_free(void *addr) { return false; } -static inline bool __must_check kfence_handle_page_fault(unsigned long addr, bool is_write, - struct pt_regs *regs) -{ - return false; -} - -#endif - -#endif /* _LINUX_KFENCE_H */ diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index eb40c638684f..773a335c2c5e 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -2614,8 +2614,6 @@ enum netdev_cmd { NETDEV_CVLAN_FILTER_DROP_INFO, NETDEV_SVLAN_FILTER_PUSH_INFO, NETDEV_SVLAN_FILTER_DROP_INFO, - NETDEV_BR_JOIN, - NETDEV_BR_LEAVE, }; const char *netdev_cmd_to_name(enum netdev_cmd cmd); diff --git a/include/linux/pid.h b/include/linux/pid.h index 064847e90cf0..8c836713d6c4 100644 --- a/include/linux/pid.h +++ b/include/linux/pid.h @@ -126,8 +126,7 @@ extern struct pid *find_vpid(int nr); extern struct pid *find_get_pid(int nr); extern struct pid *find_ge_pid(int nr, struct pid_namespace *); -extern struct pid *alloc_pid(struct pid_namespace *ns, pid_t *set_tid, - size_t set_tid_size); +extern struct pid *alloc_pid(struct pid_namespace *ns); extern void free_pid(struct pid *pid); extern void disable_pid_allocation(struct pid_namespace *ns); diff --git a/include/linux/pid_namespace.h b/include/linux/pid_namespace.h index 2ed6af88794b..49538b172483 100644 --- a/include/linux/pid_namespace.h +++ b/include/linux/pid_namespace.h @@ -12,8 +12,6 @@ #include #include -/* MAX_PID_NS_LEVEL is needed for limiting size of 'struct pid' */ -#define MAX_PID_NS_LEVEL 32 struct fs_pin; diff --git a/include/linux/random.h b/include/linux/random.h index 7e742ef51a83..8ed2e245d51e 100644 --- a/include/linux/random.h +++ b/include/linux/random.h @@ -64,8 +64,7 @@ static inline unsigned long get_random_canary(void) return get_random_long() & CANARY_MASK; } -void __init random_init_early(const char *command_line); -void __init random_init(void); +int __init random_init(const char *command_line); bool rng_is_initialized(void); int wait_for_random_bytes(void); int register_random_ready_notifier(struct notifier_block *nb); diff --git a/include/linux/sched/signal.h b/include/linux/sched/signal.h index df80d15b888e..797bbafb95c0 100644 --- a/include/linux/sched/signal.h +++ b/include/linux/sched/signal.h @@ -691,8 +691,6 @@ static inline int thread_group_empty(struct task_struct *p) extern struct sighand_struct *__lock_task_sighand(struct task_struct *task, unsigned long *flags); -extern bool thread_group_exited(struct pid *pid); - static inline struct sighand_struct *lock_task_sighand(struct task_struct *task, unsigned long *flags) { diff --git a/include/linux/sched/task.h b/include/linux/sched/task.h index b53ee6d7111d..e3c20a4f81f5 100644 --- a/include/linux/sched/task.h +++ b/include/linux/sched/task.h @@ -26,9 +26,6 @@ struct kernel_clone_args { unsigned long stack; unsigned long stack_size; unsigned long tls; - pid_t *set_tid; - /* Number of elements in *set_tid */ - size_t set_tid_size; }; /* diff --git a/include/linux/seccomp.h b/include/linux/seccomp.h index a6f90d9cea47..84868d37b35d 100644 --- a/include/linux/seccomp.h +++ b/include/linux/seccomp.h @@ -12,7 +12,6 @@ #ifdef CONFIG_SECCOMP #include -#include #include struct seccomp_filter; @@ -29,7 +28,6 @@ struct seccomp_filter; */ struct seccomp { int mode; - atomic_t filter_count; struct seccomp_filter *filter; }; @@ -83,10 +81,10 @@ static inline int seccomp_mode(struct seccomp *s) #endif /* CONFIG_SECCOMP */ #ifdef CONFIG_SECCOMP_FILTER -extern void seccomp_filter_release(struct task_struct *tsk); +extern void put_seccomp_filter(struct task_struct *tsk); extern void get_seccomp_filter(struct task_struct *tsk); #else /* CONFIG_SECCOMP_FILTER */ -static inline void seccomp_filter_release(struct task_struct *tsk) +static inline void put_seccomp_filter(struct task_struct *tsk) { return; } diff --git a/include/linux/security.h b/include/linux/security.h index 8261a0646956..ddf4116b8ba4 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -118,7 +118,6 @@ enum lockdown_reason { LOCKDOWN_MMIOTRACE, LOCKDOWN_DEBUGFS, LOCKDOWN_XMON_WR, - LOCKDOWN_BPF_WRITE_USER, LOCKDOWN_DBG_WRITE_KERNEL, LOCKDOWN_INTEGRITY_MAX, LOCKDOWN_KCORE, diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index add201a31f2c..120a2162b844 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -1626,22 +1626,6 @@ static inline int skb_unclone(struct sk_buff *skb, gfp_t pri) return 0; } -/* This variant of skb_unclone() makes sure skb->truesize is not changed */ -static inline int skb_unclone_keeptruesize(struct sk_buff *skb, gfp_t pri) -{ - might_sleep_if(gfpflags_allow_blocking(pri)); - - if (skb_cloned(skb)) { - unsigned int save = skb->truesize; - int res; - - res = pskb_expand_head(skb, 0, 0, pri); - skb->truesize = save; - return res; - } - return 0; -} - /** * skb_header_cloned - is the header a clone * @skb: buffer to check diff --git a/include/linux/skmsg.h b/include/linux/skmsg.h index 3d31b629bcbf..b14017c3dbaf 100644 --- a/include/linux/skmsg.h +++ b/include/linux/skmsg.h @@ -71,9 +71,7 @@ struct sk_psock_link { }; struct sk_psock_parser { -#if IS_ENABLED(CONFIG_BPF_STREAM_PARSER) struct strparser strp; -#endif bool enabled; void (*saved_data_ready)(struct sock *sk); }; @@ -308,27 +306,9 @@ static inline void sk_psock_report_error(struct sk_psock *psock, int err) struct sk_psock *sk_psock_init(struct sock *sk, int node); -#if IS_ENABLED(CONFIG_BPF_STREAM_PARSER) int sk_psock_init_strp(struct sock *sk, struct sk_psock *psock); void sk_psock_start_strp(struct sock *sk, struct sk_psock *psock); void sk_psock_stop_strp(struct sock *sk, struct sk_psock *psock); -#else -static inline int sk_psock_init_strp(struct sock *sk, struct sk_psock *psock) -{ - return -EOPNOTSUPP; -} - -static inline void sk_psock_start_strp(struct sock *sk, struct sk_psock *psock) -{ -} - -static inline void sk_psock_stop_strp(struct sock *sk, struct sk_psock *psock) -{ -} -#endif - -void sk_psock_start_verdict(struct sock *sk, struct sk_psock *psock); -void sk_psock_stop_verdict(struct sock *sk, struct sk_psock *psock); int sk_psock_msg_verdict(struct sock *sk, struct sk_psock *psock, struct sk_msg *msg); @@ -361,6 +341,23 @@ static inline void sk_psock_update_proto(struct sock *sk, struct sk_psock *psock, struct proto *ops) { + /* Initialize saved callbacks and original proto only once, since this + * function may be called multiple times for a psock, e.g. when + * psock->progs.msg_parser is updated. + * + * Since we've not installed the new proto, psock is not yet in use and + * we can initialize it without synchronization. + */ + if (!psock->sk_proto) { + struct proto *orig = READ_ONCE(sk->sk_prot); + + psock->saved_unhash = orig->unhash; + psock->saved_close = orig->close; + psock->saved_write_space = sk->sk_write_space; + + psock->sk_proto = orig; + } + /* Pairs with lockless read in sk_clone_lock() */ WRITE_ONCE(sk->sk_prot, ops); } diff --git a/include/linux/stackleak.h b/include/linux/stackleak.h index a59db2f08e76..3d5c3271a9a8 100644 --- a/include/linux/stackleak.h +++ b/include/linux/stackleak.h @@ -25,7 +25,7 @@ static inline void stackleak_task_init(struct task_struct *t) #ifdef CONFIG_STACKLEAK_RUNTIME_DISABLE int stack_erasing_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); #endif #else /* !CONFIG_GCC_PLUGIN_STACKLEAK */ diff --git a/include/linux/touchscreen_mmi.h b/include/linux/touchscreen_mmi.h index 7443639e086c..3655136150a1 100644 --- a/include/linux/touchscreen_mmi.h +++ b/include/linux/touchscreen_mmi.h @@ -137,9 +137,6 @@ struct drm_panel_notifier *evdata = evd; \ ((event == DRM_PANEL_EVENT_BLANK) && \ (*blank == DRM_PANEL_BLANK_UNBLANK)) -#define EVENT_DISPLAY_LP \ - (*blank == DRM_PANEL_BLANK_LP) - #else /* CONFIG_DRM_PANEL_NOTIFICATIONS */ #if LINUX_VERSION_CODE <= KERNEL_VERSION(4,14,0) #if defined(CONFIG_DRM_MSM) diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h index 3469d890d9e1..ad4d4697a167 100644 --- a/include/linux/virtio_config.h +++ b/include/linux/virtio_config.h @@ -10,11 +10,6 @@ struct irq_affinity; -struct virtio_shm_region { - u64 addr; - u64 len; -}; - /** * virtio_config_ops - operations for configuring a virtio device * Note: Do not assume that a transport implements all of the operations @@ -71,7 +66,6 @@ struct virtio_shm_region { * the caller can then copy. * @set_vq_affinity: set the affinity for a virtqueue (optional). * @get_vq_affinity: get the affinity for a virtqueue (optional). - * @get_shm_region: get a shared memory region based on the index. */ typedef void vq_callback_t(struct virtqueue *); struct virtio_config_ops { @@ -95,8 +89,6 @@ struct virtio_config_ops { const struct cpumask *cpu_mask); const struct cpumask *(*get_vq_affinity)(struct virtio_device *vdev, int index); - bool (*get_shm_region)(struct virtio_device *vdev, - struct virtio_shm_region *region, u8 id); }; /* If driver didn't advertise the feature, it will never appear. */ @@ -259,15 +251,6 @@ int virtqueue_set_affinity(struct virtqueue *vq, const struct cpumask *cpu_mask) return 0; } -static inline -bool virtio_get_shm_region(struct virtio_device *vdev, - struct virtio_shm_region *region, u8 id) -{ - if (!vdev->config->get_shm_region) - return false; - return vdev->config->get_shm_region(vdev, region, id); -} - static inline bool virtio_is_little_endian(struct virtio_device *vdev) { return virtio_has_feature(vdev, VIRTIO_F_VERSION_1) || diff --git a/include/net/checksum.h b/include/net/checksum.h index 25b66833e69b..e13d5ecf71cd 100644 --- a/include/net/checksum.h +++ b/include/net/checksum.h @@ -152,7 +152,7 @@ void inet_proto_csum_replace16(__sum16 *sum, struct sk_buff *skb, const __be32 *from, const __be32 *to, bool pseudohdr); void inet_proto_csum_replace_by_diff(__sum16 *sum, struct sk_buff *skb, - __wsum diff, bool pseudohdr, bool ipv6); + __wsum diff, bool pseudohdr); static __always_inline void inet_proto_csum_replace2(__sum16 *sum, struct sk_buff *skb, diff --git a/include/net/cnss.h b/include/net/cnss.h index 77bc3157c2aa..9c99bdc2032d 100644 --- a/include/net/cnss.h +++ b/include/net/cnss.h @@ -10,6 +10,7 @@ #include #include +#ifdef CONFIG_CNSS #define MAX_FIRMWARE_SIZE (1 * 1024 * 1024) #define CNSS_MAX_FILE_NAME 20 #define PINCTRL_SLEEP 0 @@ -176,6 +177,7 @@ int cnss_pm_runtime_request(struct device *dev, enum cnss_runtime_request request); void cnss_set_cc_source(enum cnss_cc_src cc_source); enum cnss_cc_src cnss_get_cc_source(void); +#endif void cnss_pm_wake_lock_init(struct wakeup_source **ws, const char *name); void cnss_pm_wake_lock(struct wakeup_source *ws); diff --git a/include/net/inet_connection_sock.h b/include/net/inet_connection_sock.h index 6823bcbc9f81..f2a153377a7f 100644 --- a/include/net/inet_connection_sock.h +++ b/include/net/inet_connection_sock.h @@ -359,9 +359,4 @@ static inline void inet_csk_inc_pingpong_cnt(struct sock *sk) if (icsk->icsk_ack.pingpong < U8_MAX) icsk->icsk_ack.pingpong++; } - -static inline bool inet_csk_has_ulp(struct sock *sk) -{ - return inet_sk(sk)->is_icsk && !!inet_csk(sk)->icsk_ulp_ops; -} #endif /* _INET_CONNECTION_SOCK_H */ diff --git a/include/net/ndisc.h b/include/net/ndisc.h index c9e18080ca3a..6cb3e6c11132 100644 --- a/include/net/ndisc.h +++ b/include/net/ndisc.h @@ -494,7 +494,7 @@ int igmp6_event_report(struct sk_buff *skb); #ifdef CONFIG_SYSCTL int ndisc_ifinfo_sysctl_change(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); int ndisc_ifinfo_sysctl_strategy(struct ctl_table *ctl, void __user *oldval, size_t __user *oldlenp, void __user *newval, size_t newlen); diff --git a/include/net/neighbour.h b/include/net/neighbour.h index 7b4063668ec9..4a0720ddc477 100644 --- a/include/net/neighbour.h +++ b/include/net/neighbour.h @@ -387,12 +387,13 @@ void *neigh_seq_next(struct seq_file *, void *, loff_t *); void neigh_seq_stop(struct seq_file *, void *); int neigh_proc_dointvec(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); int neigh_proc_dointvec_jiffies(struct ctl_table *ctl, int write, - void *buffer, + void __user *buffer, size_t *lenp, loff_t *ppos); int neigh_proc_dointvec_ms_jiffies(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, + size_t *lenp, loff_t *ppos); int neigh_sysctl_register(struct net_device *dev, struct neigh_parms *p, proc_handler *proc_handler); diff --git a/include/net/tcp.h b/include/net/tcp.h index 7a50f6984b80..9daea892ccd0 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -356,10 +356,10 @@ ssize_t tcp_splice_read(struct socket *sk, loff_t *ppos, /* sysctl master controller */ extern int tcp_use_userconfig_sysctl_handler(struct ctl_table *table, - int write, void *buffer, size_t *length, + int write, void __user *buffer, size_t *length, loff_t *ppos); extern int tcp_proc_delayed_ack_control(struct ctl_table *table, int write, - void *buffer, size_t *length, + void __user *buffer, size_t *length, loff_t *ppos); void tcp_enter_quickack_mode(struct sock *sk, unsigned int max_quickacks); @@ -2243,26 +2243,26 @@ void tcp_update_ulp(struct sock *sk, struct proto *p, __MODULE_INFO(alias, alias_userspace, name); \ __MODULE_INFO(alias, alias_tcp_ulp, "tcp-ulp-" name) -#ifdef CONFIG_NET_SOCK_MSG struct sk_msg; struct sk_psock; -#ifdef CONFIG_BPF_SYSCALL +#ifdef CONFIG_BPF_STREAM_PARSER struct proto *tcp_bpf_get_proto(struct sock *sk, struct sk_psock *psock); void tcp_bpf_clone(const struct sock *sk, struct sock *newsk); -#endif /* CONFIG_BPF_SYSCALL */ - -int tcp_bpf_sendmsg_redir(struct sock *sk, struct sk_msg *msg, u32 bytes, - int flags); -int __tcp_bpf_recvmsg(struct sock *sk, struct sk_psock *psock, - struct msghdr *msg, int len, int flags); -#endif /* CONFIG_NET_SOCK_MSG */ - -#if !defined(CONFIG_BPF_SYSCALL) || !defined(CONFIG_NET_SOCK_MSG) +#else static inline void tcp_bpf_clone(const struct sock *sk, struct sock *newsk) { } -#endif +#endif /* CONFIG_BPF_STREAM_PARSER */ + +#ifdef CONFIG_NET_SOCK_MSG +int tcp_bpf_sendmsg_redir(struct sock *sk, struct sk_msg *msg, u32 bytes, + int flags); +int tcp_bpf_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, + int nonblock, int flags, int *addr_len); +int __tcp_bpf_recvmsg(struct sock *sk, struct sk_psock *psock, + struct msghdr *msg, int len, int flags); +#endif /* CONFIG_NET_SOCK_MSG */ #ifdef CONFIG_CGROUP_BPF /* Copy the listen sk's HDR_OPT_CB flags to its child. diff --git a/include/net/udp.h b/include/net/udp.h index 429084c8a561..80c224566ce5 100644 --- a/include/net/udp.h +++ b/include/net/udp.h @@ -519,9 +519,4 @@ drop: return NULL; } -#ifdef CONFIG_BPF_SYSCALL -struct sk_psock; -struct proto *udp_bpf_get_proto(struct sock *sk, struct sk_psock *psock); -#endif - #endif /* _UDP_H */ diff --git a/include/trace/events/error_report.h b/include/trace/events/error_report.h deleted file mode 100644 index 96f64bf218b2..000000000000 --- a/include/trace/events/error_report.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Declarations for error reporting tracepoints. - * - * Copyright (C) 2021, Google LLC. - */ -#undef TRACE_SYSTEM -#define TRACE_SYSTEM error_report - -#if !defined(_TRACE_ERROR_REPORT_H) || defined(TRACE_HEADER_MULTI_READ) -#define _TRACE_ERROR_REPORT_H - -#include - -#ifndef __ERROR_REPORT_DECLARE_TRACE_ENUMS_ONCE_ONLY -#define __ERROR_REPORT_DECLARE_TRACE_ENUMS_ONCE_ONLY - -enum error_detector { - ERROR_DETECTOR_KFENCE, - ERROR_DETECTOR_KASAN -}; - -#endif /* __ERROR_REPORT_DECLARE_TRACE_ENUMS_ONCE_ONLY */ - -#define error_detector_list \ - EM(ERROR_DETECTOR_KFENCE, "kfence") \ - EMe(ERROR_DETECTOR_KASAN, "kasan") -/* Always end the list with an EMe. */ - -#undef EM -#undef EMe - -#define EM(a, b) TRACE_DEFINE_ENUM(a); -#define EMe(a, b) TRACE_DEFINE_ENUM(a); - -error_detector_list - -#undef EM -#undef EMe - -#define EM(a, b) { a, b }, -#define EMe(a, b) { a, b } - -#define show_error_detector_list(val) \ - __print_symbolic(val, error_detector_list) - -DECLARE_EVENT_CLASS(error_report_template, - TP_PROTO(enum error_detector error_detector, unsigned long id), - TP_ARGS(error_detector, id), - TP_STRUCT__entry(__field(enum error_detector, error_detector) - __field(unsigned long, id)), - TP_fast_assign(__entry->error_detector = error_detector; - __entry->id = id;), - TP_printk("[%s] %lx", - show_error_detector_list(__entry->error_detector), - __entry->id)); - -/** - * error_report_end - called after printing the error report - * @error_detector: short string describing the error detection tool - * @id: pseudo-unique descriptor identifying the report - * (e.g. the memory access address) - * - * This event occurs right after a debugging tool finishes printing the error - * report. - */ -DEFINE_EVENT(error_report_template, error_report_end, - TP_PROTO(enum error_detector error_detector, unsigned long id), - TP_ARGS(error_detector, id)); - -#endif /* _TRACE_ERROR_REPORT_H */ - -/* This part must be outside protection */ -#include diff --git a/include/uapi/asm-generic/socket.h b/include/uapi/asm-generic/socket.h index 645606824258..77f7c1638eb1 100644 --- a/include/uapi/asm-generic/socket.h +++ b/include/uapi/asm-generic/socket.h @@ -119,8 +119,6 @@ #define SO_DETACH_REUSEPORT_BPF 68 -#define SO_NETNS_COOKIE 71 - #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 || (defined(__x86_64__) && defined(__ILP32__)) diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h index f1307ab8c21b..9cf978154c03 100644 --- a/include/uapi/linux/bpf.h +++ b/include/uapi/linux/bpf.h @@ -199,7 +199,6 @@ enum bpf_prog_type { BPF_PROG_TYPE_EXT, BPF_PROG_TYPE_LSM, BPF_PROG_TYPE_SK_LOOKUP, - BPF_PROG_TYPE_FUSE, }; enum bpf_attach_type { @@ -910,7 +909,6 @@ union bpf_attr { * for updates resulting in a null checksum the value is set to * **CSUM_MANGLED_0** instead. Flag **BPF_F_PSEUDO_HDR** indicates * the checksum is to be computed against a pseudo-header. - * Flag **BPF_F_IPV6** should be set for IPv6 packets. * * This helper works in combination with **bpf_csum_diff**\ (), * which does not update the checksum in-place, but offers more @@ -3947,7 +3945,6 @@ enum { BPF_F_PSEUDO_HDR = (1ULL << 4), BPF_F_MARK_MANGLED_0 = (1ULL << 5), BPF_F_MARK_ENFORCE = (1ULL << 6), - BPF_F_IPV6 = (1ULL << 7), }; /* BPF_FUNC_clone_redirect and BPF_FUNC_redirect flags. */ diff --git a/include/uapi/linux/capability.h b/include/uapi/linux/capability.h index ecd623eea9fe..5fa5aac3f2ef 100644 --- a/include/uapi/linux/capability.h +++ b/include/uapi/linux/capability.h @@ -405,14 +405,7 @@ struct vfs_ns_cap_data { */ #define CAP_BPF 39 - -/* Allow checkpoint/restore related operations */ -/* Allow PID selection during clone3() */ -/* Allow writing to ns_last_pid */ - -#define CAP_CHECKPOINT_RESTORE 40 - -#define CAP_LAST_CAP CAP_CHECKPOINT_RESTORE +#define CAP_LAST_CAP CAP_BPF #define cap_valid(x) ((x) >= 0 && (x) <= CAP_LAST_CAP) diff --git a/include/uapi/linux/fuse.h b/include/uapi/linux/fuse.h index f0521a39a586..a62498fbad3e 100644 --- a/include/uapi/linux/fuse.h +++ b/include/uapi/linux/fuse.h @@ -172,9 +172,6 @@ * - add FUSE_WRITE_KILL_PRIV flag * - add FUSE_SETUPMAPPING and FUSE_REMOVEMAPPING * - add map_alignment to fuse_init_out, add FUSE_MAP_ALIGNMENT flag - * - * 7.32 - * - add flags to fuse_attr, add FUSE_ATTR_SUBMOUNT, add FUSE_SUBMOUNTS */ #ifndef _LINUX_FUSE_H @@ -210,7 +207,7 @@ #define FUSE_KERNEL_VERSION 7 /** Minor version number of this interface */ -#define FUSE_KERNEL_MINOR_VERSION 32 +#define FUSE_KERNEL_MINOR_VERSION 31 /** The node ID of the root inode */ #define FUSE_ROOT_ID 1 @@ -234,7 +231,7 @@ struct fuse_attr { uint32_t gid; uint32_t rdev; uint32_t blksize; - uint32_t flags; + uint32_t padding; }; struct fuse_kstatfs { @@ -316,10 +313,7 @@ struct fuse_file_lock { * FUSE_CACHE_SYMLINKS: cache READLINK responses * FUSE_NO_OPENDIR_SUPPORT: kernel supports zero-message opendir * FUSE_EXPLICIT_INVAL_DATA: only invalidate cached pages on explicit request - * FUSE_MAP_ALIGNMENT: init_out.map_alignment contains log2(byte alignment) for - * foffset and moffset fields in struct - * fuse_setupmapping_out and fuse_removemapping_one. - * FUSE_SUBMOUNTS: kernel supports auto-mounting directory submounts + * FUSE_MAP_ALIGNMENT: map_alignment field is valid */ #define FUSE_ASYNC_READ (1 << 0) #define FUSE_POSIX_LOCKS (1 << 1) @@ -348,7 +342,6 @@ struct fuse_file_lock { #define FUSE_NO_OPENDIR_SUPPORT (1 << 24) #define FUSE_EXPLICIT_INVAL_DATA (1 << 25) #define FUSE_MAP_ALIGNMENT (1 << 26) -#define FUSE_SUBMOUNTS (1 << 27) #define FUSE_PASSTHROUGH (1 << 31) /** @@ -425,13 +418,6 @@ struct fuse_file_lock { */ #define FUSE_FSYNC_FDATASYNC (1 << 0) -/** - * fuse_attr flags - * - * FUSE_ATTR_SUBMOUNT: Object is a submount root - */ -#define FUSE_ATTR_SUBMOUNT (1 << 0) - enum fuse_opcode { FUSE_LOOKUP = 1, FUSE_FORGET = 2, /* no reply */ @@ -516,23 +502,6 @@ struct fuse_entry_out { struct fuse_attr attr; }; -#define FUSE_ACTION_KEEP 0 -#define FUSE_ACTION_REMOVE 1 -#define FUSE_ACTION_REPLACE 2 - -struct fuse_entry_bpf_out { - uint64_t backing_action; - uint64_t backing_fd; - uint64_t bpf_action; - uint64_t bpf_fd; -}; - -struct fuse_entry_bpf { - struct fuse_entry_bpf_out out; - struct file *backing_file; - struct file *bpf_file; -}; - struct fuse_forget_in { uint64_t nlookup; }; @@ -651,12 +620,6 @@ struct fuse_read_in { uint32_t padding; }; -struct fuse_read_out { - uint64_t offset; - uint32_t again; - uint32_t padding; -}; - #define FUSE_COMPAT_WRITE_IN_SIZE 24 struct fuse_write_in { @@ -830,7 +793,7 @@ struct fuse_in_header { uint32_t uid; uint32_t gid; uint32_t pid; - uint32_t error_in; + uint32_t padding; }; struct fuse_out_header { @@ -935,82 +898,4 @@ struct fuse_copy_file_range_in { uint64_t flags; }; -#define FUSE_SETUPMAPPING_FLAG_WRITE (1ull << 0) -#define FUSE_SETUPMAPPING_FLAG_READ (1ull << 1) -struct fuse_setupmapping_in { - /* An already open handle */ - uint64_t fh; - /* Offset into the file to start the mapping */ - uint64_t foffset; - /* Length of mapping required */ - uint64_t len; - /* Flags, FUSE_SETUPMAPPING_FLAG_* */ - uint64_t flags; - /* Offset in Memory Window */ - uint64_t moffset; -}; - -struct fuse_removemapping_in { - /* number of fuse_removemapping_one follows */ - uint32_t count; -}; - -struct fuse_removemapping_one { - /* Offset into the dax window start the unmapping */ - uint64_t moffset; - /* Length of mapping required */ - uint64_t len; -}; - -#define FUSE_REMOVEMAPPING_MAX_ENTRY \ - (PAGE_SIZE / sizeof(struct fuse_removemapping_one)) - -/* - * Fuse BPF Args - * - * Used to communicate with bpf programs to allow checking or altering certain values. - * The end_offset allows the bpf verifier to check boundaries statically. This reflects - * the ends of the buffer. size shows the length that was actually used. - * - */ - -/** One input argument of a request */ -struct fuse_bpf_in_arg { - uint32_t size; - const void *value; - const void *end_offset; -}; - -/** One output argument of a request */ -struct fuse_bpf_arg { - uint32_t size; - void *value; - void *end_offset; -}; - -#define FUSE_MAX_IN_ARGS 5 -#define FUSE_MAX_OUT_ARGS 3 - -#define FUSE_BPF_FORCE (1 << 0) -#define FUSE_BPF_OUT_ARGVAR (1 << 6) - -struct fuse_bpf_args { - uint64_t nodeid; - uint32_t opcode; - uint32_t error_in; - uint32_t in_numargs; - uint32_t out_numargs; - uint32_t flags; - struct fuse_bpf_in_arg in_args[FUSE_MAX_IN_ARGS]; - struct fuse_bpf_arg out_args[FUSE_MAX_OUT_ARGS]; -}; - -#define FUSE_BPF_USER_FILTER 1 -#define FUSE_BPF_BACKING 2 -#define FUSE_BPF_POST_FILTER 4 - -#define FUSE_OPCODE_FILTER 0x0ffff -#define FUSE_PREFILTER 0x10000 -#define FUSE_POSTFILTER 0x20000 - #endif /* _LINUX_FUSE_H */ diff --git a/include/uapi/linux/ipv6.h b/include/uapi/linux/ipv6.h index 45406a092e4e..9c0f4a92bcff 100644 --- a/include/uapi/linux/ipv6.h +++ b/include/uapi/linux/ipv6.h @@ -187,7 +187,6 @@ enum { DEVCONF_DISABLE_POLICY, DEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN, DEVCONF_NDISC_TCLASS, - DEVCONF_ACCEPT_RA_MIN_LFT, DEVCONF_MAX }; diff --git a/include/uapi/linux/msm_ipa.h b/include/uapi/linux/msm_ipa.h index 5f63c7b96479..8d2bb198379d 100644 --- a/include/uapi/linux/msm_ipa.h +++ b/include/uapi/linux/msm_ipa.h @@ -2,7 +2,7 @@ /* * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. * - * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _UAPI_MSM_IPA_H_ @@ -152,9 +152,8 @@ #define IPA_IOCTL_SET_EXT_ROUTER_MODE 95 #define IPA_IOCTL_ADD_DEL_DSCP_PCP_MAPPING 96 #define IPA_IOCTL_SEND_VLAN_MUXID_MAPPING 97 -#define IPA_IOCTL_SEND_TUNNEL_TEMPLATE_INFO 98 -#define IPA_IOCTL_QUERY_TUNNEL_FEATURE 99 -#define IPA_IOCTL_ADD_IPOGRE_MAPPING 100 +#define IPA_IOCTL_SEND_TUNNEL_TEMPLATE_INFO 98 +#define IPA_IOCTL_QUERY_TUNNEL_FEATURE 99 /** * max size of the header to be inserted */ @@ -977,12 +976,8 @@ enum ipa_eth_pdu_evt { #define IPA_ENABLE_ETH_PDU_MODE_EVENT_MAX IPA_ENABLE_ETH_PDU_MODE_EVENT_MAX }; -enum ipa_ipogre_event { - IPA_IPOGRE_NOTIFY_EVENT = IPA_ENABLE_ETH_PDU_MODE_EVENT_MAX, - IPA_IPOGRE_EVENT_MAX -#define IPA_IPOGRE_EVENT_MAX IPA_IPOGRE_EVENT_MAX -}; -#define IPA_EVENT_MAX_NUM (IPA_IPOGRE_EVENT_MAX) + +#define IPA_EVENT_MAX_NUM (IPA_ENABLE_ETH_PDU_MODE_EVENT_MAX) #define IPA_EVENT_MAX ((int)IPA_EVENT_MAX_NUM) /** @@ -1145,6 +1140,48 @@ static inline const char *exception_type_as_str(enum ipa_exception_type t) "???"; } +/** + * Macro ipa_exception_type_pppoe + * + * This macro is for describing which field is to be looked at for + * exception path consideration. + * + * NOTE 1: The field implies an offset into the packet under + * consideration. This offset will be calculated on behalf of + * the user of this API. + * + * NOTE 2: When exceptions are generated/sent in an ipa_exception + * structure, they will considered to be from the upload + * perspective. And when appropriate, a corresponding, and + * perhaps inverted, downlink exception will be automatically + * created on the callers behalf. As an example: If a + * FIELD_UDP_SRC_PORT is sent, an uplink exception will be + * created for udp source port, and a corresponding + * FIELD_UDP_DST_PORT will be automatically created for the + * downlink. + */ +#define FIELD_IP_PROTOCOL_PPPOE (FIELD_ETHER_TYPE + 1) +#define FIELD_TCP_SRC_PORT_PPPOE (FIELD_IP_PROTOCOL_PPPOE + 1) +#define FIELD_TCP_DST_PORT_PPPOE (FIELD_TCP_SRC_PORT_PPPOE + 1) +#define FIELD_UDP_SRC_PORT_PPPOE (FIELD_TCP_DST_PORT_PPPOE + 1) +#define FIELD_UDP_DST_PORT_PPPOE (FIELD_UDP_SRC_PORT_PPPOE + 1) +#define FIELD_ETHER_TYPE_PPPOE (FIELD_UDP_DST_PORT_PPPOE + 1) +#define FIELD_PPPOE_MAX (FIELD_ETHER_TYPE_PPPOE + 1) + +/* Function to read PPPoE exception in string format */ +static inline const char *pppoe_exception_type_as_str(uint32_t t) +{ + return + (t == FIELD_IP_PROTOCOL_PPPOE) ? "pppoe_ip_protocol" : + (t == FIELD_TCP_SRC_PORT_PPPOE) ? "pppoe_tcp_src_port" : + (t == FIELD_TCP_DST_PORT_PPPOE) ? "pppoe_tcp_dst_port" : + (t == FIELD_UDP_SRC_PORT_PPPOE) ? "pppoe_udp_src_port" : + (t == FIELD_UDP_DST_PORT_PPPOE) ? "pppoe_udp_dst_port" : + (t == FIELD_ETHER_TYPE_PPPOE) ? "pppoe_ether_type" : + (t == FIELD_PPPOE_MAX) ? "pppoe_max" : + "???"; +} + #define IP_TYPE_EXCEPTION(x) \ ((x) == FIELD_IP_PROTOCOL || \ (x) == FIELD_TCP_SRC_PORT || \ @@ -1225,6 +1262,7 @@ struct ipa_field_val_equation_gen { * @payload_length: Payload length. * @ext_attrib_mask: Extended attributes. * @l2tp_udp_next_hdr: next header in L2TP tunneling + * @p_exception : exception to enable for mpls-pppoe * @field_val_equ: for finding a value at a particular offset */ struct ipa_rule_attrib { @@ -1270,7 +1308,7 @@ struct ipa_rule_attrib { __u16 payload_length; __u32 ext_attrib_mask; __u8 l2tp_udp_next_hdr; - __u8 padding1; + __u8 p_exception; struct ipa_field_val_equation_gen fld_val_eq; }; @@ -1556,11 +1594,9 @@ enum ipa_hdr_proc_type { IPA_HDR_PROC_EoGRE_HEADER_REMOVE, IPA_HDR_PROC_WWAN_TO_ETHII_EX, IPA_HDR_PROC_GRE_HEADER_ADD, - IPA_HDR_PROC_GRE_HEADER_REMOVE, - IPA_HDR_PROC_IPOGRE_HEADER_ADD, - IPA_HDR_PROC_IPOGRE_HEADER_REMOVE + IPA_HDR_PROC_GRE_HEADER_REMOVE }; -#define IPA_HDR_PROC_MAX (IPA_HDR_PROC_IPOGRE_HEADER_REMOVE + 1) +#define IPA_HDR_PROC_MAX (IPA_HDR_PROC_GRE_HEADER_REMOVE + 1) /** * struct ipa_rt_rule - attributes of a routing rule @@ -1965,68 +2001,6 @@ struct ipa_ioc_eogre_info { struct IpaDscpVlanPcpMap_t map_info; }; -#define MAX_FLOW_PER_IPOGRE_TUNNEL 10 - -/** - * struct ipa_ipogre_info - - * @ipv4_src: Specifies source v4 address if GRE tunnel is ipv4 - * @ipv4_dst: Specifies destination v4 address if GRE tunnel is ipv4 - * @ipv6_src: Specifies source v6 address if GRE tunnel is ipv6 - * @ipv6_dst: Specifies destination v6 address if GRE tunnel is ipv6 - * @iptype: Specifies GRE tunnel's ip address type - * @tunnel_id: Specifies tunnel id - */ - -struct ipa_ipogre_tunnel_info { - uint32_t ipv4_src; - uint32_t ipv4_dst; - uint32_t ipv6_src[4]; - uint32_t ipv6_dst[4]; - enum ipa_ip_type iptype; - uint8_t tunnel_id; -} __packed; - -/** - * struct ipa_ipogre_info - - * @ipv4_src: Specifies source v4 address if GRE tunnel is ipv4 - * @ipv4_src_subnet: Specifies source v4 address subnet if GRE tunnel is ipv4 - * @ipv4_dst: Specifies destination v4 address if GRE tunnel is ipv4 - * @ipv4_dst_subnet: Specifies destination v4 address subnet if GRE tunnel is ipv4 - * @ipv6_src: Specifies source v6 address if GRE tunnel is ipv6 - * @ipv6_src_subnet: Specifies source v6 address subnet if GRE tunnel is ipv6 - * @ipv6_dst: Specifies destination v6 address if GRE tunnel is ipv6 - * @ipv6_dst_subnet: Specifies destination v6 address subnet if GRE tunnel is ipv6 - * @iptype: Specifies GRE tunnel's ip address type - * @protocol: Specifies protocol of the data traffic - */ - -struct ipa_ipogre_flow_info { - uint32_t ipv4_src; - uint32_t ipv4_src_subnet; - uint32_t ipv4_dst; - uint32_t ipv4_dst_subnet; - uint32_t ipv6_src[4]; - uint32_t ipv6_dst[4]; - uint32_t src_port; - uint32_t dst_port; - enum ipa_ip_type iptype; - uint8_t protocol; - uint8_t ipv6_src_subnet; - uint8_t ipv6_dst_subnet; -} __packed; - -/** - * struct ipa_ipogre_info - - * @ipogre_tunnel_info: Specifies tunnel information - * @ipogre_flow_info: Specifies flows to be offloaded - * @ipa_ipogre_num_flow: Specifies number of flow to be offloaded - */ - -struct ipa_ioc_ipogre_info { - struct ipa_ipogre_tunnel_info ipogre_tunnel_info; - struct ipa_ipogre_flow_info ipogre_flow_info[MAX_FLOW_PER_IPOGRE_TUNNEL]; - uint8_t ipa_ipogre_num_flow; -}; /** * struct ipa_eogre_header_add_procparams - * @eth_hdr_retained: Specifies if Ethernet header is retained or not @@ -2118,45 +2092,6 @@ struct ipa_gre_hdr_proc_ctx_params { struct ipa_gre_header_remove_procparams hdr_remove_param; }; -/** - * struct ipa_ipogre_header_add_procparams - - * @input_ip_version: Specifies if Input header is IPV4(0) or IPV6(1) - * @output_ip_version: Specifies if template header's outer IP is IPV4(0) - * or IPV6(1) - * @Tunnel_Id: Tunnel id associated with the header. - * @Mux_Id: Specifies mux id associated with the template header - */ -struct ipa_ipogre_header_add_procparams { - uint32_t input_ip_version : 1; - uint32_t output_ip_version : 1; - uint32_t tunnel_id : 4; - uint32_t mux_id : 8; - uint32_t reserved :18; -}; - -/** - * struct ipa_ipogre_header_remove_procparams - - * @hdr_len_remove: Specifies how much (in bytes) of the header needs - * to be removed - * @input_ip_version: Specifies if Input header is IPV4(0) or IPV6(1) - * @Tunnel_Id: Tunnel id associated with the header. - */ -struct ipa_ipogre_header_remove_procparams { - uint32_t hdr_len_remove : 8; - uint32_t input_ip_version : 1; - uint32_t tunnel_id : 4; - uint32_t reserved :19; -}; - -/** - * struct ipa_ipogre_hdr_proc_ctx_params - - * @hdr_add_param: parameters for header add - * @hdr_remove_param: parameters for header remove - */ -struct ipa_ipogre_hdr_proc_ctx_params { - struct ipa_ipogre_header_add_procparams hdr_add_param; - struct ipa_ipogre_header_remove_procparams hdr_remove_param; -}; /** * struct ipa_eth_II_to_eth_II_ex_procparams - * @input_ethhdr_negative_offset: Specifies where the ethernet hdr offset is @@ -2219,7 +2154,6 @@ struct ipa_hdr_proc_ctx_add { struct ipa_eth_II_to_eth_II_ex_procparams generic_params; struct ipa_wwan_to_eth_II_ex_procparams generic_params_v2; struct ipa_gre_hdr_proc_ctx_params gre_params; - struct ipa_ipogre_hdr_proc_ctx_params ipogre_params; }; #define IPA_L2TP_HDR_PROC_SUPPORT @@ -4330,10 +4264,6 @@ struct ipa_ioc_dscp_pcp_map_info { IPA_IOCTL_QUERY_TUNNEL_FEATURE, \ uint8_t) -#define IPA_IOC_ADD_IPoGRE_MAPPING _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ADD_IPOGRE_MAPPING, \ - struct ipa_ioc_ipogre_info) - /* * unique magic number of the Tethering bridge ioctls */ diff --git a/include/uapi/linux/sched.h b/include/uapi/linux/sched.h index 4a0217832464..25b4fa00bad1 100644 --- a/include/uapi/linux/sched.h +++ b/include/uapi/linux/sched.h @@ -33,48 +33,31 @@ #define CLONE_NEWNET 0x40000000 /* New network namespace */ #define CLONE_IO 0x80000000 /* Clone io context */ -/* Flags for the clone3() syscall. */ -#define CLONE_CLEAR_SIGHAND 0x100000000ULL /* Clear any signal handler and reset to SIG_DFL. */ - #ifndef __ASSEMBLY__ /** * struct clone_args - arguments for the clone3 syscall - * @flags: Flags for the new process as listed above. - * All flags are valid except for CSIGNAL and - * CLONE_DETACHED. - * @pidfd: If CLONE_PIDFD is set, a pidfd will be - * returned in this argument. - * @child_tid: If CLONE_CHILD_SETTID is set, the TID of the - * child process will be returned in the child's - * memory. - * @parent_tid: If CLONE_PARENT_SETTID is set, the TID of - * the child process will be returned in the - * parent's memory. - * @exit_signal: The exit_signal the parent process will be - * sent when the child exits. - * @stack: Specify the location of the stack for the - * child process. - * Note, @stack is expected to point to the - * lowest address. The stack direction will be - * determined by the kernel and set up - * appropriately based on @stack_size. - * @stack_size: The size of the stack for the child process. - * @tls: If CLONE_SETTLS is set, the tls descriptor - * is set to tls. - * @set_tid: Pointer to an array of type *pid_t. The size - * of the array is defined using @set_tid_size. - * This array is used to select PIDs/TIDs for - * newly created processes. The first element in - * this defines the PID in the most nested PID - * namespace. Each additional element in the array - * defines the PID in the parent PID namespace of - * the original PID namespace. If the array has - * less entries than the number of currently - * nested PID namespaces only the PIDs in the - * corresponding namespaces are set. - * @set_tid_size: This defines the size of the array referenced - * in @set_tid. This cannot be larger than the - * kernel's limit of nested PID namespaces. + * @flags: Flags for the new process as listed above. + * All flags are valid except for CSIGNAL and + * CLONE_DETACHED. + * @pidfd: If CLONE_PIDFD is set, a pidfd will be + * returned in this argument. + * @child_tid: If CLONE_CHILD_SETTID is set, the TID of the + * child process will be returned in the child's + * memory. + * @parent_tid: If CLONE_PARENT_SETTID is set, the TID of + * the child process will be returned in the + * parent's memory. + * @exit_signal: The exit_signal the parent process will be + * sent when the child exits. + * @stack: Specify the location of the stack for the + * child process. + * Note, @stack is expected to point to the + * lowest address. The stack direction will be + * determined by the kernel and set up + * appropriately based on @stack_size. + * @stack_size: The size of the stack for the child process. + * @tls: If CLONE_SETTLS is set, the tls descriptor + * is set to tls. * * The structure is versioned by size and thus extensible. * New struct members must go at the end of the struct and @@ -89,13 +72,10 @@ struct clone_args { __aligned_u64 stack; __aligned_u64 stack_size; __aligned_u64 tls; - __aligned_u64 set_tid; - __aligned_u64 set_tid_size; }; #endif #define CLONE_ARGS_SIZE_VER0 64 /* sizeof first published struct */ -#define CLONE_ARGS_SIZE_VER1 80 /* sizeof second published struct */ /* * Scheduling policies diff --git a/include/uapi/linux/seccomp.h b/include/uapi/linux/seccomp.h index df1f4711d0b7..b5f901af79f0 100644 --- a/include/uapi/linux/seccomp.h +++ b/include/uapi/linux/seccomp.h @@ -76,35 +76,6 @@ struct seccomp_notif { struct seccomp_data data; }; -/* - * Valid flags for struct seccomp_notif_resp - * - * Note, the SECCOMP_USER_NOTIF_FLAG_CONTINUE flag must be used with caution! - * If set by the process supervising the syscalls of another process the - * syscall will continue. This is problematic because of an inherent TOCTOU. - * An attacker can exploit the time while the supervised process is waiting on - * a response from the supervising process to rewrite syscall arguments which - * are passed as pointers of the intercepted syscall. - * It should be absolutely clear that this means that the seccomp notifier - * _cannot_ be used to implement a security policy! It should only ever be used - * in scenarios where a more privileged process supervises the syscalls of a - * lesser privileged process to get around kernel-enforced security - * restrictions when the privileged process deems this safe. In other words, - * in order to continue a syscall the supervising process should be sure that - * another security mechanism or the kernel itself will sufficiently block - * syscalls if arguments are rewritten to something unsafe. - * - * Similar precautions should be applied when stacking SECCOMP_RET_USER_NOTIF - * or SECCOMP_RET_TRACE. For SECCOMP_RET_USER_NOTIF filters acting on the - * same syscall, the most recently added filter takes precedence. This means - * that the new SECCOMP_RET_USER_NOTIF filter can override any - * SECCOMP_IOCTL_NOTIF_SEND from earlier filters, essentially allowing all - * such filtered syscalls to be executed by sending the response - * SECCOMP_USER_NOTIF_FLAG_CONTINUE. Note that SECCOMP_RET_TRACE can equally - * be overriden by SECCOMP_USER_NOTIF_FLAG_CONTINUE. - */ -#define SECCOMP_USER_NOTIF_FLAG_CONTINUE BIT(0) - struct seccomp_notif_resp { __u64 id; __s64 val; diff --git a/include/uapi/linux/usb/video.h b/include/uapi/linux/usb/video.h index c79b6049d9d7..c58854fb7d94 100644 --- a/include/uapi/linux/usb/video.h +++ b/include/uapi/linux/usb/video.h @@ -597,63 +597,5 @@ struct UVC_FRAME_MJPEG(n) { \ __le32 dwFrameInterval[n]; \ } __attribute__ ((packed)) -/* Frame Based Payload - 3.1.1. Frame Based Video Format Descriptor */ -struct uvc_format_framebased { - __u8 bLength; - __u8 bDescriptorType; - __u8 bDescriptorSubType; - __u8 bFormatIndex; - __u8 bNumFrameDescriptors; - __u8 guidFormat[16]; - __u8 bBitsPerPixel; - __u8 bDefaultFrameIndex; - __u8 bAspectRatioX; - __u8 bAspectRatioY; - __u8 bmInterfaceFlags; - __u8 bCopyProtect; - __u8 bVariableSize; -} __attribute__((__packed__)); - -#define UVC_DT_FORMAT_FRAMEBASED_SIZE 28 - -/* Frame Based Payload - 3.1.2. Frame Based Video Frame Descriptor */ -struct uvc_frame_framebased { - __u8 bLength; - __u8 bDescriptorType; - __u8 bDescriptorSubType; - __u8 bFrameIndex; - __u8 bmCapabilities; - __u16 wWidth; - __u16 wHeight; - __u32 dwMinBitRate; - __u32 dwMaxBitRate; - __u32 dwDefaultFrameInterval; - __u8 bFrameIntervalType; - __u32 dwBytesPerLine; - __u32 dwFrameInterval[]; -} __attribute__((__packed__)); - -#define UVC_DT_FRAME_FRAMEBASED_SIZE(n) (26+4*(n)) - -#define UVC_FRAME_FRAMEBASED(n) \ - uvc_frame_framebased_##n - -#define DECLARE_UVC_FRAME_FRAMEBASED(n) \ - struct UVC_FRAME_FRAMEBASED(n) { \ - __u8 bLength; \ - __u8 bDescriptorType; \ - __u8 bDescriptorSubType; \ - __u8 bFrameIndex; \ - __u8 bmCapabilities; \ - __u16 wWidth; \ - __u16 wHeight; \ - __u32 dwMinBitRate; \ - __u32 dwMaxBitRate; \ - __u32 dwDefaultFrameInterval; \ - __u8 bFrameIntervalType; \ - __u32 dwBytesPerLine; \ - __u32 dwFrameInterval[n]; \ - } __attribute__ ((packed)) - #endif /* __LINUX_USB_VIDEO_H */ diff --git a/include/uapi/linux/virtio_fs.h b/include/uapi/linux/virtio_fs.h index 2f64abce781f..b02eb2ac3d99 100644 --- a/include/uapi/linux/virtio_fs.h +++ b/include/uapi/linux/virtio_fs.h @@ -16,7 +16,4 @@ struct virtio_fs_config { __u32 num_request_queues; } __attribute__((packed)); -/* For the id field in virtio_pci_shm_cap */ -#define VIRTIO_FS_SHMCAP_ID_CACHE 0 - #endif /* _UAPI_LINUX_VIRTIO_FS_H */ diff --git a/init/Kconfig b/init/Kconfig index 3fe1fd2b9625..878d74d31836 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -44,18 +44,6 @@ config CLANG_VERSION int default $(shell,$(srctree)/scripts/clang-version.sh $(CC)) -config AS_IS_GNU - def_bool $(success,test "$(as-name)" = GNU) - -config AS_IS_LLVM - def_bool $(success,test "$(as-name)" = LLVM) - -config AS_VERSION - int - # Use clang version if this is the integrated assembler - default CLANG_VERSION if AS_IS_LLVM - default $(as-version) - config CC_CAN_LINK bool default $(success,$(srctree)/scripts/cc-can-link.sh $(CC) $(CLANG_FLAGS) $(USERCFLAGS) $(USERLDFLAGS) $(m64-flag)) if 64BIT @@ -1698,7 +1686,6 @@ config BPF_SYSCALL select BPF select IRQ_WORK select TASKS_TRACE_RCU - select NET_SOCK_MSG if INET default n help Enable the bpf() system call that allows to manipulate eBPF diff --git a/init/init_task.c b/init/init_task.c index b27ceec394d7..afaea5d7cb8a 100644 --- a/init/init_task.c +++ b/init/init_task.c @@ -193,9 +193,6 @@ struct task_struct init_task #ifdef CONFIG_SECURITY .security = NULL, #endif -#ifdef CONFIG_SECCOMP_FILTER - .seccomp = { .filter_count = ATOMIC_INIT(0) }, -#endif }; EXPORT_SYMBOL(init_task); diff --git a/init/main.c b/init/main.c index cb6c59db4188..ea899e9d7743 100644 --- a/init/main.c +++ b/init/main.c @@ -39,7 +39,6 @@ #include #include #include -#include #include #include #include @@ -558,7 +557,6 @@ static void __init mm_init(void) */ page_ext_init_flatmem(); init_debug_pagealloc(); - kfence_alloc_pool(); report_meminit(); mem_init(); /* page_owner must be initialized after buddy is ready */ @@ -625,9 +623,6 @@ asmlinkage __visible void __init start_kernel(void) parse_args("Setting init args", after_dashes, NULL, 0, -1, -1, NULL, set_init_arg); - /* Architectural and non-timekeeping rng init, before allocator init */ - random_init_early(command_line); - /* * These use large bootmem allocations and must precede * kmem_cache_init() @@ -692,11 +687,14 @@ asmlinkage __visible void __init start_kernel(void) timekeeping_init(); time_init(); - /* This must be after timekeeping is initialized */ - random_init(); - - /* These make use of the fully initialized rng */ - kfence_init(); + /* + * For best initial stack canary entropy, prepare it after: + * - setup_arch() for any UEFI RNG entropy and boot cmdline access + * - timekeeping_init() for ktime entropy used in random_init() + * - time_init() for making random_get_entropy() work on some platforms + * - random_init() to initialize the RNG from from early entropy sources + */ + random_init(command_line); boot_init_stack_canary(); perf_event_init(); diff --git a/ipc/ipc_sysctl.c b/ipc/ipc_sysctl.c index 3f312bf2b116..d1b8644bfb88 100644 --- a/ipc/ipc_sysctl.c +++ b/ipc/ipc_sysctl.c @@ -85,7 +85,7 @@ static int proc_ipc_auto_msgmni(struct ctl_table *table, int write, } static int proc_ipc_sem_dointvec(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret, semmni; struct ipc_namespace *ns = current->nsproxy->ipc_ns; diff --git a/kernel/bpf/Makefile b/kernel/bpf/Makefile index bfdc63dc74db..c1b9f71ee6aa 100644 --- a/kernel/bpf/Makefile +++ b/kernel/bpf/Makefile @@ -36,6 +36,3 @@ obj-$(CONFIG_BPF_SYSCALL) += bpf_struct_ops.o obj-${CONFIG_BPF_LSM} += bpf_lsm.o endif obj-$(CONFIG_BPF_PRELOAD) += preload/ -ifeq ($(CONFIG_FUSE_BPF),y) -obj-$(CONFIG_BPF_SYSCALL) += bpf_fuse.o -endif diff --git a/kernel/bpf/bpf_fuse.c b/kernel/bpf/bpf_fuse.c deleted file mode 100644 index 00738c84b76e..000000000000 --- a/kernel/bpf/bpf_fuse.c +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2021 Google LLC - -#include -#include - -static const struct bpf_func_proto * -fuse_prog_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) -{ - switch (func_id) { - case BPF_FUNC_trace_printk: - return bpf_get_trace_printk_proto(); - - case BPF_FUNC_get_current_uid_gid: - return &bpf_get_current_uid_gid_proto; - - case BPF_FUNC_get_current_pid_tgid: - return &bpf_get_current_pid_tgid_proto; - - case BPF_FUNC_map_lookup_elem: - return &bpf_map_lookup_elem_proto; - - case BPF_FUNC_map_update_elem: - return &bpf_map_update_elem_proto; - - default: - pr_debug("Invalid fuse bpf func %d\n", func_id); - return NULL; - } -} - -static bool fuse_prog_is_valid_access(int off, int size, - enum bpf_access_type type, - const struct bpf_prog *prog, - struct bpf_insn_access_aux *info) -{ - int i; - - if (off < 0 || off > offsetofend(struct fuse_bpf_args, out_args)) - return false; - - /* TODO This is garbage. Do it properly */ - for (i = 0; i < 5; i++) { - if (off == offsetof(struct fuse_bpf_args, in_args[i].value)) { - info->reg_type = PTR_TO_RDONLY_BUF; - info->ctx_field_size = 256; - if (type != BPF_READ) - return false; - return true; - } - } - for (i = 0; i < 3; i++) { - if (off == offsetof(struct fuse_bpf_args, out_args[i].value)) { - info->reg_type = PTR_TO_RDWR_BUF; - info->ctx_field_size = 256; - return true; - } - } - if (type != BPF_READ) - return false; - - return true; -} - -const struct bpf_verifier_ops fuse_verifier_ops = { - .get_func_proto = fuse_prog_func_proto, - .is_valid_access = fuse_prog_is_valid_access, -}; - -const struct bpf_prog_ops fuse_prog_ops = { -}; - diff --git a/kernel/bpf/btf.c b/kernel/bpf/btf.c index face6bda1c93..61759369d7de 100644 --- a/kernel/bpf/btf.c +++ b/kernel/bpf/btf.c @@ -3,7 +3,6 @@ #include #include -#include #include #include #include diff --git a/kernel/exit.c b/kernel/exit.c index d5d584cd79ce..206ea9f96f7b 100644 --- a/kernel/exit.c +++ b/kernel/exit.c @@ -274,7 +274,6 @@ repeat: } write_unlock_irq(&tasklist_lock); - seccomp_filter_release(p); release_thread(p); put_task_struct_rcu_user(p); @@ -1778,30 +1777,6 @@ Efault: } #endif -/** - * thread_group_exited - check that a thread group has exited - * @pid: tgid of thread group to be checked. - * - * Test if the thread group represented by tgid has exited (all - * threads are zombies, dead or completely gone). - * - * Return: true if the thread group has exited. false otherwise. - */ -bool thread_group_exited(struct pid *pid) -{ - struct task_struct *task; - bool exited; - - rcu_read_lock(); - task = pid_task(pid, PIDTYPE_PID); - exited = !task || - (READ_ONCE(task->exit_state) && thread_group_empty(task)); - rcu_read_unlock(); - - return exited; -} -EXPORT_SYMBOL(thread_group_exited); - __weak void abort(void) { BUG(); diff --git a/kernel/fork.c b/kernel/fork.c index 3b98f44b8799..1ebe3dff3ad0 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -474,6 +474,7 @@ void free_task(struct task_struct *tsk) #endif rt_mutex_debug_task_free(tsk); ftrace_graph_exit_task(tsk); + put_seccomp_filter(tsk); arch_release_task_struct(tsk); if (tsk->flags & PF_KTHREAD) free_kthread_struct(tsk); @@ -1540,11 +1541,6 @@ static int copy_sighand(unsigned long clone_flags, struct task_struct *tsk) spin_lock_irq(¤t->sighand->siglock); memcpy(sig->action, current->sighand->action, sizeof(sig->action)); spin_unlock_irq(¤t->sighand->siglock); - - /* Reset all signal handler not set to SIG_IGN to SIG_DFL. */ - if (clone_flags & CLONE_CLEAR_SIGHAND) - flush_signal_handlers(tsk, 0); - return 0; } @@ -1748,18 +1744,22 @@ static void pidfd_show_fdinfo(struct seq_file *m, struct file *f) */ static __poll_t pidfd_poll(struct file *file, struct poll_table_struct *pts) { + struct task_struct *task; struct pid *pid = file->private_data; __poll_t poll_flags = 0; poll_wait(file, &pid->wait_pidfd, pts); + rcu_read_lock(); + task = pid_task(pid, PIDTYPE_PID); /* * Inform pollers only when the whole thread group exits. * If the thread group leader exits before all other threads in the * group, then poll(2) should block, similar to the wait(2) family. */ - if (thread_group_exited(pid)) + if (!task || (task->exit_state && thread_group_empty(task))) poll_flags = EPOLLIN | EPOLLRDNORM; + rcu_read_unlock(); return poll_flags; } @@ -2166,8 +2166,7 @@ static __latent_entropy struct task_struct *copy_process( stackleak_task_init(p); if (pid != &init_struct_pid) { - pid = alloc_pid(p->nsproxy->pid_ns_for_children, args->set_tid, - args->set_tid_size); + pid = alloc_pid(p->nsproxy->pid_ns_for_children); if (IS_ERR(pid)) { retval = PTR_ERR(pid); goto bad_fork_cleanup_thread; @@ -2665,7 +2664,6 @@ noinline static int copy_clone_args_from_user(struct kernel_clone_args *kargs, { int err; struct clone_args args; - pid_t *kset_tid = kargs->set_tid; if (unlikely(usize > PAGE_SIZE)) return -E2BIG; @@ -2676,15 +2674,6 @@ noinline static int copy_clone_args_from_user(struct kernel_clone_args *kargs, if (err) return err; - if (unlikely(args.set_tid_size > MAX_PID_NS_LEVEL)) - return -EINVAL; - - if (unlikely(!args.set_tid && args.set_tid_size > 0)) - return -EINVAL; - - if (unlikely(args.set_tid && args.set_tid_size == 0)) - return -EINVAL; - /* * Verify that higher 32bits of exit_signal are unset and that * it is a valid signal @@ -2702,16 +2691,8 @@ noinline static int copy_clone_args_from_user(struct kernel_clone_args *kargs, .stack = args.stack, .stack_size = args.stack_size, .tls = args.tls, - .set_tid_size = args.set_tid_size, }; - if (args.set_tid && - copy_from_user(kset_tid, u64_to_user_ptr(args.set_tid), - (kargs->set_tid_size * sizeof(pid_t)))) - return -EFAULT; - - kargs->set_tid = kset_tid; - return 0; } @@ -2745,8 +2726,11 @@ static inline bool clone3_stack_valid(struct kernel_clone_args *kargs) static bool clone3_args_valid(struct kernel_clone_args *kargs) { - /* Verify that no unknown flags are passed along. */ - if (kargs->flags & ~(CLONE_LEGACY_FLAGS | CLONE_CLEAR_SIGHAND)) + /* + * All lower bits of the flag word are taken. + * Verify that no other unknown flags are passed along. + */ + if (kargs->flags & ~CLONE_LEGACY_FLAGS) return false; /* @@ -2756,10 +2740,6 @@ static bool clone3_args_valid(struct kernel_clone_args *kargs) if (kargs->flags & (CLONE_DETACHED | CSIGNAL)) return false; - if ((kargs->flags & (CLONE_SIGHAND | CLONE_CLEAR_SIGHAND)) == - (CLONE_SIGHAND | CLONE_CLEAR_SIGHAND)) - return false; - if ((kargs->flags & (CLONE_THREAD | CLONE_PARENT)) && kargs->exit_signal) return false; @@ -2786,9 +2766,6 @@ SYSCALL_DEFINE2(clone3, struct clone_args __user *, uargs, size_t, size) int err; struct kernel_clone_args kargs; - pid_t set_tid[MAX_PID_NS_LEVEL]; - - kargs.set_tid = set_tid; err = copy_clone_args_from_user(&kargs, uargs, size); if (err) @@ -3113,7 +3090,7 @@ int unshare_files(struct files_struct **displaced) } int sysctl_max_threads(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table t; int ret; diff --git a/kernel/hung_task.c b/kernel/hung_task.c index 4f77a49c69cc..313fc190f265 100644 --- a/kernel/hung_task.c +++ b/kernel/hung_task.c @@ -231,7 +231,8 @@ static long hung_timeout_jiffies(unsigned long last_checked, * Process updating of timeout sysctl */ int proc_dohung_task_timeout_secs(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { int ret; diff --git a/kernel/locking/rtmutex.c b/kernel/locking/rtmutex.c index 7a68ab2c5851..7c727c4944e6 100644 --- a/kernel/locking/rtmutex.c +++ b/kernel/locking/rtmutex.c @@ -1063,26 +1063,20 @@ static void mark_wakeup_next_waiter(struct wake_q_head *wake_q, * * Must be called with lock->wait_lock held and interrupts disabled. I must * have just failed to try_to_take_rt_mutex(). - * - * When invoked from rt_mutex_start_proxy_lock() waiter::task != current ! */ static void remove_waiter(struct rt_mutex *lock, struct rt_mutex_waiter *waiter) { bool is_top_waiter = (waiter == rt_mutex_top_waiter(lock)); struct task_struct *owner = rt_mutex_owner(lock); - struct task_struct *waiter_task = waiter->task; struct rt_mutex *next_lock; lockdep_assert_held(&lock->wait_lock); - if (!waiter_task) /* never enqueued */ - return; - - raw_spin_lock(&waiter_task->pi_lock); + raw_spin_lock(¤t->pi_lock); rt_mutex_dequeue(lock, waiter); - waiter_task->pi_blocked_on = NULL; - raw_spin_unlock(&waiter_task->pi_lock); + current->pi_blocked_on = NULL; + raw_spin_unlock(¤t->pi_lock); /* * Only update priority if the waiter was the highest priority @@ -1118,7 +1112,7 @@ static void remove_waiter(struct rt_mutex *lock, raw_spin_unlock_irq(&lock->wait_lock); rt_mutex_adjust_prio_chain(owner, RT_MUTEX_MIN_CHAINWALK, lock, - next_lock, NULL, waiter_task); + next_lock, NULL, current); raw_spin_lock_irq(&lock->wait_lock); } @@ -1808,7 +1802,7 @@ int rt_mutex_start_proxy_lock(struct rt_mutex *lock, raw_spin_lock_irq(&lock->wait_lock); ret = __rt_mutex_start_proxy_lock(lock, waiter, task); - if (unlikely(ret < 0)) + if (unlikely(ret)) remove_waiter(lock, waiter); raw_spin_unlock_irq(&lock->wait_lock); diff --git a/kernel/pid.c b/kernel/pid.c index b7adaef4889b..289d0b12ab86 100644 --- a/kernel/pid.c +++ b/kernel/pid.c @@ -157,8 +157,7 @@ void free_pid(struct pid *pid) call_rcu(&pid->rcu, delayed_put_pid); } -struct pid *alloc_pid(struct pid_namespace *ns, pid_t *set_tid, - size_t set_tid_size) +struct pid *alloc_pid(struct pid_namespace *ns) { struct pid *pid; enum pid_type type; @@ -167,17 +166,6 @@ struct pid *alloc_pid(struct pid_namespace *ns, pid_t *set_tid, struct upid *upid; int retval = -ENOMEM; - /* - * set_tid_size contains the size of the set_tid array. Starting at - * the most nested currently active PID namespace it tells alloc_pid() - * which PID to set for a process in that most nested PID namespace - * up to set_tid_size PID namespaces. It does not have to set the PID - * for a process in all nested PID namespaces but set_tid_size must - * never be greater than the current ns->level + 1. - */ - if (set_tid_size > ns->level + 1) - return ERR_PTR(-EINVAL); - pid = kmem_cache_alloc(ns->pid_cachep, GFP_KERNEL); if (!pid) return ERR_PTR(retval); @@ -186,54 +174,24 @@ struct pid *alloc_pid(struct pid_namespace *ns, pid_t *set_tid, pid->level = ns->level; for (i = ns->level; i >= 0; i--) { - int tid = 0; - - if (set_tid_size) { - tid = set_tid[ns->level - i]; - - retval = -EINVAL; - if (tid < 1 || tid >= pid_max) - goto out_free; - /* - * Also fail if a PID != 1 is requested and - * no PID 1 exists. - */ - if (tid != 1 && !tmp->child_reaper) - goto out_free; - retval = -EPERM; - if (!checkpoint_restore_ns_capable(tmp->user_ns)) - goto out_free; - set_tid_size--; - } + int pid_min = 1; idr_preload(GFP_KERNEL); spin_lock_irq(&pidmap_lock); - if (tid) { - nr = idr_alloc(&tmp->idr, NULL, tid, - tid + 1, GFP_ATOMIC); - /* - * If ENOSPC is returned it means that the PID is - * alreay in use. Return EEXIST in that case. - */ - if (nr == -ENOSPC) - nr = -EEXIST; - } else { - int pid_min = 1; - /* - * init really needs pid 1, but after reaching the - * maximum wrap back to RESERVED_PIDS - */ - if (idr_get_cursor(&tmp->idr) > RESERVED_PIDS) - pid_min = RESERVED_PIDS; + /* + * init really needs pid 1, but after reaching the maximum + * wrap back to RESERVED_PIDS + */ + if (idr_get_cursor(&tmp->idr) > RESERVED_PIDS) + pid_min = RESERVED_PIDS; - /* - * Store a null pointer so find_pid_ns does not find - * a partially initialized PID (see below). - */ - nr = idr_alloc_cyclic(&tmp->idr, NULL, pid_min, - pid_max, GFP_ATOMIC); - } + /* + * Store a null pointer so find_pid_ns does not find + * a partially initialized PID (see below). + */ + nr = idr_alloc_cyclic(&tmp->idr, NULL, pid_min, + pid_max, GFP_ATOMIC); spin_unlock_irq(&pidmap_lock); idr_preload_end(); diff --git a/kernel/pid_namespace.c b/kernel/pid_namespace.c index 78b409b88fbd..ef914bb9b469 100644 --- a/kernel/pid_namespace.c +++ b/kernel/pid_namespace.c @@ -26,6 +26,8 @@ static DEFINE_MUTEX(pid_caches_mutex); static struct kmem_cache *pid_ns_cachep; +/* MAX_PID_NS_LEVEL is needed for limiting size of 'struct pid' */ +#define MAX_PID_NS_LEVEL 32 /* Write once array, filled from the beginning. */ static struct kmem_cache *pid_cache[MAX_PID_NS_LEVEL]; @@ -270,7 +272,7 @@ static int pid_ns_ctl_handler(struct ctl_table *table, int write, struct ctl_table tmp = *table; int ret, next; - if (write && !checkpoint_restore_ns_capable(pid_ns->user_ns)) + if (write && !ns_capable(pid_ns->user_ns, CAP_SYS_ADMIN)) return -EPERM; /* diff --git a/kernel/seccomp.c b/kernel/seccomp.c index 1ec9bdc1e208..b9266df69f60 100644 --- a/kernel/seccomp.c +++ b/kernel/seccomp.c @@ -13,7 +13,6 @@ * Mode 2 allows user-defined system call filters in the form * of Berkeley Packet Filters/Linux Socket Filters. */ -#define pr_fmt(fmt) "seccomp: " fmt #include #include @@ -45,7 +44,6 @@ #include #include #include -#include /* * When SECCOMP_IOCTL_NOTIF_ID_VALID was first introduced, it had the @@ -88,7 +86,6 @@ struct seccomp_knotif { /* The return values, only valid when in SECCOMP_NOTIFY_REPLIED */ int error; long val; - u32 flags; /* Signals when this has entered SECCOMP_NOTIFY_REPLIED */ struct completion ready; @@ -107,68 +104,27 @@ struct seccomp_knotif { * filter->notify_lock. * @next_id: The id of the next request. * @notifications: A list of struct seccomp_knotif elements. + * @wqh: A wait queue for poll. */ struct notification { struct semaphore request; u64 next_id; struct list_head notifications; + wait_queue_head_t wqh; }; -#ifdef SECCOMP_ARCH_NATIVE -/** - * struct action_cache - per-filter cache of seccomp actions per - * arch/syscall pair - * - * @allow_native: A bitmap where each bit represents whether the - * filter will always allow the syscall, for the - * native architecture. - * @allow_compat: A bitmap where each bit represents whether the - * filter will always allow the syscall, for the - * compat architecture. - */ -struct action_cache { - DECLARE_BITMAP(allow_native, SECCOMP_ARCH_NATIVE_NR); -#ifdef SECCOMP_ARCH_COMPAT - DECLARE_BITMAP(allow_compat, SECCOMP_ARCH_COMPAT_NR); -#endif -}; -#else -struct action_cache { }; - -static inline bool seccomp_cache_check_allow(const struct seccomp_filter *sfilter, - const struct seccomp_data *sd) -{ - return false; -} - -static inline void seccomp_cache_prepare(struct seccomp_filter *sfilter) -{ -} -#endif /* SECCOMP_ARCH_NATIVE */ - /** * struct seccomp_filter - container for seccomp BPF programs * - * @refs: Reference count to manage the object lifetime. - * A filter's reference count is incremented for each directly - * attached task, once for the dependent filter, and if - * requested for the user notifier. When @refs reaches zero, - * the filter can be freed. - * @users: A filter's @users count is incremented for each directly - * attached task (filter installation, fork(), thread_sync), - * and once for the dependent filter (tracked in filter->prev). - * When it reaches zero it indicates that no direct or indirect - * users of that filter exist. No new tasks can get associated with - * this filter after reaching 0. The @users count is always smaller - * or equal to @refs. Hence, reaching 0 for @users does not mean - * the filter can be freed. - * @cache: cache of arch/syscall mappings to actions + * @usage: reference count to manage the object lifetime. + * get/put helpers should be used when accessing an instance + * outside of a lifetime-guarded section. In general, this + * is only needed for handling filters shared across tasks. * @log: true if all actions except for SECCOMP_RET_ALLOW should be logged * @prev: points to a previously installed, or inherited, filter * @prog: the BPF program to evaluate * @notif: the struct that holds all notification related information * @notify_lock: A lock for all notification-related accesses. - * @wqh: A wait queue for poll if a notifier is in use. * * seccomp_filter objects are organized in a tree linked via the @prev * pointer. For any task, it appears to be a singly-linked list starting @@ -178,18 +134,15 @@ static inline void seccomp_cache_prepare(struct seccomp_filter *sfilter) * how namespaces work. * * seccomp_filter objects should never be modified after being attached - * to a task_struct (other than @refs). + * to a task_struct (other than @usage). */ struct seccomp_filter { - refcount_t refs; - refcount_t users; + refcount_t usage; bool log; - struct action_cache cache; struct seccomp_filter *prev; struct bpf_prog *prog; struct notification *notif; struct mutex notify_lock; - wait_queue_head_t wqh; }; /* Limit any path through the tree to 256KB worth of instructions. */ @@ -201,10 +154,6 @@ struct seccomp_filter { */ static void populate_seccomp_data(struct seccomp_data *sd) { - /* - * Instead of using current_pt_reg(), we're already doing the work - * to safely fetch "current", so just use "task" everywhere below. - */ struct task_struct *task = current; struct pt_regs *regs = task_pt_regs(task); unsigned long args[6]; @@ -303,52 +252,6 @@ static int seccomp_check_filter(struct sock_filter *filter, unsigned int flen) return 0; } -#ifdef SECCOMP_ARCH_NATIVE -static inline bool seccomp_cache_check_allow_bitmap(const void *bitmap, - size_t bitmap_size, - int syscall_nr) -{ - if (unlikely(syscall_nr < 0 || syscall_nr >= bitmap_size)) - return false; - syscall_nr = array_index_nospec(syscall_nr, bitmap_size); - - return test_bit(syscall_nr, bitmap); -} - -/** - * seccomp_cache_check_allow - lookup seccomp cache - * @sfilter: The seccomp filter - * @sd: The seccomp data to lookup the cache with - * - * Returns true if the seccomp_data is cached and allowed. - */ -static inline bool seccomp_cache_check_allow(const struct seccomp_filter *sfilter, - const struct seccomp_data *sd) -{ - int syscall_nr = sd->nr; - const struct action_cache *cache = &sfilter->cache; - -#ifndef SECCOMP_ARCH_COMPAT - /* A native-only architecture doesn't need to check sd->arch. */ - return seccomp_cache_check_allow_bitmap(cache->allow_native, - SECCOMP_ARCH_NATIVE_NR, - syscall_nr); -#else - if (likely(sd->arch == SECCOMP_ARCH_NATIVE)) - return seccomp_cache_check_allow_bitmap(cache->allow_native, - SECCOMP_ARCH_NATIVE_NR, - syscall_nr); - if (likely(sd->arch == SECCOMP_ARCH_COMPAT)) - return seccomp_cache_check_allow_bitmap(cache->allow_compat, - SECCOMP_ARCH_COMPAT_NR, - syscall_nr); -#endif /* SECCOMP_ARCH_COMPAT */ - - WARN_ON_ONCE(true); - return false; -} -#endif /* SECCOMP_ARCH_NATIVE */ - /** * seccomp_run_filters - evaluates all seccomp filters against @sd * @sd: optional seccomp data to be passed to filters @@ -371,9 +274,6 @@ static u32 seccomp_run_filters(const struct seccomp_data *sd, if (WARN_ON(f == NULL)) return SECCOMP_RET_KILL_PROCESS; - if (seccomp_cache_check_allow(f, sd)) - return SECCOMP_RET_ALLOW; - /* * All filters in the list are evaluated and the lowest BPF return * value always takes priority (ignoring the DATA). @@ -478,59 +378,6 @@ static inline pid_t seccomp_can_sync_threads(void) return 0; } -static inline void seccomp_filter_free(struct seccomp_filter *filter) -{ - if (filter) { - bpf_prog_destroy(filter->prog); - kfree(filter); - } -} - -static void __seccomp_filter_orphan(struct seccomp_filter *orig) -{ - while (orig && refcount_dec_and_test(&orig->users)) { - if (waitqueue_active(&orig->wqh)) - wake_up_poll(&orig->wqh, EPOLLHUP); - orig = orig->prev; - } -} - -static void __put_seccomp_filter(struct seccomp_filter *orig) -{ - /* Clean up single-reference branches iteratively. */ - while (orig && refcount_dec_and_test(&orig->refs)) { - struct seccomp_filter *freeme = orig; - orig = orig->prev; - seccomp_filter_free(freeme); - } -} - -static void __seccomp_filter_release(struct seccomp_filter *orig) -{ - /* Notify about any unused filters in the task's former filter tree. */ - __seccomp_filter_orphan(orig); - /* Finally drop all references to the task's former tree. */ - __put_seccomp_filter(orig); -} - -/** - * seccomp_filter_release - Detach the task from its filter tree, - * drop its reference count, and notify - * about unused filters - * - * This function should only be called when the task is exiting as - * it detaches it from its filter tree. As such, READ_ONCE() and - * barriers are not needed here, as would normally be needed. - */ -void seccomp_filter_release(struct task_struct *tsk) -{ - struct seccomp_filter *orig = tsk->seccomp.filter; - - /* Detach task from its filter tree. */ - tsk->seccomp.filter = NULL; - __seccomp_filter_release(orig); -} - /** * seccomp_sync_threads: sets all threads to use current's filter * @@ -555,19 +402,14 @@ static inline void seccomp_sync_threads(unsigned long flags) /* Get a task reference for the new leaf node. */ get_seccomp_filter(caller); - /* * Drop the task reference to the shared ancestor since * current's path will hold a reference. (This also * allows a put before the assignment.) */ - __seccomp_filter_release(thread->seccomp.filter); - - /* Make our new filter tree visible. */ + put_seccomp_filter(thread); smp_store_release(&thread->seccomp.filter, caller->seccomp.filter); - atomic_set(&thread->seccomp.filter_count, - atomic_read(&caller->seccomp.filter_count)); /* * Don't let an unprivileged task work around @@ -600,12 +442,7 @@ static struct seccomp_filter *seccomp_prepare_filter(struct sock_fprog *fprog) { struct seccomp_filter *sfilter; int ret; - const bool save_orig = -#if defined(CONFIG_CHECKPOINT_RESTORE) || defined(SECCOMP_ARCH_NATIVE) - true; -#else - false; -#endif + const bool save_orig = IS_ENABLED(CONFIG_CHECKPOINT_RESTORE); if (fprog->len == 0 || fprog->len > BPF_MAXINSNS) return ERR_PTR(-EINVAL); @@ -635,9 +472,7 @@ static struct seccomp_filter *seccomp_prepare_filter(struct sock_fprog *fprog) return ERR_PTR(ret); } - refcount_set(&sfilter->refs, 1); - refcount_set(&sfilter->users, 1); - init_waitqueue_head(&sfilter->wqh); + refcount_set(&sfilter->usage, 1); return sfilter; } @@ -670,148 +505,6 @@ out: return filter; } -#ifdef SECCOMP_ARCH_NATIVE -/** - * seccomp_is_const_allow - check if filter is constant allow with given data - * @fprog: The BPF programs - * @sd: The seccomp data to check against, only syscall number and arch - * number are considered constant. - */ -static bool seccomp_is_const_allow(struct sock_fprog_kern *fprog, - struct seccomp_data *sd) -{ - unsigned int reg_value = 0; - unsigned int pc; - bool op_res; - - if (WARN_ON_ONCE(!fprog)) - return false; - - for (pc = 0; pc < fprog->len; pc++) { - struct sock_filter *insn = &fprog->filter[pc]; - u16 code = insn->code; - u32 k = insn->k; - - switch (code) { - case BPF_LD | BPF_W | BPF_ABS: - switch (k) { - case offsetof(struct seccomp_data, nr): - reg_value = sd->nr; - break; - case offsetof(struct seccomp_data, arch): - reg_value = sd->arch; - break; - default: - /* can't optimize (non-constant value load) */ - return false; - } - break; - case BPF_RET | BPF_K: - /* reached return with constant values only, check allow */ - return k == SECCOMP_RET_ALLOW; - case BPF_JMP | BPF_JA: - pc += insn->k; - break; - case BPF_JMP | BPF_JEQ | BPF_K: - case BPF_JMP | BPF_JGE | BPF_K: - case BPF_JMP | BPF_JGT | BPF_K: - case BPF_JMP | BPF_JSET | BPF_K: - switch (BPF_OP(code)) { - case BPF_JEQ: - op_res = reg_value == k; - break; - case BPF_JGE: - op_res = reg_value >= k; - break; - case BPF_JGT: - op_res = reg_value > k; - break; - case BPF_JSET: - op_res = !!(reg_value & k); - break; - default: - /* can't optimize (unknown jump) */ - return false; - } - - pc += op_res ? insn->jt : insn->jf; - break; - case BPF_ALU | BPF_AND | BPF_K: - reg_value &= k; - break; - default: - /* can't optimize (unknown insn) */ - return false; - } - } - - /* ran off the end of the filter?! */ - WARN_ON(1); - return false; -} - -static void seccomp_cache_prepare_bitmap(struct seccomp_filter *sfilter, - void *bitmap, const void *bitmap_prev, - size_t bitmap_size, int arch) -{ - struct sock_fprog_kern *fprog = sfilter->prog->orig_prog; - struct seccomp_data sd; - int nr; - - if (bitmap_prev) { - /* The new filter must be as restrictive as the last. */ - bitmap_copy(bitmap, bitmap_prev, bitmap_size); - } else { - /* Before any filters, all syscalls are always allowed. */ - bitmap_fill(bitmap, bitmap_size); - } - - for (nr = 0; nr < bitmap_size; nr++) { - /* No bitmap change: not a cacheable action. */ - if (!test_bit(nr, bitmap)) - continue; - - sd.nr = nr; - sd.arch = arch; - - /* No bitmap change: continue to always allow. */ - if (seccomp_is_const_allow(fprog, &sd)) - continue; - - /* - * Not a cacheable action: always run filters. - * atomic clear_bit() not needed, filter not visible yet. - */ - __clear_bit(nr, bitmap); - } -} - -/** - * seccomp_cache_prepare - emulate the filter to find cachable syscalls - * @sfilter: The seccomp filter - * - * Returns 0 if successful or -errno if error occurred. - */ -static void seccomp_cache_prepare(struct seccomp_filter *sfilter) -{ - struct action_cache *cache = &sfilter->cache; - const struct action_cache *cache_prev = - sfilter->prev ? &sfilter->prev->cache : NULL; - - seccomp_cache_prepare_bitmap(sfilter, cache->allow_native, - cache_prev ? cache_prev->allow_native : NULL, - SECCOMP_ARCH_NATIVE_NR, - SECCOMP_ARCH_NATIVE); - -#ifdef SECCOMP_ARCH_COMPAT - seccomp_cache_prepare_bitmap(sfilter, cache->allow_compat, - cache_prev ? cache_prev->allow_compat : NULL, - SECCOMP_ARCH_COMPAT_NR, - SECCOMP_ARCH_COMPAT); -#endif /* SECCOMP_ARCH_COMPAT */ -} -#endif /* SECCOMP_ARCH_NATIVE */ - /** * seccomp_attach_filter: validate and attach filter * @flags: flags to change filter behavior @@ -857,9 +550,7 @@ static long seccomp_attach_filter(unsigned int flags, * task reference. */ filter->prev = current->seccomp.filter; - seccomp_cache_prepare(filter); current->seccomp.filter = filter; - atomic_inc(¤t->seccomp.filter_count); /* Now that the new filter is in place, synchronize to all threads. */ if (flags & SECCOMP_FILTER_FLAG_TSYNC) @@ -870,7 +561,7 @@ static long seccomp_attach_filter(unsigned int flags, static void __get_seccomp_filter(struct seccomp_filter *filter) { - refcount_inc(&filter->refs); + refcount_inc(&filter->usage); } /* get_seccomp_filter - increments the reference count of the filter on @tsk */ @@ -880,7 +571,30 @@ void get_seccomp_filter(struct task_struct *tsk) if (!orig) return; __get_seccomp_filter(orig); - refcount_inc(&orig->users); +} + +static inline void seccomp_filter_free(struct seccomp_filter *filter) +{ + if (filter) { + bpf_prog_destroy(filter->prog); + kfree(filter); + } +} + +static void __put_seccomp_filter(struct seccomp_filter *orig) +{ + /* Clean up single-reference branches iteratively. */ + while (orig && refcount_dec_and_test(&orig->usage)) { + struct seccomp_filter *freeme = orig; + orig = orig->prev; + seccomp_filter_free(freeme); + } +} + +/* put_seccomp_filter - decrements the ref count of tsk->seccomp.filter */ +void put_seccomp_filter(struct task_struct *tsk) +{ + __put_seccomp_filter(tsk->seccomp.filter); } static void seccomp_init_siginfo(kernel_siginfo_t *info, int syscall, int reason) @@ -977,20 +691,20 @@ static inline void seccomp_log(unsigned long syscall, long signr, u32 action, */ static const int mode1_syscalls[] = { __NR_seccomp_read, __NR_seccomp_write, __NR_seccomp_exit, __NR_seccomp_sigreturn, - -1, /* negative terminated */ + 0, /* null terminated */ }; static void __secure_computing_strict(int this_syscall) { - const int *allowed_syscalls = mode1_syscalls; + const int *syscall_whitelist = mode1_syscalls; #ifdef CONFIG_COMPAT if (in_compat_syscall()) - allowed_syscalls = get_compat_mode1_syscalls(); + syscall_whitelist = get_compat_mode1_syscalls(); #endif do { - if (*allowed_syscalls == this_syscall) + if (*syscall_whitelist == this_syscall) return; - } while (*++allowed_syscalls != -1); + } while (*++syscall_whitelist); #ifdef SECCOMP_DEBUG dump_stack(); @@ -1029,12 +743,11 @@ static u64 seccomp_next_notify_id(struct seccomp_filter *filter) return filter->notif->next_id++; } -static int seccomp_do_user_notification(int this_syscall, - struct seccomp_filter *match, - const struct seccomp_data *sd) +static void seccomp_do_user_notification(int this_syscall, + struct seccomp_filter *match, + const struct seccomp_data *sd) { int err; - u32 flags = 0; long ret = 0; struct seccomp_knotif n = {}; @@ -1051,7 +764,7 @@ static int seccomp_do_user_notification(int this_syscall, list_add(&n.list, &match->notif->notifications); up(&match->notif->request); - wake_up_poll(&match->wqh, EPOLLIN | EPOLLRDNORM); + wake_up_poll(&match->notif->wqh, EPOLLIN | EPOLLRDNORM); mutex_unlock(&match->notify_lock); /* @@ -1062,7 +775,6 @@ static int seccomp_do_user_notification(int this_syscall, if (err == 0) { ret = n.val; err = n.error; - flags = n.flags; } /* @@ -1079,14 +791,8 @@ static int seccomp_do_user_notification(int this_syscall, list_del(&n.list); out: mutex_unlock(&match->notify_lock); - - /* Userspace requests to continue the syscall. */ - if (flags & SECCOMP_USER_NOTIF_FLAG_CONTINUE) - return 0; - - syscall_set_return_value(current, current_pt_regs(), + syscall_set_return_value(current, task_pt_regs(current), err, ret); - return -1; } static int __seccomp_filter(int this_syscall, const struct seccomp_data *sd, @@ -1117,13 +823,13 @@ static int __seccomp_filter(int this_syscall, const struct seccomp_data *sd, /* Set low-order bits as an errno, capped at MAX_ERRNO. */ if (data > MAX_ERRNO) data = MAX_ERRNO; - syscall_set_return_value(current, current_pt_regs(), + syscall_set_return_value(current, task_pt_regs(current), -data, 0); goto skip; case SECCOMP_RET_TRAP: /* Show the handler the original registers. */ - syscall_rollback(current, current_pt_regs()); + syscall_rollback(current, task_pt_regs(current)); /* Let the filter pass back 16 bits of data. */ seccomp_send_sigsys(this_syscall, data); goto skip; @@ -1136,7 +842,7 @@ static int __seccomp_filter(int this_syscall, const struct seccomp_data *sd, /* ENOSYS these calls if there is no tracer attached. */ if (!ptrace_event_enabled(current, PTRACE_EVENT_SECCOMP)) { syscall_set_return_value(current, - current_pt_regs(), + task_pt_regs(current), -ENOSYS, 0); goto skip; } @@ -1156,7 +862,7 @@ static int __seccomp_filter(int this_syscall, const struct seccomp_data *sd, if (fatal_signal_pending(current)) goto skip; /* Check if the tracer forced the syscall to be skipped. */ - this_syscall = syscall_get_nr(current, current_pt_regs()); + this_syscall = syscall_get_nr(current, task_pt_regs(current)); if (this_syscall < 0) goto skip; @@ -1172,10 +878,8 @@ static int __seccomp_filter(int this_syscall, const struct seccomp_data *sd, return 0; case SECCOMP_RET_USER_NOTIF: - if (seccomp_do_user_notification(this_syscall, match, sd)) - goto skip; - - return 0; + seccomp_do_user_notification(this_syscall, match, sd); + goto skip; case SECCOMP_RET_LOG: seccomp_log(this_syscall, 0, action, true); @@ -1195,20 +899,20 @@ static int __seccomp_filter(int this_syscall, const struct seccomp_data *sd, current->seccomp.mode = SECCOMP_MODE_DEAD; seccomp_log(this_syscall, SIGSYS, action, true); /* Dump core only if this is the last remaining thread. */ - if (action != SECCOMP_RET_KILL_THREAD || + if (action == SECCOMP_RET_KILL_PROCESS || get_nr_threads(current) == 1) { kernel_siginfo_t info; /* Show the original registers in the dump. */ - syscall_rollback(current, current_pt_regs()); + syscall_rollback(current, task_pt_regs(current)); /* Trigger a manual coredump since do_exit skips it. */ seccomp_init_siginfo(&info, this_syscall, data); do_coredump(&info); } - if (action == SECCOMP_RET_KILL_THREAD) - do_exit(SIGSYS); - else + if (action == SECCOMP_RET_KILL_PROCESS) do_group_exit(SIGSYS); + else + do_exit(SIGSYS); } unreachable(); @@ -1237,7 +941,7 @@ int __secure_computing(const struct seccomp_data *sd) return 0; this_syscall = sd ? sd->nr : - syscall_get_nr(current, current_pt_regs()); + syscall_get_nr(current, task_pt_regs(current)); switch (mode) { case SECCOMP_MODE_STRICT: @@ -1291,18 +995,13 @@ out: } #ifdef CONFIG_SECCOMP_FILTER -static void seccomp_notify_free(struct seccomp_filter *filter) -{ - kfree(filter->notif); - filter->notif = NULL; -} - -static void seccomp_notify_detach(struct seccomp_filter *filter) +static int seccomp_notify_release(struct inode *inode, struct file *file) { + struct seccomp_filter *filter = file->private_data; struct seccomp_knotif *knotif; if (!filter) - return; + return 0; mutex_lock(&filter->notify_lock); @@ -1321,36 +1020,13 @@ static void seccomp_notify_detach(struct seccomp_filter *filter) complete(&knotif->ready); } - seccomp_notify_free(filter); + kfree(filter->notif); + filter->notif = NULL; mutex_unlock(&filter->notify_lock); -} - -static int seccomp_notify_release(struct inode *inode, struct file *file) -{ - struct seccomp_filter *filter = file->private_data; - - seccomp_notify_detach(filter); __put_seccomp_filter(filter); return 0; } -/* must be called with notif_lock held */ -static inline struct seccomp_knotif * -find_notification(struct seccomp_filter *filter, u64 id) -{ - struct seccomp_knotif *cur; - - lockdep_assert_held(&filter->notify_lock); - - list_for_each_entry(cur, &filter->notif->notifications, list) { - if (cur->id == id) - return cur; - } - - return NULL; -} - - static long seccomp_notify_recv(struct seccomp_filter *filter, void __user *buf) { @@ -1394,7 +1070,7 @@ static long seccomp_notify_recv(struct seccomp_filter *filter, unotif.data = *(knotif->data); knotif->state = SECCOMP_NOTIFY_SENT; - wake_up_poll(&filter->wqh, EPOLLOUT | EPOLLWRNORM); + wake_up_poll(&filter->notif->wqh, EPOLLOUT | EPOLLWRNORM); ret = 0; out: mutex_unlock(&filter->notify_lock); @@ -1408,8 +1084,15 @@ out: * may have died when we released the lock, so we need to make * sure it's still around. */ + knotif = NULL; mutex_lock(&filter->notify_lock); - knotif = find_notification(filter, unotif.id); + list_for_each_entry(cur, &filter->notif->notifications, list) { + if (cur->id == unotif.id) { + knotif = cur; + break; + } + } + if (knotif) { knotif->state = SECCOMP_NOTIFY_INIT; up(&filter->notif->request); @@ -1424,24 +1107,26 @@ static long seccomp_notify_send(struct seccomp_filter *filter, void __user *buf) { struct seccomp_notif_resp resp = {}; - struct seccomp_knotif *knotif; + struct seccomp_knotif *knotif = NULL, *cur; long ret; if (copy_from_user(&resp, buf, sizeof(resp))) return -EFAULT; - if (resp.flags & ~SECCOMP_USER_NOTIF_FLAG_CONTINUE) - return -EINVAL; - - if ((resp.flags & SECCOMP_USER_NOTIF_FLAG_CONTINUE) && - (resp.error || resp.val)) + if (resp.flags) return -EINVAL; ret = mutex_lock_interruptible(&filter->notify_lock); if (ret < 0) return ret; - knotif = find_notification(filter, resp.id); + list_for_each_entry(cur, &filter->notif->notifications, list) { + if (cur->id == resp.id) { + knotif = cur; + break; + } + } + if (!knotif) { ret = -ENOENT; goto out; @@ -1457,7 +1142,6 @@ static long seccomp_notify_send(struct seccomp_filter *filter, knotif->state = SECCOMP_NOTIFY_REPLIED; knotif->error = resp.error; knotif->val = resp.val; - knotif->flags = resp.flags; complete(&knotif->ready); out: mutex_unlock(&filter->notify_lock); @@ -1467,7 +1151,7 @@ out: static long seccomp_notify_id_valid(struct seccomp_filter *filter, void __user *buf) { - struct seccomp_knotif *knotif; + struct seccomp_knotif *knotif = NULL; u64 id; long ret; @@ -1478,12 +1162,16 @@ static long seccomp_notify_id_valid(struct seccomp_filter *filter, if (ret < 0) return ret; - knotif = find_notification(filter, id); - if (knotif && knotif->state == SECCOMP_NOTIFY_SENT) - ret = 0; - else - ret = -ENOENT; + ret = -ENOENT; + list_for_each_entry(knotif, &filter->notif->notifications, list) { + if (knotif->id == id) { + if (knotif->state == SECCOMP_NOTIFY_SENT) + ret = 0; + goto out; + } + } +out: mutex_unlock(&filter->notify_lock); return ret; } @@ -1514,7 +1202,7 @@ static __poll_t seccomp_notify_poll(struct file *file, __poll_t ret = 0; struct seccomp_knotif *cur; - poll_wait(file, &filter->wqh, poll_tab); + poll_wait(file, &filter->notif->wqh, poll_tab); if (mutex_lock_interruptible(&filter->notify_lock) < 0) return EPOLLERR; @@ -1530,9 +1218,6 @@ static __poll_t seccomp_notify_poll(struct file *file, mutex_unlock(&filter->notify_lock); - if (refcount_read(&filter->users) == 0) - ret |= EPOLLHUP; - return ret; } @@ -1555,6 +1240,7 @@ static struct file *init_listener(struct seccomp_filter *filter) sema_init(&filter->notif->request, 0); filter->notif->next_id = get_random_u64(); INIT_LIST_HEAD(&filter->notif->notifications); + init_waitqueue_head(&filter->notif->wqh); ret = anon_inode_getfile("seccomp notify", &seccomp_notify_ops, filter, O_RDWR); @@ -1566,7 +1252,7 @@ static struct file *init_listener(struct seccomp_filter *filter) out_notif: if (IS_ERR(ret)) - seccomp_notify_free(filter); + kfree(filter->notif); out: return ret; } @@ -1687,7 +1373,6 @@ out_put_fd: listener_f->private_data = NULL; fput(listener_f); put_unused_fd(listener); - seccomp_notify_detach(prepared); } else { fd_install(listener, listener_f); ret = listener; @@ -2035,7 +1720,7 @@ static bool seccomp_actions_logged_from_names(u32 *actions_logged, char *names) return true; } -static int read_actions_logged(struct ctl_table *ro_table, void *buffer, +static int read_actions_logged(struct ctl_table *ro_table, void __user *buffer, size_t *lenp, loff_t *ppos) { char names[sizeof(seccomp_actions_avail)]; @@ -2053,7 +1738,7 @@ static int read_actions_logged(struct ctl_table *ro_table, void *buffer, return proc_dostring(&table, 0, buffer, lenp, ppos); } -static int write_actions_logged(struct ctl_table *ro_table, void *buffer, +static int write_actions_logged(struct ctl_table *ro_table, void __user *buffer, size_t *lenp, loff_t *ppos, u32 *actions_logged) { char names[sizeof(seccomp_actions_avail)]; @@ -2161,7 +1846,7 @@ static int __init seccomp_sysctl_init(void) hdr = register_sysctl_paths(seccomp_sysctl_path, seccomp_sysctl_table); if (!hdr) - pr_warn("sysctl registration failed\n"); + pr_warn("seccomp: sysctl registration failed\n"); else kmemleak_not_leak(hdr); diff --git a/kernel/stackleak.c b/kernel/stackleak.c index b54bf2770bce..b193a59fc05b 100644 --- a/kernel/stackleak.c +++ b/kernel/stackleak.c @@ -20,7 +20,7 @@ static DEFINE_STATIC_KEY_FALSE(stack_erasing_bypass); int stack_erasing_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret = 0; int state = !static_branch_unlikely(&stack_erasing_bypass); diff --git a/kernel/sys.c b/kernel/sys.c index 3ed05f046c92..fa3f48a51aa9 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -2005,15 +2005,12 @@ static int prctl_set_mm_map(int opt, const void __user *addr, unsigned long data if (prctl_map.exe_fd != (u32)-1) { /* - * Check if the current user is checkpoint/restore capable. - * At the time of this writing, it checks for CAP_SYS_ADMIN - * or CAP_CHECKPOINT_RESTORE. - * Note that a user with access to ptrace can masquerade an - * arbitrary program as any executable, even setuid ones. - * This may have implications in the tomoyo subsystem. + * Make sure the caller has the rights to + * change /proc/pid/exe link: only local sys admin should + * be allowed to. */ - if (!checkpoint_restore_ns_capable(current_user_ns())) - return -EPERM; + if (!ns_capable(current_user_ns(), CAP_SYS_ADMIN)) + return -EINVAL; error = prctl_set_mm_exe_file(mm, prctl_map.exe_fd); if (error) diff --git a/kernel/sysctl.c b/kernel/sysctl.c index 6ec1bb514ecd..8dcce286f0c7 100644 --- a/kernel/sysctl.c +++ b/kernel/sysctl.c @@ -375,7 +375,8 @@ static int max_extfrag_threshold = 1000; #ifdef CONFIG_BPF_SYSCALL static int bpf_stats_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { struct static_key *key = (struct static_key *)table->data; static int saved_val; diff --git a/kernel/trace/Makefile b/kernel/trace/Makefile index d09dfa4226b8..f9f4512c617d 100644 --- a/kernel/trace/Makefile +++ b/kernel/trace/Makefile @@ -28,8 +28,6 @@ ifdef CONFIG_GCOV_PROFILE_FTRACE GCOV_PROFILE := y endif -CFLAGS_bpf_trace.o := -I$(src) - CFLAGS_trace_benchmark.o := -I$(src) CFLAGS_trace_events_filter.o := -I$(src) @@ -74,7 +72,6 @@ obj-$(CONFIG_EVENT_TRACING) += trace_events_trigger.o obj-$(CONFIG_HIST_TRIGGERS) += trace_events_hist.o obj-$(CONFIG_BPF_EVENTS) += bpf_trace.o obj-$(CONFIG_KPROBE_EVENTS) += trace_kprobe.o -obj-$(CONFIG_TRACEPOINTS) += error_report-traces.o obj-$(CONFIG_TRACEPOINTS) += power-traces.o ifeq ($(CONFIG_PM),y) obj-$(CONFIG_TRACEPOINTS) += rpm-traces.o diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index a9829e3c4914..e6bfe1915ea4 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -25,9 +24,6 @@ #include "trace_probe.h" #include "trace.h" -#define CREATE_TRACE_POINTS -#include "bpf_trace.h" - #define bpf_event_rcu_dereference(p) \ rcu_dereference_protected(p, lockdep_is_held(&bpf_event_mutex)) @@ -93,7 +89,10 @@ unsigned int trace_call_bpf(struct trace_event_call *call, void *ctx) { unsigned int ret; - cant_sleep(); + if (in_nmi()) /* not supported yet */ + return 1; + + preempt_disable(); if (unlikely(__this_cpu_inc_return(bpf_prog_active) != 1)) { /* @@ -125,6 +124,7 @@ unsigned int trace_call_bpf(struct trace_event_call *call, void *ctx) out: __this_cpu_dec(bpf_prog_active); + preempt_enable(); return ret; } @@ -178,16 +178,6 @@ bpf_probe_read_user_str_common(void *dst, u32 size, { int ret; - /* - * NB: We rely on strncpy_from_user() not copying junk past the NUL - * terminator into `dst`. - * - * strncpy_from_user() does long-sized strides in the fast path. If the - * strncpy does not mask out the bytes after the NUL in `unsafe_ptr`, - * then there could be junk after the NUL in `dst`. If user takes `dst` - * and keys a hash map with it, then semantically identical strings can - * occupy multiple entries in the map. - */ ret = strncpy_from_user_nofault(dst, unsafe_ptr, size); if (unlikely(ret < 0)) memset(dst, 0, size); @@ -394,33 +384,9 @@ static void bpf_trace_copy_string(char *buf, void *unsafe_ptr, char fmt_ptype, } } -static DEFINE_RAW_SPINLOCK(trace_printk_lock); - -#define BPF_TRACE_PRINTK_SIZE 1024 - -static __printf(1, 0) int bpf_do_trace_printk(const char *fmt, ...) -{ - static char buf[BPF_TRACE_PRINTK_SIZE]; - unsigned long flags; - va_list ap; - int ret; - - raw_spin_lock_irqsave(&trace_printk_lock, flags); - va_start(ap, fmt); - ret = vsnprintf(buf, sizeof(buf), fmt, ap); - va_end(ap); - /* vsnprintf() will not append null for zero-length strings */ - if (ret == 0) - buf[0] = '\0'; - trace_bpf_trace_printk(buf); - raw_spin_unlock_irqrestore(&trace_printk_lock, flags); - - return ret; -} - /* * Only limited trace_printk() conversion specifiers allowed: - * %d %i %u %x %ld %li %lu %lx %lld %lli %llu %llx %p %pB %pks %pus %s + * %d %i %u %x %ld %li %lu %lx %lld %lli %llu %llx %p %pks %pus %s */ BPF_CALL_5(bpf_trace_printk, char *, fmt, u32, fmt_size, u64, arg1, u64, arg2, u64, arg3) @@ -464,11 +430,6 @@ BPF_CALL_5(bpf_trace_printk, char *, fmt, u32, fmt_size, u64, arg1, goto fmt_str; } - if (fmt[i + 1] == 'B') { - i++; - goto fmt_next; - } - /* disallow any further format extensions */ if (fmt[i + 1] != 0 && !isspace(fmt[i + 1]) && @@ -527,7 +488,8 @@ fmt_next: */ #define __BPF_TP_EMIT() __BPF_ARG3_TP() #define __BPF_TP(...) \ - bpf_do_trace_printk(fmt, ##__VA_ARGS__) + __trace_printk(0 /* Fake ip */, \ + fmt, ##__VA_ARGS__) #define __BPF_ARG1_TP(...) \ ((mod[0] == 2 || (mod[0] == 1 && __BITS_PER_LONG == 64)) \ @@ -564,15 +526,10 @@ static const struct bpf_func_proto bpf_trace_printk_proto = { const struct bpf_func_proto *bpf_get_trace_printk_proto(void) { /* - * This program might be calling bpf_trace_printk, - * so enable the associated bpf_trace/bpf_trace_printk event. - * Repeat this each time as it is possible a user has - * disabled bpf_trace_printk events. By loading a program - * calling bpf_trace_printk() however the user has expressed - * the intent to see such events. + * this program might be calling bpf_trace_printk, + * so allocate per-cpu printk buffers */ - if (trace_set_clr_event("bpf_trace", "bpf_trace_printk", 1)) - pr_warn_ratelimited("could not enable bpf_trace_printk events"); + trace_printk_init_buffers(); return &bpf_trace_printk_proto; } @@ -689,8 +646,7 @@ BPF_CALL_5(bpf_seq_printf, struct seq_file *, m, char *, fmt, u32, fmt_size, if (fmt[i] == 'p') { if (fmt[i + 1] == 0 || fmt[i + 1] == 'K' || - fmt[i + 1] == 'x' || - fmt[i + 1] == 'B') { + fmt[i + 1] == 'x') { /* just kernel pointers */ params[fmt_cnt] = args[fmt_cnt]; fmt_cnt++; @@ -735,8 +691,7 @@ BPF_CALL_5(bpf_seq_printf, struct seq_file *, m, char *, fmt, u32, fmt_size, } if (fmt[i] != 'i' && fmt[i] != 'd' && - fmt[i] != 'u' && fmt[i] != 'x' && - fmt[i] != 'X') { + fmt[i] != 'u' && fmt[i] != 'x') { err = -EINVAL; goto out; } @@ -982,6 +937,7 @@ static DEFINE_PER_CPU(struct bpf_trace_sample_data, bpf_misc_sds); u64 bpf_event_output(struct bpf_map *map, u64 flags, void *meta, u64 meta_size, void *ctx, u64 ctx_size, bpf_ctx_copy_t ctx_copy) { + int nest_level = this_cpu_inc_return(bpf_event_output_nest_level); struct perf_raw_frag frag = { .copy = ctx_copy, .size = ctx_size, @@ -998,12 +954,8 @@ u64 bpf_event_output(struct bpf_map *map, u64 flags, void *meta, u64 meta_size, }; struct perf_sample_data *sd; struct pt_regs *regs; - int nest_level; u64 ret; - preempt_disable(); - nest_level = this_cpu_inc_return(bpf_event_output_nest_level); - if (WARN_ON_ONCE(nest_level > ARRAY_SIZE(bpf_misc_sds.sds))) { ret = -EBUSY; goto out; @@ -1018,7 +970,6 @@ u64 bpf_event_output(struct bpf_map *map, u64 flags, void *meta, u64 meta_size, ret = __bpf_perf_event_output(regs, map, flags, sd); out: this_cpu_dec(bpf_event_output_nest_level); - preempt_enable(); return ret; } @@ -1071,7 +1022,6 @@ static void do_bpf_send_signal(struct irq_work *entry) work = container_of(entry, struct send_signal_irq_work, irq_work); group_send_sig_info(work->sig, SEND_SIG_PRIV, work->task, work->type); - put_task_struct(work->task); } static int bpf_send_signal_common(u32 sig, enum pid_type type) @@ -1108,7 +1058,7 @@ static int bpf_send_signal_common(u32 sig, enum pid_type type) * to the irq_work. The current task may change when queued * irq works get executed. */ - work->task = get_task_struct(current); + work->task = current; work->sig = sig; work->type = type; irq_work_queue(&work->irq_work); @@ -1144,23 +1094,13 @@ static const struct bpf_func_proto bpf_send_signal_thread_proto = { BPF_CALL_3(bpf_d_path, struct path *, path, char *, buf, u32, sz) { - struct path copy; long len; char *p; if (!sz) return 0; - /* - * The path pointer is verified as trusted and safe to use, - * but let's double check it's valid anyway to workaround - * potentially broken verifier. - */ - len = copy_from_kernel_nofault(©, path, sizeof(*path)); - if (len < 0) - return len; - - p = d_path(©, buf, sz); + p = d_path(path, buf, sz); if (IS_ERR(p)) { len = PTR_ERR(p); } else { @@ -1223,7 +1163,7 @@ static int bpf_btf_printf_prepare(struct btf_ptr *ptr, u32 btf_ptr_size, *btf = bpf_get_btf_vmlinux(); if (IS_ERR_OR_NULL(*btf)) - return IS_ERR(*btf) ? PTR_ERR(*btf) : -EINVAL; + return PTR_ERR(*btf); if (ptr->type_id > 0) *btf_id = ptr->type_id; @@ -1302,13 +1242,12 @@ bpf_tracing_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_get_numa_node_id_proto; case BPF_FUNC_perf_event_read: return &bpf_perf_event_read_proto; + case BPF_FUNC_probe_write_user: + return bpf_get_probe_write_proto(); case BPF_FUNC_current_task_under_cgroup: return &bpf_current_task_under_cgroup_proto; case BPF_FUNC_get_prandom_u32: return &bpf_get_prandom_u32_proto; - case BPF_FUNC_probe_write_user: - return security_locked_down(LOCKDOWN_BPF_WRITE_USER) < 0 ? - NULL : bpf_get_probe_write_proto(); case BPF_FUNC_probe_read_user: return &bpf_probe_read_user_proto; case BPF_FUNC_probe_read_kernel: @@ -1543,6 +1482,9 @@ static const struct bpf_func_proto bpf_perf_prog_read_value_proto = { BPF_CALL_4(bpf_read_branch_records, struct bpf_perf_event_data_kern *, ctx, void *, buf, u32, size, u64, flags) { +#ifndef CONFIG_X86 + return -ENOENT; +#else static const u32 br_entry_size = sizeof(struct perf_branch_entry); struct perf_branch_stack *br_stack = ctx->data->br_stack; u32 to_copy; @@ -1551,7 +1493,7 @@ BPF_CALL_4(bpf_read_branch_records, struct bpf_perf_event_data_kern *, ctx, return -EINVAL; if (unlikely(!br_stack)) - return -ENOENT; + return -EINVAL; if (flags & BPF_F_GET_BRANCH_RECORDS_SIZE) return br_stack->nr * br_entry_size; @@ -1563,6 +1505,7 @@ BPF_CALL_4(bpf_read_branch_records, struct bpf_perf_event_data_kern *, ctx, memcpy(buf, br_stack->entries, to_copy); return to_copy; +#endif } static const struct bpf_func_proto bpf_read_branch_records_proto = { @@ -1789,22 +1732,13 @@ static bool tracing_prog_is_valid_access(int off, int size, return btf_ctx_access(off, size, type, prog, info); } -int __weak bpf_prog_test_run_tracing(struct bpf_prog *prog, - const union bpf_attr *kattr, - union bpf_attr __user *uattr) -{ - return -ENOTSUPP; -} - const struct bpf_verifier_ops raw_tracepoint_verifier_ops = { .get_func_proto = raw_tp_prog_func_proto, .is_valid_access = raw_tp_prog_is_valid_access, }; const struct bpf_prog_ops raw_tracepoint_prog_ops = { -#ifdef CONFIG_NET .test_run = bpf_prog_test_run_raw_tp, -#endif }; const struct bpf_verifier_ops tracing_verifier_ops = { diff --git a/kernel/trace/bpf_trace.h b/kernel/trace/bpf_trace.h deleted file mode 100644 index 9acbc11ac7bb..000000000000 --- a/kernel/trace/bpf_trace.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#undef TRACE_SYSTEM -#define TRACE_SYSTEM bpf_trace - -#if !defined(_TRACE_BPF_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) - -#define _TRACE_BPF_TRACE_H - -#include - -TRACE_EVENT(bpf_trace_printk, - - TP_PROTO(const char *bpf_string), - - TP_ARGS(bpf_string), - - TP_STRUCT__entry( - __string(bpf_string, bpf_string) - ), - - TP_fast_assign( - __assign_str(bpf_string, bpf_string); - ), - - TP_printk("%s", __get_str(bpf_string)) -); - -#endif /* _TRACE_BPF_TRACE_H */ - -#undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH . -#define TRACE_INCLUDE_FILE bpf_trace - -#include diff --git a/kernel/trace/error_report-traces.c b/kernel/trace/error_report-traces.c deleted file mode 100644 index 632c8c7ff079..000000000000 --- a/kernel/trace/error_report-traces.c +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Error reporting trace points. - * - * Copyright (C) 2021, Google LLC. - */ - -#define CREATE_TRACE_POINTS -#include - -EXPORT_TRACEPOINT_SYMBOL_GPL(error_report_end); - diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index bc95bddfa77d..47df680f188d 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -7212,7 +7212,8 @@ static bool is_permanent_ops_registered(void) int ftrace_enable_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { int ret = -ENODEV; diff --git a/kernel/trace/trace_stack.c b/kernel/trace/trace_stack.c index 98bba4764c52..c557f42a9397 100644 --- a/kernel/trace/trace_stack.c +++ b/kernel/trace/trace_stack.c @@ -515,8 +515,9 @@ static const struct file_operations stack_trace_filter_fops = { #endif /* CONFIG_DYNAMIC_FTRACE */ int -stack_trace_sysctl(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos) +stack_trace_sysctl(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos) { int was_enabled; int ret; diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index f47cbf5660b1..b74832919af2 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -782,7 +782,6 @@ config DEBUG_STACKOVERFLOW If in doubt, say "N". source "lib/Kconfig.kasan" -source "lib/Kconfig.kfence" endmenu # "Memory Debugging" diff --git a/lib/Kconfig.kfence b/lib/Kconfig.kfence deleted file mode 100644 index e641add33947..000000000000 --- a/lib/Kconfig.kfence +++ /dev/null @@ -1,83 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -config HAVE_ARCH_KFENCE - bool - -menuconfig KFENCE - bool "KFENCE: low-overhead sampling-based memory safety error detector" - depends on HAVE_ARCH_KFENCE && (SLAB || SLUB) - select STACKTRACE - select IRQ_WORK - help - KFENCE is a low-overhead sampling-based detector of heap out-of-bounds - access, use-after-free, and invalid-free errors. KFENCE is designed - to have negligible cost to permit enabling it in production - environments. - - See for more details. - - Note that, KFENCE is not a substitute for explicit testing with tools - such as KASAN. KFENCE can detect a subset of bugs that KASAN can - detect, albeit at very different performance profiles. If you can - afford to use KASAN, continue using KASAN, for example in test - environments. If your kernel targets production use, and cannot - enable KASAN due to its cost, consider using KFENCE. - -if KFENCE - -config KFENCE_STATIC_KEYS - bool "Use static keys to set up allocations" - default y - depends on JUMP_LABEL # To ensure performance, require jump labels - help - Use static keys (static branches) to set up KFENCE allocations. Using - static keys is normally recommended, because it avoids a dynamic - branch in the allocator's fast path. However, with very low sample - intervals, or on systems that do not support jump labels, a dynamic - branch may still be an acceptable performance trade-off. - -config KFENCE_SAMPLE_INTERVAL - int "Default sample interval in milliseconds" - default 100 - help - The KFENCE sample interval determines the frequency with which heap - allocations will be guarded by KFENCE. May be overridden via boot - parameter "kfence.sample_interval". - - Set this to 0 to disable KFENCE by default, in which case only - setting "kfence.sample_interval" to a non-zero value enables KFENCE. - -config KFENCE_NUM_OBJECTS - int "Number of guarded objects available" - range 1 65535 - default 255 - help - The number of guarded objects available. For each KFENCE object, 2 - pages are required; with one containing the object and two adjacent - ones used as guard pages. - -config KFENCE_STRESS_TEST_FAULTS - int "Stress testing of fault handling and error reporting" if EXPERT - default 0 - help - The inverse probability with which to randomly protect KFENCE object - pages, resulting in spurious use-after-frees. The main purpose of - this option is to stress test KFENCE with concurrent error reports - and allocations/frees. A value of 0 disables stress testing logic. - - Only for KFENCE testing; set to 0 if you are not a KFENCE developer. - -config KFENCE_KUNIT_TEST - tristate "KFENCE integration test suite" if !KUNIT_ALL_TESTS - default KUNIT_ALL_TESTS - depends on TRACEPOINTS && KUNIT - help - Test suite for KFENCE, testing various error detection scenarios with - various allocation types, and checking that reports are correctly - output to console. - - Say Y here if you want the test to be built into the kernel and run - during boot; say M if you want the test to build as a module; say N - if you are unsure. - -endif # KFENCE diff --git a/lib/strncpy_from_user.c b/lib/strncpy_from_user.c index e136beefa7ba..706020b06617 100644 --- a/lib/strncpy_from_user.c +++ b/lib/strncpy_from_user.c @@ -34,32 +34,17 @@ static inline long do_strncpy_from_user(char *dst, const char __user *src, goto byte_at_a_time; while (max >= sizeof(unsigned long)) { - unsigned long c, data, mask; + unsigned long c, data; /* Fall back to byte-at-a-time if we get a page fault */ unsafe_get_user(c, (unsigned long __user *)(src+res), byte_at_a_time); - /* - * Note that we mask out the bytes following the NUL. This is - * important to do because string oblivious code may read past - * the NUL. For those routines, we don't want to give them - * potentially random bytes after the NUL in `src`. - * - * One example of such code is BPF map keys. BPF treats map keys - * as an opaque set of bytes. Without the post-NUL mask, any BPF - * maps keyed by strings returned from strncpy_from_user() may - * have multiple entries for semantically identical strings. - */ + *(unsigned long *)(dst+res) = c; if (has_zero(c, &data, &constants)) { data = prep_zero_mask(c, data, &constants); data = create_zero_mask(data); - mask = zero_bytemask(data); - *(unsigned long *)(dst+res) = c & mask; return res + find_zero(data); } - - *(unsigned long *)(dst+res) = c; - res += sizeof(unsigned long); max -= sizeof(unsigned long); } diff --git a/lib/test_bitmap.c b/lib/test_bitmap.c index 1ee9d95898b5..51a98f7ee79e 100644 --- a/lib/test_bitmap.c +++ b/lib/test_bitmap.c @@ -16,7 +16,8 @@ #include "../tools/testing/selftests/kselftest_module.h" -KSTM_MODULE_GLOBALS(); +static unsigned total_tests __initdata; +static unsigned failed_tests __initdata; static char pbl_buffer[PAGE_SIZE] __initdata; diff --git a/lib/test_printf.c b/lib/test_printf.c index 0a3153f162c7..d4b711b53942 100644 --- a/lib/test_printf.c +++ b/lib/test_printf.c @@ -28,13 +28,11 @@ #define PAD_SIZE 16 #define FILL_CHAR '$' -KSTM_MODULE_GLOBALS(); - +static unsigned total_tests __initdata; +static unsigned failed_tests __initdata; static char *test_buffer __initdata; static char *alloced_buffer __initdata; -extern bool no_hash_pointers; - static int __printf(4, 0) __init do_test(int bufsize, const char *expect, int elen, const char *fmt, va_list ap) @@ -301,12 +299,6 @@ plain(void) { int err; - if (no_hash_pointers) { - pr_warn("skipping plain 'p' tests"); - skipped_tests += 2; - return; - } - err = plain_hash(); if (err) { pr_warn("plain 'p' does not appear to be hashed\n"); diff --git a/lib/vsprintf.c b/lib/vsprintf.c index f3d84136199b..d377456b8c39 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -2057,32 +2057,6 @@ static char *kobject_string(char *buf, char *end, void *ptr, return error_string(buf, end, "(%pO?)", spec); } -/* Disable pointer hashing if requested */ -bool no_hash_pointers __ro_after_init; -EXPORT_SYMBOL_GPL(no_hash_pointers); - -static int __init no_hash_pointers_enable(char *str) -{ - no_hash_pointers = true; - - pr_warn("**********************************************************\n"); - pr_warn("** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE **\n"); - pr_warn("** **\n"); - pr_warn("** This system shows unhashed kernel memory addresses **\n"); - pr_warn("** via the console, logs, and other interfaces. This **\n"); - pr_warn("** might reduce the security of your system. **\n"); - pr_warn("** **\n"); - pr_warn("** If you see this message and you are not debugging **\n"); - pr_warn("** the kernel, report this immediately to your system **\n"); - pr_warn("** administrator! **\n"); - pr_warn("** **\n"); - pr_warn("** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE **\n"); - pr_warn("**********************************************************\n"); - - return 0; -} -early_param("no_hash_pointers", no_hash_pointers_enable); - /* * Show a '%p' thing. A kernel extension is that the '%p' is followed * by an extra set of alphanumeric characters that are extended format @@ -2285,14 +2259,8 @@ char *pointer(const char *fmt, char *buf, char *end, void *ptr, if (IS_ENABLED(CONFIG_DEBUG_CONSOLE_UNHASHED_POINTERS)) return pointer_string(buf, end, ptr, spec); - /* - * default is to _not_ leak addresses, so hash before printing, - * unless no_hash_pointers is specified on the command line. - */ - if (unlikely(no_hash_pointers)) - return pointer_string(buf, end, ptr, spec); - else - return ptr_to_id(buf, end, ptr, spec); + /* default is to _not_ leak addresses, hash before printing */ + return ptr_to_id(buf, end, ptr, spec); } /* diff --git a/mm/Makefile b/mm/Makefile index 7d852be8167b..d433568ee189 100644 --- a/mm/Makefile +++ b/mm/Makefile @@ -71,7 +71,6 @@ obj-$(CONFIG_PAGE_POISONING) += page_poison.o obj-$(CONFIG_SLAB) += slab.o obj-$(CONFIG_SLUB) += slub.o obj-$(CONFIG_KASAN) += kasan/ -obj-$(CONFIG_KFENCE) += kfence/ obj-$(CONFIG_FAILSLAB) += failslab.o obj-$(CONFIG_MEMORY_HOTPLUG) += memory_hotplug.o obj-$(CONFIG_MEMTEST) += memtest.o diff --git a/mm/backing-dev.c b/mm/backing-dev.c index 1dcde0685a5f..3954ef0cc770 100644 --- a/mm/backing-dev.c +++ b/mm/backing-dev.c @@ -878,8 +878,6 @@ struct backing_dev_info *bdi_alloc_node(gfp_t gfp_mask, int node_id) kfree(bdi); return NULL; } - bdi->ra_pages = VM_READAHEAD_PAGES; - bdi->io_pages = VM_READAHEAD_PAGES; return bdi; } EXPORT_SYMBOL(bdi_alloc_node); diff --git a/mm/kasan/common.c b/mm/kasan/common.c index b71b16da066e..ac9f624158b9 100644 --- a/mm/kasan/common.c +++ b/mm/kasan/common.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -141,10 +140,6 @@ void kasan_poison_shadow(const void *address, size_t size, u8 value) */ address = reset_tag(address); - /* Skip KFENCE memory if called explicitly outside of sl*b. */ - if (is_kfence_address(address)) - return; - shadow_start = kasan_mem_to_shadow(address); shadow_end = kasan_mem_to_shadow(address + size); @@ -162,14 +157,6 @@ void kasan_unpoison_shadow(const void *address, size_t size) */ address = reset_tag(address); - /* - * Skip KFENCE memory if called explicitly outside of sl*b. Also note - * that calls to ksize(), where size is not a multiple of machine-word - * size, would otherwise poison the invalid portion of the word. - */ - if (is_kfence_address(address)) - return; - kasan_poison_shadow(address, size, tag); if (size & KASAN_SHADOW_MASK) { @@ -458,9 +445,6 @@ static bool __kasan_slab_free(struct kmem_cache *cache, void *object, tagged_object = object; object = reset_tag(object); - if (is_kfence_address(object)) - return false; - if (unlikely(nearest_obj(cache, virt_to_head_page(object), object) != object)) { kasan_report_invalid_free(tagged_object, ip); @@ -509,9 +493,6 @@ static void *__kasan_kmalloc(struct kmem_cache *cache, const void *object, if (unlikely(object == NULL)) return NULL; - if (is_kfence_address(kasan_reset_tag(object))) - return (void *)object; - redzone_start = round_up((unsigned long)(object + size), KASAN_SHADOW_SCALE_SIZE); redzone_end = round_up((unsigned long)object + cache->object_size, diff --git a/mm/kasan/report.c b/mm/kasan/report.c index 783301f294de..4d87df96acc1 100644 --- a/mm/kasan/report.c +++ b/mm/kasan/report.c @@ -29,7 +29,6 @@ #include #include #include -#include #include @@ -88,9 +87,8 @@ static void start_report(unsigned long *flags) pr_err("==================================================================\n"); } -static void end_report(unsigned long *flags, unsigned long addr) +static void end_report(unsigned long *flags) { - trace_error_report_end(ERROR_DETECTOR_KASAN, addr); pr_err("==================================================================\n"); add_taint(TAINT_BAD_PAGE, LOCKDEP_NOW_UNRELIABLE); spin_unlock_irqrestore(&report_lock, *flags); @@ -470,7 +468,7 @@ void kasan_report_invalid_free(void *object, unsigned long ip) print_address_description(object, tag); pr_err("\n"); print_shadow_for_address(object); - end_report(&flags, (unsigned long)object); + end_report(&flags); } void __kasan_report(unsigned long addr, size_t size, bool is_write, unsigned long ip) @@ -512,5 +510,5 @@ void __kasan_report(unsigned long addr, size_t size, bool is_write, unsigned lon dump_stack(); } - end_report(&flags, addr); + end_report(&flags); } diff --git a/mm/kfence/Makefile b/mm/kfence/Makefile deleted file mode 100644 index cb2bcf773083..000000000000 --- a/mm/kfence/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -obj-$(CONFIG_KFENCE) := core.o report.o - -CFLAGS_kfence_test.o := -fno-omit-frame-pointer -fno-optimize-sibling-calls -obj-$(CONFIG_KFENCE_KUNIT_TEST) += kfence_test.o diff --git a/mm/kfence/core.c b/mm/kfence/core.c deleted file mode 100644 index 566a82c3cb20..000000000000 --- a/mm/kfence/core.c +++ /dev/null @@ -1,889 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * KFENCE guarded object allocator and fault handling. - * - * Copyright (C) 2020, Google LLC. - */ - -#define pr_fmt(fmt) "kfence: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "kfence.h" - -/* - * Android 4.19 kernel does not support KCSAN, so we have to disable data race - * annotations. - */ -#ifndef data_race -#define data_race(x) (x) -#endif - -/* Disables KFENCE on the first warning assuming an irrecoverable error. */ -#define KFENCE_WARN_ON(cond) \ - ({ \ - const bool __cond = WARN_ON(cond); \ - if (unlikely(__cond)) \ - WRITE_ONCE(kfence_enabled, false); \ - __cond; \ - }) - -/* === Data ================================================================= */ - -static bool kfence_enabled __read_mostly; - -static unsigned long kfence_sample_interval __read_mostly = CONFIG_KFENCE_SAMPLE_INTERVAL; - -#ifdef MODULE_PARAM_PREFIX -#undef MODULE_PARAM_PREFIX -#endif -#define MODULE_PARAM_PREFIX "kfence." - -static int param_set_sample_interval(const char *val, const struct kernel_param *kp) -{ - unsigned long num; - int ret = kstrtoul(val, 0, &num); - - if (ret < 0) - return ret; - - if (!num) /* Using 0 to indicate KFENCE is disabled. */ - WRITE_ONCE(kfence_enabled, false); - else if (!READ_ONCE(kfence_enabled) && system_state != SYSTEM_BOOTING) - return -EINVAL; /* Cannot (re-)enable KFENCE on-the-fly. */ - - *((unsigned long *)kp->arg) = num; - return 0; -} - -static int param_get_sample_interval(char *buffer, const struct kernel_param *kp) -{ - if (!READ_ONCE(kfence_enabled)) - return sprintf(buffer, "0\n"); - - return param_get_ulong(buffer, kp); -} - -static const struct kernel_param_ops sample_interval_param_ops = { - .set = param_set_sample_interval, - .get = param_get_sample_interval, -}; -module_param_cb(sample_interval, &sample_interval_param_ops, &kfence_sample_interval, 0600); - -/* The pool of pages used for guard pages and objects. */ -char *__kfence_pool __ro_after_init; -EXPORT_SYMBOL(__kfence_pool); /* Export for test modules. */ - -/* - * Per-object metadata, with one-to-one mapping of object metadata to - * backing pages (in __kfence_pool). - */ -static_assert(CONFIG_KFENCE_NUM_OBJECTS > 0); -struct kfence_metadata kfence_metadata[CONFIG_KFENCE_NUM_OBJECTS]; - -/* Freelist with available objects. */ -static struct list_head kfence_freelist = LIST_HEAD_INIT(kfence_freelist); -static DEFINE_RAW_SPINLOCK(kfence_freelist_lock); /* Lock protecting freelist. */ - -#ifdef CONFIG_KFENCE_STATIC_KEYS -/* The static key to set up a KFENCE allocation. */ -DEFINE_STATIC_KEY_FALSE(kfence_allocation_key); -#endif - -/* Gates the allocation, ensuring only one succeeds in a given period. */ -atomic_t kfence_allocation_gate = ATOMIC_INIT(1); - -/* Statistics counters for debugfs. */ -enum kfence_counter_id { - KFENCE_COUNTER_ALLOCATED, - KFENCE_COUNTER_ALLOCS, - KFENCE_COUNTER_FREES, - KFENCE_COUNTER_ZOMBIES, - KFENCE_COUNTER_BUGS, - KFENCE_COUNTER_COUNT, -}; -static atomic_long_t counters[KFENCE_COUNTER_COUNT]; -static const char *const counter_names[] = { - [KFENCE_COUNTER_ALLOCATED] = "currently allocated", - [KFENCE_COUNTER_ALLOCS] = "total allocations", - [KFENCE_COUNTER_FREES] = "total frees", - [KFENCE_COUNTER_ZOMBIES] = "zombie allocations", - [KFENCE_COUNTER_BUGS] = "total bugs", -}; -static_assert(ARRAY_SIZE(counter_names) == KFENCE_COUNTER_COUNT); - -/* === Internals ============================================================ */ - -static bool kfence_protect(unsigned long addr) -{ - return !KFENCE_WARN_ON(!kfence_protect_page(ALIGN_DOWN(addr, PAGE_SIZE), true)); -} - -static bool kfence_unprotect(unsigned long addr) -{ - return !KFENCE_WARN_ON(!kfence_protect_page(ALIGN_DOWN(addr, PAGE_SIZE), false)); -} - -static inline struct kfence_metadata *addr_to_metadata(unsigned long addr) -{ - long index; - - /* The checks do not affect performance; only called from slow-paths. */ - - if (!is_kfence_address((void *)addr)) - return NULL; - - /* - * May be an invalid index if called with an address at the edge of - * __kfence_pool, in which case we would report an "invalid access" - * error. - */ - index = (addr - (unsigned long)__kfence_pool) / (PAGE_SIZE * 2) - 1; - if (index < 0 || index >= CONFIG_KFENCE_NUM_OBJECTS) - return NULL; - - return &kfence_metadata[index]; -} - -static inline unsigned long metadata_to_pageaddr(const struct kfence_metadata *meta) -{ - unsigned long offset = (meta - kfence_metadata + 1) * PAGE_SIZE * 2; - unsigned long pageaddr = (unsigned long)&__kfence_pool[offset]; - - /* The checks do not affect performance; only called from slow-paths. */ - - /* Only call with a pointer into kfence_metadata. */ - if (KFENCE_WARN_ON(meta < kfence_metadata || - meta >= kfence_metadata + CONFIG_KFENCE_NUM_OBJECTS)) - return 0; - - /* - * This metadata object only ever maps to 1 page; verify that the stored - * address is in the expected range. - */ - if (KFENCE_WARN_ON(ALIGN_DOWN(meta->addr, PAGE_SIZE) != pageaddr)) - return 0; - - return pageaddr; -} - -/* - * Update the object's metadata state, including updating the alloc/free stacks - * depending on the state transition. - */ -static noinline void metadata_update_state(struct kfence_metadata *meta, - enum kfence_object_state next) -{ - struct kfence_track *track = - next == KFENCE_OBJECT_FREED ? &meta->free_track : &meta->alloc_track; - - lockdep_assert_held(&meta->lock); - - /* - * Skip over 1 (this) functions; noinline ensures we do not accidentally - * skip over the caller by never inlining. - */ - track->num_stack_entries = stack_trace_save(track->stack_entries, KFENCE_STACK_DEPTH, 1); - track->pid = task_pid_nr(current); - - /* - * Pairs with READ_ONCE() in - * kfence_shutdown_cache(), - * kfence_handle_page_fault(). - */ - WRITE_ONCE(meta->state, next); -} - -/* Write canary byte to @addr. */ -static inline bool set_canary_byte(u8 *addr) -{ - *addr = KFENCE_CANARY_PATTERN(addr); - return true; -} - -/* Check canary byte at @addr. */ -static inline bool check_canary_byte(u8 *addr) -{ - if (likely(*addr == KFENCE_CANARY_PATTERN(addr))) - return true; - - atomic_long_inc(&counters[KFENCE_COUNTER_BUGS]); - kfence_report_error((unsigned long)addr, false, NULL, addr_to_metadata((unsigned long)addr), - KFENCE_ERROR_CORRUPTION); - return false; -} - -/* __always_inline this to ensure we won't do an indirect call to fn. */ -static __always_inline void for_each_canary(const struct kfence_metadata *meta, bool (*fn)(u8 *)) -{ - const unsigned long pageaddr = ALIGN_DOWN(meta->addr, PAGE_SIZE); - unsigned long addr; - - lockdep_assert_held(&meta->lock); - - /* - * We'll iterate over each canary byte per-side until fn() returns - * false. However, we'll still iterate over the canary bytes to the - * right of the object even if there was an error in the canary bytes to - * the left of the object. Specifically, if check_canary_byte() - * generates an error, showing both sides might give more clues as to - * what the error is about when displaying which bytes were corrupted. - */ - - /* Apply to left of object. */ - for (addr = pageaddr; addr < meta->addr; addr++) { - if (!fn((u8 *)addr)) - break; - } - - /* Apply to right of object. */ - for (addr = meta->addr + meta->size; addr < pageaddr + PAGE_SIZE; addr++) { - if (!fn((u8 *)addr)) - break; - } -} - -static void *kfence_guarded_alloc(struct kmem_cache *cache, size_t size, gfp_t gfp) -{ - struct kfence_metadata *meta = NULL; - unsigned long flags; - struct page *page; - void *addr; - - /* Try to obtain a free object. */ - raw_spin_lock_irqsave(&kfence_freelist_lock, flags); - if (!list_empty(&kfence_freelist)) { - meta = list_entry(kfence_freelist.next, struct kfence_metadata, list); - list_del_init(&meta->list); - } - raw_spin_unlock_irqrestore(&kfence_freelist_lock, flags); - if (!meta) - return NULL; - - if (unlikely(!raw_spin_trylock_irqsave(&meta->lock, flags))) { - /* - * This is extremely unlikely -- we are reporting on a - * use-after-free, which locked meta->lock, and the reporting - * code via printk calls kmalloc() which ends up in - * kfence_alloc() and tries to grab the same object that we're - * reporting on. While it has never been observed, lockdep does - * report that there is a possibility of deadlock. Fix it by - * using trylock and bailing out gracefully. - */ - raw_spin_lock_irqsave(&kfence_freelist_lock, flags); - /* Put the object back on the freelist. */ - list_add_tail(&meta->list, &kfence_freelist); - raw_spin_unlock_irqrestore(&kfence_freelist_lock, flags); - - return NULL; - } - - meta->addr = metadata_to_pageaddr(meta); - /* Unprotect if we're reusing this page. */ - if (meta->state == KFENCE_OBJECT_FREED) - kfence_unprotect(meta->addr); - - /* - * Note: for allocations made before RNG initialization, will always - * return zero. We still benefit from enabling KFENCE as early as - * possible, even when the RNG is not yet available, as this will allow - * KFENCE to detect bugs due to earlier allocations. The only downside - * is that the out-of-bounds accesses detected are deterministic for - * such allocations. - */ - if (prandom_u32_max(2)) { - /* Allocate on the "right" side, re-calculate address. */ - meta->addr += PAGE_SIZE - size; - meta->addr = ALIGN_DOWN(meta->addr, cache->align); - } - - addr = (void *)meta->addr; - - /* Update remaining metadata. */ - metadata_update_state(meta, KFENCE_OBJECT_ALLOCATED); - /* Pairs with READ_ONCE() in kfence_shutdown_cache(). */ - WRITE_ONCE(meta->cache, cache); - meta->size = size; - for_each_canary(meta, set_canary_byte); - - /* Set required struct page fields. */ - page = virt_to_page(meta->addr); - page->slab_cache = cache; - if (IS_ENABLED(CONFIG_SLUB)) - page->objects = 1; - if (IS_ENABLED(CONFIG_SLAB)) - page->s_mem = addr; - - raw_spin_unlock_irqrestore(&meta->lock, flags); - - /* Memory initialization. */ - - /* - * We check slab_want_init_on_alloc() ourselves, rather than letting - * SL*B do the initialization, as otherwise we might overwrite KFENCE's - * redzone. - */ - if (unlikely(slab_want_init_on_alloc(gfp, cache))) - memzero_explicit(addr, size); - if (cache->ctor) - cache->ctor(addr); - - if (CONFIG_KFENCE_STRESS_TEST_FAULTS && !prandom_u32_max(CONFIG_KFENCE_STRESS_TEST_FAULTS)) - kfence_protect(meta->addr); /* Random "faults" by protecting the object. */ - - atomic_long_inc(&counters[KFENCE_COUNTER_ALLOCATED]); - atomic_long_inc(&counters[KFENCE_COUNTER_ALLOCS]); - - return addr; -} - -static void kfence_guarded_free(void *addr, struct kfence_metadata *meta, bool zombie) -{ - unsigned long flags; - - raw_spin_lock_irqsave(&meta->lock, flags); - - if (meta->state != KFENCE_OBJECT_ALLOCATED || meta->addr != (unsigned long)addr) { - /* Invalid or double-free, bail out. */ - atomic_long_inc(&counters[KFENCE_COUNTER_BUGS]); - kfence_report_error((unsigned long)addr, false, NULL, meta, - KFENCE_ERROR_INVALID_FREE); - raw_spin_unlock_irqrestore(&meta->lock, flags); - return; - } - - if (CONFIG_KFENCE_STRESS_TEST_FAULTS) - kfence_unprotect((unsigned long)addr); /* To check canary bytes. */ - - /* Restore page protection if there was an OOB access. */ - if (meta->unprotected_page) { - memzero_explicit((void *)ALIGN_DOWN(meta->unprotected_page, PAGE_SIZE), PAGE_SIZE); - kfence_protect(meta->unprotected_page); - meta->unprotected_page = 0; - } - - /* Check canary bytes for memory corruption. */ - for_each_canary(meta, check_canary_byte); - - /* - * Clear memory if init-on-free is set. While we protect the page, the - * data is still there, and after a use-after-free is detected, we - * unprotect the page, so the data is still accessible. - */ - if (!zombie && unlikely(slab_want_init_on_free(meta->cache))) - memzero_explicit(addr, meta->size); - - /* Mark the object as freed. */ - metadata_update_state(meta, KFENCE_OBJECT_FREED); - - raw_spin_unlock_irqrestore(&meta->lock, flags); - - /* Protect to detect use-after-frees. */ - kfence_protect((unsigned long)addr); - - if (!zombie) { - /* Add it to the tail of the freelist for reuse. */ - raw_spin_lock_irqsave(&kfence_freelist_lock, flags); - KFENCE_WARN_ON(!list_empty(&meta->list)); - list_add_tail(&meta->list, &kfence_freelist); - raw_spin_unlock_irqrestore(&kfence_freelist_lock, flags); - - atomic_long_dec(&counters[KFENCE_COUNTER_ALLOCATED]); - atomic_long_inc(&counters[KFENCE_COUNTER_FREES]); - } else { - /* See kfence_shutdown_cache(). */ - atomic_long_inc(&counters[KFENCE_COUNTER_ZOMBIES]); - } -} - -static void rcu_guarded_free(struct rcu_head *h) -{ - struct kfence_metadata *meta = container_of(h, struct kfence_metadata, rcu_head); - - kfence_guarded_free((void *)meta->addr, meta, false); -} - -static bool __init kfence_init_pool(void) -{ - unsigned long addr = (unsigned long)__kfence_pool; - struct page *pages; - int i; - - if (!__kfence_pool) - return false; - - if (!arch_kfence_init_pool()) - goto err; - - pages = virt_to_page(addr); - - /* - * Set up object pages: they must have PG_slab set, to avoid freeing - * these as real pages. - * - * We also want to avoid inserting kfence_free() in the kfree() - * fast-path in SLUB, and therefore need to ensure kfree() correctly - * enters __slab_free() slow-path. - */ - for (i = 0; i < KFENCE_POOL_SIZE / PAGE_SIZE; i++) { - if (!i || (i % 2)) - continue; - - /* Verify we do not have a compound head page. */ - if (WARN_ON(compound_head(&pages[i]) != &pages[i])) - goto err; - - __SetPageSlab(&pages[i]); - } - - /* - * Protect the first 2 pages. The first page is mostly unnecessary, and - * merely serves as an extended guard page. However, adding one - * additional page in the beginning gives us an even number of pages, - * which simplifies the mapping of address to metadata index. - */ - for (i = 0; i < 2; i++) { - if (unlikely(!kfence_protect(addr))) - goto err; - - addr += PAGE_SIZE; - } - - for (i = 0; i < CONFIG_KFENCE_NUM_OBJECTS; i++) { - struct kfence_metadata *meta = &kfence_metadata[i]; - - /* Initialize metadata. */ - INIT_LIST_HEAD(&meta->list); - raw_spin_lock_init(&meta->lock); - meta->state = KFENCE_OBJECT_UNUSED; - meta->addr = addr; /* Initialize for validation in metadata_to_pageaddr(). */ - list_add_tail(&meta->list, &kfence_freelist); - - /* Protect the right redzone. */ - if (unlikely(!kfence_protect(addr + PAGE_SIZE))) - goto err; - - addr += 2 * PAGE_SIZE; - } - - /* - * The pool is live and will never be deallocated from this point on. - * Remove the pool object from the kmemleak object tree, as it would - * otherwise overlap with allocations returned by kfence_alloc(), which - * are registered with kmemleak through the slab post-alloc hook. - */ - kmemleak_free(__kfence_pool); - - return true; - -err: - /* - * Only release unprotected pages, and do not try to go back and change - * page attributes due to risk of failing to do so as well. If changing - * page attributes for some pages fails, it is very likely that it also - * fails for the first page, and therefore expect addr==__kfence_pool in - * most failure cases. - */ - memblock_free_late(__pa(addr), KFENCE_POOL_SIZE - (addr - (unsigned long)__kfence_pool)); - __kfence_pool = NULL; - return false; -} - -/* === DebugFS Interface ==================================================== */ - -static int stats_show(struct seq_file *seq, void *v) -{ - int i; - - seq_printf(seq, "enabled: %i\n", READ_ONCE(kfence_enabled)); - for (i = 0; i < KFENCE_COUNTER_COUNT; i++) - seq_printf(seq, "%s: %ld\n", counter_names[i], atomic_long_read(&counters[i])); - - return 0; -} -DEFINE_SHOW_ATTRIBUTE(stats); - -/* - * debugfs seq_file operations for /sys/kernel/debug/kfence/objects. - * start_object() and next_object() return the object index + 1, because NULL is used - * to stop iteration. - */ -static void *start_object(struct seq_file *seq, loff_t *pos) -{ - if (*pos < CONFIG_KFENCE_NUM_OBJECTS) - return (void *)((long)*pos + 1); - return NULL; -} - -static void stop_object(struct seq_file *seq, void *v) -{ -} - -static void *next_object(struct seq_file *seq, void *v, loff_t *pos) -{ - ++*pos; - if (*pos < CONFIG_KFENCE_NUM_OBJECTS) - return (void *)((long)*pos + 1); - return NULL; -} - -static int show_object(struct seq_file *seq, void *v) -{ - struct kfence_metadata *meta = &kfence_metadata[(long)v - 1]; - unsigned long flags; - - raw_spin_lock_irqsave(&meta->lock, flags); - kfence_print_object(seq, meta); - raw_spin_unlock_irqrestore(&meta->lock, flags); - seq_puts(seq, "---------------------------------\n"); - - return 0; -} - -static const struct seq_operations object_seqops = { - .start = start_object, - .next = next_object, - .stop = stop_object, - .show = show_object, -}; - -static int open_objects(struct inode *inode, struct file *file) -{ - return seq_open(file, &object_seqops); -} - -static const struct file_operations objects_fops = { - .open = open_objects, - .read = seq_read, - .llseek = seq_lseek, - .release = seq_release, -}; - -static int __init kfence_debugfs_init(void) -{ - struct dentry *kfence_dir = debugfs_create_dir("kfence", NULL); - - debugfs_create_file("stats", 0444, kfence_dir, NULL, &stats_fops); - debugfs_create_file("objects", 0400, kfence_dir, NULL, &objects_fops); - return 0; -} - -late_initcall(kfence_debugfs_init); - -/* === Allocation Gate Timer ================================================ */ - -#ifdef CONFIG_KFENCE_STATIC_KEYS -/* Wait queue to wake up allocation-gate timer task. */ -static DECLARE_WAIT_QUEUE_HEAD(allocation_wait); - -static void wake_up_kfence_timer(struct irq_work *work) -{ - wake_up(&allocation_wait); -} -static DEFINE_IRQ_WORK(wake_up_kfence_timer_work, wake_up_kfence_timer); -#endif - -/* - * Set up delayed work, which will enable and disable the static key. We need to - * use a work queue (rather than a simple timer), since enabling and disabling a - * static key cannot be done from an interrupt. - * - * Note: Toggling a static branch currently causes IPIs, and here we'll end up - * with a total of 2 IPIs to all CPUs. If this ends up a problem in future (with - * more aggressive sampling intervals), we could get away with a variant that - * avoids IPIs, at the cost of not immediately capturing allocations if the - * instructions remain cached. - */ -static struct delayed_work kfence_timer; -static void toggle_allocation_gate(struct work_struct *work) -{ - if (!READ_ONCE(kfence_enabled)) - return; - - atomic_set(&kfence_allocation_gate, 0); -#ifdef CONFIG_KFENCE_STATIC_KEYS - /* Enable static key, and await allocation to happen. */ - static_branch_enable(&kfence_allocation_key); - - if (sysctl_hung_task_timeout_secs) { - /* - * During low activity with no allocations we might wait a - * while; let's avoid the hung task warning. - */ - wait_event_idle_timeout(allocation_wait, atomic_read(&kfence_allocation_gate), - sysctl_hung_task_timeout_secs * HZ / 2); - } else { - wait_event_idle(allocation_wait, atomic_read(&kfence_allocation_gate)); - } - - /* Disable static key and reset timer. */ - static_branch_disable(&kfence_allocation_key); -#endif - queue_delayed_work(system_unbound_wq, &kfence_timer, - msecs_to_jiffies(kfence_sample_interval)); -} -static DECLARE_DELAYED_WORK(kfence_timer, toggle_allocation_gate); - -/* === Public interface ===================================================== */ - -void __init kfence_alloc_pool(void) -{ - if (!kfence_sample_interval) - return; - - __kfence_pool = memblock_alloc(KFENCE_POOL_SIZE, PAGE_SIZE); - - if (!__kfence_pool) - pr_err("failed to allocate pool\n"); -} - -void __init kfence_init(void) -{ - /* Setting kfence_sample_interval to 0 on boot disables KFENCE. */ - if (!kfence_sample_interval) - return; - - if (!kfence_init_pool()) { - pr_err("%s failed\n", __func__); - return; - } - - WRITE_ONCE(kfence_enabled, true); - queue_delayed_work(system_unbound_wq, &kfence_timer, 0); - pr_info("initialized - using %lu bytes for %d objects at 0x%p-0x%p\n", KFENCE_POOL_SIZE, - CONFIG_KFENCE_NUM_OBJECTS, (void *)__kfence_pool, - (void *)(__kfence_pool + KFENCE_POOL_SIZE)); -} - -void kfence_shutdown_cache(struct kmem_cache *s) -{ - unsigned long flags; - struct kfence_metadata *meta; - int i; - - for (i = 0; i < CONFIG_KFENCE_NUM_OBJECTS; i++) { - bool in_use; - - meta = &kfence_metadata[i]; - - /* - * If we observe some inconsistent cache and state pair where we - * should have returned false here, cache destruction is racing - * with either kmem_cache_alloc() or kmem_cache_free(). Taking - * the lock will not help, as different critical section - * serialization will have the same outcome. - */ - if (READ_ONCE(meta->cache) != s || - READ_ONCE(meta->state) != KFENCE_OBJECT_ALLOCATED) - continue; - - raw_spin_lock_irqsave(&meta->lock, flags); - in_use = meta->cache == s && meta->state == KFENCE_OBJECT_ALLOCATED; - raw_spin_unlock_irqrestore(&meta->lock, flags); - - if (in_use) { - /* - * This cache still has allocations, and we should not - * release them back into the freelist so they can still - * safely be used and retain the kernel's default - * behaviour of keeping the allocations alive (leak the - * cache); however, they effectively become "zombie - * allocations" as the KFENCE objects are the only ones - * still in use and the owning cache is being destroyed. - * - * We mark them freed, so that any subsequent use shows - * more useful error messages that will include stack - * traces of the user of the object, the original - * allocation, and caller to shutdown_cache(). - */ - kfence_guarded_free((void *)meta->addr, meta, /*zombie=*/true); - } - } - - for (i = 0; i < CONFIG_KFENCE_NUM_OBJECTS; i++) { - meta = &kfence_metadata[i]; - - /* See above. */ - if (READ_ONCE(meta->cache) != s || READ_ONCE(meta->state) != KFENCE_OBJECT_FREED) - continue; - - raw_spin_lock_irqsave(&meta->lock, flags); - if (meta->cache == s && meta->state == KFENCE_OBJECT_FREED) - meta->cache = NULL; - raw_spin_unlock_irqrestore(&meta->lock, flags); - } -} - -void *__kfence_alloc(struct kmem_cache *s, size_t size, gfp_t flags) -{ - /* - * Perform size check before switching kfence_allocation_gate, so that - * we don't disable KFENCE without making an allocation. - */ - if (size > PAGE_SIZE) - return NULL; - - /* - * Skip allocations from non-default zones, including DMA. We cannot - * guarantee that pages in the KFENCE pool will have the requested - * properties (e.g. reside in DMAable memory). - */ - if ((flags & GFP_ZONEMASK) || - (s->flags & (SLAB_CACHE_DMA | SLAB_CACHE_DMA32))) - return NULL; - - /* - * allocation_gate only needs to become non-zero, so it doesn't make - * sense to continue writing to it and pay the associated contention - * cost, in case we have a large number of concurrent allocations. - */ - if (atomic_read(&kfence_allocation_gate) || atomic_inc_return(&kfence_allocation_gate) > 1) - return NULL; -#ifdef CONFIG_KFENCE_STATIC_KEYS - /* - * waitqueue_active() is fully ordered after the update of - * kfence_allocation_gate per atomic_inc_return(). - */ - if (waitqueue_active(&allocation_wait)) { - /* - * Calling wake_up() here may deadlock when allocations happen - * from within timer code. Use an irq_work to defer it. - */ - irq_work_queue(&wake_up_kfence_timer_work); - } -#endif - - if (!READ_ONCE(kfence_enabled)) - return NULL; - - return kfence_guarded_alloc(s, size, flags); -} - -size_t kfence_ksize(const void *addr) -{ - const struct kfence_metadata *meta = addr_to_metadata((unsigned long)addr); - - /* - * Read locklessly -- if there is a race with __kfence_alloc(), this is - * either a use-after-free or invalid access. - */ - return meta ? meta->size : 0; -} - -void *kfence_object_start(const void *addr) -{ - const struct kfence_metadata *meta = addr_to_metadata((unsigned long)addr); - - /* - * Read locklessly -- if there is a race with __kfence_alloc(), this is - * either a use-after-free or invalid access. - */ - return meta ? (void *)meta->addr : NULL; -} - -void __kfence_free(void *addr) -{ - struct kfence_metadata *meta = addr_to_metadata((unsigned long)addr); - - /* - * If the objects of the cache are SLAB_TYPESAFE_BY_RCU, defer freeing - * the object, as the object page may be recycled for other-typed - * objects once it has been freed. meta->cache may be NULL if the cache - * was destroyed. - */ - if (unlikely(meta->cache && (meta->cache->flags & SLAB_TYPESAFE_BY_RCU))) - call_rcu(&meta->rcu_head, rcu_guarded_free); - else - kfence_guarded_free(addr, meta, false); -} - -bool kfence_handle_page_fault(unsigned long addr, bool is_write, struct pt_regs *regs) -{ - const int page_index = (addr - (unsigned long)__kfence_pool) / PAGE_SIZE; - struct kfence_metadata *to_report = NULL; - enum kfence_error_type error_type; - unsigned long flags; - - if (!is_kfence_address((void *)addr)) - return false; - - if (!READ_ONCE(kfence_enabled)) /* If disabled at runtime ... */ - return kfence_unprotect(addr); /* ... unprotect and proceed. */ - - atomic_long_inc(&counters[KFENCE_COUNTER_BUGS]); - - if (page_index % 2) { - /* This is a redzone, report a buffer overflow. */ - struct kfence_metadata *meta; - int distance = 0; - - meta = addr_to_metadata(addr - PAGE_SIZE); - if (meta && READ_ONCE(meta->state) == KFENCE_OBJECT_ALLOCATED) { - to_report = meta; - /* Data race ok; distance calculation approximate. */ - distance = addr - data_race(meta->addr + meta->size); - } - - meta = addr_to_metadata(addr + PAGE_SIZE); - if (meta && READ_ONCE(meta->state) == KFENCE_OBJECT_ALLOCATED) { - /* Data race ok; distance calculation approximate. */ - if (!to_report || distance > data_race(meta->addr) - addr) - to_report = meta; - } - - if (!to_report) - goto out; - - raw_spin_lock_irqsave(&to_report->lock, flags); - to_report->unprotected_page = addr; - error_type = KFENCE_ERROR_OOB; - - /* - * If the object was freed before we took the look we can still - * report this as an OOB -- the report will simply show the - * stacktrace of the free as well. - */ - } else { - to_report = addr_to_metadata(addr); - if (!to_report) - goto out; - - raw_spin_lock_irqsave(&to_report->lock, flags); - error_type = KFENCE_ERROR_UAF; - /* - * We may race with __kfence_alloc(), and it is possible that a - * freed object may be reallocated. We simply report this as a - * use-after-free, with the stack trace showing the place where - * the object was re-allocated. - */ - } - -out: - if (to_report) { - kfence_report_error(addr, is_write, regs, to_report, error_type); - raw_spin_unlock_irqrestore(&to_report->lock, flags); - } else { - /* This may be a UAF or OOB access, but we can't be sure. */ - kfence_report_error(addr, is_write, regs, NULL, KFENCE_ERROR_INVALID); - } - - return kfence_unprotect(addr); /* Unprotect and let access proceed. */ -} diff --git a/mm/kfence/kfence.h b/mm/kfence/kfence.h deleted file mode 100644 index 24065321ff8a..000000000000 --- a/mm/kfence/kfence.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Kernel Electric-Fence (KFENCE). For more info please see - * Documentation/dev-tools/kfence.rst. - * - * Copyright (C) 2020, Google LLC. - */ - -#ifndef MM_KFENCE_KFENCE_H -#define MM_KFENCE_KFENCE_H - -#include -#include -#include -#include - -#include "../slab.h" /* for struct kmem_cache */ - -/* - * Get the canary byte pattern for @addr. Use a pattern that varies based on the - * lower 3 bits of the address, to detect memory corruptions with higher - * probability, where similar constants are used. - */ -#define KFENCE_CANARY_PATTERN(addr) ((u8)0xaa ^ (u8)((unsigned long)(addr) & 0x7)) - -/* Maximum stack depth for reports. */ -#define KFENCE_STACK_DEPTH 64 - -/* KFENCE object states. */ -enum kfence_object_state { - KFENCE_OBJECT_UNUSED, /* Object is unused. */ - KFENCE_OBJECT_ALLOCATED, /* Object is currently allocated. */ - KFENCE_OBJECT_FREED, /* Object was allocated, and then freed. */ -}; - -/* Alloc/free tracking information. */ -struct kfence_track { - pid_t pid; - int num_stack_entries; - unsigned long stack_entries[KFENCE_STACK_DEPTH]; -}; - -/* KFENCE metadata per guarded allocation. */ -struct kfence_metadata { - struct list_head list; /* Freelist node; access under kfence_freelist_lock. */ - struct rcu_head rcu_head; /* For delayed freeing. */ - - /* - * Lock protecting below data; to ensure consistency of the below data, - * since the following may execute concurrently: __kfence_alloc(), - * __kfence_free(), kfence_handle_page_fault(). However, note that we - * cannot grab the same metadata off the freelist twice, and multiple - * __kfence_alloc() cannot run concurrently on the same metadata. - */ - raw_spinlock_t lock; - - /* The current state of the object; see above. */ - enum kfence_object_state state; - - /* - * Allocated object address; cannot be calculated from size, because of - * alignment requirements. - * - * Invariant: ALIGN_DOWN(addr, PAGE_SIZE) is constant. - */ - unsigned long addr; - - /* - * The size of the original allocation. - */ - size_t size; - - /* - * The kmem_cache cache of the last allocation; NULL if never allocated - * or the cache has already been destroyed. - */ - struct kmem_cache *cache; - - /* - * In case of an invalid access, the page that was unprotected; we - * optimistically only store one address. - */ - unsigned long unprotected_page; - - /* Allocation and free stack information. */ - struct kfence_track alloc_track; - struct kfence_track free_track; -}; - -extern struct kfence_metadata kfence_metadata[CONFIG_KFENCE_NUM_OBJECTS]; - -/* KFENCE error types for report generation. */ -enum kfence_error_type { - KFENCE_ERROR_OOB, /* Detected a out-of-bounds access. */ - KFENCE_ERROR_UAF, /* Detected a use-after-free access. */ - KFENCE_ERROR_CORRUPTION, /* Detected a memory corruption on free. */ - KFENCE_ERROR_INVALID, /* Invalid access of unknown type. */ - KFENCE_ERROR_INVALID_FREE, /* Invalid free. */ -}; - -void kfence_report_error(unsigned long address, bool is_write, struct pt_regs *regs, - const struct kfence_metadata *meta, enum kfence_error_type type); - -void kfence_print_object(struct seq_file *seq, const struct kfence_metadata *meta); - -#endif /* MM_KFENCE_KFENCE_H */ diff --git a/mm/kfence/kfence_test.c b/mm/kfence/kfence_test.c deleted file mode 100644 index b959548a47ce..000000000000 --- a/mm/kfence/kfence_test.c +++ /dev/null @@ -1,847 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Test cases for KFENCE memory safety error detector. Since the interface with - * which KFENCE's reports are obtained is via the console, this is the output we - * should verify. For each test case checks the presence (or absence) of - * generated reports. Relies on 'console' tracepoint to capture reports as they - * appear in the kernel log. - * - * Copyright (C) 2020, Google LLC. - * Author: Alexander Potapenko - * Marco Elver - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "kfence.h" - -/* Report as observed from console. */ -static struct { - spinlock_t lock; - int nlines; - char lines[2][256]; -} observed = { - .lock = __SPIN_LOCK_UNLOCKED(observed.lock), -}; - -/* Probe for console output: obtains observed lines of interest. */ -static void probe_console(void *ignore, const char *buf, size_t len) -{ - unsigned long flags; - int nlines; - - spin_lock_irqsave(&observed.lock, flags); - nlines = observed.nlines; - - if (strnstr(buf, "BUG: KFENCE: ", len) && strnstr(buf, "test_", len)) { - /* - * KFENCE report and related to the test. - * - * The provided @buf is not NUL-terminated; copy no more than - * @len bytes and let strscpy() add the missing NUL-terminator. - */ - strscpy(observed.lines[0], buf, min(len + 1, sizeof(observed.lines[0]))); - nlines = 1; - } else if (nlines == 1 && (strnstr(buf, "at 0x", len) || strnstr(buf, "of 0x", len))) { - strscpy(observed.lines[nlines++], buf, min(len + 1, sizeof(observed.lines[0]))); - } - - WRITE_ONCE(observed.nlines, nlines); /* Publish new nlines. */ - spin_unlock_irqrestore(&observed.lock, flags); -} - -/* Check if a report related to the test exists. */ -static bool report_available(void) -{ - return READ_ONCE(observed.nlines) == ARRAY_SIZE(observed.lines); -} - -/* Information we expect in a report. */ -struct expect_report { - enum kfence_error_type type; /* The type or error. */ - void *fn; /* Function pointer to expected function where access occurred. */ - char *addr; /* Address at which the bad access occurred. */ - bool is_write; /* Is access a write. */ -}; - -static const char *get_access_type(const struct expect_report *r) -{ - return r->is_write ? "write" : "read"; -} - -/* Check observed report matches information in @r. */ -static bool report_matches(const struct expect_report *r) -{ - bool ret = false; - unsigned long flags; - typeof(observed.lines) expect; - const char *end; - char *cur; - - /* Doubled-checked locking. */ - if (!report_available()) - return false; - - /* Generate expected report contents. */ - - /* Title */ - cur = expect[0]; - end = &expect[0][sizeof(expect[0]) - 1]; - switch (r->type) { - case KFENCE_ERROR_OOB: - cur += scnprintf(cur, end - cur, "BUG: KFENCE: out-of-bounds %s", - get_access_type(r)); - break; - case KFENCE_ERROR_UAF: - cur += scnprintf(cur, end - cur, "BUG: KFENCE: use-after-free %s", - get_access_type(r)); - break; - case KFENCE_ERROR_CORRUPTION: - cur += scnprintf(cur, end - cur, "BUG: KFENCE: memory corruption"); - break; - case KFENCE_ERROR_INVALID: - cur += scnprintf(cur, end - cur, "BUG: KFENCE: invalid %s", - get_access_type(r)); - break; - case KFENCE_ERROR_INVALID_FREE: - cur += scnprintf(cur, end - cur, "BUG: KFENCE: invalid free"); - break; - } - - scnprintf(cur, end - cur, " in %pS", r->fn); - /* The exact offset won't match, remove it; also strip module name. */ - cur = strchr(expect[0], '+'); - if (cur) - *cur = '\0'; - - /* Access information */ - cur = expect[1]; - end = &expect[1][sizeof(expect[1]) - 1]; - - switch (r->type) { - case KFENCE_ERROR_OOB: - cur += scnprintf(cur, end - cur, "Out-of-bounds %s at", get_access_type(r)); - break; - case KFENCE_ERROR_UAF: - cur += scnprintf(cur, end - cur, "Use-after-free %s at", get_access_type(r)); - break; - case KFENCE_ERROR_CORRUPTION: - cur += scnprintf(cur, end - cur, "Corrupted memory at"); - break; - case KFENCE_ERROR_INVALID: - cur += scnprintf(cur, end - cur, "Invalid %s at", get_access_type(r)); - break; - case KFENCE_ERROR_INVALID_FREE: - cur += scnprintf(cur, end - cur, "Invalid free of"); - break; - } - - cur += scnprintf(cur, end - cur, " 0x%p", (void *)r->addr); - - spin_lock_irqsave(&observed.lock, flags); - if (!report_available()) - goto out; /* A new report is being captured. */ - - /* Finally match expected output to what we actually observed. */ - ret = strstr(observed.lines[0], expect[0]) && strstr(observed.lines[1], expect[1]); -out: - spin_unlock_irqrestore(&observed.lock, flags); - return ret; -} - -/* ===== Test cases ===== */ - -#define TEST_PRIV_WANT_MEMCACHE ((void *)1) - -/* Cache used by tests; if NULL, allocate from kmalloc instead. */ -static struct kmem_cache *test_cache; - -static size_t setup_test_cache(struct kunit *test, size_t size, slab_flags_t flags, - void (*ctor)(void *)) -{ - if (test->priv != TEST_PRIV_WANT_MEMCACHE) - return size; - - kunit_info(test, "%s: size=%zu, ctor=%ps\n", __func__, size, ctor); - - /* - * Use SLAB_NOLEAKTRACE to prevent merging with existing caches. Any - * other flag in SLAB_NEVER_MERGE also works. Use SLAB_ACCOUNT to - * allocate via memcg, if enabled. - */ - flags |= SLAB_NOLEAKTRACE | SLAB_ACCOUNT; - test_cache = kmem_cache_create("test", size, 1, flags, ctor); - KUNIT_ASSERT_TRUE_MSG(test, test_cache, "could not create cache"); - - return size; -} - -static void test_cache_destroy(void) -{ - if (!test_cache) - return; - - kmem_cache_destroy(test_cache); - test_cache = NULL; -} - -static inline size_t kmalloc_cache_alignment(size_t size) -{ - return kmalloc_caches[kmalloc_type(GFP_KERNEL)][kmalloc_index(size)]->align; -} - -/* Must always inline to match stack trace against caller. */ -static __always_inline void test_free(void *ptr) -{ - if (test_cache) - kmem_cache_free(test_cache, ptr); - else - kfree(ptr); -} - -/* - * If this should be a KFENCE allocation, and on which side the allocation and - * the closest guard page should be. - */ -enum allocation_policy { - ALLOCATE_ANY, /* KFENCE, any side. */ - ALLOCATE_LEFT, /* KFENCE, left side of page. */ - ALLOCATE_RIGHT, /* KFENCE, right side of page. */ - ALLOCATE_NONE, /* No KFENCE allocation. */ -}; - -/* - * Try to get a guarded allocation from KFENCE. Uses either kmalloc() or the - * current test_cache if set up. - */ -static void *test_alloc(struct kunit *test, size_t size, gfp_t gfp, enum allocation_policy policy) -{ - void *alloc; - unsigned long timeout, resched_after; - const char *policy_name; - - switch (policy) { - case ALLOCATE_ANY: - policy_name = "any"; - break; - case ALLOCATE_LEFT: - policy_name = "left"; - break; - case ALLOCATE_RIGHT: - policy_name = "right"; - break; - case ALLOCATE_NONE: - policy_name = "none"; - break; - } - - kunit_info(test, "%s: size=%zu, gfp=%x, policy=%s, cache=%i\n", __func__, size, gfp, - policy_name, !!test_cache); - - /* - * 100x the sample interval should be more than enough to ensure we get - * a KFENCE allocation eventually. - */ - timeout = jiffies + msecs_to_jiffies(100 * CONFIG_KFENCE_SAMPLE_INTERVAL); - /* - * Especially for non-preemption kernels, ensure the allocation-gate - * timer can catch up: after @resched_after, every failed allocation - * attempt yields, to ensure the allocation-gate timer is scheduled. - */ - resched_after = jiffies + msecs_to_jiffies(CONFIG_KFENCE_SAMPLE_INTERVAL); - do { - if (test_cache) - alloc = kmem_cache_alloc(test_cache, gfp); - else - alloc = kmalloc(size, gfp); - - if (is_kfence_address(alloc)) { - if (policy == ALLOCATE_ANY) - return alloc; - if (policy == ALLOCATE_LEFT && IS_ALIGNED((unsigned long)alloc, PAGE_SIZE)) - return alloc; - if (policy == ALLOCATE_RIGHT && - !IS_ALIGNED((unsigned long)alloc, PAGE_SIZE)) - return alloc; - } else if (policy == ALLOCATE_NONE) - return alloc; - - test_free(alloc); - - if (time_after(jiffies, resched_after)) - cond_resched(); - } while (time_before(jiffies, timeout)); - - KUNIT_ASSERT_TRUE_MSG(test, false, "failed to allocate from KFENCE"); - return NULL; /* Unreachable. */ -} - -static void test_out_of_bounds_read(struct kunit *test) -{ - size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_OOB, - .fn = test_out_of_bounds_read, - .is_write = false, - }; - char *buf; - - setup_test_cache(test, size, 0, NULL); - - /* - * If we don't have our own cache, adjust based on alignment, so that we - * actually access guard pages on either side. - */ - if (!test_cache) - size = kmalloc_cache_alignment(size); - - /* Test both sides. */ - - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_LEFT); - expect.addr = buf - 1; - READ_ONCE(*expect.addr); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); - test_free(buf); - - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_RIGHT); - expect.addr = buf + size; - READ_ONCE(*expect.addr); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); - test_free(buf); -} - -static void test_out_of_bounds_write(struct kunit *test) -{ - size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_OOB, - .fn = test_out_of_bounds_write, - .is_write = true, - }; - char *buf; - - setup_test_cache(test, size, 0, NULL); - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_LEFT); - expect.addr = buf - 1; - WRITE_ONCE(*expect.addr, 42); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); - test_free(buf); -} - -static void test_use_after_free_read(struct kunit *test) -{ - const size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_UAF, - .fn = test_use_after_free_read, - .is_write = false, - }; - - setup_test_cache(test, size, 0, NULL); - expect.addr = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - test_free(expect.addr); - READ_ONCE(*expect.addr); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -static void test_double_free(struct kunit *test) -{ - const size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_INVALID_FREE, - .fn = test_double_free, - }; - - setup_test_cache(test, size, 0, NULL); - expect.addr = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - test_free(expect.addr); - test_free(expect.addr); /* Double-free. */ - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -static void test_invalid_addr_free(struct kunit *test) -{ - const size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_INVALID_FREE, - .fn = test_invalid_addr_free, - }; - char *buf; - - setup_test_cache(test, size, 0, NULL); - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - expect.addr = buf + 1; /* Free on invalid address. */ - test_free(expect.addr); /* Invalid address free. */ - test_free(buf); /* No error. */ - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -static void test_corruption(struct kunit *test) -{ - size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_CORRUPTION, - .fn = test_corruption, - }; - char *buf; - - setup_test_cache(test, size, 0, NULL); - - /* Test both sides. */ - - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_LEFT); - expect.addr = buf + size; - WRITE_ONCE(*expect.addr, 42); - test_free(buf); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); - - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_RIGHT); - expect.addr = buf - 1; - WRITE_ONCE(*expect.addr, 42); - test_free(buf); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -/* - * KFENCE is unable to detect an OOB if the allocation's alignment requirements - * leave a gap between the object and the guard page. Specifically, an - * allocation of e.g. 73 bytes is aligned on 8 and 128 bytes for SLUB or SLAB - * respectively. Therefore it is impossible for the allocated object to - * contiguously line up with the right guard page. - * - * However, we test that an access to memory beyond the gap results in KFENCE - * detecting an OOB access. - */ -static void test_kmalloc_aligned_oob_read(struct kunit *test) -{ - const size_t size = 73; - const size_t align = kmalloc_cache_alignment(size); - struct expect_report expect = { - .type = KFENCE_ERROR_OOB, - .fn = test_kmalloc_aligned_oob_read, - .is_write = false, - }; - char *buf; - - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_RIGHT); - - /* - * The object is offset to the right, so there won't be an OOB to the - * left of it. - */ - READ_ONCE(*(buf - 1)); - KUNIT_EXPECT_FALSE(test, report_available()); - - /* - * @buf must be aligned on @align, therefore buf + size belongs to the - * same page -> no OOB. - */ - READ_ONCE(*(buf + size)); - KUNIT_EXPECT_FALSE(test, report_available()); - - /* Overflowing by @align bytes will result in an OOB. */ - expect.addr = buf + size + align; - READ_ONCE(*expect.addr); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); - - test_free(buf); -} - -static void test_kmalloc_aligned_oob_write(struct kunit *test) -{ - const size_t size = 73; - struct expect_report expect = { - .type = KFENCE_ERROR_CORRUPTION, - .fn = test_kmalloc_aligned_oob_write, - }; - char *buf; - - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_RIGHT); - /* - * The object is offset to the right, so we won't get a page - * fault immediately after it. - */ - expect.addr = buf + size; - WRITE_ONCE(*expect.addr, READ_ONCE(*expect.addr) + 1); - KUNIT_EXPECT_FALSE(test, report_available()); - test_free(buf); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -/* Test cache shrinking and destroying with KFENCE. */ -static void test_shrink_memcache(struct kunit *test) -{ - const size_t size = 32; - void *buf; - - setup_test_cache(test, size, 0, NULL); - KUNIT_EXPECT_TRUE(test, test_cache); - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - kmem_cache_shrink(test_cache); - test_free(buf); - - KUNIT_EXPECT_FALSE(test, report_available()); -} - -static void ctor_set_x(void *obj) -{ - /* Every object has at least 8 bytes. */ - memset(obj, 'x', 8); -} - -/* Ensure that SL*B does not modify KFENCE objects on bulk free. */ -static void test_free_bulk(struct kunit *test) -{ - int iter; - - for (iter = 0; iter < 5; iter++) { - const size_t size = setup_test_cache(test, 8 + prandom_u32_max(300), 0, - (iter & 1) ? ctor_set_x : NULL); - void *objects[] = { - test_alloc(test, size, GFP_KERNEL, ALLOCATE_RIGHT), - test_alloc(test, size, GFP_KERNEL, ALLOCATE_NONE), - test_alloc(test, size, GFP_KERNEL, ALLOCATE_LEFT), - test_alloc(test, size, GFP_KERNEL, ALLOCATE_NONE), - test_alloc(test, size, GFP_KERNEL, ALLOCATE_NONE), - }; - - kmem_cache_free_bulk(test_cache, ARRAY_SIZE(objects), objects); - KUNIT_ASSERT_FALSE(test, report_available()); - test_cache_destroy(); - } -} - -/* Test init-on-free works. */ -static void test_init_on_free(struct kunit *test) -{ - const size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_UAF, - .fn = test_init_on_free, - .is_write = false, - }; - int i; - - if (!IS_ENABLED(CONFIG_INIT_ON_FREE_DEFAULT_ON)) - return; - /* Assume it hasn't been disabled on command line. */ - - setup_test_cache(test, size, 0, NULL); - expect.addr = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - for (i = 0; i < size; i++) - expect.addr[i] = i + 1; - test_free(expect.addr); - - for (i = 0; i < size; i++) { - /* - * This may fail if the page was recycled by KFENCE and then - * written to again -- this however, is near impossible with a - * default config. - */ - KUNIT_EXPECT_EQ(test, expect.addr[i], (char)0); - - if (!i) /* Only check first access to not fail test if page is ever re-protected. */ - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); - } -} - -/* Ensure that constructors work properly. */ -static void test_memcache_ctor(struct kunit *test) -{ - const size_t size = 32; - char *buf; - int i; - - setup_test_cache(test, size, 0, ctor_set_x); - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - - for (i = 0; i < 8; i++) - KUNIT_EXPECT_EQ(test, buf[i], (char)'x'); - - test_free(buf); - - KUNIT_EXPECT_FALSE(test, report_available()); -} - -/* Test that memory is zeroed if requested. */ -static void test_gfpzero(struct kunit *test) -{ - const size_t size = PAGE_SIZE; /* PAGE_SIZE so we can use ALLOCATE_ANY. */ - char *buf1, *buf2; - int i; - - if (CONFIG_KFENCE_SAMPLE_INTERVAL > 100) { - kunit_warn(test, "skipping ... would take too long\n"); - return; - } - - setup_test_cache(test, size, 0, NULL); - buf1 = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - for (i = 0; i < size; i++) - buf1[i] = i + 1; - test_free(buf1); - - /* Try to get same address again -- this can take a while. */ - for (i = 0;; i++) { - buf2 = test_alloc(test, size, GFP_KERNEL | __GFP_ZERO, ALLOCATE_ANY); - if (buf1 == buf2) - break; - test_free(buf2); - - if (i == CONFIG_KFENCE_NUM_OBJECTS) { - kunit_warn(test, "giving up ... cannot get same object back\n"); - return; - } - } - - for (i = 0; i < size; i++) - KUNIT_EXPECT_EQ(test, buf2[i], (char)0); - - test_free(buf2); - - KUNIT_EXPECT_FALSE(test, report_available()); -} - -static void test_invalid_access(struct kunit *test) -{ - const struct expect_report expect = { - .type = KFENCE_ERROR_INVALID, - .fn = test_invalid_access, - .addr = &__kfence_pool[10], - .is_write = false, - }; - - READ_ONCE(__kfence_pool[10]); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -/* Test SLAB_TYPESAFE_BY_RCU works. */ -static void test_memcache_typesafe_by_rcu(struct kunit *test) -{ - const size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_UAF, - .fn = test_memcache_typesafe_by_rcu, - .is_write = false, - }; - - setup_test_cache(test, size, SLAB_TYPESAFE_BY_RCU, NULL); - KUNIT_EXPECT_TRUE(test, test_cache); /* Want memcache. */ - - expect.addr = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - *expect.addr = 42; - - rcu_read_lock(); - test_free(expect.addr); - KUNIT_EXPECT_EQ(test, *expect.addr, (char)42); - /* - * Up to this point, memory should not have been freed yet, and - * therefore there should be no KFENCE report from the above access. - */ - rcu_read_unlock(); - - /* Above access to @expect.addr should not have generated a report! */ - KUNIT_EXPECT_FALSE(test, report_available()); - - /* Only after rcu_barrier() is the memory guaranteed to be freed. */ - rcu_barrier(); - - /* Expect use-after-free. */ - KUNIT_EXPECT_EQ(test, *expect.addr, (char)42); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -/* Test krealloc(). */ -static void test_krealloc(struct kunit *test) -{ - const size_t size = 32; - const struct expect_report expect = { - .type = KFENCE_ERROR_UAF, - .fn = test_krealloc, - .addr = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY), - .is_write = false, - }; - char *buf = expect.addr; - int i; - - KUNIT_EXPECT_FALSE(test, test_cache); - KUNIT_EXPECT_EQ(test, ksize(buf), size); /* Precise size match after KFENCE alloc. */ - for (i = 0; i < size; i++) - buf[i] = i + 1; - - /* Check that we successfully change the size. */ - buf = krealloc(buf, size * 3, GFP_KERNEL); /* Grow. */ - /* Note: Might no longer be a KFENCE alloc. */ - KUNIT_EXPECT_GE(test, ksize(buf), size * 3); - for (i = 0; i < size; i++) - KUNIT_EXPECT_EQ(test, buf[i], (char)(i + 1)); - for (; i < size * 3; i++) /* Fill to extra bytes. */ - buf[i] = i + 1; - - buf = krealloc(buf, size * 2, GFP_KERNEL); /* Shrink. */ - KUNIT_EXPECT_GE(test, ksize(buf), size * 2); - for (i = 0; i < size * 2; i++) - KUNIT_EXPECT_EQ(test, buf[i], (char)(i + 1)); - - buf = krealloc(buf, 0, GFP_KERNEL); /* Free. */ - KUNIT_EXPECT_EQ(test, (unsigned long)buf, (unsigned long)ZERO_SIZE_PTR); - KUNIT_ASSERT_FALSE(test, report_available()); /* No reports yet! */ - - READ_ONCE(*expect.addr); /* Ensure krealloc() actually freed earlier KFENCE object. */ - KUNIT_ASSERT_TRUE(test, report_matches(&expect)); -} - -/* Test that some objects from a bulk allocation belong to KFENCE pool. */ -static void test_memcache_alloc_bulk(struct kunit *test) -{ - const size_t size = 32; - bool pass = false; - unsigned long timeout; - - setup_test_cache(test, size, 0, NULL); - KUNIT_EXPECT_TRUE(test, test_cache); /* Want memcache. */ - /* - * 100x the sample interval should be more than enough to ensure we get - * a KFENCE allocation eventually. - */ - timeout = jiffies + msecs_to_jiffies(100 * CONFIG_KFENCE_SAMPLE_INTERVAL); - do { - void *objects[100]; - int i, num = kmem_cache_alloc_bulk(test_cache, GFP_ATOMIC, ARRAY_SIZE(objects), - objects); - if (!num) - continue; - for (i = 0; i < ARRAY_SIZE(objects); i++) { - if (is_kfence_address(objects[i])) { - pass = true; - break; - } - } - kmem_cache_free_bulk(test_cache, num, objects); - /* - * kmem_cache_alloc_bulk() disables interrupts, and calling it - * in a tight loop may not give KFENCE a chance to switch the - * static branch. Call cond_resched() to let KFENCE chime in. - */ - cond_resched(); - } while (!pass && time_before(jiffies, timeout)); - - KUNIT_EXPECT_TRUE(test, pass); - KUNIT_EXPECT_FALSE(test, report_available()); -} - -/* - * KUnit does not provide a way to provide arguments to tests, and we encode - * additional info in the name. Set up 2 tests per test case, one using the - * default allocator, and another using a custom memcache (suffix '-memcache'). - */ -#define KFENCE_KUNIT_CASE(test_name) \ - { .run_case = test_name, .name = #test_name }, \ - { .run_case = test_name, .name = #test_name "-memcache" } - -static struct kunit_case kfence_test_cases[] = { - KFENCE_KUNIT_CASE(test_out_of_bounds_read), - KFENCE_KUNIT_CASE(test_out_of_bounds_write), - KFENCE_KUNIT_CASE(test_use_after_free_read), - KFENCE_KUNIT_CASE(test_double_free), - KFENCE_KUNIT_CASE(test_invalid_addr_free), - KFENCE_KUNIT_CASE(test_corruption), - KFENCE_KUNIT_CASE(test_free_bulk), - KFENCE_KUNIT_CASE(test_init_on_free), - KUNIT_CASE(test_kmalloc_aligned_oob_read), - KUNIT_CASE(test_kmalloc_aligned_oob_write), - KUNIT_CASE(test_shrink_memcache), - KUNIT_CASE(test_memcache_ctor), - KUNIT_CASE(test_invalid_access), - KUNIT_CASE(test_gfpzero), - KUNIT_CASE(test_memcache_typesafe_by_rcu), - KUNIT_CASE(test_krealloc), - KUNIT_CASE(test_memcache_alloc_bulk), - {}, -}; - -/* ===== End test cases ===== */ - -static int test_init(struct kunit *test) -{ - unsigned long flags; - int i; - - spin_lock_irqsave(&observed.lock, flags); - for (i = 0; i < ARRAY_SIZE(observed.lines); i++) - observed.lines[i][0] = '\0'; - observed.nlines = 0; - spin_unlock_irqrestore(&observed.lock, flags); - - /* Any test with 'memcache' in its name will want a memcache. */ - if (strstr(test->name, "memcache")) - test->priv = TEST_PRIV_WANT_MEMCACHE; - else - test->priv = NULL; - - return 0; -} - -static void test_exit(struct kunit *test) -{ - test_cache_destroy(); -} - -static struct kunit_suite kfence_test_suite = { - .name = "kfence", - .test_cases = kfence_test_cases, - .init = test_init, - .exit = test_exit, -}; -static struct kunit_suite *kfence_test_suites[] = { &kfence_test_suite, NULL }; - -static void register_tracepoints(struct tracepoint *tp, void *ignore) -{ - check_trace_callback_type_console(probe_console); - if (!strcmp(tp->name, "console")) - WARN_ON(tracepoint_probe_register(tp, probe_console, NULL)); -} - -static void unregister_tracepoints(struct tracepoint *tp, void *ignore) -{ - if (!strcmp(tp->name, "console")) - tracepoint_probe_unregister(tp, probe_console, NULL); -} - -/* - * We only want to do tracepoints setup and teardown once, therefore we have to - * customize the init and exit functions and cannot rely on kunit_test_suite(). - */ -static int __init kfence_test_init(void) -{ - /* - * Because we want to be able to build the test as a module, we need to - * iterate through all known tracepoints, since the static registration - * won't work here. - */ - for_each_kernel_tracepoint(register_tracepoints, NULL); - return __kunit_test_suites_init(kfence_test_suites); -} - -static void kfence_test_exit(void) -{ - __kunit_test_suites_exit(kfence_test_suites); - for_each_kernel_tracepoint(unregister_tracepoints, NULL); - tracepoint_synchronize_unregister(); -} - -late_initcall(kfence_test_init); -module_exit(kfence_test_exit); - -MODULE_LICENSE("GPL v2"); -MODULE_AUTHOR("Alexander Potapenko , Marco Elver "); diff --git a/mm/kfence/report.c b/mm/kfence/report.c deleted file mode 100644 index e3f71451ad9e..000000000000 --- a/mm/kfence/report.c +++ /dev/null @@ -1,268 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * KFENCE reporting. - * - * Copyright (C) 2020, Google LLC. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "kfence.h" - -/* May be overridden by . */ -#ifndef ARCH_FUNC_PREFIX -#define ARCH_FUNC_PREFIX "" -#endif - -extern bool no_hash_pointers; - -/* Helper function to either print to a seq_file or to console. */ -__printf(2, 3) -static void seq_con_printf(struct seq_file *seq, const char *fmt, ...) -{ - va_list args; - - va_start(args, fmt); - if (seq) - seq_vprintf(seq, fmt, args); - else - vprintk(fmt, args); - va_end(args); -} - -/* - * Get the number of stack entries to skip to get out of MM internals. @type is - * optional, and if set to NULL, assumes an allocation or free stack. - */ -static int get_stack_skipnr(const unsigned long stack_entries[], int num_entries, - const enum kfence_error_type *type) -{ - char buf[64]; - int skipnr, fallback = 0; - - if (type) { - /* Depending on error type, find different stack entries. */ - switch (*type) { - case KFENCE_ERROR_UAF: - case KFENCE_ERROR_OOB: - case KFENCE_ERROR_INVALID: - /* - * kfence_handle_page_fault() may be called with pt_regs - * set to NULL; in that case we'll simply show the full - * stack trace. - */ - return 0; - case KFENCE_ERROR_CORRUPTION: - case KFENCE_ERROR_INVALID_FREE: - break; - } - } - - for (skipnr = 0; skipnr < num_entries; skipnr++) { - int len = scnprintf(buf, sizeof(buf), "%ps", (void *)stack_entries[skipnr]); - - if (str_has_prefix(buf, ARCH_FUNC_PREFIX "kfence_") || - str_has_prefix(buf, ARCH_FUNC_PREFIX "__kfence_") || - !strncmp(buf, ARCH_FUNC_PREFIX "__slab_free", len)) { - /* - * In case of tail calls from any of the below - * to any of the above. - */ - fallback = skipnr + 1; - } - - /* Also the *_bulk() variants by only checking prefixes. */ - if (str_has_prefix(buf, ARCH_FUNC_PREFIX "kfree") || - str_has_prefix(buf, ARCH_FUNC_PREFIX "kmem_cache_free") || - str_has_prefix(buf, ARCH_FUNC_PREFIX "__kmalloc") || - str_has_prefix(buf, ARCH_FUNC_PREFIX "kmem_cache_alloc")) - goto found; - } - if (fallback < num_entries) - return fallback; -found: - skipnr++; - return skipnr < num_entries ? skipnr : 0; -} - -static void kfence_print_stack(struct seq_file *seq, const struct kfence_metadata *meta, - bool show_alloc) -{ - const struct kfence_track *track = show_alloc ? &meta->alloc_track : &meta->free_track; - - if (track->num_stack_entries) { - /* Skip allocation/free internals stack. */ - int i = get_stack_skipnr(track->stack_entries, track->num_stack_entries, NULL); - - /* stack_trace_seq_print() does not exist; open code our own. */ - for (; i < track->num_stack_entries; i++) - seq_con_printf(seq, " %pS\n", (void *)track->stack_entries[i]); - } else { - seq_con_printf(seq, " no %s stack\n", show_alloc ? "allocation" : "deallocation"); - } -} - -void kfence_print_object(struct seq_file *seq, const struct kfence_metadata *meta) -{ - const int size = abs(meta->size); - const unsigned long start = meta->addr; - const struct kmem_cache *const cache = meta->cache; - - lockdep_assert_held(&meta->lock); - - if (meta->state == KFENCE_OBJECT_UNUSED) { - seq_con_printf(seq, "kfence-#%td unused\n", meta - kfence_metadata); - return; - } - - seq_con_printf(seq, - "kfence-#%td [0x%p-0x%p" - ", size=%d, cache=%s] allocated by task %d:\n", - meta - kfence_metadata, (void *)start, (void *)(start + size - 1), size, - (cache && cache->name) ? cache->name : "", meta->alloc_track.pid); - kfence_print_stack(seq, meta, true); - - if (meta->state == KFENCE_OBJECT_FREED) { - seq_con_printf(seq, "\nfreed by task %d:\n", meta->free_track.pid); - kfence_print_stack(seq, meta, false); - } -} - -/* - * Show bytes at @addr that are different from the expected canary values, up to - * @max_bytes. - */ -static void print_diff_canary(unsigned long address, size_t bytes_to_show, - const struct kfence_metadata *meta) -{ - const unsigned long show_until_addr = address + bytes_to_show; - const u8 *cur, *end; - - /* Do not show contents of object nor read into following guard page. */ - end = (const u8 *)(address < meta->addr ? min(show_until_addr, meta->addr) - : min(show_until_addr, PAGE_ALIGN(address))); - - pr_cont("["); - for (cur = (const u8 *)address; cur < end; cur++) { - if (*cur == KFENCE_CANARY_PATTERN(cur)) - pr_cont(" ."); - else if (no_hash_pointers) - pr_cont(" 0x%02x", *cur); - else /* Do not leak kernel memory in non-debug builds. */ - pr_cont(" !"); - } - pr_cont(" ]"); -} - -static const char *get_access_type(bool is_write) -{ - return is_write ? "write" : "read"; -} - -void kfence_report_error(unsigned long address, bool is_write, struct pt_regs *regs, - const struct kfence_metadata *meta, enum kfence_error_type type) -{ - unsigned long stack_entries[KFENCE_STACK_DEPTH] = { 0 }; - const ptrdiff_t object_index = meta ? meta - kfence_metadata : -1; - int num_stack_entries; - int skipnr = 0; - - if (regs) { - num_stack_entries = stack_trace_save_regs(regs, stack_entries, KFENCE_STACK_DEPTH, 0); - } else { - num_stack_entries = stack_trace_save(stack_entries, KFENCE_STACK_DEPTH, 1); - skipnr = get_stack_skipnr(stack_entries, num_stack_entries, &type); - } - - /* Require non-NULL meta, except if KFENCE_ERROR_INVALID. */ - if (WARN_ON(type != KFENCE_ERROR_INVALID && !meta)) - return; - - if (meta) - lockdep_assert_held(&meta->lock); - /* - * Because we may generate reports in printk-unfriendly parts of the - * kernel, such as scheduler code, the use of printk() could deadlock. - * Until such time that all printing code here is safe in all parts of - * the kernel, accept the risk, and just get our message out (given the - * system might already behave unpredictably due to the memory error). - * As such, also disable lockdep to hide warnings, and avoid disabling - * lockdep for the rest of the kernel. - */ - lockdep_off(); - - pr_err("==================================================================\n"); - /* Print report header. */ - switch (type) { - case KFENCE_ERROR_OOB: { - const bool left_of_object = address < meta->addr; - - pr_err("BUG: KFENCE: out-of-bounds %s in %pS\n\n", get_access_type(is_write), - (void *)stack_entries[skipnr]); - pr_err("Out-of-bounds %s at 0x%p (%luB %s of kfence-#%td):\n", - get_access_type(is_write), (void *)address, - left_of_object ? meta->addr - address : address - meta->addr, - left_of_object ? "left" : "right", object_index); - break; - } - case KFENCE_ERROR_UAF: - pr_err("BUG: KFENCE: use-after-free %s in %pS\n\n", get_access_type(is_write), - (void *)stack_entries[skipnr]); - pr_err("Use-after-free %s at 0x%p (in kfence-#%td):\n", - get_access_type(is_write), (void *)address, object_index); - break; - case KFENCE_ERROR_CORRUPTION: - pr_err("BUG: KFENCE: memory corruption in %pS\n\n", (void *)stack_entries[skipnr]); - pr_err("Corrupted memory at 0x%p ", (void *)address); - print_diff_canary(address, 16, meta); - pr_cont(" (in kfence-#%td):\n", object_index); - break; - case KFENCE_ERROR_INVALID: - pr_err("BUG: KFENCE: invalid %s in %pS\n\n", get_access_type(is_write), - (void *)stack_entries[skipnr]); - pr_err("Invalid %s at 0x%p:\n", get_access_type(is_write), - (void *)address); - break; - case KFENCE_ERROR_INVALID_FREE: - pr_err("BUG: KFENCE: invalid free in %pS\n\n", (void *)stack_entries[skipnr]); - pr_err("Invalid free of 0x%p (in kfence-#%td):\n", (void *)address, - object_index); - break; - } - - /* Print stack trace and object info. */ - stack_trace_print(stack_entries + skipnr, num_stack_entries - skipnr, 0); - - if (meta) { - pr_err("\n"); - kfence_print_object(NULL, meta); - } - - /* Print report footer. */ - pr_err("\n"); - if (no_hash_pointers && regs) - show_regs(regs); - else - dump_stack_print_info(KERN_ERR); - trace_error_report_end(ERROR_DETECTOR_KFENCE, address); - pr_err("==================================================================\n"); - - lockdep_on(); - - if (panic_on_warn) - panic("panic_on_warn set ...\n"); - - /* We encountered a memory unsafety error, taint the kernel! */ - add_taint(TAINT_BAD_PAGE, LOCKDEP_STILL_OK); -} diff --git a/mm/kmemleak.c b/mm/kmemleak.c index dce9e2a42549..a7fc6b23c37e 100644 --- a/mm/kmemleak.c +++ b/mm/kmemleak.c @@ -97,7 +97,6 @@ #include #include -#include #include #include @@ -593,7 +592,7 @@ static struct kmemleak_object *create_object(unsigned long ptr, size_t size, atomic_set(&object->use_count, 1); object->flags = OBJECT_ALLOCATED; object->pointer = ptr; - object->size = kfence_ksize((void *)ptr) ?: size; + object->size = size; object->excess_ref = 0; object->min_count = min_count; object->count = 0; /* white color initially */ diff --git a/mm/slab.c b/mm/slab.c index a9a5fb49373d..1a75a1204ff4 100644 --- a/mm/slab.c +++ b/mm/slab.c @@ -100,7 +100,6 @@ #include #include #include -#include #include #include #include @@ -3220,28 +3219,18 @@ must_grow: } static __always_inline void * -slab_alloc_node(struct kmem_cache *cachep, gfp_t flags, int nodeid, size_t orig_size, +slab_alloc_node(struct kmem_cache *cachep, gfp_t flags, int nodeid, unsigned long caller) { unsigned long save_flags; void *ptr; int slab_node = numa_mem_id(); - struct kmem_cache *orig_cachep = cachep; flags &= gfp_allowed_mask; cachep = slab_pre_alloc_hook(cachep, flags); if (unlikely(!cachep)) return NULL; - /* - * 5.4 note: passing in original cachep to avoid problems with memcg - * accounting. Making KFENCE properly work with memcgs on older kernels - * is not worth the effort. - */ - ptr = kfence_alloc(orig_cachep, orig_size, flags); - if (unlikely(ptr)) - goto out_hooks; - cache_alloc_debugcheck_before(cachep, flags); local_irq_save(save_flags); @@ -3274,7 +3263,6 @@ slab_alloc_node(struct kmem_cache *cachep, gfp_t flags, int nodeid, size_t orig_ if (unlikely(slab_want_init_on_alloc(flags, cachep)) && ptr) memset(ptr, 0, cachep->object_size); -out_hooks: slab_post_alloc_hook(cachep, flags, 1, &ptr); return ptr; } @@ -3312,26 +3300,16 @@ __do_cache_alloc(struct kmem_cache *cachep, gfp_t flags) #endif /* CONFIG_NUMA */ static __always_inline void * -slab_alloc(struct kmem_cache *cachep, gfp_t flags, size_t orig_size, unsigned long caller) +slab_alloc(struct kmem_cache *cachep, gfp_t flags, unsigned long caller) { unsigned long save_flags; void *objp; - struct kmem_cache *orig_cachep = cachep; flags &= gfp_allowed_mask; cachep = slab_pre_alloc_hook(cachep, flags); if (unlikely(!cachep)) return NULL; - /* - * 5.4 note: passing in original cachep to avoid problems with memcg - * accounting. Making KFENCE properly work with memcgs on older kernels - * is not worth the effort. - */ - objp = kfence_alloc(orig_cachep, orig_size, flags); - if (unlikely(objp)) - goto out; - cache_alloc_debugcheck_before(cachep, flags); local_irq_save(save_flags); objp = __do_cache_alloc(cachep, flags); @@ -3342,7 +3320,6 @@ slab_alloc(struct kmem_cache *cachep, gfp_t flags, size_t orig_size, unsigned lo if (unlikely(slab_want_init_on_alloc(flags, cachep)) && objp) memset(objp, 0, cachep->object_size); -out: slab_post_alloc_hook(cachep, flags, 1, &objp); return objp; } @@ -3448,15 +3425,6 @@ free_done: static __always_inline void __cache_free(struct kmem_cache *cachep, void *objp, unsigned long caller) { - if (is_kfence_address(objp)) { - kmemleak_free_recursive(objp, cachep->flags); - __kfence_free(objp); - return; - } - - if (unlikely(slab_want_init_on_free(cachep))) - memset(objp, 0, cachep->object_size); - /* Put the object into the quarantine, don't touch it for now. */ if (kasan_slab_free(cachep, objp, _RET_IP_)) return; @@ -3470,6 +3438,8 @@ void ___cache_free(struct kmem_cache *cachep, void *objp, struct array_cache *ac = cpu_cache_get(cachep); check_irq_off(); + if (unlikely(slab_want_init_on_free(cachep))) + memset(objp, 0, cachep->object_size); kmemleak_free_recursive(objp, cachep->flags); objp = cache_free_debugcheck(cachep, objp, caller); @@ -3514,7 +3484,7 @@ void ___cache_free(struct kmem_cache *cachep, void *objp, */ void *kmem_cache_alloc(struct kmem_cache *cachep, gfp_t flags) { - void *ret = slab_alloc(cachep, flags, cachep->object_size, _RET_IP_); + void *ret = slab_alloc(cachep, flags, _RET_IP_); trace_kmem_cache_alloc(_RET_IP_, ret, cachep->object_size, cachep->size, flags); @@ -3537,7 +3507,6 @@ int kmem_cache_alloc_bulk(struct kmem_cache *s, gfp_t flags, size_t size, void **p) { size_t i; - struct kmem_cache *root_s = s; s = slab_pre_alloc_hook(s, flags); if (!s) @@ -3547,13 +3516,7 @@ int kmem_cache_alloc_bulk(struct kmem_cache *s, gfp_t flags, size_t size, local_irq_disable(); for (i = 0; i < size; i++) { - /* - * 5.4 note: passing in original cachep to avoid problems with - * memcg accounting. Making KFENCE properly work with memcgs on - * older kernels is not worth the effort. - */ - void *objp = kfence_alloc(root_s, s->object_size, flags) ?: - __do_cache_alloc(s, flags); + void *objp = __do_cache_alloc(s, flags); if (unlikely(!objp)) goto error; @@ -3586,7 +3549,7 @@ kmem_cache_alloc_trace(struct kmem_cache *cachep, gfp_t flags, size_t size) { void *ret; - ret = slab_alloc(cachep, flags, size, _RET_IP_); + ret = slab_alloc(cachep, flags, _RET_IP_); ret = kasan_kmalloc(cachep, ret, size, flags); trace_kmalloc(_RET_IP_, ret, @@ -3612,7 +3575,7 @@ EXPORT_SYMBOL(kmem_cache_alloc_trace); */ void *kmem_cache_alloc_node(struct kmem_cache *cachep, gfp_t flags, int nodeid) { - void *ret = slab_alloc_node(cachep, flags, nodeid, cachep->object_size, _RET_IP_); + void *ret = slab_alloc_node(cachep, flags, nodeid, _RET_IP_); trace_kmem_cache_alloc_node(_RET_IP_, ret, cachep->object_size, cachep->size, @@ -3630,7 +3593,7 @@ void *kmem_cache_alloc_node_trace(struct kmem_cache *cachep, { void *ret; - ret = slab_alloc_node(cachep, flags, nodeid, size, _RET_IP_); + ret = slab_alloc_node(cachep, flags, nodeid, _RET_IP_); ret = kasan_kmalloc(cachep, ret, size, flags); trace_kmalloc_node(_RET_IP_, ret, @@ -3691,7 +3654,7 @@ static __always_inline void *__do_kmalloc(size_t size, gfp_t flags, cachep = kmalloc_slab(size, flags); if (unlikely(ZERO_OR_NULL_PTR(cachep))) return cachep; - ret = slab_alloc(cachep, flags, size, caller); + ret = slab_alloc(cachep, flags, caller); ret = kasan_kmalloc(cachep, ret, size, flags); trace_kmalloc(caller, ret, @@ -4240,10 +4203,7 @@ void __check_heap_object(const void *ptr, unsigned long n, struct page *page, BUG_ON(objnr >= cachep->num); /* Find offset within object. */ - if (is_kfence_address(ptr)) - offset = ptr - kfence_object_start(ptr); - else - offset = ptr - index_to_obj(cachep, page, objnr) - obj_offset(cachep); + offset = ptr - index_to_obj(cachep, page, objnr) - obj_offset(cachep); /* Allow address range falling entirely within usercopy region. */ if (offset >= cachep->useroffset && diff --git a/mm/slab_common.c b/mm/slab_common.c index f024c2067aa0..ca398f6bfa48 100644 --- a/mm/slab_common.c +++ b/mm/slab_common.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -594,7 +593,6 @@ static void slab_caches_to_rcu_destroy_workfn(struct work_struct *work) rcu_barrier(); list_for_each_entry_safe(s, s2, &to_destroy, list) { - kfence_shutdown_cache(s); #ifdef SLAB_SUPPORTS_SYSFS sysfs_slab_release(s); #else @@ -621,7 +619,6 @@ static int shutdown_cache(struct kmem_cache *s) list_add_tail(&s->list, &slab_caches_to_rcu_destroy); schedule_work(&slab_caches_to_rcu_destroy_work); } else { - kfence_shutdown_cache(s); #ifdef SLAB_SUPPORTS_SYSFS sysfs_slab_unlink(s); sysfs_slab_release(s); @@ -1873,7 +1870,7 @@ size_t ksize(const void *objp) if (unlikely(objp == ZERO_SIZE_PTR) || !__kasan_check_read(objp, 1)) return 0; - size = kfence_ksize(objp) ?: __ksize(objp); + size = __ksize(objp); /* * We assume that ksize callers could use whole allocated area, * so we need to unpoison this area. diff --git a/mm/slub.c b/mm/slub.c index 638736789987..ff869e0e2369 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -1487,11 +1486,6 @@ static inline bool slab_free_freelist_hook(struct kmem_cache *s, void *old_tail = *tail ? *tail : *head; int rsize; - if (is_kfence_address(next)) { - slab_free_hook(s, next); - return true; - } - /* Head and tail of the reconstructed freelist */ *head = NULL; *tail = NULL; @@ -2776,27 +2770,16 @@ static __always_inline void maybe_wipe_obj_freeptr(struct kmem_cache *s, * Otherwise we can simply pick the next object from the lockless free list. */ static __always_inline void *slab_alloc_node(struct kmem_cache *s, - gfp_t gfpflags, int node, unsigned long addr, size_t orig_size) + gfp_t gfpflags, int node, unsigned long addr) { void *object; struct kmem_cache_cpu *c; struct page *page; unsigned long tid; - struct kmem_cache *root_s = s; s = slab_pre_alloc_hook(s, gfpflags); if (!s) return NULL; - - /* - * 5.4 note: passing in original cachep to avoid problems with memcg - * accounting. Making KFENCE properly work with memcgs on older kernels - * is not worth the effort. - */ - object = kfence_alloc(root_s, orig_size, gfpflags); - if (unlikely(object)) - goto out; - redo: /* * Must read kmem_cache cpu data via this cpu ptr. Preemption is @@ -2870,21 +2853,20 @@ redo: if (unlikely(slab_want_init_on_alloc(gfpflags, s)) && object) memset(object, 0, s->object_size); -out: slab_post_alloc_hook(s, gfpflags, 1, &object); return object; } static __always_inline void *slab_alloc(struct kmem_cache *s, - gfp_t gfpflags, unsigned long addr, size_t orig_size) + gfp_t gfpflags, unsigned long addr) { - return slab_alloc_node(s, gfpflags, NUMA_NO_NODE, addr, orig_size); + return slab_alloc_node(s, gfpflags, NUMA_NO_NODE, addr); } void *kmem_cache_alloc(struct kmem_cache *s, gfp_t gfpflags) { - void *ret = slab_alloc(s, gfpflags, _RET_IP_, s->object_size); + void *ret = slab_alloc(s, gfpflags, _RET_IP_); trace_kmem_cache_alloc(_RET_IP_, ret, s->object_size, s->size, gfpflags); @@ -2896,7 +2878,7 @@ EXPORT_SYMBOL(kmem_cache_alloc); #ifdef CONFIG_TRACING void *kmem_cache_alloc_trace(struct kmem_cache *s, gfp_t gfpflags, size_t size) { - void *ret = slab_alloc(s, gfpflags, _RET_IP_, size); + void *ret = slab_alloc(s, gfpflags, _RET_IP_); trace_kmalloc(_RET_IP_, ret, size, s->size, gfpflags); ret = kasan_kmalloc(s, ret, size, gfpflags); return ret; @@ -2907,7 +2889,7 @@ EXPORT_SYMBOL(kmem_cache_alloc_trace); #ifdef CONFIG_NUMA void *kmem_cache_alloc_node(struct kmem_cache *s, gfp_t gfpflags, int node) { - void *ret = slab_alloc_node(s, gfpflags, node, _RET_IP_, s->object_size); + void *ret = slab_alloc_node(s, gfpflags, node, _RET_IP_); trace_kmem_cache_alloc_node(_RET_IP_, ret, s->object_size, s->size, gfpflags, node); @@ -2921,7 +2903,7 @@ void *kmem_cache_alloc_node_trace(struct kmem_cache *s, gfp_t gfpflags, int node, size_t size) { - void *ret = slab_alloc_node(s, gfpflags, node, _RET_IP_, size); + void *ret = slab_alloc_node(s, gfpflags, node, _RET_IP_); trace_kmalloc_node(_RET_IP_, ret, size, s->size, gfpflags, node); @@ -2955,9 +2937,6 @@ static void __slab_free(struct kmem_cache *s, struct page *page, stat(s, FREE_SLOWPATH); - if (kfence_free(head)) - return; - if (kmem_cache_debug(s) && !free_debug_processing(s, page, head, tail, cnt, addr)) return; @@ -3199,13 +3178,6 @@ int build_detached_freelist(struct kmem_cache *s, size_t size, df->s = cache_from_obj(s, object); /* Support for memcg */ } - if (is_kfence_address(object)) { - slab_free_hook(df->s, object); - __kfence_free(object); - p[size] = NULL; /* mark object processed */ - return size; - } - /* Start new detached freelist */ df->page = page; set_freepointer(df->s, object, NULL); @@ -3265,7 +3237,6 @@ int kmem_cache_alloc_bulk(struct kmem_cache *s, gfp_t flags, size_t size, { struct kmem_cache_cpu *c; int i; - struct kmem_cache *root_s = s; /* memcg and kmem_cache debug support */ s = slab_pre_alloc_hook(s, flags); @@ -3280,19 +3251,8 @@ int kmem_cache_alloc_bulk(struct kmem_cache *s, gfp_t flags, size_t size, c = this_cpu_ptr(s->cpu_slab); for (i = 0; i < size; i++) { - /* - * 5.4 note: passing in original cachep to avoid problems with memcg - * accounting. Making KFENCE properly work with memcgs on older kernels - * is not worth the effort. - */ - void *object = kfence_alloc(root_s, s->object_size, flags); + void *object = c->freelist; - if (unlikely(object)) { - p[i] = object; - continue; - } - - object = c->freelist; if (unlikely(!object)) { /* * We may have removed an object from c->freelist using @@ -3951,7 +3911,7 @@ void *__kmalloc(size_t size, gfp_t flags) if (unlikely(ZERO_OR_NULL_PTR(s))) return s; - ret = slab_alloc(s, flags, _RET_IP_, size); + ret = slab_alloc(s, flags, _RET_IP_); trace_kmalloc(_RET_IP_, ret, size, s->size, flags); @@ -3999,7 +3959,7 @@ void *__kmalloc_node(size_t size, gfp_t flags, int node) if (unlikely(ZERO_OR_NULL_PTR(s))) return s; - ret = slab_alloc_node(s, flags, node, _RET_IP_, size); + ret = slab_alloc_node(s, flags, node, _RET_IP_); trace_kmalloc_node(_RET_IP_, ret, size, s->size, flags, node); @@ -4025,7 +3985,6 @@ void __check_heap_object(const void *ptr, unsigned long n, struct page *page, struct kmem_cache *s; unsigned int offset; size_t object_size; - bool is_kfence = is_kfence_address(ptr); ptr = kasan_reset_tag(ptr); @@ -4038,13 +3997,10 @@ void __check_heap_object(const void *ptr, unsigned long n, struct page *page, to_user, 0, n); /* Find offset within object. */ - if (is_kfence) - offset = ptr - kfence_object_start(ptr); - else - offset = (ptr - page_address(page)) % s->size; + offset = (ptr - page_address(page)) % s->size; /* Adjust for redzone and reject if within the redzone. */ - if (!is_kfence && kmem_cache_debug(s) && s->flags & SLAB_RED_ZONE) { + if (kmem_cache_debug(s) && s->flags & SLAB_RED_ZONE) { if (offset < s->red_left_pad) usercopy_abort("SLUB object in left red zone", s->name, to_user, offset, n); @@ -4491,7 +4447,7 @@ void *__kmalloc_track_caller(size_t size, gfp_t gfpflags, unsigned long caller) if (unlikely(ZERO_OR_NULL_PTR(s))) return s; - ret = slab_alloc(s, gfpflags, caller, size); + ret = slab_alloc(s, gfpflags, caller); /* Honor the call site pointer we received. */ trace_kmalloc(caller, ret, size, s->size, gfpflags); @@ -4522,7 +4478,7 @@ void *__kmalloc_node_track_caller(size_t size, gfp_t gfpflags, if (unlikely(ZERO_OR_NULL_PTR(s))) return s; - ret = slab_alloc_node(s, gfpflags, node, caller, size); + ret = slab_alloc_node(s, gfpflags, node, caller); /* Honor the call site pointer we received. */ trace_kmalloc_node(caller, ret, size, s->size, gfpflags, node); diff --git a/net/Kconfig b/net/Kconfig index deca236df35f..7bab19b67941 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -258,7 +258,7 @@ config XPS default y config HWBM - bool + bool config CGROUP_NET_PRIO bool "Network priority cgroup" @@ -309,8 +309,12 @@ config BPF_STREAM_PARSER select STREAM_PARSER select NET_SOCK_MSG ---help--- - Enabling this allows a stream parser to be used with - BPF_MAP_TYPE_SOCKMAP. + Enabling this allows a stream parser to be used with + BPF_MAP_TYPE_SOCKMAP. + + BPF_MAP_TYPE_SOCKMAP provides a map type to use with network sockets. + It can be used to enforce socket policy, implement socket redirects, + etc. config NET_FLOW_LIMIT bool @@ -345,12 +349,12 @@ config NET_DROP_MONITOR tristate "Network packet drop alerting service" depends on INET && TRACEPOINTS ---help--- - This feature provides an alerting service to userspace in the - event that packets are discarded in the network stack. Alerts - are broadcast via netlink socket to any listening user space - process. If you don't need network drop alerts, or if you are ok - just checking the various proc files and other utilities for - drop statistics, say N here. + This feature provides an alerting service to userspace in the + event that packets are discarded in the network stack. Alerts + are broadcast via netlink socket to any listening user space + process. If you don't need network drop alerts, or if you are ok + just checking the various proc files and other utilities for + drop statistics, say N here. endmenu @@ -430,7 +434,7 @@ config NET_DEVLINK imply NET_DROP_MONITOR config PAGE_POOL - bool + bool config FAILOVER tristate "Generic failover module" diff --git a/net/bpfilter/Kconfig b/net/bpfilter/Kconfig index 8ad0233ce497..c3142b9d5e2f 100644 --- a/net/bpfilter/Kconfig +++ b/net/bpfilter/Kconfig @@ -10,14 +10,8 @@ menuconfig BPFILTER if BPFILTER config BPFILTER_UMH tristate "bpfilter kernel module with user mode helper" - depends on CC_CAN_LINK - depends on m || CC_CAN_LINK_STATIC + depends on CC_CAN_LINK_STATIC default m help This builds bpfilter kernel module with embedded user mode helper - - Note: To compile this as built-in, your toolchain must support - building static binaries, since rootfs isn't mounted at the time - when __init functions are called and do_execv won't be able to find - the elf interpreter. endif diff --git a/net/bpfilter/Makefile b/net/bpfilter/Makefile index cdac82b8c53a..05930c2fafd5 100644 --- a/net/bpfilter/Makefile +++ b/net/bpfilter/Makefile @@ -3,15 +3,17 @@ # Makefile for the Linux BPFILTER layer. # -userprogs := bpfilter_umh +hostprogs-y := bpfilter_umh bpfilter_umh-objs := main.o -userccflags += -I $(srctree)/tools/include/ -I $(srctree)/tools/include/uapi +KBUILD_HOSTCFLAGS += -I $(srctree)/tools/include/ -I $(srctree)/tools/include/uapi \ + $(filter -m32 -m64, $(KBUILD_CFLAGS)) +HOSTCC := $(CC) ifeq ($(CONFIG_BPFILTER_UMH), y) -# builtin bpfilter_umh should be linked with -static +# builtin bpfilter_umh should be compiled with -static # since rootfs isn't mounted at the time of __init # function is called and do_execv won't find elf interpreter -userldflags += -static +KBUILD_HOSTLDFLAGS += -static $(filter -m32 -m64, $(KBUILD_CFLAGS)) endif $(obj)/bpfilter_umh_blob.o: $(obj)/bpfilter_umh diff --git a/net/bpfilter/bpfilter_kern.c b/net/bpfilter/bpfilter_kern.c index 51a941b56ec3..08ea77c2b137 100644 --- a/net/bpfilter/bpfilter_kern.c +++ b/net/bpfilter/bpfilter_kern.c @@ -18,11 +18,10 @@ static void shutdown_umh(void) struct umd_info *info = &bpfilter_ops.info; struct pid *tgid = info->tgid; - if (tgid) { - kill_pid(tgid, SIGKILL, 1); - wait_event(tgid->wait_pidfd, thread_group_exited(tgid)); - bpfilter_umh_cleanup(info); - } + if (bpfilter_ops.stop) + return; + + kill_pid(tgid, SIGKILL, 1); } static void __stop_umh(void) @@ -31,65 +30,58 @@ static void __stop_umh(void) shutdown_umh(); } -static int bpfilter_send_req(struct mbox_request *req) +static int __bpfilter_process_sockopt(struct sock *sk, int optname, + char __user *optval, + unsigned int optlen, bool is_set) { + struct mbox_request req; struct mbox_reply reply; - loff_t pos = 0; + loff_t pos; ssize_t n; + int ret = -EFAULT; + req.is_set = is_set; + req.pid = current->pid; + req.cmd = optname; + req.addr = (long __force __user)optval; + req.len = optlen; if (!bpfilter_ops.info.tgid) - return -EFAULT; - pos = 0; - n = kernel_write(bpfilter_ops.info.pipe_to_umh, req, sizeof(*req), + goto out; + n = __kernel_write(bpfilter_ops.info.pipe_to_umh, &req, sizeof(req), &pos); - if (n != sizeof(*req)) { + if (n != sizeof(req)) { pr_err("write fail %zd\n", n); - goto stop; + __stop_umh(); + ret = -EFAULT; + goto out; } pos = 0; n = kernel_read(bpfilter_ops.info.pipe_from_umh, &reply, sizeof(reply), &pos); if (n != sizeof(reply)) { pr_err("read fail %zd\n", n); - goto stop; + __stop_umh(); + ret = -EFAULT; + goto out; } - return reply.status; -stop: - __stop_umh(); - return -EFAULT; -} - -static int bpfilter_process_sockopt(struct sock *sk, int optname, - sockptr_t optval, unsigned int optlen, - bool is_set) -{ - struct mbox_request req = { - .is_set = is_set, - .pid = current->pid, - .cmd = optname, - .addr = (uintptr_t)optval.user, - .len = optlen, - }; - if (uaccess_kernel() || sockptr_is_kernel(optval)) { - pr_err("kernel access not supported\n"); - return -EFAULT; - } - return bpfilter_send_req(&req); + ret = reply.status; +out: + return ret; } static int start_umh(void) { - struct mbox_request req = { .pid = current->pid }; int err; /* fork usermode process */ err = fork_usermode_driver(&bpfilter_ops.info); if (err) return err; + bpfilter_ops.stop = false; pr_info("Loaded bpfilter_umh pid %d\n", pid_nr(bpfilter_ops.info.tgid)); /* health check that usermode process started correctly */ - if (bpfilter_send_req(&req) != 0) { + if (__bpfilter_process_sockopt(NULL, 0, NULL, 0, 0) != 0) { shutdown_umh(); return -EFAULT; } @@ -108,11 +100,16 @@ static int __init load_umh(void) return err; mutex_lock(&bpfilter_ops.lock); + if (!bpfilter_ops.stop) { + err = -EFAULT; + goto out; + } err = start_umh(); if (!err && IS_ENABLED(CONFIG_INET)) { - bpfilter_ops.sockopt = &bpfilter_process_sockopt; + bpfilter_ops.sockopt = &__bpfilter_process_sockopt; bpfilter_ops.start = &start_umh; } +out: mutex_unlock(&bpfilter_ops.lock); if (err) umd_unload_blob(&bpfilter_ops.info); diff --git a/net/bpfilter/bpfilter_umh_blob.S b/net/bpfilter/bpfilter_umh_blob.S index 40311d10d2f2..9ea6100dca87 100644 --- a/net/bpfilter/bpfilter_umh_blob.S +++ b/net/bpfilter/bpfilter_umh_blob.S @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ - .section .init.rodata, "a" + .section .rodata, "a" .global bpfilter_umh_start bpfilter_umh_start: .incbin "net/bpfilter/bpfilter_umh" diff --git a/net/bridge/br_device.c b/net/bridge/br_device.c index ec4dee64357b..00438505c175 100644 --- a/net/bridge/br_device.c +++ b/net/bridge/br_device.c @@ -34,10 +34,6 @@ netdev_tx_t br_dev_xmit(struct sk_buff *skb, struct net_device *dev) const struct nf_br_ops *nf_ops; const unsigned char *dest; u16 vid = 0; -#ifdef CONFIG_HYFI_BRIDGE_HOOKS - struct net_bridge_port *pdst; - br_get_dst_hook_t *get_dst_hook; -#endif if (unlikely(!pskb_may_pull(skb, ETH_HLEN))) { kfree_skb(skb); @@ -86,10 +82,6 @@ netdev_tx_t br_dev_xmit(struct sk_buff *skb, struct net_device *dev) br_do_suppress_nd(skb, br, vid, NULL, msg); } -#ifdef CONFIG_HYFI_BRIDGE_HOOKS - get_dst_hook = rcu_dereference(br_get_dst_hook); -#endif - dest = eth_hdr(skb)->h_dest; if (is_broadcast_ether_addr(dest)) { br_flood(br, skb, BR_PKT_BROADCAST, false, true); @@ -115,24 +107,11 @@ netdev_tx_t br_dev_xmit(struct sk_buff *skb, struct net_device *dev) br_multicast_flood(mdst, skb, false, true); else br_flood(br, skb, BR_PKT_MULTICAST, false, true); + } else if ((dst = br_fdb_find_rcu(br, dest, vid)) != NULL) { + br_forward(dst->dst, skb, false, true); } else { -#ifdef CONFIG_HYFI_BRIDGE_HOOKS - pdst = __br_get(get_dst_hook, NULL, NULL, &skb); - if (pdst) { - if (!skb) - goto out; - br_forward(pdst, skb, false, true); - } else -#endif - { - dst = br_fdb_find_rcu(br, dest, vid); - if (dst) - br_forward(dst->dst, skb, false, true); - else - br_flood(br, skb, BR_PKT_UNICAST, false, true); - } + br_flood(br, skb, BR_PKT_UNICAST, false, true); } - out: rcu_read_unlock(); return NETDEV_TX_OK; diff --git a/net/bridge/br_if.c b/net/bridge/br_if.c index a5565b7dfb06..ea0ddd513cc1 100644 --- a/net/bridge/br_if.c +++ b/net/bridge/br_if.c @@ -695,7 +695,6 @@ int br_add_if(struct net_bridge *br, struct net_device *dev, br_set_gso_limits(br); kobject_uevent(&p->kobj, KOBJ_ADD); - call_netdevice_notifiers(NETDEV_BR_JOIN, dev); return 0; @@ -733,8 +732,6 @@ int br_del_if(struct net_bridge *br, struct net_device *dev) if (!p || p->br != br) return -EINVAL; - call_netdevice_notifiers(NETDEV_BR_LEAVE, dev); - /* Since more than one interface can be attached to a bridge, * there still maybe an alternate path for netconsole to use; * therefore there is no reason for a NETDEV_RELEASE event. diff --git a/net/bridge/br_input.c b/net/bridge/br_input.c index 02dbaf13f591..ace461e94830 100644 --- a/net/bridge/br_input.c +++ b/net/bridge/br_input.c @@ -33,11 +33,6 @@ br_netif_receive_skb(struct net *net, struct sock *sk, struct sk_buff *skb) /* Hook for external Multicast handler */ br_multicast_handle_hook_t __rcu *br_multicast_handle_hook __read_mostly; EXPORT_SYMBOL(br_multicast_handle_hook); - -/* Hook for external forwarding logic */ -br_get_dst_hook_t __rcu *br_get_dst_hook __read_mostly; -EXPORT_SYMBOL_GPL(br_get_dst_hook); - #endif int br_pass_frame_up(struct sk_buff *skb) @@ -99,8 +94,6 @@ int br_handle_frame_finish(struct net *net, struct sock *sk, struct sk_buff *skb struct net_bridge *br; #ifdef CONFIG_HYFI_BRIDGE_HOOKS br_multicast_handle_hook_t *multicast_handle_hook; - struct net_bridge_port *pdst = NULL; - br_get_dst_hook_t *get_dst_hook = rcu_dereference(br_get_dst_hook); #endif u16 vid = 0; @@ -175,17 +168,7 @@ int br_handle_frame_finish(struct net *net, struct sock *sk, struct sk_buff *skb } break; case BR_PKT_UNICAST: -#ifdef CONFIG_HYFI_BRIDGE_HOOKS - pdst = __br_get(get_dst_hook, NULL, p, &skb); - if (pdst) { - if (!skb) - goto out; - } else -#endif - { - dst = br_fdb_find_rcu(br, eth_hdr(skb)->h_dest, vid); - } - break; + dst = br_fdb_find_rcu(br, eth_hdr(skb)->h_dest, vid); default: break; } diff --git a/net/bridge/br_private.h b/net/bridge/br_private.h index 023ecc1f4494..c7130fff57a0 100644 --- a/net/bridge/br_private.h +++ b/net/bridge/br_private.h @@ -195,9 +195,6 @@ struct net_bridge_fdb_entry { struct net_bridge_fdb_key key; struct hlist_node fdb_node; - unsigned char is_local:1, - is_static:1; - unsigned long flags; unsigned char offloaded:1; diff --git a/net/core/Makefile b/net/core/Makefile index 26ef2eb6b1e6..a104dc8faafc 100644 --- a/net/core/Makefile +++ b/net/core/Makefile @@ -16,6 +16,7 @@ obj-y += dev.o ethtool.o dev_addr_lists.o dst.o netevent.o \ obj-y += net-sysfs.o obj-$(CONFIG_PAGE_POOL) += page_pool.o obj-$(CONFIG_PROC_FS) += net-procfs.o +obj-$(CONFIG_NET_SOCK_MSG) += skmsg.o obj-$(CONFIG_NET_PKTGEN) += pktgen.o obj-$(CONFIG_NETPOLL) += netpoll.o obj-$(CONFIG_FIB_RULES) += fib_rules.o @@ -27,13 +28,10 @@ obj-$(CONFIG_CGROUP_NET_PRIO) += netprio_cgroup.o obj-$(CONFIG_CGROUP_NET_CLASSID) += netclassid_cgroup.o obj-$(CONFIG_LWTUNNEL) += lwtunnel.o obj-$(CONFIG_LWTUNNEL_BPF) += lwt_bpf.o +obj-$(CONFIG_BPF_STREAM_PARSER) += sock_map.o obj-$(CONFIG_DST_CACHE) += dst_cache.o obj-$(CONFIG_HWBM) += hwbm.o obj-$(CONFIG_NET_DEVLINK) += devlink.o obj-$(CONFIG_GRO_CELLS) += gro_cells.o obj-$(CONFIG_FAILOVER) += failover.o -ifeq ($(CONFIG_INET),y) -obj-$(CONFIG_NET_SOCK_MSG) += skmsg.o -obj-$(CONFIG_BPF_SYSCALL) += sock_map.o -endif obj-$(CONFIG_BPF_SYSCALL) += bpf_sk_storage.o diff --git a/net/core/dev.c b/net/core/dev.c index 9b8bd2d89595..8f9f92b8bd80 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -1521,7 +1521,7 @@ const char *netdev_cmd_to_name(enum netdev_cmd cmd) N(UDP_TUNNEL_DROP_INFO) N(CHANGE_TX_QUEUE_LEN) N(CVLAN_FILTER_PUSH_INFO) N(CVLAN_FILTER_DROP_INFO) N(SVLAN_FILTER_PUSH_INFO) N(SVLAN_FILTER_DROP_INFO) - N(PRE_CHANGEADDR) N(BR_JOIN) N(BR_LEAVE) + N(PRE_CHANGEADDR) } #undef N return "UNKNOWN_NETDEV_EVENT"; diff --git a/net/core/filter.c b/net/core/filter.c index 5c88141ac58d..477fa754dba0 100644 --- a/net/core/filter.c +++ b/net/core/filter.c @@ -1505,7 +1505,7 @@ struct bpf_prog *__get_filter(struct sock_fprog *fprog, struct sock *sk) if (copy_from_user(prog->insns, fprog->filter, fsize)) { __bpf_prog_free(prog); - return ERR_PTR(-EFAULT); + return ERR_PTR(-EINVAL); } prog->len = fprog->len; @@ -1952,11 +1952,10 @@ BPF_CALL_5(bpf_l4_csum_replace, struct sk_buff *, skb, u32, offset, bool is_pseudo = flags & BPF_F_PSEUDO_HDR; bool is_mmzero = flags & BPF_F_MARK_MANGLED_0; bool do_mforce = flags & BPF_F_MARK_ENFORCE; - bool is_ipv6 = flags & BPF_F_IPV6; __sum16 *ptr; if (unlikely(flags & ~(BPF_F_MARK_MANGLED_0 | BPF_F_MARK_ENFORCE | - BPF_F_PSEUDO_HDR | BPF_F_HDR_FIELD_MASK | BPF_F_IPV6))) + BPF_F_PSEUDO_HDR | BPF_F_HDR_FIELD_MASK))) return -EINVAL; if (unlikely(offset > 0xffff || offset & 1)) return -EFAULT; @@ -1972,7 +1971,7 @@ BPF_CALL_5(bpf_l4_csum_replace, struct sk_buff *, skb, u32, offset, if (unlikely(from != 0)) return -EINVAL; - inet_proto_csum_replace_by_diff(ptr, skb, to, is_pseudo, is_ipv6); + inet_proto_csum_replace_by_diff(ptr, skb, to, is_pseudo); break; case 2: inet_proto_csum_replace2(ptr, skb, from, to, is_pseudo); @@ -10151,7 +10150,7 @@ sk_reuseport_is_valid_access(int off, int size, case bpf_ctx_range(struct sk_reuseport_md, eth_protocol): if (size < FIELD_SIZEOF(struct sk_buff, protocol)) return false; - fallthrough; + /* fall through */ case bpf_ctx_range(struct sk_reuseport_md, ip_protocol): case bpf_ctx_range(struct sk_reuseport_md, bind_inany): case bpf_ctx_range(struct sk_reuseport_md, len): diff --git a/net/core/lwt_bpf.c b/net/core/lwt_bpf.c index f91d3f53f218..017ed82611a8 100644 --- a/net/core/lwt_bpf.c +++ b/net/core/lwt_bpf.c @@ -39,10 +39,10 @@ static int run_lwt_bpf(struct sk_buff *skb, struct bpf_lwt_prog *lwt, { int ret; - /* Migration disable and BH disable are needed to protect per-cpu + /* Preempt disable and BH disable are needed to protect per-cpu * redirect_info between BPF prog and skb_do_redirect(). */ - migrate_disable(); + preempt_disable(); local_bh_disable(); bpf_compute_data_pointers(skb); ret = bpf_prog_run_save_cb(lwt->prog, skb); @@ -77,7 +77,7 @@ static int run_lwt_bpf(struct sk_buff *skb, struct bpf_lwt_prog *lwt, } local_bh_enable(); - migrate_enable(); + preempt_enable(); return ret; } diff --git a/net/core/skbuff.c b/net/core/skbuff.c index 15e7a2a27989..0b21a9902e29 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -1605,7 +1605,6 @@ struct sk_buff *__pskb_copy_fclone(struct sk_buff *skb, int headroom, skb_frag_ref(skb, i); } skb_shinfo(n)->nr_frags = i; - skb_shinfo(n)->tx_flags |= skb_shinfo(skb)->tx_flags & SKBTX_SHARED_FRAG; } if (skb_has_frag_list(skb)) { @@ -3360,7 +3359,19 @@ EXPORT_SYMBOL(skb_split); */ static int skb_prepare_for_shift(struct sk_buff *skb) { - return skb_unclone_keeptruesize(skb, GFP_ATOMIC); + int ret = 0; + + if (skb_cloned(skb)) { + /* Save and restore truesize: pskb_expand_head() may reallocate + * memory where ksize(kmalloc(S)) != ksize(kmalloc(S)), but we + * cannot change truesize at this point. + */ + unsigned int save_truesize = skb->truesize; + + ret = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); + skb->truesize = save_truesize; + } + return ret; } /** @@ -3490,8 +3501,6 @@ onlymerged: tgt->ip_summed = CHECKSUM_PARTIAL; skb->ip_summed = CHECKSUM_PARTIAL; - skb_shinfo(tgt)->tx_flags |= skb_shinfo(skb)->tx_flags & SKBTX_SHARED_FRAG; - /* Yak, is it really working this way? Some helper please? */ skb->len -= shiftlen; skb->data_len -= shiftlen; @@ -3835,8 +3844,6 @@ int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb) p->truesize += skb->truesize; p->len += skb->len; - skb_shinfo(p)->tx_flags |= skb_shinfo(skb)->tx_flags & SKBTX_SHARED_FRAG; - NAPI_GRO_CB(skb)->same_flow = 1; return 0; @@ -4066,8 +4073,7 @@ normal: skb_copy_from_linear_data_offset(head_skb, offset, skb_put(nskb, hsize), hsize); - skb_shinfo(nskb)->tx_flags |= (skb_shinfo(head_skb)->tx_flags | - skb_shinfo(frag_skb)->tx_flags) & + skb_shinfo(nskb)->tx_flags |= skb_shinfo(head_skb)->tx_flags & SKBTX_SHARED_FRAG; if (skb_zerocopy_clone(nskb, frag_skb, GFP_ATOMIC)) @@ -4084,9 +4090,6 @@ normal: nfrags = skb_shinfo(list_skb)->nr_frags; frag = skb_shinfo(list_skb)->frags; frag_skb = list_skb; - - skb_shinfo(nskb)->tx_flags |= skb_shinfo(frag_skb)->tx_flags & SKBTX_SHARED_FRAG; - if (!skb_headlen(list_skb)) { BUG_ON(!nfrags); } else { @@ -4303,12 +4306,10 @@ done: p->data_len += len; p->truesize += delta_truesize; p->len += len; - skb_shinfo(p)->tx_flags |= skb_shinfo(skb)->tx_flags & SKBTX_SHARED_FRAG; if (lp != p) { lp->data_len += len; lp->truesize += delta_truesize; lp->len += len; - skb_shinfo(lp)->tx_flags |= skbinfo->tx_flags & SKBTX_SHARED_FRAG; } NAPI_GRO_CB(skb)->same_flow = 1; return 0; @@ -5306,8 +5307,6 @@ bool skb_try_coalesce(struct sk_buff *to, struct sk_buff *from, from_shinfo->frags, from_shinfo->nr_frags * sizeof(skb_frag_t)); to_shinfo->nr_frags += from_shinfo->nr_frags; - if (from_shinfo->nr_frags) - to_shinfo->tx_flags |= from_shinfo->tx_flags & SKBTX_SHARED_FRAG; if (!skb_cloned(from)) from_shinfo->nr_frags = 0; @@ -6036,8 +6035,6 @@ static int pskb_carve_inside_header(struct sk_buff *skb, const u32 off, kfree(data); return -ENOMEM; } - if (skb_zcopy(skb)) - refcount_inc(&skb_uarg(skb)->refcnt); for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) skb_frag_ref(skb, i); if (skb_has_frag_list(skb)) @@ -6191,8 +6188,6 @@ static int pskb_carve_inside_nonlinear(struct sk_buff *skb, const u32 off, kfree(data); return -ENOMEM; } - if (skb_zcopy(skb)) - refcount_inc(&skb_uarg(skb)->refcnt); skb_release_data(skb); skb->head = data; diff --git a/net/core/skmsg.c b/net/core/skmsg.c index e1477e062ca7..caef78caf032 100644 --- a/net/core/skmsg.c +++ b/net/core/skmsg.c @@ -549,35 +549,15 @@ end: struct sk_psock *sk_psock_init(struct sock *sk, int node) { - struct sk_psock *psock; - struct proto *prot; + struct sk_psock *psock = kzalloc_node(sizeof(*psock), + GFP_ATOMIC | __GFP_NOWARN, + node); + if (!psock) + return NULL; - write_lock_bh(&sk->sk_callback_lock); - - if (inet_csk_has_ulp(sk)) { - psock = ERR_PTR(-EINVAL); - goto out; - } - - if (sk->sk_user_data) { - psock = ERR_PTR(-EBUSY); - goto out; - } - - psock = kzalloc_node(sizeof(*psock), GFP_ATOMIC | __GFP_NOWARN, node); - if (!psock) { - psock = ERR_PTR(-ENOMEM); - goto out; - } - - prot = READ_ONCE(sk->sk_prot); psock->sk = sk; - psock->eval = __SK_NONE; - psock->sk_proto = prot; + psock->eval = __SK_NONE; psock->saved_destroy = prot->destroy; - psock->saved_unhash = prot->unhash; - psock->saved_close = prot->close; - psock->saved_write_space = sk->sk_write_space; INIT_LIST_HEAD(&psock->link); spin_lock_init(&psock->link_lock); @@ -592,8 +572,6 @@ struct sk_psock *sk_psock_init(struct sock *sk, int node) rcu_assign_sk_user_data_nocopy(sk, psock); sock_hold(sk); -out: - write_unlock_bh(&sk->sk_callback_lock); return psock; } EXPORT_SYMBOL_GPL(sk_psock_init); @@ -638,15 +616,15 @@ static void sk_psock_link_destroy(struct sk_psock *psock) } } -static void sk_psock_done_strp(struct sk_psock *psock); - static void sk_psock_destroy_deferred(struct work_struct *gc) { struct sk_psock *psock = container_of(gc, struct sk_psock, gc); /* No sk_callback_lock since already detached. */ - sk_psock_done_strp(psock); + /* Parser has been stopped */ + if (psock->progs.skb_parser) + strp_done(&psock->parser.strp); cancel_work_sync(&psock->work); @@ -681,8 +659,6 @@ void sk_psock_drop(struct sock *sk, struct sk_psock *psock) rcu_assign_sk_user_data(sk, NULL); if (psock->progs.skb_parser) sk_psock_stop_strp(sk, psock); - else if (psock->progs.skb_verdict) - sk_psock_stop_verdict(sk, psock); write_unlock_bh(&sk->sk_callback_lock); sk_psock_clear_state(psock, SK_PSOCK_TX_ENABLED); @@ -759,6 +735,14 @@ static int sk_psock_bpf_run(struct sk_psock *psock, struct bpf_prog *prog, return ret; } +static struct sk_psock *sk_psock_from_strp(struct strparser *strp) +{ + struct sk_psock_parser *parser; + + parser = container_of(strp, struct sk_psock_parser, strp); + return container_of(parser, struct sk_psock, parser); +} + static void sk_psock_skb_redirect(struct sk_buff *skb) { struct sk_psock *psock_other; @@ -865,24 +849,6 @@ out_free: } } -static void sk_psock_write_space(struct sock *sk) -{ - struct sk_psock *psock; - void (*write_space)(struct sock *sk) = NULL; - - rcu_read_lock(); - psock = sk_psock(sk); - if (likely(psock)) { - if (sk_psock_test_state(psock, SK_PSOCK_TX_ENABLED)) - schedule_work(&psock->work); - write_space = psock->saved_write_space; - } - rcu_read_unlock(); - if (write_space) - write_space(sk); -} - -#if IS_ENABLED(CONFIG_BPF_STREAM_PARSER) static void sk_psock_strp_read(struct strparser *strp, struct sk_buff *skb) { struct sk_psock *psock; @@ -914,14 +880,6 @@ static int sk_psock_strp_read_done(struct strparser *strp, int err) return err; } -static struct sk_psock *sk_psock_from_strp(struct strparser *strp) -{ - struct sk_psock_parser *parser; - - parser = container_of(strp, struct sk_psock_parser, strp); - return container_of(parser, struct sk_psock, parser); -} - static int sk_psock_strp_parse(struct strparser *strp, struct sk_buff *skb) { struct sk_psock *psock = sk_psock_from_strp(strp); @@ -955,6 +913,23 @@ static void sk_psock_strp_data_ready(struct sock *sk) rcu_read_unlock(); } +static void sk_psock_write_space(struct sock *sk) +{ + struct sk_psock *psock; + void (*write_space)(struct sock *sk) = NULL; + + rcu_read_lock(); + psock = sk_psock(sk); + if (likely(psock)) { + if (sk_psock_test_state(psock, SK_PSOCK_TX_ENABLED)) + schedule_work(&psock->work); + write_space = psock->saved_write_space; + } + rcu_read_unlock(); + if (write_space) + write_space(sk); +} + int sk_psock_init_strp(struct sock *sk, struct sk_psock *psock) { static const struct strp_callbacks cb = { @@ -992,91 +967,3 @@ void sk_psock_stop_strp(struct sock *sk, struct sk_psock *psock) strp_stop(&parser->strp); parser->enabled = false; } - -static void sk_psock_done_strp(struct sk_psock *psock) -{ - /* Parser has been stopped */ - if (psock->progs.skb_parser) - strp_done(&psock->parser.strp); -} -#else -static void sk_psock_done_strp(struct sk_psock *psock) -{ -} -#endif /* CONFIG_BPF_STREAM_PARSER */ - -static int sk_psock_verdict_recv(read_descriptor_t *desc, struct sk_buff *skb, - unsigned int offset, size_t orig_len) -{ - struct sock *sk = (struct sock *)desc->arg.data; - struct sk_psock *psock; - struct bpf_prog *prog; - int ret = __SK_DROP; - int len = skb->len; - - /* clone here so sk_eat_skb() in tcp_read_sock does not drop our data */ - skb = skb_clone(skb, GFP_ATOMIC); - if (!skb) { - desc->error = -ENOMEM; - return 0; - } - - rcu_read_lock(); - psock = sk_psock(sk); - if (unlikely(!psock)) { - len = 0; - kfree_skb(skb); - goto out; - } - skb_set_owner_r(skb, sk); - prog = READ_ONCE(psock->progs.skb_verdict); - if (likely(prog)) { - tcp_skb_bpf_redirect_clear(skb); - ret = sk_psock_bpf_run(psock, prog, skb); - ret = sk_psock_map_verd(ret, tcp_skb_bpf_redirect_fetch(skb)); - } - sk_psock_verdict_apply(psock, skb, ret); -out: - rcu_read_unlock(); - return len; -} - -static void sk_psock_verdict_data_ready(struct sock *sk) -{ - struct socket *sock = sk->sk_socket; - read_descriptor_t desc; - - if (unlikely(!sock || !sock->ops || !sock->ops->read_sock)) - return; - - desc.arg.data = sk; - desc.error = 0; - desc.count = 1; - - sock->ops->read_sock(sk, &desc, sk_psock_verdict_recv); -} - -void sk_psock_start_verdict(struct sock *sk, struct sk_psock *psock) -{ - struct sk_psock_parser *parser = &psock->parser; - - if (parser->enabled) - return; - - parser->saved_data_ready = sk->sk_data_ready; - sk->sk_data_ready = sk_psock_verdict_data_ready; - sk->sk_write_space = sk_psock_write_space; - parser->enabled = true; -} - -void sk_psock_stop_verdict(struct sock *sk, struct sk_psock *psock) -{ - struct sk_psock_parser *parser = &psock->parser; - - if (!parser->enabled) - return; - - sk->sk_data_ready = parser->saved_data_ready; - parser->saved_data_ready = NULL; - parser->enabled = false; -} diff --git a/net/core/sock.c b/net/core/sock.c index 1c9d99fe59cb..cf74d31f61ff 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -578,7 +578,7 @@ static int sock_bindtoindex_locked(struct sock *sk, int ifindex) /* Sorry... */ ret = -EPERM; - if (sk->sk_bound_dev_if && !ns_capable(net->user_ns, CAP_NET_RAW)) + if (!ns_capable(net->user_ns, CAP_NET_RAW)) goto out; ret = -EINVAL; @@ -1542,13 +1542,6 @@ static int sk_getsockopt(struct sock *sk, int level, int optname, v.val = sk->sk_bound_dev_if; break; - case SO_NETNS_COOKIE: - lv = sizeof(u64); - if (len != lv) - return -EINVAL; - v.val64 = atomic64_read(&sock_net(sk)->net_cookie); - break; - default: /* We implement the SO_SNDLOWAT etc to not be settable * (1003.1g 7). diff --git a/net/core/sock_map.c b/net/core/sock_map.c index 001d7a3b6ead..eb3b1bb92e0c 100644 --- a/net/core/sock_map.c +++ b/net/core/sock_map.c @@ -11,7 +11,6 @@ #include #include #include -#include struct bpf_stab { struct bpf_map map; @@ -142,8 +141,8 @@ static void sock_map_add_link(struct sk_psock *psock, static void sock_map_del_link(struct sock *sk, struct sk_psock *psock, void *link_raw) { - bool strp_stop = false, verdict_stop = false; struct sk_psock_link *link, *tmp; + bool strp_stop = false; spin_lock_bh(&psock->link_lock); list_for_each_entry_safe(link, tmp, &psock->link, list) { @@ -153,20 +152,15 @@ static void sock_map_del_link(struct sock *sk, map); if (psock->parser.enabled && stab->progs.skb_parser) strp_stop = true; - if (psock->parser.enabled && stab->progs.skb_verdict) - verdict_stop = true; list_del(&link->list); sk_psock_free_link(link); break; } } spin_unlock_bh(&psock->link_lock); - if (strp_stop || verdict_stop) { + if (strp_stop) { write_lock_bh(&sk->sk_callback_lock); - if (strp_stop) - sk_psock_stop_strp(sk, psock); - else - sk_psock_stop_verdict(sk, psock); + sk_psock_stop_strp(sk, psock); write_unlock_bh(&sk->sk_callback_lock); } } @@ -181,27 +175,28 @@ static void sock_map_unref(struct sock *sk, void *link_raw) } } -static int sock_map_init_proto(struct sock *sk, struct sk_psock *psock) +static int sock_map_init_proto(struct sock *sk) { + struct sk_psock *psock; struct proto *prot; - switch (sk->sk_type) { - case SOCK_STREAM: - prot = tcp_bpf_get_proto(sk, psock); - break; + sock_owned_by_me(sk); - case SOCK_DGRAM: - prot = udp_bpf_get_proto(sk, psock); - break; - - default: + rcu_read_lock(); + psock = sk_psock(sk); + if (unlikely(!psock)) { + rcu_read_unlock(); return -EINVAL; } - if (IS_ERR(prot)) + prot = tcp_bpf_get_proto(sk, psock); + if (IS_ERR(prot)) { + rcu_read_unlock(); return PTR_ERR(prot); + } sk_psock_update_proto(sk, psock, prot); + rcu_read_unlock(); return 0; } @@ -212,7 +207,7 @@ static struct sk_psock *sock_map_psock_get_checked(struct sock *sk) rcu_read_lock(); psock = sk_psock(sk); if (psock) { - if (sk->sk_prot->close != sock_map_close) { + if (sk->sk_prot->recvmsg != tcp_bpf_recvmsg) { psock = ERR_PTR(-EBUSY); goto out; } @@ -271,8 +266,8 @@ static int sock_map_link(struct bpf_map *map, struct sk_psock_progs *progs, } } else { psock = sk_psock_init(sk, map->numa_node); - if (IS_ERR(psock)) { - ret = PTR_ERR(psock); + if (!psock) { + ret = -ENOMEM; goto out_progs; } } @@ -280,26 +275,23 @@ static int sock_map_link(struct bpf_map *map, struct sk_psock_progs *progs, if (msg_parser) psock_set_prog(&psock->progs.msg_parser, msg_parser); - ret = sock_map_init_proto(sk, psock); + ret = sock_map_init_proto(sk); if (ret < 0) goto out_drop; write_lock_bh(&sk->sk_callback_lock); if (skb_progs && !psock->parser.enabled) { ret = sk_psock_init_strp(sk, psock); - if (ret) - goto out_unlock_drop; + if (ret) { + write_unlock_bh(&sk->sk_callback_lock); + goto out_drop; + } psock_set_prog(&psock->progs.skb_verdict, skb_verdict); psock_set_prog(&psock->progs.skb_parser, skb_parser); sk_psock_start_strp(sk, psock); - } else if (!skb_parser && skb_verdict && !psock->parser.enabled) { - psock_set_prog(&psock->progs.skb_verdict, skb_verdict); - sk_psock_start_verdict(sk,psock); } write_unlock_bh(&sk->sk_callback_lock); return 0; -out_unlock_drop: - write_unlock_bh(&sk->sk_callback_lock); out_drop: sk_psock_put(sk, psock); out_progs: @@ -324,11 +316,11 @@ static int sock_map_link_no_progs(struct bpf_map *map, struct sock *sk) if (!psock) { psock = sk_psock_init(sk, map->numa_node); - if (IS_ERR(psock)) - return PTR_ERR(psock); + if (!psock) + return -ENOMEM; } - ret = sock_map_init_proto(sk, psock); + ret = sock_map_init_proto(sk); if (ret < 0) sk_psock_put(sk, psock); return ret; @@ -542,31 +534,15 @@ static bool sock_map_op_okay(const struct bpf_sock_ops_kern *ops) ops->op == BPF_SOCK_OPS_TCP_LISTEN_CB; } -static bool sk_is_tcp(const struct sock *sk) +static bool sock_map_sk_is_suitable(const struct sock *sk) { return sk->sk_type == SOCK_STREAM && sk->sk_protocol == IPPROTO_TCP; } -static bool sk_is_udp(const struct sock *sk) -{ - return sk->sk_type == SOCK_DGRAM && - sk->sk_protocol == IPPROTO_UDP; -} - -static bool sock_map_sk_is_suitable(const struct sock *sk) -{ - return sk_is_tcp(sk) || sk_is_udp(sk); -} - static bool sock_map_sk_state_allowed(const struct sock *sk) { - if (sk_is_tcp(sk)) - return (1 << sk->sk_state) & (TCPF_ESTABLISHED | TCPF_LISTEN); - else if (sk_is_udp(sk)) - return sk_hashed(sk); - - return false; + return (1 << sk->sk_state) & (TCPF_ESTABLISHED | TCPF_LISTEN); } static int sock_hash_update_common(struct bpf_map *map, void *key, @@ -1265,11 +1241,9 @@ int sock_map_prog_update(struct bpf_map *map, struct bpf_prog *prog, case BPF_SK_MSG_VERDICT: pprog = &progs->msg_parser; break; -#if IS_ENABLED(CONFIG_BPF_STREAM_PARSER) case BPF_SK_SKB_STREAM_PARSER: pprog = &progs->skb_parser; break; -#endif case BPF_SK_SKB_STREAM_VERDICT: pprog = &progs->skb_verdict; break; diff --git a/net/core/sysctl_net_core.c b/net/core/sysctl_net_core.c index f18d8a2e4468..2ee5289d885a 100644 --- a/net/core/sysctl_net_core.c +++ b/net/core/sysctl_net_core.c @@ -126,7 +126,7 @@ static int flow_limit_cpu_sysctl(struct ctl_table *table, int write, return -ENOMEM; if (write) { - ret = cpumask_parse(buffer, mask); + ret = cpumask_parse_user(buffer, *lenp, mask); if (ret) goto done; diff --git a/net/core/utils.c b/net/core/utils.c index d010fcf1dc08..1f31a39236d5 100644 --- a/net/core/utils.c +++ b/net/core/utils.c @@ -473,11 +473,11 @@ void inet_proto_csum_replace16(__sum16 *sum, struct sk_buff *skb, EXPORT_SYMBOL(inet_proto_csum_replace16); void inet_proto_csum_replace_by_diff(__sum16 *sum, struct sk_buff *skb, - __wsum diff, bool pseudohdr, bool ipv6) + __wsum diff, bool pseudohdr) { if (skb->ip_summed != CHECKSUM_PARTIAL) { *sum = csum_fold(csum_add(diff, ~csum_unfold(*sum))); - if (skb->ip_summed == CHECKSUM_COMPLETE && pseudohdr && !ipv6) + if (skb->ip_summed == CHECKSUM_COMPLETE && pseudohdr) skb->csum = ~csum_add(diff, ~skb->csum); } else if (pseudohdr) { *sum = ~csum_fold(csum_add(diff, csum_unfold(*sum))); diff --git a/net/ipv4/Kconfig b/net/ipv4/Kconfig index a8acc22d3571..f5af8c6b2f87 100644 --- a/net/ipv4/Kconfig +++ b/net/ipv4/Kconfig @@ -180,8 +180,8 @@ config NET_IPIP config NET_IPGRE_DEMUX tristate "IP: GRE demultiplexer" help - This is helper module to demultiplex GRE packets on GRE version field criteria. - Required by ip_gre and pptp modules. + This is helper module to demultiplex GRE packets on GRE version field criteria. + Required by ip_gre and pptp modules. config NET_IP_TUNNEL tristate @@ -470,185 +470,185 @@ config TCP_CONG_BIC tristate "Binary Increase Congestion (BIC) control" default m ---help--- - BIC-TCP is a sender-side only change that ensures a linear RTT - fairness under large windows while offering both scalability and - bounded TCP-friendliness. The protocol combines two schemes - called additive increase and binary search increase. When the - congestion window is large, additive increase with a large - increment ensures linear RTT fairness as well as good - scalability. Under small congestion windows, binary search - increase provides TCP friendliness. - See http://www.csc.ncsu.edu/faculty/rhee/export/bitcp/ + BIC-TCP is a sender-side only change that ensures a linear RTT + fairness under large windows while offering both scalability and + bounded TCP-friendliness. The protocol combines two schemes + called additive increase and binary search increase. When the + congestion window is large, additive increase with a large + increment ensures linear RTT fairness as well as good + scalability. Under small congestion windows, binary search + increase provides TCP friendliness. + See http://www.csc.ncsu.edu/faculty/rhee/export/bitcp/ config TCP_CONG_CUBIC tristate "CUBIC TCP" default y ---help--- - This is version 2.0 of BIC-TCP which uses a cubic growth function - among other techniques. - See http://www.csc.ncsu.edu/faculty/rhee/export/bitcp/cubic-paper.pdf + This is version 2.0 of BIC-TCP which uses a cubic growth function + among other techniques. + See http://www.csc.ncsu.edu/faculty/rhee/export/bitcp/cubic-paper.pdf config TCP_CONG_WESTWOOD tristate "TCP Westwood+" default m ---help--- - TCP Westwood+ is a sender-side only modification of the TCP Reno - protocol stack that optimizes the performance of TCP congestion - control. It is based on end-to-end bandwidth estimation to set - congestion window and slow start threshold after a congestion - episode. Using this estimation, TCP Westwood+ adaptively sets a - slow start threshold and a congestion window which takes into - account the bandwidth used at the time congestion is experienced. - TCP Westwood+ significantly increases fairness wrt TCP Reno in - wired networks and throughput over wireless links. + TCP Westwood+ is a sender-side only modification of the TCP Reno + protocol stack that optimizes the performance of TCP congestion + control. It is based on end-to-end bandwidth estimation to set + congestion window and slow start threshold after a congestion + episode. Using this estimation, TCP Westwood+ adaptively sets a + slow start threshold and a congestion window which takes into + account the bandwidth used at the time congestion is experienced. + TCP Westwood+ significantly increases fairness wrt TCP Reno in + wired networks and throughput over wireless links. config TCP_CONG_HTCP tristate "H-TCP" default m ---help--- - H-TCP is a send-side only modifications of the TCP Reno - protocol stack that optimizes the performance of TCP - congestion control for high speed network links. It uses a - modeswitch to change the alpha and beta parameters of TCP Reno - based on network conditions and in a way so as to be fair with - other Reno and H-TCP flows. + H-TCP is a send-side only modifications of the TCP Reno + protocol stack that optimizes the performance of TCP + congestion control for high speed network links. It uses a + modeswitch to change the alpha and beta parameters of TCP Reno + based on network conditions and in a way so as to be fair with + other Reno and H-TCP flows. config TCP_CONG_HSTCP tristate "High Speed TCP" default n ---help--- - Sally Floyd's High Speed TCP (RFC 3649) congestion control. - A modification to TCP's congestion control mechanism for use - with large congestion windows. A table indicates how much to - increase the congestion window by when an ACK is received. - For more detail see http://www.icir.org/floyd/hstcp.html + Sally Floyd's High Speed TCP (RFC 3649) congestion control. + A modification to TCP's congestion control mechanism for use + with large congestion windows. A table indicates how much to + increase the congestion window by when an ACK is received. + For more detail see http://www.icir.org/floyd/hstcp.html config TCP_CONG_HYBLA tristate "TCP-Hybla congestion control algorithm" default n ---help--- - TCP-Hybla is a sender-side only change that eliminates penalization of - long-RTT, large-bandwidth connections, like when satellite legs are - involved, especially when sharing a common bottleneck with normal - terrestrial connections. + TCP-Hybla is a sender-side only change that eliminates penalization of + long-RTT, large-bandwidth connections, like when satellite legs are + involved, especially when sharing a common bottleneck with normal + terrestrial connections. config TCP_CONG_VEGAS tristate "TCP Vegas" default n ---help--- - TCP Vegas is a sender-side only change to TCP that anticipates - the onset of congestion by estimating the bandwidth. TCP Vegas - adjusts the sending rate by modifying the congestion - window. TCP Vegas should provide less packet loss, but it is - not as aggressive as TCP Reno. + TCP Vegas is a sender-side only change to TCP that anticipates + the onset of congestion by estimating the bandwidth. TCP Vegas + adjusts the sending rate by modifying the congestion + window. TCP Vegas should provide less packet loss, but it is + not as aggressive as TCP Reno. config TCP_CONG_NV - tristate "TCP NV" - default n - ---help--- - TCP NV is a follow up to TCP Vegas. It has been modified to deal with - 10G networks, measurement noise introduced by LRO, GRO and interrupt - coalescence. In addition, it will decrease its cwnd multiplicatively - instead of linearly. + tristate "TCP NV" + default n + ---help--- + TCP NV is a follow up to TCP Vegas. It has been modified to deal with + 10G networks, measurement noise introduced by LRO, GRO and interrupt + coalescence. In addition, it will decrease its cwnd multiplicatively + instead of linearly. - Note that in general congestion avoidance (cwnd decreased when # packets - queued grows) cannot coexist with congestion control (cwnd decreased only - when there is packet loss) due to fairness issues. One scenario when they - can coexist safely is when the CA flows have RTTs << CC flows RTTs. + Note that in general congestion avoidance (cwnd decreased when # packets + queued grows) cannot coexist with congestion control (cwnd decreased only + when there is packet loss) due to fairness issues. One scenario when they + can coexist safely is when the CA flows have RTTs << CC flows RTTs. - For further details see http://www.brakmo.org/networking/tcp-nv/ + For further details see http://www.brakmo.org/networking/tcp-nv/ config TCP_CONG_SCALABLE tristate "Scalable TCP" default n ---help--- - Scalable TCP is a sender-side only change to TCP which uses a - MIMD congestion control algorithm which has some nice scaling - properties, though is known to have fairness issues. - See http://www.deneholme.net/tom/scalable/ + Scalable TCP is a sender-side only change to TCP which uses a + MIMD congestion control algorithm which has some nice scaling + properties, though is known to have fairness issues. + See http://www.deneholme.net/tom/scalable/ config TCP_CONG_LP tristate "TCP Low Priority" default n ---help--- - TCP Low Priority (TCP-LP), a distributed algorithm whose goal is - to utilize only the excess network bandwidth as compared to the - ``fair share`` of bandwidth as targeted by TCP. - See http://www-ece.rice.edu/networks/TCP-LP/ + TCP Low Priority (TCP-LP), a distributed algorithm whose goal is + to utilize only the excess network bandwidth as compared to the + ``fair share`` of bandwidth as targeted by TCP. + See http://www-ece.rice.edu/networks/TCP-LP/ config TCP_CONG_VENO tristate "TCP Veno" default n ---help--- - TCP Veno is a sender-side only enhancement of TCP to obtain better - throughput over wireless networks. TCP Veno makes use of state - distinguishing to circumvent the difficult judgment of the packet loss - type. TCP Veno cuts down less congestion window in response to random - loss packets. - See + TCP Veno is a sender-side only enhancement of TCP to obtain better + throughput over wireless networks. TCP Veno makes use of state + distinguishing to circumvent the difficult judgment of the packet loss + type. TCP Veno cuts down less congestion window in response to random + loss packets. + See config TCP_CONG_YEAH tristate "YeAH TCP" select TCP_CONG_VEGAS default n ---help--- - YeAH-TCP is a sender-side high-speed enabled TCP congestion control - algorithm, which uses a mixed loss/delay approach to compute the - congestion window. It's design goals target high efficiency, - internal, RTT and Reno fairness, resilience to link loss while - keeping network elements load as low as possible. + YeAH-TCP is a sender-side high-speed enabled TCP congestion control + algorithm, which uses a mixed loss/delay approach to compute the + congestion window. It's design goals target high efficiency, + internal, RTT and Reno fairness, resilience to link loss while + keeping network elements load as low as possible. - For further details look here: - http://wil.cs.caltech.edu/pfldnet2007/paper/YeAH_TCP.pdf + For further details look here: + http://wil.cs.caltech.edu/pfldnet2007/paper/YeAH_TCP.pdf config TCP_CONG_ILLINOIS tristate "TCP Illinois" default n ---help--- - TCP-Illinois is a sender-side modification of TCP Reno for - high speed long delay links. It uses round-trip-time to - adjust the alpha and beta parameters to achieve a higher average - throughput and maintain fairness. + TCP-Illinois is a sender-side modification of TCP Reno for + high speed long delay links. It uses round-trip-time to + adjust the alpha and beta parameters to achieve a higher average + throughput and maintain fairness. - For further details see: - http://www.ews.uiuc.edu/~shaoliu/tcpillinois/index.html + For further details see: + http://www.ews.uiuc.edu/~shaoliu/tcpillinois/index.html config TCP_CONG_DCTCP tristate "DataCenter TCP (DCTCP)" default n ---help--- - DCTCP leverages Explicit Congestion Notification (ECN) in the network to - provide multi-bit feedback to the end hosts. It is designed to provide: + DCTCP leverages Explicit Congestion Notification (ECN) in the network to + provide multi-bit feedback to the end hosts. It is designed to provide: - - High burst tolerance (incast due to partition/aggregate), - - Low latency (short flows, queries), - - High throughput (continuous data updates, large file transfers) with - commodity, shallow-buffered switches. + - High burst tolerance (incast due to partition/aggregate), + - Low latency (short flows, queries), + - High throughput (continuous data updates, large file transfers) with + commodity, shallow-buffered switches. - All switches in the data center network running DCTCP must support - ECN marking and be configured for marking when reaching defined switch - buffer thresholds. The default ECN marking threshold heuristic for - DCTCP on switches is 20 packets (30KB) at 1Gbps, and 65 packets - (~100KB) at 10Gbps, but might need further careful tweaking. + All switches in the data center network running DCTCP must support + ECN marking and be configured for marking when reaching defined switch + buffer thresholds. The default ECN marking threshold heuristic for + DCTCP on switches is 20 packets (30KB) at 1Gbps, and 65 packets + (~100KB) at 10Gbps, but might need further careful tweaking. - For further details see: - http://simula.stanford.edu/~alizade/Site/DCTCP_files/dctcp-final.pdf + For further details see: + http://simula.stanford.edu/~alizade/Site/DCTCP_files/dctcp-final.pdf config TCP_CONG_CDG tristate "CAIA Delay-Gradient (CDG)" default n ---help--- - CAIA Delay-Gradient (CDG) is a TCP congestion control that modifies - the TCP sender in order to: + CAIA Delay-Gradient (CDG) is a TCP congestion control that modifies + the TCP sender in order to: o Use the delay gradient as a congestion signal. o Back off with an average probability that is independent of the RTT. o Coexist with flows that use loss-based congestion control. o Tolerate packet loss unrelated to congestion. - For further details see: - D.A. Hayes and G. Armitage. "Revisiting TCP congestion control using - delay gradients." In Networking 2011. Preprint: http://goo.gl/No3vdg + For further details see: + D.A. Hayes and G. Armitage. "Revisiting TCP congestion control using + delay gradients." In Networking 2011. Preprint: http://goo.gl/No3vdg config TCP_CONG_BBR tristate "BBR TCP" diff --git a/net/ipv4/Makefile b/net/ipv4/Makefile index bbdd9c44f14e..506a6ca8d03e 100644 --- a/net/ipv4/Makefile +++ b/net/ipv4/Makefile @@ -62,7 +62,6 @@ obj-$(CONFIG_TCP_CONG_LP) += tcp_lp.o obj-$(CONFIG_TCP_CONG_YEAH) += tcp_yeah.o obj-$(CONFIG_TCP_CONG_ILLINOIS) += tcp_illinois.o obj-$(CONFIG_NET_SOCK_MSG) += tcp_bpf.o -obj-$(CONFIG_BPF_SYSCALL) += udp_bpf.o obj-$(CONFIG_NETLABEL) += cipso_ipv4.o obj-$(CONFIG_XFRM) += xfrm4_policy.o xfrm4_state.o xfrm4_input.o \ diff --git a/net/ipv4/bpfilter/sockopt.c b/net/ipv4/bpfilter/sockopt.c index 1b34cb9a7708..56cbc43145f6 100644 --- a/net/ipv4/bpfilter/sockopt.c +++ b/net/ipv4/bpfilter/sockopt.c @@ -12,16 +12,19 @@ struct bpfilter_umh_ops bpfilter_ops; EXPORT_SYMBOL_GPL(bpfilter_ops); -void bpfilter_umh_cleanup(struct umd_info *info) +static void bpfilter_umh_cleanup(struct umd_info *info) { + mutex_lock(&bpfilter_ops.lock); + bpfilter_ops.stop = true; fput(info->pipe_to_umh); fput(info->pipe_from_umh); put_pid(info->tgid); info->tgid = NULL; + mutex_unlock(&bpfilter_ops.lock); } -EXPORT_SYMBOL_GPL(bpfilter_umh_cleanup); -static int bpfilter_mbox_request(struct sock *sk, int optname, sockptr_t optval, +static int bpfilter_mbox_request(struct sock *sk, int optname, + char __user *optval, unsigned int optlen, bool is_set) { int err; @@ -36,11 +39,7 @@ static int bpfilter_mbox_request(struct sock *sk, int optname, sockptr_t optval, goto out; } } - if (bpfilter_ops.info.tgid && - thread_group_exited(bpfilter_ops.info.tgid)) - bpfilter_umh_cleanup(&bpfilter_ops.info); - - if (!bpfilter_ops.info.tgid) { + if (bpfilter_ops.stop) { err = bpfilter_ops.start(); if (err) goto out; @@ -51,7 +50,7 @@ out: return err; } -int bpfilter_ip_set_sockopt(struct sock *sk, int optname, sockptr_t optval, +int bpfilter_ip_set_sockopt(struct sock *sk, int optname, char __user *optval, unsigned int optlen) { return bpfilter_mbox_request(sk, optname, optval, optlen, true); @@ -65,15 +64,15 @@ int bpfilter_ip_get_sockopt(struct sock *sk, int optname, char __user *optval, if (get_user(len, optlen)) return -EFAULT; - return bpfilter_mbox_request(sk, optname, USER_SOCKPTR(optval), len, - false); + return bpfilter_mbox_request(sk, optname, optval, len, false); } static int __init bpfilter_sockopt_init(void) { mutex_init(&bpfilter_ops.lock); - bpfilter_ops.info.tgid = NULL; + bpfilter_ops.stop = true; bpfilter_ops.info.driver_name = "bpfilter_umh"; + bpfilter_ops.info.cleanup = &bpfilter_umh_cleanup; return 0; } diff --git a/net/ipv4/ip_sockglue.c b/net/ipv4/ip_sockglue.c index 650ccd695fbf..0c528f642eb8 100644 --- a/net/ipv4/ip_sockglue.c +++ b/net/ipv4/ip_sockglue.c @@ -1256,8 +1256,7 @@ int ip_setsockopt(struct sock *sk, int level, #if IS_ENABLED(CONFIG_BPFILTER_UMH) if (optname >= BPFILTER_IPT_SO_SET_REPLACE && optname < BPFILTER_IPT_SET_MAX) - err = bpfilter_ip_set_sockopt(sk, optname, USER_SOCKPTR(optval), - optlen); + err = bpfilter_ip_set_sockopt(sk, optname, optval, optlen); #endif #ifdef CONFIG_NETFILTER /* we need to exclude all possible ENOPROTOOPTs except default case */ diff --git a/net/ipv4/netfilter/ipt_NATTYPE.c b/net/ipv4/netfilter/ipt_NATTYPE.c index 484c0c111e4a..fae7cad3f89f 100644 --- a/net/ipv4/netfilter/ipt_NATTYPE.c +++ b/net/ipv4/netfilter/ipt_NATTYPE.c @@ -53,8 +53,8 @@ static void nattype_nte_debug_print(const struct ipt_nattype *nte, &nte->range.min_addr.ip, ntohs(nte->range.min_proto.all), ntohs(nte->nat_port), &nte->dest_addr, ntohs(nte->dest_port)); - DEBUGP("Timeout[%lx], Expires[%lx], Current[%lx]\n", nte->timeout_value, - nte->timeout.expires, jiffies); + DEBUGP("Timeout[%lx], Expires[%lx]\n", nte->timeout_value, + nte->timeout.expires); } /* netfilter NATTYPE nattype_free() @@ -80,9 +80,8 @@ bool nattype_refresh_timer_impl(unsigned long nat_type, spin_unlock_bh(&nattype_lock); return false; } - DEBUGP("%s: timeout_value=%lx, jiffies=%lx", __func__, timeout_value, jiffies); if (del_timer(&nte->timeout)) { - nte->timeout.expires = timeout_value + jiffies - nfct_time_stamp; + nte->timeout.expires = timeout_value; add_timer(&nte->timeout); spin_unlock_bh(&nattype_lock); nattype_nte_debug_print(nte, "refresh"); @@ -294,7 +293,7 @@ static unsigned int nattype_nat(struct sk_buff *skb, * found the entry. */ if (!nattype_refresh_timer((unsigned long)nte, - nfct_time_stamp + nte->timeout_value)) + jiffies + nte->timeout_value)) break; /* netfilter @@ -327,7 +326,6 @@ static unsigned int nattype_forward(struct sk_buff *skb, const struct ipt_nattype_info *info = par->targinfo; u16 nat_port; enum ip_conntrack_dir dir; - unsigned long timeout_value; if (xt_hooknum(par) != NF_INET_POST_ROUTING) return XT_CONTINUE; @@ -360,7 +358,7 @@ static unsigned int nattype_forward(struct sk_buff *skb, * found the entry. */ if (!nattype_refresh_timer((unsigned long)nte, - ct->timeout)) + ct->timeout)) break; /* netfilter NATTYPE @@ -433,8 +431,7 @@ static unsigned int nattype_forward(struct sk_buff *skb, * entry as this one is timed out and will be removed * from the list shortly. */ - timeout_value = nfct_time_stamp + nte2->timeout_value; - if (!nattype_refresh_timer((unsigned long)nte2, timeout_value)) + if (!nattype_refresh_timer((unsigned long)nte2, jiffies + nte2->timeout_value)) break; /* netfilter NATTYPE diff --git a/net/ipv4/tcp_bpf.c b/net/ipv4/tcp_bpf.c index e5a72106d292..4c156b5aa4f3 100644 --- a/net/ipv4/tcp_bpf.c +++ b/net/ipv4/tcp_bpf.c @@ -10,6 +10,38 @@ #include #include +static bool tcp_bpf_stream_read(const struct sock *sk) +{ + struct sk_psock *psock; + bool empty = true; + + rcu_read_lock(); + psock = sk_psock(sk); + if (likely(psock)) + empty = list_empty(&psock->ingress_msg); + rcu_read_unlock(); + return !empty; +} + +static int tcp_bpf_wait_data(struct sock *sk, struct sk_psock *psock, + int flags, long timeo, int *err) +{ + DEFINE_WAIT_FUNC(wait, woken_wake_function); + int ret = 0; + + if (!timeo) + return ret; + + add_wait_queue(sk_sleep(sk), &wait); + sk_set_bit(SOCKWQ_ASYNC_WAITDATA, sk); + ret = sk_wait_event(sk, &timeo, + !list_empty(&psock->ingress_msg) || + !skb_queue_empty(&sk->sk_receive_queue), &wait); + sk_clear_bit(SOCKWQ_ASYNC_WAITDATA, sk); + remove_wait_queue(sk_sleep(sk), &wait); + return ret; +} + int __tcp_bpf_recvmsg(struct sock *sk, struct sk_psock *psock, struct msghdr *msg, int len, int flags) { @@ -90,6 +122,52 @@ int __tcp_bpf_recvmsg(struct sock *sk, struct sk_psock *psock, } EXPORT_SYMBOL_GPL(__tcp_bpf_recvmsg); +int tcp_bpf_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, + int nonblock, int flags, int *addr_len) +{ + struct sk_psock *psock; + int copied, ret; + + if (unlikely(flags & MSG_ERRQUEUE)) + return inet_recv_error(sk, msg, len, addr_len); + + psock = sk_psock_get(sk); + if (unlikely(!psock)) + return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); + if (!skb_queue_empty(&sk->sk_receive_queue) && + sk_psock_queue_empty(psock)) { + sk_psock_put(sk, psock); + return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); + } + lock_sock(sk); +msg_bytes_ready: + copied = __tcp_bpf_recvmsg(sk, psock, msg, len, flags); + if (!copied) { + int data, err = 0; + long timeo; + + timeo = sock_rcvtimeo(sk, nonblock); + data = tcp_bpf_wait_data(sk, psock, flags, timeo, &err); + if (data) { + if (!sk_psock_queue_empty(psock)) + goto msg_bytes_ready; + release_sock(sk); + sk_psock_put(sk, psock); + return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); + } + if (err) { + ret = err; + goto out; + } + copied = -EAGAIN; + } + ret = copied; +out: + release_sock(sk); + sk_psock_put(sk, psock); + return ret; +} + static int bpf_tcp_ingress(struct sock *sk, struct sk_psock *psock, struct sk_msg *msg, u32 apply_bytes, int flags) { @@ -231,85 +309,6 @@ int tcp_bpf_sendmsg_redir(struct sock *sk, struct sk_msg *msg, } EXPORT_SYMBOL_GPL(tcp_bpf_sendmsg_redir); -#ifdef CONFIG_BPF_SYSCALL -static bool tcp_bpf_stream_read(const struct sock *sk) -{ - struct sk_psock *psock; - bool empty = true; - - rcu_read_lock(); - psock = sk_psock(sk); - if (likely(psock)) - empty = list_empty(&psock->ingress_msg); - rcu_read_unlock(); - return !empty; -} - -static int tcp_bpf_wait_data(struct sock *sk, struct sk_psock *psock, - int flags, long timeo, int *err) -{ - DEFINE_WAIT_FUNC(wait, woken_wake_function); - int ret = 0; - - if (!timeo) - return ret; - - add_wait_queue(sk_sleep(sk), &wait); - sk_set_bit(SOCKWQ_ASYNC_WAITDATA, sk); - ret = sk_wait_event(sk, &timeo, - !list_empty(&psock->ingress_msg) || - !skb_queue_empty(&sk->sk_receive_queue), &wait); - sk_clear_bit(SOCKWQ_ASYNC_WAITDATA, sk); - remove_wait_queue(sk_sleep(sk), &wait); - return ret; -} - -static int tcp_bpf_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, - int nonblock, int flags, int *addr_len) -{ - struct sk_psock *psock; - int copied, ret; - - if (unlikely(flags & MSG_ERRQUEUE)) - return inet_recv_error(sk, msg, len, addr_len); - - psock = sk_psock_get(sk); - if (unlikely(!psock)) - return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); - if (!skb_queue_empty(&sk->sk_receive_queue) && - sk_psock_queue_empty(psock)) { - sk_psock_put(sk, psock); - return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); - } - lock_sock(sk); -msg_bytes_ready: - copied = __tcp_bpf_recvmsg(sk, psock, msg, len, flags); - if (!copied) { - int data, err = 0; - long timeo; - - timeo = sock_rcvtimeo(sk, nonblock); - data = tcp_bpf_wait_data(sk, psock, flags, timeo, &err); - if (data) { - if (!sk_psock_queue_empty(psock)) - goto msg_bytes_ready; - release_sock(sk); - sk_psock_put(sk, psock); - return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); - } - if (err) { - ret = err; - goto out; - } - copied = -EAGAIN; - } - ret = copied; -out: - release_sock(sk); - sk_psock_put(sk, psock); - return ret; -} - static int tcp_bpf_send_verdict(struct sock *sk, struct sk_psock *psock, struct sk_msg *msg, int *copied, int flags) { @@ -558,6 +557,7 @@ out_err: return copied ? copied : err; } +#ifdef CONFIG_BPF_STREAM_PARSER enum { TCP_BPF_IPV4, TCP_BPF_IPV6, @@ -589,9 +589,10 @@ static void tcp_bpf_rebuild_protos(struct proto prot[TCP_BPF_NUM_CFGS], prot[TCP_BPF_TX].sendpage = tcp_bpf_sendpage; } -static void tcp_bpf_check_v6_needs_rebuild(struct proto *ops) +static void tcp_bpf_check_v6_needs_rebuild(struct sock *sk, struct proto *ops) { - if (unlikely(ops != smp_load_acquire(&tcpv6_prot_saved))) { + if (sk->sk_family == AF_INET6 && + unlikely(ops != smp_load_acquire(&tcpv6_prot_saved))) { spin_lock_bh(&tcpv6_prot_lock); if (likely(ops != tcpv6_prot_saved)) { tcp_bpf_rebuild_protos(tcp_bpf_prots[TCP_BPF_IPV6], ops); @@ -624,11 +625,13 @@ struct proto *tcp_bpf_get_proto(struct sock *sk, struct sk_psock *psock) int family = sk->sk_family == AF_INET6 ? TCP_BPF_IPV6 : TCP_BPF_IPV4; int config = psock->progs.msg_parser ? TCP_BPF_TX : TCP_BPF_BASE; - if (sk->sk_family == AF_INET6) { - if (tcp_bpf_assert_proto_ops(psock->sk_proto)) + if (!psock->sk_proto) { + struct proto *ops = READ_ONCE(sk->sk_prot); + + if (tcp_bpf_assert_proto_ops(ops)) return ERR_PTR(-EINVAL); - tcp_bpf_check_v6_needs_rebuild(psock->sk_proto); + tcp_bpf_check_v6_needs_rebuild(sk, ops); } return &tcp_bpf_prots[family][config]; @@ -647,4 +650,4 @@ void tcp_bpf_clone(const struct sock *sk, struct sock *newsk) if (prot == &tcp_bpf_prots[family][TCP_BPF_BASE]) newsk->sk_prot = sk->sk_prot_creator; } -#endif /* CONFIG_BPF_SYSCALL */ +#endif /* CONFIG_BPF_STREAM_PARSER */ diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index 9a6e8eb85bdb..cd252f530a2e 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -1492,7 +1492,7 @@ int tcp_fragment(struct sock *sk, enum tcp_queue tcp_queue, return -ENOMEM; } - if (skb_unclone_keeptruesize(skb, gfp)) + if (skb_unclone(skb, gfp)) return -ENOMEM; /* Get a new skb... force flag on. */ @@ -1601,7 +1601,7 @@ int tcp_trim_head(struct sock *sk, struct sk_buff *skb, u32 len) { u32 delta_truesize; - if (skb_unclone_keeptruesize(skb, GFP_ATOMIC)) + if (skb_unclone(skb, GFP_ATOMIC)) return -ENOMEM; delta_truesize = __pskb_trim_head(skb, len); @@ -3160,7 +3160,7 @@ start: cur_mss, GFP_ATOMIC)) return -ENOMEM; /* We'll try again later. */ } else { - if (skb_unclone_keeptruesize(skb, GFP_ATOMIC)) + if (skb_unclone(skb, GFP_ATOMIC)) return -ENOMEM; diff = tcp_skb_pcount(skb); diff --git a/net/ipv4/tcp_timer.c b/net/ipv4/tcp_timer.c index 2e1e1908097e..3b7f98ef34a4 100644 --- a/net/ipv4/tcp_timer.c +++ b/net/ipv4/tcp_timer.c @@ -47,7 +47,7 @@ static void set_tcp_default(void) /*sysctl handler for tcp_ack realted master control */ int tcp_proc_delayed_ack_control(struct ctl_table *table, int write, - void *buffer, size_t *length, + void __user *buffer, size_t *length, loff_t *ppos) { int ret = proc_dointvec_minmax(table, write, buffer, length, ppos); @@ -61,7 +61,7 @@ int tcp_proc_delayed_ack_control(struct ctl_table *table, int write, /*sysctl handler for tcp_ack realted master control */ int tcp_use_userconfig_sysctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, + void __user *buffer, size_t *length, loff_t *ppos) { int ret = proc_dointvec_minmax(table, write, buffer, length, ppos); diff --git a/net/ipv4/udp_bpf.c b/net/ipv4/udp_bpf.c deleted file mode 100644 index 7a94791efc1a..000000000000 --- a/net/ipv4/udp_bpf.c +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2020 Cloudflare Ltd https://cloudflare.com */ - -#include -#include -#include - -enum { - UDP_BPF_IPV4, - UDP_BPF_IPV6, - UDP_BPF_NUM_PROTS, -}; - -static struct proto *udpv6_prot_saved __read_mostly; -static DEFINE_SPINLOCK(udpv6_prot_lock); -static struct proto udp_bpf_prots[UDP_BPF_NUM_PROTS]; - -static void udp_bpf_rebuild_protos(struct proto *prot, const struct proto *base) -{ - *prot = *base; - prot->unhash = sock_map_unhash; - prot->close = sock_map_close; -} - -static void udp_bpf_check_v6_needs_rebuild(struct proto *ops) -{ - if (unlikely(ops != smp_load_acquire(&udpv6_prot_saved))) { - spin_lock_bh(&udpv6_prot_lock); - if (likely(ops != udpv6_prot_saved)) { - udp_bpf_rebuild_protos(&udp_bpf_prots[UDP_BPF_IPV6], ops); - smp_store_release(&udpv6_prot_saved, ops); - } - spin_unlock_bh(&udpv6_prot_lock); - } -} - -static int __init udp_bpf_v4_build_proto(void) -{ - udp_bpf_rebuild_protos(&udp_bpf_prots[UDP_BPF_IPV4], &udp_prot); - return 0; -} -core_initcall(udp_bpf_v4_build_proto); - -struct proto *udp_bpf_get_proto(struct sock *sk, struct sk_psock *psock) -{ - int family = sk->sk_family == AF_INET ? UDP_BPF_IPV4 : UDP_BPF_IPV6; - - if (sk->sk_family == AF_INET6) - udp_bpf_check_v6_needs_rebuild(psock->sk_proto); - - return &udp_bpf_prots[family]; -} diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c index 318d0111455d..7b9ac231b654 100644 --- a/net/ipv6/addrconf.c +++ b/net/ipv6/addrconf.c @@ -208,7 +208,6 @@ static struct ipv6_devconf ipv6_devconf __read_mostly = { .accept_ra_defrtr = 1, .accept_ra_from_local = 0, .accept_ra_min_hop_limit= 1, - .accept_ra_min_lft = 0, .accept_ra_pinfo = 1, #ifdef CONFIG_IPV6_ROUTER_PREF .accept_ra_rtr_pref = 1, @@ -264,7 +263,6 @@ static struct ipv6_devconf ipv6_devconf_dflt __read_mostly = { .accept_ra_defrtr = 1, .accept_ra_from_local = 0, .accept_ra_min_hop_limit= 1, - .accept_ra_min_lft = 0, .accept_ra_pinfo = 1, #ifdef CONFIG_IPV6_ROUTER_PREF .accept_ra_rtr_pref = 1, @@ -2751,9 +2749,6 @@ void addrconf_prefix_rcv(struct net_device *dev, u8 *opt, int len, bool sllao) return; } - if (valid_lft != 0 && valid_lft < in6_dev->cnf.accept_ra_min_lft) - goto put; - /* * Two things going on here: * 1) Add routes for on-link prefixes @@ -5552,7 +5547,6 @@ static inline void ipv6_store_devconf(struct ipv6_devconf *cnf, array[DEVCONF_ADDR_GEN_MODE] = cnf->addr_gen_mode; array[DEVCONF_DISABLE_POLICY] = cnf->disable_policy; array[DEVCONF_NDISC_TCLASS] = cnf->ndisc_tclass; - array[DEVCONF_ACCEPT_RA_MIN_LFT] = cnf->accept_ra_min_lft; } static inline size_t inet6_ifla6_size(void) @@ -6720,13 +6714,6 @@ static const struct ctl_table addrconf_sysctl[] = { .mode = 0644, .proc_handler = proc_dointvec, }, - { - .procname = "accept_ra_min_lft", - .data = &ipv6_devconf.accept_ra_min_lft, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec, - }, { .procname = "accept_ra_pinfo", .data = &ipv6_devconf.accept_ra_pinfo, diff --git a/net/ipv6/icmp.c b/net/ipv6/icmp.c index 012cadd47f43..169467b5c98a 100644 --- a/net/ipv6/icmp.c +++ b/net/ipv6/icmp.c @@ -639,9 +639,6 @@ int ip6_err_gen_icmpv6_unreach(struct sk_buff *skb, int nhs, int type, if (!skb2) return 1; - /* Remove debris left by IPv4 stack. */ - memset(IP6CB(skb2), 0, sizeof(*IP6CB(skb2))); - skb_dst_drop(skb2); skb_pull(skb2, nhs); skb_reset_network_header(skb2); diff --git a/net/ipv6/ila/ila_common.c b/net/ipv6/ila/ila_common.c index b8d43ed4689d..95e9146918cc 100644 --- a/net/ipv6/ila/ila_common.c +++ b/net/ipv6/ila/ila_common.c @@ -86,7 +86,7 @@ static void ila_csum_adjust_transport(struct sk_buff *skb, diff = get_csum_diff(ip6h, p); inet_proto_csum_replace_by_diff(&th->check, skb, - diff, true, true); + diff, true); } break; case NEXTHDR_UDP: @@ -97,7 +97,7 @@ static void ila_csum_adjust_transport(struct sk_buff *skb, if (uh->check || skb->ip_summed == CHECKSUM_PARTIAL) { diff = get_csum_diff(ip6h, p); inet_proto_csum_replace_by_diff(&uh->check, skb, - diff, true, true); + diff, true); if (!uh->check) uh->check = CSUM_MANGLED_0; } @@ -111,7 +111,7 @@ static void ila_csum_adjust_transport(struct sk_buff *skb, diff = get_csum_diff(ip6h, p); inet_proto_csum_replace_by_diff(&ih->icmp6_cksum, skb, - diff, true, true); + diff, true); } break; } diff --git a/net/ipv6/ip6_tunnel.c b/net/ipv6/ip6_tunnel.c index 604a6c018b2b..c79e6c032b30 100644 --- a/net/ipv6/ip6_tunnel.c +++ b/net/ipv6/ip6_tunnel.c @@ -601,16 +601,11 @@ ip4ip6_err(struct sk_buff *skb, struct inet6_skb_parm *opt, if (!skb2) return 0; - /* Remove debris left by IPv6 stack. */ - memset(IPCB(skb2), 0, sizeof(*IPCB(skb2))); - skb_dst_drop(skb2); skb_pull(skb2, offset); skb_reset_network_header(skb2); eiph = ip_hdr(skb2); - if (eiph->version != 4 || eiph->ihl < 5) - goto out; /* Try to guess incoming interface */ rt = ip_route_output_ports(dev_net(skb->dev), &fl4, NULL, eiph->saddr, diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c index 653e5bc7f047..f6b5340c5e11 100644 --- a/net/ipv6/ndisc.c +++ b/net/ipv6/ndisc.c @@ -1271,14 +1271,6 @@ static void ndisc_router_discovery(struct sk_buff *skb) goto skip_defrtr; } - lifetime = ntohs(ra_msg->icmph.icmp6_rt_lifetime); - if (lifetime != 0 && lifetime < in6_dev->cnf.accept_ra_min_lft) { - ND_PRINTK(2, info, - "RA: router lifetime (%ds) is too short: %s\n", - lifetime, skb->dev->name); - goto skip_defrtr; - } - /* Do not accept RA with source-addr found on local machine unless * accept_ra_from_local is set to true. */ @@ -1291,6 +1283,8 @@ static void ndisc_router_discovery(struct sk_buff *skb) goto skip_defrtr; } + lifetime = ntohs(ra_msg->icmph.icmp6_rt_lifetime); + #ifdef CONFIG_IPV6_ROUTER_PREF pref = ra_msg->icmph.icmp6_router_pref; /* 10b is handled as if it were 00b (medium) */ @@ -1461,9 +1455,6 @@ skip_linkparms: if (ri->prefix_len == 0 && !in6_dev->cnf.accept_ra_defrtr) continue; - if (ri->lifetime != 0 && - ntohl(ri->lifetime) < in6_dev->cnf.accept_ra_min_lft) - continue; if (ri->prefix_len < in6_dev->cnf.accept_ra_rt_info_min_plen) continue; if (ri->prefix_len > in6_dev->cnf.accept_ra_rt_info_max_plen) diff --git a/net/ipv6/netfilter/Kconfig b/net/ipv6/netfilter/Kconfig index 2e45c75da225..69443e9a3aa5 100644 --- a/net/ipv6/netfilter/Kconfig +++ b/net/ipv6/netfilter/Kconfig @@ -128,9 +128,9 @@ config IP6_NF_MATCH_HL depends on NETFILTER_ADVANCED select NETFILTER_XT_MATCH_HL ---help--- - This is a backwards-compat option for the user's convenience - (e.g. when running oldconfig). It selects - CONFIG_NETFILTER_XT_MATCH_HL. + This is a backwards-compat option for the user's convenience + (e.g. when running oldconfig). It selects + CONFIG_NETFILTER_XT_MATCH_HL. config IP6_NF_MATCH_IPV6HEADER tristate '"ipv6header" IPv6 Extension Headers Match' @@ -184,9 +184,9 @@ config IP6_NF_TARGET_HL depends on NETFILTER_ADVANCED && IP6_NF_MANGLE select NETFILTER_XT_TARGET_HL ---help--- - This is a backwards-compatible option for the user's convenience - (e.g. when running oldconfig). It selects - CONFIG_NETFILTER_XT_TARGET_HL. + This is a backwards-compatible option for the user's convenience + (e.g. when running oldconfig). It selects + CONFIG_NETFILTER_XT_TARGET_HL. config IP6_NF_FILTER tristate "Packet filtering" diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c index effa09102d3c..e999b6d8da11 100644 --- a/net/netfilter/nf_conntrack_core.c +++ b/net/netfilter/nf_conntrack_core.c @@ -1853,12 +1853,8 @@ void __nf_ct_refresh_acct(struct nf_conn *ct, /* Refresh the NAT type entry. */ #if defined(CONFIG_IP_NF_TARGET_NATTYPE_MODULE) nattype_ref_timer = rcu_dereference(nattype_refresh_timer); - if (nattype_ref_timer) { - if (nf_ct_is_confirmed(ct)) - nattype_ref_timer(ct->nattype_entry, ct->timeout); - else - nattype_ref_timer(ct->nattype_entry, extra_jiffies + nfct_time_stamp); - } + if (nattype_ref_timer) + nattype_ref_timer(ct->nattype_entry, ct->timeout); #endif acct: diff --git a/net/nfc/hci/Kconfig b/net/nfc/hci/Kconfig index 4822d6f46947..97bd3a2c5c98 100644 --- a/net/nfc/hci/Kconfig +++ b/net/nfc/hci/Kconfig @@ -1,12 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only config NFC_HCI - depends on NFC - tristate "NFC HCI implementation" - default n - help - Say Y here if you want to build support for a kernel NFC HCI - implementation. This is mostly needed for devices that only process - HCI frames, like for example the NXP pn544. + depends on NFC + tristate "NFC HCI implementation" + default n + help + Say Y here if you want to build support for a kernel NFC HCI + implementation. This is mostly needed for devices that only process + HCI frames, like for example the NXP pn544. config NFC_SHDLC depends on NFC_HCI diff --git a/net/nfc/llcp_core.c b/net/nfc/llcp_core.c index cd481490bcfe..da3cb0d29b97 100644 --- a/net/nfc/llcp_core.c +++ b/net/nfc/llcp_core.c @@ -1096,7 +1096,6 @@ static void nfc_llcp_recv_hdlc(struct nfc_llcp_local *local, if (sk->sk_state == LLCP_CLOSED) { release_sock(sk); nfc_llcp_sock_put(llcp_sock); - return; } /* Pass the payload upstream */ @@ -1188,7 +1187,6 @@ static void nfc_llcp_recv_disc(struct nfc_llcp_local *local, if (sk->sk_state == LLCP_CLOSED) { release_sock(sk); nfc_llcp_sock_put(llcp_sock); - return; } if (sk->sk_state == LLCP_CONNECTED) { diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index 9c6cc1cf547c..f7e02f9f9ed1 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -3117,7 +3117,6 @@ static int packet_release(struct socket *sock) spin_lock(&po->bind_lock); unregister_prot_hook(sk, false); - WRITE_ONCE(po->num, 0); packet_cached_dev_reset(po); if (po->prot_hook.dev) { diff --git a/net/rfkill/core.c b/net/rfkill/core.c index 97101c55763d..5bba7c36ac74 100644 --- a/net/rfkill/core.c +++ b/net/rfkill/core.c @@ -1317,7 +1317,7 @@ static const struct file_operations rfkill_fops = { .release = rfkill_fop_release, #ifdef CONFIG_RFKILL_INPUT .unlocked_ioctl = rfkill_fop_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = rfkill_fop_ioctl, #endif .llseek = no_llseek, }; diff --git a/net/sctp/socket.c b/net/sctp/socket.c index 50b6b6ee734b..9f775a482443 100644 --- a/net/sctp/socket.c +++ b/net/sctp/socket.c @@ -1338,7 +1338,7 @@ static int __sctp_setsockopt_connectx(struct sock *sk, kaddrs = memdup_user(addrs, addrs_size); if (IS_ERR(kaddrs)) - return PTR_ERR(kaddrs); + return PTR_ERR(kaddrs) == -EFAULT ? -EINVAL : PTR_ERR(kaddrs); /* Allow security module to validate connectx addresses. */ err = security_sctp_bind_connect(sk, SCTP_SOCKOPT_CONNECTX, diff --git a/net/tipc/msg.c b/net/tipc/msg.c index 5ba2c8ec8e11..ff167decbef1 100644 --- a/net/tipc/msg.c +++ b/net/tipc/msg.c @@ -175,20 +175,8 @@ int tipc_buf_append(struct sk_buff **headbuf, struct sk_buff **buf) if (fragid == LAST_FRAGMENT) { TIPC_SKB_CB(head)->validated = false; - - /* If the reassembled skb has been freed in - * tipc_msg_validate() because of an invalid truesize, - * then head will point to a newly allocated reassembled - * skb, while *headbuf points to freed reassembled skb. - * In such cases, correct *headbuf for freeing the newly - * allocated reassembled skb later. - */ - if (unlikely(!tipc_msg_validate(&head))) { - if (head != *headbuf) - *headbuf = head; + if (unlikely(!tipc_msg_validate(&head))) goto err; - } - *buf = head; TIPC_SKB_CB(head)->tail = NULL; *headbuf = NULL; diff --git a/net/xfrm/Kconfig b/net/xfrm/Kconfig index 86656a3dc24f..e5815cb2c297 100644 --- a/net/xfrm/Kconfig +++ b/net/xfrm/Kconfig @@ -3,13 +3,13 @@ # XFRM configuration # config XFRM - bool - depends on INET - select GRO_CELLS - select SKB_EXTENSIONS + bool + depends on INET + select GRO_CELLS + select SKB_EXTENSIONS config XFRM_OFFLOAD - bool + bool config XFRM_ALGO tristate diff --git a/scripts/Kconfig.include b/scripts/Kconfig.include index 363c354e9562..496d11c92c97 100644 --- a/scripts/Kconfig.include +++ b/scripts/Kconfig.include @@ -51,9 +51,3 @@ gcc-version := $(shell,$(srctree)/scripts/gcc-version.sh $(CC)) cc-option-bit = $(if-success,$(CC) -Werror $(1) -E -x c /dev/null -o /dev/null,$(1)) m32-flag := $(cc-option-bit,-m32) m64-flag := $(cc-option-bit,-m64) - -# Get the assembler name, version, and error out if it is not supported. -as-info := $(shell,$(srctree)/scripts/as-version.sh $(CC) $(CLANG_FLAGS)) -$(error-if,$(success,test -z "$(as-info)"),Sorry$(comma) this assembler is not supported.) -as-name := $(shell,set -- $(as-info) && echo $1) -as-version := $(shell,set -- $(as-info) && echo $2) diff --git a/scripts/as-version.sh b/scripts/as-version.sh deleted file mode 100755 index 532270bd4b7e..000000000000 --- a/scripts/as-version.sh +++ /dev/null @@ -1,69 +0,0 @@ -#!/bin/sh -# SPDX-License-Identifier: GPL-2.0-only -# -# Print the assembler name and its version in a 5 or 6-digit form. -# Also, perform the minimum version check. -# (If it is the integrated assembler, return 0 as the version, and -# skip the version check.) - -set -e - -# Convert the version string x.y.z to a canonical 5 or 6-digit form. -get_canonical_version() -{ - IFS=. - set -- $1 - - # If the 2nd or 3rd field is missing, fill it with a zero. - # - # The 4th field, if present, is ignored. - # This occurs in development snapshots as in 2.35.1.20201116 - echo $((10000 * $1 + 100 * ${2:-0} + ${3:-0})) -} - -# Clang fails to handle -Wa,--version unless -fno-integrated-as is given. -# We check -fintegrated-as, expecting it is explicitly passed in for the -# integrated assembler case. -check_integrated_as() -{ - while [ $# -gt 0 ]; do - if [ "$1" = -fintegrated-as ]; then - # For the integrated assembler, we do not check the - # version here. It is the same as the clang version, and - # it has been already checked by scripts/cc-version.sh. - echo LLVM 0 - exit 0 - fi - shift - done -} - -check_integrated_as "$@" - -orig_args="$@" - -# Get the first line of the --version output. -IFS=' -' -set -- $(LC_ALL=C "$@" -Wa,--version -c -x assembler /dev/null -o /dev/null 2>/dev/null) - -# Split the line on spaces. -IFS=' ' -set -- $1 - -if [ "$1" = GNU -a "$2" = assembler ]; then - shift $(($# - 1)) - version=$1 - name=GNU -else - echo "$orig_args: unknown assembler invoked" >&2 - exit 1 -fi - -# Some distributions append a package release number, as in 2.34-4.fc32 -# Trim the hyphen and any characters that follow. -version=${version%-*} - -cversion=$(get_canonical_version $version) - -echo $name $cversion diff --git a/scripts/dummy-tools/gcc b/scripts/dummy-tools/gcc deleted file mode 100755 index 9f5e943e7491..000000000000 --- a/scripts/dummy-tools/gcc +++ /dev/null @@ -1,98 +0,0 @@ -#!/bin/sh -# SPDX-License-Identifier: GPL-2.0-only -# -# Staring v4.18, Kconfig evaluates compiler capabilities, and hides CONFIG -# options your compiler does not support. This works well if you configure and -# build the kernel on the same host machine. -# -# It is inconvenient if you prepare the .config that is carried to a different -# build environment (typically this happens when you package the kernel for -# distros) because using a different compiler potentially produces different -# CONFIG options than the real build environment. So, you probably want to make -# as many options visible as possible. In other words, you need to create a -# super-set of CONFIG options that cover any build environment. If some of the -# CONFIG options turned out to be unsupported on the build machine, they are -# automatically disabled by the nature of Kconfig. -# -# However, it is not feasible to get a full-featured compiler for every arch. -# Hence these dummy toolchains to make all compiler tests pass. -# -# Usage: -# -# From the top directory of the source tree, run -# -# $ make CROSS_COMPILE=scripts/dummy-tools/ oldconfig -# -# Most of compiler features are tested by cc-option, which simply checks the -# exit code of $(CC). This script does nothing and just exits with 0 in most -# cases. So, $(cc-option, ...) is evaluated as 'y'. -# -# This scripts caters to more checks; handle --version and pre-process __GNUC__ -# etc. to pretend to be GCC, and also do right things to satisfy some scripts. - -# Check if the first parameter appears in the rest. Succeeds if found. -# This helper is useful if a particular option was passed to this script. -# Typically used like this: -# arg_contain "$@" -arg_contain () -{ - search="$1" - shift - - while [ $# -gt 0 ] - do - if [ "$search" = "$1" ]; then - return 0 - fi - shift - done - - return 1 -} - -# To set CONFIG_CC_IS_GCC=y -if arg_contain --version "$@"; then - echo "gcc (scripts/dummy-tools/gcc)" - exit 0 -fi - -if arg_contain -E "$@"; then - # For scripts/gcc-version.sh; This emulates GCC 20.0.0 - if arg_contain - "$@"; then - sed 's/^__GNUC__$/20/; s/^__GNUC_MINOR__$/0/; s/^__GNUC_PATCHLEVEL__$/0/' - exit 0 - else - echo "no input files" >&2 - exit 1 - fi -fi - -# To set CONFIG_AS_IS_GNU -if arg_contain -Wa,--version "$@"; then - echo "GNU assembler (scripts/dummy-tools) 2.50" - exit 0 -fi - -if arg_contain -S "$@"; then - # For scripts/gcc-x86-*-has-stack-protector.sh - if arg_contain -fstack-protector "$@"; then - echo "%gs" - exit 0 - fi -fi - -# To set GCC_PLUGINS -if arg_contain -print-file-name=plugin "$@"; then - plugin_dir=$(mktemp -d) - - mkdir -p $plugin_dir/include - touch $plugin_dir/include/plugin-version.h - - echo $plugin_dir - exit 0 -fi - -# inverted return value -if arg_contain -D__SIZEOF_INT128__=0 "$@"; then - exit 1 -fi diff --git a/scripts/dummy-tools/ld b/scripts/dummy-tools/ld deleted file mode 100755 index f68233050405..000000000000 --- a/scripts/dummy-tools/ld +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/sh -# SPDX-License-Identifier: GPL-2.0-only - -# Dummy script that always succeeds. - -# Check if the first parameter appears in the rest. Succeeds if found. -# This helper is useful if a particular option was passed to this script. -# Typically used like this: -# arg_contain "$@" -arg_contain () -{ - search="$1" - shift - - while [ $# -gt 0 ] - do - if [ "$search" = "$1" ]; then - return 0 - fi - shift - done - - return 1 -} - -if arg_contain --version "$@" || arg_contain -v "$@"; then - progname=$(basename $0) - echo "GNU $progname (scripts/dummy-tools/$progname) 2.50" - exit 0 -fi diff --git a/scripts/dummy-tools/nm b/scripts/dummy-tools/nm deleted file mode 120000 index c0648b38dd42..000000000000 --- a/scripts/dummy-tools/nm +++ /dev/null @@ -1 +0,0 @@ -ld \ No newline at end of file diff --git a/scripts/dummy-tools/objcopy b/scripts/dummy-tools/objcopy deleted file mode 120000 index c0648b38dd42..000000000000 --- a/scripts/dummy-tools/objcopy +++ /dev/null @@ -1 +0,0 @@ -ld \ No newline at end of file diff --git a/scripts/headers_install.sh b/scripts/headers_install.sh index da1d8fe8380a..be8626cdcd12 100755 --- a/scripts/headers_install.sh +++ b/scripts/headers_install.sh @@ -97,7 +97,6 @@ include/uapi/linux/eventpoll.h:CONFIG_PM_SLEEP include/uapi/linux/hw_breakpoint.h:CONFIG_HAVE_MIXED_BREAKPOINTS_REGS include/uapi/linux/pktcdvd.h:CONFIG_CDROM_PKTCDVD_WCACHE include/uapi/linux/raw.h:CONFIG_MAX_RAW_DEVS -techpack/camera/include/uapi/camera/media/cam_ope.h:CONFIG_SPECTRA_CAMERA_LEGACY " for c in $configs diff --git a/scripts/tools-support-relr.sh b/scripts/tools-support-relr.sh index 4c121946e517..cb55878bd5b8 100755 --- a/scripts/tools-support-relr.sh +++ b/scripts/tools-support-relr.sh @@ -7,12 +7,8 @@ trap "rm -f $tmp_file.o $tmp_file $tmp_file.bin" EXIT cat << "END" | $CC -c -x c - -o $tmp_file.o >/dev/null 2>&1 void *p = &p; END - -# ld.lld before 15 did not support -z pack-relative-relocs. -if ! $LD $tmp_file.o -shared -Bsymbolic --pack-dyn-relocs=relr -o $tmp_file 2>/dev/null; then - $LD $tmp_file.o -shared -Bsymbolic -z pack-relative-relocs -o $tmp_file 2>&1 | - grep -q pack-relative-relocs && exit 1 -fi +$LD $tmp_file.o -shared -Bsymbolic --pack-dyn-relocs=relr \ + --use-android-relr-tags -o $tmp_file # Despite printing an error message, GNU nm still exits with exit code 0 if it # sees a relr section. So we need to check that nothing is printed to stderr. diff --git a/security/lockdown/lockdown.c b/security/lockdown/lockdown.c index 81dad4f40141..655a6edb5d7f 100644 --- a/security/lockdown/lockdown.c +++ b/security/lockdown/lockdown.c @@ -33,7 +33,6 @@ static const char *const lockdown_reasons[LOCKDOWN_CONFIDENTIALITY_MAX+1] = { [LOCKDOWN_MMIOTRACE] = "unsafe mmio", [LOCKDOWN_DEBUGFS] = "debugfs access", [LOCKDOWN_XMON_WR] = "xmon write access", - [LOCKDOWN_BPF_WRITE_USER] = "use of bpf to write user RAM", [LOCKDOWN_DBG_WRITE_KERNEL] = "use of kgdb/kdb to write kernel RAM", [LOCKDOWN_INTEGRITY_MAX] = "integrity", [LOCKDOWN_KCORE] = "/proc/kcore access", diff --git a/security/selinux/include/classmap.h b/security/selinux/include/classmap.h index d77f52b70671..78ece5ab9886 100644 --- a/security/selinux/include/classmap.h +++ b/security/selinux/include/classmap.h @@ -27,10 +27,9 @@ "audit_control", "setfcap" #define COMMON_CAP2_PERMS "mac_override", "mac_admin", "syslog", \ - "wake_alarm", "block_suspend", "audit_read", "perfmon", "bpf", \ - "checkpoint_restore" + "wake_alarm", "block_suspend", "audit_read", "perfmon", "bpf" -#if CAP_LAST_CAP > CAP_CHECKPOINT_RESTORE +#if CAP_LAST_CAP > CAP_BPF #error New capability defined, please update COMMON_CAP2_PERMS. #endif diff --git a/techpack/audio/asoc/codecs/wcd938x/wcd938x.c b/techpack/audio/asoc/codecs/wcd938x/wcd938x.c index d124b31b8e9c..5f33ec26f4b8 100644 --- a/techpack/audio/asoc/codecs/wcd938x/wcd938x.c +++ b/techpack/audio/asoc/codecs/wcd938x/wcd938x.c @@ -3381,35 +3381,35 @@ static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = { SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch, ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC0, + SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1, 0, dmic1_switch, ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC1, + SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2, 0, dmic2_switch, ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC2, + SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3, 0, dmic3_switch, ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC3, + SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4, 0, dmic4_switch, ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC4, + SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5, 0, dmic5_switch, ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC5, + SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6, 0, dmic6_switch, ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC6, + SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7, 0, dmic7_switch, ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC7, + SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8, 0, dmic8_switch, ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), diff --git a/techpack/audio/asoc/codecs/wcd_cpe_services.c b/techpack/audio/asoc/codecs/wcd_cpe_services.c index fb6e1de56a21..96e2bb1945a4 100644 --- a/techpack/audio/asoc/codecs/wcd_cpe_services.c +++ b/techpack/audio/asoc/codecs/wcd_cpe_services.c @@ -987,7 +987,7 @@ static enum cpe_svc_result broadcast_boot_event( static enum cpe_process_result cpe_boot_initialize(struct cpe_info *t_info, enum cpe_svc_result *cpe_rc) { - enum cpe_process_result rc = CPE_PROC_FAILED; + enum cpe_process_result rc = CPE_SVC_FAILED; struct cpe_svc_notification payload; struct cmi_core_svc_event_system_boot *p = NULL; @@ -1991,7 +1991,7 @@ enum cmi_api_result cmi_send_msg(void *message) GFP_ATOMIC); if (!msg) { CPE_SVC_REL_LOCK(&cpe_d.cpe_api_mutex, "cpe_api"); - return CMI_API_NO_MEMORY; + return CPE_SVC_NO_MEMORY; } if (CMI_HDR_GET_OBM_FLAG(hdr) == CMI_OBM_FLAG_OUT_BAND) @@ -2006,7 +2006,7 @@ enum cmi_api_result cmi_send_msg(void *message) if (!msg->payload) { kfree(msg); CPE_SVC_REL_LOCK(&cpe_d.cpe_api_mutex, "cpe_api"); - return CMI_API_NO_MEMORY; + return CPE_SVC_NO_MEMORY; } msg->address = 0; diff --git a/techpack/audio/asoc/lahaina-port-config.h b/techpack/audio/asoc/lahaina-port-config.h index 12f89b0620b5..62cdd512be20 100644 --- a/techpack/audio/asoc/lahaina-port-config.h +++ b/techpack/audio/asoc/lahaina-port-config.h @@ -75,8 +75,8 @@ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */ static struct port_params tx_frame_params_shima[SWR_MSTR_PORT_LEN] = { {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX1 */ - {7, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ - {7, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX3 */ + {7, 5, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ + {7, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */ }; /* 4.8 MHz clock */ diff --git a/techpack/audio/asoc/msm-audio-effects-q6-v2.c b/techpack/audio/asoc/msm-audio-effects-q6-v2.c index 4a7b4b32654e..cb795f5bef45 100644 --- a/techpack/audio/asoc/msm-audio-effects-q6-v2.c +++ b/techpack/audio/asoc/msm-audio-effects-q6-v2.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -1092,7 +1091,7 @@ int msm_audio_effects_popless_eq_handler(struct audio_client *ac, u32 packed_data_size = 0; u8 *eq_config_data = NULL; u32 *updt_config_data = NULL; - int config_param_length, prev_config_param_length = 0; + int config_param_length; pr_debug("%s\n", __func__); if (!ac || (devices == -EINVAL) || (num_commands == -EINVAL)) { @@ -1212,12 +1211,7 @@ int msm_audio_effects_popless_eq_handler(struct audio_client *ac, if (!eq_config_data) eq_config_data = kzalloc(config_param_length, GFP_KERNEL); - else if (config_param_length != prev_config_param_length) { - if (eq_config_data) - kfree(eq_config_data); - eq_config_data = kzalloc(config_param_length, - GFP_KERNEL); - } else + else memset(eq_config_data, 0, config_param_length); if (!eq_config_data) { pr_err("%s, EQ_CONFIG:memory alloc failed\n", @@ -1244,7 +1238,6 @@ int msm_audio_effects_popless_eq_handler(struct audio_client *ac, *updt_config_data++ = eq->per_band_cfg[idx].band_idx; } - prev_config_param_length = config_param_length; break; case EQ_BAND_INDEX: if (length != 1 || index_offset != 0) { @@ -1327,8 +1320,7 @@ int msm_audio_effects_popless_eq_handler(struct audio_client *ac, pr_debug("%s: did not send pp params\n", __func__); invalid_config: kfree(params); - if (eq_config_data) - kfree(eq_config_data); + kfree(eq_config_data); return rc; } EXPORT_SYMBOL(msm_audio_effects_popless_eq_handler); diff --git a/techpack/audio/asoc/msm-compress-q6-v2.c b/techpack/audio/asoc/msm-compress-q6-v2.c index df48c414b05b..14f549310547 100644 --- a/techpack/audio/asoc/msm-compress-q6-v2.c +++ b/techpack/audio/asoc/msm-compress-q6-v2.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.​ */ @@ -4220,7 +4219,6 @@ static int msm_compr_adsp_stream_cmd_put(struct snd_kcontrol *kcontrol, return -EINVAL; } - mutex_lock(&pdata->lock); cstream = pdata->cstream[fe_id]; if (cstream == NULL) { pr_err("%s cstream is null\n", __func__); @@ -4233,6 +4231,7 @@ static int msm_compr_adsp_stream_cmd_put(struct snd_kcontrol *kcontrol, return -EINVAL; } + mutex_lock(&pdata->lock); if (prtd->audio_client == NULL) { pr_err("%s: audio_client is null\n", __func__); ret = -EINVAL; diff --git a/techpack/audio/asoc/msm-lsm-client.c b/techpack/audio/asoc/msm-lsm-client.c index 7d69b97ca7c6..bd9b73571263 100644 --- a/techpack/audio/asoc/msm-lsm-client.c +++ b/techpack/audio/asoc/msm-lsm-client.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -42,11 +42,6 @@ #define LSM_IS_LAST_STAGE(client, stage_idx) \ (client->num_stages == (stage_idx + 1)) -struct lsm_char_dev { - /* Protects access to LSM client sessions and shared resources */ - struct mutex lock; -}; - static struct snd_pcm_hardware msm_pcm_hardware_capture = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_BLOCK_TRANSFER | @@ -688,47 +683,15 @@ static int msm_lsm_set_conf(struct snd_pcm_substream *substream, struct lsm_params_info_v2 *p_info) { struct snd_pcm_runtime *runtime = substream->runtime; - struct lsm_priv *prtd = NULL; + struct lsm_priv *prtd = runtime->private_data; struct snd_soc_pcm_runtime *rtd = substream->private_data; int rc = 0; - struct lsm_char_dev *lsm_dev; - struct snd_soc_component *component = NULL; - - if (!rtd) { - pr_err("%s substream runtime or private_data not found\n", - __func__); - return -EINVAL; - } - component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); - if (!component || !component->dev) { - pr_err("%s: invalid component\n", __func__); - return -EINVAL; - } - lsm_dev = (struct lsm_char_dev *) dev_get_drvdata(component->dev); - if (!lsm_dev) { - pr_err("%s: platform data is NULL\n", __func__); - return -EINVAL; - } - - mutex_lock(&lsm_dev->lock); - if (!runtime) { - pr_err("%s: Invalid runtime", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } - prtd = runtime->private_data; - if (!prtd || !prtd->lsm_client) { - pr_err("%s: No LSM session active\n", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } if (p_info->param_type == LSM_MULTI_SND_MODEL_CONFIDENCE_LEVELS) { if (p_info->param_size > MAX_KEYWORDS_SUPPORTED) { dev_err(rtd->dev, "%s: invalid number of snd_model keywords %d, the max is %d\n", __func__, p_info->param_size, MAX_KEYWORDS_SUPPORTED); - mutex_unlock(&lsm_dev->lock); return -EINVAL; } @@ -739,7 +702,6 @@ static int msm_lsm_set_conf(struct snd_pcm_substream *substream, dev_err(rtd->dev, "%s: get_conf_levels failed for snd_model %d, err = %d\n", __func__, p_info->model_id, rc); - mutex_unlock(&lsm_dev->lock); return rc; } @@ -760,7 +722,6 @@ static int msm_lsm_set_conf(struct snd_pcm_substream *substream, dev_err(rtd->dev, "%s: invalid confidence levels %d\n", __func__, p_info->param_size); - mutex_unlock(&lsm_dev->lock); return -EINVAL; } @@ -772,7 +733,6 @@ static int msm_lsm_set_conf(struct snd_pcm_substream *substream, dev_err(rtd->dev, "%s: get_conf_levels failed, err = %d\n", __func__, rc); - mutex_unlock(&lsm_dev->lock); return rc; } @@ -789,7 +749,6 @@ static int msm_lsm_set_conf(struct snd_pcm_substream *substream, prtd->lsm_client->confidence_levels = NULL; } } - mutex_unlock(&lsm_dev->lock); return rc; } @@ -1030,63 +989,23 @@ static int msm_lsm_check_and_set_lab_controls(struct snd_pcm_substream *substrea u32 enable, struct lsm_params_info_v2 *p_info) { struct snd_pcm_runtime *runtime = substream->runtime; - struct lsm_priv *prtd = NULL; + struct lsm_priv *prtd = runtime->private_data; struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct lsm_hw_params *out_hw_params = NULL; - struct snd_soc_component *component = NULL; - struct lsm_char_dev *lsm_dev = NULL; + struct lsm_hw_params *out_hw_params = &prtd->lsm_client->out_hw_params; u8 *chmap = NULL; u32 ch_idx; int rc = 0, stage_idx = p_info->stage_idx; - if (!rtd) { - pr_err("%s substream runtime or private_data not found\n", - __func__); - return -EINVAL; - } - component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); - if (!component || !component->dev) { - pr_err("%s: invalid component\n", __func__); - return -EINVAL; - } - lsm_dev = (struct lsm_char_dev *) dev_get_drvdata(component->dev); - if (!lsm_dev) { - pr_err("%s: platform data is NULL\n", __func__); - return -EINVAL; - } - - mutex_lock(&lsm_dev->lock); - if (!runtime) { - pr_err("%s: Invalid runtime", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } - prtd = runtime->private_data; - if (!prtd || !prtd->lsm_client) { - pr_err("%s: No LSM session active\n", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } - out_hw_params = &prtd->lsm_client->out_hw_params; - if (!out_hw_params) { - pr_err("%s: Invalid hw params\n", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } - if (prtd->lsm_client->stage_cfg[stage_idx].lab_enable == enable) { dev_dbg(rtd->dev, "%s: Lab for session %d, stage %d already %s\n", __func__, prtd->lsm_client->session, stage_idx, enable ? "enabled" : "disabled"); - mutex_unlock(&lsm_dev->lock); return rc; } chmap = kzalloc(out_hw_params->num_chs, GFP_KERNEL); - if (!chmap) { - mutex_unlock(&lsm_dev->lock); + if (!chmap) return -ENOMEM; - } rc = q6lsm_lab_control(prtd->lsm_client, enable, p_info); if (rc) { @@ -1127,7 +1046,6 @@ static int msm_lsm_check_and_set_lab_controls(struct snd_pcm_substream *substrea fail: kfree(chmap); - mutex_unlock(&lsm_dev->lock); return rc; } @@ -3188,11 +3106,9 @@ static int msm_lsm_close(struct snd_pcm_substream *substream) { unsigned long flags; struct snd_pcm_runtime *runtime = substream->runtime; - struct lsm_priv *prtd = NULL; + struct lsm_priv *prtd = runtime->private_data; struct snd_soc_pcm_runtime *rtd; struct msm_pcm_stream_app_type_cfg cfg_data = {0}; - struct lsm_char_dev *lsm_dev; - struct snd_soc_component *component = NULL; int ret = 0; int be_id = 0; int fe_id = 0; @@ -3201,29 +3117,12 @@ static int msm_lsm_close(struct snd_pcm_substream *substream) pr_err("%s: Invalid private_data", __func__); return -EINVAL; } - if (!component || !component->dev) { - pr_err("%s: Invalid component\n", __func__); + if (!prtd || !prtd->lsm_client) { + pr_err("%s: No LSM session active\n", __func__); return -EINVAL; } rtd = substream->private_data; - lsm_dev = (struct lsm_char_dev *) dev_get_drvdata(component->dev); - if (!lsm_dev) { - pr_err("%s: platform data is NULL\n", __func__); - return -EINVAL; - } - mutex_lock(&lsm_dev->lock); - if (!runtime) { - pr_err("%s: Invalid runtime", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } - prtd = runtime->private_data; - if (!prtd || !prtd->lsm_client) { - pr_err("%s: No LSM session active\n", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } dev_dbg(rtd->dev, "%s\n", __func__); if (prtd->lsm_client->started) { if (prtd->lsm_client->lab_enable) { @@ -3333,7 +3232,6 @@ static int msm_lsm_close(struct snd_pcm_substream *substream) mutex_destroy(&prtd->lsm_api_lock); kfree(prtd); runtime->private_data = NULL; - mutex_unlock(&lsm_dev->lock); return 0; } @@ -3342,36 +3240,21 @@ static int msm_lsm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_pcm_runtime *runtime = substream->runtime; - struct lsm_priv *prtd = NULL; + struct lsm_priv *prtd = runtime->private_data; struct lsm_hw_params *out_hw_params = NULL; struct lsm_hw_params *in_hw_params = NULL; struct snd_soc_pcm_runtime *rtd; - struct lsm_char_dev *lsm_dev = NULL; - struct snd_soc_component *component = NULL; if (!substream->private_data) { pr_err("%s: Invalid private_data", __func__); return -EINVAL; } rtd = substream->private_data; - component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); - if (!component || !component->dev) { - pr_err("%s: Invalid component\n", __func__); - return -EINVAL; - } - lsm_dev = (struct lsm_char_dev *) dev_get_drvdata(component->dev); - if (!lsm_dev) { - pr_err("%s: platform data is NULL\n", __func__); - return -EINVAL; - } - mutex_lock(&lsm_dev->lock); - prtd = runtime->private_data; if (!prtd || !params) { dev_err(rtd->dev, "%s: invalid params prtd %pK params %pK", __func__, prtd, params); - mutex_unlock(&lsm_dev->lock); return -EINVAL; } in_hw_params = &prtd->lsm_client->in_hw_params; @@ -3386,7 +3269,6 @@ static int msm_lsm_hw_params(struct snd_pcm_substream *substream, "%s: Invalid Params sample rate %d period count %d\n", __func__, out_hw_params->sample_rate, out_hw_params->period_count); - mutex_unlock(&lsm_dev->lock); return -EINVAL; } @@ -3397,7 +3279,6 @@ static int msm_lsm_hw_params(struct snd_pcm_substream *substream, } else { dev_err(rtd->dev, "%s: Invalid Format 0x%x\n", __func__, params_format(params)); - mutex_unlock(&lsm_dev->lock); return -EINVAL; } @@ -3418,7 +3299,6 @@ static int msm_lsm_hw_params(struct snd_pcm_substream *substream, */ memcpy(in_hw_params, out_hw_params, sizeof(struct lsm_hw_params)); - mutex_unlock(&lsm_dev->lock); return 0; } @@ -3749,14 +3629,6 @@ static struct snd_soc_component_driver msm_soc_component = { static int msm_lsm_probe(struct platform_device *pdev) { - struct lsm_char_dev *lsm_dev; - - lsm_dev = devm_kzalloc(&pdev->dev, sizeof(*lsm_dev), GFP_KERNEL); - if (!lsm_dev) - return -ENOMEM; - - mutex_init(&lsm_dev->lock); - dev_set_drvdata(&pdev->dev, lsm_dev); return snd_soc_register_component(&pdev->dev, &msm_soc_component, NULL, 0); @@ -3764,10 +3636,6 @@ static int msm_lsm_probe(struct platform_device *pdev) static int msm_lsm_remove(struct platform_device *pdev) { - struct lsm_char_dev *lsm_dev; - lsm_dev = dev_get_drvdata(&pdev->dev); - mutex_destroy(&lsm_dev->lock); - snd_soc_unregister_component(&pdev->dev); return 0; diff --git a/techpack/audio/asoc/msm-pcm-routing-v2.c b/techpack/audio/asoc/msm-pcm-routing-v2.c index 09b6ed61dd61..c3b5f480993f 100644 --- a/techpack/audio/asoc/msm-pcm-routing-v2.c +++ b/techpack/audio/asoc/msm-pcm-routing-v2.c @@ -26945,10 +26945,6 @@ static const struct snd_kcontrol_new mmul17_mixer_controls[] = { MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, @@ -41421,7 +41417,6 @@ static const struct snd_soc_dapm_route intercon_mi2s[] = { {"MultiMedia29 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, {"MultiMedia30 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, {"MultiMedia8 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia17 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, {"MultiMedia18 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, {"MultiMedia19 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, {"MultiMedia28 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, diff --git a/techpack/audio/asoc/msm_dailink.h b/techpack/audio/asoc/msm_dailink.h index ef588206d321..c7353b9ae05d 100644 --- a/techpack/audio/asoc/msm_dailink.h +++ b/techpack/audio/asoc/msm_dailink.h @@ -957,8 +957,7 @@ SND_SOC_DAILINK_DEFS(quat_mi2s_tx, SND_SOC_DAILINK_DEFS(quin_mi2s_rx, DAILINK_COMP_ARRAY(COMP_CPU("msm-dai-q6-mi2s.8")), - DAILINK_COMP_ARRAY(COMP_CODEC("msm-stub-codec.1", "msm-stub-rx"), - COMP_CODEC("acm8625s_codec", "acm8625s-hifi")), + DAILINK_COMP_ARRAY(COMP_CODEC("msm-stub-codec.1", "msm-stub-rx")), DAILINK_COMP_ARRAY(COMP_PLATFORM("msm-pcm-routing"))); SND_SOC_DAILINK_DEFS(quin_mi2s_tx, diff --git a/techpack/audio/dsp/q6adm.c b/techpack/audio/dsp/q6adm.c index 15a1d7830ebd..cd876fde3f37 100644 --- a/techpack/audio/dsp/q6adm.c +++ b/techpack/audio/dsp/q6adm.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -3911,14 +3911,10 @@ void adm_copp_mfc_cfg(int port_id, int copp_idx, int dst_sample_rate) pr_err("%s: unable to get channal map\n", __func__); goto fail_cmd; } - if (mfc_cfg.num_channels <= AUDPROC_MFC_OUT_CHANNELS_MAX) { - for (i = 0; i < mfc_cfg.num_channels; i++) - mfc_cfg.channel_type[i] = + + for (i = 0; i < mfc_cfg.num_channels; i++) + mfc_cfg.channel_type[i] = (uint16_t) open.dev_channel_mapping[i]; - } else { - pr_err("%s: size of num_channels is greater than channel type \n", __func__); - goto fail_cmd; - } atomic_set(&this_adm.copp.stat[port_idx][copp_idx], -1); diff --git a/techpack/camera/Makefile b/techpack/camera/Makefile index 81116b28ebb3..2568ff61c873 100644 --- a/techpack/camera/Makefile +++ b/techpack/camera/Makefile @@ -94,11 +94,6 @@ endif endif -ifeq ($(CONFIG_IBIZA_DTB), y) -LINUXINCLUDE += \ - -include $(srctree)/techpack/camera/config/legacycameraconf.h -endif - ifneq (,$(filter $(CONFIG_SPECTRA_CAMERA), y m)) # Use USERINCLUDE when you must reference the UAPI directories only. USERINCLUDE += \ diff --git a/techpack/camera/config/legacycameraconf.h b/techpack/camera/config/legacycameraconf.h deleted file mode 100644 index 6a17cb1ff12f..000000000000 --- a/techpack/camera/config/legacycameraconf.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#define CONFIG_SPECTRA_CAMERA_LEGACY 1 diff --git a/techpack/camera/drivers/cam_core/cam_node.c b/techpack/camera/drivers/cam_core/cam_node.c index f9fa98fe6c5c..d27bcdd6bf0d 100644 --- a/techpack/camera/drivers/cam_core/cam_node.c +++ b/techpack/camera/drivers/cam_core/cam_node.c @@ -812,7 +812,6 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) } case CAM_ACQUIRE_HW: { uint32_t api_version; - uint32_t struct_version; void *acquire_ptr = NULL; size_t acquire_size; @@ -847,16 +846,6 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) } if (api_version == 1) { - struct_version = - ((struct cam_acquire_hw_cmd_v1 *)acquire_ptr)->struct_version; - if (struct_version != api_version) { - CAM_ERR(CAM_CORE, - "Unmatched struct api version %u and struct version %u", - api_version, struct_version); - rc = -EINVAL; - goto acquire_kfree; - } - rc = __cam_node_handle_acquire_hw_v1(node, acquire_ptr); if (rc) { CAM_ERR(CAM_CORE, @@ -864,16 +853,6 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) goto acquire_kfree; } } else if (api_version == 2) { - struct_version = - ((struct cam_acquire_hw_cmd_v2 *)acquire_ptr)->struct_version; - if (struct_version != api_version) { - CAM_ERR(CAM_CORE, - "Unmatched struct api version %u and struct version %u", - api_version, struct_version); - rc = -EINVAL; - goto acquire_kfree; - } - rc = __cam_node_handle_acquire_hw_v2(node, acquire_ptr); if (rc) { CAM_ERR(CAM_CORE, diff --git a/techpack/camera/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/techpack/camera/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 900aeb051db1..137f126caedf 100644 --- a/techpack/camera/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/techpack/camera/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2022, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include diff --git a/techpack/camera/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c b/techpack/camera/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c index bda409c6453c..6d325961680c 100644 --- a/techpack/camera/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/techpack/camera/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -574,10 +574,8 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, /* Loop through multiple command buffers */ for (i = 0; i < csl_packet->num_cmd_buf; i++) { rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]); - if (rc) { - cam_mem_put_cpu_buf(config.packet_handle); + if (rc) return rc; - } total_cmd_buf_in_bytes = cmd_desc[i].length; if (!total_cmd_buf_in_bytes) diff --git a/techpack/camera/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/techpack/camera/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 6e10d319a224..534a05cb82f0 100644 --- a/techpack/camera/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/techpack/camera/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -383,7 +383,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, CAM_ERR(CAM_CSIPHY, "Inval cam_packet strut size: %zu, len_of_buff: %zu", sizeof(struct cam_packet), len); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); rc = -EINVAL; return rc; } @@ -395,7 +394,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, if (cam_packet_util_validate_packet(csl_packet, remain_len)) { CAM_ERR(CAM_CSIPHY, "Invalid packet params"); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); rc = -EINVAL; return rc; } @@ -406,7 +404,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, csl_packet->cmd_buf_offset / 4); else { CAM_ERR(CAM_CSIPHY, "num_cmd_buffers = %d", csl_packet->num_cmd_buf); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); rc = -EINVAL; return rc; } @@ -414,7 +411,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, rc = cam_packet_util_validate_cmd_desc(cmd_desc); if (rc) { CAM_ERR(CAM_CSIPHY, "Invalid cmd desc ret: %d", rc); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); return rc; } @@ -423,7 +419,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, if (rc < 0) { CAM_ERR(CAM_CSIPHY, "Failed to get cmd buf Mem address : %d", rc); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); return rc; } @@ -431,8 +426,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, (cmd_desc->offset > (len - sizeof(struct cam_csiphy_info)))) { CAM_ERR(CAM_CSIPHY, "Not enough buffer provided for cam_cisphy_info"); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); - cam_mem_put_cpu_buf(cmd_desc->mem_handle); rc = -EINVAL; return rc; } @@ -444,7 +437,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, index = cam_csiphy_get_instance_offset(csiphy_dev, cfg_dev->dev_handle); if (index < 0 || index >= csiphy_dev->session_max_device_support) { CAM_ERR(CAM_CSIPHY, "index in invalid: %d", index); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); cam_mem_put_cpu_buf(cmd_desc->mem_handle); return -EINVAL; } @@ -455,7 +447,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, CAM_ERR(CAM_CSIPHY, "Wrong configuration lane_cnt: %u", cam_cmd_csiphy_info->lane_cnt); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); cam_mem_put_cpu_buf(cmd_desc->mem_handle); return rc; } diff --git a/techpack/camera/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/techpack/camera/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c index 5635e053f40c..9eca22741e75 100644 --- a/techpack/camera/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/techpack/camera/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -633,10 +633,8 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) for (i = 0; i < pkt->num_cmd_buf; i++) { rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]); - if (rc) { - cam_mem_put_cpu_buf(handle); + if (rc) return rc; - } if (!(cmd_desc[i].length)) continue; diff --git a/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c index 4e9fabc0d822..325e52e6a5a2 100644 --- a/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c +++ b/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c @@ -316,12 +316,12 @@ static int32_t cam_sensor_get_io_buffer( (uint8_t *)buf_addr + io_cfg->offsets[0]; i2c_settings->read_buff_len = buf_size - io_cfg->offsets[0]; - cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); } else { CAM_ERR(CAM_SENSOR, "Invalid direction: %d", io_cfg->direction); rc = -EINVAL; } + cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); return rc; } diff --git a/techpack/camera/include/uapi/camera/media/cam_ope.h b/techpack/camera/include/uapi/camera/media/cam_ope.h index ee6c3423860f..b6a9a41d8dfe 100644 --- a/techpack/camera/include/uapi/camera/media/cam_ope.h +++ b/techpack/camera/include/uapi/camera/media/cam_ope.h @@ -73,11 +73,7 @@ #define OPE_MAX_IO_BUFS (OPE_OUT_RES_MAX + OPE_IN_RES_MAX) #define OPE_MAX_PASS 1 #define OPE_MAX_PLANES 2 -#ifdef CONFIG_SPECTRA_CAMERA_LEGACY -#define OPE_MAX_STRIPES 48 -#else #define OPE_MAX_STRIPES 64 -#endif #define OPE_MAX_BATCH_SIZE 16 /** diff --git a/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c b/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c index 28285a6eed57..a3f090def566 100644 --- a/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c +++ b/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c @@ -710,10 +710,7 @@ static int __ipa3_del_hdr_proc_ctx(u32 proc_ctx_hdl, return 0; } - if (entry->hdr && entry == entry->hdr->proc_ctx) - entry->hdr->proc_ctx = NULL; - - if (entry->hdr && release_hdr) + if (release_hdr) __ipa3_del_hdr(entry->hdr->id, false); /* move the offset entry to appropriate free list */ @@ -777,19 +774,17 @@ int __ipa3_del_hdr(u32 hdr_hdl, bool by_user) return 0; } - if (entry->proc_ctx && entry == entry->proc_ctx->hdr) - entry->proc_ctx->hdr = NULL; - if (entry->is_hdr_proc_ctx || entry->proc_ctx) { dma_unmap_single(ipa3_ctx->pdev, entry->phys_base, entry->hdr_len, DMA_TO_DEVICE); __ipa3_del_hdr_proc_ctx(entry->proc_ctx->id, false, false); + } else { + /* move the offset entry to appropriate free list */ + list_move(&entry->offset_entry->link, + &htbl->head_free_offset_list[entry->offset_entry->bin]); } - /* move the offset entry to appropriate free list */ - list_move(&entry->offset_entry->link, - &htbl->head_free_offset_list[entry->offset_entry->bin]); list_del(&entry->link); htbl->hdr_cnt--; entry->cookie = 0; diff --git a/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c b/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c index 0db725a54626..c2232d59b691 100644 --- a/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c +++ b/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -771,9 +770,9 @@ int ipa_pm_register(struct ipa_pm_register_params *params, u32 *hdl) client->skip_clk_vote = params->skip_clk_vote; client->wlock = wakeup_source_register(NULL, client->name); if (!client->wlock) { + ipa_pm_deregister(*hdl); IPA_PM_ERR("IPA wakeup source register failed %s\n", client->name); - ipa_pm_deregister(*hdl); return -ENOMEM; } diff --git a/techpack/datarmnet-ext/shs/rmnet_shs_config.c b/techpack/datarmnet-ext/shs/rmnet_shs_config.c index a7988474c084..56115cc8d2a9 100644 --- a/techpack/datarmnet-ext/shs/rmnet_shs_config.c +++ b/techpack/datarmnet-ext/shs/rmnet_shs_config.c @@ -61,14 +61,14 @@ DATARMNET5fc54f7a13 __read_mostly={.notifier_call=DATARMNETe9173bbe0e,.priority= "\x49\x32\x36\x33\x33\x36\x37\x39\x61\x65\x36\x34\x37\x61\x30\x36\x36\x62\x32\x38\x36\x32\x66\x39\x31\x33\x30\x31\x31\x64\x33\x33\x65\x33\x38\x32\x36\x63\x61\x32\x35" , "\x49\x36\x36\x39\x35\x65\x39\x38\x30\x63\x35\x65\x37\x62\x62\x32\x39\x33\x36\x35\x63\x34\x37\x65\x31\x35\x33\x36\x64\x63\x31\x34\x65\x66\x61\x31\x63\x30\x30\x34\x33" -};static int DATARMNET2cb9ae589c;static int __init DATARMNET163e93649e(void){pr_info( +};static int DATARMNET2cb9ae589c;int __init DATARMNET163e93649e(void){pr_info( "\x25\x73\x28\x29\x3a\x20\x53\x74\x61\x72\x74\x69\x6e\x67\x20\x72\x6d\x6e\x65\x74\x20\x53\x48\x53\x20\x6d\x6f\x64\x75\x6c\x65\x20\x25\x73\x20" "\n" ,__func__,DATARMNETbc8418e817[(0xd2d+202-0xdf7)]);trace_rmnet_shs_high( DATARMNET1790979ccf,DATARMNET72cb00fdc0,(0x16e8+787-0xc0c),(0x16e8+787-0xc0c), (0x16e8+787-0xc0c),(0x16e8+787-0xc0c),NULL,NULL);if(DATARMNET0dbc627e8f()){ rm_err("\x25\x73", "\x53\x48\x53\x5f\x47\x4e\x4c\x3a\x20\x46\x61\x69\x6c\x65\x64\x20\x74\x6f\x20\x69\x6e\x69\x74\x20\x67\x65\x6e\x65\x72\x69\x63\x20\x6e\x65\x74\x6c\x69\x6e\x6b" -);}return register_netdevice_notifier(&DATARMNET5fc54f7a13);}static void __exit +);}return register_netdevice_notifier(&DATARMNET5fc54f7a13);}void __exit DATARMNETf3298dab6f(void){trace_rmnet_shs_high(DATARMNET1790979ccf, DATARMNET89958f9b63,(0x16e8+787-0xc0c),(0x16e8+787-0xc0c),(0x16e8+787-0xc0c), (0x16e8+787-0xc0c),NULL,NULL);unregister_netdevice_notifier(&DATARMNET5fc54f7a13 diff --git a/techpack/datarmnet-ext/shs/rmnet_shs_config.h b/techpack/datarmnet-ext/shs/rmnet_shs_config.h index 52a342bd3157..ac99913202f5 100644 --- a/techpack/datarmnet-ext/shs/rmnet_shs_config.h +++ b/techpack/datarmnet-ext/shs/rmnet_shs_config.h @@ -20,6 +20,7 @@ #define DATARMNET8120d41372 (0xd1f+216-0xdf5) #define DATARMNET47c2367f93 (0xd18+223-0xdf4) extern struct DATARMNETa6b20d7e8b DATARMNETecc0627c70;extern int -rmnet_is_real_dev_registered(const struct net_device*real_dev); +rmnet_is_real_dev_registered(const struct net_device*real_dev);int __init +DATARMNET163e93649e(void);void __exit DATARMNETf3298dab6f(void); #endif diff --git a/techpack/display/config/lahainadisp.conf b/techpack/display/config/lahainadisp.conf index 953a3ef338f8..d413be39445f 100644 --- a/techpack/display/config/lahainadisp.conf +++ b/techpack/display/config/lahainadisp.conf @@ -4,7 +4,7 @@ export CONFIG_DRM_MSM_DP=y export CONFIG_DRM_MSM_DP_MST=y export CONFIG_SYNC_FILE=y export CONFIG_DRM_MSM_DSI=y -export CONFIG_DSI_PARSER=n +export CONFIG_DSI_PARSER=y export CONFIG_DRM_SDE_WB=y export CONFIG_DRM_MSM_REGISTER_LOGGING=y export CONFIG_QCOM_MDSS_PLL=y diff --git a/techpack/display/config/lahainadispconf.h b/techpack/display/config/lahainadispconf.h index 3a0210956e2a..e72e0a43f1ab 100644 --- a/techpack/display/config/lahainadispconf.h +++ b/techpack/display/config/lahainadispconf.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ #define CONFIG_DRM_MSM 1 @@ -10,6 +9,7 @@ #define CONFIG_DRM_MSM_SDE 1 #define CONFIG_SYNC_FILE 1 #define CONFIG_DRM_MSM_DSI 1 +#define CONFIG_DSI_PARSER 1 #define CONFIG_DRM_SDE_WB 1 #define CONFIG_DRM_MSM_REGISTER_LOGGING 1 #define CONFIG_DRM_SDE_EVTLOG_DEBUG 1 diff --git a/techpack/display/msm/dp/dp_display.c b/techpack/display/msm/dp/dp_display.c index 0e7760d242d2..ddafc11d5921 100644 --- a/techpack/display/msm/dp/dp_display.c +++ b/techpack/display/msm/dp/dp_display.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ @@ -1184,7 +1184,6 @@ error_ctrl: static int dp_display_panel_ready(struct dp_display_private *dp) { int rc = 0; - bool skip_op = is_skip_required(&dp->dp_display); if (dp->dp_display.is_edp) { rc = dp->power->edp_panel_set_gpio(dp->power, DP_GPIO_EDP_VCC_EN, true); @@ -1202,9 +1201,9 @@ static int dp_display_panel_ready(struct dp_display_private *dp) } return -ETIMEDOUT; } - - dp->panel->init(dp->panel, skip_op); } + if (!dp->dp_display.cont_splash_enabled) + dp->panel->init(dp->panel); return 0; } @@ -1248,7 +1247,6 @@ static int dp_display_host_ready(struct dp_display_private *dp) dp->ctrl->abort(dp->ctrl, false); dp->aux->init(dp->aux, dp->parser->aux_cfg, skip_op); - dp_display_state_add(DP_STATE_READY); /* log this as it results from user action of cable connection */ DP_INFO("[OK]\n"); @@ -3920,7 +3918,6 @@ static int dp_display_get_display_type(struct dp_display *dp_display, const char **display_type) { struct dp_display_private *dp; - struct device_node *of_node; if (!dp_display || !display_type) { pr_err("invalid input\n"); @@ -3930,11 +3927,7 @@ static int dp_display_get_display_type(struct dp_display *dp_display, dp = container_of(dp_display, struct dp_display_private, dp_display); if (dp->parser) *display_type = dp->parser->display_type; - else { - of_node = dp->pdev->dev.of_node; - *display_type = of_get_property(of_node, "qcom,display-type", - NULL); - } + return 0; } diff --git a/techpack/display/msm/dp/dp_drm.c b/techpack/display/msm/dp/dp_drm.c index ad90da674401..6af98873cb38 100644 --- a/techpack/display/msm/dp/dp_drm.c +++ b/techpack/display/msm/dp/dp_drm.c @@ -471,7 +471,6 @@ int dp_connector_get_info(struct drm_connector *connector, { struct dp_display *display = data; const char *display_type = NULL; - u32 conn_disp_type = SDE_CONNECTOR_PRIMARY; if (!info || !display || !display->drm_dev) { DP_ERR("invalid params\n"); @@ -481,11 +480,11 @@ int dp_connector_get_info(struct drm_connector *connector, info->intf_type = DRM_MODE_CONNECTOR_DisplayPort; display->get_display_type(display, &display_type); - if (display_type) { + if (display_type){ if (!strcmp(display_type, "primary")) - conn_disp_type = SDE_CONNECTOR_PRIMARY; + info->display_type = SDE_CONNECTOR_PRIMARY; else if (!strcmp(display_type, "secondary")) - conn_disp_type = SDE_CONNECTOR_SECONDARY; + info->display_type = SDE_CONNECTOR_SECONDARY; } info->num_of_h_tiles = 1; @@ -496,8 +495,7 @@ int dp_connector_get_info(struct drm_connector *connector, if (display && display->is_edp) { info->intf_type = DRM_MODE_CONNECTOR_eDP; - info->display_type = conn_disp_type; - if (display->ext_hpd_en) + if(display->ext_hpd_en) info->capabilities |= MSM_DISPLAY_CAP_HOT_PLUG; else info->is_connected = true; diff --git a/techpack/display/msm/dp/dp_panel.c b/techpack/display/msm/dp/dp_panel.c index a9f65f1aba8c..8fc1b13c3e32 100644 --- a/techpack/display/msm/dp/dp_panel.c +++ b/techpack/display/msm/dp/dp_panel.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ @@ -2381,7 +2381,7 @@ error: return rc; } -static int dp_panel_init_panel_info(struct dp_panel *dp_panel, bool skip_op) +static int dp_panel_init_panel_info(struct dp_panel *dp_panel) { int rc = 0; struct dp_panel_private *panel; @@ -2393,9 +2393,6 @@ static int dp_panel_init_panel_info(struct dp_panel *dp_panel, bool skip_op) goto end; } - if (skip_op) - goto end; - panel = container_of(dp_panel, struct dp_panel_private, dp_panel); pinfo = &dp_panel->pinfo; diff --git a/techpack/display/msm/dp/dp_panel.h b/techpack/display/msm/dp/dp_panel.h index 206b62dc32c7..3abb41297584 100644 --- a/techpack/display/msm/dp/dp_panel.h +++ b/techpack/display/msm/dp/dp_panel.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. */ @@ -162,7 +162,7 @@ struct dp_panel { s64 fec_overhead_fp; - int (*init)(struct dp_panel *dp_panel, bool skip_op); + int (*init)(struct dp_panel *dp_panel); int (*deinit)(struct dp_panel *dp_panel, u32 flags); int (*hw_cfg)(struct dp_panel *dp_panel, bool enable); int (*read_sink_caps)(struct dp_panel *dp_panel, diff --git a/techpack/display/msm/dp/dp_parser.c b/techpack/display/msm/dp/dp_parser.c index 0a138bbe4a1d..ea5546ea476c 100644 --- a/techpack/display/msm/dp/dp_parser.c +++ b/techpack/display/msm/dp/dp_parser.c @@ -178,10 +178,13 @@ static int dp_parser_misc(struct dp_parser *parser) &parser->pixel_base_off[i]); } - parser->display_type = of_get_property(of_node, "qcom,display-type", - NULL); - if (!parser->display_type) - parser->display_type = "unknown"; + parser->display_type = of_get_property(of_node, "qcom,display-type", NULL); + if (!parser->display_type) { + if (parser->is_edp) + parser->display_type = "primary"; + else + parser->display_type = "secondary"; + } parser->panel_notifier_support = of_property_read_bool(of_node, "qcom,panel-notifier-support"); diff --git a/techpack/display/msm/dsi/dsi_ctrl.c b/techpack/display/msm/dsi/dsi_ctrl.c index 988b3e60a462..278e3dcbe921 100644 --- a/techpack/display/msm/dsi/dsi_ctrl.c +++ b/techpack/display/msm/dsi/dsi_ctrl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -229,10 +229,10 @@ static ssize_t debugfs_line_count_read(struct file *file, dsi_ctrl->cmd_trigger_frame); len += scnprintf((buf + len), max_len - len, "Command successful at line: %04x\n", - atomic_read(&dsi_ctrl->cmd_success_line)); + dsi_ctrl->cmd_success_line); len += scnprintf((buf + len), max_len - len, "Command successful at frame: %04x\n", - atomic_read(&dsi_ctrl->cmd_success_frame)); + dsi_ctrl->cmd_success_frame); mutex_unlock(&dsi_ctrl->ctrl_lock); @@ -2891,13 +2891,12 @@ static irqreturn_t dsi_ctrl_isr(int irq, void *ptr) if (dsi_ctrl->enable_cmd_dma_stats) { u32 reg = dsi_ctrl->hw.ops.log_line_count(&dsi_ctrl->hw, dsi_ctrl->cmd_mode); - atomic_set(&dsi_ctrl->cmd_success_line, (reg & 0xFFFF)); - atomic_set(&dsi_ctrl->cmd_success_frame, ((reg >> 16) & 0xFFFF)); + dsi_ctrl->cmd_success_line = (reg & 0xFFFF); + dsi_ctrl->cmd_success_frame = ((reg >> 16) & 0xFFFF); SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1, dsi_ctrl->cmd_success_line, dsi_ctrl->cmd_success_frame); } - atomic_set(&dsi_ctrl->dma_irq_trig, 1); dsi_ctrl_disable_status_interrupt(dsi_ctrl, DSI_SINT_CMD_MODE_DMA_DONE); diff --git a/techpack/display/msm/dsi/dsi_ctrl.h b/techpack/display/msm/dsi/dsi_ctrl.h index 944debaa28a4..a3290750520b 100644 --- a/techpack/display/msm/dsi/dsi_ctrl.h +++ b/techpack/display/msm/dsi/dsi_ctrl.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. */ @@ -310,8 +309,8 @@ struct dsi_ctrl { bool cmd_mode; u32 cmd_trigger_line; u32 cmd_trigger_frame; - atomic_t cmd_success_line; - atomic_t cmd_success_frame; + u32 cmd_success_line; + u32 cmd_success_frame; }; /** diff --git a/techpack/display/msm/dsi/dsi_display.c b/techpack/display/msm/dsi/dsi_display.c index 51c6376b6a17..506d24720a29 100644 --- a/techpack/display/msm/dsi/dsi_display.c +++ b/techpack/display/msm/dsi/dsi_display.c @@ -6488,25 +6488,15 @@ static int dsi_display_init(struct dsi_display *display) if (rc) { DSI_ERR("[%s] failed to enable vregs, rc=%d\n", display->panel->name, rc); - goto vreg_fail; + return rc; } } rc = component_add(&pdev->dev, &dsi_display_comp_ops); - if (rc) { + if (rc) DSI_ERR("component add failed, rc=%d\n", rc); - goto comp_add_fail; - } DSI_DEBUG("component add success: %s\n", display->name); - return rc; - -comp_add_fail: - if (display->panel) - dsi_pwr_enable_regulator(&display->panel->power_info, false); -vreg_fail: - _dsi_display_dev_deinit(display); - end: return rc; } @@ -7836,10 +7826,8 @@ exit: rc = 0; error: - if (rc) { + if (rc) kfree(display->modes); - display->modes = NULL; - } mutex_unlock(&display->display_lock); return rc; diff --git a/techpack/display/msm/msm_smmu.c b/techpack/display/msm/msm_smmu.c index af9ba0ba87f5..53f5f926560a 100644 --- a/techpack/display/msm/msm_smmu.c +++ b/techpack/display/msm/msm_smmu.c @@ -1,5 +1,4 @@ /* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark @@ -212,10 +211,6 @@ static void msm_smmu_destroy(struct msm_mmu *mmu) { struct msm_smmu *smmu = to_msm_smmu(mmu); struct platform_device *pdev = to_platform_device(smmu->client_dev); - struct iommu_domain *domain = iommu_get_domain_for_dev(smmu->client_dev); - - if (domain) - iommu_set_fault_handler(domain, NULL, NULL); if (smmu->client_dev) platform_device_unregister(pdev); diff --git a/techpack/display/msm/sde/sde_crtc.h b/techpack/display/msm/sde/sde_crtc.h index 3a9e4b68eb0b..75fb998ed06d 100644 --- a/techpack/display/msm/sde/sde_crtc.h +++ b/techpack/display/msm/sde/sde_crtc.h @@ -519,8 +519,7 @@ static inline int sde_crtc_get_mixer_width(struct sde_crtc *sde_crtc, if (cstate->num_ds_enabled) mixer_width = cstate->ds_cfg[0].lm_width; else - mixer_width = sde_crtc->num_mixers ? - mode->hdisplay / sde_crtc->num_mixers : mode->hdisplay; + mixer_width = mode->hdisplay / sde_crtc->num_mixers; return mixer_width; } diff --git a/techpack/display/msm/sde/sde_kms.c b/techpack/display/msm/sde/sde_kms.c index ab090babd5e7..63e33a7481d5 100644 --- a/techpack/display/msm/sde/sde_kms.c +++ b/techpack/display/msm/sde/sde_kms.c @@ -1,5 +1,5 @@ /* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark @@ -1264,6 +1264,16 @@ static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms, SDE_EVT32(DRMID(crtc), crtc->state->active, sde_kms->splash_data.num_splash_displays); + /*remove all votes if eDP displays are done with splash*/ + if (dp_display_get_num_of_boot_displays()) { + for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) + sde_power_data_bus_set_quota(phandle, i, + SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA, + phandle->ib_quota[i]); + pm_runtime_put_sync(sde_kms->dev->dev); + sde_kms->splash_data.num_splash_displays--; + } + for (i = 0; i < MAX_DSI_DISPLAYS; i++) { splash_display = &sde_kms->splash_data.splash_display[i]; if (splash_display->encoder && @@ -3395,7 +3405,7 @@ static int sde_kms_cont_splash_config(struct msm_kms *kms, struct msm_display_info info; struct drm_encoder *encoder = NULL; struct drm_crtc *crtc = NULL; - int i, rc = 0, splash_index = 0; + int i, rc = 0; struct drm_display_mode *drm_mode = NULL; struct drm_device *dev; struct msm_drm_private *priv; @@ -3433,7 +3443,7 @@ static int sde_kms_cont_splash_config(struct msm_kms *kms, DRM_INFO("cont_splash enabled in %d of %d display(s)\n", sde_kms->splash_data.num_splash_displays, - sde_kms->dsi_display_count + sde_kms->dp_display_count); + sde_kms->dsi_display_count); /* dsi */ for (i = 0; i < sde_kms->dsi_display_count; ++i) { @@ -3499,20 +3509,11 @@ static int sde_kms_cont_splash_config(struct msm_kms *kms, mutex_unlock(&dev->mode_config.mutex); return -EINVAL; } + mutex_unlock(&dev->mode_config.mutex); crtc->state->encoder_mask = (1 << drm_encoder_index(encoder)); - /* get supported modes in case of external bridge panels*/ - if (!dsi_display->panel->num_timing_nodes) { - connector->funcs->fill_modes(connector, - dev->mode_config.max_width, - dev->mode_config.max_height); - drm_mode = list_first_entry(&connector->modes, - struct drm_display_mode, head); - } - else - drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, state); - mutex_unlock(&dev->mode_config.mutex); + drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, state); if (!drm_mode) { SDE_ERROR("drm_mode not found; handoff_type:%d\n", sde_kms->splash_data.type); @@ -3569,19 +3570,6 @@ static int sde_kms_cont_splash_config(struct msm_kms *kms, break; } - splash_display = &sde_kms->splash_data.splash_display[splash_index]; - if (splash_display->cont_splash_enabled) { - priv = sde_kms->dev->dev_private; - encoder->crtc = priv->crtcs[splash_index]; - splash_display->encoder = encoder; - - SDE_DEBUG("dp-display:%d splash_index:%d crtc id[%d]:%d enc id[%d]:%d\n", - i, splash_index, encoder->crtc->index, encoder->crtc->base.id, - encoder->index, encoder->base.id); - - splash_index++; - } - mutex_lock(&dev->mode_config.mutex); drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { diff --git a/techpack/display/msm/sde/sde_rm.c b/techpack/display/msm/sde/sde_rm.c index 0922d7818db0..4367cf9d2055 100644 --- a/techpack/display/msm/sde/sde_rm.c +++ b/techpack/display/msm/sde/sde_rm.c @@ -987,7 +987,7 @@ static bool _sde_rm_check_lm_and_get_connected_blks( u32 conn_lm_mask) { const struct sde_lm_cfg *lm_cfg = to_sde_hw_mixer(lm->hw)->cap; - const struct sde_pingpong_cfg *pp_cfg = NULL; + const struct sde_pingpong_cfg *pp_cfg; bool ret, is_conn_primary, is_conn_secondary; u32 lm_primary_pref, lm_secondary_pref, cwb_pref; diff --git a/techpack/display/msm/sde/sde_wb.c b/techpack/display/msm/sde/sde_wb.c index d6648ad7e2fc..dcb308fabf84 100644 --- a/techpack/display/msm/sde/sde_wb.c +++ b/techpack/display/msm/sde/sde_wb.c @@ -204,8 +204,6 @@ int sde_wb_connector_set_modes(struct sde_wb_device *wb_dev, memset(&dispmode, 0, sizeof(dispmode)); ret = drm_mode_convert_umode(wb_dev->drm_dev, &dispmode, &modeinfo[i]); - /* null terminate the string */ - modeinfo[i].name[DRM_DISPLAY_MODE_LEN - 1] = '\0'; if (ret) { SDE_ERROR( "failed to convert mode %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x status:%d rc:%d\n", diff --git a/techpack/display/rotator/sde_rotator_r3.c b/techpack/display/rotator/sde_rotator_r3.c index f36c0ce6ce7c..b1e2f15a4b84 100644 --- a/techpack/display/rotator/sde_rotator_r3.c +++ b/techpack/display/rotator/sde_rotator_r3.c @@ -1419,14 +1419,14 @@ static void sde_hw_rotator_vbif_rt_setting(void) for (j = 0; j < MAX_XIN; j++) { reg_high = ((mdata->vbif_xin_id[j] & 0x8) >> 3) * 4 + (i * 8); - reg_shift = (mdata->vbif_xin_id[j] & 0x7) * 4; + reg_shift = mdata->vbif_xin_id[j] * 4; reg_val = SDE_VBIF_READ(mdata, MMSS_VBIF_NRT_VBIF_QOS_RP_REMAP_000 + reg_high); reg_val_lvl = SDE_VBIF_READ(mdata, MMSS_VBIF_NRT_VBIF_QOS_LVL_REMAP_000 + reg_high); - mask = 0x7 << reg_shift; + mask = 0x7 << (mdata->vbif_xin_id[j] * 4); vbif_qos = mdata->vbif_nrt_qos[i]; diff --git a/techpack/video/msm/vidc/msm_venc.c b/techpack/video/msm/vidc/msm_venc.c index f95639e02465..25a282e5aa4a 100644 --- a/techpack/video/msm/vidc/msm_venc.c +++ b/techpack/video/msm/vidc/msm_venc.c @@ -3710,9 +3710,6 @@ int msm_venc_enable_hybrid_hp(struct msm_vidc_inst *inst) if (ctrl->val) return 0; - if (msm_vidc_get_fps(inst) <= 60) - return 0; - ctrl = get_ctrl(inst, V4L2_CID_MPEG_VIDC_VIDEO_HEVC_MAX_HIER_CODING_LAYER); layer = get_ctrl(inst, V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER); diff --git a/techpack/video/msm/vidc/msm_vidc.c b/techpack/video/msm/vidc/msm_vidc.c index db0f6529abb8..d848eb08976b 100644 --- a/techpack/video/msm/vidc/msm_vidc.c +++ b/techpack/video/msm/vidc/msm_vidc.c @@ -1482,6 +1482,7 @@ static void close_helper(struct kref *kref) { struct msm_vidc_inst *inst = container_of(kref, struct msm_vidc_inst, kref); + msm_vidc_destroy(inst); } @@ -1496,19 +1497,19 @@ void *msm_vidc_open(int core_id, int session_type) session_type >= MSM_VIDC_MAX_DEVICES) { d_vpr_e("Invalid input, core_id = %d, session = %d\n", core_id, session_type); - return NULL; + goto err_invalid_core; } core = get_vidc_core(core_id); if (!core) { d_vpr_e("Failed to find core for core_id = %d\n", core_id); - return NULL; + goto err_invalid_core; } inst = kzalloc(sizeof(*inst), GFP_KERNEL); if (!inst) { d_vpr_e("Failed to allocate memory\n"); rc = -ENOMEM; - return NULL; + goto err_invalid_core; } mutex_lock(&core->lock); rc = get_sid(&inst->sid, session_type); @@ -1608,15 +1609,14 @@ void *msm_vidc_open(int core_id, int session_type) s_vpr_e(inst->sid, "Failed to move video instance to init state\n"); kref_put(&inst->kref, close_helper); - return NULL; + inst = NULL; + goto err_invalid_core; } if (msm_comm_check_for_inst_overload(core)) { s_vpr_e(inst->sid, "Instance count reached Max limit, rejecting session"); - msm_comm_kill_session(inst); - kref_put(&inst->kref, close_helper); - return NULL; + goto fail_init; } msm_comm_scale_clocks_and_bus(inst, 1); @@ -1625,6 +1625,14 @@ void *msm_vidc_open(int core_id, int session_type) msm_vidc_debugfs_init_inst(inst, core->debugfs_root); return inst; +fail_init: + mutex_lock(&core->lock); + list_del(&inst->list); + mutex_unlock(&core->lock); + + v4l2_fh_del(&inst->event_handler); + v4l2_fh_exit(&inst->event_handler); + vb2_queue_release(&inst->bufq[INPUT_PORT].vb2_bufq); fail_bufq_output: vb2_queue_release(&inst->bufq[OUTPUT_PORT].vb2_bufq); fail_bufq_capture: @@ -1652,6 +1660,7 @@ err_invalid_sid: put_sid(inst->sid); kfree(inst); inst = NULL; +err_invalid_core: return inst; } EXPORT_SYMBOL(msm_vidc_open); diff --git a/techpack/video/msm/vidc/msm_vidc_common.c b/techpack/video/msm/vidc/msm_vidc_common.c index de7670f265cb..f38687d5e943 100644 --- a/techpack/video/msm/vidc/msm_vidc_common.c +++ b/techpack/video/msm/vidc/msm_vidc_common.c @@ -2728,7 +2728,7 @@ exit: put_inst(inst); } -void handle_cmd_response(u32 cmd, void *data) +void handle_cmd_response(enum hal_command_response cmd, void *data) { switch (cmd) { case HAL_SYS_INIT_DONE: diff --git a/techpack/video/msm/vidc/msm_vidc_internal.h b/techpack/video/msm/vidc/msm_vidc_internal.h index a74630199b45..0f1614a613d3 100644 --- a/techpack/video/msm/vidc/msm_vidc_internal.h +++ b/techpack/video/msm/vidc/msm_vidc_internal.h @@ -623,7 +623,7 @@ struct msm_vidc_ctrl { const char * const *qmenu; }; -void handle_cmd_response(u32 cmd, void *data); +void handle_cmd_response(enum hal_command_response cmd, void *data); int msm_vidc_trigger_ssr(struct msm_vidc_core *core, u64 trigger_ssr_val); int msm_vidc_noc_error_info(struct msm_vidc_core *core); diff --git a/techpack/video/msm/vidc/vidc_hfi_api.h b/techpack/video/msm/vidc/vidc_hfi_api.h index 17b28bcb0b3a..069185c1b0d8 100644 --- a/techpack/video/msm/vidc/vidc_hfi_api.h +++ b/techpack/video/msm/vidc/vidc_hfi_api.h @@ -678,8 +678,10 @@ struct hfi_device { enum hal_default_properties (*get_default_properties)(void *dev); }; -typedef void (*hfi_cmd_response_callback) (u32 cmd, void *data); -typedef void (*msm_vidc_callback) (u32 response, void *callback); +typedef void (*hfi_cmd_response_callback) (enum hal_command_response cmd, + void *data); +typedef void (*msm_vidc_callback) (enum hal_command_response response, + void *callback); struct hfi_device *vidc_hfi_initialize(enum msm_vidc_hfi_type hfi_type, u32 device_id, struct msm_vidc_platform_resources *res, diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h index b4a1cbd06fcc..3731a7b0886d 100644 --- a/tools/include/uapi/linux/bpf.h +++ b/tools/include/uapi/linux/bpf.h @@ -886,7 +886,6 @@ union bpf_attr { * for updates resulting in a null checksum the value is set to * **CSUM_MANGLED_0** instead. Flag **BPF_F_PSEUDO_HDR** indicates * the checksum is to be computed against a pseudo-header. - * Flag **BPF_F_IPV6** should be set for IPv6 packets. * * This helper works in combination with **bpf_csum_diff**\ (), * which does not update the checksum in-place, but offers more @@ -3905,7 +3904,6 @@ enum { BPF_F_PSEUDO_HDR = (1ULL << 4), BPF_F_MARK_MANGLED_0 = (1ULL << 5), BPF_F_MARK_ENFORCE = (1ULL << 6), - BPF_F_IPV6 = (1ULL << 7), }; /* BPF_FUNC_clone_redirect and BPF_FUNC_redirect flags. */ diff --git a/tools/testing/selftests/Makefile b/tools/testing/selftests/Makefile index 7b4106268541..9514f6dbe46b 100644 --- a/tools/testing/selftests/Makefile +++ b/tools/testing/selftests/Makefile @@ -4,7 +4,6 @@ TARGETS += bpf TARGETS += breakpoints TARGETS += capabilities TARGETS += cgroup -TARGETS += clone3 TARGETS += cpufreq TARGETS += cpu-hotplug TARGETS += drivers/dma-buf diff --git a/tools/testing/selftests/clone3/.gitignore b/tools/testing/selftests/clone3/.gitignore deleted file mode 100644 index fb6d704eb61e..000000000000 --- a/tools/testing/selftests/clone3/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -clone3 -clone3_clear_sighand -clone3_set_tid -clone3_cap_checkpoint_restore diff --git a/tools/testing/selftests/clone3/Makefile b/tools/testing/selftests/clone3/Makefile deleted file mode 100644 index ef7564cb7abe..000000000000 --- a/tools/testing/selftests/clone3/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -CFLAGS += -g -I../../../../usr/include/ -LDLIBS += -lcap - -TEST_GEN_PROGS := clone3 clone3_clear_sighand clone3_set_tid \ - clone3_cap_checkpoint_restore - -include ../lib.mk diff --git a/tools/testing/selftests/clone3/clone3.c b/tools/testing/selftests/clone3/clone3.c deleted file mode 100644 index 4669b3d418e7..000000000000 --- a/tools/testing/selftests/clone3/clone3.c +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* Based on Christian Brauner's clone3() example */ - -#define _GNU_SOURCE -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../kselftest.h" -#include "clone3_selftests.h" - -/* - * Different sizes of struct clone_args - */ -#ifndef CLONE3_ARGS_SIZE_V0 -#define CLONE3_ARGS_SIZE_V0 64 -#endif - -enum test_mode { - CLONE3_ARGS_NO_TEST, - CLONE3_ARGS_ALL_0, - CLONE3_ARGS_INVAL_EXIT_SIGNAL_BIG, - CLONE3_ARGS_INVAL_EXIT_SIGNAL_NEG, - CLONE3_ARGS_INVAL_EXIT_SIGNAL_CSIG, - CLONE3_ARGS_INVAL_EXIT_SIGNAL_NSIG, -}; - -static int call_clone3(uint64_t flags, size_t size, enum test_mode test_mode) -{ - struct clone_args args = { - .flags = flags, - .exit_signal = SIGCHLD, - }; - - struct clone_args_extended { - struct clone_args args; - __aligned_u64 excess_space[2]; - } args_ext; - - pid_t pid = -1; - int status; - - memset(&args_ext, 0, sizeof(args_ext)); - if (size > sizeof(struct clone_args)) - args_ext.excess_space[1] = 1; - - if (size == 0) - size = sizeof(struct clone_args); - - switch (test_mode) { - case CLONE3_ARGS_ALL_0: - args.flags = 0; - args.exit_signal = 0; - break; - case CLONE3_ARGS_INVAL_EXIT_SIGNAL_BIG: - args.exit_signal = 0xbadc0ded00000000ULL; - break; - case CLONE3_ARGS_INVAL_EXIT_SIGNAL_NEG: - args.exit_signal = 0x0000000080000000ULL; - break; - case CLONE3_ARGS_INVAL_EXIT_SIGNAL_CSIG: - args.exit_signal = 0x0000000000000100ULL; - break; - case CLONE3_ARGS_INVAL_EXIT_SIGNAL_NSIG: - args.exit_signal = 0x00000000000000f0ULL; - break; - } - - memcpy(&args_ext.args, &args, sizeof(struct clone_args)); - - pid = sys_clone3((struct clone_args *)&args_ext, size); - if (pid < 0) { - ksft_print_msg("%s - Failed to create new process\n", - strerror(errno)); - return -errno; - } - - if (pid == 0) { - ksft_print_msg("I am the child, my PID is %d\n", getpid()); - _exit(EXIT_SUCCESS); - } - - ksft_print_msg("I am the parent (%d). My child's pid is %d\n", - getpid(), pid); - - if (waitpid(-1, &status, __WALL) < 0) { - ksft_print_msg("Child returned %s\n", strerror(errno)); - return -errno; - } - if (WEXITSTATUS(status)) - return WEXITSTATUS(status); - - return 0; -} - -static void test_clone3(uint64_t flags, size_t size, int expected, - enum test_mode test_mode) -{ - int ret; - - ksft_print_msg( - "[%d] Trying clone3() with flags %#" PRIx64 " (size %zu)\n", - getpid(), flags, size); - ret = call_clone3(flags, size, test_mode); - ksft_print_msg("[%d] clone3() with flags says: %d expected %d\n", - getpid(), ret, expected); - if (ret != expected) - ksft_test_result_fail( - "[%d] Result (%d) is different than expected (%d)\n", - getpid(), ret, expected); - else - ksft_test_result_pass( - "[%d] Result (%d) matches expectation (%d)\n", - getpid(), ret, expected); -} - -int main(int argc, char *argv[]) -{ - pid_t pid; - - uid_t uid = getuid(); - - ksft_print_header(); - ksft_set_plan(17); - - /* Just a simple clone3() should return 0.*/ - test_clone3(0, 0, 0, CLONE3_ARGS_NO_TEST); - - /* Do a clone3() in a new PID NS.*/ - if (uid == 0) - test_clone3(CLONE_NEWPID, 0, 0, CLONE3_ARGS_NO_TEST); - else - ksft_test_result_skip("Skipping clone3() with CLONE_NEWPID\n"); - - /* Do a clone3() with CLONE3_ARGS_SIZE_V0. */ - test_clone3(0, CLONE3_ARGS_SIZE_V0, 0, CLONE3_ARGS_NO_TEST); - - /* Do a clone3() with CLONE3_ARGS_SIZE_V0 - 8 */ - test_clone3(0, CLONE3_ARGS_SIZE_V0 - 8, -EINVAL, CLONE3_ARGS_NO_TEST); - - /* Do a clone3() with sizeof(struct clone_args) + 8 */ - test_clone3(0, sizeof(struct clone_args) + 8, 0, CLONE3_ARGS_NO_TEST); - - /* Do a clone3() with exit_signal having highest 32 bits non-zero */ - test_clone3(0, 0, -EINVAL, CLONE3_ARGS_INVAL_EXIT_SIGNAL_BIG); - - /* Do a clone3() with negative 32-bit exit_signal */ - test_clone3(0, 0, -EINVAL, CLONE3_ARGS_INVAL_EXIT_SIGNAL_NEG); - - /* Do a clone3() with exit_signal not fitting into CSIGNAL mask */ - test_clone3(0, 0, -EINVAL, CLONE3_ARGS_INVAL_EXIT_SIGNAL_CSIG); - - /* Do a clone3() with NSIG < exit_signal < CSIG */ - test_clone3(0, 0, -EINVAL, CLONE3_ARGS_INVAL_EXIT_SIGNAL_NSIG); - - test_clone3(0, sizeof(struct clone_args) + 8, 0, CLONE3_ARGS_ALL_0); - - test_clone3(0, sizeof(struct clone_args) + 16, -E2BIG, - CLONE3_ARGS_ALL_0); - - test_clone3(0, sizeof(struct clone_args) * 2, -E2BIG, - CLONE3_ARGS_ALL_0); - - /* Do a clone3() with > page size */ - test_clone3(0, getpagesize() + 8, -E2BIG, CLONE3_ARGS_NO_TEST); - - /* Do a clone3() with CLONE3_ARGS_SIZE_V0 in a new PID NS. */ - if (uid == 0) - test_clone3(CLONE_NEWPID, CLONE3_ARGS_SIZE_V0, 0, - CLONE3_ARGS_NO_TEST); - else - ksft_test_result_skip("Skipping clone3() with CLONE_NEWPID\n"); - - /* Do a clone3() with CLONE3_ARGS_SIZE_V0 - 8 in a new PID NS */ - test_clone3(CLONE_NEWPID, CLONE3_ARGS_SIZE_V0 - 8, -EINVAL, - CLONE3_ARGS_NO_TEST); - - /* Do a clone3() with sizeof(struct clone_args) + 8 in a new PID NS */ - if (uid == 0) - test_clone3(CLONE_NEWPID, sizeof(struct clone_args) + 8, 0, - CLONE3_ARGS_NO_TEST); - else - ksft_test_result_skip("Skipping clone3() with CLONE_NEWPID\n"); - - /* Do a clone3() with > page size in a new PID NS */ - test_clone3(CLONE_NEWPID, getpagesize() + 8, -E2BIG, - CLONE3_ARGS_NO_TEST); - - return !ksft_get_fail_cnt() ? ksft_exit_pass() : ksft_exit_fail(); -} diff --git a/tools/testing/selftests/clone3/clone3_cap_checkpoint_restore.c b/tools/testing/selftests/clone3/clone3_cap_checkpoint_restore.c deleted file mode 100644 index 9562425aa0a9..000000000000 --- a/tools/testing/selftests/clone3/clone3_cap_checkpoint_restore.c +++ /dev/null @@ -1,182 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * Based on Christian Brauner's clone3() example. - * These tests are assuming to be running in the host's - * PID namespace. - */ - -/* capabilities related code based on selftests/bpf/test_verifier.c */ - -#define _GNU_SOURCE -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../kselftest_harness.h" -#include "clone3_selftests.h" - -#ifndef MAX_PID_NS_LEVEL -#define MAX_PID_NS_LEVEL 32 -#endif - -static void child_exit(int ret) -{ - fflush(stdout); - fflush(stderr); - _exit(ret); -} - -static int call_clone3_set_tid(struct __test_metadata *_metadata, - pid_t *set_tid, size_t set_tid_size) -{ - int status; - pid_t pid = -1; - - struct clone_args args = { - .exit_signal = SIGCHLD, - .set_tid = ptr_to_u64(set_tid), - .set_tid_size = set_tid_size, - }; - - pid = sys_clone3(&args, sizeof(struct clone_args)); - if (pid < 0) { - TH_LOG("%s - Failed to create new process", strerror(errno)); - return -errno; - } - - if (pid == 0) { - int ret; - char tmp = 0; - - TH_LOG("I am the child, my PID is %d (expected %d)", getpid(), set_tid[0]); - - if (set_tid[0] != getpid()) - child_exit(EXIT_FAILURE); - child_exit(EXIT_SUCCESS); - } - - TH_LOG("I am the parent (%d). My child's pid is %d", getpid(), pid); - - if (waitpid(pid, &status, 0) < 0) { - TH_LOG("Child returned %s", strerror(errno)); - return -errno; - } - - if (!WIFEXITED(status)) - return -1; - - return WEXITSTATUS(status); -} - -static int test_clone3_set_tid(struct __test_metadata *_metadata, - pid_t *set_tid, size_t set_tid_size) -{ - int ret; - - TH_LOG("[%d] Trying clone3() with CLONE_SET_TID to %d", getpid(), set_tid[0]); - ret = call_clone3_set_tid(_metadata, set_tid, set_tid_size); - TH_LOG("[%d] clone3() with CLONE_SET_TID %d says:%d", getpid(), set_tid[0], ret); - return ret; -} - -struct libcap { - struct __user_cap_header_struct hdr; - struct __user_cap_data_struct data[2]; -}; - -static int set_capability(void) -{ - cap_value_t cap_values[] = { CAP_SETUID, CAP_SETGID }; - struct libcap *cap; - int ret = -1; - cap_t caps; - - caps = cap_get_proc(); - if (!caps) { - perror("cap_get_proc"); - return -1; - } - - /* Drop all capabilities */ - if (cap_clear(caps)) { - perror("cap_clear"); - goto out; - } - - cap_set_flag(caps, CAP_EFFECTIVE, 2, cap_values, CAP_SET); - cap_set_flag(caps, CAP_PERMITTED, 2, cap_values, CAP_SET); - - cap = (struct libcap *) caps; - - /* 40 -> CAP_CHECKPOINT_RESTORE */ - cap->data[1].effective |= 1 << (40 - 32); - cap->data[1].permitted |= 1 << (40 - 32); - - if (cap_set_proc(caps)) { - perror("cap_set_proc"); - goto out; - } - ret = 0; -out: - if (cap_free(caps)) - perror("cap_free"); - return ret; -} - -TEST(clone3_cap_checkpoint_restore) -{ - pid_t pid; - int status; - int ret = 0; - pid_t set_tid[1]; - - test_clone3_supported(); - - EXPECT_EQ(getuid(), 0) - XFAIL(return, "Skipping all tests as non-root\n"); - - memset(&set_tid, 0, sizeof(set_tid)); - - /* Find the current active PID */ - pid = fork(); - if (pid == 0) { - TH_LOG("Child has PID %d", getpid()); - child_exit(EXIT_SUCCESS); - } - ASSERT_GT(waitpid(pid, &status, 0), 0) - TH_LOG("Waiting for child %d failed", pid); - - /* After the child has finished, its PID should be free. */ - set_tid[0] = pid; - - ASSERT_EQ(set_capability(), 0) - TH_LOG("Could not set CAP_CHECKPOINT_RESTORE"); - - ASSERT_EQ(prctl(PR_SET_KEEPCAPS, 1, 0, 0, 0), 0); - - EXPECT_EQ(setgid(65534), 0) - TH_LOG("Failed to setgid(65534)"); - ASSERT_EQ(setuid(65534), 0); - - set_tid[0] = pid; - /* This would fail without CAP_CHECKPOINT_RESTORE */ - ASSERT_EQ(test_clone3_set_tid(_metadata, set_tid, 1), -EPERM); - ASSERT_EQ(set_capability(), 0) - TH_LOG("Could not set CAP_CHECKPOINT_RESTORE"); - /* This should work as we have CAP_CHECKPOINT_RESTORE as non-root */ - ASSERT_EQ(test_clone3_set_tid(_metadata, set_tid, 1), 0); -} - -TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/clone3/clone3_clear_sighand.c b/tools/testing/selftests/clone3/clone3_clear_sighand.c deleted file mode 100644 index 456783ad19d6..000000000000 --- a/tools/testing/selftests/clone3/clone3_clear_sighand.c +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#define _GNU_SOURCE -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../kselftest.h" -#include "clone3_selftests.h" - -#ifndef CLONE_CLEAR_SIGHAND -#define CLONE_CLEAR_SIGHAND 0x100000000ULL -#endif - -static void test_clone3_supported(void) -{ - pid_t pid; - struct clone_args args = {}; - - if (__NR_clone3 < 0) - ksft_exit_skip("clone3() syscall is not supported\n"); - - /* Set to something that will always cause EINVAL. */ - args.exit_signal = -1; - pid = sys_clone3(&args, sizeof(args)); - if (!pid) - exit(EXIT_SUCCESS); - - if (pid > 0) { - wait(NULL); - ksft_exit_fail_msg( - "Managed to create child process with invalid exit_signal\n"); - } - - if (errno == ENOSYS) - ksft_exit_skip("clone3() syscall is not supported\n"); - - ksft_print_msg("clone3() syscall supported\n"); -} - -static void nop_handler(int signo) -{ -} - -static int wait_for_pid(pid_t pid) -{ - int status, ret; - -again: - ret = waitpid(pid, &status, 0); - if (ret == -1) { - if (errno == EINTR) - goto again; - - return -1; - } - - if (!WIFEXITED(status)) - return -1; - - return WEXITSTATUS(status); -} - -static void test_clone3_clear_sighand(void) -{ - int ret; - pid_t pid; - struct clone_args args = {}; - struct sigaction act; - - /* - * Check that CLONE_CLEAR_SIGHAND and CLONE_SIGHAND are mutually - * exclusive. - */ - args.flags |= CLONE_CLEAR_SIGHAND | CLONE_SIGHAND; - args.exit_signal = SIGCHLD; - pid = sys_clone3(&args, sizeof(args)); - if (pid > 0) - ksft_exit_fail_msg( - "clone3(CLONE_CLEAR_SIGHAND | CLONE_SIGHAND) succeeded\n"); - - act.sa_handler = nop_handler; - ret = sigemptyset(&act.sa_mask); - if (ret < 0) - ksft_exit_fail_msg("%s - sigemptyset() failed\n", - strerror(errno)); - - act.sa_flags = 0; - - /* Register signal handler for SIGUSR1 */ - ret = sigaction(SIGUSR1, &act, NULL); - if (ret < 0) - ksft_exit_fail_msg( - "%s - sigaction(SIGUSR1, &act, NULL) failed\n", - strerror(errno)); - - /* Register signal handler for SIGUSR2 */ - ret = sigaction(SIGUSR2, &act, NULL); - if (ret < 0) - ksft_exit_fail_msg( - "%s - sigaction(SIGUSR2, &act, NULL) failed\n", - strerror(errno)); - - /* Check that CLONE_CLEAR_SIGHAND works. */ - args.flags = CLONE_CLEAR_SIGHAND; - pid = sys_clone3(&args, sizeof(args)); - if (pid < 0) - ksft_exit_fail_msg("%s - clone3(CLONE_CLEAR_SIGHAND) failed\n", - strerror(errno)); - - if (pid == 0) { - ret = sigaction(SIGUSR1, NULL, &act); - if (ret < 0) - exit(EXIT_FAILURE); - - if (act.sa_handler != SIG_DFL) - exit(EXIT_FAILURE); - - ret = sigaction(SIGUSR2, NULL, &act); - if (ret < 0) - exit(EXIT_FAILURE); - - if (act.sa_handler != SIG_DFL) - exit(EXIT_FAILURE); - - exit(EXIT_SUCCESS); - } - - ret = wait_for_pid(pid); - if (ret) - ksft_exit_fail_msg( - "Failed to clear signal handler for child process\n"); - - ksft_test_result_pass("Cleared signal handlers for child process\n"); -} - -int main(int argc, char **argv) -{ - ksft_print_header(); - ksft_set_plan(1); - - test_clone3_supported(); - test_clone3_clear_sighand(); - - return ksft_exit_pass(); -} diff --git a/tools/testing/selftests/clone3/clone3_selftests.h b/tools/testing/selftests/clone3/clone3_selftests.h deleted file mode 100644 index 1a270390766a..000000000000 --- a/tools/testing/selftests/clone3/clone3_selftests.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _CLONE3_SELFTESTS_H -#define _CLONE3_SELFTESTS_H - -#define _GNU_SOURCE -#include -#include -#include -#include - -#define ptr_to_u64(ptr) ((__u64)((uintptr_t)(ptr))) - -#ifndef __NR_clone3 -#define __NR_clone3 -1 -struct clone_args { - __aligned_u64 flags; - __aligned_u64 pidfd; - __aligned_u64 child_tid; - __aligned_u64 parent_tid; - __aligned_u64 exit_signal; - __aligned_u64 stack; - __aligned_u64 stack_size; - __aligned_u64 tls; - __aligned_u64 set_tid; - __aligned_u64 set_tid_size; -}; -#endif - -static pid_t sys_clone3(struct clone_args *args, size_t size) -{ - return syscall(__NR_clone3, args, size); -} - -#endif /* _CLONE3_SELFTESTS_H */ diff --git a/tools/testing/selftests/clone3/clone3_set_tid.c b/tools/testing/selftests/clone3/clone3_set_tid.c deleted file mode 100644 index 3480e1c46983..000000000000 --- a/tools/testing/selftests/clone3/clone3_set_tid.c +++ /dev/null @@ -1,381 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * Based on Christian Brauner's clone3() example. - * These tests are assuming to be running in the host's - * PID namespace. - */ - -#define _GNU_SOURCE -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../kselftest.h" -#include "clone3_selftests.h" - -#ifndef MAX_PID_NS_LEVEL -#define MAX_PID_NS_LEVEL 32 -#endif - -static int pipe_1[2]; -static int pipe_2[2]; - -static int call_clone3_set_tid(pid_t *set_tid, - size_t set_tid_size, - int flags, - int expected_pid, - bool wait_for_it) -{ - int status; - pid_t pid = -1; - - struct clone_args args = { - .flags = flags, - .exit_signal = SIGCHLD, - .set_tid = ptr_to_u64(set_tid), - .set_tid_size = set_tid_size, - }; - - pid = sys_clone3(&args, sizeof(struct clone_args)); - if (pid < 0) { - ksft_print_msg("%s - Failed to create new process\n", - strerror(errno)); - return -errno; - } - - if (pid == 0) { - int ret; - char tmp = 0; - int exit_code = EXIT_SUCCESS; - - ksft_print_msg("I am the child, my PID is %d (expected %d)\n", - getpid(), set_tid[0]); - if (wait_for_it) { - ksft_print_msg("[%d] Child is ready and waiting\n", - getpid()); - - /* Signal the parent that the child is ready */ - close(pipe_1[0]); - ret = write(pipe_1[1], &tmp, 1); - if (ret != 1) { - ksft_print_msg( - "Writing to pipe returned %d", ret); - exit_code = EXIT_FAILURE; - } - close(pipe_1[1]); - close(pipe_2[1]); - ret = read(pipe_2[0], &tmp, 1); - if (ret != 1) { - ksft_print_msg( - "Reading from pipe returned %d", ret); - exit_code = EXIT_FAILURE; - } - close(pipe_2[0]); - } - - if (set_tid[0] != getpid()) - _exit(EXIT_FAILURE); - _exit(exit_code); - } - - if (expected_pid == 0 || expected_pid == pid) { - ksft_print_msg("I am the parent (%d). My child's pid is %d\n", - getpid(), pid); - } else { - ksft_print_msg( - "Expected child pid %d does not match actual pid %d\n", - expected_pid, pid); - return -1; - } - - if (waitpid(pid, &status, 0) < 0) { - ksft_print_msg("Child returned %s\n", strerror(errno)); - return -errno; - } - - if (!WIFEXITED(status)) - return -1; - - return WEXITSTATUS(status); -} - -static void test_clone3_set_tid(pid_t *set_tid, - size_t set_tid_size, - int flags, - int expected, - int expected_pid, - bool wait_for_it) -{ - int ret; - - ksft_print_msg( - "[%d] Trying clone3() with CLONE_SET_TID to %d and 0x%x\n", - getpid(), set_tid[0], flags); - ret = call_clone3_set_tid(set_tid, set_tid_size, flags, expected_pid, - wait_for_it); - ksft_print_msg( - "[%d] clone3() with CLONE_SET_TID %d says :%d - expected %d\n", - getpid(), set_tid[0], ret, expected); - if (ret != expected) - ksft_test_result_fail( - "[%d] Result (%d) is different than expected (%d)\n", - getpid(), ret, expected); - else - ksft_test_result_pass( - "[%d] Result (%d) matches expectation (%d)\n", - getpid(), ret, expected); -} -int main(int argc, char *argv[]) -{ - FILE *f; - char buf; - char *line; - int status; - int ret = -1; - size_t len = 0; - int pid_max = 0; - uid_t uid = getuid(); - char proc_path[100] = {0}; - pid_t pid, ns1, ns2, ns3, ns_pid; - pid_t set_tid[MAX_PID_NS_LEVEL * 2]; - - if (pipe(pipe_1) < 0 || pipe(pipe_2) < 0) - ksft_exit_fail_msg("pipe() failed\n"); - - ksft_print_header(); - ksft_set_plan(27); - - f = fopen("/proc/sys/kernel/pid_max", "r"); - if (f == NULL) - ksft_exit_fail_msg( - "%s - Could not open /proc/sys/kernel/pid_max\n", - strerror(errno)); - fscanf(f, "%d", &pid_max); - fclose(f); - ksft_print_msg("/proc/sys/kernel/pid_max %d\n", pid_max); - - /* Try invalid settings */ - memset(&set_tid, 0, sizeof(set_tid)); - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL + 1, 0, -EINVAL, 0, 0); - - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL * 2, 0, -EINVAL, 0, 0); - - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL * 2 + 1, 0, - -EINVAL, 0, 0); - - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL * 42, 0, -EINVAL, 0, 0); - - /* - * This can actually work if this test running in a MAX_PID_NS_LEVEL - 1 - * nested PID namespace. - */ - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL - 1, 0, -EINVAL, 0, 0); - - memset(&set_tid, 0xff, sizeof(set_tid)); - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL + 1, 0, -EINVAL, 0, 0); - - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL * 2, 0, -EINVAL, 0, 0); - - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL * 2 + 1, 0, - -EINVAL, 0, 0); - - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL * 42, 0, -EINVAL, 0, 0); - - /* - * This can actually work if this test running in a MAX_PID_NS_LEVEL - 1 - * nested PID namespace. - */ - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL - 1, 0, -EINVAL, 0, 0); - - memset(&set_tid, 0, sizeof(set_tid)); - /* Try with an invalid PID */ - set_tid[0] = 0; - test_clone3_set_tid(set_tid, 1, 0, -EINVAL, 0, 0); - - set_tid[0] = -1; - test_clone3_set_tid(set_tid, 1, 0, -EINVAL, 0, 0); - - /* Claim that the set_tid array actually contains 2 elements. */ - test_clone3_set_tid(set_tid, 2, 0, -EINVAL, 0, 0); - - /* Try it in a new PID namespace */ - if (uid == 0) - test_clone3_set_tid(set_tid, 1, CLONE_NEWPID, -EINVAL, 0, 0); - else - ksft_test_result_skip("Clone3() with set_tid requires root\n"); - - /* Try with a valid PID (1) this should return -EEXIST. */ - set_tid[0] = 1; - if (uid == 0) - test_clone3_set_tid(set_tid, 1, 0, -EEXIST, 0, 0); - else - ksft_test_result_skip("Clone3() with set_tid requires root\n"); - - /* Try it in a new PID namespace */ - if (uid == 0) - test_clone3_set_tid(set_tid, 1, CLONE_NEWPID, 0, 0, 0); - else - ksft_test_result_skip("Clone3() with set_tid requires root\n"); - - /* pid_max should fail everywhere */ - set_tid[0] = pid_max; - test_clone3_set_tid(set_tid, 1, 0, -EINVAL, 0, 0); - - if (uid == 0) - test_clone3_set_tid(set_tid, 1, CLONE_NEWPID, -EINVAL, 0, 0); - else - ksft_test_result_skip("Clone3() with set_tid requires root\n"); - - if (uid != 0) { - /* - * All remaining tests require root. Tell the framework - * that all those tests are skipped as non-root. - */ - ksft_cnt.ksft_xskip += ksft_plan - ksft_test_num(); - goto out; - } - - /* Find the current active PID */ - pid = fork(); - if (pid == 0) { - ksft_print_msg("Child has PID %d\n", getpid()); - _exit(EXIT_SUCCESS); - } - if (waitpid(pid, &status, 0) < 0) - ksft_exit_fail_msg("Waiting for child %d failed", pid); - - /* After the child has finished, its PID should be free. */ - set_tid[0] = pid; - test_clone3_set_tid(set_tid, 1, 0, 0, 0, 0); - - /* This should fail as there is no PID 1 in that namespace */ - test_clone3_set_tid(set_tid, 1, CLONE_NEWPID, -EINVAL, 0, 0); - - /* - * Creating a process with PID 1 in the newly created most nested - * PID namespace and PID 'pid' in the parent PID namespace. This - * needs to work. - */ - set_tid[0] = 1; - set_tid[1] = pid; - test_clone3_set_tid(set_tid, 2, CLONE_NEWPID, 0, pid, 0); - - ksft_print_msg("unshare PID namespace\n"); - if (unshare(CLONE_NEWPID) == -1) - ksft_exit_fail_msg("unshare(CLONE_NEWPID) failed: %s\n", - strerror(errno)); - - set_tid[0] = pid; - - /* This should fail as there is no PID 1 in that namespace */ - test_clone3_set_tid(set_tid, 1, 0, -EINVAL, 0, 0); - - /* Let's create a PID 1 */ - ns_pid = fork(); - if (ns_pid == 0) { - ksft_print_msg("Child in PID namespace has PID %d\n", getpid()); - set_tid[0] = 2; - test_clone3_set_tid(set_tid, 1, 0, 0, 2, 0); - - set_tid[0] = 1; - set_tid[1] = -1; - set_tid[2] = pid; - /* This should fail as there is invalid PID at level '1'. */ - test_clone3_set_tid(set_tid, 3, CLONE_NEWPID, -EINVAL, 0, 0); - - set_tid[0] = 1; - set_tid[1] = 42; - set_tid[2] = pid; - /* - * This should fail as there are not enough active PID - * namespaces. Again assuming this is running in the host's - * PID namespace. Not yet nested. - */ - test_clone3_set_tid(set_tid, 4, CLONE_NEWPID, -EINVAL, 0, 0); - - /* - * This should work and from the parent we should see - * something like 'NSpid: pid 42 1'. - */ - test_clone3_set_tid(set_tid, 3, CLONE_NEWPID, 0, 42, true); - - _exit(ksft_cnt.ksft_pass); - } - - close(pipe_1[1]); - close(pipe_2[0]); - while (read(pipe_1[0], &buf, 1) > 0) { - ksft_print_msg("[%d] Child is ready and waiting\n", getpid()); - break; - } - - snprintf(proc_path, sizeof(proc_path), "/proc/%d/status", pid); - f = fopen(proc_path, "r"); - if (f == NULL) - ksft_exit_fail_msg( - "%s - Could not open %s\n", - strerror(errno), proc_path); - - while (getline(&line, &len, f) != -1) { - if (strstr(line, "NSpid")) { - int i; - - /* Verify that all generated PIDs are as expected. */ - i = sscanf(line, "NSpid:\t%d\t%d\t%d", - &ns3, &ns2, &ns1); - if (i != 3) { - ksft_print_msg( - "Unexpected 'NSPid:' entry: %s", - line); - ns1 = ns2 = ns3 = 0; - } - break; - } - } - fclose(f); - free(line); - close(pipe_2[0]); - - /* Tell the clone3()'d child to finish. */ - write(pipe_2[1], &buf, 1); - close(pipe_2[1]); - - if (waitpid(ns_pid, &status, 0) < 0) { - ksft_print_msg("Child returned %s\n", strerror(errno)); - ret = -errno; - goto out; - } - - if (!WIFEXITED(status)) - ksft_test_result_fail("Child error\n"); - - if (WEXITSTATUS(status)) - /* - * Update the number of total tests with the tests from the - * child processes. - */ - ksft_cnt.ksft_pass = WEXITSTATUS(status); - - if (ns3 == pid && ns2 == 42 && ns1 == 1) - ksft_test_result_pass( - "PIDs in all namespaces as expected (%d,%d,%d)\n", - ns3, ns2, ns1); - else - ksft_test_result_fail( - "PIDs in all namespaces not as expected (%d,%d,%d)\n", - ns3, ns2, ns1); -out: - ret = 0; - - return !ret ? ksft_exit_pass() : ksft_exit_fail(); -} diff --git a/tools/testing/selftests/kselftest_module.h b/tools/testing/selftests/kselftest_module.h index e2ea41de3f35..e8eafaf0941a 100644 --- a/tools/testing/selftests/kselftest_module.h +++ b/tools/testing/selftests/kselftest_module.h @@ -11,8 +11,7 @@ #define KSTM_MODULE_GLOBALS() \ static unsigned int total_tests __initdata; \ -static unsigned int failed_tests __initdata; \ -static unsigned int skipped_tests __initdata +static unsigned int failed_tests __initdata #define KSTM_CHECK_ZERO(x) do { \ total_tests++; \ @@ -22,16 +21,11 @@ static unsigned int skipped_tests __initdata } \ } while (0) -static inline int kstm_report(unsigned int total_tests, unsigned int failed_tests, - unsigned int skipped_tests) +static inline int kstm_report(unsigned int total_tests, unsigned int failed_tests) { - if (failed_tests == 0) { - if (skipped_tests) { - pr_info("skipped %u tests\n", skipped_tests); - pr_info("remaining %u tests passed\n", total_tests); - } else - pr_info("all %u tests passed\n", total_tests); - } else + if (failed_tests == 0) + pr_info("all %u tests passed\n", total_tests); + else pr_warn("failed %u out of %u tests\n", failed_tests, total_tests); return failed_tests ? -EINVAL : 0; @@ -42,7 +36,7 @@ static int __init __module##_init(void) \ { \ pr_info("loaded.\n"); \ selftest(); \ - return kstm_report(total_tests, failed_tests, skipped_tests); \ + return kstm_report(total_tests, failed_tests); \ } \ static void __exit __module##_exit(void) \ { \ diff --git a/tools/testing/selftests/seccomp/seccomp_benchmark.c b/tools/testing/selftests/seccomp/seccomp_benchmark.c index fcc806585266..5838c8697ec3 100644 --- a/tools/testing/selftests/seccomp/seccomp_benchmark.c +++ b/tools/testing/selftests/seccomp/seccomp_benchmark.c @@ -4,16 +4,12 @@ */ #define _GNU_SOURCE #include -#include -#include -#include #include #include #include #include #include #include -#include #include #include #include @@ -22,9 +18,9 @@ unsigned long long timing(clockid_t clk_id, unsigned long long samples) { - struct timespec start, finish; - unsigned long long i; pid_t pid, ret; + unsigned long long i; + struct timespec start, finish; pid = getpid(); assert(clock_gettime(clk_id, &start) == 0); @@ -35,208 +31,69 @@ unsigned long long timing(clockid_t clk_id, unsigned long long samples) assert(clock_gettime(clk_id, &finish) == 0); i = finish.tv_sec - start.tv_sec; - i *= 1000000000ULL; + i *= 1000000000; i += finish.tv_nsec - start.tv_nsec; - printf("%lu.%09lu - %lu.%09lu = %llu (%.1fs)\n", + printf("%lu.%09lu - %lu.%09lu = %llu\n", finish.tv_sec, finish.tv_nsec, start.tv_sec, start.tv_nsec, - i, (double)i / 1000000000.0); + i); return i; } unsigned long long calibrate(void) { - struct timespec start, finish; - unsigned long long i, samples, step = 9973; - pid_t pid, ret; - int seconds = 15; + unsigned long long i; - printf("Calibrating sample size for %d seconds worth of syscalls ...\n", seconds); + printf("Calibrating reasonable sample size...\n"); - samples = 0; - pid = getpid(); - assert(clock_gettime(CLOCK_MONOTONIC, &start) == 0); - do { - for (i = 0; i < step; i++) { - ret = syscall(__NR_getpid); - assert(pid == ret); - } - assert(clock_gettime(CLOCK_MONOTONIC, &finish) == 0); + for (i = 5; ; i++) { + unsigned long long samples = 1 << i; - samples += step; - i = finish.tv_sec - start.tv_sec; - i *= 1000000000ULL; - i += finish.tv_nsec - start.tv_nsec; - } while (i < 1000000000ULL); - - return samples * seconds; -} - -bool approx(int i_one, int i_two) -{ - double one = i_one, one_bump = one * 0.01; - double two = i_two, two_bump = two * 0.01; - - one_bump = one + MAX(one_bump, 2.0); - two_bump = two + MAX(two_bump, 2.0); - - /* Equal to, or within 1% or 2 digits */ - if (one == two || - (one > two && one <= two_bump) || - (two > one && two <= one_bump)) - return true; - return false; -} - -bool le(int i_one, int i_two) -{ - if (i_one <= i_two) - return true; - return false; -} - -long compare(const char *name_one, const char *name_eval, const char *name_two, - unsigned long long one, bool (*eval)(int, int), unsigned long long two) -{ - bool good; - - printf("\t%s %s %s (%lld %s %lld): ", name_one, name_eval, name_two, - (long long)one, name_eval, (long long)two); - if (one > INT_MAX) { - printf("Miscalculation! Measurement went negative: %lld\n", (long long)one); - return 1; + /* Find something that takes more than 5 seconds to run. */ + if (timing(CLOCK_REALTIME, samples) / 1000000000ULL > 5) + return samples; } - if (two > INT_MAX) { - printf("Miscalculation! Measurement went negative: %lld\n", (long long)two); - return 1; - } - - good = eval(one, two); - printf("%s\n", good ? "✔️" : "❌"); - - return good ? 0 : 1; } int main(int argc, char *argv[]) { - struct sock_filter bitmap_filter[] = { - BPF_STMT(BPF_LD|BPF_W|BPF_ABS, offsetof(struct seccomp_data, nr)), - BPF_STMT(BPF_RET|BPF_K, SECCOMP_RET_ALLOW), - }; - struct sock_fprog bitmap_prog = { - .len = (unsigned short)ARRAY_SIZE(bitmap_filter), - .filter = bitmap_filter, - }; struct sock_filter filter[] = { - BPF_STMT(BPF_LD|BPF_W|BPF_ABS, offsetof(struct seccomp_data, args[0])), BPF_STMT(BPF_RET|BPF_K, SECCOMP_RET_ALLOW), }; struct sock_fprog prog = { .len = (unsigned short)ARRAY_SIZE(filter), .filter = filter, }; - - long ret, bits; - unsigned long long samples, calc; - unsigned long long native, filter1, filter2, bitmap1, bitmap2; - unsigned long long entry, per_filter1, per_filter2; - - printf("Current BPF sysctl settings:\n"); - system("sysctl net.core.bpf_jit_enable"); - system("sysctl net.core.bpf_jit_harden"); + long ret; + unsigned long long samples; + unsigned long long native, filtered; if (argc > 1) samples = strtoull(argv[1], NULL, 0); else samples = calibrate(); - printf("Benchmarking %llu syscalls...\n", samples); + printf("Benchmarking %llu samples...\n", samples); - /* Native call */ native = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; printf("getpid native: %llu ns\n", native); ret = prctl(PR_SET_NO_NEW_PRIVS, 1, 0, 0, 0); assert(ret == 0); - /* One filter resulting in a bitmap */ - ret = prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &bitmap_prog); - assert(ret == 0); - - bitmap1 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; - printf("getpid RET_ALLOW 1 filter (bitmap): %llu ns\n", bitmap1); - - /* Second filter resulting in a bitmap */ - ret = prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &bitmap_prog); - assert(ret == 0); - - bitmap2 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; - printf("getpid RET_ALLOW 2 filters (bitmap): %llu ns\n", bitmap2); - - /* Third filter, can no longer be converted to bitmap */ ret = prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &prog); assert(ret == 0); - filter1 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; - printf("getpid RET_ALLOW 3 filters (full): %llu ns\n", filter1); + filtered = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; + printf("getpid RET_ALLOW: %llu ns\n", filtered); - /* Fourth filter, can not be converted to bitmap because of filter 3 */ - ret = prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &bitmap_prog); - assert(ret == 0); + printf("Estimated seccomp overhead per syscall: %llu ns\n", + filtered - native); - filter2 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; - printf("getpid RET_ALLOW 4 filters (full): %llu ns\n", filter2); + if (filtered == native) + printf("Trying running again with more samples.\n"); - /* Estimations */ -#define ESTIMATE(fmt, var, what) do { \ - var = (what); \ - printf("Estimated " fmt ": %llu ns\n", var); \ - if (var > INT_MAX) \ - goto more_samples; \ - } while (0) - - ESTIMATE("total seccomp overhead for 1 bitmapped filter", calc, - bitmap1 - native); - ESTIMATE("total seccomp overhead for 2 bitmapped filters", calc, - bitmap2 - native); - ESTIMATE("total seccomp overhead for 3 full filters", calc, - filter1 - native); - ESTIMATE("total seccomp overhead for 4 full filters", calc, - filter2 - native); - ESTIMATE("seccomp entry overhead", entry, - bitmap1 - native - (bitmap2 - bitmap1)); - ESTIMATE("seccomp per-filter overhead (last 2 diff)", per_filter1, - filter2 - filter1); - ESTIMATE("seccomp per-filter overhead (filters / 4)", per_filter2, - (filter2 - native - entry) / 4); - - printf("Expectations:\n"); - ret |= compare("native", "≤", "1 bitmap", native, le, bitmap1); - bits = compare("native", "≤", "1 filter", native, le, filter1); - if (bits) - goto more_samples; - - ret |= compare("per-filter (last 2 diff)", "≈", "per-filter (filters / 4)", - per_filter1, approx, per_filter2); - - bits = compare("1 bitmapped", "≈", "2 bitmapped", - bitmap1 - native, approx, bitmap2 - native); - if (bits) { - printf("Skipping constant action bitmap expectations: they appear unsupported.\n"); - goto out; - } - - ret |= compare("entry", "≈", "1 bitmapped", entry, approx, bitmap1 - native); - ret |= compare("entry", "≈", "2 bitmapped", entry, approx, bitmap2 - native); - ret |= compare("native + entry + (per filter * 4)", "≈", "4 filters total", - entry + (per_filter1 * 4) + native, approx, filter2); - if (ret == 0) - goto out; - -more_samples: - printf("Saw unexpected benchmark result. Try running again with more samples?\n"); -out: return 0; } diff --git a/tools/testing/selftests/seccomp/seccomp_bpf.c b/tools/testing/selftests/seccomp/seccomp_bpf.c index 412e69e11620..a12eea3aff10 100644 --- a/tools/testing/selftests/seccomp/seccomp_bpf.c +++ b/tools/testing/selftests/seccomp/seccomp_bpf.c @@ -3504,6 +3504,7 @@ TEST(seccomp_get_notif_sizes) /* * TODO: + * - add microbenchmarks * - expand NNP testing * - better arch-specific TRACE and TRAP handlers. * - endianness checking when appropriate @@ -3511,6 +3512,7 @@ TEST(seccomp_get_notif_sizes) * - arch value testing (x86 modes especially) * - verify that FILTER_FLAG_LOG filters generate log messages * - verify that RET_LOG generates log messages + * - ... */ TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/seccomp/settings b/tools/testing/selftests/seccomp/settings deleted file mode 100644 index 6091b45d226b..000000000000 --- a/tools/testing/selftests/seccomp/settings +++ /dev/null @@ -1 +0,0 @@ -timeout=120